microwave monolithic power amplifier design

microwave monolithic power amplifier design
Microwave monolithic integrated circuits (MMICs) are
used extensively in virtually every commercial and military microwave system. Monolithic implementations of
most receiver and transmitter building blocks are commercially available, covering a multitude of applications
and frequency bands. These functions include but are not
limited to mixers, modulators, switches, digital/analog attenuators, digital/analog phase shifters, low-noise amplifiers (LNAs), driver amplifiers, and power amplifiers (PAs).
Many of these MMICs are based on gallium arsenide
(GaAs) or indium phosphide (InP) material systems (1–3).
However, increasingly, many new monolithic circuit functions are being realized with silicon-based technologies, examples of which are silicon germanium (SiGe), metal oxide
based devices Complementary Metal Oxide Semiconductor (CMOS), Laterally Diffused Metal Oxide Semiconductor (LDMOS), and blended technologies (SiGe-BiCMOS)
(3, 4). An emerging semiconductor technology for microwave high-power applications is gallium nitride (GaN),
which may be epitaxially deposited on silicon carbide
(SiC) or silicon substrates (5). These devices have the
unique combination of simultaneous high-voltage and
high-frequency operation, and they are well suited for the
next generation of high-performance power amplifiers.
Power amplifier MMICs are of particular importance
in modern microwave systems. It is not uncommon for
the PA MMIC to be the most expensive component in the
system. It is also not unusual for it to be the component
that dominates system reliability. For radar and electronic
warfare (EW) applications, these devices are often run at
near-saturated output power levels. For analog and digital communication systems, linear operation is required,
and the power amplifier may be run at a high bias current,
high supply voltage, and/or output power levels where the
efficiency is low. In either case, the PA MMICs are likely
the highest power dissipation and hottest components in
the microwave subsystem driving thermal management requirements for the entire system. Clearly, the performance
and reliability of the power amplifier MMICs will have a
significant influence on the operation of the overall system.
Monolithic power amplifiers have some significant advantages over designs constructed from discrete components. MMIC power amplifiers are usually much smaller
and lighter than discrete circuits. There will be less performance variation unit to unit for the “as-built” circuits or,
conversely, less postfabrication tuning and adjustment of
the amplifiers to achieve a set level of uniformity. Because
other circuit functions are available in monolithic format, an opportunity exists for higher levels of integration
and complexity for MMIC power amplifiers. Entire transmit/receive systems have been successfully integrated on
to a single die (6). Additional degrees of freedom are available to the circuit designer. For example, the transistor
cells used in the circuit can be designed for optimum electrical and thermal performance. One is not restricted to a
particular set of available transistor cell sizes, as is the
case with a discrete amplifier. For MMIC power amplifiers that incorporate multiple gain stages, the impedance
levels between the stages are arbitrary and can be optimized for bandwidth, gain, and efficiency. Discrete PA
circuits tend to be designed for a fixed real impedance, typically 50 , such that they can be cascaded. As the operating frequency increases, discrete circuit architectures become more difficult to realize. Above 10 GHz, the selection
of high-quality surface mount components used for quasilumped element matching becomes limited and distributed
circuit approaches are more common (7). Above 18 GHz,
monolithic implementations for the power amplifier start
to become the only feasible option.
Monolithic circuits do have some significant drawbacks.
A smaller power amplifier footprint means that more heat
must be removed from the backside of the MMIC, which
can impact the cost and complexity of the thermal management system. Thermal management issues at the nextlevel assembly typically get flowed back to the MMIC manufacturer as a higher backside temperature requirement
for which the device must maintain reliable operation. For
the power amplifier designer, reliable operation generally
means that transistor channel temperature must not exceed some maximum value (2). MMIC components can be
more costly than discrete circuits. The most direct way to
reduce MMIC cost is to make the die as small as possible. However, in the case of power amplifiers, die size compaction is in direct conflict with maintaining a low channel
temperature. Amplifiers constructed with discrete components are relatively easy to tune, element values can be
adjusted, metal traces can be cut or widened, etc. Some limited circuit tuning is possible for MMIC power amplifiers.
However, adjustments are limited and require specialized
equipment and highly skilled personnel. Generally speaking, one has to get it right the first time when designing
MMIC components.
The general subject of microwave power amplifier
design has been covered extensively in the published literature. Excellent references on power amplifier circuits,
architecture, applications, analysis, and modes of operation are readily available. It is of course not possible to list
them all, and the reader is referred to a few excellent, concise publications (2, 3, 8–11). This article focuses on considerations, approaches, and methods that are of greater
concern to monolithic power amplifier design. The concepts
discussed apply to MMICs using bipolar devices (Bipolar
Junction Transistor (BJT), Heterojunction Bipolar Transistor (HBT), etc.) or unipolar transistors (Metal Semiconductor Field Effect Transistor (MESFET), Pseudomorphic
High Electron Mobility Transistor (PHEMT), High Electron Mobility Transistor (HEMT), Field Effect Transistor
(FET), etc.). However, the material that follows will focus
on the latter. The first section reviews an example specification for a high-frequency, narrowband, saturated power
amplifier MMIC. The next sections cover transistor cell
analysis and selection for the case of a 0.15-␮m GaN on
SiC device. This is followed by the description and application of a methodology for synthesizing and realizing the
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2013 John Wiley & Sons, Inc.
Microwave Monolithic Power Amplifier Design
Table 1. Example MMIC Power Amplifier Specification
Small signal gain
Small signal gain flatness
Input return loss
Output power: P3dB
Power-added efficiency: P3dB
Power supply current: P3dB
Power supply voltage
Die size (width × length)
MMIC backside temp.
Info. only
2.5 × 3.5
MMIC matching networks in microstrip format. The article
is concluded with the discussion of some practical considerations, including the impact of off-chip components and
stability analysis.
The first step in the design of a MMIC power amplifier is
an analysis of the specifications that define the circuit. Depending on the intended application, a given MMIC PA
may be described by a long and varied list of specifications. Most power amplifiers, however, do have some key
performance parameters in common. An example specification for a microwave power amplifier intended for a highefficiency saturated operation is shown in Table 1, along
with a detailed description of each parameter and how the
requirement can impact circuit design. Note that the parameters listed in Table 1 are generally with respect to
some system reference impedance, commonly 50 .
1. Frequency: Defines the frequency band over which
the remainder of the specifications applies. The operating frequency of the amplifier will be a factor in
determining the transistor process (gate length and
material system) that is used for the design as well
as for the transistor unit cell size (cell periphery and
gate finger length).
2. Small Signal Gain: Defines the minimum and maximum linear gain (Gss ) for the amplifier. This is equivalent to the s-parameter S21 . The specified amount of
small signal gain will determine how many stages of
amplification will be required.
V out Gss (dB) = S21 (dB) = 20log Vin
3. Small Signal Gain Flatness: The amount in decibels that the small gain of a particular amplifier is
allowed to vary over the operational frequency range.
4. Input Return Loss: Specifies how close the input
impedance of the amplifier has be to some reference
impedance. For most microwave systems, the reference impedance is 50 . This parameter is equivalent
to the s-parameter S11 and is defined in equation 2
for a 50- reference impedance.
RL(dB) = − S11 (dB) = −20log
Zin − 50 Zin + 50 (2)
5. Output Power—P3dB: Defines the minimum output power (Pout ) for the amplifier at an input power
level (Pin ) that compresses the gain 3 dB from the
small signal level. The minimum amplifier output
power level determines the total periphery of the output transistor cells. The output power value in Table
1 is given in a commonly used decibel scale referenced
to 1 mW. The conversion between Watts and dBm is
shown in Equation 3.
P(dBm) = 10 log
1 mW
6. Power-Added Efficiency (PAE)—P3dB: Defines
the minimum PAE for the amplifier at an input
power level that compresses the gain 3 dB from the
small signal level. Power-added efficiency is often
given in percent and is defined below. Note that the
DC power (PDC ) is the total consumed power for the
input power associated with the specified output
power, not the small signal or quiescent DC power.
%PAE = 100
Pout (W) − Pin (W)
Pout (W) − Pin (W)
= 100
7. Power Supply Current—P3dB: The power supply
current (IDC ) drawn by the amplifier at an input
power level that compresses the gain 3 dB from the
small signal level. This is listed as “information only”
for this example meaning that the customer will
want to know what the current is but is not placing
pass/fail limits on the value. This is not uncommon
when a maximum output power is not specified.
For example, what if the fabricated design produces
38 dBm of output power and is greater than 40% efficient? It would still be specification compliant but
will draw considerable more supply current than a
37-dBm amplifier at the same PAE. An estimation
of this current level is useful for sizing the system
power supply as well as various components on the
MMIC such as metal traces, thin-film resistors, and
the number of bondwires required to connect the
power supply.
8. Power Supply Voltage: Defines the minimum and
maximum available power supply voltages (VDC ) for
the amplifier. This parameter influences process selection, as a given transistor technology will have
a maximum operating voltage. The supply voltage
level can also impact the circuit architecture and thin
film capacitor design.
9. Die Size: Defines the maximum die size for the
fabricated MMIC. The die size of course has a direct impact on the cost of the MMIC. However, it is
also specified due to limited available space at the
next-level assembly or the MMIC is replacing an existing part and has to be precisely the same size. In
most cases, it is desirable to make the die as small as
possible while maintaining an acceptable maximum
channel temperature.
10. MMIC Backside Temperature: This
often reflects the user’s ability to manage the
Microwave Monolithic Power Amplifier Design
thermal interface between the MMIC and the
next-level assembly at some assumed level of power
dissipation. This is the MMIC backside temperature
that one would use for thermal analysis to determine
transistor channel temperature.
The next task is the design and selection of an appropriate
transistor cell for the output stage of the circuit. Several
terms have been introduced, and it may be helpful at this
point to review an example that illustrates how these parameters interact with each other. Given the 20-V power
supply voltage and relatively high-frequency operation, a
0.15-␮m gate length GaN on SiC HEMT process will be
considered for this design. The foundry that will be building this MMIC has data and models available for the FET
cell shown in Fig. 1. This transistor cell is constructed of
eight gate fingers, each being 75 ␮m long for a total device
size of 600 ␮m. The separation of the gate fingers, the gateto-gate pitch, is 15 ␮m. A smaller pitch will result in better electrical performance; however, the transistor junction
temperature will also be higher. Note that the transistor
is configured as common source with the source connected
to the MMIC backside ground plane on two sides with substrate vias.
A good way to assess transistor cell performance for a
specific application is to subject the device to load/source
pull testing. Load/source pull characterization is a measurement technique where tuners at the input and output
of the device are adjusted to optimize some performance
parameter of interest (1, 3, 8, 10, 12). Ideally, one would
analyze measured load pull data on a candidate transistor
cell. However, in the absence of measured data, the load
pull test can be emulated with a circuit simulator, given
an accurate nonlinear model for the transistor cell is available. Transistor cell load pull data under different tuning
conditions over a range of frequencies is often available
from the foundry. Efficiency-tuned load pull data measured
at 23 GHz for the device shown in Fig. 1 is plotted in Fig. 2.
The tuners were adjusted for maximum power-added efficiency at 2–3 dB of gain compression. The transistor is
biased at a quiescent bias condition of Vds = 20 V and
Figure 1. An 8 × 75 ␮m FET cell layout.
Figure 2. 23-GHz PAE tuned load pull for an 8 × 75-␮m GaN
0.15-␮m FET.
Ids = 60 mA. The maximum observed value of PAE is 52%,
and it occurs at an input power of about 23 dBm. The output power was measured to be 32.3 dBm or 1.7 W, and the
gain is compressed about 2.5 dB from the 11.8 dB observed
at 8 dBm of input power (approximately small signal). Using Equation 4, the power supply current IDC at 23 dBm of
input power is 144 mA, which is more than double the quiescent current. The load and source reflection coefficients
(50- system) for optimum efficiency tuning at 23 GHz
were measured to be S = 0.76 /173◦ and L = 0.76/122◦ .
This transistor cell performs well at the center frequency
of the amplifier specified in Table 1 and is a good candidate for this design. The load pull data indicate that the
electrical performance of this transistor cell is acceptable.
However, will the transistor junction temperature result
in a reliable operation given the maximum MMIC backside temperature listed in Table 1? The power dissipated
by the device is calculated with the following:
PD (W) = PDC (W) + Pin (W) − Pout (W) = PDC (1 − % PAE/100)
For the data shown in Fig. 2 under optimal PAE tuning conditions, this works out to be 1.38 W or 2.3 W/mm of device
periphery. A somewhat higher power dissipation should be
considered in the thermal analysis to provide margin. A
thermal simulation of the transistor shown in Fig. 1 for a
3.4-W/mm power dissipation and 95◦ C backside temperature is shown in Fig. 3. The maximum projected junction
temperature under this condition is around 160◦ C. Data
for maximum allowable transistor junction temperature
versus device lifetime should be available from the manufacturer.
Ideally, if one were to combine four of these transistors, it should be possible to achieve an output power of
4 × 1.7 W = 6.8 W, or 38.3 dBm. Of course, a matching network will need to be designed to transform the 50- load
impedance connected to the amplifier output such that
the efficiency-tuned impedance determined from the load
pull data is presented to each transistor cell. This circuit
will also have to function as a power combiner, summing
the power from the four transistors to a single output for
the amplifier. Real output matching networks are not lossless, and the loss tends to increase as the number of FET
Microwave Monolithic Power Amplifier Design
Figure 3. Thermal simulation for an 8 × 75-␮m GaN 0.15-␮m FET cell with 3.4 W/mm dissipation.
cells being combined increases. Surprisingly, for narrowband (10–20% bandwidth) amplifiers, the output matching
network loss is not a strong function of operating frequency.
These circuits use distributed transmission lines to realize series inductance. The loss of these lines does increase
with frequency. However, less inductance is required at
high frequency. In other words, the loss per unit length
increases but the overall length tends to decrease, and the
two effects more or less cancel. The approximate values for
output matching network loss for narrowband circuits on
semi-insulating substrates (GaAs, GaN on SiC, InP) loss
are listed in Table 2 for increasing levels of binary transistor cell combining. Also shown in Table 2 is the impact that
output network loss has on efficiency. For an output matching network with 0.8 dB of loss, the maximum achievable
efficiency is reduced to 83%. In other words, if the transistors are 100% efficient and have infinite gain, then the
PAE for the amplifier would be 83%.
Therefore, including the estimated output network loss,
a MMIC combining four 8 × 75-␮m transistor cells could
produce up to 38.3 dBm − 0.4 dB = 37.9 dBm = 6.2 W.
However, an actual device will probably deliver less power
for several reasons. The maximum backside temperature
listed in Table 1 is probably higher than the backside temperature for the die subjected to load pull testing. The
output matching network will not perfectly match the transistors over the entire operating frequency band of the amplifier, nor will it present exactly the same load impedance
to all four cells. There will also be some process variation
Table 2. Approximate Output Matching Network Loss and Impact on Efficiency
Number of Cells
Loss (dB)
from device to device within a given lot and manufacturing
variation lot to lot. The transistor cells present on the fabricated MMIC will not be exactly the same as those tested
at load pull. In other words, additional margin should be
included when selecting a transistor cell size. Assuming a
four-way combined output network, it would be prudent to
use an 8 × 75-␮m FET cell to meet the output power requirement specified in Table 1. The linear gain shown in
Figure 2 is about 11 dB, which is short of the minimum
16 dB of small signal gain called for in Table 1. This amplifier will need at least two stages of gain using this 0.15-␮m
GaN process technology.
The transistor output tuning condition determined from
load pull testing is useful for designing the output matching network. The function of the output matching network
will be to transform the 50- output load impedance to
present the efficiency-tuned load to each of the four transistor cells. Recall that at 23 GHz, load pull testing determined that the optimum load reflection coefficient in a 50-
system was L = 0.76 /122◦ . This is easily converted into a
load impedance, as follows:
L =
ZL − 50
1 + L
⇒ ZL = 50
= 8.86 + j27.05 (6)
ZL + 50
1 − L
That implies that the output impedance of the transistor
can be modeled as the conjugate of Equation 6 such that
maximum power transfer occurs when conjugate matched.
The conjugate of Equation 6 is in the form of a series RC
network; however, an analysis of load pull data suggests
that the frequency dependence of this transistor output
model actually behaves more like a parallel RC circuit.
Converting the conjugated impedance given in Equation 6
into a parallel RC network:
YL∗ =
+ jωCp
= 10.94 + j33.39 mS =
8.86 − j27.05
Microwave Monolithic Power Amplifier Design
Figure 4. Output matching network problem.
where ω is the angular frequency in rad/s. Therefore, the
output model will be a parallel RC with the following values:
Rp =
= 91.4
Cp =
= 0.23 pF
2 ␲ ×23 GHz
Load pull data is often provided in manufacturer
datasheets in Rp and Cp format. The output matching problem for four-way combining is shown on the left side of
Fig. 4. Ideally, all four transistors are driven in phase and
have identical output voltages. In other words, the matching network is operating in the even mode. Under evenmode excitation, the input nodes of the matching network
can be arbitrarily connected together with a lumped element component. Because the voltage is identical at all
four nodes, no current will flow in the connected element,
and it will have no influence on even-mode circuit operation. Even-mode only excitation is an important assumption, as it allows for reductions in the circuit that can simplify network synthesis greatly. Under the even-mode assumption, the four outputs can be connected together and
the matching problem recast as shown on the right side of
Fig. 4. A prototype matching network is given in Fig. 5. The
goal is to achieve a real impedance, over the operating frequency of the amplifier, of Rp /4, which equals 22.9 . The
first 0.92-pF shunt capacitor represents the output capacitance of the four transistor cells, 4Cp . Some of the circuit elements shown in Fig. 5 reflect the need to bias and connect
the circuit to the outside world. The first shunt inductor is
Figure 5. Prototype lumped element output matching network.
intended to supply the drain bias voltage to the transistors
and is high-frequency grounded by a 30-pF bypass capacitor. For relatively narrow bandwidth designs, this inductor
can be used to tune out some of the transistor output capacitance, 4Cp . To prevent power supply current from flowing
through the 50- load, a 6-pF series DC blocking capacitor
is placed near the output of the network. The final 0.25nH inductor in series with the 50- load models one or
more bondwires connected to the output of the amplifier.
It is best to include the bias circuitry and MMIC interface elements early in the design process such that they
can be seamlessly integrated into the matching network.
The 50.7-pH shunt inductor is sized to resonate with 4Cp
in the frequency range of interest approximately reducing the problem to matching 22.9 to 50 . A standard
low-pass matching topology consisting of series inductors
and shunt capacitors is used to accomplish this. The simulated frequency of the prototype output matching network
is plotted in Fig. 6. The real part of the input impedance
is predicted to be 22.9 ± 1 over the 22–24 GHz operating
frequency band. The reactive component is simulated to be
0 ± 2.2 .
Under the assumption of even-mode excitation, the prototype matching circuit can be transformed into a four-way
combiner. An intermediate step is shown in Fig. 7, where
the left side of the circuit has been separated into two parallel connected channels. This circuit is equivalent to the
original prototype. If the two inputs are driven in-phase
with equal amplitude signals (even-mode), there will be no
Microwave Monolithic Power Amplifier Design
Figure 6. Frequency response of prototype network.
Figure 7. Equivalent even-mode two-way combiner circuit.
Figure 8. Final even-mode four-way lumped element combiner circuit.
current flowing in the connecting trace, and this connection
may be removed separating the two inputs. This procedure
can be continued, yielding the final lumped element fourway output matching network shown in Fig. 8.
Now the lumped element circuit shown in Fig. 8 will
have to be converted into a microstrip circuit that can be
fabricated with MMIC process technology. Some practical
matters need to be addressed at this point. Process design
rules will place some restrictions on realizing a microstrip
implementation of the matching network. An analysis of
the load pull data collected on the 8 × 75-␮m transistor
cell revealed that under saturated conditions, the device
draws about 144 mA of current. There are four of these
FETs in the output stage of this amplifier for an approximate total current draw with a margin of 600 mA. Semiconductor manufacturers provide design rules for their
processes, and this document will define safe maximum
Microwave Monolithic Power Amplifier Design
Figure 9. Approximate equivalent circuits for sections of transmission line.
ratings for the various process elements. For example, assume that the maximum current that a conductor can
handle is 15 mA/␮m of line width. The trace used to realize the 0.2-nH bias inductor will need to be at least
600 mA/15 mA/␮m = 40 ␮m wide if the amplifier is biased
from one side of the circuit only. Now if the amplifier can
be biased from both sides of the circuit, then the bias line
will have to be at least 20 ␮m wide. The designer must ensure that all current-carrying elements are sized to handle
the expected current densities. The transistor cell shown
in Fig. 1 has physical dimensions and one or more process
design rules governing how close together these FETs can
placed. For example, there will be a design rule restricting
the minimum separation between substrate vias, for now
assume 100 ␮m. This rule will force the center-to-center
transistor drain bus separation between adjacent cells to
be at least 420 ␮m. In other words, the transmission line
realizations for some of the inductors that connect the transistor cells together cannot be arbitrarily short.
Approximate lumped element equivalent circuits for
sections of transmission line take the form of the “Tee”
and “Pi” networks shown in Fig. 9. Therefore, the inductors shown in Fig. 8 can be replaced by sections of microstrip transmission line where some amount of shunt
capacitance will be absorbed into the line. The remaining
shunt capacitance can be realized as metal-insulator-metal
(MIM) capacitors or open-circuited transmission line stubs
(13). Typically, the dielectric material for MIM capacitors
is silicon nitride. Many MMIC manufacturers will provide
a capacitance density for their MIM capacitance, as well
a maximum operating voltage. Typical MIM capacitance
densities range from 200 pF/mm2 to 1200 pF/mm2 . Bear in
mind that the higher the capacitance density, the lower
the operating voltage. A recommended procedure is to replace circuit elements in Fig. 8 one at a time with elements
from the foundry process design kit (PDK). After each element is replaced, then re-optimize the circuit to replicate
Figure 6 as closely as possible. For example, replace all of
the 0.2nH inductors with transmission line sections that
are 40 ␮m wide and optimize the line length. Next, replace the 7.5-pF and 15-pF shunt capacitors with foundry
kit models. These capacitors will have a nonzero electrical
length. The via connected to the bottom plate will have inductance and the capacitor itself will have a physical distance that the RF current must traverse before reaching
the via contact. The trace that replaced the 0.2-nH inductors will therefore need to be shortened slightly to recover
the original frequency response once foundry models for
the shunt bypass capacitors have been added. Repeat this
procedure with each element in the circuit until all inductors have been replaced with sections of microstrip trans-
Figure 10. Microstrip realization of the output matching network.
mission line and all capacitors have been replaced with the
PDK models. A possible MMIC compatible realization of
the output matching network is shown in Fig. 10. Transmission line sections are realized as a microstrip line (9,
13). The SiC substrate is 100 ␮m thick and has a dielectric constant of εr = 9.7. The metallization is gold and is
assumed to 6 ␮m thick. The values of the shunt capacitors are listed on the drawing, and they are constructed
on top of substrate vias to provide a ground connection
for the bottom plate to the back of the MMIC. Note that
curved “trombone” sections of line are used to reduce the
overall length of the network. The patch of microstrip at
the far right side is the output bondpad required for bondwire attachment to the next component in the system. At
this point, the width dimension of the MMIC can be estimated as the width of the circuit shown in Fig. 10, plus any
“keep out” region between the actual edge of the MMIC and
the metallization. Design rules for the “keep out” region
will be available from the foundry that is building the device. A representative number for GaN on SiC is 125 ␮m.
Based on the output matching network layout shown in
Fig. 10, the width of the MMIC is estimated to be 2.0 mm,
which is well within the 2.5 mm maximum dimension listed
in Table 1.
The simulated frequency response for the input
impedance of this circuit is near identical to that of the
prototype network shown in Fig. 6. The predicted dissipative loss for the output matching network is plotted in
Fig. 11. Dissipative loss is calculated from the network sparameters with Equation 8. Less than 0.3 dB of loss is projected for the output matching network at 22 GHz putting
the estimated amplifier output at 38 dBm or 6.3 W. Note
that the simulated output matching network loss is in line
with the approximate value of 0.4 dB listed in Table 2 for
Microwave Monolithic Power Amplifier Design
Figure 11. Predicted loss for the output matching network.
four-way combining.
Loss(dB) = −10 log
|S21 |2
1 − |S11 |2
The linear gain specification listed in Table 1 is 15 dB minimum, and the linear gain shown in the load pull data is
around 11 dB. To meet the linear gain requirement, an additional gain stage will be required. The network between
amplifier stages is referred to as an interstage matching
network and has many functions. This network provides
gate bias voltage to the second (output) stage and drain
bias voltage to the first (input) stage. The interstage circuit is sometimes used to compensate for negative gain
slope versus frequency that will occur for the output stage.
These transistors are more than capable of causing oscillations. Amplifier stabilization circuits, the intentional introduction of loss, are included as needed in the interstage
network. This is particularly true for even-mode excitation,
and these stability circuits often cause the interstage network loss to be somewhat higher than that of the output
matching network. According to the load pull data, each
output transistor cell must be driven with at least 23 dBm
of power to reach 3 dB of gain compression. In other words,
given the input stage transistor cell size, the interstage network must present a good enough load to the output of the
first stage devices such that they produce sufficient power
to drive the output stage. To make matters worse, neither
the source nor the load impedance is purely real, as the
network is loaded by the highly reactive input impedance
of the output stage transistors. Nevertheless, interstage
networks can be designed to cover these requirements acceptably.
Step 1 is to estimate how large the first stage transistor cells need to be to overcome the loss of the interstage
matching network and drive the output stage to peak efficiency with sufficient margin for temperature and part-topart variation. So why not just make the first-stage FETs
as big as the output stage devices? The first stage transistors do not contribute to the overall output power of the
amplifier; however, they do consume DC power. If these devices are made too large, then the power-added efficiency
of the amplifier will be impacted in a negative way. If the
first-stage FETs are made too small, then there will not be
sufficient power to drive the output stage to 3 dB of compression, and both output power and PAE will be adversely
affected. The latter situation is far worse, and it is recommended that one err on the side of oversizing the first stage
transistors and accepting a few percentage points of lower
efficiency. This procedure can be somewhat iterative because it is based on an initial estimate of the interstage
network loss. Examining the load pull data shown in Fig.
2, it took about 23 dBm of input power to drive the transistor to peak PAE. Because there are four transistors in
the output stage of this design, the first stage will have to
deliver 29 dBm of power measured at the input of the output stage devices. Now assume a worst case of 2 dB of loss
for the interstage network, such that the first-stage transistors will have to deliver a total 31 dBm of output power.
The load pull data shown in Fig. 2 were probably measured
at room temperature; however, this amplifier will need to
operate with a +95◦ C MMIC backside temperature. A good
rule of thumb for power amplifiers is a gain temperature
coefficient of –0.015 dB/◦ C/stage. Assuming a +25◦ C MMIC
backside temperature for the load pull measurement, the
output stage gain for a +95◦ C base could drop by as much
as 0.015 × (95◦ C – 25◦ C) = 1.05 dB. The mechanical tuners
used for the load pull test also have a physical limitation on
how high the magnitude reflection coefficient can be that
is presented to the device. The source tuner at the transistor input probably cannot tune these devices for maximum
gain at 23 GHz. In other words, the gain capability of the
transistor under investigation may be higher than what
is measured at load pull. Taking this under consideration,
the output power required from the first-stage transistors
is approximately 31–32 dBm. However, most of the allowed
3 dB of gain compression for the entire amplifier will occur
in the output stage to reach peak efficiency. According to
the load pull data, the transistor is 2 dB compressed when
driven to peak PAE, meaning that only 1 dB of gain compression is allowed in the first stage. The output power for
these devices at 1 dB of gain compression is about 29 dBm.
Two 8 × 75-␮m FETs will be able to deliver 32 dBm at 1 dB
of gain compression when tuned for efficiency. This is a good
initial guess for the first-stage transistor periphery, as it
accounts for gain compression and provides some margin
to the estimated 31–32-dBm requirement.
At this point, one should do a sanity check on the DC
power budget. The projected output power is 38 dBm and
the current draw from the output devices will be about
4 × 144 mA = 576 mA. The amplifier gain at 3 dB of gain
compression must exceed 13 dB, so the maximum input
power will be 38 dBm – 13 dB = 25 dBm or 316 mW. Solving Equation 4 for DC current given a 35% minimum PAE
and a 20 V DC supply projects a total current budget of
856 mA or 289 mA for the first stage. The load pull data at
1 dB of gain compression shows a current draw of 96 mA
per 8 × 75-␮m FET cell or 192 mA for two such devices.
Therefore, a first stage constructed with two 8 × 75-␮m
transistor cells supports the drive requirement over temperature as well as the current budget, so long as the 2 dB
assumption for the interstage loss is fairly accurate. The
matching problem for the interstage network is shown in
Microwave Monolithic Power Amplifier Design
Figure 12. Interstage matching network problem.
Fig. 12 along with the conversion to an even-mode two-port
Clearly, one will need a model for the transistor cells
to design the interstage network. Ideally, this would be
a nonlinear model supplied by the foundry manufacturing the MMIC. Suitable nonlinear models should be available in the process design kit for the technology of choice.
Nonlinear models can have convergence issues and will
result in having a longer simulation time than a linear
equivalent. During the initial design phase, it is sometimes
advantageous to use linear models and load pull data to
represent the transistor cells. This allows the designer to
investigate quickly different circuit topologies and synthesize matching networks that are reasonably close to optimum. Of course, the final design optimization should be
performed under large signal conditions with a nonlinear
model. A commonly used linear equivalent circuit model
for the device shown in Fig. 1 is illustrated in Fig. 13. This
model includes the gate and drain feed networks as well as
the inductance of the two substrate vias connected to the
source. Note that the controlling voltage for the voltagecontrolled current source (VCCS) is across Cgs and Ri . The
complex exponential governing the phase of the current
source is handled within the circuit simulator and the user
need only enter the parameter τ. There are many excellent
references on linear circuit modeling of microwave FETs
for the interested reader (1–3, 14–19).
Figure 13. Linear circuit model for an 8 × 75-␮m GaN transistor.
A prototype even-mode interstage matching network is
shown in Fig. 14. Note that a DC block, drain/gate bias
inductors, and bypass capacitors are integrated into the
circuit topology. Some resistors are included, which can be
useful for stabilizing the amplifier and compensating for
gain slope versus frequency. Using even-mode transformations, as was done for the output network, this circuit can
be configured as a two-way to four-way divider network
as shown on the left side of Fig. 12. The simulated input
impedance for the interstage network is plotted in Fig. 15.
Note that the bandwidth of the interstage is not as wide as
the output matching network (Fig. 6). The output matching network had a reactive source impedance but a purely
real 50- load. The interstage network has reactive source
and load impedances, which will reduce the bandwidth for
a matching circuit of similar complexity.
Following the same procedure used for designing the
output matching network, a microstrip implementation of
the interstage network was generated and optimized. The
resulting circuit layout added to the output network is
shown in Fig. 16. The frequency response of the microstrip
version of the interstage is predicted to be essentially identical to that of the lumped element prototype plotted in Fig.
15. The predicted loss of the microstrip interstage matching network as a function of frequency is given in Fig. 17.
Note that the network loss is projected to be 2 dB or less
over the operating band of the amplifier and decreases
Microwave Monolithic Power Amplifier Design
Figure 14. Prototype even-mode interstage matching network.
Figure 15. Frequency response of prototype interstage network.
as the frequency increases. This positive slope versus frequency will compensate for some of the negative gain slope
characteristic of the transistors. The simulated small signal frequency response of the circuit configured as shown
on the left side of Fig. 12 is plotted in Fig. 18. The simulated linear gain over the 22–24 GHz design frequency
band is about 11 dB and relatively flat. Accounting for the
simulated loss of the matching networks, this transistor is
producing about 13 dB of linear gain. This is about 1.3 dB
Figure 17. Predicted loss for the interstage matching network.
more gain than was measured at load pull, suggesting that
the input tuner may not have sufficient range to match the
input of this device.
The input matching network problem is shown in Fig. 19.
This network supplies gate bias voltage to the first stage
transistors and performs the necessary division of the
Figure 16. Microstrip realization of the interstage and output matching networks.
Microwave Monolithic Power Amplifier Design
Figure 18. Simulated small signal frequency response of the circuit shown in Fig. 12.
input signal. Like the interstage, the input network is often used to compensate for gain slope versus frequency and
to provide amplifier stabilization through the intentional
introduction of loss. Most microwave systems operate into
a 50- impedance reference and the input matching network should be designed such that the input impedance
Figure 19. Input matching network problem.
Figure 20. Prototype even-mode input matching network.
of the amplifier is approximately equal to 50 . A prototype even-mode network for a candidate input matching
network is shown in Fig. 20. Following the procedure used
for the other networks, a microstrip realization of the circuit was developed. The two-stage MMIC with input, interstage, and output matching networks is illustrated in
Fig. 21. Note that the chip edge is now included and labels
have been added to identify the MMIC bondpads. Labeling
can usually be done with a Silicon Nitride layer such that
the proximity of the labels to the actual circuitry will have
a negligible impact on amplifier performance. The overall
length of the MMIC is estimated to be 3.2 mm. The simulated small signal frequency response for the amplifier is
plotted in Figure 22. Linear gain, gain flatness, input return loss and die size are all meeting the requirements
set forth in Table 1. Now a large signal simulation of
the power amplifier MMIC should be performed. Using
the manufacturer-supplied nonlinear transistor model, the
projected output power and efficiency at 3 dB of gain compression is plotted in Fig. 23. The quiescent bias condition
is Vd = 20 V and Id = 360 mA, requiring a gate voltage
of –2.38 V. The output power is predicted to be greater
than 38 dBm (6.3 W), which provides some degree of margin over the 37-dBm (5-W) specification for manufacturing
Microwave Monolithic Power Amplifier Design
Figure 21. MMIC layout with input, interstage, and output matching networks.
of gain compression varies between 767 mA and 843 mA,
depending on frequency.
The simulations shown thus far are based on microstrip
circuit element models resident within the simulation environment. Whereas these models generally have good accuracy, whenever possible the network models should be
verified with electromagnetic simulation. This will account
for mode generation and electromagnetic coupling between
sections of the circuit that will not be predicted by the
microstrip element models. Small adjustments may be required after the electromagnet simulations reoptimize the
predicted amplifier performance.
Figure 22. Simulated small signal frequency response for the PA
and temperature variation. The power-added efficiency is
simulated to be in excess of 40% over the operating band of
the amplifier, again providing margin to the 35% requirement. The total DC current draw when operated at 3 dB
Figure 23. Large signal simulated results for the complete
MMIC design.
Generally speaking, it is not good to have significant levels of gain outside the specified operating frequency range
of the amplifier. Out-of-band terminating impedances are
typically not well controlled, increasing the likelihood of oscillation and other issues such as noise power generation,
jamming sensitivity, unintended frequency conversion, etc.
A wideband simulation of the amplifier is plotted in Fig. 24,
and there is significant gain at low frequency. The reason
for this is the bypass capacitors on the MMIC are not a
high enough value to provide an AC ground (bypass) at low
frequency. Apparently, this amplifier will require some “off
chip” capacitors and the impact of these components should
be included in the circuit simulation. Simulated amplifier
frequency responses for two different bypass circuits are
shown in Figs. 25 and 26. The inductor models a bondwire
connecting the MMIC to the off-chip components. The circuit inset in Fig. 25 achieves a low-frequency bypass with a
0.01-␮F capacitor to ground. Examining the plot, the gain
has indeed been reduced at a very low frequency. However, things are actually worse around 2 GHz where the
circuit has positive gain and several sharp resonant peaks
Microwave Monolithic Power Amplifier Design
low-frequency gain has been reduced to about –17 dB and
the sharp resonances are no longer present.
At this point, one should assess the stability of the amplifier. A commonly used measure of the stability of a two-port
network is the k-factor. The k-factor is calculated from the
two-port network s-parameters of the amplifier and is useful as a rough indicator of amplifier stability (9, 13).
Figure 24. Simulated wideband frequency response for the PA
Figure 25. Simulated wideband frequency response for a
0.01-␮F bypass capacitor.
are present. What has happened is that the 0.01-␮F capacitor is an AC ground effectively connecting the bondwire inductance to ground. This inductor may now parallel resonate with the on-chip bypass capacitors effectively
negating (open circuiting) them at the resonant frequency.
Now consider the bypass circuit and simulation shown in
Fig. 26. Placing a 13- resistor in series with the 0.01␮F off-chip capacitor greatly improves the situation as the
Figure 26. Simulated wideband frequency response with the addition of a 13- resistor.
1 − |S11 |2 − |S22 |2 − |S11 S22 − S12 S21 |2
2 |S12 S21 |
If k > 1, then the two-port network will not oscillate for
any passive source and load terminating impedance in the
absence of external feedback. Of course, there is a lot of
feedback occurring within the amplifier, as well as modes
of oscillation that do not depend on source/load impedance.
In other words, k > 1 does not necessarily guarantee that
a multistage amplifier is unconditionally stable; however,
k < 1 does guarantee that it is not unconditionally stable.
So keeping an eye on the k-factor during the design phase
is good practice until a more rigorous stability analysis can
be performed on the completed circuit.
Although k-factor analysis may be useful for spotting
serious stability issues, it is not useful for rigorously determining the stability of a multistage amplifier with multiple FET cell combining (20). Several rigorous stability
analysis techniques are described in the literature (21, 22).
One method familiar to analog circuit designers is the loop
gain analysis (4). To apply loop gain stability analysis to a
MMIC power amplifier, one must first alter the linear FET
model to gain access to the circuit loop in a manner that
does not load the circuit. A linear FET model suitable for
loop gain analysis is shown in Fig. 27. Some foundry design kits do not allow the user to edit the transistor circuit
models. In this case, it is recommended that the foundry
transistor model s-parameters be fit to the circuit model
shown in Fig. 13.
Note that two VCCS have been added to the transistor
model. These additional components serve two purposes.
First, they act as high-impedance buffers such that whatever is connected to the ports labeled Vin and Vout will not
load the circuit under investigation. Second, they shift the
ground reference. Simply connecting high-impedance ports
to the top of the current source and Cgs would place V1 and
V2 across these points and the circuit ground, not across
the current source and Cgs and Ri as shown in Fig. 27. Note
that the controlling voltage for the VCCS, which was initially across the series combination of Ri and Cgs , is moved
to an external voltage controlled voltage source (VCVS)
with unity gain. The controlling voltage of a second unity
gain VCVS is connected across the series combination of
Ri and Cgs . This VCVS is functioning as a high-impedance
voltmeter to measure the voltage that appears across Ri
and Cgs , which was the original location of the controlling
voltage for the current source in the FET model shown in
Fig. 13. Note that if the Vin and Vout nodes are connected
together, then the circuit shown in Fig. 27 is equivalent
to the linear circuit model in Fig. 13. Therefore, all the
Microwave Monolithic Power Amplifier Design
Figure 27. Linear FET model suitable for loop gain analysis.
linear transistor models in the circuit simulation can be
replaced with the circuit shown in Fig. 27 with the Vin and
Vout ports connected together. The circuit works as follows:
inject a 1-V signal into the Vin port, which is connected to
the controlling port of the VCCS. This activates the transistor model current source and the resulting current flows
throughout the amplifier network causing a voltage to appear at the Vout port, the controlling port for the VCCS in
the original transistor model shown in Fig. 13. If this return signal has a magnitude greater than or equal to 1 V
and is in-phase, it is self sustaining and will grow into an
oscillation. The complex ratio of Vout to Vin is called the
loop gain (LG) of the circuit, which may be plotted in polar
LG =
To perform stability analysis disconnect, the Vin and
Vout ports of one of the transistors in the circuit, leaving
these ports connected for all of the other transistors. Calculate the complex loop gain and plot in polar format. If
this curve encircles the polar point 1 and at angle of 0◦ ,
then the amplifier is oscillating. Amplifier stability can be
a strong function of the terminating impedances connected
to the input and output ports of the amplifier. Ideally, both
of these impedances would be a constant 50 for all frequencies; however, in reality this condition is not practical.
Outside of the operating frequency range of the system that
the amplifier is embedded in, the terminating impedances
can deviate significantly from 50 . In practice, one should
try to demonstrate stability for arbitrary passive terminating impedances–in other words, input and output reflection coefficients of unity magnitude with an arbitrary
angle between 0◦ and 360◦ . One also has to be concerned
about transistor variation, from unit to unit and over temperature. A good rule of thumb is to attempt to demonstrate amplifier stability with the following modifications
to the transistor model. Increase gm by 30%, decrease Cgs
by 30%, and increase Cgd by 30%. This will generally produce a worst-case scenario for amplifier stability covering
device-to-device variation and variation over temperature.
Figure 28. Loop gain plot for Q3 under worst-case conditions.
A loop gain plot for transistor Q3 is shown in Fig. 28. For
this analysis, all circuit transistors have been modified to
produce a worst-case stability scenario. The analysis is carried out over a wide enough frequency range such that loop
gain trace approaches the center of the chart for the upper
and lower frequency sweep limits. The trace starts at the
center of chart for the lower frequency limit of 0.5 GHz and
is approaching the center for the high-frequency limit of
70 GHz. The trace does not encircle the unity gain point
denoted by the red X, and the amplifier is therefore stable with respect to Q3 . The worst-case phase margin is 60◦
occurring at 20.8 GHz. Similar plots will need to be generated for all of the transistors in the circuit above the line
of half symmetry (Fig. 29).
The assumption of even-mode operation has been used
several times in the development of this amplifier circuit. However, it is possible for this circuit to operate
in the odd mode as well. There will be an unavoidable
odd-mode component due to microstrip discontinuities,
Microwave Monolithic Power Amplifier Design
Figure 29. MMIC half and quarter symmetry lines.
unintended coupling, and process variation across the
MMIC for the transistors, capacitors, line widths, etc.
Therefore, amplifier stability for odd-mode operation must
also be considered. Under the even-mode assumption, adjacent transistors operate in phase, meaning that zero current would flow in a connection between them. In other
words, virtual open circuits are located at the MMIC lines
of symmetry as indentified in Fig. 29. For the case of oddmode operation, adjacent transistors operate 180◦ out of
phase and a virtual short circuit will exist along the lines
of symmetry. Because this amplifier combines four transistors in the output stage, there are two different odd-mode
Figure 30. Half and quarter symmetry odd-mode circuits.
circuits to consider. The half symmetry circuit is formed
by placing a virtual short along the MMIC horizontal center line as shown in Fig. 29. Any circuit elements touching
the half symmetry line are to be shorted to ground in the
circuit simulation. This amplifier also has quarter symmetry; again, parts of the circuit touching this line are to
be shorted to ground in the simulation. Half and quarter
odd-mode circuits for this MMIC are illustrated in Fig. 30.
Odd-mode stability analysis is carried out as previously
described, disconnecting the loop gain ports one at a time
for the transistors in the odd-mode circuit and generating
loop plots. Note that odd-mode stability is not a function
Microwave Monolithic Power Amplifier Design
no power and have no impact on amplifier performance. In
practice, these resistors are realized as thin-film resistors
with finite dimensions so they will add a small parasitic
capacitance that can be easily absorbed into the matching
networks. For odd-mode operation, the situation is very different. These resistors are divided by the lines of symmetry
into two series-connected resistors. Each of them is half the
value of the original, with the node between the resistors
grounded by the symmetry line. This grounded shunt resistor has a significant impact on odd-mode stability. Loop
gain plots for the odd-mode circuits are shown in Fig. 33
with 20- odd-mode stability resistors placed between the
transistor cells. This analysis was performed for the same
conditions as that shown in Fig. 31 and the phase margin
has increased to 115◦ .
Figure 31. Half and quarter symmetry odd-mode loop gain plot
for Q3 under worst-case conditions.
of the terminating impedances because the amplifier input and outputs ports are short circuited. Loop gain plots
for transistor Q3 quarter and half symmetry circuits are
shown in Fig. 31. Again, all circuit transistors have been
modified to produce a worst-case stability scenario, and the
analysis is performed over a 0.5-GHz to 70-GHz frequency
range. The traces do not encircle the unity gain point denoted by the red X and the amplifier is therefore odd-mode
stable. However, the phase margin for the quarter symmetry circuit is only 38◦ at 23.5 GHz. Fortunately, odd-mode
stability can be greatly improved with very little impact
on even-mode circuit performance. So-called “odd-mode resistors” can be connected between the transistor cells as
shown in Fig. 32. For the even-mode operation, the voltage across these resistors will be zero; they will dissipate
Figure 33. Half and quarter symmetry odd-mode loop gain plot
for Q3 with odd-mode resistors.
Figure 32. Two-stage MMIC block diagram with the inclusion of odd-mode stability resistors.
Microwave Monolithic Power Amplifier Design
The performance of the power amplifier MMICs can literally make or break the chances of having a successful
design and can affect the operation of modern microwave
systems. The advent of high-voltage MMIC technologies,
such as gallium nitride, has resulted in more advanced and
better performing system architectures. However, taking
full advantage of the higher operating voltage leaves little
margin for error in the electrical and thermal design of the
power amplifier MMIC. This is particularly true at a high
frequency where high-quality discrete devices and matching components are no longer available and a monolithic
implementation of the circuit is the only option. To illustrate a design approach, a two-stage saturated power amplifier MMIC example has been presented. The key steps in
the design process have been described and demonstrated,
starting with a description of the power amplifier specifications. This was followed by an examination of transistor
level data and the selection of a unit cell with appropriate
electrical and thermal characteristics. Next, the various
matching networks were synthesized and implemented in
a microstrip, and then an entire circuit was analyzed to
ensure stable operation under worst-case conditions.
The author would like to thank Chris Rodenbeck for his initial recommendation to write this article and Cassie Strickland at John Wiley & Sons, Inc. for cheerfully putting up
with my multiple requests for deadline extensions. I would
like to thank the reviewers for insightful comments that
improved the accuracy and quality of the work, and Eli
Reese and Kenneth Wills for proofreading the original submission. Finally, thanks goes to TriQuint Semiconductor
senior management for supporting this project and providing the necessary resources to complete the document.
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