Intel Quark SoC X1000
Intel® Quark™ SoC X1000
Datasheet
November 2014
Document Number: 329676-004US
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Datasheet
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Contents—Intel® Quark™ SoC X1000
Contents
1.0
Introduction ............................................................................................................ 37
1.1
About This Manual ............................................................................................. 37
1.2
Component Overview......................................................................................... 37
1.2.1 SoC CPU Core Features ........................................................................... 38
1.2.2 System Memory Controller Features ......................................................... 39
1.2.3 Embedded SRAM Features ....................................................................... 39
1.2.4 Power Management Features ................................................................... 39
1.2.5 Security Features ................................................................................... 39
1.2.6 PCI Express* Features ............................................................................ 39
1.2.7 Ethernet Features................................................................................... 40
1.2.8 USB2 Host Controller Features ................................................................. 40
1.2.9 USB2 Device Controller Features .............................................................. 40
1.2.10 SD/SDIO/eMMC Controller Features .......................................................... 40
1.2.11 I2C* Master Controller ............................................................................ 40
1.2.12 GPIO Features ....................................................................................... 41
1.2.13 SPI Master Controller .............................................................................. 41
1.2.14 High Speed UART Controller with DMA ...................................................... 41
1.2.15 Legacy Bridge ........................................................................................ 41
1.2.16 Package ................................................................................................ 41
1.3
Component Identification ................................................................................... 41
2.0
Physical Interfaces .................................................................................................. 45
2.1
Pin States Through Reset ................................................................................... 47
2.2
System Memory Signals ..................................................................................... 47
2.3
PCI Express* 2.0 Signals .................................................................................... 48
2.4
Ethernet Interface Signals .................................................................................. 49
2.5
USB 2.0 Interface Signals................................................................................... 49
2.6
Integrated Clock Interface Signals ....................................................................... 50
2.7
SDIO/SD/MMC Signals ....................................................................................... 50
2.8
High Speed UART Interface Signals...................................................................... 51
2.9
I2C* Interface Signals........................................................................................ 51
2.10 Legacy Serial Peripheral Interface (SPI) Signals..................................................... 52
2.11 Serial Peripheral Interface (SPI) .......................................................................... 52
2.12 Real Time Clock (RTC) Interface Signals ............................................................... 53
2.13 Power Management Signals ................................................................................ 53
2.14 JTAG and Debug Interface Signals ....................................................................... 53
2.15 Legacy Interface Signals .................................................................................... 54
2.16 General Purpose I/O Interface Signals.................................................................. 54
2.17 Power And Ground Pins ...................................................................................... 55
2.18 Hardware Straps ............................................................................................... 56
3.0
Ballout and Package Information............................................................................. 59
3.1
Package Diagram .............................................................................................. 59
3.2
Ball Listings ...................................................................................................... 60
4.0
Electrical Characteristics ......................................................................................... 69
4.1
Absolute Maximum Ratings ................................................................................. 69
4.2
Recommended Power Supply Ranges ................................................................... 70
4.3
Maximum Supply Current ................................................................................... 71
4.4
Configurable IO Characteristics ........................................................................... 72
4.5
RTC DC Characteristics ...................................................................................... 74
4.6
PCI Express* 2.0 DC/AC Characteristics ............................................................... 74
4.7
USB 2.0 DC/AC Characteristics............................................................................ 77
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4.8
4.9
General Interface Timing ....................................................................................79
4.8.1 Legacy SPI Interface Timing .....................................................................79
4.8.2 SPI0/1 Interface Timing...........................................................................80
4.8.3 SDIO Interface Timing.............................................................................81
Clock AC Timing ................................................................................................82
4.9.1 Reference Clock AC Characteristics............................................................82
5.0
Register Access Methods.........................................................................................85
5.1
Fixed I/O Register Access ...................................................................................85
5.2
Fixed Memory Mapped Register Access .................................................................85
5.3
I/O Referenced Register Access ...........................................................................85
5.4
Memory Referenced Register Access.....................................................................86
5.5
PCI Configuration Register Access ........................................................................86
5.5.1 PCI Configuration Access - CAM: I/O Indexed Scheme .................................86
5.5.2 PCI Configuration Access - ECAM: Memory Mapped Scheme .........................87
5.6
Message Bus Register Access ..............................................................................88
5.7
Register Field Access Types.................................................................................89
6.0
Mapping Address Spaces ..........................................................................................91
6.1
Physical Address Space Mappings.........................................................................91
6.1.1 Bridge Memory Map ................................................................................91
6.1.1.1 MMIO ......................................................................................93
6.1.1.2 DOS DRAM ...............................................................................94
6.1.1.3 Additional Mappings...................................................................94
6.1.2 MMIO Map .............................................................................................95
6.2
I/O Address Space .............................................................................................95
6.2.1 Host Bridge I/O Map ...............................................................................96
6.2.2 I/O Fabric I/O Map..................................................................................96
6.2.2.1 Legacy Bridge Fixed I/O Address Ranges ......................................96
6.2.2.2 Variable I/O Address Ranges.......................................................96
6.3
PCI Configuration Space .....................................................................................97
6.4
Message Bus Space............................................................................................99
7.0
Clocking ................................................................................................................. 101
7.1
Clocking Features ............................................................................................ 101
7.2
Platform/System Clock Domains ........................................................................ 102
8.0
Power Management ............................................................................................... 105
8.1
Power Management Features............................................................................. 105
8.2
Signal Descriptions .......................................................................................... 105
8.3
ACPI Supported States ..................................................................................... 106
8.3.1 S-State Definition ................................................................................. 106
8.3.1.1 S0 - Full On ............................................................................ 106
8.3.1.2 S3 - Suspend to RAM (Standby) ................................................ 106
8.3.1.3 S4 - Suspend to Disk (Hibernate) .............................................. 106
8.3.1.4 S5 - Soft Off ........................................................................... 107
8.3.2 System States...................................................................................... 107
8.3.3 Processor Idle States............................................................................. 108
8.3.4 Integrated Memory Controller States ....................................................... 108
8.3.5 PCIe* States ........................................................................................ 108
8.3.6 Interface State Combinations ................................................................. 109
8.4
Processor Core Power Management .................................................................... 109
8.4.1 Low-Power Idle States........................................................................... 109
8.4.1.1 Clock Control and Low-Power States .......................................... 109
8.4.2 Processor Core C-States Description........................................................ 109
8.4.2.1 Core C0 State ......................................................................... 109
8.4.2.2 Core C1 State ......................................................................... 110
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Contents—Intel® Quark™ SoC X1000
8.5
9.0
8.4.2.3 Core C2 State......................................................................... 110
Memory Controller Power Management............................................................... 110
8.5.1 Disabling Unused System Memory Outputs .............................................. 110
8.5.2 DRAM Power Management and Initialization ............................................. 110
8.5.2.1 Initialization Role of CKE .......................................................... 110
8.5.2.2 Dynamic Self-Refresh .............................................................. 110
8.5.2.3 Dynamic Power Down Operation ............................................... 111
8.5.2.4 Functional Clock Gating ........................................................... 111
Power Up and Reset Sequence............................................................................... 113
9.1
Intel® Quark™ SoC X1000 System States ........................................................... 113
9.1.1 System Sleep States Control (S-States) .................................................. 113
9.2
Power Up and Down Sequences......................................................................... 113
9.2.1 Power Up, Wake and Reset Overview ...................................................... 113
9.2.2 RTC Power Well Transition: G5 to G3 State Transition ............................... 114
9.2.3 AC Power Applied: G3 to S4/S5 State Transition ....................................... 115
9.2.4 Using PWR_BTN_B: Transition from S4/S5 to S0 ...................................... 116
9.2.5 Power-Up Sequence without G2/G3: No Coin-Cell Battery .......................... 118
9.2.6 Going to Sleep: Transitions from S0 to S3 or S4/S5 .................................. 120
9.2.7 Wake Events: Transition from S3 to S0 ................................................... 120
9.2.8 System Reset Sequences....................................................................... 121
9.2.8.1 Cold Boot Sequence ............................................................... 121
9.2.8.2 Cold Reset Sequence............................................................... 121
9.2.8.3 Warm Reset Sequence (Internal) .............................................. 122
9.2.8.4 Externally Initiated Warm Reset Sequence ................................. 122
9.2.9 Handling Power Failures ........................................................................ 122
10.0 Thermal Management ............................................................................................ 123
10.1 Overview ....................................................................................................... 123
10.2 Thermal Sensor............................................................................................... 123
11.0 Processor Core ...................................................................................................... 125
12.0 Host Bridge ........................................................................................................... 127
12.1 Embedded SRAM (eSRAM)................................................................................ 127
12.1.1 Initialization ........................................................................................ 127
12.1.2 Configuration ....................................................................................... 127
12.1.2.1 4KB Page Mode ...................................................................... 127
12.1.2.2 512KB Block Page Mode........................................................... 128
12.1.3 Configuration Locking ........................................................................... 129
12.1.4 ECC Protection ..................................................................................... 130
12.1.5 Flush to DRAM ..................................................................................... 130
12.2 Isolated Memory Regions (IMR)......................................................................... 130
12.2.1 IMR Violation ....................................................................................... 131
12.2.2 IMR Locking......................................................................................... 131
12.3 Remote Management Unit DMA ......................................................................... 131
12.4 Register Map .................................................................................................. 132
12.5 PCI Configuration Registers .............................................................................. 132
12.5.1 PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—Offset 0h....... 133
12.5.2 PCI Status and Command Fields (PCI_STATUS_COMMAND)—Offset 4h ........ 133
12.5.3 PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)—Offset 8h... 134
12.5.4 PCI Miscellaneous Fields (PCI_MISC)—Offset Ch ....................................... 134
12.5.5 PCI Subsystem ID and Subsystem Vendor ID Fields
(PCI_SUBSYSTEM)—Offset 2Ch .............................................................. 135
12.5.6 Message Bus Control Register (MCR) (SB_PACKET_REG)—Offset D0h.......... 135
12.5.7 Message Data Register (MDR) (SB_DATA_REG)—Offset D4h ...................... 136
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12.6
12.7
12.5.8 Message Control Register eXtension (MCRX) (SB_ADDR_EXTN_REG)—Offset
D8h .................................................................................................... 136
12.5.9 Manufacturer ID (PCI_MANUFACTURER)—Offset F8h ................................. 137
IO Mapped Register ......................................................................................... 138
12.6.1 ACPI Processor Block............................................................................. 138
12.6.1.1 Processor Control (P_CNT)—Offset 0h ........................................ 138
12.6.1.2 Level 2 Register (P_LVL2)—Offset 4h ......................................... 138
12.6.1.3 C6 Control Register (P_C6C)—Offset Ch ..................................... 139
12.6.2 SPI DMA Block ..................................................................................... 140
12.6.2.1 Option Register 1(P_CFG_72) —Offset 72h ................................. 140
Message Bus Register....................................................................................... 140
12.7.1 Host Bridge Arbiter (Port 0x00) .............................................................. 140
12.7.1.1 Enhanced Configuration Space (AEC_CTRL)—Offset 0h ................ 141
12.7.1.2 STATUS—Offset 21h ............................................................... 141
12.7.1.3 Requester ID Match Control (ASUBCHAN_CTRL)—Offset 50h ........ 142
12.7.1.4 Requester ID Match Sub-Channel 1 (ASUBCHAN1_MATCH)—Offset
51h ....................................................................................... 143
12.7.1.5 Requester ID Match Sub-Channel 2 (ASUBCHAN2_MATCH)—Offset
52h ....................................................................................... 143
12.7.1.6 Requester ID Match Sub-Channel 3 (ASUBCHAN3_MATCH)—Offset
53h ....................................................................................... 144
12.7.2 Host Bridge (Port 0x03) ......................................................................... 145
12.7.2.1 Host Miscellaneous Controls 2 (HMISC2)—Offset 3h .................... 146
12.7.2.2 Host System Management Mode Controls (HSMMCTL)—Offset 4h.. 147
12.7.2.3 Host Memory I/O Boundary (HMBOUND)—Offset 8h .................... 148
12.7.2.4 Extended Configuration Space (HECREG)—Offset 9h ................... 148
12.7.2.5 Miscellaneous Legacy Signal Enables (HLEGACY)—Offset Ah ......... 149
12.7.2.6 Host Bridge Write Flush Control (HWFLUSH)—Offset Ch ............... 149
12.7.2.7 MTRR Capabilities (MTRR_CAP)—Offset 40h ............................... 150
12.7.2.8 MTRR Default Type (MTRR_DEF_TYPE)—Offset 41h ..................... 151
12.7.2.9 MTRR Fixed 64KB Range 0x00000 (MTRR_FIX64K_00000)—Offset
42h ....................................................................................... 151
12.7.2.10 MTRR Fixed 64KB Range 0x40000 (MTRR_FIX64K_40000)—Offset
43h ....................................................................................... 152
12.7.2.11 MTRR Fixed 16KB Range 0x80000 (MTRR_FIX16K_80000)—Offset
44h ....................................................................................... 152
12.7.2.12 MTRR Fixed 16KB Range 0x90000 (MTRR_FIX16K_90000)—Offset
45h ....................................................................................... 153
12.7.2.13 MTRR Fixed 16KB Range 0xA0000 (MTRR_FIX16K_A0000)—Offset
46h ....................................................................................... 154
12.7.2.14 MTRR Fixed 16KB Range 0xB0000 (MTRR_FIX16K_B0000)—Offset
47h ....................................................................................... 154
12.7.2.15 MTRR Fixed 4KB Range 0xC0000 (MTRR_FIX4K_C0000)—Offset
48h ....................................................................................... 155
12.7.2.16 MTRR Fixed 4KB Range 0xC4000 (MTRR_FIX4K_C4000)—Offset
49h ....................................................................................... 155
12.7.2.17 MTRR Fixed 4KB Range 0xC8000 (MTRR_FIX4K_C8000)—Offset
4Ah ....................................................................................... 156
12.7.2.18 MTRR Fixed 4KB Range 0xCC000 (MTRR_FIX4K_CC000)—Offset
4Bh ....................................................................................... 156
12.7.2.19 MTRR Fixed 4KB Range 0xD0000 (MTRR_FIX4K_D0000)—Offset
4Ch ....................................................................................... 157
12.7.2.20 MTRR Fixed 4KB Range 0xD40000 (MTRR_FIX4K_D4000)—Offset
4Dh....................................................................................... 158
12.7.2.21 MTRR Fixed 4KB Range 0xD8000 (MTRR_FIX4K_D8000)—Offset
4Eh ....................................................................................... 158
12.7.2.22 MTRR Fixed 4KB Range 0xDC000 (MTRR_FIX4K_DC000)—Offset
4Fh ....................................................................................... 159
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12.7.2.23 MTRR Fixed 4KB Range 0xE0000 (MTRR_FIX4K_E0000)—Offset
50h....................................................................................... 159
12.7.2.24 MTRR Fixed 4KB Range 0xE4000 (MTRR_FIX4K_E4000)—Offset
51h....................................................................................... 160
12.7.2.25 MTRR Fixed 4KB Range 0xE8000 (MTRR_FIX4K_E8000)—Offset
52h....................................................................................... 160
12.7.2.26 MTRR Fixed 4KB Range 0xEC000 (MTRR_FIX4K_EC000)—Offset
53h....................................................................................... 161
12.7.2.27 MTRR Fixed 4KB Range 0xF0000 (MTRR_FIX4K_F0000)—Offset
54h....................................................................................... 161
12.7.2.28 MTRR Fixed 4KB Range 0xF4000 (MTRR_FIX4K_F4000)—Offset
55h....................................................................................... 162
12.7.2.29 MTRR Fixed 4KB Range 0xF8000 (MTRR_FIX4K_F8000)—Offset
56h....................................................................................... 163
12.7.2.30 MTRR Fixed 4KB Range 0xFC000 (MTRR_FIX4K_FC000)—Offset
57h....................................................................................... 163
12.7.2.31 System Management Range Physical Base
(MTRR_SMRR_PHYSBASE)—Offset 58h ...................................... 164
12.7.2.32 System Management Range Physical Mask
(MTRR_SMRR_PHYSMASK)—Offset 59h...................................... 164
12.7.2.33 MTRR Variable Range Physical Base 0
(MTRR_VAR_PHYSBASE0)—Offset 5Ah....................................... 165
12.7.2.34 MTRR Variable Range Physical Mask 0 (MTRR_VAR_PHYSMASK0)—
Offset 5Bh ............................................................................. 165
12.7.2.35 MTRR Variable Range Physical Base 1
(MTRR_VAR_PHYSBASE1)—Offset 5Ch....................................... 166
12.7.2.36 MTRR Variable Range Physical Mask 1 (MTRR_VAR_PHYSMASK1)—
Offset 5Dh ............................................................................. 167
12.7.2.37 MTRR Variable Range Physical Base 2
(MTRR_VAR_PHYSBASE2)—Offset 5Eh....................................... 167
12.7.2.38 MTRR Variable Range Physical Mask 2 (MTRR_VAR_PHYSMASK2)—
Offset 5Fh.............................................................................. 168
12.7.2.39 MTRR Variable Range Physical Base 3
(MTRR_VAR_PHYSBASE3)—Offset 60h....................................... 168
12.7.2.40 MTRR Variable Range Physical Mask 3 (MTRR_VAR_PHYSMASK3)—
Offset 61h ............................................................................. 169
12.7.2.41 MTRR Variable Range Physical Base 4
(MTRR_VAR_PHYSBASE4)—Offset 62h....................................... 169
12.7.2.42 MTRR Variable Range Physical Mask 4 (MTRR_VAR_PHYSMASK4)—
Offset 63h ............................................................................. 170
12.7.2.43 MTRR Variable Range Physical Base 5
(MTRR_VAR_PHYSBASE5)—Offset 64h....................................... 171
12.7.2.44 MTRR Variable Range Physical Mask 5 (MTRR_VAR_PHYSMASK5)—
Offset 65h ............................................................................. 171
12.7.2.45 MTRR Variable Range Physical Base 6
(MTRR_VAR_PHYSBASE6)—Offset 66h....................................... 172
12.7.2.46 MTRR Variable Range Physical Mask 6 (MTRR_VAR_PHYSMASK6)—
Offset 67h ............................................................................. 172
12.7.2.47 MTRR Variable Range Physical Base 7
(MTRR_VAR_PHYSBASE7)—Offset 68h....................................... 173
12.7.2.48 MTRR Variable Range Physical Mask 7 (MTRR_VAR_PHYSMASK7)—
Offset 69h ............................................................................. 173
12.7.3 Remote Management Unit (Port 0x04) .................................................... 174
12.7.3.1 SPI DMA Count Register (P_CFG_60)—Offset 60h........................ 174
12.7.3.2 SPI DMA Destination Register (P_CFG_61)—Offset 61h ................ 175
12.7.3.3 SPI DMA Source Register (P_CFG_62)—Offset 62h ...................... 175
12.7.3.4 Processor Register Block (P_BLK) Base Address
(P_CFG_70)—Offset 70h .......................................................... 176
12.7.3.5 Control Register (P_CFG_71)—Offset 71h................................... 176
12.7.3.6 Watchdog Control Register (P_CFG_74)—Offset 74h .................... 177
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12.7.3.7 Thermal Sensor Mode Register (P_CFG_B0)—Offset B0h............... 178
12.7.3.8 Thermal Sensor Temperature Register (P_CFG_B1)—Offset B1h .... 178
12.7.3.9 Thermal Sensor Programmable Trip Point Register
(P_CFG_B2)—Offset B2h .......................................................... 179
12.7.4 Memory Manager (Port 0x05) ................................................................. 180
12.7.4.1 Control (BCTRL)—Offset 1h ...................................................... 181
12.7.4.2 Write Flush Policy (BWFLUSH)—Offset 2h ................................... 182
12.7.4.3 Isolated Memory Region Violation Control (BIMRVCTL)—Offset 19h 183
12.7.4.4 Debug 1 (DEBUG1)—Offset 31h ................................................ 184
12.7.4.5 Isolated Memory Region 0 Low Address (IMR0L)—Offset 40h ........ 186
12.7.4.6 Isolated Memory Region 0 High Address (IMR0H)—Offset 41h ....... 186
12.7.4.7 Isolated Memory Region 0 Read Mask (IMR0RM)—Offset 42h ........ 187
12.7.4.8 Isolated Memory Region 0 Write Mask (IMR0WM)—Offset 43h ....... 189
12.7.4.9 Isolated Memory Region 1 Low Address (IMR1L)—Offset 44h ........ 190
12.7.4.10 Isolated Memory Region 1 High Address (IMR1H)—Offset 45h.... 191
12.7.4.11 Isolated Memory Region 1 Read Mask (IMR1RM)—Offset 46h..... 191
12.7.4.12 Isolated Memory Region 1 Write Mask (IMR1WM)—Offset 47h ... 193
12.7.4.13 Isolated Memory Region 2 Low Address (IMR2L)—Offset 48h ..... 195
12.7.4.14 Isolated Memory Region 2 High Address (IMR2H)—Offset 49h.... 196
12.7.4.15 Isolated Memory Region 2 Read Mask (IMR2RM)—Offset 4Ah..... 196
12.7.4.16 Isolated Memory Region 2 Write Mask (IMR2WM)—Offset 4Bh ... 198
12.7.4.17 Isolated Memory Region 3 Low Address (IMR3L)—Offset 4Ch ..... 200
12.7.4.18 Isolated Memory Region 3 High Address (IMR3H)—Offset 4Dh ... 200
12.7.4.19 Isolated Memory Region 3 Read Mask (IMR3RM)—Offset 4Eh ..... 201
12.7.4.20 Isolated Memory Region 3 Write Mask (IMR3WM)—Offset 4Fh.... 203
12.7.4.21 Isolated Memory Region 4 Low Address (IMR4L)—Offset 50h ..... 204
12.7.4.22 Isolated Memory Region 4 High Address (IMR4H)—Offset 51h.... 205
12.7.4.23 Isolated Memory Region 4 Read Mask (IMR4RM)—Offset 52h..... 205
12.7.4.24 Isolated Memory Region 4 Write Mask (IMR4WM)—Offset 53h ... 207
12.7.4.25 Isolated Memory Region 5 Low Address (IMR5L)—Offset 54h ..... 209
12.7.4.26 Isolated Memory Region 5 High Address (IMR5H)—Offset 55h.... 210
12.7.4.27 Isolated Memory Region 5 Read Mask (IMR5RM)—Offset 56h..... 210
12.7.4.28 Isolated Memory Region 5 Write Mask (IMR5WM)—Offset 57h ... 212
12.7.4.29 Isolated Memory Region 6 Low Address (IMR6L)—Offset 58h ..... 214
12.7.4.30 Isolated Memory Region 6 High Address (IMR6H)—Offset 59h.... 214
12.7.4.31 Isolated Memory Region 6 Read Mask (IMR6RM)—Offset 5Ah..... 215
12.7.4.32 Isolated Memory Region 6 Write Mask (IMR6WM)—Offset 5Bh ... 217
12.7.4.33 Isolated Memory Region 7 Low Address (IMR7L)—Offset 5Ch ..... 218
12.7.4.34 Isolated Memory Region 7 High Address (IMR7H)—Offset 5Dh ... 219
12.7.4.35 Isolated Memory Region 7 Read Mask (IMR7RM)—Offset 5Eh ..... 219
12.7.4.36 Isolated Memory Region 7 Write Mask (IMR7WM)—Offset 5Fh.... 221
12.7.4.37 eSRAM Control (ESRAMCTRL)—Offset 81h ............................... 223
12.7.4.38 eSRAM Block Page Control (ESRAMPGCTRL_BLOCK)—Offset 82h 224
12.7.4.39 eSRAM Correctable Error (ESRAMCERR)—Offset 83h................. 226
12.7.4.40 eSRAM Uncorrectable Error (ESRAMUERR)—Offset 84h ............. 226
12.7.4.41 eSRAM ECC Error Syndrome (ESRAMSDROME)—Offset 88h ....... 227
12.7.5 Memory Manager eSRAM (Port 0x05) ...................................................... 228
12.7.5.1 eSRAM Page Control Register[0-127]
(ESRAMPGCTRL[0-127])—Offset 0h, Count 128, Stride 4h ............ 228
12.7.6 SoC Unit (Port 0x31) ............................................................................. 229
12.7.6.1 Thermal Sensor Configuration 4 (SCU_TSCFG4_Config)—Offset
34h ....................................................................................... 229
12.7.6.2 Sticky Write Once (CFGSTICKY_W1)—Offset 50h ......................... 230
12.7.6.3 Sticky Read/Write (CFGSTICKY_RW)—Offset 51h......................... 231
12.7.6.4 Non-Sticky Read/Write Once (CFGNONSTICKY_W1)—Offset 52h .... 231
13.0 System Memory Controller ..................................................................................... 233
13.1 Signal Descriptions .......................................................................................... 233
13.2 Features ......................................................................................................... 234
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13.3
13.4
13.5
13.2.1 System Memory Technology Supported ................................................... 234
13.2.2 Rules for Populating Memory Down Ranks................................................ 235
13.2.3 DRAM Error Detection & Correction (EDC)................................................ 235
13.2.4 DRAM Data Scrambling ......................................................................... 236
13.2.5 Power Management .............................................................................. 236
Register Map .................................................................................................. 236
Message Bus Registers..................................................................................... 236
13.4.1 DRAM Rank Population (DRP)—Offset 0h ................................................. 237
13.4.2 DRAM Timing Register 0 (DTR0)—Offset 1h ............................................. 238
13.4.3 DRAM Timing Register 1 (DTR1)—Offset 2h ............................................. 240
13.4.4 DRAM Timing Register 2 (DTR2)—Offset 3h ............................................. 242
13.4.5 DRAM Timing Register 3 (DTR3)—Offset 4h ............................................. 243
13.4.6 DRAM Timing Register 4 (DTR4)—Offset 5h ............................................. 244
13.4.7 DRAM Power Management Control 0 (DPMC0)—Offset 6h........................... 245
13.4.8 DRAM Refresh Control (DRFC)—Offset 8h ................................................ 247
13.4.9 DRAM Scheduler Control (DSCH)—Offset 9h............................................. 248
13.4.10 DRAM Calibration Control (DCAL)—Offset Ah .......................................... 249
13.4.11 DRAM Reset Management Control (DRMC)—Offset Bh.............................. 250
13.4.12 Power Management Status (PMSTS)—Offset Ch ...................................... 251
13.4.13 DRAM Control Operation (DCO)—Offset Fh ............................................. 252
13.4.14 Sticky Scratchpad 0 (SSKPD0)—Offset 4Ah ............................................ 252
13.4.15 Sticky Scratchpad 1 (SSKPD1)—Offset 4Bh ............................................ 253
13.4.16 DRAM ECC Control Register (DECCCTRL)—Offset 60h .............................. 253
13.4.17 DRAM ECC Status (DECCSTAT)—Offset 61h............................................ 254
13.4.18 DRAM ECC Single Bit Error Count (DECCSBECNT)—Offset 62h .................. 254
13.4.19 DRAM Single Bit ECC Error Captured Address (DECCSBECA)—Offset 68h .... 255
13.4.20 DRAM Single Bit ECC Error Captured Syndrome (DECCSBECS)—Offset 69h. 256
13.4.21 DRAM Double Bit ECC Error Captured Address (DECCDBECA)—Offset 6Ah .. 256
13.4.22 DRAM Double Bit ECC Error Captured Syndrome (DECCDBECS)—Offset 6Bh 257
13.4.23 Memory Controller Fuse Status (DFUSESTAT)—Offset 70h ........................ 257
13.4.24 Scrambler Seed (DSCRMSEED)—Offset 80h............................................ 258
Message Bus Commands .................................................................................. 259
14.0 PCI Express* 2.0 ................................................................................................... 261
14.1 Signal Descriptions .......................................................................................... 261
14.2 Features ........................................................................................................ 261
14.2.1 Interrupts and Events ........................................................................... 262
14.2.1.1 Express Card Hot Plug Events ................................................... 262
14.2.1.2 System Error (SERR)............................................................... 263
14.2.2 Power Management .............................................................................. 263
14.3 References ..................................................................................................... 263
14.4 Register Map .................................................................................................. 263
14.5 PCI Configuration Registers .............................................................................. 264
14.5.1 Identifiers (ID)—Offset 0h ..................................................................... 266
14.5.2 Primary Status (CMD_PSTS)—Offset 4h................................................... 266
14.5.3 Class Code (RID_CC)—Offset 8h............................................................. 268
14.5.4 Header Type (CLS_PLT_HTYPE)—Offset Ch .............................................. 268
14.5.5 Secondary Latency Timer (BNUM_SLT)—Offset 18h .................................. 269
14.5.6 Secondary Status (IOBL_SSTS)—Offset 1Ch ............................................ 269
14.5.7 Memory Base and Limit (MBL)—Offset 20h .............................................. 270
14.5.8 Prefetchable Memory Base and Limit (PMBL)—Offset 24h........................... 271
14.5.9 Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h ................. 271
14.5.10 Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch ............... 272
14.5.11 Capabilities List Pointer (CAPP)—Offset 34h............................................ 272
14.5.12 Bridge Control (INTR_BCTRL)—Offset 3Ch.............................................. 273
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Intel® Quark™ SoC X1000—Contents
14.5.13
14.5.14
14.5.15
14.5.16
14.5.17
14.5.18
14.5.19
14.5.20
14.5.21
14.5.22
14.5.23
14.5.24
14.5.25
14.5.26
14.5.27
14.5.28
14.5.29
14.5.30
14.5.31
14.5.32
14.5.33
14.5.34
14.5.35
14.5.36
14.5.37
14.5.38
14.5.39
14.5.40
14.5.41
14.5.42
14.5.43
14.5.44
14.5.45
14.5.46
14.5.47
14.5.48
14.5.49
14.5.50
14.5.51
14.5.52
14.5.53
PCI Express Capabilities (CLIST_XCAP)—Offset 40h ................................. 274
Device Capabilities (DCAP)—Offset 44h .................................................. 275
Device Status (DCTL_DSTS)—Offset 48h ................................................ 276
Link Capabilities (LCAP)—Offset 4Ch ...................................................... 277
Link Status (LCTL_LSTS)—Offset 50h..................................................... 279
Slot Capabilities (SLCAP)—Offset 54h .................................................... 280
Slot Status (SLCTL_SLSTS)—Offset 58h ................................................. 281
Root Control (RCTL)—Offset 5Ch ........................................................... 283
Root Status (RSTS)—Offset 60h ............................................................ 283
Device Capabilities 2 (DCAP2)—Offset 64h ............................................. 284
Device Status 2 (DCTL2_DSTS2)—Offset 68h.......................................... 285
Link Capability 2 (LCAP2)—Offset 6Ch.................................................... 286
Link Status 2 (LCTL2_LSTS2)—Offset 70h .............................................. 286
Slot Capabilities 2 (SLCAP2)—Offset 74h ................................................ 288
Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h ........................................... 288
Message Signaled Interrupt Message Control (MID_MC)—Offset 80h .......... 289
Message Signaled Interrupt Message Address (MA)—Offset 84h ................ 289
Message Signaled Interrupt Message Data (MD)—Offset 88h..................... 290
Subsystem Vendor Capability (SVCAP)—Offset 90h.................................. 290
Subsystem Vendor IDs (SVID)—Offset 94h ............................................. 291
PCI Power Management Capabilities (PMCAP_PMC)—Offset A0h................. 291
PCI Power Management Control And Status (PMCS)—Offset A4h................ 292
Channel Configuration (CCFG)—Offset D0h ............................................. 293
Miscellaneous Port Configuration 2 (MPC2)—Offset D4h ............................ 294
Miscellaneous Port Configuration (MPC)—Offset D8h ................................ 295
SMI / SCI Status (SMSCS)—Offset DCh .................................................. 296
Message Bus Control (PHYCTL_PHYCTL2_IOSFSBCTL)—Offset F4h ............. 297
Advanced Error Reporting Capability Header (AECH)—Offset 100h ............. 298
Uncorrectable Error Status (UES)—Offset 104h ....................................... 299
Uncorrectable Error Mask (UEM)—Offset 108h......................................... 300
Uncorrectable Error Severity (UEV)—Offset 10Ch..................................... 301
Correctable Error Status (CES)—Offset 110h........................................... 302
Correctable Error Mask (CEM)—Offset 114h ............................................ 303
Advanced Error Capabilities and Control (AECC)—Offset 118h ................... 304
Header Log (HL_DW1)—Offset 11Ch ...................................................... 304
Header Log (HL_DW2)—Offset 120h ...................................................... 305
Header Log (HL_DW3)—Offset 124h ...................................................... 305
Header Log (HL_DW4)—Offset 128h ...................................................... 305
Root Error Command (REC)—Offset 12Ch ............................................... 306
Root Error Status (RES)—Offset 130h .................................................... 306
Error Source Identification (ESID)—Offset 134h ...................................... 307
15.0 10/100 Mbps Ethernet ........................................................................................... 309
15.1 Signal Descriptions .......................................................................................... 309
15.2 Features:........................................................................................................ 309
15.3 References...................................................................................................... 310
15.4 Register Map................................................................................................... 311
15.5 PCI Configuration Registers............................................................................... 311
15.5.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 312
15.5.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 313
15.5.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 313
15.5.4 Status Register (STATUS)—Offset 6h....................................................... 314
15.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 315
15.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 315
15.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ............................................ 315
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Contents—Intel® Quark™ SoC X1000
15.6
15.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 316
15.5.9 BIST (BIST)—Offset Fh ......................................................................... 316
15.5.10 Base Address Register (BAR0)—Offset 10h ............................................. 317
15.5.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h..................... 317
15.5.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 318
15.5.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh.............................................. 318
15.5.14 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h ............ 318
15.5.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 319
15.5.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 319
15.5.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 320
15.5.18 MIN_GNT (MIN_GNT)—Offset 3Eh ......................................................... 320
15.5.19 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 320
15.5.20 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 321
15.5.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .......................... 321
15.5.22 Power Management Capabilities (PMC)—Offset 82h ................................. 321
15.5.23 Power Management Control/Status Register (PMCSR)—Offset 84h ............. 322
15.5.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h.... 323
15.5.25 Power Management Data Register (DATA_REGISTER)—Offset 87h............. 323
15.5.26 Capability ID (MSI_CAP_ID)—Offset A0h ............................................... 324
15.5.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 324
15.5.28 Message Control (MESSAGE_CTRL)—Offset A2h ...................................... 324
15.5.29 Message Address (MESSAGE_ADDR)—Offset A4h .................................... 325
15.5.30 Message Data (MESSAGE_DATA)—Offset A8h ......................................... 325
15.5.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 326
15.5.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................................. 326
Memory Mapped Registers ................................................................................ 327
15.6.1 MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h............ 331
15.6.2 MAC Frame Filter (Register 1) (GMAC_REG_1)—Offset 4h .......................... 334
15.6.3 Hash Table High Register (Register 2) (GMAC_REG_2)—Offset 8h ............... 336
15.6.4 Hash Table Low Register (Register 3) (GMAC_REG_3)—Offset Ch ............... 336
15.6.5 GMII Address Register (Register 4) (GMAC_REG_4)—Offset 10h ................. 337
15.6.6 GMII Data Register (Register 5) (GMAC_REG_5)—Offset 14h ..................... 338
15.6.7 Flow Control Register (Register 6) (GMAC_REG_6)—Offset 18h .................. 339
15.6.8 VLAN Tag Register (Register 7) (GMAC_REG_7)—Offset 1Ch ...................... 340
15.6.9 Version Register (Register 8) (GMAC_REG_8)—Offset 20h ......................... 341
15.6.10 Debug Register (Register 9) (GMAC_REG_9)—Offset 24h......................... 342
15.6.11 Interrupt Register (Register 14) (GMAC_REG_14)—Offset 38h.................. 343
15.6.12 Interrupt Mask Register (Register 15) (GMAC_REG_15)—Offset 3Ch ......... 344
15.6.13 MAC Address0 High Register (Register 16) (GMAC_REG_16)—Offset 40h ... 345
15.6.14 MAC Address0 Low Register (Register 17) (GMAC_REG_17)—Offset 44h .... 345
15.6.15 MMC Control Register (Register 64) (GMAC_REG_64)—Offset 100h ........... 346
15.6.16 MMC Receive Interrupt Register (MMC_INTR_RX)—Offset 104h ................ 347
15.6.17 MMC Transmit Interrupt Register (MMC_INTR_TX)—Offset 108h ............... 349
15.6.18 MMC Receive Interrupt Mask Register
(MMC_INTR_MASK_RX)—Offset 10Ch ................................................... 351
15.6.19 MMC Transmit Interrupt Mask Register
(MMC_INTR_MASK_TX)—Offset 110h.................................................... 353
15.6.20 MMC Transmit Good Bad Octet Counter Register
(TXOCTETCOUNT_GB)—Offset 114h........................................................ 355
15.6.21 MMC Transmit Good Bad Frame Counter Register
(TXFRAMECOUNT_GB)—Offset 118h ....................................................... 355
15.6.22 MMC Transmit Broadcast Good Frame Counter Register
(TXBROADCASTFRAMES_G)—Offset 11Ch................................................ 356
15.6.23 MMC Transmit Multicast Good Frame Counter Register
(TXMULTICASTFRAMES_G)—Offset 120h ................................................. 356
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15.6.24 MMC Transmit 64 Octet Good Bad Frame Counter Register
(TX64OCTETS_GB)—Offset 124h ............................................................ 357
15.6.25 MMC Transmit 65 to 127 Octet Good Bad Frame Counter Register
(TX65TO127OCTETS_GB)—Offset 128h ................................................... 357
15.6.26 MMC Transmit 128 to 255 Octet Good Bad Frame Counter Register
(TX128TO255OCTETS_GB)—Offset 12Ch ................................................. 358
15.6.27 MMC Transmit 256 to 511 Octet Good Bad Frame Counter Register
(TX256TO511OCTETS_GB)—Offset 130h.................................................. 358
15.6.28 MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Register
(TX512TO1023OCTETS_GB)—Offset 134h ................................................ 358
15.6.29 MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Register
(TX1024TOMAXOCTETS_GB)—Offset 138h ............................................... 359
15.6.30 MMC Transmit Unicast Good Bad Frame Counter Register
(TXUNICASTFRAMES_GB)—Offset 13Ch ................................................... 359
15.6.31 MMC Transmit Multicast Good Bad Frame Counter Register
(TXMULTICASTFRAMES_GB)—Offset 140h................................................ 360
15.6.32 MMC Transmit Broadcast Good Bad Frame Counter Register
(TXBROADCASTFRAMES_GB)—Offset 144h .............................................. 360
15.6.33 MMC Transmit Underflow Error Frame Counter Register
(TXUNDERFLOWERROR)—Offset 148h ..................................................... 361
15.6.34 MMC Transmit Single Collision Good Frame Counter Register
(TXSINGLECOL_G)—Offset 14Ch............................................................. 361
15.6.35 MMC Transmit Multiple Collision Good Frame Counter Register
(TXMULTICOL_G)—Offset 150h............................................................... 362
15.6.36 MMC Transmit Deferred Frame Counter Register (TXDEFERRED)—Offset
154h ................................................................................................... 362
15.6.37 MMC Transmit Late Collision Frame Counter Register (TXLATECOL)—Offset
158h ................................................................................................... 362
15.6.38 MMC Transmit Excessive Collision Frame Counter Register
(TXEXESSCOL)—Offset 15Ch .................................................................. 363
15.6.39 MMC Transmit Carrier Error Frame Counter Register
(TXCARRIERERROR)—Offset 160h........................................................... 363
15.6.40 MMC Transmit Good Octet Counter Register (TXOCTETCOUNT_G)—Offset
164h ................................................................................................... 364
15.6.41 MMC Transmit Good Frame Counter Register (TXFRAMECOUNT_G)—Offset
168h ................................................................................................... 364
15.6.42 MMC Transmit Excessive Deferral Frame Counter Register (TXEXCESSDEF)—
Offset 16Ch ......................................................................................... 365
15.6.43 MMC Transmit Pause Frame Counter Register (TXPAUSEFRAMES)—Offset
170h ................................................................................................... 365
15.6.44 MMC Transmit VLAN Good Frame Counter Register
(TXVLANFRAMES_G)—Offset 174h .......................................................... 366
15.6.45 MMC Transmit Oversize Good Frame Counter Register
(TXOVERSIZE_G)—Offset 178h............................................................... 366
15.6.46 MMC Receive Good Bad Frame Counter Register
(RXFRAMECOUNT_GB)—Offset 180h........................................................ 366
15.6.47 MMC Receive Good Bad Octet Counter Register
(RXOCTETCOUNT_GB)—Offset 184h........................................................ 367
15.6.48 MMC Receive Good Octet Counter Register (RXOCTETCOUNT_G)—Offset
188h ................................................................................................... 367
15.6.49 MMC Receive Broadcast Good Frame Counter Register
(RXBROADCASTFRAMES_G)—Offset 18Ch ................................................ 368
15.6.50 MMC Receive Multicast Good Frame Counter Register
(RXMULTICASTFRAMES_G)—Offset 190h ................................................. 368
15.6.51 MMC Receive CRC Error Frame Counter Register (RXCRCERROR)—Offset
194h ................................................................................................... 369
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15.6.52 MMC Receive Alignment Error Frame Counter Register
(RXALIGNMENTERROR)—Offset 198h ...................................................... 369
15.6.53 MMC Receive Runt Frame Counter Register (RXRUNTERROR)—Offset 19Ch 370
15.6.54 MMC Receive Jabber Error Frame Counter Register
(RXJABBERERROR)—Offset 1A0h ............................................................ 370
15.6.55 MMC Receive Undersize Good Frame Counter Register
(RXUNDERSIZE_G)—Offset 1A4h............................................................ 370
15.6.56 MMC Receive Oversize Good Frame Counter Register
(RXOVERSIZE_G)—Offset 1A8h.............................................................. 371
15.6.57 MMC Receive 64 Octet Good Bad Frame Counter Register
(RX64OCTETS_GB)—Offset 1ACh ........................................................... 371
15.6.58 MMC Receive 65 to 127 Octet Good Bad Frame Counter Register
(RX65TO127OCTETS_GB)—Offset 1B0h................................................... 372
15.6.59 MMC Receive 128 to 255 Octet Good Bad Frame Counter Register
(RX128TO255OCTETS_GB)—Offset 1B4h ................................................. 372
15.6.60 MMC Receive 256 to 511 Octet Good Bad Frame Counter Register
(RX256TO511OCTETS_GB)—Offset 1B8h ................................................. 373
15.6.61 MMC Receive 512 to 1023 Octet Good Bad Frame Counter Register
(RX512TO1023OCTETS_GB)—Offset 1BCh ............................................... 373
15.6.62 MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Register
(RX1024TOMAXOCTETS_GB)—Offset 1C0h .............................................. 374
15.6.63 MMC Receive Unicast Good Frame Counter Register (RXUNICASTFRAMES_G)—
Offset 1C4h ......................................................................................... 374
15.6.64 MMC Receive Length Error Frame Counter Register
(RXLENGTHERROR)—Offset 1C8h ........................................................... 374
15.6.65 MMC Receive Out Of Range Error Frame Counter Register
(RXOUTOFRANGETYPE)—Offset 1CCh...................................................... 375
15.6.66 MMC Receive Pause Frame Counter Register (RXPAUSEFRAMES)—Offset
1D0h .................................................................................................. 375
15.6.67 MMC Receive FIFO Overflow Frame Counter Register
(RXFIFOOVERFLOW)—Offset 1D4h.......................................................... 376
15.6.68 MMC Receive VLAN Good Bad Frame Counter Register (RXVLANFRAMES_GB)—
Offset 1D8h......................................................................................... 376
15.6.69 MMC Receive Watchdog Error Frame Counter Register
(RXWATCHDOGERROR)—Offset 1DCh ..................................................... 377
15.6.70 MMC Receive Error Frame Counter Register (RXRCVERROR)—Offset 1E0h .. 377
15.6.71 MMC Receive Control Frame Counter Register (RXCTRLFRAMES_G)—Offset
1E4h .................................................................................................. 378
15.6.72 MMC IPC Receive Checksum Offload Interrupt Mask Register
(MMC_IPC_INTR_MASK_RX)—Offset 200h ............................................... 378
15.6.73 MMC Receive Checksum Offload Interrupt Register
(MMC_IPC_INTR_RX)—Offset 208h ......................................................... 380
15.6.74 MMC Receive IPV4 Good Frame Counter Register
(RXIPV4_GD_FRMS)—Offset 210h .......................................................... 382
15.6.75 MMC Receive IPV4 Header Error Frame Counter Register
(RXIPV4_HDRERR_FRMS)—Offset 214h ................................................... 383
15.6.76 MMC Receive IPV4 No Payload Frame Counter Register
(RXIPV4_NOPAY_FRMS)—Offset 218h ..................................................... 383
15.6.77 MMC Receive IPV4 Fragmented Frame Counter Register
(RXIPV4_FRAG_FRMS)—Offset 21Ch ....................................................... 384
15.6.78 MMC Receive IPV4 UDP Checksum Disabled Frame Counter Register
(RXIPV4_UDSBL_FRMS)—Offset 220h ..................................................... 384
15.6.79 MMC Receive IPV6 Good Frame Counter Register
(RXIPV6_GD_FRMS)—Offset 224h .......................................................... 384
15.6.80 MMC Receive IPV6 Header Error Frame Counter Register
(RXIPV6_HDRERR_FRMS)—Offset 228h ................................................... 385
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15.6.81 MMC Receive IPV6 No Payload Frame Counter Register
(RXIPV6_NOPAY_FRMS)—Offset 22Ch ..................................................... 385
15.6.82 MMC Receive UDP Good Frame Counter Register (RXUDP_GD_FRMS)—Offset
230h ................................................................................................... 386
15.6.83 MMC Receive UDP Error Frame Counter Register
(RXUDP_ERR_FRMS)—Offset 234h .......................................................... 386
15.6.84 MMC Receive TCP Good Frame Counter Register (RXTCP_GD_FRMS)—Offset
238h ................................................................................................... 387
15.6.85 MMC Receive TCP Error Frame Counter Register (RXTCP_ERR_FRMS)—Offset
23Ch................................................................................................... 387
15.6.86 MMC Receive ICMP Good Frame Counter Register
(RXICMP_GD_FRMS)—Offset 240h .......................................................... 388
15.6.87 MMC Receive ICMP Error Frame Counter Register
(RXICMP_ERR_FRMS)—Offset 244h......................................................... 388
15.6.88 MMC Receive IPV4 Good Octet Counter Register
(RXIPV4_GD_OCTETS)—Offset 250h ....................................................... 388
15.6.89 MMC Receive IPV4 Header Error Octet Counter Register
(RXIPV4_HDRERR_OCTETS)—Offset 254h ................................................ 389
15.6.90 MMC Receive IPV4 No Payload Octet Counter Register
(RXIPV4_NOPAY_OCTETS)—Offset 258h .................................................. 389
15.6.91 MMC Receive IPV4 Fragmented Octet Counter Register
(RXIPV4_FRAG_OCTETS)—Offset 25Ch .................................................... 390
15.6.92 MMC Receive IPV4 UDP Checksum Disabled Octet Counter Register
(RXIPV4_UDSBL_OCTETS)—Offset 260h .................................................. 390
15.6.93 MMC Receive IPV6 Good Octet Counter Register
(RXIPV6_GD_OCTETS)—Offset 264h ....................................................... 391
15.6.94 MMC Receive IPV6 Good Octet Counter Register (RXIPV6_HDRERR_OCTETS)—
Offset 268h.......................................................................................... 391
15.6.95 MMC Receive IPV6 Header Error Octet Counter Register
(RXIPV6_NOPAY_OCTETS)—Offset 26Ch .................................................. 392
15.6.96 MMC Receive IPV6 No Payload Octet Counter Register (RXUDP_GD_OCTETS)—
Offset 270h.......................................................................................... 392
15.6.97 MMC Receive UDP Good Octet Counter Register
(RXUDP_ERR_OCTETS)—Offset 274h....................................................... 392
15.6.98 MMC Receive TCP Good Octet Counter Register
(RXTCP_GD_OCTETS)—Offset 278h ........................................................ 393
15.6.99 MMC Receive TCP Error Octet Counter Register
(RXTCP_ERR_OCTETS)—Offset 27Ch ....................................................... 393
15.6.100 MMC Receive ICMP Good Octet Counter Register
(RXICMP_GD_OCTETS)—Offset 280h....................................................... 394
15.6.101 MMC Receive ICMP Error Octet Counter Register
(RXICMP_ERR_OCTETS)—Offset 284h ..................................................... 394
15.6.102 VLAN Tag Inclusion or Replacement Register (Register 353)
(GMAC_REG_353)—Offset 584h.............................................................. 395
15.6.103 VLAN Hash Table Register (Register 354) (GMAC_REG_354)—Offset 588h 396
15.6.104 Timestamp Control Register (Register 448)
(GMAC_REG_448)—Offset 700h ......................................................... 396
15.6.105 Sub-Second Increment Register (Register 449) (GMAC_REG_449)—Offset
704h ................................................................................................... 398
15.6.106 System Time - Seconds Register (Register 450) (GMAC_REG_450)—Offset
708h ................................................................................................... 398
15.6.107 System Time - Nanoseconds Register (Register 451)
(GMAC_REG_451)—Offset 70Ch ............................................................. 399
15.6.108 System Time - Seconds Update Register (Register 452) (GMAC_REG_452)—
Offset 710h.......................................................................................... 399
15.6.109 System Time - Nanoseconds Update Register (Register 453)
(GMAC_REG_453)—Offset 714h.............................................................. 400
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15.7
15.6.110 Timestamp Addend Register (Register 454)
(GMAC_REG_454)—Offset 718h ......................................................... 400
15.6.111 Target Time Seconds Register (Register 455) (GMAC_REG_455)—Offset
71Ch .................................................................................................. 401
15.6.112 Target Time Nanoseconds Register (Register 456)
(GMAC_REG_456)—Offset 720h ............................................................. 401
15.6.113 System Time - Higher Word Seconds Register (Register 457)
(GMAC_REG_457)—Offset 724h ............................................................. 402
15.6.114 Timestamp Status Register (Register 458)
(GMAC_REG_458)—Offset 728h.......................................................... 403
15.6.115 Bus Mode Register (Register 0) (DMA_REG_0)—Offset 1000h ................. 404
15.6.116 Transmit Poll Demand Register (Register 1) (DMA_REG_1)—Offset 1004h 406
15.6.117 Receive Poll Demand Register (Register 2) (DMA_REG_2)—Offset 1008h.. 406
15.6.118 Receive Descriptor List Address Register (Register 3) (DMA_REG_3)—Offset
100Ch ................................................................................................ 407
15.6.119 Transmit Descriptor List Address Register (Register 4)
(DMA_REG_4)—Offset 1010h ................................................................. 407
15.6.120 Status Register (Register 5) (DMA_REG_5)—Offset 1014h...................... 408
15.6.121 Operation Mode Register (Register 6) (DMA_REG_6)—Offset 1018h......... 411
15.6.122 Interrupt Enable Register (Register 7) (DMA_REG_7)—Offset 101Ch........ 414
15.6.123 Missed Frame and Buffer Overflow Counter Register (Register 8)
(DMA_REG_8)—Offset 1020h ................................................................. 415
15.6.124 Receive Interrupt Watchdog Timer Register (Register 9)
(DMA_REG_9)—Offset 1024h ................................................................. 416
15.6.125 AHB Status Register (Register 11) (DMA_REG_11)—Offset 102Ch ........... 416
15.6.126 Current Host Transmit Descriptor Register (Register 18)
(DMA_REG_18)—Offset 1048h ............................................................... 417
15.6.127 Current Host Receive Descriptor Register (Register 19)
(DMA_REG_19)—Offset 104Ch ............................................................... 417
15.6.128 Current Host Transmit Buffer Address Register (Register 20)
(DMA_REG_20)—Offset 1050h ............................................................... 418
15.6.129 Current Host Receive Buffer Address Register (Register 21) (DMA_REG_21)—
Offset 1054h ....................................................................................... 418
15.6.130 HW Feature Register (Register 22) (DMA_REG_22)—Offset 1058h ........... 419
MAC Descriptor Details..................................................................................... 421
15.7.1 Descriptor Overview ............................................................................. 421
15.7.2 Descriptor Endianness .......................................................................... 421
15.7.3 Transmit Descriptor ............................................................................. 421
15.7.4 Receive Descriptor ............................................................................... 427
16.0 USB 2.0 ................................................................................................................. 435
16.1 Signal Descriptions .......................................................................................... 435
16.2 Features ........................................................................................................ 435
16.2.1 USB2.0 Host Controller Features ............................................................ 435
16.2.2 USB2.0 Device Features ........................................................................ 436
16.3 References ..................................................................................................... 436
16.4 Register Map .................................................................................................. 437
16.5 PCI Configuration Registers .............................................................................. 437
16.5.1 USB Device ......................................................................................... 437
16.5.1.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 438
16.5.1.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 439
16.5.1.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 439
16.5.1.4 Status Register (STATUS)—Offset 6h......................................... 440
16.5.1.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 440
16.5.1.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 441
16.5.1.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 441
16.5.1.8 Header Type (HEADER_TYPE)—Offset Eh ................................... 442
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16.5.1.9 BIST (BIST)—Offset Fh ............................................................ 442
16.5.1.10 Base Address Register (BAR0)—Offset 10h ............................... 443
16.5.1.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ....... 443
16.5.1.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch........ 444
16.5.1.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ................................ 444
16.5.1.14 Expansion ROM Base Address
(EXP_ROM_BASE_ADR)—Offset 30h ........................................ 444
16.5.1.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ........................ 445
16.5.1.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch ....................... 445
16.5.1.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh .......................... 446
16.5.1.18 MIN_GNT (MIN_GNT)—Offset 3Eh ............................................ 446
16.5.1.19 MAX_LAT (MAX_LAT)—Offset 3Fh ............................................ 446
16.5.1.20 Capability ID (PM_CAP_ID)—Offset 80h .................................... 447
16.5.1.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ............. 447
16.5.1.22 Power Management Capabilities (PMC)—Offset 82h .................... 447
16.5.1.23 Power Management Control/Status Register (PMCSR)—Offset 84h 448
16.5.1.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h ....................................................................................... 449
16.5.1.25 Power Management Data Register (DATA_REGISTER)—Offset 87h 449
16.5.1.26 Capability ID (MSI_CAP_ID)—Offset A0h .................................. 450
16.5.1.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........... 450
16.5.1.28 Message Control (MESSAGE_CTRL)—Offset A2h ......................... 450
16.5.1.29 Message Address (MESSAGE_ADDR)—Offset A4h ....................... 451
16.5.1.30 Message Data (MESSAGE_DATA)—Offset A8h ............................ 451
16.5.1.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ....................... 452
16.5.1.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h .................... 452
16.5.2 USB EHCI ............................................................................................ 453
16.5.2.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 454
16.5.2.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 454
16.5.2.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 454
16.5.2.4 Status Register (STATUS)—Offset 6h ......................................... 455
16.5.2.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 456
16.5.2.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 456
16.5.2.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 457
16.5.2.8 Header Type (HEADER_TYPE)—Offset Eh .................................... 457
16.5.2.9 BIST (BIST)—Offset Fh ............................................................ 457
16.5.2.10 Base Address Register (BAR0)—Offset 10h ............................... 458
16.5.2.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ....... 459
16.5.2.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ....... 459
16.5.2.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ................................ 459
16.5.2.14 Expansion ROM Base Address
(EXP_ROM_BASE_ADR)—Offset 30h ........................................ 460
16.5.2.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ....................... 460
16.5.2.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch....................... 460
16.5.2.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh.......................... 461
16.5.2.18 MIN_GNT (MIN_GNT)—Offset 3Eh ........................................... 461
16.5.2.19 MAX_LAT (MAX_LAT)—Offset 3Fh............................................ 462
16.5.2.20 Serial Bus Release Number Register (SBRN)—Offset 60h ............ 462
16.5.2.21 Frame Length Adjustment Register (FLADJ)—Offset 61h............. 462
16.5.2.22 Capability ID (PM_CAP_ID)—Offset 80h ................................... 463
16.5.2.23 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ............ 463
16.5.2.24 Power Management Capabilities (PMC)—Offset 82h.................... 463
16.5.2.25 Power Management Control/Status Register
(PMCSR)—Offset 84h............................................................. 464
16.5.2.26 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h ....................................................................................... 465
16.5.2.27 Power Management Data Register
(DATA_REGISTER)—Offset 87h ............................................... 465
16.5.2.28 Capability ID (MSI_CAP_ID)—Offset A0h .................................. 465
16.5.2.29 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h........... 466
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16.6
16.5.2.30 Message Control (MESSAGE_CTRL)—Offset A2h........................ 466
16.5.2.31 Message Address (MESSAGE_ADDR)—Offset A4h...................... 467
16.5.2.32 Message Data (MESSAGE_DATA)—Offset A8h........................... 467
16.5.2.33 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ...................... 468
16.5.2.34 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h................... 468
16.5.2.35 USB Legacy Support Extended Capability (USBLEGSUP)—Offset
C0h ...................................................................................... 468
16.5.2.36 USB Legacy Support Control/Status
(USBLEGCTLSTS)—Offset C4h ................................................ 469
16.5.3 USB OHCI ........................................................................................... 471
16.5.3.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 472
16.5.3.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 472
16.5.3.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 473
16.5.3.4 Status Register (STATUS)—Offset 6h......................................... 473
16.5.3.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 474
16.5.3.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 475
16.5.3.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 475
16.5.3.8 Header Type (HEADER_TYPE)—Offset Eh ................................... 475
16.5.3.9 BIST (BIST)—Offset Fh ............................................................ 476
16.5.3.10 Base Address Register (BAR0)—Offset 10h ............................... 476
16.5.3.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ....... 477
16.5.3.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch........ 477
16.5.3.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ................................ 478
16.5.3.14 Expansion ROM Base Address
(EXP_ROM_BASE_ADR)—Offset 30h ........................................ 478
16.5.3.15 Capabilities Pointer (CAP_POINTER)—Offset 34h........................ 479
16.5.3.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch ....................... 479
16.5.3.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh .......................... 479
16.5.3.18 MIN_GNT (MIN_GNT)—Offset 3Eh ........................................... 480
16.5.3.19 MAX_LAT (MAX_LAT)—Offset 3Fh ............................................ 480
16.5.3.20 Capability ID (PM_CAP_ID)—Offset 80h.................................... 480
16.5.3.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ............ 481
16.5.3.22 Power Management Capabilities (PMC)—Offset 82h.................... 481
16.5.3.23 Power Management Control/Status Register (PMCSR)—Offset 84h 482
16.5.3.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h....................................................................................... 483
16.5.3.25 Power Management Data Register (DATA_REGISTER)—Offset 87h 483
16.5.3.26 Capability ID (MSI_CAP_ID)—Offset A0h .................................. 483
16.5.3.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........... 484
16.5.3.28 Message Control (MESSAGE_CTRL)—Offset A2h ........................ 484
16.5.3.29 Message Address (MESSAGE_ADDR)—Offset A4h ...................... 484
16.5.3.30 Message Data (MESSAGE_DATA)—Offset A8h ........................... 485
16.5.3.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ....................... 485
16.5.3.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................... 486
Memory Mapped Registers ................................................................................ 486
16.6.1 USB Device ......................................................................................... 486
16.6.1.1 IN Endpoint 0 Control Register (ep0_in_ctrl_udc_reg)—Offset 0h .. 489
16.6.1.2 IN Endpoint 0 Status Register (ep0_in_sts_udc_reg)—Offset 4h .... 490
16.6.1.3 IN Endpoint 0 Buffer Size Register
(ep0_in_bufsize_udc_reg)—Offset 8h ........................................ 492
16.6.1.4 IN Endpoint 0 Maximum Packet Size Register
(ep0_in_mpkt_sz_reg)—Offset Ch............................................. 493
16.6.1.5 IN Endpoint 0 Data Descriptor Pointer Register
(ep0_in_desptr_udc_reg)—Offset 14h ....................................... 493
16.6.1.6 IN Endpoint 0 Write Confirmation register (for Slave-Only mode)
(ep0_wr_cfrm_udc_reg)—Offset 1Ch ......................................... 494
16.6.1.7 IN Endpoint 1 Control Register (ep1_in_ctrl_udc_reg)—Offset 20h 494
16.6.1.8 IN Endpoint 1 Status Register (ep1_in_sts_udc_reg)—Offset 24h .. 495
16.6.1.9 IN Endpoint 1 Buffer Size Register
(ep1_in_bufsize_udc_reg)—Offset 28h....................................... 497
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16.6.1.10 IN Endpoint 1 Maximum Packet Size Register
(ep1_in_mpkt_sz_reg)—Offset 2Ch ........................................... 498
16.6.1.11 IN Endpoint 1 Data Descriptor Pointer Register
(ep1_in_desptr_udc_reg)—Offset 34h ........................................ 498
16.6.1.12 IN Endpoint 1 Write Confirmation register (for Slave-Only mode)
(ep1_wr_cfrm_udc_reg)—Offset 3Ch ......................................... 499
16.6.1.13 IN Endpoint 2 Control Register (ep2_in_ctrl_udc_reg)—Offset 40h499
16.6.1.14 IN Endpoint 2 Status Register (ep2_in_sts_udc_reg)—Offset 44h . 500
16.6.1.15 IN Endpoint 2 Buffer Size Register
(ep2_in_bufsize_udc_reg)—Offset 48h ....................................... 502
16.6.1.16 IN Endpoint 2 Maximum Packet Size Register
(ep2_in_mpkt_sz_reg)—Offset 4Ch ........................................... 503
16.6.1.17 IN Endpoint 2 Data Descriptor Pointer Register
(ep2_in_desptr_udc_reg)—Offset 54h ........................................ 503
16.6.1.18 IN Endpoint 2 Write Confirmation register (for Slave-Only mode)
(ep2_wr_cfrm_udc_reg)—Offset 5Ch ......................................... 504
16.6.1.19 IN Endpoint 3 Control Register (ep3_in_ctrl_udc_reg)—Offset 60h504
16.6.1.20 IN Endpoint 3 Status Register (ep3_in_sts_udc_reg)—Offset 64h . 505
16.6.1.21 IN Endpoint 3 Buffer Size Register
(ep3_in_bufsize_udc_reg)—Offset 68h ....................................... 507
16.6.1.22 IN Endpoint 3 Maximum Packet Size Register
(ep3_in_mpkt_sz_reg)—Offset 6Ch ........................................... 508
16.6.1.23 IN Endpoint 3 Data Descriptor Pointer Register
(ep3_in_desptr_udc_reg)—Offset 74h ........................................ 508
16.6.1.24 IN Endpoint 3 Write Confirmation register (for Slave-Only mode)
(ep3_wr_cfrm_udc_reg)—Offset 7Ch ......................................... 509
16.6.1.25 OUT Endpoint 0 Control Register (ep0_out_ctrl_udc_reg)—Offset
200h ..................................................................................... 509
16.6.1.26 OUT Endpoint 0 Status Register (ep0_out_sts_udc_reg)—Offset
204h ..................................................................................... 510
16.6.1.27 OUT Endpoint 0 Receive Packet Frame Number Register
(ep0_out_rpf_udc_reg)—Offset 208h ......................................... 512
16.6.1.28 OUT Endpoint 0 Buffer Size Register (ep0_out_bufsize_udc_reg)—
Offset 20Ch ............................................................................ 513
16.6.1.29 OUT Endpoint 0 SETUP Buffer Pointer Register
(ep0_subptr_udc_reg)—Offset 210h .......................................... 513
16.6.1.30 OUT Endpoint 0 Data Descriptor Pointer Register
(ep0_out_desptr_udc_reg)—Offset 214h .................................... 514
16.6.1.31 OUT Endpoint 0 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep0_rd_cfrm_udc_reg)—Offset 21Ch . 514
16.6.1.32 OUT Endpoint 1 Control Register (ep1_out_ctrl_udc_reg)—Offset
220h ..................................................................................... 515
16.6.1.33 OUT Endpoint 1 Status Register (ep1_out_sts_udc_reg)—Offset
224h ..................................................................................... 516
16.6.1.34 OUT Endpoint 1 Receive Packet Frame Number Register
(ep1_out_rpf_udc_reg)—Offset 228h ......................................... 518
16.6.1.35 OUT Endpoint 1 Buffer Size Register (ep1_out_bufsize_udc_reg)—
Offset 22Ch ............................................................................ 519
16.6.1.36 OUT Endpoint 1 SETUP Buffer Pointer Register
(ep1_subptr_udc_reg)—Offset 230h .......................................... 519
16.6.1.37 OUT Endpoint 1 Data Descriptor Pointer Register
(ep1_out_desptr_udc_reg)—Offset 234h .................................... 520
16.6.1.38 OUT Endpoint 1 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep1_rd_cfrm_udc_reg)—Offset 23Ch . 520
16.6.1.39 OUT Endpoint 2 Control Register (ep2_out_ctrl_udc_reg)—Offset
240h ..................................................................................... 521
16.6.1.40 OUT Endpoint 2 Status Register (ep2_out_sts_udc_reg)—Offset
244h ..................................................................................... 522
16.6.1.41 OUT Endpoint 2 Receive Packet Frame Number Register
(ep2_out_rpf_udc_reg)—Offset 248h ......................................... 524
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16.6.1.42 OUT Endpoint 2 Buffer Size Register (ep2_out_bufsize_udc_reg)—
Offset 24Ch ........................................................................... 525
16.6.1.43 OUT Endpoint 2 SETUP Buffer Pointer Register
(ep2_subptr_udc_reg)—Offset 250h .......................................... 525
16.6.1.44 OUT Endpoint 2 Data Descriptor Pointer Register
(ep2_out_desptr_udc_reg)—Offset 254h.................................... 526
16.6.1.45 OUT Endpoint 2 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep2_rd_cfrm_udc_reg)—Offset 25Ch. 526
16.6.1.46 OUT Endpoint 3 Control Register (ep3_out_ctrl_udc_reg)—Offset
260h ..................................................................................... 527
16.6.1.47 OUT Endpoint 3 Status Register (ep3_out_sts_udc_reg)—Offset
264h ..................................................................................... 528
16.6.1.48 OUT Endpoint 3 Receive Packet Frame Number Register
(ep3_out_rpf_udc_reg)—Offset 268h......................................... 530
16.6.1.49 OUT Endpoint 3 Buffer Size Register (ep3_out_bufsize_udc_reg)—
Offset 26Ch ........................................................................... 531
16.6.1.50 OUT Endpoint 3 SETUP Buffer Pointer Register
(ep3_subptr_udc_reg)—Offset 270h .......................................... 531
16.6.1.51 OUT Endpoint 3 Data Descriptor Pointer Register
(ep3_out_desptr_udc_reg)—Offset 274h.................................... 532
16.6.1.52 OUT Endpoint 3 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep3_rd_cfrm_udc_reg)—Offset 27Ch. 532
16.6.1.53 Device Configuration Register (d_cfg_udc_reg)—Offset 400h ...... 533
16.6.1.54 Device Control Register (d_ctrl_udc_reg)—Offset 404h .............. 534
16.6.1.55 Device Status Register (d_sts_udc_reg)—Offset 408h................ 536
16.6.1.56 Device Interrupt Register (d_intr_udc_reg)—Offset 40Ch ........... 537
16.6.1.57 Device Interrupt Mask Register (d_intr_msk_udc_reg)—Offset
410h ..................................................................................... 538
16.6.1.58 Endpoints Interrupt Register (ep_intr_udc_reg)—Offset 414h ..... 539
16.6.1.59 Endpoints Interrupt Mask Register (ep_intr_msk_udc_reg)—Offset
418h ..................................................................................... 539
16.6.1.60 Test Mode Register (test_mode_udc_reg)—Offset 41Ch ............. 540
16.6.1.61 Product Release Number Register
(revision_udc_reg)—Offset 420h............................................. 541
16.6.1.62 SETUP command address pointer register
(udc_desc_addr_udc_reg)—Offset 500h..................................... 541
16.6.1.63 Physical Endpoint 0 Register
(udc_ep_ne_udc_reg_0)—Offset 504h ..................................... 542
16.6.1.64 Physical Endpoint 1 Register
(udc_ep_ne_udc_reg_1)—Offset 508h ..................................... 542
16.6.1.65 Physical Endpoint 2 Register (udc_ep_ne_udc_reg_2)—Offset
50Ch..................................................................................... 543
16.6.1.66 Physical Endpoint 3 Register
(udc_ep_ne_udc_reg_3)—Offset 510h ..................................... 544
16.6.1.67 Physical Endpoint 4 Register
(udc_ep_ne_udc_reg_4)—Offset 514h ..................................... 545
16.6.1.68 Physical Endpoint 5 Register
(udc_ep_ne_udc_reg_5)—Offset 518h ..................................... 546
16.6.1.69 Physical Endpoint 6 Register (udc_ep_ne_udc_reg_6)—Offset
51Ch..................................................................................... 546
16.6.1.70 RxFIFO Array[0-511] (udc_rx_fifo_reg_array[0-511])—Offset
800h, Count 512, Stride 4h ...................................................... 547
16.6.1.71 TxFIFO 0 Array[0-255] (udc_tx_fifo_reg_0_array[0-255])—Offset
1000h, Count 256, Stride 4h .................................................... 548
16.6.1.72 TxFIFO 1 Array[0-255] (udc_tx_fifo_reg_1_array[0-255])—Offset
1400h, Count 256, Stride 4h .................................................... 548
16.6.1.73 TxFIFO 2 Array[0-255] (udc_tx_fifo_reg_2_array[0-255])—Offset
1800h, Count 256, Stride 4h .................................................... 548
16.6.1.74 TxFIFO 3 Array[0-255] (udc_tx_fifo_reg_3_array[0-255])—Offset
1C00h, Count 256, Stride 4h .................................................... 549
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16.6.2 USB EHCI ............................................................................................ 549
16.6.2.1 Host Controller Interface Version Number and Capability Registers
Length (HCCAPBASE)—Offset 0h ............................................... 550
16.6.2.2 Host Controller Structural Parameters (HCSPARAMS)—Offset 4h .... 550
16.6.2.3 Host Controller Capability Parameters (HCCPARAMS)—Offset 8h .... 552
16.6.2.4 USB Command (USBCMD)—Offset 10h....................................... 553
16.6.2.5 USB Status (USBSTS)—Offset 14h ............................................. 555
16.6.2.6 USB Interrupt Enable (USBINTR)—Offset 18h.............................. 557
16.6.2.7 USB Frame Index (FRINDEX)—Offset 1Ch................................... 558
16.6.2.8 4 Gigabyte Memory Segment Selector (CTRLDSSEGMENT)—Offset
20h ....................................................................................... 559
16.6.2.9 Periodic Frame List Base Address (PERIODICLISTBASE)—Offset
24h ....................................................................................... 559
16.6.2.10 Asynchronous List Address (ASYNCLISTADDR)—Offset 28h ......... 560
16.6.2.11 Configure Flag (CONFIGFLAG)—Offset 50h................................ 560
16.6.2.12 Port Status/Control[0-1] (PORTSC[0-1])—Offset 54h, Count 2,
Stride 4h................................................................................ 561
16.6.2.13 Programmable Microframe Base Value (INSNREG00)—Offset 90h. 564
16.6.2.14 Programmable Packet Buffer OUT/IN Thresholds
(INSNREG01)—Offset 94h ........................................................ 565
16.6.2.15 Programmable Packet Buffer Depth (INSNREG02)—Offset 98h..... 565
16.6.2.16 Programmable Controller Settings (INSNREG03)—Offset 9Ch ...... 566
16.6.2.17 Programmable Controller Settings (INSNREG04)—Offset A0h ...... 567
16.6.2.18 UTMI Configuration (INSNREG05)—Offset A4h........................... 568
16.6.3 USB OHCI............................................................................................ 569
16.6.3.1 OHCI Revision (HCREVISION)—Offset 0h.................................... 570
16.6.3.2 Host Controller Control (HCCONTROL)—Offset 4h ........................ 570
16.6.3.3 Host Controller Command Status (HCCMDSTATUS)—Offset 8h ...... 571
16.6.3.4 Host Controller Interrupt Status (HCINTRSTATUS)—Offset Ch ....... 573
16.6.3.5 Host Controller Interrupt Enable (HCINTRENABLE)—Offset 10h...... 574
16.6.3.6 Host Controller Interrupt Disable (HCINTRDISABLE)—Offset 14h ... 575
16.6.3.7 Host Controller Communication Area (HCHCCA)—Offset 18h ......... 576
16.6.3.8 Host Controller Current Isochronous or Interrupt Endpoint
(HCPRDCURED)—Offset 1Ch ..................................................... 577
16.6.3.9 Host Controller Current First Control Endpoint (HCCTRLHEADED)—
Offset 20h .............................................................................. 577
16.6.3.10 Host Controller Current Control Endpoint (HCCTRLCURED)—Offset
24h ....................................................................................... 578
16.6.3.11 Host Controller First Bulk Endpoint (HCBULKHEADED)—Offset 28h578
16.6.3.12 Host Controller Current Bulk Endpoint (HCBULKCURED)—Offset
2Ch ....................................................................................... 579
16.6.3.13 Host Controller Last Completed Descriptor (HCDONEHEAD)—Offset
30h ....................................................................................... 580
16.6.3.14 Host Controller Frame Interval (HCFMINTERVAL)—Offset 34h ...... 580
16.6.3.15 Host Controller Remaining Frame (HCFMREMAINING)—Offset 38h 581
16.6.3.16 Host Controller Frame Number (HCFMNUMBER)—Offset 3Ch........ 582
16.6.3.17 Host Controller Periodic List Start (HCPERIODICSTART)—Offset
40h ....................................................................................... 583
16.6.3.18 Host Controller LS Threshold (HCLSTHRESHOLD)—Offset 44h ...... 583
16.6.3.19 Host Controller Root Hub Descriptor A (HCRHDESPA)—Offset 48h 584
16.6.3.20 Host Controller Root Hub Descriptor B (HCRHDESPB)—Offset 4Ch 585
16.6.3.21 Host Controller Root Hub Status (HCRHSTATUS)—Offset 50h....... 586
16.6.3.22 Host Controller Root Hub Port Status (HCRHPORTSTS)—Offset 54h ...
587
17.0 SDIO/SD/eMMC ..................................................................................................... 591
17.1 Signal Descriptions .......................................................................................... 591
17.2 Features ......................................................................................................... 592
17.2.1 SDIO/SD/eMMC Features ....................................................................... 592
17.2.2 SD 3.0/ SDIO 3.0 / eMMC 4.41 Interfaces ................................................ 592
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17.3
17.4
17.5
17.6
17.2.2.1 SD 3.0 Bus Topology ............................................................... 592
17.2.2.2 SDIO 3.0 Interface.................................................................. 593
17.2.2.3 eMMC Interface ...................................................................... 594
17.2.3 SDIO/SD/eMMC Host Controller.............................................................. 594
17.2.3.1 SD DMA................................................................................. 595
References ..................................................................................................... 595
Register Map .................................................................................................. 595
PCI Configuration Registers .............................................................................. 596
17.5.1 Vendor ID (VENDOR_ID)—Offset 0h ....................................................... 597
17.5.2 Device ID (DEVICE_ID)—Offset 2h ......................................................... 598
17.5.3 Command Register (COMMAND_REGISTER)—Offset 4h ............................. 598
17.5.4 Status Register (STATUS)—Offset 6h ...................................................... 599
17.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h ................. 599
17.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ...................................... 600
17.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 600
17.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 601
17.5.9 BIST (BIST)—Offset Fh ......................................................................... 601
17.5.10 Base Address Register (BAR0)—Offset 10h ............................................. 602
17.5.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h..................... 602
17.5.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 603
17.5.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh.............................................. 603
17.5.14 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h ............ 603
17.5.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 604
17.5.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 604
17.5.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 605
17.5.18 MIN_GNT (MIN_GNT)—Offset 3Eh ......................................................... 605
17.5.19 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 605
17.5.20 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 606
17.5.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .......................... 606
17.5.22 Power Management Capabilities (PMC)—Offset 82h ................................. 606
17.5.23 Power Management Control/Status Register (PMCSR)—Offset 84h ............. 607
17.5.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h.... 608
17.5.25 Power Management Data Register (DATA_REGISTER)—Offset 87h............. 608
17.5.26 Capability ID (MSI_CAP_ID)—Offset A0h ............................................... 609
17.5.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 609
17.5.28 Message Control (MESSAGE_CTRL)—Offset A2h ...................................... 609
17.5.29 Message Address (MESSAGE_ADDR)—Offset A4h .................................... 610
17.5.30 Message Data (MESSAGE_DATA)—Offset A8h ......................................... 610
17.5.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 611
17.5.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................................. 611
Memory Mapped Registers ................................................................................ 612
17.6.1 SDMA System Address Register (SYS_ADR)—Offset 0h.............................. 613
17.6.2 Block Size Register (BLK_SIZE)—Offset 4h .............................................. 614
17.6.3 Block Count Register (BLK_COUNT)—Offset 6h......................................... 615
17.6.4 Argument Register (ARGUMENT)—Offset 8h............................................. 616
17.6.5 Transfer Mode Register (TX_MODE)—Offset Ch......................................... 616
17.6.6 Command Register (CMD)—Offset Eh...................................................... 618
17.6.7 Response Register 0 (RESPONSE0)—Offset 10h........................................ 619
17.6.8 Response Register 2 (RESPONSE2)—Offset 14h........................................ 620
17.6.9 Response Register 4 (RESPONSE4)—Offset 18h........................................ 620
17.6.10 Response Register 6 (RESPONSE6)—Offset 1Ch ...................................... 621
17.6.11 Buffer Data Port Register (BUF_DATA_PORT)—Offset 20h......................... 621
17.6.12 Present State Register (PRE_STATE)—Offset 24h .................................... 622
17.6.13 Host Control Register (HOST_CTL)—Offset 28h ....................................... 627
17.6.14 Power Control Register (PWR_CTL)—Offset 29h ...................................... 628
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17.6.15
17.6.16
17.6.17
17.6.18
17.6.19
17.6.20
17.6.21
17.6.22
17.6.23
17.6.24
17.6.25
17.6.26
17.6.27
17.6.28
17.6.29
17.6.30
Block Gap Control Register (BLK_GAP_CTL)—Offset 2Ah ........................... 628
Clock Control Register (CLK_CTL)—Offset 2Ch......................................... 630
Timeout Control Register (TIMEOUT_CTL)—Offset 2Eh.............................. 632
Software Reset Register (SW_RST)—Offset 2Fh ....................................... 633
Normal Interrupt Status Register (NML_INT_STATUS)—Offset 30h ............. 634
Error Interrupt Status Register (ERR_INT_STATUS)—Offset 32h ................ 636
Normal Interrupt Status Enable (NRM_INT_STATUS_EN)—Offset 34h ......... 638
Error Interrupt Status Enable Register (ERR_INT_STAT_EN)—Offset 36h .... 639
Normal Interrupt Signal Enable Register (NRM_INT_SIG_EN)—Offset 38h ... 640
Error Interrupt Signal Enable Register (ERR_INT_SIG_EN)—Offset 3Ah....... 642
Auto CMD12 Error Status Register (CMD12_ERR_STAT)—Offset 3Ch .......... 643
Host Control 2 Register (HOST_CTRL_2)—Offset 3Eh ............................... 644
Capabilities Register (CAPABILITIES)—Offset 40h .................................... 645
Capabilities Register 2 (CAPABILITIES_2)—Offset 44h .............................. 647
Maximum Current Capabilities Register (MAX_CUR_CAP)—Offset 48h ......... 648
Force Event Register for Auto CMD12 Error Status
(FORCE_EVENT_CMD12_ERR_STAT)—Offset 50h ...................................... 649
17.6.31 Force Event Register for Error Interrupt Status
(FORCE_EVENT_ERR_INT_STAT)—Offset 52h ........................................... 650
17.6.32 ADMA Error Status Register (ADMA_ERR_STAT)—Offset 54h ..................... 651
17.6.33 ADMA System Address Register (ADMA_SYS_ADDR)—Offset 58h ............... 652
17.6.34 initialization Preset Values Register (3.3v or 1.8v)
(PRESET_VALUE_0)—Offset 60h ............................................................. 653
17.6.35 Default Speed Preset Values Register (PRESET_VALUE_1)—Offset 62h ....... 653
17.6.36 High Speed Preset Values Register (PRESET_VALUE_2)—Offset 64h ........... 654
17.6.37 SDR12 Preset Values Register (PRESET_VALUE_3)—Offset 66h ................. 654
17.6.38 SDR25 Preset Values Register (PRESET_VALUE_4)—Offset 68h ................. 655
17.6.39 SDR50 Preset Values Register (PRESET_VALUE_5)—Offset 6Ah ................. 656
17.6.40 SDR104 Preset Values Register (PRESET_VALUE_6)—Offset 6Ch................ 656
17.6.41 DDR50 Preset Values Register (PRESET_VALUE_7)—Offset 6Eh ................. 657
17.6.42 Boot Time-out control register (BOOT_TIMEOUT_CTRL)—Offset 70h........... 658
17.6.43 Debug Selection Register (DEBUG_SEL)—Offset 74h ................................ 658
17.6.44 Shared Bus Control Register (SHARED_BUS)—Offset E0h.......................... 659
17.6.45 SPI Interrupt Support Register (SPI_INT_SUP)—Offset F0h ....................... 660
17.6.46 Slot Interrupt Status Register (SLOT_INT_STAT)—Offset FCh .................... 661
17.6.47 Host Controller Version Register (HOST_CTRL_VER)—Offset FEh................ 661
18.0 High Speed UART ................................................................................................... 663
18.1 Signal Descriptions .......................................................................................... 663
18.2 Features ......................................................................................................... 664
18.2.1 UART Function...................................................................................... 664
18.2.2 Baud Rate Generator............................................................................. 664
18.3 Usage ............................................................................................................ 665
18.3.1 DMA Mode Operation............................................................................. 665
18.3.1.1 Receiver DMA ......................................................................... 665
18.3.1.2 Transmitter DMA ..................................................................... 666
18.3.2 FIFO Interrupt-Mode Operation............................................................... 666
18.3.2.1 Receiver Interrupt ................................................................... 666
18.3.2.2 Transmitter Interrupt............................................................... 666
18.3.3 FIFO Polled-Mode Operation ................................................................... 667
18.3.3.1 Receive Data Service ............................................................... 667
18.3.3.2 Transmit Data Service.............................................................. 667
18.3.4 Autoflow Control................................................................................... 667
18.3.4.1 RTS (UART Output) ................................................................. 667
18.3.4.2 CTS (UART Input) ................................................................... 668
18.4 Register Map................................................................................................... 668
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18.5
18.6
PCI Configuration Registers .............................................................................. 669
18.5.1 Vendor ID (VENDOR_ID)—Offset 0h ....................................................... 669
18.5.2 Device ID (DEVICE_ID)—Offset 2h ......................................................... 670
18.5.3 Command Register (COMMAND_REGISTER)—Offset 4h ............................. 670
18.5.4 Status Register (STATUS)—Offset 6h ...................................................... 671
18.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h ................. 672
18.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ...................................... 672
18.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 673
18.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 673
18.5.9 BIST (BIST)—Offset Fh ......................................................................... 673
18.5.10 Base Address Register (BAR0)—Offset 10h............................................. 674
18.5.11 Base Address Register (BAR1)—Offset 14h............................................. 674
18.5.12 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h .................... 675
18.5.13 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 675
18.5.14 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ............................................. 676
18.5.15 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h............ 676
18.5.16 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 676
18.5.17 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 677
18.5.18 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 677
18.5.19 MIN_GNT (MIN_GNT)—Offset 3Eh......................................................... 678
18.5.20 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 678
18.5.21 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 678
18.5.22 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h.......................... 679
18.5.23 Power Management Capabilities (PMC)—Offset 82h ................................. 679
18.5.24 Power Management Control/Status Register (PMCSR)—Offset 84h............. 680
18.5.25 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ... 681
18.5.26 Power Management Data Register (DATA_REGISTER)—Offset 87h ............ 681
18.5.27 Capability ID (MSI_CAP_ID)—Offset A0h ............................................... 681
18.5.28 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 682
18.5.29 Message Control (MESSAGE_CTRL)—Offset A2h...................................... 682
18.5.30 Message Address (MESSAGE_ADDR)—Offset A4h.................................... 682
18.5.31 Message Data (MESSAGE_DATA)—Offset A8h......................................... 683
18.5.32 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 683
18.5.33 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h................................. 684
Memory Mapped Registers ................................................................................ 684
18.6.1 UART Registers .................................................................................... 684
18.6.1.1 Receive Buffer / Transmit Holding / Divisor Latch Low
(RBR_THR_DLL)—Offset 0h ...................................................... 685
18.6.1.2 Interrupt Enable / Divisor Latch High (IER_DLH)—Offset 4h.......... 685
18.6.1.3 Interrupt Identification / FIFO Control (IIR_FCR)—Offset 8h ......... 686
18.6.1.4 Line Control (LCR)—Offset Ch................................................... 688
18.6.1.5 MODEM Control (MCR)—Offset 10h ........................................... 688
18.6.1.6 Line Status (LSR)—Offset 14h .................................................. 689
18.6.1.7 MODEM Status (MSR)—Offset 18h............................................. 691
18.6.1.8 Scratchpad (SCR)—Offset 1Ch .................................................. 692
18.6.1.9 UART Status (USR)—Offset 7Ch ................................................ 693
18.6.1.10 Halt Transmission (HTX)—Offset A4h....................................... 693
18.6.1.11 DMA Software Acknowledge (DMASA)—Offset A8h .................... 694
18.6.2 DMA Controller Registers....................................................................... 694
18.6.2.1 Channel 0 Source Address (SAR0)—Offset 0h ............................. 696
18.6.2.2 Channel 0 Destination Address (DAR0)—Offset 8h ....................... 696
18.6.2.3 Channel 0 Linked List Pointer (LLP0)—Offset 10h ........................ 697
18.6.2.4 Channel 0 Control LOWER (CTL0_L)—Offset 18h ......................... 697
18.6.2.5 Channel 0 Control UPPER (CTL0_U)—Offset 1Ch.......................... 699
18.6.2.6 Channel 0 Source Status (SSTAT0)—Offset 20h .......................... 700
18.6.2.7 Channel 0 Destination Status (DSTAT0)—Offset 28h .................... 700
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18.6.2.8 Channel 0 Source Status Address (SSTATAR0)—Offset 30h ........... 701
18.6.2.9 Channel 0 Destination Status Address (DSTATAR0)—Offset 38h..... 701
18.6.2.10 Channel 0 Configuration LOWER (CFG0_L)—Offset 40h .............. 702
18.6.2.11 Channel 0 configuration UPPER (CFG0_U)—Offset 44h ............... 703
18.6.2.12 Channel 0 Source Gather (SGR0)—Offset 48h ........................... 704
18.6.2.13 Channel 0 Destination Scatter (DSR0)—Offset 50h ..................... 705
18.6.2.14 Channel 1 Source Address (SAR1)—Offset 58h .......................... 705
18.6.2.15 Channel 1 Destination Address (DAR1)—Offset 60h .................... 706
18.6.2.16 Channel 1 Linked List Pointer (LLP1)—Offset 68h ....................... 706
18.6.2.17 Channel 1 Control LOWER (CTL1_L)—Offset 70h ........................ 707
18.6.2.18 Channel 1 Control UPPER (CTL1_U)—Offset 74h......................... 709
18.6.2.19 Channel 1 Source Status (SSTAT1)—Offset 78h ......................... 710
18.6.2.20 Channel 1 Destination Status (DSTAT1)—Offset 80h................... 710
18.6.2.21 Channel 1 Source Status Address (SSTATAR1)—Offset 88h ......... 711
18.6.2.22 Channel 1 Destination Status Address (DSTATAR1)—Offset 90h ... 711
18.6.2.23 Channel 1 Configuration LOWER (CFG1_L)—Offset 98h ............... 712
18.6.2.24 Channel 1 configuration UPPER (CFG1_U)—Offset 9Ch ................ 713
18.6.2.25 Channel 1 Source Gather (SGR1)—Offset A0h ........................... 714
18.6.2.26 Channel 1 Destination Scatter (DSR1)—Offset A8h ..................... 714
18.6.2.27 Raw Status for IntTfr Interrupt (RAW_TFR)—Offset 2C0h ............ 715
18.6.2.28 Raw Status for IntBlock Interrupt (RAW_BLOCK)—Offset 2C8h .... 715
18.6.2.29 Raw Status for IntSrcTran Interrupt (RAW_SRC_TRAN)—Offset
2D0h ..................................................................................... 716
18.6.2.30 Raw Status for IntDstTran Interrupt (RAW_DST_TRAN)—Offset
2D8h ..................................................................................... 716
18.6.2.31 Raw Status for IntErr Interrupt (RAW_ERR)—Offset 2E0h............ 717
18.6.2.32 Status for IntTfr Interrupt (STATUS_TFR)—Offset 2E8h .............. 717
18.6.2.33 Status for IntBlock Interrupt (STATUS_BLOCK)—Offset 2F0h ....... 718
18.6.2.34 Status for IntSrcTran Interrupt
(STATUS_SRC_TRAN)—Offset 2F8h.......................................... 718
18.6.2.35 Status for IntDstTran Interrupt
(STATUS_DST_TRAN)—Offset 300h.......................................... 719
18.6.2.36 Status for IntErr Interrupt (STATUS_ERR)—Offset 308h .............. 719
18.6.2.37 Mask for IntTfr Interrupt (MASK_TFR)—Offset 310h ................... 720
18.6.2.38 Mask for IntBlock Interrupt (MASK_BLOCK)—Offset 318h............ 720
18.6.2.39 Mask for IntSrcTran Interrupt (MASK_SRC_TRAN)—Offset 320h... 721
18.6.2.40 Mask for IntDstTran Interrupt (MASK_DST_TRAN)—Offset 328h... 722
18.6.2.41 Mask for IntErr Interrupt (MASK_ERR)—Offset 330h................... 722
18.6.2.42 Clear for IntTfr Interrupt (CLEAR_TFR)—Offset 338h .................. 723
18.6.2.43 Clear for IntBlock Interrupt (CLEAR_BLOCK)—Offset 340h........... 723
18.6.2.44 Clear for IntSrcTran Interrupt (CLEAR_SRC_TRAN)—Offset 348h.. 724
18.6.2.45 Clear for IntDstTran Interrupt (CLEAR_DST_TRAN)—Offset 350h . 724
18.6.2.46 Clear for IntErr Interrupt (CLEAR_ERR)—Offset 358h.................. 725
18.6.2.47 Combined Interrupt Status (STATUS_INT)—Offset 360h.............. 725
18.6.2.48 Source Software Transaction Request (REQ_SRC_REG)—Offset
368h ..................................................................................... 726
18.6.2.49 Destination Software Transaction Request register
(REQ_DST_REG)—Offset 370h .................................................. 726
18.6.2.50 Source Single Transaction Request (SGL_REQ_SRC_REG)—Offset
378h ..................................................................................... 727
18.6.2.51 Destination Single Software Transaction Request
(SGL_REQ_DST_REG)—Offset 380h ........................................... 728
18.6.2.52 Source Last Transaction Request (LST_SRC_REG)—Offset 388h ... 728
18.6.2.53 Destination Single Transaction Request (LST_DST_REG)—Offset
390h ..................................................................................... 729
18.6.2.54 DMA Configuration (DMA_CFG_REG)—Offset 398h ..................... 729
18.6.2.55 Channel Enable (CH_EN_REG)—Offset 3A0h.............................. 730
19.0 I2C* Controller/GPIO Controller ............................................................................ 731
19.1 I2C Controller.................................................................................................. 731
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19.2
19.3
19.4
19.5
19.1.1 Signal Descriptions ............................................................................... 731
19.1.2 Features ............................................................................................. 731
19.1.2.1 I2C* Protocol.......................................................................... 731
19.1.2.2 I2C* Modes of Operation.......................................................... 732
19.1.2.3 Functional Description ............................................................. 732
19.1.3 Use .................................................................................................... 737
19.1.3.1 Master Mode Operation............................................................ 737
19.1.3.2 Disabling I2C* Controller.......................................................... 737
19.1.4 References .......................................................................................... 738
GPIO Controller............................................................................................... 738
19.2.1 Signal Descriptions ............................................................................... 738
19.2.2 Features ............................................................................................. 738
Register Map .................................................................................................. 738
PCI Configuration Registers .............................................................................. 739
19.4.1 Vendor ID (VENDOR_ID)—Offset 0h ....................................................... 740
19.4.2 Device ID (DEVICE_ID)—Offset 2h ......................................................... 741
19.4.3 Command Register (COMMAND_REGISTER)—Offset 4h ............................. 741
19.4.4 Status Register (STATUS)—Offset 6h ...................................................... 742
19.4.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h ................. 742
19.4.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ...................................... 743
19.4.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 743
19.4.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 744
19.4.9 BIST (BIST)—Offset Fh ......................................................................... 744
19.4.10 Base Address Register (BAR0)—Offset 10h............................................. 745
19.4.11 Base Address Register (BAR1)—Offset 14h............................................. 745
19.4.12 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h .................... 746
19.4.13 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 746
19.4.14 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ............................................. 747
19.4.15 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h............ 747
19.4.16 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 747
19.4.17 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 748
19.4.18 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 748
19.4.19 MIN_GNT (MIN_GNT)—Offset 3Eh......................................................... 749
19.4.20 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 749
19.4.21 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 749
19.4.22 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h.......................... 750
19.4.23 Power Management Capabilities (PMC)—Offset 82h ................................. 750
19.4.24 Power Management Control/Status Register (PMCSR)—Offset 84h............. 751
19.4.25 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ... 752
19.4.26 Power Management Data Register (DATA_REGISTER)—Offset 87h ............ 752
19.4.27 Capability ID (MSI_CAP_ID)—Offset A0h ............................................... 752
19.4.28 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 753
19.4.29 Message Control (MESSAGE_CTRL)—Offset A2h...................................... 753
19.4.30 Message Address (MESSAGE_ADDR)—Offset A4h.................................... 754
19.4.31 Message Data (MESSAGE_DATA)—Offset A8h......................................... 754
19.4.32 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 754
19.4.33 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h................................. 755
Memory Mapped Registers ................................................................................ 755
19.5.1 I2C* Controller Memory Mapped Registers............................................... 755
19.5.1.1 Control Register (IC_CON)—Offset 0h........................................ 756
19.5.1.2 Master Target Address (IC_TAR)—Offset 4h................................ 757
19.5.1.3 Data Buffer and Command (IC_DATA_CMD)—Offset 10h .............. 758
19.5.1.4 Standard Speed Clock SCL High Count (IC_SS_SCL_HCNT)—Offset
14h....................................................................................... 759
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19.5.1.5 Standard Speed Clock SCL Low Count (IC_SS_SCL_LCNT)—Offset
18h ....................................................................................... 760
19.5.1.6 Fast Speed Clock SCL High Count (IC_FS_SCL_HCNT)—Offset 1Ch 760
19.5.1.7 Fast Speed Clock SCL Low Count (IC_FS_SCL_LCNT)—Offset 20h .. 761
19.5.1.8 Interrupt Status (IC_INTR_STAT)—Offset 2Ch............................. 761
19.5.1.9 Interrupt Mask (IC_INTR_MASK)—Offset 30h .............................. 763
19.5.1.10 Raw Interrupt Status (IC_RAW_INTR_STAT)—Offset 34h ........... 764
19.5.1.11 Receive FIFO Threshold Level (IC_RX_TL)—Offset 38h ............... 766
19.5.1.12 Transmit FIFO Threshold Level (IC_TX_TL)—Offset 3Ch.............. 766
19.5.1.13 Clear Combined and Individual Interrupt (IC_CLR_INTR)—Offset
40h ....................................................................................... 767
19.5.1.14 Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)—Offset 44h ..... 767
19.5.1.15 Clear RX_OVER Interrupt (IC_CLR_RX_OVER)—Offset 48h ......... 768
19.5.1.16 Clear TX_OVER Interrupt (IC_CLR_TX_OVER)—Offset 4Ch.......... 768
19.5.1.17 Clear RD_REQ Interrupt (IC_CLR_RD_REQ)—Offset 50h............. 769
19.5.1.18 Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)—Offset 54h .......... 769
19.5.1.19 Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)—Offset 5Ch.......... 770
19.5.1.20 Clear STOP_DET Interrupt (IC_CLR_STOP_DET)—Offset 60h....... 770
19.5.1.21 Clear START_DET Interrupt (IC_CLR_START_DET)—Offset 64h ... 771
19.5.1.22 Enable (IC_ENABLE)—Offset 6Ch ............................................ 771
19.5.1.23 Status (IC_STATUS)—Offset 70h............................................. 772
19.5.1.24 Transmit FIFO Level (IC_TXFLR)—Offset 74h ............................ 773
19.5.1.25 Receive FIFO Level (IC_RXFLR)—Offset 78h ............................. 774
19.5.1.26 SDA Hold (IC_SDA_HOLD)—Offset 7Ch .................................... 774
19.5.1.27 Transmit Abort Source (IC_TX_ABRT_SOURCE)—Offset 80h ....... 775
19.5.1.28 Enable Status (IC_ENABLE_STATUS)—Offset 9Ch...................... 776
19.5.1.29 SS and FS Spike Suppression Limit (IC_FS_SPKLEN)—Offset A0h 777
19.5.2 GPIO Controller Memory Mapped Registers............................................... 777
19.5.2.1 Port A Data (GPIO_SWPORTA_DR)—Offset 0h ............................. 778
19.5.2.2 Port A Data Direction (GPIO_SWPORTA_DDR)—Offset 4h.............. 778
19.5.2.3 Interrupt Enable (GPIO_INTEN)—Offset 30h ............................... 779
19.5.2.4 Interrupt Mask (GPIO_INTMASK)—Offset 34h ............................. 779
19.5.2.5 Interrupt Type (GPIO_INTTYPE_LEVEL)—Offset 38h ..................... 780
19.5.2.6 Interrupt Polarity (GPIO_INT_POLARITY)—Offset 3Ch .................. 781
19.5.2.7 Interrupt Status (GPIO_INTSTATUS)—Offset 40h......................... 781
19.5.2.8 Raw Interrupt Status (GPIO_RAW_INTSTATUS)—Offset 44h.......... 782
19.5.2.9 Debounce Enable (GPIO_DEBOUNCE)—Offset 48h ....................... 782
19.5.2.10 Clear Interrupt (GPIO_PORTA_EOI)—Offset 4Ch ........................ 783
19.5.2.11 Port A External Port (GPIO_EXT_PORTA)—Offset 50h ................. 784
19.5.2.12 Synchronization Level (GPIO_LS_SYNC)—Offset 60h .................. 784
20.0 SPI Interface ........................................................................................................ 787
20.1 Signal Descriptions .......................................................................................... 787
20.2 Features ......................................................................................................... 787
20.2.1 SPI Controller....................................................................................... 787
20.2.1.1 Processor-Initiated Data Transfer .............................................. 788
20.2.1.2 Data Format ........................................................................... 788
20.2.1.3 FIFO Operation ....................................................................... 789
20.2.1.4 Baud Rate Generation .............................................................. 789
20.3 Register Map................................................................................................... 791
20.4 PCI Configuration Registers............................................................................... 792
20.4.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 792
20.4.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 793
20.4.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 793
20.4.4 Status Register (STATUS)—Offset 6h....................................................... 794
20.4.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 795
20.4.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 795
20.4.7 Latency Timer (LATENCY_TIMER)—Offset Dh ............................................ 796
20.4.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 796
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20.5
20.4.9 BIST (BIST)—Offset Fh ......................................................................... 796
20.4.10 Base Address Register (BAR0)—Offset 10h ............................................. 797
20.4.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h..................... 798
20.4.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 798
20.4.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh.............................................. 798
20.4.14 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h ............ 799
20.4.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 799
20.4.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 799
20.4.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 800
20.4.18 MIN_GNT (MIN_GNT)—Offset 3Eh ......................................................... 800
20.4.19 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 801
20.4.20 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 801
20.4.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .......................... 801
20.4.22 Power Management Capabilities (PMC)—Offset 82h ................................. 802
20.4.23 Power Management Control/Status Register (PMCSR)—Offset 84h ............. 802
20.4.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h.... 803
20.4.25 Power Management Data Register (DATA_REGISTER)—Offset 87h............. 803
20.4.26 Capability ID (MSI_CAP_ID)—Offset A0h ............................................... 804
20.4.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 804
20.4.28 Message Control (MESSAGE_CTRL)—Offset A2h ...................................... 804
20.4.29 Message Address (MESSAGE_ADDR)—Offset A4h .................................... 805
20.4.30 Message Data (MESSAGE_DATA)—Offset A8h ......................................... 805
20.4.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 806
20.4.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................................. 806
Memory Mapped Registers ................................................................................ 807
20.5.1 SPI Control Register 0 (SSCR0)—Offset 0h .............................................. 807
20.5.2 SPI Control Register 1 (SSCR1)—Offset 4h .............................................. 808
20.5.3 SPI Status Register (SSSR)—Offset 8h .................................................... 810
20.5.4 SPI Data Register (SSDR)—Offset 10h .................................................... 811
20.5.5 DDS Clock Rate Register (DDS_RATE)—Offset 28h.................................... 812
21.0 Legacy Bridge........................................................................................................ 815
21.1 Features ........................................................................................................ 815
21.2 Register Map .................................................................................................. 816
21.3 PCI Configuration Registers .............................................................................. 817
21.3.1 PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—Offset 0h....... 818
21.3.2 PCI Status and Command Fields (PCI_STATUS_COMMAND)—Offset 4h ........ 818
21.3.3 PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)—Offset 8h... 819
21.3.4 PCI Miscellaneous Fields (PCI_MISC)—Offset Ch ....................................... 819
21.3.5 PCI Subsystem ID and Subsystem Vendor ID Fields
(PCI_SUBSYSTEM)—Offset 2Ch .............................................................. 820
21.3.6 GPIO Base Address (GBA)—Offset 44h .................................................... 821
21.3.7 PM1_BLK Base Address (PM1BLK)—Offset 48h ......................................... 821
21.3.8 GPE0_BLK Base Address (GPE0BLK)—Offset 4Ch ...................................... 821
21.3.9 ACPI Control (ACTL)—Offset 58h ............................................................ 822
21.3.10 PIRQA, PIRQB, PIRQC and PIRQD Routing Control (PABCDRC)—Offset 60h. 822
21.3.11 PIRQE, PIRQF, PIRQG and PIRQH Routing Control (PEFGHRC)—Offset 64h . 824
21.3.12 Watch Dog Timer Base Address (WDTBA)—Offset 84h ............................. 824
21.3.13 BIOS Decode Enable (BCE)—Offset D4h ................................................ 825
21.3.14 BIOS Control (BC)—Offset D8h............................................................. 826
21.3.15 Root Complex Base Address (RCBA)—Offset F0h..................................... 827
21.4 Memory Mapped Registers ................................................................................ 827
21.4.1 Root Complex Register Block ................................................................. 827
21.4.1.1 Root Complex Topology Capabilities List (RCTCL)—Offset 0h......... 828
21.4.1.2 Element Self Description (ESD)—Offset 4h ................................. 828
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21.5
21.6
21.7
21.4.1.3 Interrupt Queue Agent 0 (IRQAGENT0)—Offset 3140h.................. 829
21.4.1.4 Interrupt Queue Agent 1 (IRQAGENT1)—Offset 3142h.................. 829
21.4.1.5 Interrupt Queue Agent 2 (IRQAGENT2)—Offset 3144h.................. 830
21.4.1.6 Interrupt Queue Agent 3 (IRQAGENT3)—Offset 3146h.................. 830
21.4.1.7 RTC Configuration (RC)—Offset 3400h ....................................... 831
IO Registers.................................................................................................... 832
21.5.1 Fixed IO Registers ................................................................................ 832
21.5.1.1 NMI Status and Control Register (NSC)—Offset 61h ..................... 832
21.5.1.2 NMI Enable and RTC Index Register (NMIE)—Offset 70h ............... 833
21.5.1.3 Software SMI Control Port (SWSMICTL)—Offset B2h .................... 833
21.5.1.4 Software SMI Status Port (SWSMISTS)—Offset B3h ..................... 834
21.5.1.5 Reset Control Register (RSTC)—Offset CF9h................................ 834
21.5.2 ACPI GPE0 Block................................................................................... 835
21.5.2.1 GPE0 Status Register (GPE0STS)—Offset 0h ............................... 835
21.5.2.2 GPE0 Enable Register (GPE0EN)—Offset 4h................................. 836
21.5.2.3 SMI Enable Register (SMIEN)—Offset 10h................................... 837
21.5.2.4 SMI Status Register (SMISTS)—Offset 14h ................................. 838
21.5.2.5 General Purpose Event Control Register (GPEC)—Offset 18h ......... 839
21.5.2.6 Power Management Configuration Core Well Register
(PMCW)—Offset 28h ................................................................ 839
21.5.2.7 Power Management Configuration Suspend Well Register (PMSW)—
Offset 2Ch.............................................................................. 840
21.5.2.8 Power Management Configuration RTC Well Register
(PMRW)—Offset 30h ................................................................ 841
21.5.3 ACPI PM1 Block .................................................................................... 841
21.5.3.1 PM1 Status Register (PM1S)—Offset 0h ...................................... 841
21.5.3.2 PM1 Enable Register (PM1E)—Offset 2h...................................... 842
21.5.3.3 PM1 Control Register (PM1C)—Offset 4h ..................................... 843
21.5.3.4 Power Management 1 Timer Register (PM1T)—Offset 8h ............... 844
Legacy GPIO ................................................................................................... 845
21.6.1 Signal Descriptions ............................................................................... 845
21.6.2 Features .............................................................................................. 845
21.6.3 Use..................................................................................................... 845
21.6.4 Register Map........................................................................................ 846
21.6.5 IO Mapped Registers ............................................................................. 846
21.6.5.1 Core Well GPIO Enable (CGEN)—Offset 0h .................................. 847
21.6.5.2 Core Well GPIO Input/Output Select (CGIO)—Offset 4h ................ 847
21.6.5.3 Core Well GPIO Level for Input or Output (CGLVL)—Offset 8h........ 848
21.6.5.4 Core Well GPIO Trigger Positive Edge Enable (CGTPE)—Offset Ch .. 848
21.6.5.5 Core Well GPIO Trigger Negative Edge Enable (CGTNE)—Offset
10h ....................................................................................... 849
21.6.5.6 Core Well GPIO GPE Enable (CGGPE)—Offset 14h ........................ 849
21.6.5.7 Core Well GPIO SMI Enable (CGSMI)—Offset 18h ........................ 850
21.6.5.8 Core Well GPIO Trigger Status (CGTS)—Offset 1Ch ...................... 850
21.6.5.9 Resume Well GPIO Enable (RGEN)—Offset 20h............................ 851
21.6.5.10 Resume Well GPIO Input/Output Select (RGIO)—Offset 24h ........ 851
21.6.5.11 Resume Well GPIO Level for Input or Output (RGLVL)—Offset 28h 852
21.6.5.12 Resume Well GPIO Trigger Positive Edge Enable (RGTPE)—Offset
2Ch ....................................................................................... 852
21.6.5.13 Resume Well GPIO Trigger Negative Edge Enable (RGTNE)—Offset
30h ....................................................................................... 852
21.6.5.14 Resume Well GPIO GPE Enable (RGGPE)—Offset 34h .................. 853
21.6.5.15 Resume Well GPIO SMI Enable (RGSMI)—Offset 38h .................. 854
21.6.5.16 Resume Well GPIO Trigger Status (RGTS)—Offset 3Ch................ 854
21.6.5.17 Core Well GPIO NMI Enable (CGNMIEN)—Offset 40h................... 855
21.6.5.18 Resume Well GPIO NMI Enable (RGNMIEN)—Offset 44h .............. 855
Legacy SPI Controller ....................................................................................... 856
21.7.1 Signal Descriptions ............................................................................... 856
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21.8
21.9
21.7.2 Features ............................................................................................. 856
21.7.3 Register Map ....................................................................................... 856
21.7.4 Legacy SPI Host Interface Registers........................................................ 857
21.7.4.1 SPI Status (SPISTS)—Offset 3020h ........................................... 859
21.7.4.2 SPI Control (SPICTL)—Offset 3022h .......................................... 859
21.7.4.3 SPI Address (SPIADDR)—Offset 3024h ...................................... 860
21.7.4.4 SPI Data 0 - Lower 32 Bits (SPID0_1)—Offset 3028h................... 861
21.7.4.5 SPI Data 0 - Upper 32 Bits (SPID0_2)—Offset 302Ch................... 861
21.7.4.6 SPI Data 1 - Lower 32 Bits (SPID1_1)—Offset 3030h................... 862
21.7.4.7 SPI Data 1 - Upper 32 Bits (SPID1_2)—Offset 3034h................... 862
21.7.4.8 SPI Data 2 - Lower 32 Bits (SPID2_1)—Offset 3038h................... 862
21.7.4.9 SPI Data 2 - Upper 32 Bits (SPID2_2)—Offset 303Ch................... 863
21.7.4.10 SPI Data 3 - Lower 32 Bits (SPID3_1)—Offset 3040h ................. 863
21.7.4.11 SPI Data 3 - Upper 32 Bits (SPID3_2)—Offset 3044h ................. 863
21.7.4.12 SPI Data 4 - Lower 32 Bits (SPID4_1)—Offset 3048h ................. 864
21.7.4.13 SPI Data 4 - Upper 32 Bits (SPID4_2)—Offset 304Ch ................. 864
21.7.4.14 SPI Data 5 - Lower 32 Bits (SPID5_1)—Offset 3050h ................. 865
21.7.4.15 SPI Data 5 - Upper 32 Bits (SPID5_2)—Offset 3054h ................. 865
21.7.4.16 SPI Data 6 - Lower 32 Bits (SPID6_1)—Offset 3058h ................. 865
21.7.4.17 SPI Data 6 - Upper 32 Bits (SPID6_2)—Offset 305Ch ................. 866
21.7.4.18 SPI Data 7 - Lower 32 Bits (SPID7_1)—Offset 3060h ................. 866
21.7.4.19 SPI Data 7 - Upper 32 Bits (SPID7_2)—Offset 3064h ................. 866
21.7.4.20 BIOS Base Address (BBAR)—Offset 3070h ................................ 867
21.7.4.21 Prefix Opcode Configuration (PREOP)—Offset 3074h .................. 867
21.7.4.22 Opcode Type Configuration (OPTYPE)—Offset 3076h .................. 868
21.7.4.23 Opcode Menu Configuration - Lower 32 Bits (OPMENU_1)—Offset
3078h ................................................................................... 869
21.7.4.24 Opcode Menu Configuration - Upper 32 Bits (OPMENU_2)—Offset
307Ch ................................................................................... 869
21.7.4.25 Protected BIOS Range 0 (PBR0)—Offset 3080h ......................... 870
21.7.4.26 Protected BIOS Range 1 (PBR1)—Offset 3084h ......................... 871
21.7.4.27 Protected BIOS Range 2 (PBR2)—Offset 3088h ......................... 871
8254 Programmable Interval Timer.................................................................... 873
21.8.1 Features ............................................................................................. 873
21.8.1.1 Counter 0, System Timer ......................................................... 873
21.8.1.2 Counter 1, Refresh Request Signal ............................................ 873
21.8.1.3 Counter 2, Speaker Tone ......................................................... 873
21.8.2 Use .................................................................................................... 873
21.8.2.1 Timer Programming ................................................................ 873
21.8.2.2 Reading from the Interval Timer ............................................... 874
21.8.3 Register Map ....................................................................................... 875
21.8.4 Timer I/O Registers .............................................................................. 876
21.8.4.1 Counter 0 Interval Time Status Byte Format (C0TS)—Offset 40h ... 877
21.8.4.2 Counter 1 Interval Time Status Byte Format (C1TS)—Offset 41h ... 877
21.8.4.3 Counter 2 Interval Time Status Byte Format (C2TS)—Offset 42h ... 878
21.8.4.4 Timer Control Word Register (TCW)—Offset 43h ......................... 879
21.8.4.5 Counter 0 Counter Access Port Register (C0AP)—Offset 50h ......... 879
21.8.4.6 Counter 1 Counter Access Port Register (C1AP)—Offset 51h ......... 880
21.8.4.7 Counter 2 Counter Access Port Register (C2AP)—Offset 52h ......... 880
High Precision Event Timer (HPET)..................................................................... 880
21.9.1 Features ............................................................................................. 881
21.9.1.1 Non-Periodic Mode - All Timers ................................................. 881
21.9.1.2 Periodic Mode - Timer 0 Only.................................................... 881
21.9.1.3 Interrupts .............................................................................. 882
21.9.2 Register Map ....................................................................................... 882
21.9.3 Memory Mapped Registers ..................................................................... 883
21.9.3.1 General Capabilities and ID Register - Lower 32 Bits
(GCID_1)—Offset 0h ............................................................... 884
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21.9.3.2 General Capabilities and ID Register - Upper 32 Bits
(GCID_2)—Offset 4h................................................................ 885
21.9.3.3 General Configuration (GC)—Offset 10h ..................................... 885
21.9.3.4 General Interrupt Status Register (GIS)—Offset 20h .................... 885
21.9.3.5 Main Counter Value Register - Lower 32 Bits (MCV_1)—Offset F0h . 886
21.9.3.6 Main Counter Value Register - Upper 32 Bits (MCV_2)—Offset F4h . 886
21.9.3.7 Timer 0 Config and Capabilities Register - Lower 32 Bits
(T0C_1)—Offset 100h .............................................................. 887
21.9.3.8 Timer 0 Config and Capabilities Register - Upper 32 Bits
(T0C_2)—Offset 104h .............................................................. 888
21.9.3.9 Timer 0 Comparator Value Register - Lower 32 Bits
(T0CV_1)—Offset 108h ............................................................ 888
21.9.3.10 Timer 0 Comparator Value Register - Upper 32 Bits
(T0CV_2)—Offset 10Ch ............................................................ 888
21.9.3.11 Timer 1 Config and Capabilities Register - Lower 32 Bits (T1C_1)—
Offset 120h ............................................................................ 889
21.9.3.12 Timer 1 Config and Capabilities Register - Upper 32 Bits (T1C_2)—
Offset 124h ............................................................................ 890
21.9.3.13 Timer 1 Comparator Value Register (T1CV_1)—Offset 128h......... 890
21.9.3.14 Timer 2 Config and Capabilities Register - Lower 32 Bits (T2C_1)—
Offset 140h ............................................................................ 890
21.9.3.15 Timer 2 Config and Capabilities Register - Upper 32 Bits (T2C_2)—
Offset 144h ............................................................................ 891
21.9.3.16 Timer 2 Comparator Value Register (T2CV_1)—Offset 148h......... 892
21.9.4 References........................................................................................... 892
21.10 Real Time Clock (RTC)...................................................................................... 892
21.10.1 Signal Descriptions .............................................................................. 892
21.10.2 Features ............................................................................................ 893
21.10.2.1 Update Cycles ....................................................................... 893
21.10.2.2 Interrupts............................................................................. 893
21.10.2.3 Lockable RAM Ranges ............................................................ 893
21.10.3Register Map........................................................................................ 894
21.10.4I/O Registers ....................................................................................... 894
21.10.5Indexed Registers ................................................................................. 895
21.10.5.1 Offset 0Ah: Register A ........................................................... 896
21.10.5.2 Offset 0Bh: Register B - General Configuration .......................... 896
21.10.5.3 Offset 0Ch: Register C - Flag Register ...................................... 897
21.10.5.4 Offset 0Dh: Register D - Flag Register ...................................... 898
21.10.6References........................................................................................... 898
21.11 Interrupt Decoding & Routing ............................................................................ 898
21.11.1Features .............................................................................................. 898
21.11.1.1 Interrupt Decoder .................................................................. 898
21.11.1.2 Interrupt Router .................................................................... 899
21.12 8259 Programmable Interrupt Controllers (PIC) ................................................... 899
21.12.1Features .............................................................................................. 900
21.12.1.1 Interrupt Handling ................................................................. 900
21.12.1.2 Initialization Command Words (ICWx) ...................................... 902
21.12.1.3 Operation Command Words (OCW) .......................................... 903
21.12.1.4 Modes of Operation................................................................ 903
21.12.1.5 Masking Interrupts ................................................................ 905
21.12.1.6 Steering of PCI Interrupts....................................................... 905
21.12.2Register Map........................................................................................ 905
21.12.3I/O Registers ....................................................................................... 906
21.12.3.1 Master Initialization Command Word 1 (MICW1)—Offset 20h ....... 908
21.12.3.2 Master Initialization Command Word 2 (MICW2)—Offset 21h ....... 909
21.12.3.3 Master Operational Control Word 2 (MOCW2)—Offset 24h ........... 909
21.12.3.4 Master Initialization Command Word 3 (MICW3)—Offset 25h ....... 910
21.12.3.5 Master Operational Control Word 3 (MOCW3)—Offset 28h ........... 910
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21.12.3.6 Master Initialization Command Word 4 (MICW4)—Offset 29h ...... 911
21.12.3.7 Master Operational Control Word 1 (MOCW1)—Offset 2Dh .......... 912
21.12.3.8 Slave Initialization Command Word 1 (SICW1)—Offset A0h ........ 912
21.12.3.9 Slave Initialization Command Word 2 (SICW2)—Offset A1h ........ 913
21.12.3.10 Slave Operational Control Word 2 (SoCW2)—Offset A4h............ 913
21.12.3.11 Slave Initialization Command Word 3 (SICW3)—Offset A5h ....... 914
21.12.3.12 Slave Operational Control Word 3 (SoCW3)—Offset A8h............ 914
21.12.3.13 Slave Initialization Command Word 4 (SICW4)—Offset A9h ....... 915
21.12.3.14 Slave Operational Control Word 1 (SoCW1)—Offset ADh ........... 916
21.12.3.15 Master Edge/Level Control (ELCR1)—Offset 4D0h..................... 916
21.12.3.16 Slave Edge/Level Control (ELCR2)—Offset 4D1h ...................... 916
21.13 I/O APIC ........................................................................................................ 918
21.13.1Features ............................................................................................. 918
21.13.2Use .................................................................................................... 919
21.13.3Unsupported Modes .............................................................................. 919
21.13.4Register Map ....................................................................................... 920
21.13.5Memory Mapped Registers ..................................................................... 920
21.13.5.1 Index Register (IDX)—Offset FEC00000h .................................. 921
21.13.5.2 Window Register (WDW)—Offset FEC00010h............................. 921
21.13.5.3 End of Interrupt Register (EOI)—Offset FEC00040h.................... 921
21.13.6Index Registers.................................................................................... 922
21.13.6.1 Identification Register (ID)—Offset 0h ..................................... 922
21.13.6.2 Version Register (VS)—Offset 1h............................................. 923
21.13.6.3 Redirection Table Entry Lower (RTE[0-23]L)—Offset 10h - 3Eh.... 923
21.13.6.4 Redirection Table Entry Upper (RTE[0-23]U)—Offset 11h - 3Fh ... 924
21.14 Watchdog Timer.............................................................................................. 926
21.14.1Features ............................................................................................. 926
21.14.2Use .................................................................................................... 926
21.14.3Register Map ....................................................................................... 927
21.14.4I/O Mapped Registers ........................................................................... 927
21.14.4.1 Preload Value 1 Register 0 (PV1R0)—Offset 0h ......................... 928
21.14.4.2 Preload Value 1 Register 1 (PV1R1)—Offset 1h ......................... 928
21.14.4.3 Preload Value 1 Register 2 (PV1R2)—Offset 2h ......................... 929
21.14.4.4 Preload Value 2 Register 0 (PV2R0)—Offset 4h ......................... 929
21.14.4.5 Preload Value 2 Register 1 (PV2R1)—Offset 5h ......................... 930
21.14.4.6 Preload Value 2 Register 2 (PV2R2)—Offset 6h ......................... 930
21.14.4.7 Reload Register 0 (RR0)—Offset Ch ......................................... 930
21.14.4.8 Reload Register 1 (RR1)—Offset Dh......................................... 931
21.14.4.9 WDT Configuration Register (WDTCR)—Offset 10h .................... 931
21.14.4.10 WDT Lock Register (WDTLR)—Offset 18h ................................ 932
22.0 Debug Port and JTAG/TAP ..................................................................................... 935
22.1 Signal Descriptions .......................................................................................... 935
22.2 Features ........................................................................................................ 936
22.2.1 OpenOCD ............................................................................................ 936
Figures
1
2
3
4
5
6
7
Block Diagram ......................................................................................................... 38
Intel® Quark™ SoC X1000 PCI View............................................................................ 43
Signals In Default System Pin List .............................................................................. 46
Intel® Quark™ SoC X1000 Package Dimensions............................................................ 59
PCI Express Transmitter Eye...................................................................................... 76
PCI Express Receiver Eye .......................................................................................... 76
USB Rise and Fall Time ............................................................................................. 78
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Intel® Quark™ SoC X1000—Contents
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45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
USB Jitter................................................................................................................79
USB EOP Width ........................................................................................................79
SPI Interface Timing .................................................................................................81
SDIO Interface Timing ..............................................................................................82
Measurement Points for Differential Clocks...................................................................84
Physical Address Space - Low DRAM & MMIO................................................................92
Physical Address Space - MMIO ..................................................................................93
Physical Address Space - DOS DRAM...........................................................................94
Physical Address Space - SMM Range ..........................................................................95
Bus 0 PCI Devices and Functions ................................................................................98
Message Bus with PCI Space ......................................................................................99
SoC Platform Clocking ............................................................................................. 102
RTC Power Well Timing Diagrams ............................................................................. 115
Power Up Sequence ................................................................................................ 117
Power-Up Sequence without G2/G3........................................................................... 118
eSRAM 4KB Page Mapping ....................................................................................... 128
eSRAM 512KB Page Mapping.................................................................................... 129
Intel® Quark™ SoC X1000 Host Bridge Register Map ................................................... 132
Register Map.......................................................................................................... 236
PCI Express Register Map ........................................................................................ 264
Ethernet Register Map............................................................................................. 311
Transmit Descriptor Fields ....................................................................................... 422
Transmit Descriptor Fetch (Read) ............................................................................. 423
Receive Descriptor Fields ......................................................................................... 427
USB Register Map................................................................................................... 437
SD Memory Card Bus Topology................................................................................. 593
SDIO Card Bus Topology ......................................................................................... 593
eMMC Interface ...................................................................................................... 594
SDIO/SD/eMMC Register Map................................................................................... 596
UART Data Transfer Flow ......................................................................................... 664
HSUART Register Map ............................................................................................. 668
Data Transfer on the I2C* Bus.................................................................................. 733
START and STOP Conditions..................................................................................... 733
7-Bit Address Format .............................................................................................. 734
10-bit Address Format ............................................................................................ 734
Master Transmitter Protocol ..................................................................................... 735
Master Receiver Protocol ......................................................................................... 736
START Byte Transfer ............................................................................................... 736
I2C*/GPIO Register Map.......................................................................................... 739
Generic SPI Waveform ............................................................................................ 788
SPI Register Map .................................................................................................... 791
Legacy Bridge Register Map ..................................................................................... 817
Legacy GPIO Register Map ....................................................................................... 846
Legacy SPI Register Map ......................................................................................... 857
8254 Timers Register Map ....................................................................................... 876
HPET Register Map ................................................................................................. 883
RTC Register Map ................................................................................................... 894
8259 Register Map.................................................................................................. 906
Detailed I/O APIC Block Diagram .............................................................................. 918
MSI Address and Data............................................................................................. 919
I/O APIC Register Map ............................................................................................ 920
Watchdog Timer Register Map .................................................................................. 927
Tables
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42
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46
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48
49
50
51
52
53
54
55
Industry Specifications.............................................................................................. 37
Component Identification .......................................................................................... 42
Intel® Quark™ SoC X1000 Device ID .......................................................................... 44
I/O Power Well Definitions......................................................................................... 47
Buffer Type Definitions ............................................................................................. 47
Default Buffer State Definitions .................................................................................. 47
System Memory Signals............................................................................................ 48
PCI Express* 2.0 Signals........................................................................................... 48
Ethernet Interface Signals ......................................................................................... 49
USB 2.0 Interface Signals ......................................................................................... 49
Integrated Clock Interface Signals.............................................................................. 50
SD/SDIO/MMC Signals .............................................................................................. 50
High Speed UART Signals .......................................................................................... 51
I2C* Signals ............................................................................................................ 51
Legacy SPI Signals ................................................................................................... 52
SPI Signals ............................................................................................................. 52
Real Time Clock (RTC) Interface Signals...................................................................... 53
Power Management Interface Signals.......................................................................... 53
JTAG and Debug Interface Signals .............................................................................. 54
Legacy Interface Signals ........................................................................................... 54
General Purpose I/O Signals ..................................................................................... 54
Power and Ground Pins ............................................................................................. 55
Hardware Straps ...................................................................................................... 57
Alphabetical Ball Listing ............................................................................................ 60
Alphabetical Signal Listing ......................................................................................... 64
Intel® Quark™ SoC X1000 Absolute Maximum Voltage Ratings ....................................... 69
Power Supply Rail Ranges ......................................................................................... 70
Maximum Supply Current: ICC Max ............................................................................ 71
Configurable IO (CFIO) Bi-directional Signal Groupings ................................................. 72
CFIO DC Characteristics ............................................................................................ 73
CFIO AC Characteristics ............................................................................................ 73
RTC DC Characteristics ............................................................................................. 74
PCI Express* 2.0 Differential Signal DC Characteristics ................................................. 74
PCI Express* 2.0 Interface Timings ............................................................................ 75
USB 2.0 Differential Signal DC Characteristics .............................................................. 77
USB 2.0 Interface Timings......................................................................................... 77
Legacy SPI Interface Timings (20 MHz) ....................................................................... 79
SPI0/1 Interface Timings (25 MHz)............................................................................. 80
SDIO Timing ........................................................................................................... 81
Reference Clocks AC Characteristics ........................................................................... 82
Fixed I/O Register Access Method Example (NSC Register) ............................................ 85
Fixed Memory Mapped Register Access Method Example (IDX Register)........................... 85
Referenced I/O Register Access Method Example (PM1S Register) .................................. 86
Memory Mapped Register Access Method Example (ESD Register) .................................. 86
PCI Register Access Method Example (PCI_DEVICE_VENDOR Register)............................ 86
PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping ............................................ 87
PCI Configuration Memory Bar Mapping ...................................................................... 87
MCR Description ...................................................................................................... 88
MCRX Description..................................................................................................... 88
Register Access Types and Definitions......................................................................... 89
Fixed Memory Ranges in the Legacy Bridge ................................................................. 95
Fixed I/O Ranges in the Legacy Bridge ........................................................................ 96
Movable I/O Ranges Decoded by PCI Devices on the I/O Fabric ...................................... 96
PCI Devices and Functions......................................................................................... 97
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Intel® Quark™ SoC X1000—Contents
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
Message Types.........................................................................................................99
Intel® Quark™ SoC X1000 Clock Inputs ..................................................................... 103
Intel® Quark™ SoC X1000 Clock Outputs ................................................................... 103
Power Management ................................................................................................ 105
General Power States for System.............................................................................. 107
ACPI PM State Transition Rules................................................................................. 107
Processor Core/ States Support ................................................................................ 108
Main Memory States ............................................................................................... 108
PCIe* States.......................................................................................................... 108
G, S and C State Combinations................................................................................. 109
RTC Power Well Timing Parameters........................................................................... 115
S4/S5 to S0 Timing Parameters................................................................................ 119
Intel® Quark™ SoC X1000 S3 Wake Events................................................................ 121
SoC Reset Events ................................................................................................... 121
Thermal Sensor Signals ........................................................................................... 123
Summary of PCI Configuration Registers—0/0/0 ......................................................... 132
Summary of I/O Registers—PMBA............................................................................. 138
Summary of Message Bus Registers—0x00 ................................................................ 140
Summary of Message Bus Registers—0x03 ................................................................ 145
Summary of Message Bus Registers—0x04 ................................................................ 174
Summary of Message Bus Registers—0x05 ................................................................ 180
Summary of Message Bus Registers—0x05 ................................................................ 228
Summary of Message Bus Registers—0x31 ................................................................ 229
Memory Signals...................................................................................................... 233
Supported DDR3 DRAM Devices................................................................................ 235
Supported DDR3 Memory Configurations ................................................................... 235
Summary of Message Bus Registers—0x01 ................................................................ 236
PCI Express* 2.0 Signals ......................................................................................... 261
Possible Interrupts Generated From Events/Packets .................................................... 262
Summary of PCI Configuration Registers—0/23/0 ....................................................... 264
10/100 Ethernet Interface Signals ............................................................................ 309
Summary of PCI Configuration Registers—0/20/6 ....................................................... 311
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 327
Transmit Descriptor Word 0 (TDES0)......................................................................... 423
Transmit Descriptor Word 1 (TDES1)......................................................................... 426
Transmit Descriptor 2 (TDES2) ................................................................................. 426
Transmit Descriptor 3 (TDES3) ................................................................................. 426
Transmit Descriptor 6 (TDES6) ................................................................................. 426
Transmit Descriptor 7 (TDES7) ................................................................................. 427
Receive Descriptor Fields (RDES0) ............................................................................ 428
Receive Descriptor Fields 1 (RDES1) ......................................................................... 429
Receive Descriptor Fields 2 (RDES2) ......................................................................... 430
Receive Descriptor Fields 3 (RDES3) ......................................................................... 430
Receive Descriptor Fields 4 (RDES4) ......................................................................... 431
Receive Descriptor Fields 6 (RDES6) ......................................................................... 433
Receive Descriptor Fields 7 (RDES7) ......................................................................... 433
Signals.................................................................................................................. 435
Summary of PCI Configuration Registers—0/20/2 ....................................................... 437
Summary of PCI Configuration Registers—0/20/3 ....................................................... 453
Summary of PCI Configuration Registers—0/20/4 ....................................................... 471
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 486
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 549
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 569
SDIO/SD/eMMC Interface Signals ............................................................................. 591
SDIO/SD/eMMC Features......................................................................................... 592
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Contents—Intel® Quark™ SoC X1000
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
Summary of PCI Configuration Registers—0/20/0 ....................................................... 596
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 612
UART 0 Interface Signals......................................................................................... 663
UART 1 Interface Signals......................................................................................... 663
Baud Rates Achievable with Different DLAB Settings ................................................... 664
Summary of PCI Configuration Registers—0/20/1 ....................................................... 669
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 684
Summary of Memory Mapped I/O Registers—BAR1 ..................................................... 694
I2C* Signals .......................................................................................................... 731
I2C* Definition of Bits in First Byte ........................................................................... 734
GPIO Signals ......................................................................................................... 738
Summary of PCI Configuration Registers—0/21/2 ....................................................... 739
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 755
Summary of Memory Mapped I/O Registers—BAR1 ..................................................... 777
SPI Interface Signals .............................................................................................. 787
SPI Clock Frequency Settings .................................................................................. 790
Summary of PCI Configuration Registers—0/21/0 ....................................................... 792
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 807
Miscellaneous Legacy Signals................................................................................... 816
Summary of PCI Configuration Registers—0/31/0 ....................................................... 817
Summary of Memory Mapped I/O Registers—RCBA..................................................... 827
Summary of I/O Registers....................................................................................... 832
Summary of I/O Registers—GPE0BLK ....................................................................... 835
Summary of I/O Registers—PM1BLK ......................................................................... 841
Legacy GPIO Signals .............................................................................................. 845
Summary of I/O Registers—GBA .............................................................................. 846
Legacy SPI Signals ................................................................................................. 856
Summary of Memory Mapped I/O Registers—RCBA..................................................... 858
Counter Operating Modes........................................................................................ 874
Register Aliases ..................................................................................................... 876
8254 Interrupt Mapping .......................................................................................... 882
Summary of Memory Mapped I/O Registers—0xFED00000........................................... 883
RTC Signals........................................................................................................... 893
I/O Registers Alias Locations ................................................................................... 895
Indexed Registers .................................................................................................. 895
IRQAGENT Description ............................................................................................ 899
Interrupt Controller Connections .............................................................................. 900
Interrupt Status Registers ....................................................................................... 901
Content of Interrupt Vector Byte .............................................................................. 901
8259 I/O Registers Alias Locations ........................................................................... 907
Summary of I/O Registers....................................................................................... 907
I/O APIC Memory Mapped Registers ......................................................................... 921
Index Registers ..................................................................................................... 922
Summary of I/O Registers—WDTBA.......................................................................... 927
Debug Port and JTAG/TAP Signals ............................................................................ 935
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Intel® Quark™ SoC X1000—Revision History
Revision History
Date
Revision
November 2014
004
•
•
Updated Section 9.2.3, “AC Power Applied: G3 to S4/S5 State Transition” on page 115
Updated Section 9.2.4, “Using PWR_BTN_B: Transition from S4/S5 to S0” on page 116
003
•
•
•
•
•
•
•
•
Updated
Updated
Updated
Updated
Updated
Updated
Updated
Updated
August 2014
Description
Table 23, “Hardware Straps” on page 57
subsection numbering under Section 12.6.2, “SPI DMA Block” on page 140
Table 27, “Power Supply Rail Ranges” on page 70
Table 28, “Maximum Supply Current: ICC Max” on page 71
Table 33, “RTC DC Characteristics” on page 74
Table 36, “USB 2.0 Differential Signal DC Characteristics” on page 77
Table 66, “RTC Power Well Timing Parameters” on page 115
Table 110, “SDIO/SD/eMMC Features” on page 592
May 2014
002
Updated Chapter 3 Ballout and Package Information
Updated Table 18 Power Management Interface Signals
Updated Table 23 Hardware Straps
Added Table 30, “Configurable IO (CFIO) Bi-directional Signal Groupings” on page 72 and Table 31,
“CFIO DC Characteristics” on page 73
Replaced Figure 19, “SoC Platform Clocking” on page 102
Removed ECC Scrubbing (Sections 12.7.3.1 - 12.7.3.10, Section 12.3.1)
Removed SPI DMA (Updated Section 12.3, Removed Sections 12.6.2.1 - 12.6.2.3, Added Register
Option Register 1(P_CFG_72) —Offset 72h)
Updated Table 49
Added Table 54 Message Types to Section 6.4 Message Bus Space
Updated Table 67
Added 12.7.9.2 Miscellaneous Legacy Signal Enables (HLEGACY)—Offset 0Ah
Updated Section 13.4.1 DRAM Rank Population (DRP)—Offset 0h
Added Table 78 Message Opcode Definition (Section 13.5)
Added Section 15.7, “MAC Descriptor Details”
Other changes are marked with change bars
October 2013
001
Initial Public Release
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Introduction—Intel® Quark™ SoC X1000
1.0
Introduction
1.1
About This Manual
This document is intended for Original Equipment Manufacturers and BIOS vendors
creating products based on the Intel® Quark™ SoC X1000 application processor.
Note:
Throughout this document, SoC is used as a general term and refers to all Intel®
Quark™ SoC X1000 SKUs, unless specifically noted otherwise.
This manual assumes a working knowledge of the vocabulary and principles of
interfaces and architectures such as PCI Express*, USB, SDIO/MMC, and ACPI.
Although some details of these features are described within this manual, refer to the
individual industry specifications listed in Table 1 for the complete details.
All PCI buses, devices and functions in this manual are abbreviated using the following
nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as
Dn and functions as Fn. For example, Device 31 Function 0 is abbreviated as D31:F0,
Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number is not
used, and can be considered to be Bus 0.
Table 1.
Industry Specifications
Specification
1.2
Location
PCI Express* Base Specification, Revision 2.0
http://www.pcisig.com/specifications
PCI Local Bus Specification, Revision 2.3 (PCI)
http://www.pcisig.com/specifications
PCI Power Management Specification, Revision 1.2
http://www.pcisig.com/specifications
Universal Serial Bus Specification (USB), Revision 2.0
http://www.usb.org/developers/docs
Advanced Configuration and Power Interface, Version 3.0 (ACPI)
http://www.acpi.info/spec.htm
Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 1.0 (EHCI)
http://developer.intel.com/technology/usb/
ehcispec.htm
IEEE 802.3 Fast Ethernet
http://standards.ieee.org/getieee802/
AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6)
http://T13.org (T13 1410D)
IA-PC HPET (High Precision Event Timers) Specification,
Revision 1.0a
http://www.intel.com/content/www/us/en/
software-developers/software-developershpet-spec-1-0a.html
Component Overview
The Intel® Quark™ SoC X1000 processor is the next generation secure, low-power
Intel® Architecture (IA) SoC for deeply embedded applications. The SoC integrates the
Inte® QuarkTM SoC X1000 Core plus all the required hardware components to run offthe-shelf operating systems and to leverage the vast x86 software ecosystem.
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Intel® Quark™ SoC X1000—Introduction
To enable secure applications, the SoC secure SKUs feature an on-die Boot ROM that is
used to establish a hardware Root of Trust (RoT). The immutable code located within
the Boot ROM is used to initiate an iterative firmware authentication process ensuring
only trusted code is executed when taking the platform out of reset.
To facilitate low-cost platforms with sensitive Bill of Material (BOM) requirements, all
SoC clocks can be generated from a single crystal oscillator while all the required SoC
voltage levels can be derived from a single commercial off-the-shelf (COTS) voltage
regulator. In addition, the SoC provides an ECC-protected DRAM solution using only
standard x8 DDR3 devices.
The SoC also features a 512 Kbyte on-die embedded SRAM (eSRAM) that can be
configured to overlay regions of DRAM to provide low latency access to critical portions
of system memory. For robustness, the contents of this on-die eSRAM are also ECC
protected.
Figure 1.
Block Diagram
CPU Core
Clock
eSRAM
Host Bridge
JTAG
DDR3
Memory
Controller
AMBA Fabric
I/O
I/O
I/O
SPI
I/O
I/O
APIC
I/O
ROM
8259
I/O
HPET
8254
I/O
I/O
RTC
I/O
I/O
SDIO
I/O
GPIO
UART
I/O
I/O
USB 2.0
I/O
PMC
10/100 ETH
I/O
I/O
SPI
PCIe*
I2C*/GPIO
I/O
1.2.1
Legacy Bridge
SoC CPU Core Features
• 400 MHz maximum operating frequency
• Low power options to run at half or at quarter of maximum CPU frequency
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Introduction—Intel® Quark™ SoC X1000
• 32-bit address bus, 32-bit data bus
• 16 Kbyte shared instruction and data L1 cache.
1.2.2
System Memory Controller Features
• Single channel DDR3 memory controller with ECC support
• 16-bit data bus
• Supports up to two ranks total
• Supports DDR3 with 800 MT/s data rates
• x8 DRAM device data width
• 1 Gbit, 2 Gbit, and 4 Gbit DRAM device densities
• Total memory size from 128 Mbyte to 2 Gbyte
• Supports different physical mappings of bank addresses to optimize performance
• Out-of-order request processing to increase performance
• Aggressive power management to reduce power consumption
• Proactive page closing policies to close unused pages
• Supports soldered down DRAM devices
1.2.3
Embedded SRAM Features
• Low Latency 512 Kbyte on-die embedded SRAM
• Configurable to either overlay a 512 Kbyte block or overlay individual 4 Kbyte
pages of system memory
• ECC protected
1.2.4
Power Management Features
• Supports ACPI 3.0 specification
• Supports C0, C1, and C2 processor power states
• Supports S0, S3, and S4/S5 system power states
1.2.5
Security Features
• On-die Boot ROM provides Hardware Root of Trust (RoT) for firmware
authentication
1.2.6
PCI Express* Features
The SoC has two PCI Express* root ports, each supporting the PCI Express Base
specification Rev 2.0 at a maximum of 2.5 GT/s data transfer rates. Each root port is
configured as a x1 link.
• 128 Byte max payload size with the capability of splitting the request at 64 Byte
granularity
• Software-Initiated Link Power Management (D1, D2, D3Hot, and L1 States)
• PME event generation
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Intel® Quark™ SoC X1000—Introduction
1.2.7
Ethernet Features
• 10 and 100 Mbps data transfer rates with RMII interface to communicate with an
external Fast Ethernet PHY
• Full-duplex operation:
— IEEE 802.3x flow control support
— Optional forwarding of received pause control frames to the user application
• Half-duplex operation:
— CSMA/CD Protocol support
• Flexible address filtering modes:
— 64-bit Hash filter for multicast and unicast (DA) addresses
— Option to pass all multicast addressed frames
— Promiscuous mode to pass all frames without any filtering for network
monitoring
— Pass all incoming packets (as per filter) with a status report
• Programmable frame length to support Standard Ethernet frames with size up to
1522 bytes
• Enhanced Receive module for checking IPv4 header checksum and TCP, UDP, or
ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type 2)
• Support Ethernet frame time stamping as described in IEEE 1588-2002 and IEEE
1588-2008. The 64-bit timestamps are given in the transmit or receive status of
each frame.
1.2.8
USB2 Host Controller Features
• 2 host ports that support high-speed (480 Mbps), full-speed (12 Mbps), and lowspeed (1.5 Mbps) operation
• EHCI and OHCI host controllers
1.2.9
USB2 Device Controller Features
• Single device port that supports high-speed (480 Mbps) and full-speed (12 Mbps)
operation
1.2.10
SD/SDIO/eMMC Controller Features
• Host Controller provides a single port configurable as an SD, SDIO, or eMMC
interface
• SD Clock Frequency up to 50 MHz
• Supports SD Host Controller Standard Specification 3.0
• Supports SDIO card specification 3.0
• Supports SD Memory Card Specification 3.0
• Supports SD Memory Card Security Specification 1.01
• Supports eMMC Specification 4.41
1.2.11
I2C* Master Controller
• Two-wire I2C serial bus interface
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Introduction—Intel® Quark™ SoC X1000
• Two I2C speeds supported: Standard (100 Kbit/s) and Fast (400 Kbit/s) data rates
• Fully asynchronous I2C clock signal
• Master I2C operation
1.2.12
GPIO Features
• 16 GPIO pins provided
• 6 GPIO pins remain active during S3 and can be used to wake the system from the
Suspend state.
• Remaining 10 GPIO pins are powered during S0 state only and are not available in
S3
1.2.13
SPI Master Controller
• Two SPI Master controllers
• One Chip Select per master controller
• Configurable SCLK frequency from 1 kHz up to 25 MHz
1.2.14
High Speed UART Controller with DMA
• Two 16550 compliant UART controllers
• Supported Baud rates from 300 to 2764800
• Integrated DMA capability with hardware flow control
1.2.15
Legacy Bridge
The Legacy Bridge is a collection of hardware blocks critical to implement an Intel
Architecture compatible platform. Some of its key features are:
• A 20 MHz Serial Peripheral Interface (SPI) for Flash only - stores boot FW and
system configuration data
• A Power Management Controller (PMC) that controls many of the power
management features present in the SoC
• Legacy Bridge Components - Provides hardware blocks required to support legacy
PC platform features. The legacy bridge components include the RTC, Interrupt
Controllers, Timers and General Purpose I/Os (GPIO).
1.2.16
Package
The SoC is packaged in a Flip-Chip Ball Grid Array (FCBGA) package with 393 solder
balls with 0.593 mm ball pitch. The package dimensions are 15mm x 15mm.
1.3
Component Identification
The Intel® Quark™ SoC X1000 stepping is identified by both:
• Processor Family/Model/Stepping returned by the CPUID instruction. This always
returns 0x590 for SoC.
• Revision ID register of the Host Bridge, located at D0:F0. Reads of the register
reflect the stepping.
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Intel® Quark™ SoC X1000—Introduction
Table 2.
Component Identification
Vendor ID1
Device ID2
Revision ID3
Stepping
8086h
0958h
00h
A0h
Notes:
1.
The Vendor ID corresponds to bits 15-0 of the Vendor ID Register located at offset 00-01h in the PCI
configuration space of the device.
2.
The Device ID corresponds to bits 15-0 of the Device ID Register located at offset 02-03h in the PCI
configuration space of the device.
3.
The Revision ID corresponds to bits 7-0 of the Revision ID Register located at offset 08h in the PCI
configuration space of the device.
The SoC incorporates a variety of PCI functions as listed in Table 3. All devices reside
on PCI Bus 0 as shown in Figure 2.
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Introduction—Intel® Quark™ SoC X1000
Figure 2.
Intel® Quark™ SoC X1000 PCI View
PCI Space
CPU
Core
Host Bridge
D:0,F:0
PCI
CAM
(I/O)
Bus 0
PCI
ECAM
(Mem)
I2C*/GPIO F:2
HSUART0 F:1
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
RP0 F:1
PMC
Legacy Bridge
D:31,F:0
SDIO/eMMC F:0
PCIe*
D:23
SPI1 F:1
IO Fabric
D:21
SPI0 F:0
RP0 F:0
GPIO
RTC
8254
8259
HPET
IO APIC
SPI
MAC0 F:6
MAC1 F:7
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Intel® Quark™ SoC X1000—Introduction
Table 3.
Intel® Quark™ SoC X1000 Device ID
Device Function
Description
Device ID
A0 SRID
D0:F0
Host Bridge
0958h
00h
D31:F0
Legacy Bridge
095Eh
00h
D23:F0
PCIe* Root Port 0
11C3h
00h
D23:F1
PCIe* Root Port 1
11C4h
00h
D20:F0
SDIO / eMMC Controller
08A7h
10h
D20:F1
HS-UART 0
0936h
10h
D20:F2
USB 2.0 Device
0939h
10h
D20:F3
USB EHCI Host Controller
0939h
10h
D20:F4
USB OHCI Host Controller
093Ah
10h
D20:F5
HS-UART 1
0936h
10h
D20:F6
10/100 Ethernet MAC 0
0937h
10h
D20:F7
10/100 Ethernet MAC 1
0937h
10h
D21:F0
SPI Controller 0
0935h
10h
D21:F1
SPI Controller 1
0935h
10h
I C* Controller and GPIO Controller
0934h
10h
D21:F2
2
§§
Intel® Quark™ SoC X1000
Datasheet
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Physical Interfaces—Intel® Quark™ SoC X1000
2.0
Physical Interfaces
Many interfaces contain physical pins. These groups of pins make up the physical
interfaces. This chapter summarizes the physical interfaces.
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Intel® Quark™ SoC X1000—Physical Interfaces
Figure 3.
Signals In Default System Pin List
DDR3_DQ[15:0]
DDR3_DQS[1:0]
DDR3_DQSB[1:0]
DDR3_DM[1:0]
DDR3_MA[15:0]
DDR3_BS[2:0]
DDR3_RASB
DDR3_CASB
DDR3_WEB
DDR3_CSB[1:0]
DDR3_ODT[1:0]
DDR3_CKE[1:0]
DDR3_CK[1:0]
DDR3_CKB[1:0]
DDR3_VREF
DDR3_ODTPU/DQPU/CMDPU
DDR3_IDRAM_PWROK
DDR3_ISYSPWRGOOD
DDR3_DRAMRSTB
DDR3
Interface
MAC[0/1]_TXEN
MAC[0/1]_TXDATA[1:0]
MAC[0/1]_RXDV
MAC[0/1]_RXDATA[1:0]
MAC[0/1]_MDC
MAC[0/1]_MDIO
RMII_REF_CLK
Ethernet
RMII
Interface
CPU
Core
IVCCRTCEXT
RTCX1
RTCX2
RTCRST_B
THERM_B
SMI_B
LSPI_SS_B
LSPI_SCK
Legacy Bridge
LSPI_MISO
LSPI_MOSI
RESET_BTN_B
PWR_BTN_B
WAKE_B
PCIE_PETP[1:0]
PCIE_PETN[1:0]
PCIE_PERP[1:0]
PCIE_PERN[1:0]
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_IRCOMP
PCIE_RBIAS
PCI Express* 2.0
Interface
SD_DATA[7:0]
SD_CMD
SD_CLK
SD_WP
SD_CD_B
SD_LED
SD_PWR
SD/MMC
Interface
USBD_DP
USBD_DN
USBH[1:0]_DP
USBH[1:0]_DN
USBH[1:0]_OC_B
IUSBCOMP
OUSBCOMP
USBH[1:0]_PWR_EN
Legacy
Components
GPE_B
S5_PG
Power
Management
Controller
Interface
S3_3V3_EN
S3_1V5_EN
S3_PG
S0_3V3_EN
S0_1V5_EN
S0_1V0_EN
S0_1P0_PG
S0_PG
ODRAM_PWROK
OSYSPWRGOOD
SIU0_DCD_B
SIU0_DSR_B
Universal Serial
Bus 2.0
Interface
HSUART
Interface
SIU0_DTR_B
SIU0_RI_B
SIU[0/1]_CTS_B
SIU[0/1]_RTS_B
SIU[0/1]_RXD
SIU[0/1]_TXD
FLEX_CLK[2:0]
CKSYS25OUT
RMII_REF_CLK_OUT
REF[0/1]_OUTCLK_P
REF[0/1]_OUTCLK_N
OSC_COMP
XTAL_IN
XTAL_OUT
Internal Clocking
SPI
Interface
SPI[0/1]_MOSI
RTC_EXT_CLK_EN
PRDY_B
PREQ_B
TCK
TDI
TDO
TMS
TRST_B
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SPI[0/1]_SS_B
SPI[0/1]_SCK
SPI[0/1]_MISO
JTAG Port
I2C*
Interface
I2C_CLK
I2C_DATA
GPIO
Interface
GPIO_SUS[5:0]
GPIO[9:0]
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Physical Interfaces—Intel® Quark™ SoC X1000
2.1
Pin States Through Reset
This chapter describes the each signal state before, during, and directly after reset.
Additionally, some signals have internal pull-up/pull-down termination resistors, and
their values are also provided.
Table 4.
I/O Power Well Definitions
Power Type
Table 5.
Power Well Description
CORE
Core I/O, and everything else uses the CORE power well.
SUS
Devices outside of memory that must remain on in the S3 state use the SUS power well.
RTC
Devices that must be on in the S4/S5 state use the RTC power well.
Buffer Type Definitions
Buffer Type
Table 6.
Buffer Description
PCIe*
PCIe*, differential buffer type
SSTL-15
DDR3, 1.5V tolerant SSTL buffer type
DDI
DDR (TMDS, DP) 1.0V tolerant differential buffer type
CMOS[Voltage]
CMOS buffer type. [Voltage] can be of the following types: 1.05, 1.5, 1.8, and 3.3.
CMOS[Voltage]_OD
Open drain CMOS buffer type [Voltage] can be of the following types: 1.05, 1.5, 1.8 and
3.3.
Analog
Analog pins that do not have specific digital requirements. Often used for circuit
calibration or monitoring.
Default Buffer State Definitions
Buffer State
2.2
Description
High-Z
The SoC places this output in a high-impedance state. For inputs, external drivers are not
expected.
Do Not Care
The state of the input (driven or tristated) does not affect the SoC. For outputs, it is
assumed that the output buffer is in a high-impedance state.
VOH
The SoC drives this signal high.
VOL
The SoC drives this signal low.
Unknown
The SoC drives or expects an indeterminate value.
VIH
The SoC expects/requires the signal to be driven high.
VIL
The SoC expects/requires the signal to be driven low.
Pull-up
This signal is pulled high by a pull-up resistor (internal or external — internal value
specified in “Term” column).
Pull-down
This signal is pulled low by a pull-down resistor (internal or external — internal value
specified in “Term” column).
Running
The clock is toggling, or the signal is transitioning.
Off
The power plane for this signal is powered down. The SoC does not drive outputs, and
inputs should not be driven to the SoC. (VSS on output)
System Memory Signals
See Section 6.0 for more details of the DDR3 interface signals. Termination not listed.
November 2014
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Intel® Quark™ SoC X1000
Datasheet
47
Intel® Quark™ SoC X1000—Physical Interfaces
Table 7.
System Memory Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
DDR3_BS[2:0]
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CASB
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_RASB
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_WEB
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_MA[15:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CK[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CKB[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CKE[1:0]
I/O
-
1.5V
SSTL-15
Off
VOL
VOL
VOL
DDR3_CSB[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
VOH
DDR3_ODT[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
VOL
DDR3_DQ[15:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_DM[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_DQS[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_DQSB[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_IDRAM_PWROK
I
Ext
1.5V
CMOS-15
VIL
VIH
Pull-up
VIH
DDR3_ISYSPWRGOOD
I
Ext
1.5V
CMOS-15
VIL
VIL
Pull-up
VIH
DDR3_DRAMRSTB
O
-
1.5V
CMOS-15
Off
VOH
VOL
VOL/VOH(S3
Exit)
DDR3_VREF
I/O
-
1.5V
Reference
Off
Reference
Reference
Reference
DDR3_ODTPU
I/O
-
1.5V
Analog
Off
Analog
Analog
Analog
DDR3_DQPU
I/O
-
1.5V
Analog
Off
Analog
Analog
Analog
DDR3_CMDPU
I/O
-
1.5V
Analog
Off
Analog
Analog
Analog
2.3
PCI Express* 2.0 Signals
See “PCI Express* 2.0” on page 261 for more details of the interface signals.
Table 8.
PCI Express* 2.0 Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
PCIE_REFCLKP
I
-
1.05V
PCIe
Off
Off
Running/
Unknown
PCIE_REFCLKN
I
-
1.05V
PCIe
Off
Off
Running/
Unknown
PCIE_PETP[1:0]
O
-
1.05V
PCIe
Off
Off
PCIE_PETN[1:0]
O
-
1.05V
PCIe
Off
Off
VOL
VOL
PCIE_PERP[1:0]
I
-
1.05V
PCIe
Off
Off
High-Z
High-Z
PCIE_PERN[1:0]
PCIE_IRCOMP
PCIE_RBIAS
Intel® Quark™ SoC X1000
Datasheet
48
VOL
Enter S0
Running/
Unknown
Running/
Unknown
VOL
I
-
1.05V
PCIe
Off
Off
High-Z
High-Z
I/O
-
1.5V
Analog
Off
Off
Analog
Analog
I
-
1.5V
Analog
Off
Off
Analog
Analog
November 2014
Document Number: 329676-004US
Physical Interfaces—Intel® Quark™ SoC X1000
2.4
Ethernet Interface Signals
See Chapter 15.0, “10/100 Mbps Ethernet” for more details of the Ethernet interface
signals.
Table 9.
Ethernet Interface Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
RMII_REF_CLK
I
-
3.3V
CMOS3.3
Off
Off
Running/
Unknown
Running
MAC0_TXEN
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC0_TXDATA[1:0]
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC0_RXDV
I
20k(L)
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
MAC0_RXDATA[1:0]
I
-
3.3V
CMOS3.3
Off
Off
Unknown
Unknown
MAC0_MDC
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
MAC0_MDIO
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
MAC1_TXEN
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC1_TXDATA[1:0]
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC1_RXDV
I
20k(L)
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
MAC1_RXDATA[1:0]
I
-
3.3V
CMOS3.3
Off
Off
Unknown
Unknown
MAC1_MDC
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
MAC1_MDIO
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
2.5
USB 2.0 Interface Signals
See Chapter 16.0, “USB 2.0” for more details of the USB 2.0 interface signals.
Table 10.
USB 2.0 Interface Signals (Sheet 1 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
USBH0_OC_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
USBH1_OC_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
USBH0_PWR_EN
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
USBH1_PWR_EN
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
USBH0_DP
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBH0_DN
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBH1_DP
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBH1_DN
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBD_DP
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBD_DN
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
I
-
1.05V
USB
Off
Off
Running/
Unknown
Running/
Unknown
USB_CLK96P
November 2014
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Intel® Quark™ SoC X1000
Datasheet
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Intel® Quark™ SoC X1000—Physical Interfaces
Table 10.
USB 2.0 Interface Signals (Sheet 2 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
USB_CLK96N
I
-
1.05V
USB
Off
Off
Running/
Unknown
Running/
Unknown
OUSBCOMP_P18
O
-
1.8V
Analog
Off
Off
Analog
Analog
IUSBCOMP_N18
I
-
1.8V
Analog
Off
Off
Analog
Analog
2.6
Integrated Clock Interface Signals
See Chapter 7.0, “Clocking” for more details of the Integrated Clock interface signals.
Table 11.
Integrated Clock Interface Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
XTAL_IN
I
-
1.05V
Analog
Running
Running
Running
Running
XTAL_OUT
O
-
1.05V
Analog
Running
Running
Running
Running
CKSYS25OUT
O
-
3.3V
CMOS3.3
Running
Running
Running
Running
REF0_OUTCLK_P
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
REF0_OUTCLK_N
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
REF1_OUTCLK_P
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
REF1_OUTCLK_N
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
FLEX0_CLK
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
FLEX1_CLK
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
FLEX2_CLK
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
RMII_REF_CLK_OUT
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
OSC_COMP
I
-
1.5V
Analog
Analog
Analog
Analog
Analog
HPLL_REFCLK_P
I
-
1.05V
CMOS1.05
Off
Off
Running/
Unknown
Running/
Unknown
HPLL_REFCLK_N
I
-
1.05V
CMOS1.05
Off
Off
Running/
Unknown
Running/
Unknown
PAD_BYPASS_CLK
I
-
1.05V
CMOS1.05
Off
Off
Running/
Unknown
Running/
Unknown
2.7
SDIO/SD/MMC Signals
See Chapter 17.0, “SDIO/SD/eMMC” for more details of the interface signals, including
different options based on port configuration.
Table 12.
SD/SDIO/MMC Signals (Sheet 1 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
SD_DATA[7:0]
I/O
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SD_CMD
I/O
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SD_CLK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
Intel® Quark™ SoC X1000
Datasheet
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November 2014
Document Number: 329676-004US
Physical Interfaces—Intel® Quark™ SoC X1000
Table 12.
SD/SDIO/MMC Signals (Sheet 2 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I
20k(L)
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
SD_CD_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SD_LED
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SD_PWR
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SD_WP
2.8
High Speed UART Interface Signals
The SoC features two separate High Speed UARTs. However, only UART0 provides the
Modem Control pins DCD, DSR, DTR and RI.
See Chapter 18.0, “High Speed UART” for more details of the HSUART interface signals.
Table 13.
High Speed UART Signals
Default Buffer State
Signal Name
SIU0_CTS_B
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_DCD_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_DSR_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_DTR_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU0_RI_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_RTS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU0_RXD
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_TXD
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU1_CTS_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU1_RTS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU1_RXD
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU1_TXD
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
I2C* Interface Signals
2.9
See Chapter 19.0, “I2C* Controller/GPIO Controller” for more details of the I2C
Interface signals.
Table 14.
I2C* Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I2C_DATA
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
I2C_CLK
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
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Datasheet
51
Intel® Quark™ SoC X1000—Physical Interfaces
2.10
Legacy Serial Peripheral Interface (SPI) Signals
See Section 21.7 for more details of the SPI signals.
Table 15.
Legacy SPI Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
LSPI_MISO
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
LSPI_SS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
LSPI_SCK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
LSPI_MOSI
2.11
Serial Peripheral Interface (SPI)
See Chapter 20.0, “SPI Interface” for more details of the SPI signals.
Table 16.
SPI Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI0_MISO
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SPI0_SS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SPI0_SCK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI1_MOSI
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI1_MISO
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SPI1_SS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SPI1_SCK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI0_MOSI
Intel® Quark™ SoC X1000
Datasheet
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November 2014
Document Number: 329676-004US
Physical Interfaces—Intel® Quark™ SoC X1000
2.12
Real Time Clock (RTC) Interface Signals
See Section 21.10 for more details of the RTC interface signals.
Table 17.
Real Time Clock (RTC) Interface Signals
Default Buffer State
Signal Name
RTCX1
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I/O
-
<1V
Analog
Running
Running
Running
Running
RTCX2
I/O
-
<1V
Analog
Running
Running
Running
Running
IVCCRTCEXT
I/O
-
1.5V
Analog
Analog
Analog
Analog
Analog
RTCRST_B
I
-
3.3V
CMOS3.3
ViH
ViH
ViH
ViH
RTC_EXT_CLK_EN_B
I
-
3.3V
CMOS3.3
ViH/ViL
ViH/ViL
ViH/ViL
ViH/ViL
2.13
Power Management Signals
See Chapter 8.0, “Power Management” for more details of the Power Management
interface signals.
Table 18.
Power Management Interface Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
PWR_BTN_B
I
-
3.3V
CMOS3.3
ViH
ViH
ViH
ViH
RESET_BTN_B
I
20k(H)
3.3V
CMOS3.3
Off
Pull-up
Pull-up
Pull-up
S5_PG
I
-
3.3V
CMOS3.3
ViH
ViH
ViH
ViH
S3_PG
I
-
3.3V
CMOS3.3
ViL
ViH
ViH
ViH
S0_PG
I
-
3.3V
CMOS3.3
ViL
ViL
ViH
ViH
S0_1P0_PG
I
-
3.3V
CMOS3.3
ViL
ViL
ViH
ViH
S3_3V3_EN
O
Ext
3.3V
CMOS3.3
VOL
VOH
VOH
VOH
S3_1V5_EN
O
Ext
3.3V
CMOS3.3
VOL
VOH
VOH
VOH
S0_3V3_EN
O
Ext
3.3V
CMOS3.3
Pull-down
VOL
VOL
VOiH
S0_1V5_EN
O
Ext
3.3V
CMOS3.3
Pull-down
VoL
VoH
VoH
S0_1P0_EN
O
Ext
3.3V
CMOS3.3
Pull-down
VoL
VoH
VoH
ODRAM_PWROK
O
Ext
3.3V
CMOS3.3_OD
Pull-up
Pull-up
Pull-up
Pull-up
OSYSPWRGOOD
O
Ext
3.3V
CMOS3.3_OD
Pull-up
Pull-up
Pull-up
Pull-up
VNNSENSE
I/O
-
1.05V
Analog
Off
Off
Analog
Analog
VSSSENSE
I/O
-
GND
Analog
Off
Off
Analog
Analog
2.14
JTAG and Debug Interface Signals
See Chapter 22.0, “Debug Port and JTAG/TAP” for more details of the JTAG interface
signals.
November 2014
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Intel® Quark™ SoC X1000
Datasheet
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Intel® Quark™ SoC X1000—Physical Interfaces
Table 19.
JTAG and Debug Interface Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I
20k(L)
3.3V
CMOS3.3
Pull-down
Pull-down
Pull-down
Pull-down
TDI
I
20k(H)
3.3V
CMOS3.3
Pull-up
Pull-up
Pull-up
Pull-up
TDO
O
Ext
3.3V
CMOS3.3
Pull-up
Pull-up
Pull-up
Pull-up
TCK
TMS
I
20k(H)
3.3V
CMOS3.3
Pull-up
Pull-up
Pull-up
Pull-up
TRST_B
I
20k(H)
3.3V
CMOS3.3
Pull-up
Pull-up
Pull-up
Pull-up
PRDY_B
O
-
3.3V
CMOS3.3
Off
Off
VoH
VoH
PREQ_B
I
20k(H)
3.3V
CMOS3.3
Pull-up
Pull-up
Pull-up
Pull-up
2.15
Legacy Interface Signals
See Chapter 19.0, “I2C* Controller/GPIO Controller” and Chapter 21.0, “Legacy
Bridge” for more details of the legacy interface signals.
Table 20.
Legacy Interface Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
CLK14
I
-
3.3V
CMOS3.3
Off
Off
Unknown/
Running
Unknown/
Running
WAKE_B
I
20k(H)
3.3V
CMOS3.3_OD
Off
Pull-up
Pull-up
Pull-up
GPE_B
I
20k(H)
3.3V
CMOS3.3_OD
Off
Pull-up
Pull-up
Pull-up
THRM_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SMI_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
2.16
General Purpose I/O Interface Signals
All GPIOs default to inputs. GPIO_SUS[5:0] are suspend well GPIOs and remain
available in S3. The default buffer state of these GPIOs while in S3 and when entering
S0 from S3 is configuration dependent.
Table 21.
General Purpose I/O Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
GPIO_SUS[5:0]
I/O
-
3.3V
CMOS3.3
Off
GPIO[9:0]
I/O
-
3.3V
CMOS3.3
Off
Intel® Quark™ SoC X1000
Datasheet
54
Reset
Enter S0
Unknown
ViX
ViX/Unknown
Off
ViX
ViX
November 2014
Document Number: 329676-004US
Physical Interfaces—Intel® Quark™ SoC X1000
2.17
Power And Ground Pins
Table 22.
Power and Ground Pins (Sheet 1 of 2)
Signal Name
Nominal
Voltage
Lowest
Active State
Description/Notes
OVOUT_1P0_S5
Unused output from internal LDO. Leave this pin No Connect
VCC1P0_S5
Standard 1.0V Rail for S5 Logic
VCCAICLKCB_1P0
VCCAICLKDBUFF_1P0
ICLK Control Supply
1.0V
ICLK Differential Output Buffer Supply
VCCAICLKSSC1_1P0
ICLK SSC Supply
VCCDICLKDIG_1P0
VCCAICLKSFR_1P5
OVOUT_1P8_S5
VCC1P8_S5
VCC3P3_S5
VCCAICLKSE_3P3
OVOUT_1P0_S3
VCC1P0_S3
VCCCLKDDR_1P5
VCCDDR_1P5
S5
1.5V
ICLK SFR (for Oscillator, IPLL)
S5 1.8V Rail Standby LDO Output
1.8V
S5 1.8V CFIO Supply
S5 3.3V Rail Standby LDO Input
3.3V
ICLK Single Ended Output Buffer Supply
S3 1.0V Rail Standby LDO Output
1.0V
Standard 1.0V Rail for S3 logic
DDR IO Clock Analog Thick Gate Isolated Quiet Supply
1.5V
DDR IO Analog Thick Gate Supply
OVOUT_1P8_S3
VCC1P8_S3
ICLK Digital Supply
S3 1.8V Rail Standby LDO Output
1.8V
S3
S3 1.8V CFIO Supply
VCCAUSB_1P8_S3
USB 1.8V Supply
VCC3P3_S3
S3 3.3V Rail Standby LDO Input
VCC3P3_USB_S3
3.3V
November 2014
Document Number: 329676-004US
USB 3.3V Supply
The USB PHY resides in the S3 power domain. However, from a
functional point of view USB is only active in S0.
Intel® Quark™ SoC X1000
Datasheet
55
Intel® Quark™ SoC X1000—Physical Interfaces
Table 22.
Power and Ground Pins (Sheet 2 of 2)
Signal Name
Nominal
Voltage
Lowest
Active State
Description/Notes
VCC1P0_S0
Standard 1.0V Rail for HPLL (Host PLL) and USB Logic
VCCACLKDDR_1P0
DDR IO Digital Clock Isolated Quiet Supply
VCCADDR_1P0
DDR IO Digital Supply
VCCADLLDDR_1P0
VCCAPCIE_1P0
DDR IO Digital Isolated Quiet Supply
1.0V
PCIe Analog Supply
VCCAVISA_1P0
VISA IO Analog Supply
VCCPLLDDR_1P0
DDR IO Digital PLL High Voltage
VNN
Default 1.0V Standard Cell Rail including Core and Uncore Logic
OVOUT_1P05_S0
S0 1.05V Rail Standby LDO Output
VCCFHVSOC_1P05
1.05V
VCCFSOC_1P05
VCC1P5_S0
VCCSFRPLLDDR_1P5
S0
SoC Fuses Supply
Fuse Digital Sensing
PCIe Band-Gap Supply
1.5V
DDR IO PLL High Voltage
OVOUT_1P8_S0
S0 1.8V Rail Standby LDO Output
OVOUT_1P8_SLDO
VCC1P8_S0
S0 1.8V Rail Standby LDO Output (Currently Unused)
1.8V
S0 1.8V CFIO Supply
VCCAA_1P8
1.8V Analog Supply
VCCAUSB_1P8
USB 1.8V Analog Supply
VCC3P3_A
VCCRTC3P3
VSS
VSSA_USB
2.18
S0 3.3V Rail Standby LDO Input (Currently Unused)
3.3V
VCC3P3_S0
S0 3.3V Rail Standby LDO Input
3.3V
G3
0V
-
RTC Well Supply
To be active in G3, the source supply for VCCRTC3P3 must be a 3.0V
coin cell battery or equivalent. If the target application does not
require the RTC to be operational in G3, VCCRTC3P3 should be
supplied from a 3.3V supply that is active in S5.
Ground
USB Low-Noise Ground
Hardware Straps
The pins used for hardware straps are output pins in functional mode.Initially during a
cold boot, these strap pins are configured as inputs. These pins remain inputs until the
external pull up or pull down values are sampled during S0 Power OK. Once sampled,
the pins are enabled as outputs only.
Intel® Quark™ SoC X1000
Datasheet
56
November 2014
Document Number: 329676-004US
Physical Interfaces—Intel® Quark™ SoC X1000
Table 23.
Hardware Straps
Signal Name
SPI0_MOSI
{SPI0_SCK,
SPI1_MOSI}
LSPI_MOSI
{MAC0_TXDATA[1],
MAC0_TXDATA[0],
MAC1_TXDATA[1]
MAC1_TXDATA[0]
{LSPI_SCK, SD_CLK}
PWR_BTN_B
November 2014
Document Number: 329676-004US
Default
1b
11b
Strap Description
Reports the Strap status of Recovery Mode:
0 = Recovery Mode
1 = Normal Mode
Defines Memory Device Density
00b = Reserved
01b = 1Gb
10b = 2Gb
11b = 4Gb
1b
Defines the Number of Ranks Enabled
0b = 1 Rank
1b = 2 Ranks
010b
Frequency SKU Power Optimize Mode
[2:1] CPU Clock/DDR Clock
00b = Reserved
01b = 400MHz/800MHz
10b = 200MHz/800MHz
11b = 100MHz/800MHz
[0]
0b = Low Latency
1b = Low Power
0b
00b
0b
0b = FFF0_0000h
1b = FFD0_0000h
SDIO Slot Type
00b = Removable Card Slot
01b = Embedded Slot for One Device
10b = Shared Bus Slot
11b = Reserved
Power Button Disable
0b = Power Button Disabled
1b = Power Button Enabled
Intel® Quark™ SoC X1000
Datasheet
57
Intel® Quark™ SoC X1000—Physical Interfaces
§§
Intel® Quark™ SoC X1000
Datasheet
58
November 2014
Document Number: 329676-004US
Ballout and Package Information—Intel® Quark™ SoC X1000
3.0
Ballout and Package Information
The Intel® Quark™ SoC X1000 package comes in a 373 ball, 15mm x 15mm FCBGA based on a
0.593 mm pitch.
3.1
Package Diagram
Figure 4.
Intel® Quark™ SoC X1000 Package Dimensions
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
59
Intel® Quark™ SoC X1000—Ballout and Package Information
3.2
Ball Listings
Table 24. Alphabetical Ball Listing
C7
I2C_CLK
E32
VSS
A2
RESERVED
C10
SMI_B
E35
VSS
A4
S0_PG
C12
MAC1_TXEN
F2
S0_1V5_EN
A5
WAKE_B
C14
MAC1_RXDV
F4
S0_1V0_EN
A7
VSS
C16
RMII_REF_CLK
F6
VSS
A10
VSS
C18
MAC0_RXDV
F30
VCC3P3_A
A12
VSS
C21
MAC0_TXEN
F32
VSS
A14
VSS
C23
SD_DATA[0]
F34
USBH0_PWR_EN
A16
VSS
C26
SD_DATA[3]
G1
VSS
A18
VSS
C28
SD_DATA[7]
G3
RTCX2
A21
MAC0_TXDATA[0]
C35
VSS
G7
S5_PG
A23
VSS
D2
S0_1P0_PG
G11
GPIO_SUS[0]
A26
SD_DATA[4]
D5
VSS
G12
VSS
A28
VSS
D6
RESET_BTN_B
G15
GPIO_SUS[4]
A31
VSS
D9
CLK14
G17
SD_PWR
A32
VSS
D11
MAC1_MDIO
G19
SD_WP
A34
VSS
D13
MAC1_RXDATA[0]
G33
USBH1_PWR_EN
B1
RESERVED
D15
MAC1_TXDATA[0]
G35
USBH0_OC_B
B2
PREQ_B
D17
MAC0_MDC
H6
REF1_OUTCLK_N
B4
GPE_B
D20
MAC0_RXDATA[0]
H17
VSS
B6
I2C_DATA
D22
MAC0_TXDATA[1]
H30
VSSSENSE
B9
THRM_B
D24
SD_DATA[1]
J2
RTCX1
B11
MAC1_MDC
D27
SD_DATA[5]
J4
S3_PG
B13
MAC1_RXDATA[1]
D29
VSS
J6
REF1_OUTCLK_P
B15
MAC1_TXDATA[1]
D31
VSS
J7
RTCRST_B
B17
MAC0_MDIO
D33
VSS
J11
IVCCRTCEXT
B20
MAC0_RXDATA[1]
E1
VCCRTC_3P3
J12
GPIO_SUS[2]
B22
SD_CMD
E4
S0_3V3_EN
J15
GPIO_SUS[5]
B24
SD_DATA[2]
E7
PRDY_B
J19
SD_CLK
B27
SD_DATA[6]
VSS
VSS
RTC_EXT_CLK_EN_
B
J25
B29
E11
J30
VNNSENSE
VSS
E12
GPIO_SUS[1]
J32
USBH1_OC_B
VSS
E15
GPIO_SUS[3]
J34
OUSBCOMP_P18
VSS
E17
SD_LED
K1
S3_1V5_EN
VSS
E19
SD_CD_B
K3
S3_3V3_EN
B31
B33
B35
C1
Intel® Quark™ SoC X1000
Datasheet
60
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000—Ballout and Package Information
K11
OVOUT_1P8_S5
P11
VCCDICLKDIG_1P0
K13
VCC1P8_S5
P13
VSS
K14
VCC3P3_S3
P14
VCC1P0_S3
K16
VCC3P3_USB_S3
P16
VSSA_USB
K18
VCC1P8_S3
P18
OVOUT_1P8_S0
K20
VCCAUSB_1P8_S3
P20
VCC1P8_S0
K22
VCCAA_1P8
P22
VCCAUSB_1P8
K24
OVOUT_1P8_SLDO
P24
OVOUT_1P05_S0
K33
IUSBCOMP_N18
P27
VSS
K35
VSS
P29
USBH1_DP
L2
PWR_BTN_B
P30
USBH1_DN
L4
TRST_B
R1
TDO
L32
RESERVED
R3
ODRAM_PWROK
L34
RESERVED
R10
VCCAICLKSFR_1P5
M1
VSS
R26
VCCFSOC_1P05
M3
TCK
R33
GPIO[2]
M5
VSS
R35
GPIO[3]
M6
REF0_OUTCLK_N
T2
OSYSPWRGOOD
M8
REF0_OUTCLK_P
T4
M11
VSS
RMII_REF_CLK_OU
T
M13
VSS
T11
VCCAICLKCB_1P0
M14
OVOUT_1P0_S3
T13
VCC1P0_S5
M16
VSS
T14
OVOUT_1P0_S5
M18
OVOUT_1P8_S3
T16
VSS
M22
VSS
T18
VCCAVISA_1P0
M28
VSS
T20
VCC1P8_S0
M29
USBD_DP
T22
VSS
M31
USBD_DN
T24
VCCFHVSOC_1P05
M33
USB_CLK96N
T32
GPIO[4]
M35
USB_CLK96P
T34
GPIO[5]
N2
TMS
U1
VSS
N4
TDI
U3
FLEX2_CLK
N32
GPIO[0]
U33
GPIO[6]
N34
GPIO[1]
U35
VSS
P5
VCC3P3_S5
V2
FLEX1_CLK
P7
VCCAICLKSE_3P3
V4
FLEX0_CLK
P9
VSS
V5
HPLL_REFCLK_N
V7
HPLL_REFCLK_P
Intel® Quark™ SoC X1000
Datasheet
61
V9
VSS
V11
VCCAICLKDBUFF_1
P0
V13
VCCAICLKSSC1_1P
0
V14
VCC1P0_S0
V16
VCC1P0_S0
V18
VNN
V20
VNN
V22
VSS
V27
VSS
V29
USBH0_DN
V30
USBH0_DP
V32
GPIO[7]
V34
GPIO[8]
W1
VSS
W3
OSC_COMP
W5
RESERVED
W7
CKSYS25OUT
W9
TS_IREF_N
W27
VSS
W29
SIU0_DTR_B
W30
SIU0_RTS_B
W33
GPIO[9]
W35
SIU0_TXD
Y11
VSS
Y13
VSS
Y14
VCCAPCIE_1P0
Y16
VNN
Y18
VNN
Y20
VNN
Y22
VSS
AA2
XTAL_IN
AA4
RESERVED
AA10
RESERVED
AA26
VCC3P3_S0
AA32
SIU0_DSR_B
AA34
SIU0_RXD
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000—Ballout and Package Information
AB1
XTAL_OUT
AD35
VSS
AK2
PCIE_PERP_1
AB3
VSS
AE2
PCIE_REFCLKP
AK4
PCIE_PERN_1
AB11
VSS
AE4
PCIE_REFCLKN
AK7
DDR3_DQS[0]
AB13
VCCACLKDDR_1P0
AE10
RESERVED
AK11
DDR3_DQ[1]
AB14
VCCADDR_1P0
AE26
VSS
AK12
DDR3_DQ[7]
AB16
VSS
AE32
SPI0_SCK
AK15
VSS
AB18
VNN
AE34
SPI0_SS_B
AK17
RESERVED
AB20
VNN
AF11
RESERVED
AK19
RESERVED
AB24
VCC3P3_S0
AF13
VSS
AK23
DDR3_CMDPU
AB33
SIU1_CTS_B
AF20
VSS
AK25
AB35
VSS
AF22
VSS
DDR3_IDRAM_PWR
OK
AC2
VSS
AF24
VSS
AK29
VSS
AC4
PAD_BYPASS_CLK
AG1
VSS
AK32
LSPI_MOSI
AC5
TS_TDC
AG3
VSS
AK34
SPI1_MISO
AC7
TS_TDA
AG6
DDR3_DQ[4]
AL6
VSS
AC9
VSS
AG30
DDR3_CK[1]
AL11
DDR3_DQ[0]
AC27
SIU0_DCD_B
AG33
SPI0_MISO
AL12
DDR3_DM[0]
AC29
VSS
AG35
SPI0_MOSI
AL15
DDR3_DQ[2]
AC30
VSS
AH2
PCIE_PETN_1
AL17
RESERVED
AC32
SIU1_TXD
AH4
PCIE_PETP_1
AL19
DDR3_ODTPU
AC34
SIU1_RXD
AH7
DDR3_DQSB[0]
AL23
VSS
AD1
PCIE_PETN_0
AH11
VSS
AL25
DDR3_DRAMRSTB
AD3
PCIE_PETP_0
AH12
DDR3_DQ[6]
AL30
DDR3_CKB[0]
AD5
VCC1P5_S0
AH15
DDR3_DQ[3]
AM1
VSS
AD6
VSS
AH17
VSS
AM2
PCIE_PERP_0
AD8
VSS
AH19
RESERVED
AM4
VSS
AD11
RESERVED
AH23
DDR3_DQPU
AM7
VSS
AD13
VCCPLLDDR_1P0
DDR3_VREF
AD14
VCCADLLDDR_1P0
DDR3_ISYSPWRGO
OD
AM29
AH25
AM32
VSS
AD16
VSS
AH29
DDR3_CKB[1]
AM33
LSPI_SS_B
AD18
VSS
AH32
SPI1_MOSI
AM35
LSPI_SCK
AD20
VSS
AH34
SPI1_SCK
AN1
PCIE_PERN_0
AD24
VCC3P3_S0
AJ1
PCIE_IRCOMP
AN5
DDR3_DQ[13]
AD28
SIU0_RI_B
AJ3
PCIE_RBIAS
AN6
DDR3_DQS[1]
AD29
SIU0_CTS_B
AJ6
DDR3_DQ[5]
AN9
VSS
VCCSFRPLLDDR_1
P5
AJ30
DDR3_CK[0]
AN11
DDR3_CKE[0]
AD31
AJ33
SPI1_SS_B
AN13
VSS
AD33
SIU1_RTS_B
AJ35
VSS
AN15
DDR3_MA[11]
Intel® Quark™ SoC X1000
Datasheet
62
November 2014
Document Number: 329676-004US
Ballout and Package Information—Intel® Quark™ SoC X1000
AN17
DDR3_MA[7]
AT5
DDR3_DQ[12]
AN20
DDR3_MA[5]
AT7
VSS
AN22
DDR3_MA[1]
AT10
DDR3_DQ[14]
AN24
DDR3_MA[10]
AT12
VCCDDR_1P5
AN27
VSS
AT14
DDR3_MA[15]
AN29
DDR3_CASB
AT16
VCCDDR_1P5
AN31
DDR3_CSB[0]
AT18
VCCDDR_1P5
AN35
LSPI_MISO
AT21
DDR3_MA[4]
AP2
VSS
AT23
VCCDDR_1P5
AP4
DDR3_DQ[9]
AT26
DDR3_BS[1]
AP7
DDR3_DM[1]
AT28
VCCCLKDDR_1P5
AP10
DDR3_DQ[11]
AT31
DDR3_ODT[0]
AP12
DDR3_CKE[1]
AT32
DDR3_ODT[1]
AP14
DDR3_MA[14]
AT34
RESERVED
AP16
DDR3_MA[9]
NOTE: The following balls are
No Connect (NC):
AP18
VSS
M26
AP21
DDR3_MA[3]
E25
AP23
VSS
AP26
DDR3_BS[0]
AP28
DDR3_WEB
AP31
DDR3_CSB[1]
AP33
VSS
M20
AR1
RESERVED
AD22
AR6
DDR3_DQSB[1]
AR9
DDR3_DQ[10]
AR11
DDR3_DQ[15]
AR13
DDR3_BS[2]
AR15
DDR3_MA[12]
AR17
DDR3_MA[8]
AR20
DDR3_MA[6]
AR22
DDR3_MA[2]
AR24
DDR3_MA[0]
AR27
DDR3_RASB
AR29
DDR3_MA[13]
AR35
RESERVED
AT2
RESERVED
AT3
DDR3_DQ[8]
November 2014
Document Number: 329676-004US
J23
M24
Y24
G25
AF16
G23
AF14
AB22
V24
E23
G29
AF18
J29
E29
Intel® Quark™ SoC X1000
Datasheet
63
Intel® Quark™ SoC X1000—Ballout and Package Information
Table 25. Alphabetical Signal Listing
DDR3_DQSB[0]
AH7
GPIO_SUS[5]
J15
DDR3_DQSB[1]
AR6
GPIO[0]
N32
DDR3_DRAMRSTB
AL25
GPIO[1]
N34
DDR3_IDRAM_PWROK
AK25
GPIO[2]
R33
AR13
DDR3_ISYSPWRGOO
D
AH25
DDR3_CASB
AN29
DDR3_MA[0]
AR24
DDR3_CK[0]
AJ30
DDR3_MA[1]
AN22
DDR3_CK[1]
AG30
DDR3_MA[10]
AN24
DDR3_CKB[0]
AL30
DDR3_MA[11]
AN15
DDR3_CKB[1]
AH29
DDR3_MA[12]
AR15
DDR3_CKE[0]
AN11
DDR3_MA[13]
AR29
DDR3_CKE[1]
AP12
DDR3_MA[14]
AP14
DDR3_CMDPU
AK23
DDR3_MA[15]
AT14
DDR3_CSB[0]
AN31
DDR3_MA[2]
AR22
DDR3_CSB[1]
AP31
DDR3_MA[3]
AP21
DDR3_DM[0]
AL12
DDR3_MA[4]
AT21
DDR3_DM[1]
AP7
DDR3_MA[5]
AN20
DDR3_DQ[0]
AL11
DDR3_MA[6]
AR20
DDR3_DQ[1]
AK11
DDR3_MA[7]
AN17
DDR3_DQ[10]
AR9
DDR3_MA[8]
AR17
DDR3_DQ[11]
AP10
DDR3_MA[9]
AP16
DDR3_DQ[12]
AT5
DDR3_ODT[0]
AT31
DDR3_DQ[13]
AN5
DDR3_ODT[1]
AT32
DDR3_DQ[14]
AT10
DDR3_ODTPU
AL19
DDR3_DQ[15]
AR11
DDR3_RASB
AR27
DDR3_DQ[2]
AL15
DDR3_VREF
AM29
DDR3_DQ[3]
AH15
DDR3_WEB
AP28
DDR3_DQ[4]
AG6
FLEX0_CLK
V4
DDR3_DQ[5]
AJ6
FLEX1_CLK
V2
DDR3_DQ[6]
AH12
FLEX2_CLK
U3
DDR3_DQ[7]
AK12
GPE_B
B4
DDR3_DQ[8]
AT3
GPIO_SUS[0]
G11
DDR3_DQ[9]
AP4
GPIO_SUS[1]
E12
DDR3_DQPU
AH23
GPIO_SUS[2]
J12
DDR3_DQS[0]
AK7
GPIO_SUS[3]
E15
DDR3_DQS[1]
AN6
GPIO_SUS[4]
G15
CKSYS25OUT
W7
CLK14
D9
DDR3_BS[0]
AP26
DDR3_BS[1]
AT26
DDR3_BS[2]
Intel® Quark™ SoC X1000
Datasheet
64
GPIO[3]
R35
GPIO[4]
T32
GPIO[5]
T34
GPIO[6]
U33
GPIO[7]
V32
GPIO[8]
V34
GPIO[9]
W33
HPLL_REFCLK_N
V5
HPLL_REFCLK_P
V7
I2C_CLK
C7
I2C_DATA
B6
IUSBCOMP_N18
K33
IVCCRTCEXT
J11
LSPI_MISO
AN35
LSPI_MOSI
AK32
LSPI_SCK
AM35
LSPI_SS_B
AM33
MAC0_MDC
D17
MAC0_MDIO
B17
MAC0_RXDATA[0]
D20
MAC0_RXDATA[1]
B20
MAC0_RXDV
C18
MAC0_TXDATA[0]
A21
MAC0_TXDATA[1]
D22
MAC0_TXEN
C21
MAC1_MDC
B11
MAC1_MDIO
D11
MAC1_RXDATA[0]
D13
MAC1_RXDATA[1]
B13
MAC1_RXDV
C14
MAC1_TXDATA[0]
D15
MAC1_TXDATA[1]
B15
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Ballout and Package Information—Intel® Quark™ SoC X1000
MAC1_TXEN
C12
RESERVED
AK17
SD_DATA[5]
D27
ODRAM_PWROK
R3
RESERVED
AT2
SD_DATA[6]
B27
OSC_COMP
W3
RESERVED
AR1
SD_DATA[7]
C28
OSYSPWRGOOD
T2
RESERVED
AD11
SD_LED
E17
OUSBCOMP_P18
J34
RESERVED
AF11
SD_PWR
G17
OVOUT_1P0_S3
M14
RESERVED
A2
SD_WP
G19
OVOUT_1P0_S5
T14
RESERVED
B1
SIU0_CTS_B
AD29
OVOUT_1P05_S0
P24
RESERVED
AA10
SIU0_DCD_B
AC27
OVOUT_1P8_S0
P18
RESERVED
AE10
SIU0_DSR_B
AA32
OVOUT_1P8_S3
M18
RESERVED
AA4
SIU0_DTR_B
W29
OVOUT_1P8_S5
K11
RESERVED
W5
SIU0_RI_B
AD28
OVOUT_1P8_SLDO
K24
RESERVED
L32
SIU0_RTS_B
W30
PAD_BYPASS_CLK
AC4
RESERVED
L34
SIU0_RXD
AA34
PCIE_IRCOMP
AJ1
RESET_BTN_B
D6
SIU0_TXD
W35
PCIE_PERN_0
AN1
RMII_REF_CLK
C16
SIU1_CTS_B
AB33
PCIE_PERN_1
AK4
RMII_REF_CLK_OUT
T4
SIU1_RTS_B
AD33
PCIE_PERP_0
AM2
RTC_EXT_CLK_EN_B
E11
SIU1_RXD
AC34
PCIE_PERP_1
AK2
RTCRST_B
J7
SIU1_TXD
AC32
PCIE_PETN_0
AD1
RTCX1
J2
SMI_B
C10
PCIE_PETN_1
AH2
RTCX2
G3
SPI0_MISO
AG33
PCIE_PETP_0
AD3
S0_1P0_PG
D2
SPI0_MOSI
AG35
PCIE_PETP_1
AH4
S0_1V0_EN
F4
SPI0_SCK
AE32
PCIE_RBIAS
AJ3
S0_1V5_EN
F2
SPI0_SS_B
AE34
PCIE_REFCLKN
AE4
S0_3V3_EN
E4
SPI1_MISO
AK34
PCIE_REFCLKP
AE2
S0_PG
A4
SPI1_MOSI
AH32
PRDY_B
E7
S3_1V5_EN
K1
SPI1_SCK
AH34
PREQ_B
B2
S3_3V3_EN
K3
SPI1_SS_B
AJ33
PWR_BTN_B
L2
S3_PG
J4
TCK
M3
REF0_OUTCLK_N
M6
S5_PG
G7
TDI
N4
REF0_OUTCLK_P
M8
SD_CD_B
E19
TDO
R1
REF1_OUTCLK_N
H6
SD_CLK
J19
THRM_B
B9
REF1_OUTCLK_P
J6
SD_CMD
B22
TMS
N2
RESERVED
AR35
SD_DATA[0]
C23
TRST_B
L4
RESERVED
AT34
SD_DATA[1]
D24
TS_IREF_N
W9
RESERVED
AH19
SD_DATA[2]
B24
TS_TDA
AC7
RESERVED
AK19
SD_DATA[3]
C26
TS_TDC
AC5
RESERVED
AL17
SD_DATA[4]
A26
USB_CLK96N
M33
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Datasheet
65
Intel® Quark™ SoC X1000—Ballout and Package Information
USB_CLK96P
M35
VCCAUSB_1P8
P22
VSS
C1
USBD_DN
M31
VCCAUSB_1P8_S3
K20
VSS
C35
USBD_DP
M29
VCCAVISA_1P0
T18
VSS
D5
USBH0_DN
V29
VCCCLKDDR_1P5
AT28
VSS
D29
USBH0_DP
V30
VCCDDR_1P5
AT12
VSS
D31
USBH0_OC_B
G35
VCCDDR_1P5
AT16
VSS
D33
USBH0_PWR_EN
F34
VCCDDR_1P5
AT18
VSS
E32
USBH1_DN
P30
VCCDDR_1P5
AT23
VSS
E35
USBH1_DP
P29
VCCDICLKDIG_1P0
P11
VSS
F6
USBH1_OC_B
J32
VCCFHVSOC_1P05
T24
VSS
F32
USBH1_PWR_EN
G33
VCCFSOC_1P05
R26
VSS
G1
VCC1P0_S0
V14
VCCPLLDDR_1P0
AD13
VSS
G12
VCC1P0_S0
V16
VCCRTC_3P3
E1
VSS
H17
VCC1P0_S3
P14
VCCSFRPLLDDR_1P5
AD31
VSS
J25
VCC1P0_S5
T13
VNN
V18
VSS
K35
VCC1P5_S0
AD5
VNN
V20
VSS
M1
VCC1P8_S0
P20
VNN
Y16
VSS
M5
VCC1P8_S0
T20
VNN
Y18
VSS
M11
VCC1P8_S3
K18
VNN
Y20
VSS
M13
VCC1P8_S5
K13
VNN
AB18
VSS
M16
VCC3P3_A
F30
VNN
AB20
VSS
M22
VCC3P3_S0
AA26
VNNSENSE
J30
VSS
M28
VCC3P3_S0
AB24
VSS
A7
VSS
P9
VCC3P3_S0
AD24
VSS
A10
VSS
P13
VCC3P3_S3
K14
VSS
A12
VSS
P27
VCC3P3_S5
P5
VSS
A14
VSS
T16
VCC3P3_USB_S3
K16
VSS
A16
VSS
T22
VCCAA_1P8
K22
VSS
A18
VSS
U1
VCCACLKDDR_1P0
AB13
VSS
A23
VSS
U35
VCCADDR_1P0
AB14
VSS
A28
VSS
V9
VCCADLLDDR_1P0
AD14
VSS
A31
VSS
V22
VCCAICLKCB_1P0
T11
VSS
A32
VSS
V27
VCCAICLKDBUFF_1P0
V11
VSS
A34
VSS
W1
VCCAICLKSE_3P3
P7
VSS
B29
VSS
W27
VCCAICLKSFR_1P5
R10
VSS
B31
VSS
Y11
VCCAICLKSSC1_1P0
V13
VSS
B33
VSS
Y13
VCCAPCIE_1P0
Y14
VSS
B35
VSS
Y22
Intel® Quark™ SoC X1000
Datasheet
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November 2014
Document Number: 329676-004US
Ballout and Package Information—Intel® Quark™ SoC X1000
VSS
AB3
VSS
AP23
VSS
AB11
VSS
AP33
VSS
AB16
VSS
AT7
VSS
AB35
VSSA_USB
P16
VSS
AC2
VSSSENSE
H30
VSS
AC9
WAKE_B
A5
VSS
AC29
XTAL_IN
AA2
VSS
AC30
XTAL_OUT
AB1
VSS
AD6
VSS
AD8
VSS
AD16
VSS
AD18
VSS
AD20
VSS
AD35
VSS
AE26
VSS
AF13
VSS
AF20
VSS
AF22
VSS
AF24
VSS
AG1
VSS
AG3
VSS
AH11
VSS
AH17
VSS
AJ35
VSS
AK15
VSS
AK29
VSS
AL6
VSS
AL23
VSS
AM1
VSS
AM4
VSS
AM7
VSS
AM32
VSS
AN9
VSS
AN13
VSS
AN27
VSS
AP2
VSS
AP18
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Datasheet
67
Intel® Quark™ SoC X1000—Ballout and Package Information
Intel® Quark™ SoC X1000
Datasheet
68
November 2014
Document Number: 329676-004US
Electrical Characteristics—Intel® Quark™ SoC X1000
4.0
Electrical Characteristics
This chapter contains the DC and AC characteristics for Intel® Quark™ SoC X1000. AC
timing diagrams are included.
4.1
Absolute Maximum Ratings
Table 26 specifies the absolute maximum and minimum ratings of the Intel® Quark™
SoC X1000 processor. At conditions outside of the functional operating condition limits,
but within the absolute maximum and minimum ratings, neither functionality nor longterm reliability can be expected. If a device is returned to conditions within the
functional operating limits after having been subjected to conditions outside these
limits (but within the absolute maximum and minimum ratings) the device may be
functional, but with its lifetime degraded depending on exposure to conditions
exceeding the functional operating condition limits.
At conditions exceeding the absolute maximum and minimum ratings, neither
functionality nor long-term reliability can be expected. Moreover, if a device is
subjected to these conditions for any length of time, it will either not function or its
reliability will be severely degraded when returned to conditions within the functional
operating condition limits.
Although the SoC contains protective circuitry to resist damage from Electrostatic
Discharge (ESD), precautions should always be taken to avoid high static voltages or
electric fields.
All voltage values are given with respect to VSS.
Table 26.
Intel® Quark™ SoC X1000 Absolute Maximum Voltage Ratings (Sheet 1 of 2)
Parameter
Minimum
Limits
Maximum
Limits
Temperature
Junction Temperature (C)
0
110
-55
125
3.3V Supply Voltage (V)
—
3.7
1.8V Supply Voltage (V)
—
2.0
1.5V Supply Voltage (V)
—
1.65
1.05V Supply Voltage (V)
—
1.3
1.0V Supply Voltage (V)
—
1.3
—
3.7 V
Storage Temperature Range (C)
Supplies
Signals
Voltage on any 3.3 V Pin (V)
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Datasheet
69
Intel® Quark™ SoC X1000—Electrical Characteristics
Table 26.
Intel® Quark™ SoC X1000 Absolute Maximum Voltage Ratings (Sheet 2 of 2)
Minimum
Limits
Parameter
Maximum
Limits
Voltage on any 1.8 V Pin (V)
—
2.0
Voltage on any 1.5 V Pin (V)
—
1.65
Voltage on any 1.0V Tolerant Pin (V)
—
1.3
4.2
Recommended Power Supply Ranges
Table 27 shows the recommended operating voltage ranges for each SoC supply pin.
Typically total tolerance (DC+AC +Ripple) is +/- 5% of the nominal value unless
otherwise stated.
Table 27.
Power Supply Rail Ranges (Sheet 1 of 2)
Package Ball
Description
Min (V)
Nom (V)
Max (V)
Notes
VCC3P3_S5
S5 3.3V rail Standby LDO input
3.20
3.30
3.40
+/-3%
VCC3P3_S3
S3 3.3V rail Standby LDO input
3.20
3.30
3.40
+/-3%
VCC3P3_S0
S0 3.3V rail Standby LDO input
3.20
3.30
3.40
+/-3%
VCC3P3_A
S0 3.3V rail Standby LDO input
3.20
3.30
3.40
+/-3%
Default 1.0V standard cell rail including Core
and Uncore logic
0.95
1.00
1.10
VCC1P0_S3
Standard 1.0V rail for S3 logic
0.95
1.00
1.05
VCC1P0_S5
Standard 1.0V rail for S5 logic
0.95
1.00
1.05
+/-5%
DDR IO digital PLL high voltage
0.95
1.00
1.05
+/-5%
VNN
VCCPLLDDR_1P0
Active in state
S0 only
+/-5%
VCCADLLDDR_1P0
DDR IO digital isolated quiet supply
0.95
1.00
1.05
+/-5%
VCCACLKDDR_1P0
DDR IO digital clock isolated quiet supply
0.95
1.00
1.05
+/-5%
DDR IO Digital supply
0.95
1.00
1.05
+/-5%
DDR IO analog thick gate supply
1.42
1.50
1.57
+/-5%
DDR IO PLL high voltage
1.42
1.50
1.57
+/-5%
DDR IO clock analog thick gate isolated quiet
supply
1.42
1.50
1.57
+/-5%
VCCADDR_1P0
VCCDDR_1P5
VCCSFRPLLDDR_1P5
VCCCLKDDR_1P5
VCCAPCIE_1P0
PCIe analog supply
0.95
1.00
1.05
+/-5%
VCC1P5_S0
PCIe band-gap supply
1.42
1.50
1.57
+/-5%
VCC1P8_S0
S0 1.8V CFIO supply
1.71
1.80
1.89
+/-5%
VCC1P8_S3
S3 1.8V CFIO supply
1.71
1.80
1.89
+/-5%
S5 1.8V CFIO supply
1.71
1.80
1.89
+/-5%
RTC well supply
2.00
-
3.40
+/-5%
VCC1P8_S5
VCCRTC_3P3
VCCAUSB_1P8_S3
VCC3P3_USB_S3
VCCAUSB_1P8
USB 1.8V analog supply - suspend rail
1.71
1.80
1.89
+/-5%
USB 3.3V supply - suspend rail
3.13
3.30
3.46
+/-5%
USB 1.8V supply
1.71
1.80
1.89
+/-5%
VSSA_USB
USB low-noise ground
0.00
0.00
0.00
+/-5%
VCCAA_1P8
1.8V analog supply
1.71
1.80
1.89
VCC1P0_S0
Intel® Quark™ SoC X1000
Datasheet
70
Standard 1.0V rail for HPLL (host PLL) and
USB logic
0.95
1.00
1.05
+/-5%
Active in S0only; can in
general be
connected to
VNN
November 2014
Document Number: 329676-004US
Electrical Characteristics—Intel® Quark™ SoC X1000
Table 27.
Power Supply Rail Ranges (Sheet 2 of 2)
Package Ball
VCCAVISA_1P0
VCCFHVSOC_1P05
Description
VISA IO analog supply
SoC Fuses supply (sensing)
Min (V)
Nom (V)
Max (V)
Notes
0.95
1.00
1.05
+/-5%
1.0
1.05
1.10
+/-5%
VCCFSOC_1P05
Fuse digital sensing
1.0
1.05
1.10
+/-5%
VCCAICLKCB_1P0
ICLK control supply
0.95
1.00
1.05
+/-5%
VCCAICLKSSC1_1P0
ICLK SSC supply
0.95
1.00
1.05
+/-5%
ICLK differential output buffer supply
0.95
1.00
1.05
+/-5%
VCCDICLKDIG_1P0
ICLK digital supply
0.95
1.00
1.05
+/-5%
VCCAICLKSFR_1P5
ICLK SFR (for oscillator, IPLL)
1.42
1.50
1.57
+/-5%
ICLK single ended output buffer supply
3.13
3.30
3.46
+/-5%
VCCAICLKDBUFF_1P0
VCCAICLKSE_3P3
4.3
Maximum Supply Current
Table 28.
Maximum Supply Current: ICC Max (Sheet 1 of 2)
Voltage Rail
Voltage
(V)
ICCMax (mA)
VCC3P3_S5
3.3
180
VCC3P3_S3
3.3
280
VCC3P3_S0
3.3
680
VCC3P3_A
3.3
5
VNN
1.0
480
VCC1P0_S3
1.0
70
VCC1P0_S5
1.0
40
VCCPLLDDR_1P0
1.0
25
VCCADLLDDR_1P0
1.0
100
VCCACLKDDR_1P0
1.0
15
VCCADDR_1P0
1.0
300
VCCDDR_1P5
1.5
580
VCCSFRPLLDDR_1P5
1.5
35
VCCCLKDDR_1P5
1.5
90
VCCAPCIE_1P0
1.0
330
VCC1P5_S0
1.5
120
VCC1P8_S0
1.8
50
VCC1P8_S3
1.8
110
VCC1P8_S5
1.8
15
VCCRTC_3P3
3.3
3
VCCRTC_3P3 (Battery)
3.0
6uA
VCCAUSB_1P8_S3
1.8
20
VCC3P3_USB_S3
3.3
40
VSSA_USB
0.0
20
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Datasheet
71
Intel® Quark™ SoC X1000—Electrical Characteristics
Table 28.
Maximum Supply Current: ICC Max (Sheet 2 of 2)
Voltage
(V)
Voltage Rail
4.4
ICCMax (mA)
VCCAA_1P8
1.8
10
VCC1P0_S0
1.0
120
VCCAVISA_1P0
1.0
280
VCCFHVSOC_1P05
1.05
100
VCCFSOC_1P05
1.05
40
VCCAICLKCB_1P0
1.0
40
VCCAICLKSSC1_1P0
1.0
15
VCCAICLKDBUFF_1P0
1.0
30
VCCDICLKDIG_1P0
1.0
15
VCCAICLKSFR_1P5
1.5
40
VCCAICLKSE_3P3
3.3
15
VCCAUSB_1P8
1.8
20
Configurable IO Characteristics
The signals in Table 30 are brought on- and off-chip via standard configurable IO
groups. This section describes the DC and AC characteristics associated with these
signals.
Table 30.
Configurable IO (CFIO) Bi-directional Signal Groupings
Group Name
Interfaces
Related Supply
(VCC)
S0 CFIO Group 0
SPI
Legacy SPI
VCCCFIO_0_3P3
SPI0_MOSI, SPI0_MISO, SPI0_SS_B, SPI0_SCK,
SPI1_MOSI, SPI1_MISO, SPI1_SS_B, SPI1_SCK
LSPI_MOSI, LSPI_MISO, LSPI_SS_B, LSPI_SCK
S0 CFIO Group 1
UART
VCCCFIO_1_3P3
SIU0_CTS_B, SIU0_DCD_B, SIU0_DSR_B, SIU0_DTR_B,
SIU0_RI_B, SIU0_RTS_B, SIU0_RXD, SIU0_TXD,
SIU1_CTS_B, SIU1_RTS_B, SIU1_RXD, SIU1_TXD
S0 CFIO Group 2
USB
GPIO
VCCCFIO_2_3P3
USB_OC_0, USB_OC_1, USB_PWR_EN[0], USB_PWR_EN[1]
GPIO[0], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[5],
GPIO[6], GPIO[7], GPIO[8], GPIO[9]
S0 CFIO Group 3
SDIO
VCCCFIO_3_3P3
SD_DATA[0], SD_DATA[1], SD_DATA[2], SD_DATA[3],
SD_DATA[4], SD_DATA[5], SD_DATA[6], SD_DATA[7],
SD_CMD , SD_CLK, SD_WP, SD_CD_B,
S0 CFIO Group 4
SDIO
Ethernet MAC
VCCCFIO_4_3P3
SD_LED, SD_PWR_B
MAC0_TXDATA[1], MAC0_TXDATA[0], MAC0_RXDV,
MAC0_RXDATA[1], MAC0_RXDATA[0], MAC1_TXDATA[1],
MAC1_TXDATA[0], MAC1_RXDV, MAC1_RXDATA[1],
MAC1_RXDATA[0]
Intel® Quark™ SoC X1000
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Signals
November 2014
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Electrical Characteristics—Intel® Quark™ SoC X1000
Table 30.
Configurable IO (CFIO) Bi-directional Signal Groupings
Group Name
Interfaces
Related Supply
(VCC)
S0 CFIO Group 5
Ethernet MAC
I2C
Legacy
VCCCFIO_5_3P3
S3 CFIO Group
Legacy
Power Management
Suspend GPIOs
VCCCFIO_S3_3P3
RESET_BTN_B, WAKE_B, GPE_B
S0_3V3_EN, S0_1V5_EN, S0_1V0_EN
GPIO_SUS[0], GPIO_SUS[1], GPIO_SUS[2], GPIO_SUS[3],
GPIO_SUS[4], GPIO_SUS[5]
S5 CFIO Group
JTAG/Debug
Power Management
VCCCFIO_S5_3P3
TCK, TDI, TDO, TMS, TRST_B
PWR_BTN_B, S3_3V3_EN, S3_1V5_EN, ODRAM_PWROK,
OSYSPWRGOOD, PRDY_B, PREQ_B
Table 31.
Type
Signals
MAC0_TXEN, MAC0_MDC, MAC0_MDIO, MAC1_TXEN,
MAC1_MDC, MAC1_MDIO
I2C_DATA, I2C_CLK
THRM_B, SMI_B, RMII_REF_CLK, CLK14
CFIO DC Characteristics
Symbol
Parameter
Min
Max
Unit
Condition
Notes
This data applies to all signals in Table 30.
To determine the correct VCC supply for a signal use the related supply shown in Table 30
Input
Output
VCC
Supply Voltage Reference
3.13
3.49
V
VIH
Input High Voltage
0.625 X VCC
VCC + 0.3
V
2
VIL
Input Low Voltage
—
0.25 X VCC
V
2
IIL
Input Leakage Current
—
35
uA
CIN
Input Pin Capacitance
—
10
pF
VOH
Output High Voltage
0.75 x VCC
—
V
Iout=2mA
1, 2
VOL
Output Low Voltage
—
0.125 x VCC
V
Iout=-2mA
2
Notes:
1.
The VOH specification does not apply to open-collector or open-drain drivers. Signals of this type must have an external
pull-up resistor, and that’s what determines the high-output voltage level. Refer to Chapter 2 for details on signal types.
2.
Input characteristics apply when a signal is configured as Input or to signals that are only Inputs. Output characteristics
apply when a signal is configured as an Output or to signals that are only Outputs. Refer to Chapter 2 for details on
signal types.
Table 32.
Type
CFIO AC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
This data applies to all signals in Table 30.
To determine the correct VCC supply for a signal use the related supply shown in Table 30
VCC
Output
3.13
3.49
V
SRRISE
Supply Voltage Reference
Slew Rate Rise
0.5
3.0
V/ns
CLOAD = 10pF
SRFALL
Slew Rate Fall
0.5
3.0
V/ns
CLOAD = 10pF
TRISE
Output Rise Time
0.88
5.28
ns
0.10*VCC 0.90*VCC
TFALL
Output Fall Time
0.88
5.28
ns
0.90*VCC 0.10*VCC
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Intel® Quark™ SoC X1000—Electrical Characteristics
4.5
RTC DC Characteristics
Table 33.
RTC DC Characteristics
Type
Symbol
Parameter
Min
Max
Unit
Condition
2.00
3.40
V
N/A
Notes
Associated Signals: RTCRST_B
Related Supply (VCC): VCCRTC_3P3
VCC
Input
Supply Voltage Reference
VIH
Input High Voltage
.7 x VCC
VCC + 0.5
V
N/A
2
VIL
Input Low Voltage
-0.5
0.78
V
N/A
2
CIN
Input Pin Capacitance
—
3
pF
N/A
Associated Signals: S5_PG, RTC_EXT_CLK_EN_B, S0_PG
Related Supply (VCC): VCCRTC_3P3
VCC
Supply Voltage Reference
2.0
3.40
V
N/A
VIH
Input High Voltage
2.0
VCC + 0.5
V
N/A
2
VIL
Input Low Voltage
-0.5
0.78
V
N/A
2
CIN
Input Pin Capacitance
—
3
pF
N/A
Input
4.6
PCI Express* 2.0 DC/AC Characteristics
Table 34.
PCI Express* 2.0 Differential Signal DC Characteristics
Symbol
Parameter
Min
Max
Unit
Differential Peak to Peak Output Voltage
0.8
1.2
V
Low power differential Peak to Peak Output
Voltage
0.4
1.2
V
Figures
Notes
Associated Signals:
PCIE_PERN[1], PCIE_PERP[1],
PCIE_PETN[1], PCIE_PETP[1],
PCIE_PERN[0], PCIE_PERP[0],
PCIE_PETN[0], PCIE_PETP[0]
Related Supply (VCC):
VCCAPCIE_1P0
VTX-DIFF P-P
VTX-DIFF P-P - Low
VTX_CM-ACp
TX AC Common Mode Output Voltage (2.5GT/
s)
—
20
mV
ZTX-DIFF-DC
DC Differential TX Impedance
80
120

VRX-DIFF p-p
Differential Input Peak to Peak Voltage
0.175
1.2
V
VRX_CM-ACp
AC peak Common Mode Input Voltage
—
150
mV
1
1
Notes:
1.
PCI Express mVdiff p-p = 2*|PETP[x] – PETN[x]|; PCI Express mVdiff p-p = 2*|PERP[x] – PERN[x]|
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Datasheet
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Electrical Characteristics—Intel® Quark™ SoC X1000
Table 35.
PCI Express* 2.0 Interface Timings
Symbol
Parameter
Min
Max
Unit
399.88
400.12
ps
0.7
—
Figures
Notes
Transmitter and Receiver Timings
UI
TTX-EYE
TTX-RISE/Fall
TRX-EYE
Unit Interval – PCI Express*
Minimum Transmission Eye Width
D+/D- TX Out put Rise/Fall time
Minimum Receiver Eye Width
0.125
0.40
UI
5,6
5
UI
—
UI
1,2,6
1,2,6
6
3,4,6
Notes:
1.
Specified at the measurement point into a timing and voltage compliance test load and measured over any 250
consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram)
2.
A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the
Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter
budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
3.
Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI
Express* specification 2.0 should be used as the RX device when taking measurements (also refer to the Receiver
compliance eye diagram). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
4.
A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter
budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the
TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
5.
Nominal Unit Interval is 400 ps for 2.5 GT/s.
6.
Intel® Quark™ SoC X1000 supports PCI Gen 1 timing only: 2.5 GT/s
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Intel® Quark™ SoC X1000—Electrical Characteristics
Figure 5.
PCI Express Transmitter Eye
Figure 6.
PCI Express Receiver Eye
VTS-Diff = 0mV
D+/D- Crossing point
VRS-Diffp-p-Min>175mV
.4 UI =TRX-EYE min
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Datasheet
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Electrical Characteristics—Intel® Quark™ SoC X1000
4.7
USB 2.0 DC/AC Characteristics
Table 36.
USB 2.0 Differential Signal DC Characteristics
Symbol
Parameter
Min
Max
Unit
Conditions
Notes
0.2
—
V
N/A
1,3
Associated Signals:
USBD_DP, USBD_DN,
USBH1_DP, USBH1_DN,
USBH0_DP, USBH0_DN,
USBH(1:0)_OC_B, USBH(1:0)_PWR_EN
Related Supply (VCC):
VCCUSBSUS_3P3
VDI
Differential Input Sensitivity
VCM
Differential Common Mode Range
0.8
2.5
V
N/A
2,3
VSE
Single-Ended Receiver Threshold
0.8
2
V
N/A
3
Output Signal Crossover Voltage
1.3
2
V
N/A
3
VOL
Output Low Voltage
—
0.4
V
Iol=5 mA
3
VOH
Output High Voltage
VCRS
VCC – 0.5
—
V
Ioh=-2mA
3
HS Squelch Detection Threshold
100
150
mV
N/A
4
HS Disconnect Detection Threshold
525
625
mV
N/A
4
VHSCM
HS Data Signaling Common Mode Voltage Range
-50
500
mV
N/A
4
VHSOI
HS Idle Level
-10
10
mV
N/A
4
VHSOH
HS Data Signaling High
360
440
mV
N/A
4
VHSSQ
VHSDSC
HS Data Signaling Low
-10
10
mV
N/A
4
VCHIRPJ
Chirp J Level
700
1100
mV
N/A
4
VCHIRPK
Chirp K Level
-900
-500
mV
N/A
4
Max
Units
Notes
Fig
VHSOL
Notes:
1.
2.
3.
4.
VDI = | USBHx_DP – USBHx_DN |
Includes VDI range
Applies to Low-Speed/Full-Speed USB
Applies to High-Speed USB 2.0
Table 37.
USB 2.0 Interface Timings (Sheet 1 of 2)
Symbol
Parameter
Min
Full-speed Source (Note 7)
t100
USBHx_DP, USBHx_DN - Driver Rise Time
4
20
ns
1,6 CL = 50 pF
8
t101
USBHx_DP, USBHx_DN Driver Fall Time
4
20
ns
1,6 CL = 50 pF
8
t102
Source Differential Driver Jitter
- To Next Transition
- For Paired Transitions
–3.5
–4
3.5
4
ns
ns
2, 3
9
t103
Source SE0 interval of EOP
160
175
ns
4
10
t104
Source Jitter for Differential Transition to SE0
Transition
–2
5
ns
5
t105
Receiver Data Jitter Tolerance
- T o Next Transition
- For Paired Transitions
–18.5
–9
18.5
9
ns
ns
3
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Intel® Quark™ SoC X1000—Electrical Characteristics
Table 37.
USB 2.0 Interface Timings (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
Notes
Fig
4
10
Full-speed Source (Note 7)
t106
EOP Width: Must accept as EOP
82
—
ns
t107
Width of SE0 interval during differential transition
—
14
ns
Low-speed Source (Note 8)
t108
USBHx_DP, USBHx_DN - Driver Rise Time
75
300
ns
1, 6
CL = 200 pF
CL = 600 pF
8
t109
USBHx_DP, USBHx_DN Driver Fall Time
75
300
ns
1,6
CL = 200 pF
CL = 600 pF
8
t110
Source Differential Driver Jitter
To Next Transition
For Paired Transitions
–25
–14
25
14
ns
ns
2, 3
9
t111
Source SE0 interval of EOP
1.25
1.50
µs
4
10
t112
Source Jitter for Differential Transition to SE0
Transition
–40
100
ns
5
t113
Receiver Data Jitter Tolerance
- To Next Transition
- For Paired Transitions
–152
–200
152
200
ns
ns
3
9
t114
EOP Width: Must accept as EOP
670
—
ns
4
10
t115
Width of SE0 interval during differential transition
—
210
ns
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Driver output resistance under steady state drive is specified at 28  at minimum and 43  at maximum.
Timing difference between the differential data signals.
Measured at crossover point of differential data signals.
Measured at 50% swing point of data signals.
Measured from last crossover point to 50% swing point of data line at leading edge of EOP.
Measured from 10% to 90% of the data signal.
Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s.
Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s.
Figure 7.
USB Rise and Fall Time
Rise Time
CL
90%
Fall Time
90%
Differential
Data Lines
10%
10%
CL
tR
tF
Low-speed: 75 ns at CL = 50 pF, 300 ns at C L = 350 pF
Full-speed: 4 to 20 ns at C L = 50 pF
High-speed: 0.8 to 1.2 ns at C L = 10 pF
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Electrical Characteristics—Intel® Quark™ SoC X1000
Figure 8.
USB Jitter
T period
Crossover
Points
Differential
Data Lines
Jitter
Consecutive
Transitions
Paired
Transitions
Figure 9.
USB EOP Width
Tperiod
Data
Crossover
Level
Differential
Data Lines
EOP
Width
4.8
General Interface Timing
4.8.1
Legacy SPI Interface Timing
Table 38.
Legacy SPI Interface Timings (20 MHz) (Sheet 1 of 2)
Sym
F
Parameter
Serial Clock Frequency - 20M Hz Operation
Min
Max
Units
—
20
MHz
Fig
TCH
LSPI_SCK high time
20
—
ns
10
TCL
LSPI_SCK low time
30
—
ns
10
TDSCR
Setup of LSPI_MISO with respect to
LPSI_SCK rising edge
11.7
—
ns
10
TCRDH
Hold time of LSPI_MISO with respect to
LPSI_SCK rising edge
-3.0
—
ns
10
TCFDV
LSPI_SCK falling edge to LSPI_MOSI valid
-1.9
2.5
ns
10
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Intel® Quark™ SoC X1000—Electrical Characteristics
Table 38.
Legacy SPI Interface Timings (20 MHz) (Sheet 2 of 2)
Sym
Parameter
Min
Max
Units
Fig
TCFSF
LSPI_SCK falling edge to LSPI_SS_B low
-1.6
2.4
ns
10
TCFSR
LSPI_SCK falling edge to LSPI_SS_B high
-1.7
2.3
ns
10
Notes:
1.
All input signals have a slope of 1.0ns measured between 20% and 80% VCC values.
2.
All output signals are loaded with 20pF.
3.
Measurements are made at 50% VCC levels.
4.8.2
SPI0/1 Interface Timing
Table 39.
SPI0/1 Interface Timings (25 MHz)
Sym
Parameter
F
Min
Max
Units
Fig
Serial Clock Frequency - 25MHz Operation
—
25
MHz
TCH
SPI0/1_SCK high time
20
—
ns
10
TCL
SPI0/1_SCK low time
20
—
ns
10
TDSCR
Setup of SPI0/1_MISO with respect to SPI0/
1_SCK capturing edge
10.7
—
ns
10
TCRDH
Hold time of SPI0/1_MISO with respect to
SPI0/1_SCK capturing edge
-2.5
—
ns
10
TCFDV
SPI0/1_SCK driving edge to SPI0/1_MOSI
valid
-0.8
3.5
ns
10
TSSCF
Setup of SPI0/1_SS_B with respect to first
edge out of inactive state of SPI0/1_SCK
20
—
ns
10
TCLSH
Hold of SPI0/1_SS_B with respect to last
edge into inactive state of SPI0/1_SCK
20
—
ns
10
Note:
1.
2.
3.
4.
Intel® Quark™ SoC X1000
Datasheet
80
All input signals have a slope of 1.0ns measured between 20%and 80% VCC values
All output signals are loaded with 20pF
Measurements are made at 50% VCC levels
Driving edge and capturing edge of SPI0/1_SCK are determined by SPI Control Register 1
settings SSCR1.SPH and SSCR1.SPO; Figure 10 shows SPI_SCK rising edge as the driving
edge and SPI_SCK falling edge as the capturing edge by way of example
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Electrical Characteristics—Intel® Quark™ SoC X1000
Figure 10.
SPI Interface Timing
TCH
TCL
SPI_SCK
TCDDV
SPI_MOSI
TSSCF
TCLSH
SPI_SS_B
TDSCC
TCCDH
SPI_MISO
4.8.3
SDIO Interface Timing
Table 40.
SDIO Timing
Sym
Parameter
F
Operating Frequency SD_CLK
Min
Max
Units
-
50
MHz
Notes
Fig
TCH
Clock High Time SD_CLK
10
-
ns
11
TCL
Clock Low Time SD_CLK
10
-
ns
11
TDSCR
SD_DATA[7:0]/SD_CMD setup time
with respect to SD_CLK rising
0.6
-
ns
11
TCRDH
SD_DATA[7:0]/SD_CMD hold time
with respect to SD_CLK rising
1.6
-
TCFDV
SD_CLK falling to data valid on
SD_DATA[7:0]/SD_CMD
-2.0
2.7
Note:
1.
2.
3.
11
ns
11
All input signals have a slope of 1.0ns measured between 20%and 80% VCC values
All output signals are loaded with 20pF
Measurements are made at 50% VCC levels
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Intel® Quark™ SoC X1000—Electrical Characteristics
Figure 11.
SDIO Interface Timing
TCL
TCH
SD_CLK
TCFDV
SD_DATA[7:0]
SD_CMD
(outputs)
TDSCR
TCRDH
SD_DATA[7:0]
SD_CMD
(inputs)
4.9
Clock AC Timing
4.9.1
Reference Clock AC Characteristics
Table 41.
Reference Clocks AC Characteristics (Sheet 1 of 2)
Parameter
Description
Min
Max
Units
Notes
Fig
Associated Signals:
REF0_OUTCLK_P, REF0_OUTCLK_N,
REF1_OUTCLK_P, REF1_OUTCLK_N
Related Supply:
VCCAICLKDBUFF_1P0
TSLEW_RISE
Rising slew rate
1.5
8.0
V/ns
2,3,10
12
TSLEW_FALL
Falling slew rate
1.5
8.0
V/ns
2,3,10
12
PSLEW_VAR
Slew rate matching
-
20
%
1,9,10
12
VSWING
Differential output swing
300
-
mV
2,11
12
VCROSS
Crossing point voltage
300
550
mV
1,4,5,11
12
VCROSS_DELTA
VCROSS variation
-
140
mV
1,4,8,11
12
VMAX
Maximum output voltage
-
1.15
V
1,6,11
12
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Electrical Characteristics—Intel® Quark™ SoC X1000
Table 41.
Reference Clocks AC Characteristics (Sheet 2 of 2)
Parameter
Description
VMIN
Minimum output voltage
PDTY_CYC
Duty Cycle
Note:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Min
Max
Units
Notes
Fig
-0.3
-
V
1,7,11
12
40
60
%
2,10
12
Measurement taken from a single-ended waveform on a component test board
Measurement taken from a differential waveform on a component test board
Slew rate measured through VSWING voltage measured at differential zero
VCROSS is defined as the voltage where CLK_P = CLK_N
Only applies to differential rising edge (CLK_P rising, CLK_N falling)
The maximum voltage including over-shoot
The minimum voltage including under-shoot
The total variation of all VCROSS measurements in any particular system
Matching applies to rising edge rate for CLK_P and falling edge rate for CLK_N; It is measured using a
±75mV window centered on the average cross point where CLK_P rising meets CLK_N falling. The
median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge
rate calculations
Average measurement
Instantaneous measurement
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Intel® Quark™ SoC X1000—Electrical Characteristics
l
Figure 12.
Measurement Points for Differential Clocks1
Differential Clock – Single Ended Measurements
V max = 1.15V
Clock#
V max = 1.15V
Vcross max =
550mV
Vcross max =
550mV
Vcross min = 300 mV
Vcross min = 300 mV
Clock
V min = -0. 30V
V min = -0.30V
Clock#
Vcross delta = 140mV
Vcross delta = 140mV
Clock
Clock#
Vcross median
Vcross median
a ll
Tf
Vcross median
+75mV
Tr
is
e
Clock#
Vcross median -75mV
Clock
Clock
Differential Clock – Differential Measurements
Clock Period (Differential )
Positive Duty Cycle (Differential )
Negative Duty Cycle (Differential )
0.0V
Clock-Clock#
Rise
Edge
Rate
Fall
Edge
Rate
Vih_min = +150 mV
0.0V
Vil_max = -150 mV
Clock-Clock#
1. Clock == CLK_P; Clock# == CLK_N
§§
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Register Access Methods—Intel® Quark™ SoC X1000
5.0
Register Access Methods
There are six different common register access methods:
• Fixed I/O Register Access
• Fixed Memory Mapped Register Access
• I/O Referenced Register Access
• Memory Referenced Register Access
• PCI Configuration Register Access (Indirect - via Memory or I/O registers)
• Message Bus Register Access (Indirect - via PCI Configuration Registers)
5.1
Fixed I/O Register Access
Fixed I/O registers are accessed by specifying their 16-bit address in a PORT IN and/or
PORT OUT transaction from the CPU core. This allows direct manipulation of the
registers. Fixed I/O registers are unmovable registers in I/O space.
Table 42.
Fixed I/O Register Access Method Example (NSC Register)
Type: I/O Register
(Size: 8 bits)
5.2
NSC: 61h
Fixed Memory Mapped Register Access
Fixed Memory Mapped I/O (MMIO) registers are accessed by specifying their 32-bit
address in a memory transaction from the CPU core. This allows direct manipulation of
the registers. Fixed MMIO registers are unmovable registers in memory space.
Table 43.
Fixed Memory Mapped Register Access Method Example (IDX Register)
Type: Memory Mapped I/O Register
(Size: 32 bits)
5.3
IDX: FEC00000h
I/O Referenced Register Access
I/O referenced registers use programmable base address registers (BARs) to select a
range of I/O addresses that it uses to decode PORT IN and/or PORT OUT transactions
from the CPU to directly access a register. Thus, the I/O BARs act as pointers to blocks
of actual I/O registers. To access an I/O referenced register for a specific I/O base
address, start with that base address and add the register’s offset. Example
pseudocode for an I/O referenced register read is shown below:
Register_Snapshot = IOREAD([IO_BAR]+Register_Offset)
Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other base address register types may include fixed
memory registers, fixed I/O registers or message bus registers.
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Intel® Quark™ SoC X1000—Register Access Methods
Table 44.
Referenced I/O Register Access Method Example (PM1S Register)
Type: I/O Register
(Size: 16 bits)
PM1S: [PM1BLK] + 0h
PM1BLK Type: PCI Configuration Register (Size: 32 bits)
PM1BLK Reference: [B:0, D:31, F:0] + 48h
5.4
Memory Referenced Register Access
The SoC uses programmable base address registers (BARs) to set a range of physical
address (memory) locations that it uses to decode memory reads and writes from the
CPU to directly access a register. These BARs act as pointers to blocks of actual
memory mapped I/O (MMIO) registers. To access a memory referenced register for a
specific base address, start with that base address and add the register’s offset.
Example pseudocode for a read is shown below:
Register_Snapshot = MEMREAD([Mem_BAR]+Register_Offset)
Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other common base address register types include
fixed memory registers and I/O registers that point to MMIO register blocks.
Table 45.
Memory Mapped Register Access Method Example (ESD Register)
Type: Memory Mapped I/O Register
(Size: 32 bits)
ESD: [RCBA] + 4h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
5.5
PCI Configuration Register Access
Access to PCI configuration space registers is performed through one of two different
configuration access methods (CAMs):
• I/O indexed - PCI CAM
• Memory mapped - PCI Enhanced CAM (ECAM)
Each PCI function (see Section 6.3, “PCI Configuration Space” on page 97) has a
standard PCI header consisting of 256 bytes for the I/O access scheme (CAM), or 4096
bytes for the enhanced memory access method (ECAM). Invalid read accesses return
binary strings of 1s.
Table 46.
PCI Register Access Method Example (PCI_DEVICE_VENDOR Register)
Type: PCI Configuration Register
(Size: 32 bits)
5.5.1
PCI_DEVICE_VENDOR: [B:0, D:31, F:0] + 0h
PCI Configuration Access - CAM: I/O Indexed Scheme
Accesses to configuration space using the I/O method rely on two 32-bit I/O registers:
• CONFIG_ADDRESS - I/O Port CF8h
• CONFIG_DATA - I/O Port CFCh
These two registers are both 32-bit registers in I/O space. Using this indirect access
mode, software uses CONFIG_ADDRESS (CF8h) as an index register, indicating which
configuration space register to access, and CONFIG_DATA (CFCh) acts as a window to
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Register Access Methods—Intel® Quark™ SoC X1000
the register pointed to in CONFIG_ADDRESS. Accesses to CONFIG_ADDRESS (CF8h)
are internally captured. Upon a read or write access to CONFIG_DATA (CFCh),
configuration cycles are generated to the PCI function specified by the address
captured in CONFIG_ADDRESS. The format of the address is shown in Table 47.
Table 47.
PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping
Field
CONFIG_ADDRESS Bits
Enable PCI Config. Space Mapping
31
Reserved
Note:
30:24
Bus Number
23:16
Device Number
15:11
Function Number
10:08
Register/Offset Number
07:02
Bit 31 of CONFIG_ADDRESS must be set for a configuration cycle to be generated.
Pseudocode for a PCI register read is shown below:
MyCfgAddr[23:16] = bus; MyCfgAddr[15:11] = device; MyCfgAddr[10:8] = funct;
MyCfgAddr[7:2] = dWordMask(offset); MyCfgAddr[31] = 1;
IOWRITE(0xCF8, MyCfgAddr)
Register_Snapshot = IOREAD(0xCFC)
5.5.2
PCI Configuration Access - ECAM: Memory Mapped Scheme
A flat, 256 Mbyte memory space may also be allocated to perform configuration
transactions. This is enabled through the HECREG message bus register (Port: 3h,
Register: 09h) found in the Host Bridge. HECREG allows remapping this 256 Mbyte
region anywhere in physical memory space. Memory accesses within the programmed
MMIO range result in configuration cycles to the appropriate PCI devices specified by
the memory address as shown below.
Table 48.
PCI Configuration Memory Bar Mapping
ECAM Memory Address Field
Note:
ECAM Memory Address Bits
Use from BAR: HECREG[31:28]
31:28
Bus Number
27:20
Device Number
19:15
Function Number
14:12
Register Number
11:02
ECAM accesses are only possible when HECREG.EC_ENABLE (bit 0) is set.
Pseudocode for an enhanced PCI configuration register read is shown below:
MyCfgAddr[27:20] = bus; MyCfgAddr[19:15] = device; MyCfgAddr[14:12] = funct;
MyCfgAddr[11:2] = dw_offset; MyCfgAddr[31:28] = HECREG[31:28];
Register_Snapshot = MEMREAD(MyCfgAddr)
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5.6
Message Bus Register Access
Accesses to the message bus space are through the Host Bridge’s PCI configuration
registers. This unit relies on three 32-bit PCI configuration registers to generate
messages:
• Message Bus Control Register (MCR) - PCI[B:0,D:0,F:0] + D0h
• Message Data Register (MDR) - PCI[B:0,D:0,F:0] + D4h
• Message Control Register eXtension (MCRX) - PCI[B:0,D:0,F:0] + D8h
This indirect access mode is similar to PCI CAM. Software uses the MCR/MCRX as an
index register, indicating which message bus space register to access (MCRX only when
required), and MDR as the data register. Writes to the MCR trigger message bus
transactions.
Writes to MCRX and MDR are captured. Writes to MCR generates an internal ‘message
bus’ transaction with the opcode and target (port, offset, byte enable) specified in the
MCR and the captured MCRX. When a write opcode is specified in MCR, the data that
was captured by MDR is used for the write. When a data read opcode is specified in
MCR, the data is available in the MDR register after the MCR write completes (nonposted). The format of MCR and MCRX are shown in Table 49 and Table 50.
Table 49.
MCR Description
Field
Table 50.
MBPR Bits
OpCode (typically 10h for read, 11h for write)
31:24
Port
23:16
Offset/Register
15:08
Byte Enable
07:04
MCRX Description
Field
MBPER Bits
Offset/Register Extension. This is used for messages sent to end points that require more
than 8 bits for the offset/register. These bits are a direct extension of MCR[15:8].
31:08
Most message bus registers are located in the Host Bridge. The default opcode
messages for those registers are as follows:
• Message ‘Read Register’ Opcode: 10h
• Message ‘Write Register’ Opcode: 11h
Registers with different opcodes are specified as applicable. Pseudocode of a message
bus register read is shown below (where ReadOp==0x10):
MyMCR[31:24] = ReadOp; MyMCR[23:16] = port; MyMCR[15:8] = offset;
MyMCR[7:4] = 0xf
PCIWRITE(0, 0, 0, 0xD0, MyMCR)
Register_Snapshot = PCIREAD(0, 0, 0, 0xD4)
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5.7
Register Field Access Types
Table 51.
Register Access Types and Definitions
Access Type
Meaning
Description
Read Only
In some cases, if a register is read only, writes to this register
location have no effect. However, in other cases, two separate
registers are located at the same location where a read accesses
one of the registers and a write accesses the other register. See the
I/O and memory map tables for details.
WO
Write Only
In some cases, if a register is write only, reads to this register
location have no effect. However, in other cases, two separate
registers are located at the same location where a read accesses
one of the registers and a write accesses the other register. See the
I/O and memory map tables for details.
RW
Read/Write
A register with this attribute can be read and written.
RW/C
Read/Write Clear
A register bit with this attribute can be read and written. However, a
write of 1 clears (sets to 0) the corresponding bit and a write of 0
has no effect.
RW/O
Read/Write-Once
A register bit with this attribute can be written only once after power
up. After the first write, the bit becomes read only.
RW/L
Read/Write Lockable
A register bit with the attribute can be read at any time but writes
may only occur if the associated lock bit is set to unlock. If the
associated lock bit is set to lock, this register bit becomes RO unless
otherwise indicated.
RW/L/O
Read/Write, LockOnce
RW/SN
Read/Write
Read/Write register initial value loaded from NVM.
Reserved
Reserved
The value of reserved bits must never be changed.
RO
Default
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Default
A register bit with this attribute can be written to the non-locked
value multiple times, but to the locked value only once. After the
locked value has been written, the bit becomes read only.
When the processor is reset, it sets its registers to predetermined
default states. The default state represents the minimum
functionality feature set required to successfully bring up the
system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization
software to determine configuration, operating parameters, and
optional system features that are applicable, and to program the
processor registers accordingly.
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Mapping Address Spaces—Intel® Quark™ SoC X1000
6.0
Mapping Address Spaces
The Intel® Quark™ SoC X1000 supports four different address spaces:
• Physical Address Space Mappings (Memory Space)
• I/O Address Space
• PCI Configuration Space
• Message Bus Space
The CPU core can only directly access memory space through memory reads and writes
and I/O space through the IN and OUT I/O port instructions. PCI configuration space is
indirectly accessed through I/O or memory space, and the Message Bus space is
accessed through PCI configuration space. See Chapter 5.0, “Register Access Methods”
for details.
This chapter describes how the memory, I/O, PCI, and Message Bus spaces are mapped
to interfaces in the SoC.
Note:
See Chapter 12.0, “Host Bridge” for registers specified in the chapter.
6.1
Physical Address Space Mappings
There are 4 Gbyte (32-bits) of physical address space that can be used as:
• Memory Mapped I/O (MMIO - I/O fabric)
• Physical Memory (DRAM)
The CPU core can access the full physical address space, while downstream devices can
only access SoC DRAM, and the CPU core’s local APIC. Peer to peer transactions are not
supported.
Most devices map their registers and memory to the physical address space. This
chapter summarizes the possible mappings.
6.1.1
Bridge Memory Map
The Host Bridge maps the physical address space as follows:
• CPU core to DRAM
• CPU core to I/O fabric (MMIO)
• CPU core to extended PCI registers (ECAM accesses)
• I/O fabric to CPU cores (local APIC interrupts)
This SoC has the following distinct memory regions:
• DOS DRAM + Low DRAM
• MMIO
The HMBOUND register is used to create these memory regions, as shown in Figure 13.
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Figure 13.
Physical Address Space - Low DRAM & MMIO
4 Gbyte
MMIO
HMBOUND
Low DRAM
Low DRAM
DOS DRAM
DOS DRAM
Physical Address
Space
DRAM Address
Space
1 Mbyte
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6.1.1.1
MMIO
The MMIO mappings are shown in Figure 14.
Figure 14.
Physical Address Space - MMIO
4 Gbyte
Boot Vector
MMIO
- 1 (FFFFFFFFh)
- 128 Kbyte (FFFE0000h)
- 17 Mbyte (FEEFFFFFh)
Local APIC
- 18 Mbyte (FEE0 0000h)
HMBOUND
HECREG + 256 Mbyte
Low DRAM
PCI ECAM
HECREG
1 Mbyte
DOS DRAM
Physical Address
Space
By default, CPU core reads targeting the Boot Vector range (FFFFFFFFh-FFFE0000h)
are sent to the Legacy Bridge, and write accesses target DRAM. For secure SKU’s, reads
targeting the Boot Vector are decoded and routed to a Secure Root of Trust Boot ROM.
For non-secure SKU’s, reads targeting this region are routed to a boot SPI flash device
connected to the Legacy Bridge.
Upstream writes from the I/O fabric to the Local APIC range (FEE00000h-FEEFFFFFh)
are sent to the CPU core’s APIC.
Accesses in the 256 Mbyte PCI ECAM range starting at HECREG generate enhanced
PCI configuration register accesses when enabled (HECREG.EC_ENABLE). Unlike
traditional memory writes, writes to this range are non-posted when enabled. See
Chapter 5.0, “Register Access Methods” for more details.
All other downstream accesses in the MMIO range are decoded based on PCI resource
allocations. The subtractive agent (for unclaimed accesses) is the I/O Fabric. The I/O
Fabric returns an UNSUPPORTED REQUEST for unclaimed accesses.
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6.1.1.2
DOS DRAM
The DOS DRAM is the memory space below 1 MByte. In general, accesses from a
processor targeting DOS DRAM target system DRAM. Exceptions are shown in
Figure 15.
Figure 15.
Physical Address Space - DOS DRAM
4 Gbyte
MMIO
HMBOUND
F Segment
64 Kbyte (F 0000h to F FFFFh)
E Segment
64 Kbyte (E 0000h to E FFFFh)
VGA/CSEG
128 Kbyte (A 0000h to BFFFFh)
Low DRAM
1 Mbyte
DOS DRAM
Physical Address
Space
Processor writes to the 64 Kbyte (each) E and F segments (E0000h-EFFFFh and
F0000h-FFFFFh) always target DRAM. The HMISC2 register is used to direct CPU core
reads in these two segments to DRAM or the I/O fabric (MMIO).
CPU core accesses to the 128 Kbyte VGA/CSEG range (A0000h-BFFFFh) can target
DRAM or the MMIO space depending on the setting of HMISC2.ABSEG_IN_DRAM. When
targeting MMIO space, requests are sent to the PCIe* port if legacy VGA is enabled in
the PCIe controller.
6.1.1.3
Additional Mappings
There is one additional mapping available in the Host Bridge:
• SMM range
Figure 16 shows these mappings.
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Figure 16.
Physical Address Space - SMM Range
L o w o r H ig h
D R A M in P h y s ic a l
Space
H S M M C T L .S M M _ E N D
SM M Range
H S M M C T L .S M M _ S T A R T
0
SMI handlers running on a CPU core execute out of SMRAM. To protect this memory
from non-CPU core access, the SMM Range (HSMMCTL.SMM_START HSMMCTL.SMM_END) may be programmed anywhere in low DRAM space (1 Mbyte
aligned). This range only allows accesses from the CPU core while in SMM.
6.1.2
MMIO Map
Memory accesses targeting MMIO are routed by the programmed PCI ranges.
Fixed MMIO is claimed by the Legacy Bridge. The default regions are listed below.
Movable ranges are not shown. See the register maps of all Legacy Bridge components
for details.
Table 52.
Fixed Memory Ranges in the Legacy Bridge
Device
Start Address
End Address
Comments
Low BIOS (Flash Boot)
000E0000h
000FFFFFh
Starts 128 Kbyte below 1 Mbyte; Firmware/
BIOS
I/O APIC
FEC00000h
FEC00040h
Starts 20 Mbyte below 4 Gbyte
HPET
FED00000h
FED003FFh
Starts 19 Mbyte below 4 Gbyte
High BIOS/Boot Vector
FFFE0000h
FFFFFFFFh
Starts 128 Kbyte below 4 Gbyte; Firmware/
BIOS
PCI devices may also claim memory resources in MMIO space. For details see each
device’s interface chapter.
Warning:
Variable memory ranges should not be set to conflict with other memory ranges. There
may be unpredictable results if the configuration software allows conflicts to occur.
Hardware does not check for conflicts.
6.2
I/O Address Space
There are 64 Kbyte + 3 bytes of I/O space (0h-10002h) for accessing I/O registers.
Most I/O registers exists for legacy functions in the Legacy Bridge or for PCI devices,
while some are claimed by the Host Bridge for the PCI configuration space access
registers.
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6.2.1
Host Bridge I/O Map
The Host Bridge claims I/O transactions for VGA/Extended VGA found in the display/
graphics interface. It also claims the two 32-bit registers at port CF8h and CFCh used
to access PCI configuration space.
6.2.2
I/O Fabric I/O Map
6.2.2.1
Legacy Bridge Fixed I/O Address Ranges
Table 53 shows the fixed I/O space ranges seen by a processor.
Table 53.
Fixed I/O Ranges in the Legacy Bridge
Device
I/O Address
8259 Master
6.2.2.2
Comments
20h-3Dh
8254s
40h-43h, 50h-53h
NMI Controller
61h, 63h, 65h, 67h
RTC
70h-73h
Scratch Pad
80h-83h
8259 Slave
A0h-BDh
Reset Control
CF9h
Overlaps PCI I/O registers
Variable I/O Address Ranges
Table 54 shows the variable I/O decode ranges. They are set using base address
registers (BARs) or other similar means. Plug-and-play (PnP) software (PCI/ACPI) can
use their configuration mechanisms to set and adjust these values.
Warning:
The variable I/O ranges should not be set to conflict with other I/O ranges. There may
be unpredictable results if the configuration software allows conflicts to occur.
Hardware does not check for conflicts.
Table 54.
Movable I/O Ranges Decoded by PCI Devices on the I/O Fabric
Device
Size (bytes)
Target
ACPI Power Management
16
PM1BLK: PCI[B:0,D:31,F:0] + 48h
ACPI General Purpose Event 0
64
GPE0BLK: PCI[B:0,D:31,F:0] + 4Ch
GPIO
128
GBA: PCI[B:0,D:31,F:0] + 44h
Watchdog Timer
64
WDTBA: PCI[B:0,D:31,F:0] + 84h
ACPI Processor Block
16
PMBA: Port[0x04] + 70h
SPI DMA Block
16
SPI_DMA_BAR: Port[0x04] + 7Ah
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6.3
PCI Configuration Space
All PCI devices/functions are shown below.
Table 55.
PCI Devices and Functions
Bus
Device
0
20
0
21
Function
0
Device Description
Host Bridge
0
SDIO / eMMC
1
HS-UART 0
2
USB 2.0 Device
3
4
I/O Fabric
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USB EHCI
USB OHCI
5
HS-UART 1
6
10/100 Ethernet MAC 0
7
10/100 Ethernet MAC 1
0
SPI 0
1
I/O Fabric
0
1
0
SPI 1
I2C* / GPIO
2
23
Function Description
PCI Express*
Legacy Bridge
Root Port 0
Root Port 1
Legacy Components
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Figure 17.
Bus 0 PCI Devices and Functions
PCI Space
CPU
Core
Host Bridge
D:0,F:0
PCI
CAM
(I/O)
Bus 0
PCI
ECAM
(Mem)
I2C*/GPIO F:2
HSUART0 F:1
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
RP0 F:1
PMC
Legacy Bridge
D:31,F:0
SDIO/eMMC F:0
PCIe*
D:23
SPI1 F:1
IO Fabric
D:21
SPI0 F:0
RP0 F:0
GPIO
RTC
8254
8259
HPET
IO APIC
SPI
MAC0 F:6
MAC1 F:7
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6.4
Message Bus Space
Message bus space provides access to different units within the host bridge. These
units are useful in configuring the memory map, power management, and more.
Figure 18.
Message Bus with PCI Space
CPU
Core
Host
Bridge
B:0,D:0,F0
Table 56.
Message Bus Space
Port: 0x00
Port: 0x01
Memory
Arbiter
Memory
Controller
Port: 0x03 Port: 0x04
Host
Bridge
Remote
Management
Unit
Port: 0x05
Memory
Manager
Message Types
Msg Type
Message Description
RegWr
Register Write message - used to write to the 32-bit
Dunit registers.
RegRd
Register Read message - used to read from the 32-bit
Dunit registers.
Msg
Simple message without data - used to send atomic
commands, such as Wake and Suspend.
MsgD
Simple Message with 4 bytes of data - used to
communicate with the DRAM devices during
initialization.
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Clocking—Intel® Quark™ SoC X1000
7.0
Clocking
The SoC has a variable frequency, multiple clock domain, and multiple power plane
clocking system. This clock architecture achieves a low power clocking solution that
supports the various clocking requirements of the different IPs on the SoC. This is
achieved by using an Integrated Clock module (iClock) that supplies the clocks to the
entire platform.
7.1
Clocking Features
The SoC provides a complete system clocking solution through integrated clocking. All
the required platform clocks are provided by the SoC using only one input: a 25 MHz
primary reference for the integrated clock block. An optional 32 KHz reference for the
Real Time Clock (RTC) block may be provided if required.
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Figure 19.
SoC Platform Clocking
Platform
Clocks
25 MHz
Primary
Reference
DDR3_CK/CKB[1:0]
DRAM Ranks [0-1]
XTAL_IN/OUT
REF[0/1]_OUTCLK_P/N
RMII_REF_CLK_OUT
PCIe* Connector(s)
Ethernet
PHY
(RMII)
RMII_REF_CLK
I2C_CLK
I2C* Interface
32 kHz
RTC Reference
(optional)
RTC_X1/X2
LSPI_SCK
SPI[0/1]_SCK
FLEX0_CLK
FLEX1_CLK
FLEX2_CLK
SPI Flash
SPI Device
External Device(s)
The reference clocks required for the various interface PLLs (e.g., USB/PCIe*) and the
processor are internally generated by the Integrated Clocking unit.
7.2
Platform/System Clock Domains
The SoC contains multiple clock domains to support its various interfaces. Table 57 and
Table 58 summarize the different clock inputs and outputs in the system.
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Table 57.
Intel® Quark™ SoC X1000 Clock Inputs
Clock Domain
Table 58.
Signal Name
Frequency
Usage/Description
Main
XTAL_IN
XTAL_OUT
25 MHz
25 MHz reference for the iCLK PLL
RTC
RTCX1
RTCX2
32 kHz
RTC Crystal I/O for RTC block.
This clock is optional and may be
generated internally by the iCLK PLL.
Ethernet PHY
RMII_REF_CLK
50 MHz
JTAG
TCK
25 MHz
JTAG Test Clock
CPU/PLL
OSC_COMP
Static current
Ext. precision R 10.5 kOhm to 1.5V
RMII 50MHz Clock
This clock is a loopback of
RMII_REF_CLK_OUT
Intel® Quark™ SoC X1000 Clock Outputs
Clock Domain
Signal Name
Frequency
Usage/Description
DDR
DDR3_CK[1:0]
DDR3_CKB[3:0]
400 MHz
Drives the Memory ranks 0-1. Data rate is
2x the clock rate.
PCI Express*
REF[0/1]_OUTCLK_N
REF[0/1]_OUTCLK_P
100 MHz
Differential Clocks supplied to external PCI
Express* devices
Flex Clocks
FLEX0_CLK
FLEX1_CLK
FLEX2_CLK
33 MHz
33 MHz
48 MHz
Output clock for External devices
Legacy SPI
LSPI_SCK
20 MHz
Clock for external SPI Flash
SPI
SPI[0/1]_SCK
25 MHz
SPI serial clocks
Ethernet PHY
RMII_REF_CLK_OUT
50 MHz
Reference clock for RMII interface
I2C*
I2C_CLK
400 kHz
I2C clocks
SD
SD_CLK
50 MHz
SD Clock
Main
CKSYS25OUT
25 MHz
25 MHz Oscillator Output
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Power Management—Intel® Quark™ SoC X1000
8.0
Power Management
This chapter provides information on the following power management topics:
• ACPI States
• Processor Core
• PCI Express*
8.1
Power Management Features
• ACPI 3.0 specification support
• ACPI Processor C States (C0, C1, and C2)
• ACPI Sleep State Support (S0, S3, S4, and S5)
• PCI Express L0, L1, L2, and L3
8.2
Signal Descriptions
See Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 59.
Power Management (Sheet 1 of 2)
Direction/
Type
Description
RESET_BTN_B
I
PwrMgmt
Reset Button: With the SOC in S0 an activation of this input will
result in a 'Warm Reset'. Active LOW
WAKE_B
I
PwrMgmt
PCI Express Wake Event:
This signal indicates a PCI Express port wants to wake the
system. Can optionally be used by an external device to wake
the system if the WAKE_B functionality is not required by PCI
Express.
GPE_B
I
PwrMgmt
General Purpose Event:
GPE_B is asserted by an external device to log an event in the
system's ACPI space and cause an SCI (if enabled).
PWR_BTN_B
I
PwrMgmt
Power Button: Two modes of operation.
1. A power button press is required to complete cold boot.
Active LOW.
2. The button is tied low, results in an automated start at power
on.
S3_3V3_EN
O
PwrMgmt
S3 Domain 3.3v platform rail enable. Active HIGH.
Signal Name
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Table 59.
Power Management (Sheet 2 of 2)
Signal Name
8.3
Direction/
Type
Description
S3_1V5_EN
O
PwrMgmt
S3 Domain 1.5v platform rail enable. Active HIGH.
S3_PG
I
PwrMgmt
S3 Power Good
S0_1P0_PG
I
PwrMgmt
S0 Domain 1.0V Power Good
S0_3V3_EN
O
PwrMgmt
S0 Domain 3.3v platform rail enable. Active HIGH.
S0_1V5_EN
O
PwrMgmt
S0 Domain 1.5v platform rail enable. Active HIGH.
S0_1V0_EN
O
PwrMgmt
S0 Domain 1.0v platform rail enable. Active HIGH.
ODRAM_PWROK
O
PwrMgmt
DRAM Power Okay: Active HIGH.
OSYSPWRGOOD
O
PwrMgmt
System Power Good: S0 power is good. Active HIGH
VNNSENSE
IO
PwrMgmt
VNN sense voltage for IMVP
VSSSENSE
IO
PwrMgmt
VSS sense voltage for IMVP
ACPI Supported States
The ACPI states supported by the processor are described in this section.
8.3.1
S-State Definition
8.3.1.1
S0 - Full On
This is the normal operating state of the processor. In S0, the core processor
transitions in and out of the various processor C-States.
Note:
The processor core does not support P-states.
8.3.1.2
S3 - Suspend to RAM (Standby)
S3 is a suspend state in which the core power planes of the processor are turned off
and the suspend wells remain powered.
• All power wells are disabled, except for the suspend and RTC wells.
• The core processor’s macro-state is saved in memory.
• Memory is held in self-refresh and the memory interface is disabled, except the
CKE pin as it is powered from the memory voltage rail. CKE is driven low.
8.3.1.3
S4 - Suspend to Disk (Hibernate)
S4 is a suspend state in which most power planes of the processor are turned off,
except for the suspend and RTC well. In this ACPI state, system context is saved to the
mass storage device attached to SDIO/eMMC interface.
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Note:
This is a software based state that is the same as S5 to hardware. On S4 entry, the
system saves the entire contents of data off to NVRAM. On S4 resume, the system
restores the entire contents of memory after performing the a typical S5-S0 boot.
Key features:
• No activity is allowed.
• All power wells are disabled, except for the suspend and RTC well.
8.3.1.4
S5 - Soft Off
From a hardware perspective the S5 state is identical to the S4 state. The difference is
purely software; software does not write system context to OS storage when entering
S5.
8.3.2
System States
Table 60.
General Power States for System
States/Sub-states
Legacy Name / Description
G0/S0/C0
FULL ON: CPU operating. Individual devices may be shut down to save power. The
different CPU operating levels are defined by Cx states.
G0/S0/Cx
Cx State: CPU manages C-state itself.
G1/S3
Suspend-To-RAM (STR): The system context is maintained in system DRAM, but
power is shut to non-critical circuits. Memory is retained, and refreshes continue. All
external clocks are shut off; RTC clock and internal ring oscillator clocks are still
toggling.
G1/S4
Suspend-To-Disk (STD): The context of the system is maintained on the disk. All
power is shut down except power for the logic to resume.
G2/S5
Soft-Off: System context is not maintained. All power is shut down except power for
the logic to restart. A full boot is required to restart. A full boot is required when
waking.
G3
Mechanical OFF. System content is not maintained. All power shutdown except for
the RTC. No “Wake” events are possible, because the system does not have any
power. This state occurs if the user removes the batteries, turns off a mechanical
switch, or if the system power supply is at a level that is insufficient to power the
“waking” logic. When system power returns, transition depends on the state just prior
to the entry to G3.
Table 61 shows the transition rules among the various states. Note that transitions
among the various states may appear to temporarily transition through intermediate
states. These intermediate transitions and states are not listed in the table.
Table 61.
ACPI PM State Transition Rules (Sheet 1 of 2)
Present
State
G0/S0/C0
G0/S0/C2
Transition Trigger
Next State
P_LVL2 Read
G0/S0/C2
PM1C.SLP_EN bit set
G1/Sx or G2/S5 state (specified by
PM1C.SLP_TYPE)
Power Button Override
G2/S5
Mechanical Off/Power Failure
G3
C2 break events which include: MSI, Legacy
Interrupt
G0/S0/C0
Power Button Override
G2/S5
Resume Well Power Failure
G3
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Table 61.
ACPI PM State Transition Rules (Sheet 2 of 2)
Present
State
Transition Trigger
Any Enabled Wake Event
G1/S3, G1/S4 Power button Override
G2/S5
G3
Next State
G0/S0/C0
G2/S5
Resume Well Power Failure
G3
Any Enabled Wake Event
G0/S0/C0
Power Failure or Removal
G3
Power Returns
Option to go to S0/C0 (reboot) or G2/S5 (stay
off until power button pressed or other enabled
wake event) or G1/S4 (if system state was S4
prior to the power failure). Some wake events
are preserved through a power failure.
8.3.3
Processor Idle States
Table 62.
Processor Core/ States Support
State
C0
Description
Active mode, processor executing code
C1
AutoHALT state
C2
Stop Grant state
8.3.4
Integrated Memory Controller States
Table 63.
Main Memory States
States
Powerup
Description
CKE asserted. Active mode.
Precharge Powerdown
CKE de-asserted (not self-refresh) with all banks closed.
Active Powerdown
CKE de-asserted (not self-refresh) with at least one bank active.
Self-Refresh
CKE de-asserted using device self-refresh
8.3.5
PCIe* States
Table 64.
PCIe* States
States
Description
L0
Full on – Active transfer state
L0s
First Active Power Management low power state – Low exit latency
L1
Lowest Active Power Management - Longer exit latency
L3
Lowest power state (power-off) – Longest exit latency
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8.3.6
Interface State Combinations
Table 65.
G, S and C State Combinations
8.4
Global (G)
State
Sleep
(S) State
Processor
Core
(C) State
Processor State
System
Clocks
Description
G0
S0
C0
Full On
On
Full On
G0
S0
C1
Auto-Halt
On
Auto-Halt
G0
S0
C2
Stop Grant
On
Stop Grant
G1
S3
Power Off
Off except RTC
& internal ring
OSC
Suspend to RAM
G1
S4
Power Off
Off except RTC
& internal ring
OSC
Suspend to Disk
G2
S5
Power Off
Off except RTC
& internal ring
OSC
Soft Off
G3
NA
Power Off
Power Off
Hard Off
Processor Core Power Management
When the processor is not executing code, it is idle. A low-power idle state is defined by
ACPI as a C-state. In general, lower power C-states have longer entry and exit
latencies.
8.4.1
Low-Power Idle States
When the processor core is idle, low-power idle states (C-states) are used to save
power. More power savings actions are taken for numerically higher C-state. However,
higher C-states have longer exit and entry latencies.
8.4.1.1
Clock Control and Low-Power States
The processor core supports low power states at core level. States for processor core
include Normal (C0), Auto-Halt (C1) and Stop Grant (C2).
Transition to processor core power states higher than C1 are triggered by initiating a
P_LVLx (P_LVL2) I/O read.
The Cx state ends due to a break event. Based on the break event, the processor
returns the system to C0. The following are examples of such break events:
• Any unmasked interrupt goes active
• Any internal event that will cause an NMI or SMI_B
• CPU Pending Break Event (PBE_B)
• MSI
8.4.2
Processor Core C-States Description
8.4.2.1
Core C0 State
The normal operating state of a core where code is being executed.
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8.4.2.2
Core C1 State
C1 is a low power state entered when the core executes a HLT instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1 state. See the Intel® 64 and IA-32 Architecture Software Developer’s
Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While the core is in C1 state, it still processes snoops.
8.4.2.3
Core C2 State
C2 is entered when the processor reads the P_LVL2 register to trigger a transition from
C0 to C2. While the core is in the C2 state, it processes snoops.
An interrupt or a reset is required to exit the C2 state and return to the C0 state.
8.5
Memory Controller Power Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
8.5.1
Disabling Unused System Memory Outputs
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tri-stated the memory module is
not guaranteed to maintain data integrity.
8.5.2
DRAM Power Management and Initialization
The SoC implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, SRE, SRX, PDE and PDX, which the SDRAM controller supports. The SoC drives
two CKE pins to perform these operations.
8.5.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that is recognized (other than the
DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to
make sure the SDRAM components float DQ and DQS during power-up.
CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is guaranteed to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.
8.5.2.2
Dynamic Self-Refresh
When Dynamic Self-Refresh (SR) is enabled, via DPMC0.DYNSREN, the Memory
Controller places the SDRAM in SR mode when the following conditions are true:
1. No requests are pending
2. Internal Request Status is low priority
3. No SR exit requests from the DDRIO (for RCOMP updates)
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If one of the above conditions change prior to the SR Entry command being sent to the
DRAM the process is terminated.
When Dynamic SR is enabled the Memory Controller exits SR mode when one of the
following is true:
1. Requests are pending and the Internal Request Status is normal or urgent
2. A SR exit request from the DDRIO
8.5.2.3
Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The Memory Controller
implements aggressive CKE control to dynamically put the DRAM devices in a power
down state. The Memory Controller can be configured to put the devices in active
power down (CKE de-assertion with open pages) or precharge power down (CKE deassertion with all pages closed). Precharge power down provides greater power savings
but has a bigger performance impact, since all pages will first be closed before putting
the devices in power down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
8.5.2.4
Functional Clock Gating
The Memory Controller has internal clock gating for the majority of its clocked logic.
When enabled the clock gating is activated when all inputs are inactive and all
commands are complete and DDR3 timing trackers are flushed. When Dynamic SR is
enabled, clock gating is only applied when the SDRAM is in Self-Refresh.
§§
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Power Up and Reset Sequence—Intel® Quark™ SoC X1000
9.0
Power Up and Reset Sequence
This chapter provides information on the following topics:
• Power up and down sequences, including wake events
• Reset behavior
9.1
Intel® Quark™ SoC X1000 System States
9.1.1
System Sleep States Control (S-States)
The SoC supports the S0, S3, S4, and S5 sleep states. S4 and S5 states are identical
from a hardware perspective.
The SoC integrates a Power Management Controller (PMC). No external power
controller IC is required.
The SoC sleep states are described in Chapter 8.0, “Power Management”.
9.2
Power Up and Down Sequences
Note:
Delays in power sequences are dependent on components outside the SoC. As long as
the sequencing is preserved, the SoC will operate.
9.2.1
Power Up, Wake and Reset Overview
SoC power up is dependent on two supplies:
• VCC3P3_S5, which is generated from AC power
• VCCRTC_3P3, which powers the RTC well only
VCCRTC_3P3 is derived directly from VCC3P3_S5, if present. Otherwise it can be driven
by a coin-cell battery.
• In the case where the coin-cell battery is present but not AC power, only the RTC
well is powered up. The SoC can move to state G3 only. The SoC can subsequently
be transitioned to state S4/S5 by applying AC power.
• In the case where AC power is present but there is no coin-cell battery, power up is
initiated directly by the ramping of the VCC3P3_S5 supply. The SoC transitions
directly to state S4/S5.
Subsequent transition from S4/S5 to S0 is governed by activity on the power button
pin, PWR_BTN_B:
• If PWR_BTN_B is strapped low (auto power button mode) when AC power is
applied, the SoC transitions directly to S0 from S4/S5 via a transitional S3 state.
• If PWR_BTN_B is high when AC power is applied, the SoC transitions to S4/S5 only.
A subsequent falling edge on PWR_BTN_B, with the low value being maintained for
2.5ms or more, is required to initiate a transition to S0 via the transitional S3 state.
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Once in state S0 the SoC can be put to sleep, i.e., transitioned to sleep states S3 or S4/
S5, through appropriate settings of the Legacy Bridge ACPI registers PM1C.SLPTYPE
and PM1C.SLPEN.
A wake event is defined as a transition from state S3 to state S0. The chip can be
woken up via a number of mechanisms including specific register settings, or by
asserting specific SoC pins. A watchdog function in the Legacy Bridge can also trigger a
wake event.
In auto power button mode, if the SoC is placed in sleep state S4/S5, the system can
only be woken by the removal and reapplication of AC power. It does not resume from
S4, rather it is a new start with context loss. Since PWR_BTN_B is low it will power up
and transition directly back to S0 as described in the power up sequence.
There are two classes of reset associated with Intel® Quark™ SoC X1000:
• A cold reset means transitioning from S0 to S4/S5 and back to S0 again,
independent of the PWR_BTN_B value. This can only be initiated from state S0
through the register RSTC.COLD_RST. All registers except those driven by the RTC
supply are effectively reset.
• A warm reset resets CPU and peripheral blocks without the removal of the power
supplies. This can be initiated via a write to the register RSTC.WARM_RST or by
asserting the SoC pin, RESET_BTN_B (active low). It can occur only in state S0 and
after reset the SoC remains in state S0. RTC well and suspend well registers are left
unaffected.
A cold boot is the sequence where AC power is applied followed by an immediate
transition to S0 using the PWR_BTN_B signal or directly in auto power button mode.
Catastrophic shutdown can be carried out by holding PWR_BTN_B low for at least
3s. This results in a direct return to the S4/S5 state. It can also be initiated by software
under specific error conditions. See the Intel® Quark™ SoC X1000 UEFI Firmware
Writer’s Guide (Document # 330236) for more information.
The following sections provide more detail on these power-related functions.
9.2.2
RTC Power Well Transition: G5 to G3 State Transition
The transition to the G3 state is initiated when VCCRTC_3P3 is ramped. The sequence
is as follows:
1. VCCRTC_3P3 ramps. RTCRST_B should be low.
2. The SoC starts the real time clock oscillator.
3. A minimum of t1 units after VCCRTC_3P3 ramps external circuitry deasserts
RTCRST_B. The system is now in the G3 state.
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Figure 20.
RTC Power Well Timing Diagrams
Initial
Power Up
State G3
Insert coin-cell battery
VCCRTC_3P3
RTCRST_B
t1 [ext]
t2
32kHz Oscillator [int]
Table 66.
Clock Valid
Oscillator Start-Up
RTC Power Well Timing Parameters
Parameter
Description
t1
VCCRTC_3P3 to RTCRST_B
deassertion
t2
Oscillator Startup Time
Min
Max
Units
Notes
9
N/A
ms
1
-N/A
-N/A
s
2
Notes:
1.
This delay is typically created from an RC circuit.
2.
The oscillator startup times are component and design specific. A crystal oscillator can take as long as
2 s to reach a large enough voltage swing. Whereas, a silicon oscillator can have startups times
<10 ms.
9.2.3
AC Power Applied: G3 to S4/S5 State Transition
The timings shown in Figure 21 and Table 67 occur when AC power is applied. The
following occurs:
1. The supplies VCC3P3_S5, VCC1P0_S5 and VCC1P5_S5 are generated by the
platform regulator. These voltages start ramping at [t1,t2,t3].
Note: It is required that the platform power sequence ensures that the 3 voltages
ramp in this order (VCC3P3_S5 --> VCC1P0_S5 --> VCC1P5_S5) All S5
voltages (3P3,1P8,1P0) must be stable prior to VCC1P5_S5.
2. VCC3P3_S5 drives an internal S5 LDO regulator that generates an internal 1.0V
and 1.8V supplies. The 1.8V is driven off chip at time t4 on pin OVOUT_1P8_S5.
Note: It is intended the 1P8V generated by the LDO is connected back into the
VCC1P8_S5 input in order to eliminate the need to generate this voltage on
the platform.
Note: The 1.0V supply output at pin OVOUT_1P0_S5 is unused and should remain
not connected at the platform.
3. When the internal supplies are stable an internal S5 power-good signal is
generated.
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4. A platform S5 power good signal is generated when all Platform Generated S5
supplies are stable at 95% of nominal voltage. This signal is applied at the S5_PG
pin [t6]
Note: If the VCC1P8_S5 is generated by the platform then this voltage must also
be stable prior to assertion of the S5_PG."
5. When both the internal S5 power-good and S5_PG signals are asserted the system
is in state S4/S5.
9.2.4
Using PWR_BTN_B: Transition from S4/S5 to S0
1. The internal power management controller detects an event: either PWR_BTN_B is
actively brought low and remains low for at least 2.5ms [t7], or it is tied low for an
automatic start from the S5 state (auto power button mode). This initiates the
transition from S4/S5 to S0.
2. After a PLL settling time the internal PMC generates a switch enable S3_3V3_EN
which should be used to switch on of the platform S3 supply VCC3P3_S3 [t8, t8’].
3. This is followed by the assertion of S3_1V5_EN to switch on VCC1P5_S3 [t9].
Note: The switch enables are active high and should be used to drive PFET
switches or regulator enables on the platform.
Note: The switch enables are staggered because of SoC rail sequencing
constraints.
4. After a switch-on time [t10] the S3 supply VCC3P3_S3 starts ramping. This is
followed in turn by VCC1P5_S3 [t12].
5. VCC3P3_S3 drives an internal S3 LDO regulator which generates internal 1.0V and
1.8V supplies. These are driven off chip via the OVOUT_1P0_S3 and
OVOUT_1P8_S3 pins [t13, t14].
6. When the internal supplies are stable an internal S3 power-good signal is
generated [t15].
7. The Platform S3_PG pin [t16] is asserted when the Platform generated VCC1P5_S3
Power rails is stable. Based on the power rail sequencing this will ensure that all
platform generated S3 rails will be stable.
8. When both the internal S3 power-good and S3_PG signals are asserted, the SoC is
in a transitional S3 state.
9. The PMC now generates the switch enable S0_3V3_EN which should be used to
switch on the S0 supply VCC3P3_S0 [t17].
10. This is followed by the assertion of S0_1V0_EN to switch on VCC1P0_S0 [t18].
11. After a switch-on time [t19], the S0 supply VCC3P3_S0 starts ramping. This is
followed in turn by VCC1P0_S0 [t21].
12. VCC3P3_S0 drives an internal S0 LDO regulator which generates internal 1.05V
and 1.8V supplies. These are driven off chip via the OVOUT_1P05_S0 and
OVOUT_1P8_S0 pins [t22, t23].
13. Once VCC1P0_S0 is stable the platform should generate an active high power good
signal which is applied to the S0_1P0_PG pin [t25].
14. The PMC now generates the switch enable S0_1V5_EN after S0_1P0_PG asserted.
15. This followed by the assertion of S0_1V5_EN to switch on VCC1P5_S0 [t27].
16. The Platform S0_PG pin [t28] is asserted when the Platform generated VCC1P5_S0
Power rails is stable. Based on the power rail sequencing this will ensure that all
platform generated S0 rails will be stable.
17. All supplies all now on and the system us in state S0.
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Figure 21.
Power Up Sequence
Power In
(t0)
If power button is used S5 – S3/S0
transition occurs upon de-assertion
of PW R_BTN_B.
`
t7 – debounce time
X1000 Input – PWR_BTN
RC Delay – EN_3P3
RC Delay – EN_1P5
VCC3P3_S5
t8
S5 Rails
RC Delay – EN_1P0
(t1)
VCC1P0_S5 (t2)
VCC1P5_S5 (t3)
t4
X1000 Vout – OVOUT_1P8_S5
t6
X1000 Input – S5_PGOOD
X1000 Output – S3_3V3_EN
t8'
t9
X1000 Output – S3_1V5_EN
t10
`
S3 Rails
VCC3P3_S3
t12
VCC1P5_S3
t13
X1000 Vout – OVOUT_1P0_S3
t14
X1000 Vout – OVOUT_1P8_S3
t16
X1000 Input – S3_PGOOD
X1000 Out – S0_3V3_EN
t17
t18
X1000 Out – S0_1V0_EN
S0_1P
0_PG
(t26)
X1000 Out – S0_1V5_EN
t19
VCC3P3_S0
t21
after
erted
t22
X1000 Vout – OVOUT_1P8_S0
t23
X1000 Vout – OVOUT_1P05_S0
t27
_EN a
ss
VCC1P5_S0
S0_1V
5
S0 Rails
VCC1P0_S0
t25
X1000 Input – S0_1P0_PG
X1000 Input – S0_PG
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9.2.5
Power-Up Sequence without G2/G3: No Coin-Cell Battery
This sequence must be adhered to in cases where one of the following conditions apply:
1. The system does not implement an RTC battery (coin cell) or a main battery.
2. The coin cell is drained with no main or a dead main battery.
3. No coin cell implemented or dead coin cell and main battery is being swapped.
AND one of the following conditions also applies:
1. The platform does not implement a power button to initiate a sequence to S0, and
AC power becomes available.
2. The platform does use a power button, but the default first sequence when power is
available is entry into S0.
In these cases, the relative timing between RTC and suspend wells becomes important.
The key point is that, as well as a minimum time, there is a maximum time by which
RTCRST_B must be deasserted. It must happen before an internal reset associated with
the suspend well is deasserted. This is shown in Figure 22.
Figure 22.
Power-Up Sequence without G2/G3
Apply AC Power
VCCRTC_3P3
t0
[ext]
t1min
RTCRST_B
t1max
t2
32kHz Oscillator [int]
VCC3P3_S5
Clock Valid
Oscillator Start-Up
t0'
[ext]
Resume well reset [int]
Initial Power
Up
State G3
(transitional)
State S4/S5
Notes:
1.
This delay is typically created from an RC circuit.
2.
The oscillator startup times are component and design specific. A crystal oscillator can take as long as
2 s to reach a large enough voltage swing. Whereas, a silicon oscillator can have startups times
<10 ms.
3.
System transitions automatically through S4/S5 to S0. See Section 9.2.4 for S0 power on sequence.
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Table 67.
S4/S5 to S0 Timing Parameters (Sheet 1 of 2)
Time
Internal
(SoC)/
External
(Platform)
Description
Min
Max
Units
Notes
t0
N/A
Apply AC
power
t1
ext
VCC3P3_S5
t2
ext
VCC1P0_S5
t3
ext
VCC1P5_S5
t4
int
OVOUT_1P8_
S5 (Delay)
tracks the VCC3P3_S5 with negligible delay.
There is no specific value.
t6
ext
Assertion of
S5_PG
Platform detection of all platform generated
S5 rails to only activate once they are at
~95%, the delay is an RC so is platform
controlled.
1
N/A
N/A
Assume SoC
is in state G3
N/A
Platform related and are specific to the
voltage regulator selected.
t7
int
PWR_BTN_B
debounce
time
2.5
-
ms
Must hold
PWR_BTN_B
low for at
least this
time for
falling edge
to take effect
t8
int
S3_3V3_EN
(Delay)
N/A
N/A
N/A
With respect
to
PWR_BTN_B
event
t8’
int
S3_3V3_EN
(Delay)
N/A
N/A
N/A
auto power
button mode:
With respect
to S5_PG
s
Offset from
S3_3V3_EN
due to SoC
rail
sequencing
requirements
t9
int
S3_1V5_EN
(Delay)
t10
ext
VCC3P3_S3
(Switch
Delay)
t12
ext
VCC1P5_S3
(Switch
Delay)
t13
int
OVOUT_1P8_
S3 (Delay)
t14
int
OVOUT_1P0_
S3 (Delay)
t16
ext
Assertion of
S3_PG
Platform detection of all S3 rails to only
activate once they are at ~95%, the delay is
a RC so is platform controlled.
t17
int
S0_3V3_EN
(Delay)
N/A
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1800
Platform delays based on component delays.
Track the VCC3P3_S3 with negligible delay.
N/A
1
N/A
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Table 67.
S4/S5 to S0 Timing Parameters (Sheet 2 of 2)
Time
Internal
(SoC)/
External
(Platform)
Description
Min
Max
Units
t18
int
S0_1V0_EN
(Delay)
t19
ext
VCC3P3_S0
(Switch
Delay)
t21
ext
VCC1P0_S0
(Switch
Delay)
t22
int
OVOUT_1P8_
S0 (Delay)
t23
int
OVOUT_1P05
_S0 (Delay)
t25
ext
Assertion of
S0_1P0_PG
N/A
N/A
N/A
t26
int
S0_1V5_EN
(Delay)
N/A
N/A
N/A
t27
ext
VCC1P5_S0
(Delay)
Platform delays based on component delays.
t28
ext
Assertion of
S0_PG
Platform detection of all S0 rails to only
activate once they are at ~95%, the delay is
a RC so is platform controlled
N/A
N/A
N/A
Notes
Offset from
S3_3V3_EN
due to SoC
rail
sequencing
requirements
Platform delays based on component delays.
Track the VCC3P3_S0 with negligible delay.
1
1 - Must be asserted after internal power good assertions from respective [S5/S3/S0] LDO regulators
9.2.6
Going to Sleep: Transitions from S0 to S3 or S4/S5
Entry to sleep states (S3, S4/S5) is initiated by any of the following methods:
• Setting the desired type in PM1C.SLPTYPE and setting PM1C.SLPEN in the Legacy
Bridge ACPI registers.
• Detection of a catastrophic event causes a direct transition to S4/S5. This can occur
when the main power well is on, i.e. in the S0 state. Such an event can be initiated
by pressing PWR_BTN_B low for more than 3s. It can also be initiated by software
after detection of a temperature (see Chapter 10.0) or other error event.
9.2.7
Wake Events: Transition from S3 to S0
Wake events are used to return the system to S0 and can only be initiated in state S3.
They are controlled completely by the PMC. Upon exit from sleep states, the
PM1S.WAKE bit in the Legacy Bridge ACPI registers will be set.
Table 68 describes these events:
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Table 68.
Intel® Quark™ SoC X1000 S3 Wake Events
Event
9.2.8
How Enabled
Description
RTC Alarm
Set both PM1S.RTC and PM1E.RTC in
Legacy Bridge
Triggered by RTC asserting IRQ#8 in
Legacy Block
Resume GPIOSUS
Set both GPE0STS.GPIO and
GPE0EN.GPIO in Legacy Bridge
Generates SCI/SMI via ACPI GPE0
registers in Legacy Bridge
External GPE_B (pin)
Set both GPE0S.EGPE and GPE0E.EGPE
in Legacy Bridge
Generates SCI/SMI via General Purpose
Event Register in Legacy Bridge
WAKE_B (pin)
N/A
Input to SoC that indicates a PCI
Express port wants to wake the system.
Power button
Press PWR_BTN_B
PWR_BTN_B press (active low) triggers
transition to S0
Reset button
Press RESET_BTN_B
RESET_BTN_B press (active low)
triggers transition to S0
System Reset Sequences
There are two types of reset:
• Cold Reset: Results in power cycling of all rails except the RTC well. The entire chip
is reset except for the RTC well.
• Warm Reset: Results in a reset without the removal of power. All core logic gets
reset. The suspend and RTC wells are not reset. The system remains in state S0.
Table 69.
SoC Reset Events
Sequence Type
9.2.8.1
How Initiated
Cold Boot
Switch AC power off and then on again
When not in auto power button mode PWR_BTN_B is asserted (low) for at
least 2.5ms
Cold Reset (Internal)
RSTC.COLD_RST bit set
Warm Reset (External)
RESET_BTN_B pin asserted (low) for at least 2.5ms
Warm Reset (Internal)
RSTC.WARM_RST bit set
Cold Boot Sequence
Cold boot happens when AC power is turned off and on again. The power button is used
to wake up the system: assert PWR_BTN_B low for at least 2.5ms. In auto power
button mode (PWR_BTN_B strapped low) the system proceeds straight to state S0 once
the AC power is applied, as documented in the power up sequence.
9.2.8.2
Cold Reset Sequence
Cold reset is initiated by the CPU writing to Reset Control Register bit RSTC.COLD_RST
in the Legacy Bridge. Cold reset causes a full cycling of power. The chip is transitioned
to state S4/S5 and then back to S0, independent of the setting of PWR_BTN_B. All
functions are reset except for those powered from the RTC well.
The Watchdog Timer in the Legacy Bridge can be enabled to generate a cold reset in
the event of a timeout event. This is indistinguishable from a cold reset due to
RSTC.COLD_RST being set.
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9.2.8.3
Warm Reset Sequence (Internal)
Warm reset is initiated by the CPU writing to Reset Control Register bit
RSTC.WARM_RST in the Legacy Bridge. Warm reset causes reset of the CPU and
peripherals without switching off their power supplies.
The Watchdog Timer in the Legacy Bridge can be enabled to generate a warm reset in
the event of a timeout event. This is indistinguishable from a warm reset due to
RSTC.WARM_RST being set.
9.2.8.4
Externally Initiated Warm Reset Sequence
Warm Reset can also be externally initiated by asserting the reset button
RESET_BTN_B. It results in reset without removal of power on any of the supplies.
9.2.9
Handling Power Failures
When the power supply to SoC is removed in a disorderly fashion, either through
removal of the coin-cell battery or a failure on the AC supply, a normal cold boot
sequence should be initiated.
§§
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Thermal Management—Intel® Quark™ SoC X1000
10.0
Thermal Management
10.1
Overview
The Intel® Quark™ SoC X1000 thermal management feature helps in managing the
overall thermal profile of the system to prevent overheating and system breakdown.
The architecture implements various proven methods of maintaining maximum
performance while remaining within the thermal specification.
The thermal management features are:
• On-die thermal sensor
• Supports a hardware trip point and programmable trip points based on the
temperature indicated by thermal sensor.
— Hot trip point is usually used to indicate that the system has reached a
threshold temperature at which damage may occur. A possible action might be
to turn on a fan to cool the system.
— Catastrophic trip point is usually used to indicate that the system has reached
the maximum possible temperature. A possible action might be to shut down
the system.
— See Section 12.7.3.9 for the register description.
10.2
Thermal Sensor
The SoC provides an on-die Thermal Sensor that can be read via Message Bus
registers. The Thermal Sensor provides an 8-bit temperature reading with a resolution
of 1 degree Celsius.
To use the Thermal Sensor:
1. It first must be taken out of reset by setting bit 0 of Msg Port 31:R34h (see
Section 12.7.6.1) to 0 and subsequently enabled via bit 15 of Msg Port 04:RB0h
(see Section 12.7.3.7).
2. Once enabled, registers within the Remote Management Unit can be used to
configure trip points and read the current temperature value.
Table 70.
Thermal Sensor Signals
Signal Name
Direction/
Type
Description
TS_TDA
I/O
Analog
(Reference current – thermal diode anode) max voltage 0.7
TS_TDC
I/O
Analog
(Reference current – thermal diode cathode) max voltage 0.7
I/O
Analog
(Reference current) max voltage 0.7
TS_IREF_N
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Intel® Quark™ SoC X1000—Thermal Management
§§
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Processor Core—Intel® Quark™ SoC X1000
11.0
Processor Core
Processor core features on the Intel® Quark™ SoC X1000 include:
• Single processor core
• Single Instruction 5-stage pipeline
• 32-bit processor with 32-bit data bus
• Integrated Floating Point Unit
• 16 KByte, 4-way shared instruction and data L1 write-back cache
• Integrated local APIC
• Support for IA 32-bit Pentium x86 ISA compatibility
• Supports C0, C1, and C2 states
• Supports Supervisor Mode Execution Protection (SMEP)
• Supports Execute-Disable Page Protection (PAE.XD)
Note:
The processor core provides an integrated Local APIC but does not support the
IA32_APIC_BASE MSR. As a result, the Local APIC is always globally enabled and the
Local APIC base address is fixed at FEE00000h. Attempting to access the
IA32_APIC_BASE MSR causes a general protection fault.
See the Intel® Quark™ SoC X1000 Core Hardware Reference Manual (Order #329678)
for more information.
§§
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Host Bridge—Intel® Quark™ SoC X1000
12.0
Host Bridge
The Host Bridge is a central hub that routes transactions to and from the Intel® Quark™
SoC X1000’s CPU core, DRAM controller, and other functional blocks. In general, it
handles:
• CPU Core Interface: Requests for CPU Core-initiated memory and I/O read and
write operations and processor-initiated message-signaled interrupt transactions
• Device MMIO and PCI configuration access routing
• Buffering and memory arbitration
• PCI Config and MMIO accesses to host device (0/0/0)
12.1
Embedded SRAM (eSRAM)
The Host Bridge contains an interface to 512KB of on-chip, low latency, embedded
SRAM (eSRAM). The eSRAM memory may be used as either 128 x 4KB pages, or in
block mode as a single contiguous 512KB block page. The eSRAM pages may be
mapped anywhere in the physical address space as a DRAM overlay.
The eSRAM is a volatile memory and functionality is provided to flush eSRAM pages to
DRAM as part of entry to an S3 system state. Sections of DRAM overlaid by eSRAM are
inaccessible to all system agents.
12.1.1
Initialization
Immediately on coming out of a warm or cold reset, the Host Bridge initializes eSRAM
data to 0. While this is taking place the register fields ESRAMPGCTRLx.INIT_IN_PROG
(where x=0-127) and ESRAMPGCTRL_BLOCK.BLOCK_INIT_IN_PROG are 1. Software
may map and enable eSRAM pages during this time, but accesses to an eSRAM 4KB
page will not complete until the page has completed initialization.
12.1.2
Configuration
Once an eSRAM page (4KB page or 512KB block page) is enabled (see Section 12.1.2.1
and Section 12.1.2.2), it may only be flushed or disabled as part of an entry to an S3
system state. In order to re-configure an eSRAM page, the Host Bridge must be warm
or cold reset.
12.1.2.1
4KB Page Mode
The Host Bridge provides 128 registers (ESRAMPGCTRLx, where x=0-127) that allow
individual configuration of the 128*4KB eSRAM pages. If the block page is already
enabled, it is not possible to individually map 4KB pages.
To map and enable 4KB page x, the following steps should be followed:
• Set ESRAMPGCTRLx.PG_SYSTEM_ADDRESS_4K to the required address value
• Set ESRAMPGCTRLx.ENABLE_PG to 1
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Software must be careful not to map different eSRAM pages to the same system
address. There is no hardware protection against this.
Figure 23.
eSRAM 4KB Page Mapping
4 Gbyte
MMIO
HMBOUND
2*4KB
unused
2*4KB
unused
10*4KB
unused
DOS DRAM
1*4KB
unused
Physical Address Space
eSRAM DRAM Overlay
DRAM Address
Space
Low DRAM
1 Mbyte
12.1.2.2
512KB Block Page Mode
To map the eSRAM as a single 512KB block page, the register ESRAMPGCTRL_BLOCK is
used. If any of the 4KB pages are already enabled, it is not possible to enable the block
page.
To map and enable the 512KB block page, the following steps should be followed
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Host Bridge—Intel® Quark™ SoC X1000
• Set ESRAMPGCTRL_BLOCK.BLOCK_PG_SYSTEM_ADDRESS_16MB to the required
address value
• Set ESRAMPGCTRL_BLOCK.BLOCK_ENABLE_PG to 1
Figure 24.
eSRAM 512KB Page Mapping
4 Gbyte
MMIO
HMBOUND
Low DRAM
512KB
unused
eSRAM DRAM Overlay
DRAM Address
Space
1 Mbyte
DOS DRAM
Physical Address Space
12.1.3
Configuration Locking
Once an eSRAM page is enabled, the page configuration is implicitly locked and any
further configuration change attempts will fail.
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eSRAM page configuration may be explicitly locked on a per page basis with the
ESRAMPGCTRLx. PAGE_CSR_LOCK and ESRAMPGCTRL_BLOCK.
BLOCK_PAGE_CSR_LOCK fields. Locked eSRAM pages may still be flushed to DRAM.
All eSRAM configuration registers may be locked with the
ESRAMCTRL.eSRAM_GLOBAL_CSR_LOCK field.
12.1.4
ECC Protection
The Host Bridge implements ECC protection for the eSRAM. The eSRAM ECC provides
single bit error correction and double bit error detection (SECDED). It is enabled by
default, but may be disabled/enabled by setting the register field
ESRAMCTRL.SECDED_ENABLE to 0/1.
The ESRAMCERR register provides debug information on the most recent single bit ECC
error. Software may configure a threshold number of correctable ECC errors with the
ESRAMCTRL.ECC_THRESH field. If the ECC_THRESH_SB_MSG_EN field is set to 1, and
the threshold number of correctable ECC errors is reached, the Memory Manager will
send an interrupt to the Remote Management Unit with the opcode 0xD8.
The ESRAMUERR register provides debug information on un-correctable ECC errors. If
an un-correctable eSRAM ECC error occurs the Memory Manager will send a message to
inform the Remote Management Unit. A warm reset of the Host Bridge is required in
this case.
The ESRAMSDROME register can be used to decode where in the eSRAM data word the
most recent ECC error occurred.
12.1.5
Flush to DRAM
In order to flush a page to DRAM, software must set the ESRAMPGCTRLx.FLUSH_PG_ENABLE
field to 1 for 4KB pages or the ESRAMPGCTRL_BLOCK.BLOCK_FLUSH_PG_ENABLE to 1 for the
512KB block page. On an S3 entry or warm reset, firmware will flush pages configured in this way to
DRAM.
12.2
Isolated Memory Regions (IMR)
The Host Bridge provides support for Isolated Memory Regions (IMRs). An IMR is an
area of system memory that is accessible only to certain system agents. The range and
access rights of an IMR are software configurable. There are 3 types of IMR
• General IMR
• Host Memory I/O Boundary (HMBOUND) IMR
• System Management Mode (SMM) IMR
There are 8 general IMRs available. The general IMRs allow any location of system
memory- with a 1KB granularity, to have software controlled access rights. The upper
and lower boundaries of a general IMR are set via the IMRxL.IMRL and IMRxH.IMRH
register fields (where x=one of the 8 IMRs). Read access rights are controlled via the
IMRxRM registers, write access rights are controlled via the IMRx.WM register fields.
General IMRs may be overlapping. In this case, in order be allowed access a particular
region in memory, an agent will need to have access rights to all the IMRs which
contain that region.
The HMBOUND IMR prevents access by non host agents to any region of memory above
HMBOUND. HMBOUND is software configured in the HMBOUND register.
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The SMM IMR prevents access by non host agents to any region of memory contained
within the SMM region. The SMM region access rights are configured in the HSMMCTL
register.
12.2.1
IMR Violation
If an agent is blocked attempting to write to a region covered by an IMR, its write data
is dropped, and system memory is not updated.
If an agent is blocked attempting to read to a region covered by an IMR, all 0s are
returned for read data. The region of memory is still read (with ECC checking/
correction performed if enabled), but false (all 0) data is returned to the agent instead
of the real data from system memory.
If the register field BIMRVCTL.EnableIMRInt is set to 1, and an IMR violation occurs, an
interrupt will be sent to the Remote Management Unit with opcode 0xC0. In this case,
software may use the BIMRVCTL register to debug the cause of the violation.
12.2.2
IMR Locking
The following settings lock the relevant IMR
• General IMR: set IMRxL.IMR_LOCK to 1
• HMBOUND IMR: set HMBOUND.HMBOUND_LOCK to 1
• SMM IMR: set HSMMCTL.SMM_LOCK to 1
Until HMBOUND is configured and locked, any General IMR region that is programmed
will only be applied if the General IMR’s register set is not locked. This allows software
to configure a General IMR region and test it without locking it’s register set. Once a
General IMR register set is locked, however, HMBOUND is required to be configured and
locked or the security mechanism will deny all accesses to that General IMR region.
Until HMBOUND is configured and locked, the SMM IMR region that is programmed will
only be applied if the SMM IMR’s register set is not locked. This allows software to
configure the SMM IMR region and test it without locking it’s register set. Once the
SMM IMR register set is locked, however, HMBOUND is required to be configured and
locked or the security mechanism will deny all accesses to the SMM IMR region.
12.3
Remote Management Unit DMA
The Remote Management Unit supports DMA transfers between System Memory and
Legacy SPI Flash. The DMA engine is used on boot-up to perform the initial firmware
fetch from SPI Flash. In addition, this can be used for shadowing firmware to DRAM or
eSRAM.
Remote Management Unit message bus registers - SPI DMA Count Register
(P_CFG_60), SPI DMA Destination Register (P_CFG_61) and SPI DMA Source Register
(P_CFG_62) are used to control DMA transfers. These registers are managed by the
Remote Management Unit firmware.
The SPI DMA Count Register (P_CFG_60) should be programmed after the SPI DMA
Source Register (P_CFG_62) and the SPI DMA Destination Register (P_CFG_61) as
writing to the SPI DMA Count Register (P_CFG_60) will trigger the start of the DMA
transfer.
See Option Register 1(P_CFG_72) bit [0] for details on how to disable DMA
functionality.
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12.4
Register Map
See Chapter 5.0, “Register Access Methods” for additional information.
Figure 25.
Intel® Quark™ SoC X1000 Host Bridge Register Map
PCI Space
CPU
Core
Host Bridge
D:0,F:0
PCI
CAM
(I/O)
Bus 0
PCI
ECAM
(Mem)
I 2C*/GPIO F:2
PCIe*
D:23
SPI1 F:1
IO Fabric
D:21
SPI0 F:0
RP0 F:0
RP0 F:1
Legacy Bridge
D:31, F:0
SDIO/eMMC F:0
HSUART0 F:1
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
MAC0 F:6
MAC1 F:7
12.5
PCI Configuration Registers
Table 71.
Summary of PCI Configuration Registers—0/0/0
Offset Start
Offset End
Default
Value
Register ID—Description
0h
3h
“PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—Offset 0h” on
page 133
09588086h
4h
7h
“PCI Status and Command Fields (PCI_STATUS_COMMAND)—Offset 4h” on
page 133
00000007h
8h
Bh
“PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)—Offset 8h” on
page 134
06000000h
Ch
Fh
“PCI Miscellaneous Fields (PCI_MISC)—Offset Ch” on page 134
00000000h
2Fh
“PCI Subsystem ID and Subsystem Vendor ID Fields (PCI_SUBSYSTEM)—Offset
2Ch” on page 135
00000000h
2Ch
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Table 71.
Offset Start
Summary of PCI Configuration Registers—0/0/0 (Continued)
Offset End
Default
Value
Register ID—Description
D0h
D3h
“Message Bus Control Register (MCR) (SB_PACKET_REG)—Offset D0h” on
page 135
00000000h
D4h
D7h
“Message Data Register (MDR) (SB_DATA_REG)—Offset D4h” on page 136
00000000h
D8h
DBh
“Message Control Register eXtension (MCRX) (SB_ADDR_EXTN_REG)—Offset
D8h” on page 136
00000000h
F8h
FBh
“Manufacturer ID (PCI_MANUFACTURER)—Offset F8h” on page 137
00000FB1h
12.5.1
PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—
Offset 0h
PCI Device ID
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PCI_DEVICE_VENDOR: [B:0, D:0, F:0] + 0h
Default: 09588086h
31
0
0
0
24
1
0
0
1
20
0
1
0
1
16
1
0
0
0
12
1
0
0
0
8
0
0
0
12.5.2
0
4
1
0
0
0
0
0
1
1
0
VENDOR_ID
DEVICE_ID
0
28
Bit
Range
Default &
Access
31: 16
0958h
RO
Device ID (DEVICE_ID): PCI Device ID
15: 0
8086h
RO
Vendor ID (VENDOR_ID): PCI Vendor ID for Intel
Description
PCI Status and Command Fields (PCI_STATUS_COMMAND)—
Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PCI_STATUS_COMMAND: [B:0, D:0, F:0] + 4h
Default: 00000007h
0
0
0
24
0
0
0
0
STATUS
0
28
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20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
1
1
1
COMMAND
31
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12.5.3
Bit
Range
Default &
Access
31: 16
0000h
RO
Status (STATUS): Hardwired to 0.
15: 0
0007h
RO
Command (COMMAND): Hardwired to 0.
Description
PCI Class Code and Revision ID Fields
(PCI_CLASS_REVISION)—Offset 8h
PCI Revision ID
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PCI_CLASS_REVISION: [B:0, D:0, F:0] + 8h
Default: 06000000h
31
0
0
24
0
0
1
1
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
Bit
Range
Default &
Access
060000h
RO
31: 8
12.5.4
0
0
0
0
Description
Class Code (CLASS_CODE): PCI Class Code for Chipset.
00h
RO
7: 0
0
0
REVISION_ID
CLASS_CODE
0
28
Revision ID (REVISION_ID): PCI Revision ID
PCI Miscellaneous Fields (PCI_MISC)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PCI_MISC: [B:0, D:0, F:0] + Ch
Default: 00000000h
0
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0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CACHE_LINE_SIZE
0
24
LATENCY
0
BIST
0
28
HEADER
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12.5.5
Bit
Range
Default &
Access
31: 24
00h
RO
BIST (BIST): PCI BIST Field
23: 16
00h
RO
Header Type (HEADER): PCI Header Type Field
15: 8
00h
RO
Latency Timer (LATENCY): PCI Latency Timer Field
7: 0
00h
RO
Cache Line Size (CACHE_LINE_SIZE): PCI Cache Line Size Field
Description
PCI Subsystem ID and Subsystem Vendor ID Fields
(PCI_SUBSYSTEM)—Offset 2Ch
PCI Subsystem ID
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PCI_SUBSYSTEM: [B:0, D:0, F:0] + 2Ch
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
SUBSYSTEM_VENDOR_ID
0
28
12.5.6
0
4
0
0
0
0
0
0
0
0
0
SUBSYSTEM_ID
31
Bit
Range
Default &
Access
31: 16
0000h
RO
Subsystem Vendor ID (SUBSYSTEM_VENDOR_ID): PCI Subsystem Vendor ID
15: 0
0000h
RO
Subsystem ID (SUBSYSTEM_ID): PCI Subsystem ID
Description
Message Bus Control Register (MCR) (SB_PACKET_REG)—Offset
D0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
SB_PACKET_REG: [B:0, D:0, F:0] + D0h
Default: 00000000h
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0
0
0
0
0
0
0
12.5.7
0
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV
0
16
SB_BE
0
20
SB_ADDR
0
24
SB_OPCODE
0
28
SB_PORT
31
Bit
Range
Default &
Access
31: 24
00h
WO
OpCode (SB_OPCODE): The operation to be performed on the target port.
23: 16
00h
WO
Port (SB_PORT): The device or unit to be targeted by the message bus transaction.
15: 8
00h
WO
Offset/Register (SB_ADDR): Bits 7:0 of the private register offset to be targeted by
the message bus transaction. This field applies only to register read and write
operations.
7: 4
0h
WO
Byte Enable (SB_BE): The byte enables to be used by the triggered transaction. This
field applies only to register read and write operations.
3: 0
0h
WO
Reserved (RSV): Reserved.
Description
Message Data Register (MDR) (SB_DATA_REG)—Offset D4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
SB_DATA_REG: [B:0, D:0, F:0] + D4h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
SB_DATA
0
28
Bit
Range
31: 0
12.5.8
Default &
Access
Description
0h
RW
Data (SB_DATA): Used as the place to store the data when the operation triggered is
a read semantic, or the place to get the data if the triggered operation is a data write
semantic.
Message Control Register eXtension (MCRX)
(SB_ADDR_EXTN_REG)—Offset D8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
SB_ADDR_EXTN_REG: [B:0, D:0, F:0] + D8h
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
136
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
0
0
24
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
SB_ADDR_EXTN
0
28
Bit
Range
Default &
Access
00h
RO
7: 0
12.5.9
0
0
0
0
Description
Offset/Register Extension (SB_ADDR_EXTN): This is used for messages sent to
end points that require more than 8 bits for the offset/register. These bits are a direct
extension of MCR[15:8].
000000h
RW/S
31: 8
0
0
RSV
31
Reserved (RSV): Reserved.
Manufacturer ID (PCI_MANUFACTURER)—Offset F8h
Manufacturer ID
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PCI_MANUFACTURER: [B:0, D:0, F:0] + F8h
Default: 00000FB1h
28
0
0
24
0
0
0
0
0
20
0
0
0
0
16
0
0
0
RSV
0
Bit
Range
Default &
Access
31: 24
00h
RO
23: 0
0
12
0
0
0
0
8
1
1
1
1
4
1
0
1
1
0
0
0
0
1
MANUFACTURER_ID
31
000FB1h
RO
November 2014
Document Number: 329676-004US
Description
Reserved (RSV): Reserved.
Manufacturer ID (MANUFACTURER_ID): Manufacturer ID
Intel® Quark™ SoC X1000
Datasheet
137
Intel® Quark™ SoC X1000—Host Bridge
12.6
IO Mapped Register
12.6.1
ACPI Processor Block
Table 72.
Summary of I/O Registers—PMBA
Offset
Start
Offset End
Default
Value
Register ID—Description
0h
3h
“Processor Control (P_CNT)—Offset 0h” on page 138
00000000h
4h
7h
“Level 2 Register (P_LVL2)—Offset 4h” on page 138
00000000h
Ch
Fh
“C6 Control Register (P_C6C)—Offset Ch” on page 139
00000000h
12.6.1.1
Processor Control (P_CNT)—Offset 0h
Access Method
Type: I/O Register
(Size: 32 bits)
P_CNT: [PMBA] + 0h
PMBA Type: Message Bus Register (Size: 32 bits)
PMBA Reference: [Port: 0x04] + 70h
Default: 00000000h
0
0
0
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
Description
31:5
0b
RO
Reserved (P_CNT_RSV2): Reserved.
4
0b
RW
Throttle Enable (THROTL_EN): When set and the processor is in C0, it enables
software-controlled STPCLK# throttling. The duty cycle is selected via
THROTL_DUTY_CYCLE. It remains in effect on each re-entry to C0 as long as enabled.
000b
RW
Throttle Duty Cycle (THROTL_DUTY_CYCLE): This field determines the duty cycle of
throttling (percentage of time STPCLK# is asserted) when throttling is enabled.
000b : 50% (Default)
001b : 87.5%
010b : 75%
011b : 62.5%
100b : 50%
101b : 37.5%
110b : 35%
111b : 12.5%
3:1
0
12.6.1.2
0
4
P_CNT_RSV1
0
20
THROTL_DUTY_CYCLE
0
24
P_CNT_RSV2
0
28
THROTL_EN
31
0b
RO
Reserved (P_CNT_RSV1): Reserved.
Level 2 Register (P_LVL2)—Offset 4h
Level 2 Register is an 8-bit register that is used to generate requests to enter C2.
Intel® Quark™ SoC X1000
Datasheet
138
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Access Method
Type: I/O Register
(Size: 32 bits)
P_LVL2: [PMBA] + 4h
PMBA Type: Message Bus Register (Size: 32 bits)
PMBA Reference: [Port: 0x04] + 70h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
Bit
Range
12.6.1.3
0
0
0
0
0
0
GO_TO_C2
P_LVL2_RSV
0
28
Default &
Access
Description
31:8
0b
RW
Reserved (P_LVL2_RSV): Reserved.
7:0
00h
RO
Go to C2 (GO_TO_C2): Reads to this register return all zeroes, writes have no effect.
Reads to this register generate a C2 request.
C6 Control Register (P_C6C)—Offset Ch
This is a read only register. It provides information on the last C-state entered and
residency in the last entered C-state
Access Method
Type: I/O Register
(Size: 32 bits)
P_C6C: [PMBA] + Ch
PMBA Type: Message Bus Register (Size: 32 bits)
PMBA Reference: [Port: 0x04] + 70h
Default: 00000000h
31
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
Bit
Range
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RESIDENCY_COUNT
LAST_CSTATE
0
P_C6C_RSV
0
28
Default &
Access
Description
31
0b
RO
Reserved (P_C6C_RSV): Reserved.
30:27
0b
RO
Last Entered C-State (LAST_CSTATE): Once CPU transitions from C0 to C2, it
updates this register.
0000b : C0
0010b : C2
All other values are reserved.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
139
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
0b
RO
26:0
12.6.2
Description
Residency Count (RESIDENCY_COUNT): This register reports the residency in the
last entered C-state. The granularity used is microseconds
SPI DMA Block
DMA functionality must be disabled on boot completion to prevent an attacker from
using it to take control of the system.
12.6.2.1
Option Register 1(P_CFG_72) —Offset 72h
Access Method
Type: I/O Register
(Size: 32 bits)
Offset: [Port: 0x04] + 72h
SPI_DMA_BAR Type: Message Bus Register (Size: 32 bits)
SPI_DMA_BAR Reference: [Port: 0x04] + 72h
Default: 00000000h
31
0
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
Field Name (ID): Description
31:1
0
RO
Reserved (RSVD): Reserved.
0
0
RW
DMA_DISABLE: Remote Management Unit DMA disable. Once set RMU DMA
functionality is disabled until system reset
12.7
Message Bus Register
12.7.1
Host Bridge Arbiter (Port 0x00)
Table 73.
Summary of Message Bus Registers—0x00
Offset
Default
Value
Register ID—Description
0h
“Enhanced Configuration Space (AEC_CTRL)—Offset 0h” on page 141
00000000h
21h
“STATUS—Offset 21h” on page 141
00000000h
50h
“Requester ID Match Control (ASUBCHAN_CTRL)—Offset 50h” on page 142
00000000h
51h
“Requester ID Match Sub-Channel 1 (ASUBCHAN1_MATCH)—Offset 51h” on page 143
00000000h
52h
“Requester ID Match Sub-Channel 2 (ASUBCHAN2_MATCH)—Offset 52h” on page 143
00000000h
53h
“Requester ID Match Sub-Channel 3 (ASUBCHAN3_MATCH)—Offset 53h” on page 144
00000000h
Intel® Quark™ SoC X1000
Datasheet
140
0
DMA_DISABLE
Reserved
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.1.1
Enhanced Configuration Space (AEC_CTRL)—Offset 0h
Access Method
Type: Message Bus Register
(Size: 32 bits)
AEC_CTRL: [Port: 0x00] + 0h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
RSV
Bit
Range
12.7.1.2
0
8
0
EC_ENABLE
0
24
EC_BASE
0
28
Default &
Access
Description
31:28
0b
RW
Enhanced Configuration Space Base Address (EC_BASE): When EC_BASE
matches bits [31:28] of a system memory address that has been forwarded to the Host
Bridge Arbiter and Enhanced Configuration operation is enabled, the corresponding
operation is treated as an Enhanced Configuration Space access.
27:1
0b
RO
Reserved (RSV): Reserved.
0
0b
RW
Enable (EC_ENABLE): Enables Enhanced Configuration operation
STATUS—Offset 21h
Access Method
Type: Message Bus Register
(Size: 32 bits)
ASTATUS: [Port: 0x00] + 21h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
Bit
Range
31:12
Default &
Access
0b
RO
November 2014
Document Number: 329676-004US
0
0
0
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
STATUS0_DEFAULT_VALUE
0
12
STATUS1_DEFAULT_VALUE
0
16
RSV1
0
20
STATUS0_RAISED_VALUE
0
24
RSV2
0
28
STATUS1_RAISED_VALUE
31
Description
RSV2: Reserved
Intel® Quark™ SoC X1000
Datasheet
141
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
Description
STATUS1_RAISED_VALUE: Elevated Status value presented to the Memory Manager
for Virtual Channel 1 (VC1) accesses from the Host Bridge Arbiter.
0b
RW
11:10
Encodings as follows:
2'b00 = Casual - Channel is requesting low priority, will be serviced only if convenient.
2'b01 = Reserved.
2'b10 = Normal - Channel is requesting normal priority for servicing.
2'b11 = Urgent - Channel is requesting high priority for servicing.
STATUS0_RAISED_VALUE: Elevated Status value presented to the Memory Manager
for Virtual Channel 0 (VC0) accesses from the Host Bridge Arbiter.
9:8
0b
RW
7:4
0b
RO
Encodings as follows:
2'b00 = Casual - Channel is requesting low priority, will be serviced only if convenient.
2'b01 = Reserved.
2'b10 = Normal - Channel is requesting normal priority for servicing.
2'b11 = Urgent - Channel is requesting high priority for servicing.
RSV1: Reserved
STATUS1_DEFAULT_VALUE: Default Status value presented to the Memory Manager
for Virtual Channel 1 (VC1) accesses from the Host Bridge Arbiter.
0b
RW
3:2
Encodings as follows:
2'b00 = Casual - Channel is requesting low priority, will be serviced only if convenient.
2'b01 = Reserved.
2'b10 = Normal - Channel is requesting normal priority for servicing.
2'b11 = Urgent - Channel is requesting high priority for servicing.
STATUS0_DEFAULT_VALUE: Default Status value presented to the Memory Manager
for Virtual Channel 0 (VC0) accesses from the Host Bridge Arbiter.
0b
RW
1:0
12.7.1.3
Encodings as follows:
2'b00 = Casual - Channel is requesting low priority, will be serviced only if convenient.
2'b01 = Reserved.
2'b10 = Normal - Channel is requesting normal priority for servicing.
2'b11 = Urgent - Channel is requesting high priority for servicing.
Requester ID Match Control (ASUBCHAN_CTRL)—Offset 50h
Access Method
Type: Message Bus Register
(Size: 32 bits)
ASUBCHAN_CTRL: [Port: 0x00] + 50h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
Intel® Quark™ SoC X1000
Datasheet
142
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SUB_CHAN_MATCH_LOCK
0
4
SUB_CHAN1_MRQID_ENABLE
0
8
RSV1
0
12
RSV2
0
16
SUB_CHAN2_MRQID_ENABLE
0
20
RSV3
0
24
RSV4
0
28
SUB_CHAN3_MRQID_ENABLE
31
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.1.4
Default &
Access
Description
31:7
0b
RO
Reserved (RSV4): Reserved.
6
0b
RO
Reserved (RSV3): Reserved.
5
0b
RW/L
4
0b
RO
3
0b
RW/L
2
0b
RO
1
0b
RW/L
Enable Sub-Channel 1 Matching (SUB_CHAN1_MRQID_ENABLE): When set,
register 51h will be enabled for Sub-Channel 1 generation on a Requester ID match.
0
0b
RW/O
Lock Requester ID Matching Registers (SUB_CHAN_MATCH_LOCK): When set,
registers 50h-53h will be set to read-only, in order to preserve the integrity of the IMR
Sub-Channel mechanism.
Enable Sub-Channel 3 Matching (SUB_CHAN3_MRQID_ENABLE): When set,
register 53h will be enabled for Sub-Channel 3 generation on a Requester ID match.
Reserved (RSV2): Reserved.
Enable Sub-Channel 2 Matching (SUB_CHAN2_MRQID_ENABLE): When set,
register 52h will be enabled for Sub-Channel 2 generation on a Requester ID match.
Reserved (RSV1): Reserved.
Requester ID Match Sub-Channel 1 (ASUBCHAN1_MATCH)—Offset 51h
Access Method
Type: Message Bus Register
(Size: 32 bits)
ASUBCHAN1_MATCH: [Port: 0x00] + 51h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
Bit
Range
0
0
0
0
16
0
0
0
0
Default &
Access
0b
RO
Reserved (RSV2): Reserved.
22:16
0b
RO
Reserved (RSV1): Reserved.
0b
RW/L
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Description
31:23
15:0
12.7.1.5
0
20
SUB_CHAN1_MRQID
0
24
RSV2
0
28
RSV1
31
Requester ID Match Value (SUB_CHAN1_MRQID): Value compared to an incoming
Requester ID value to determine its Sub-Channel.
Requester ID Match Sub-Channel 2 (ASUBCHAN2_MATCH)—Offset 52h
Access Method
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
143
Intel® Quark™ SoC X1000—Host Bridge
Type: Message Bus Register
(Size: 32 bits)
ASUBCHAN2_MATCH: [Port: 0x00] + 52h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
Bit
Range
0
0
0
0
12
0
Default &
Access
0
0
0
8
0
0
0
0b
RO
Reserved (RSV2): Reserved.
22:16
0b
RO
Reserved (RSV1): Reserved.
0b
RW/L
0
4
0
0
0
0
0
0
0
0
0
Description
31:23
15:0
12.7.1.6
16
SUB_CHAN2_MRQID
0
24
RSV2
0
28
RSV1
31
Requester ID Match Value (SUB_CHAN2_MRQID): Value compared to an incoming
Requester ID value to determine its Sub-Channel.
Requester ID Match Sub-Channel 3 (ASUBCHAN3_MATCH)—Offset 53h
Access Method
Type: Message Bus Register
(Size: 32 bits)
ASUBCHAN3_MATCH: [Port: 0x00] + 53h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
Bit
Range
0
20
0
0
0
0
16
0
0
0
0
Default &
Access
0b
RO
Reserved (RSV2): Reserved.
22:16
0b
RO
Reserved (RSV1): Reserved.
Intel® Quark™ SoC X1000
Datasheet
144
0b
RW/L
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Description
31:23
15:0
12
0
SUB_CHAN3_MRQID
28
0
RSV2
0
RSV1
31
Requester ID Match Value (SUB_CHAN3_MRQID): Value compared to an incoming
Requester ID value to determine its Sub-Channel.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.2
Host Bridge (Port 0x03)
Table 74.
Summary of Message Bus Registers—0x03
Offset
3h
Default
Value
Register ID—Description
“Host Miscellaneous Controls 2 (HMISC2)—Offset 3h” on page 146
00170001h
4h
“Host System Management Mode Controls (HSMMCTL)—Offset 4h” on page 147
00060006h
8h
“Host Memory I/O Boundary (HMBOUND)—Offset 8h” on page 148
40000000h
9h
“Extended Configuration Space (HECREG)—Offset 9h” on page 148
00000000h
Ah
“Miscellaneous Legacy Signal Enables (HLEGACY)—Offset Ah” on page 149
00008000h
Ch
“Host Bridge Write Flush Control (HWFLUSH)—Offset Ch” on page 149
00010000h
40h
“MTRR Capabilities (MTRR_CAP)—Offset 40h” on page 150
00000908h
41h
“MTRR Default Type (MTRR_DEF_TYPE)—Offset 41h” on page 151
00000000h
42h
“MTRR Fixed 64KB Range 0x00000 (MTRR_FIX64K_00000)—Offset 42h” on page 151
00000000h
43h
“MTRR Fixed 64KB Range 0x40000 (MTRR_FIX64K_40000)—Offset 43h” on page 152
00000000h
44h
“MTRR Fixed 16KB Range 0x80000 (MTRR_FIX16K_80000)—Offset 44h” on page 152
00000000h
45h
“MTRR Fixed 16KB Range 0x90000 (MTRR_FIX16K_90000)—Offset 45h” on page 153
00000000h
46h
“MTRR Fixed 16KB Range 0xA0000 (MTRR_FIX16K_A0000)—Offset 46h” on page 154
00000000h
47h
“MTRR Fixed 16KB Range 0xB0000 (MTRR_FIX16K_B0000)—Offset 47h” on page 154
00000000h
48h
“MTRR Fixed 4KB Range 0xC0000 (MTRR_FIX4K_C0000)—Offset 48h” on page 155
00000000h
49h
“MTRR Fixed 4KB Range 0xC4000 (MTRR_FIX4K_C4000)—Offset 49h” on page 155
00000000h
4Ah
“MTRR Fixed 4KB Range 0xC8000 (MTRR_FIX4K_C8000)—Offset 4Ah” on page 156
00000000h
4Bh
“MTRR Fixed 4KB Range 0xCC000 (MTRR_FIX4K_CC000)—Offset 4Bh” on page 156
00000000h
4Ch
“MTRR Fixed 4KB Range 0xD0000 (MTRR_FIX4K_D0000)—Offset 4Ch” on page 157
00000000h
4Dh
“MTRR Fixed 4KB Range 0xD40000 (MTRR_FIX4K_D4000)—Offset 4Dh” on page 158
00000000h
4Eh
“MTRR Fixed 4KB Range 0xD8000 (MTRR_FIX4K_D8000)—Offset 4Eh” on page 158
00000000h
4Fh
“MTRR Fixed 4KB Range 0xDC000 (MTRR_FIX4K_DC000)—Offset 4Fh” on page 159
00000000h
50h
“MTRR Fixed 4KB Range 0xE0000 (MTRR_FIX4K_E0000)—Offset 50h” on page 159
00000000h
51h
“MTRR Fixed 4KB Range 0xE4000 (MTRR_FIX4K_E4000)—Offset 51h” on page 160
00000000h
52h
“MTRR Fixed 4KB Range 0xE8000 (MTRR_FIX4K_E8000)—Offset 52h” on page 160
00000000h
53h
“MTRR Fixed 4KB Range 0xEC000 (MTRR_FIX4K_EC000)—Offset 53h” on page 161
00000000h
54h
“MTRR Fixed 4KB Range 0xF0000 (MTRR_FIX4K_F0000)—Offset 54h” on page 161
00000000h
55h
“MTRR Fixed 4KB Range 0xF4000 (MTRR_FIX4K_F4000)—Offset 55h” on page 162
00000000h
56h
“MTRR Fixed 4KB Range 0xF8000 (MTRR_FIX4K_F8000)—Offset 56h” on page 163
00000000h
57h
“MTRR Fixed 4KB Range 0xFC000 (MTRR_FIX4K_FC000)—Offset 57h” on page 163
00000000h
58h
“System Management Range Physical Base (MTRR_SMRR_PHYSBASE)—Offset 58h” on page 164
00000000h
59h
“System Management Range Physical Mask (MTRR_SMRR_PHYSMASK)—Offset 59h” on page 164
00000000h
5Ah
“MTRR Variable Range Physical Base 0 (MTRR_VAR_PHYSBASE0)—Offset 5Ah” on page 165
00000000h
5Bh
“MTRR Variable Range Physical Mask 0 (MTRR_VAR_PHYSMASK0)—Offset 5Bh” on page 165
00000000h
5Ch
“MTRR Variable Range Physical Base 1 (MTRR_VAR_PHYSBASE1)—Offset 5Ch” on page 166
00000000h
5Dh
“MTRR Variable Range Physical Mask 1 (MTRR_VAR_PHYSMASK1)—Offset 5Dh” on page 167
00000000h
5Eh
“MTRR Variable Range Physical Base 2 (MTRR_VAR_PHYSBASE2)—Offset 5Eh” on page 167
00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
145
Intel® Quark™ SoC X1000—Host Bridge
Table 74.
Summary of Message Bus Registers—0x03 (Continued)
Offset
Default
Value
Register ID—Description
5Fh
“MTRR Variable Range Physical Mask 2 (MTRR_VAR_PHYSMASK2)—Offset 5Fh” on page 168
00000000h
60h
“MTRR Variable Range Physical Base 3 (MTRR_VAR_PHYSBASE3)—Offset 60h” on page 168
00000000h
61h
“MTRR Variable Range Physical Mask 3 (MTRR_VAR_PHYSMASK3)—Offset 61h” on page 169
00000000h
62h
“MTRR Variable Range Physical Base 4 (MTRR_VAR_PHYSBASE4)—Offset 62h” on page 169
00000000h
63h
“MTRR Variable Range Physical Mask 4 (MTRR_VAR_PHYSMASK4)—Offset 63h” on page 170
00000000h
64h
“MTRR Variable Range Physical Base 5 (MTRR_VAR_PHYSBASE5)—Offset 64h” on page 171
00000000h
65h
“MTRR Variable Range Physical Mask 5 (MTRR_VAR_PHYSMASK5)—Offset 65h” on page 171
00000000h
66h
“MTRR Variable Range Physical Base 6 (MTRR_VAR_PHYSBASE6)—Offset 66h” on page 172
00000000h
67h
“MTRR Variable Range Physical Mask 6 (MTRR_VAR_PHYSMASK6)—Offset 67h” on page 172
00000000h
68h
“MTRR Variable Range Physical Base 7 (MTRR_VAR_PHYSBASE7)—Offset 68h” on page 173
00000000h
69h
“MTRR Variable Range Physical Mask 7 (MTRR_VAR_PHYSMASK7)—Offset 69h” on page 173
00000000h
12.7.2.1
Host Miscellaneous Controls 2 (HMISC2)—Offset 3h
Access Method
Type: Message Bus Register
(Size: 32 bits)
HMISC2: [Port: 0x03] + 3h
Op Codes:
10h - Read, 11h - Write
Default: 00170001h
Bit
Range
0
0
1
16
0
1
1
1
Default &
Access
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
1
RSVD
20
0
ESEG_RD_DRAM
0
RSV03
0
FSEG_RD_DRAM
0
ABSEG_IN_DRAM
24
0
RSV04
0
OR_PM
0
RSV05
28
0
RSV43
0
PBE_STATUS
31
Description
31:23
0h
RO
Reserved (RSV43): Reserved.
22
0b
RO
PBE Status (PBE_STATUS): Reflects the value of the Pending Break Event pin from
the processor
21
0b
RO
Reserved (RSV05): Reserved.
20:16
Intel® Quark™ SoC X1000
Datasheet
146
10111b
RW
OR PM Signals from Legacy Bridge (OR_PM): When set, the Host Bridge will OR the
power management signals driven by the Legacy Bridge with the internal values
generated by the Remote Management Unit. This field specifies, on a signal-by-signal
basis, whether a given bit should be driven via a message from the Remote
Management Unit or via a direct pin from the Legacy Bridge.
[20] Reserved
[19] SMI
[18] NMI
[17] INIT
[16] INTR
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
0000h
RO
15:5
12.7.2.2
Description
Reserved (RSV04): Reserved.
4
0b
RW
A and B Segment in DRAM (ABSEG_IN_DRAM): When this bit is set, memory reads
and writes targeting A-segment or B-segment are routed to DRAM
3
0b
RO
Reserved (RSV03): Reserved.
2
0b
RW
Read F Segment from DRAM (FSEG_RD_DRAM): When this bit is set, memory
reads targeting F-segment are routed to DRAM
1
0b
RW
Read E Segment from DRAM (ESEG_RD_DRAM): When this bit is set, memory
reads targeting E-segment are routed to DRAM
0
1b
RO
Reserved (RSVD): Reserved.
Host System Management Mode Controls (HSMMCTL)—Offset 4h
Access Method
Type: Message Bus Register
(Size: 32 bits)
HSMMCTL: [Port: 0x03] + 4h
Op Codes:
10h - Read, 11h - Write
Default: 00060006h
Bit
Range
31:20
0
0
0
0
1
1
0
Default &
Access
000h
RW/L
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
SMM_LOCK
0
0
SMM_RD_OPEN
0
4
RSV06
0
8
SMM_WR_OPEN
0
12
SMM_START
0
RSV07
0
16
NON_HOST_SMM_RD_OPEN
0
20
RSV42
0
24
SMM_END
0
28
NON_HOST_SMM_WR_OPEN
31
Description
SMM Upper Bound (SMM_END): These bits are compared with bits [31:20] of the
incoming address to determine the upper 1MB aligned value of the protected SMM
range.
19
0b
RO
18
1b
RW/L
Non-Host SMM Writes Open (NON_HOST_SMM_WR_OPEN): Allow writes to SMM
space from non-host devices. The Memory Manager uses this bit to allow non-host
writes to the SMM space defined by the SMM Start and SMM End fields
17
1b
RW/L
Non-Host SMM Reads Open (NON_HOST_SMM_RD_OPEN): Allow reads to SMM
space from non-host devices. The Memory Manager uses this bit to allow non-host reads
to the SMM space defined by the SMM Start and SMM End fields
16
0b
RO
November 2014
Document Number: 329676-004US
Reserved (RSV42): Reserved.
Reserved (RSV07): Reserved.
Intel® Quark™ SoC X1000
Datasheet
147
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
Description
000h
RW/L
SMM Lower Bound (SMM_START): These bits are compared with bits [31:20] of the
incoming address to determine the lower 1MB aligned value of the protected SMM
range.
15:4
12.7.2.3
3
0b
RO
2
1b
RW/L
SMM Writes Open (SMM_WR_OPEN): Allow non-SMM writes to SMM space. This bit
allows processor writes to the SMM space defined by the SMM Start and SMM End fields
even when the processor is not in SMM mode
1
1b
RW/L
SMM Reads Open (SMM_RD_OPEN): Allow non-SMM reads to SMM space. This bit
allows processor reads to the SMM space defined by the SMM Start and SMM End fields
even when the processor is not in SMM mode
0
0b
RW/O
SMM Locked (SMM_LOCK): When set, this bit locks this register and prevents write
access until the system is reset
Reserved (RSV06): Reserved.
Host Memory I/O Boundary (HMBOUND)—Offset 8h
Access Method
Type: Message Bus Register
(Size: 32 bits)
HMBOUND: [Port: 0x03] + 8h
Op Codes:
10h - Read, 11h - Write
Default: 40000000h
0
0
0
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
31:12
12.7.2.4
4
0
0
0
0
0
0
0
0
0
HMBOUND_LOCK
0
20
IO_DISABLE
1
24
HMBOUND
0
28
RSV10
31
Default &
Access
Description
40000h
RW/L
Host IO Boundary (HMBOUND): This register field is compared with the bits [31:12]
of incoming memory accesses to determine if the transaction should be routed to
Memory space or MMIO space. If address bits[31:12] are greater than or equal to the
Host IO Boundary then the transaction is routed to MMIO space.
This allows the Host IO Boundary to be set to a 4KB aligned boundary. By default, the
Host IO Boundary is set at 1GB.
11:2
000h
RO
Reserved (RSV10): Reserved.
1
0b
RW/L
Host IO Disable (IO_DISABLE): When this bit is set, all accesses will be sent to
memory regardless of the address with the exception of accesses to the A, B, E and F
Segments. Access to the segments is controlled by HMISC2
0
0b
RW/O
HMBOUND Lock (HMBOUND_LOCK): When this bit is set, the HMBOUND register is
locked and can no longer be modified until Host Bridge is reset
Extended Configuration Space (HECREG)—Offset 9h
Access Method
Intel® Quark™ SoC X1000
Datasheet
148
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Type: Message Bus Register
(Size: 32 bits)
HECREG: [Port: 0x03] + 9h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
Bit
Range
Default &
Access
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
000000h
RO
27:1
Description
Reserved (RSV11): Reserved.
Extended Configuration Space Enable (EC_ENABLE): When set, causes the
EC_Base range to be compared to incoming memory accesses. If bits [31:28] of the
memory access match the EC_Base value then a posted memory access is treated as a
non-posted configuration access.
0b
RW
0
0
Extended Configuration Space Base Address (EC_BASE): This field describes the
upper 4-bits of the 32-bit address range used to access the memory-mapped
configuration space. This field must not be set to 0xF
0000b
RW
31:28
12.7.2.5
0
8
RSV11
EC_BASE
0
28
EC_ENABLE
31
Miscellaneous Legacy Signal Enables (HLEGACY)—Offset Ah
Access Method
Type: Message Bus Register
(Size: 32 bits)
HLEGACY: [Port: 0x03] + Ah
Op Codes:
10h - Read, 11h - Write
Default: 00008000h
0
0
0
0
0
0
20
0
0
0
0
16
0
12.7.2.6
Bit
Range
Default &
Access
31: 13
0b
RO
12
0b
RW/SE
11: 0
0b
RO
0
0
0
12
1
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV
0
24
RSV
0
28
SMI
31
Description
Reserved: Reserved.
SMI Pin Value (SMI): Reflects the value of the SMI pin set via message 0x70. Pin
value can also be set by writes to this register field.
Reserved: Reserved.
Host Bridge Write Flush Control (HWFLUSH)—Offset Ch
Access Method
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
149
Intel® Quark™ SoC X1000—Host Bridge
Type: Message Bus Register
(Size: 32 bits)
HWFLUSH: [Port: 0x03] + Ch
Op Codes:
10h - Read, 11h - Write
Default: 00010000h
0
0
0
0
0
0
0
0
0
16
0
0
0
Bit
Range
0
Default &
Access
0000h
RO
31:17
12.7.2.7
1
12
0
0
8
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
HWM
0
20
RSV17
0
24
RSV18
0
28
ALL_FLUSHED
31
Description
Reserved (RSV18): Reserved.
16
1b
RO
All Entries Flushed (ALL_FLUSHED): Indicates all dirty entries have been flushed
from the Host Bridge to the Memory Manager
15:8
00h
RO
Reserved (RSV17): Reserved.
7:0
00h
RW
High Water Mark (HWM): High Water Mark for Dirty Entries within the Host Bridge.
When this threshold is exceeded, entries are flushed from the Host Bridge to the
Memory Manager. Valid values are 0x00, 0x01 and 0x02
MTRR Capabilities (MTRR_CAP)—Offset 40h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_CAP: [Port: 0x03] + 40h
Op Codes:
10h - Read, 11h - Write
Default: 00000908h
0
0
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:12
Intel® Quark™ SoC X1000
Datasheet
150
00000h
RO
0
0
0
0
8
1
0
0
1
4
0
0
0
0
0
1
0
0
0
VCNT
0
12
FIX
0
16
WC
0
20
RSV20
0
24
RSV21
0
28
SMRR
31
Description
Reserved (RSV21): Reserved.
11
1b
RO
System Management Register Range Supported (SMRR): System Management
Register Range supported if set
10
0b
RO
Write Combining Memory Type Supported (WC): Write Combining memory
supported if set
9
0b
RO
Reserved (RSV20): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.2.8
Default &
Access
Description
8
1b
RO
Fixed Range Registers Supported (FIX): Indicates fixed range registers are
supported if set
7:0
08h
RO
Variable Range Registers Count (VCNT): Indicates the number of variable range
registers implemented in the Host Bridge
MTRR Default Type (MTRR_DEF_TYPE)—Offset 41h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_DEF_TYPE: [Port: 0x03] + 41h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Range
31:12
12.7.2.9
Default &
Access
00000h
RO
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DEF_TYPE
0
16
RSV22
0
20
E
0
24
RSV23
0
28
FE
31
Description
Reserved (RSV23): Reserved.
11
0b
RW
MTRR Enable (E): MTRRs are enabled when set and are disabled when clear and the
UC memory type is applied to all of physical memory. When this flag is set, the FE flag
can disable the fixed range MTRRs. When the flag is clear, the FE flag has no affect.
When the E flag is set, the type specified in the default memory type field is used for
areas of memory not already mapped by either a fixed or variable MTRR.
10
0b
RW
Fixed MTRR Enable (FE): Fixed range MTRRs are enabled when set and are disabled
when clear. When the fixed range MTRRs are enabled, they take priority over the
variable range MTRRs when overlaps in ranges occur. If the fixed range MTRRs are
disabled, the variable range MTRRs can still be used and can map the range ordinarily
covered by the fixed range MTRRs.
9:8
00b
RO
Reserved (RSV22): Reserved.
7:0
00h
RW
Default Memory Type (DEF_TYPE): Indicates the default memory type used for
memory address ranges that do not have a memory type specified for them by an
MTRR. Default value is UC (Uncached)
MTRR Fixed 64KB Range 0x00000 (MTRR_FIX64K_00000)—Offset 42h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX64K_00000: [Port: 0x03] + 42h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
151
Intel® Quark™ SoC X1000—Host Bridge
0
0
0
0
0
0
0
0
Bit
Range
12.7.2.10
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX64K_00000
0
20
FIX64K_10000
0
24
FIX64K_30000
0
28
FIX64K_20000
31
Default &
Access
Description
31:24
00h
RW
Fixed 64KB Range 0x30000 (FIX64K_30000): Maps the 64KB range from 0x30000
to 0x3FFFF
23:16
00h
RW
Fixed 64KB Range 0x20000 (FIX64K_20000): Maps the 64KB range from 0x20000
to 0x2FFFF
15:8
00h
RW
Fixed 64KB Range 0x10000 (FIX64K_10000): Maps the 64KB range from 0x10000
to 0x1FFFF
7:0
00h
RW
Fixed 64KB Range 0x00000 (FIX64K_00000): Maps the 64KB range from 0x00000
to 0x0FFFF
MTRR Fixed 64KB Range 0x40000 (MTRR_FIX64K_40000)—Offset 43h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX64K_40000: [Port: 0x03] + 43h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
24
0
0
0
Bit
Range
12.7.2.11
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX64K_40000
0
FIX64K_50000
28
0
FIX64K_70000
0
FIX64K_60000
31
Default &
Access
Description
31:24
00h
RW
Fixed 64KB Range 0x70000 (FIX64K_70000): Maps the 64KB range from 0x70000
to 0x7FFFF
23:16
00h
RW
Fixed 64KB Range 0x60000 (FIX64K_60000): Maps the 64KB range from 0x60000
to 0x6FFFF
15:8
00h
RW
Fixed 64KB Range 0x50000 (FIX64K_50000): Maps the 64KB range from 0x50000
to 0x5FFFF
7:0
00h
RW
Fixed 64KB Range 0x40000 (FIX64K_40000): Maps the 64KB range from 0x40000
to 0x4FFFF
MTRR Fixed 16KB Range 0x80000 (MTRR_FIX16K_80000)—Offset 44h
Access Method
Intel® Quark™ SoC X1000
Datasheet
152
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX16K_80000: [Port: 0x03] + 44h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
Bit
Range
12.7.2.12
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX16K_80000
0
20
FIX16K_84000
0
24
FIX16K_8C000
0
28
FIX16K_88000
31
Default &
Access
Description
31:24
00h
RW
Fixed 16KB Range 0x8C000 (FIX16K_8C000): Maps the 16KB range from 0x8C000
to 0x8FFFF
23:16
00h
RW
Fixed 16KB Range 0x88000 (FIX16K_88000): Maps the 16KB range from 0x88000
to 0x8BFFF
15:8
00h
RW
Fixed 16KB Range 0x84000 (FIX16K_84000): Maps the 16KB range from 0x84000
to 0x87FFF
7:0
00h
RW
Fixed 16KB Range 0x80000 (FIX16K_80000): Maps the 16KB range from 0x80000
to 0x83FFF
MTRR Fixed 16KB Range 0x90000 (MTRR_FIX16K_90000)—Offset 45h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX16K_90000: [Port: 0x03] + 45h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
Bit
Range
20
0
0
0
0
FIX16K_98000
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX16K_90000
28
0
FIX16K_9C000
0
FIX16K_94000
31
Default &
Access
Description
31:24
00h
RW
Fixed 16KB Range 0x9C000 (FIX16K_9C000): Maps the 16KB range from 0x9C000
to 0x9FFFF
23:16
00h
RW
Fixed 16KB Range 0x98000 (FIX16K_98000): Maps the 16KB range from 0x98000
to 0x9BFFF
15:8
00h
RW
Fixed 16KB Range 0x94000 (FIX16K_94000): Maps the 16KB range from 0x94000
to 0x97FFF
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
153
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
Description
00h
RW
Fixed 16KB Range 0x90000 (FIX16K_90000): Maps the 16KB range from 0x90000
to 0x93FFF
7:0
12.7.2.13
MTRR Fixed 16KB Range 0xA0000 (MTRR_FIX16K_A0000)—Offset
46h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX16K_A0000: [Port: 0x03] + 46h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
Bit
Range
12.7.2.14
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX16K_A0000
0
20
FIX16K_A4000
0
24
FIX16K_AC000
0
28
FIX16K_A8000
31
Default &
Access
Description
31:24
00h
RW
Fixed 16KB Range 0xAC000 (FIX16K_AC000): Maps the 16KB range from 0xAC000
to 0xAFFFF
23:16
00h
RW
Fixed 16KB Range 0xA8000 (FIX16K_A8000): Maps the 16KB range from 0xA8000
to 0xABFFF
15:8
00h
RW
Fixed 16KB Range 0xA4000 (FIX16K_A4000): Maps the 16KB range from 0xA4000
to 0xA7FFF
7:0
00h
RW
Fixed 16KB Range 0xA0000 (FIX16K_A0000): Maps the 16KB range from 0xA0000
to 0xA3FFF
MTRR Fixed 16KB Range 0xB0000 (MTRR_FIX16K_B0000)—Offset
47h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX16K_B0000: [Port: 0x03] + 47h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
Intel® Quark™ SoC X1000
Datasheet
154
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX16K_B0000
0
24
FIX16K_B4000
0
FIX16K_BC000
0
28
FIX16K_B8000
31
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.2.15
Default &
Access
Description
31:24
00h
RW
Fixed 16KB Range 0xBC000 (FIX16K_BC000): Maps the 16KB range from 0xBC000
to 0xBFFFF
23:16
00h
RW
Fixed 16KB Range 0xB8000 (FIX16K_B8000): Maps the 16KB range from 0xB8000
to 0xBBFFF
15:8
00h
RW
Fixed 16KB Range 0xB4000 (FIX16K_B4000): Maps the 16KB range from 0xB4000
to 0xB7FFF
7:0
00h
RW
Fixed 16KB Range 0xB0000 (FIX16K_B0000): Maps the 16KB range from 0xB0000
to 0xB3FFF
MTRR Fixed 4KB Range 0xC0000 (MTRR_FIX4K_C0000)—Offset 48h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_C0000: [Port: 0x03] + 48h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
Bit
Range
12.7.2.16
0
0
0
Default &
Access
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_C0000
0
20
FIX4K_C1000
0
24
FIX4K_C3000
0
28
FIX4K_C2000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xC3000 (FIX4K_C3000): Maps the 4KB range from 0xC3000 to
0xC3FFF
23:16
00h
RW
Fixed 4KB Range 0xC2000 (FIX4K_C2000): Maps the 4KB range from 0xC2000 to
0xC2FFF
15:8
00h
RW
Fixed 4KB Range 0xC1000 (FIX4K_C1000): Maps the 4KB range from 0xC1000 to
0xC1FFF
7:0
00h
RW
Fixed 4KB Range 0xC0000 (FIX4K_C0000): Maps the 4KB range from 0xC0000 to
0xC0FFF
MTRR Fixed 4KB Range 0xC4000 (MTRR_FIX4K_C4000)—Offset 49h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_C4000: [Port: 0x03] + 49h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
155
Intel® Quark™ SoC X1000—Host Bridge
0
0
0
0
0
0
0
0
Bit
Range
12.7.2.17
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
Default &
Access
0
0
0
0
0
0
FIX4K_C4000
0
20
FIX4K_C5000
0
24
FIX4K_C7000
0
28
FIX4K_C6000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xC7000 (FIX4K_C7000): Maps the 4KB range from 0xC7000 to
0xC7FFF
23:16
00h
RW
Fixed 4KB Range 0xC6000 (FIX4K_C6000): Maps the 4KB range from 0xC6000 to
0xC6FFF
15:8
00h
RW
Fixed 4KB Range 0xC5000 (FIX4K_C5000): Maps the 4KB range from 0xC5000 to
0xC5FFF
7:0
00h
RW
Fixed 4KB Range 0xC4000 (FIX4K_C4000): Maps the 4KB range from 0xC4000 to
0xC4FFF
MTRR Fixed 4KB Range 0xC8000 (MTRR_FIX4K_C8000)—Offset 4Ah
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_C8000: [Port: 0x03] + 4Ah
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
Bit
Range
12.7.2.18
20
0
0
0
0
FIX4K_CA000
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_C8000
28
0
FIX4K_CB000
0
FIX4K_C9000
31
Default &
Access
Description
31:24
00h
RW
Fixed 4KB Range 0xCB000 (FIX4K_CB000): Maps the 4KB range from 0xCB000 to
0xCBFFF
23:16
00h
RW
Fixed 4KB Range 0xCA000 (FIX4K_CA000): Maps the 4KB range from 0xCA000 to
0xCAFFF
15:8
00h
RW
Fixed 4KB Range 0xC9000 (FIX4K_C9000): Maps the 4KB range from 0xC9000 to
0xC9FFF
7:0
00h
RW
Fixed 4KB Range 0xC8000 (FIX4K_C8000): Maps the 4KB range from 0xC8000 to
0xC8FFF
MTRR Fixed 4KB Range 0xCC000 (MTRR_FIX4K_CC000)—Offset 4Bh
Access Method
Intel® Quark™ SoC X1000
Datasheet
156
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_CC000: [Port: 0x03] + 4Bh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
Bit
Range
12.7.2.19
0
0
0
0
12
0
0
0
FIX4K_CE000
0
16
0
8
0
0
0
0
4
0
0
0
Default &
Access
0
0
0
0
0
0
FIX4K_CC000
0
24
FIX4K_CF000
0
28
FIX4K_CD000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xCF000 (FIX4K_CF000): Maps the 4KB range from 0xCF000 to
0xCFFFF
23:16
00h
RW
Fixed 4KB Range 0xCE000 (FIX4K_CE000): Maps the 4KB range from 0xCE000 to
0xCEFFF
15:8
00h
RW
Fixed 4KB Range 0xCD000 (FIX4K_CD000): Maps the 4KB range from 0xCD000 to
0xCDFFF
7:0
00h
RW
Fixed 4KB Range 0xCC000 (FIX4K_CC000): Maps the 4KB range from 0xCC000 to
0xCCFFF
MTRR Fixed 4KB Range 0xD0000 (MTRR_FIX4K_D0000)—Offset 4Ch
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_D0000: [Port: 0x03] + 4Ch
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
Bit
Range
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_D0000
0
20
FIX4K_D1000
0
24
FIX4K_D3000
0
28
FIX4K_D2000
31
Default &
Access
Description
31:24
00h
RW
Fixed 4KB Range 0xD3000 (FIX4K_D3000): Maps the 4KB range from 0xD3000 to
0xD3FFF
23:16
00h
RW
Fixed 4KB Range 0xD2000 (FIX4K_D2000): Maps the 4KB range from 0xD2000 to
0xD2FFF
15:8
00h
RW
Fixed 4KB Range 0xD1000 (FIX4K_D1000): Maps the 4KB range from 0xD1000 to
0xD1FFF
7:0
00h
RW
Fixed 4KB Range 0xD0000 (FIX4K_D0000): Maps the 4KB range from 0xD0000 to
0xD0FFF
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
157
Intel® Quark™ SoC X1000—Host Bridge
12.7.2.20
MTRR Fixed 4KB Range 0xD40000 (MTRR_FIX4K_D4000)—Offset 4Dh
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_D4000: [Port: 0x03] + 4Dh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
Bit
Range
12.7.2.21
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_D4000
0
20
FIX4K_D5000
0
24
FIX4K_D7000
0
28
FIX4K_D6000
31
Default &
Access
Description
31:24
00h
RW
Fixed 4KB Range 0xD7000 (FIX4K_D7000): Maps the 4KB range from 0xD7000 to
0xD7FFF
23:16
00h
RW
Fixed 4KB Range 0xD6000 (FIX4K_D6000): Maps the 4KB range from 0xD6000 to
0xD6FFF
15:8
00h
RW
Fixed 4KB Range 0xD5000 (FIX4K_D5000): Maps the 4KB range from 0xD5000 to
0xD5FFF
7:0
00h
RW
Fixed 4KB Range 0xD4000 (FIX4K_D4000): Maps the 4KB range from 0xD4000 to
0xD4FFF
MTRR Fixed 4KB Range 0xD8000 (MTRR_FIX4K_D8000)—Offset 4Eh
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_D8000: [Port: 0x03] + 4Eh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
Bit
Range
0
0
0
0
FIX4K_DA000
0
20
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_D8000
0
24
FIX4K_DB000
0
28
FIX4K_D9000
31
Default &
Access
Description
31:24
00h
RW
Fixed 4KB Range 0xDB000 (FIX4K_DB000): Maps the 4KB range from 0xDB000 to
0xDBFFF
23:16
00h
RW
Fixed 4KB Range 0xDA000 (FIX4K_DA000): Maps the 4KB range from 0xDA000 to
0xDAFFF
Intel® Quark™ SoC X1000
Datasheet
158
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.2.22
Default &
Access
Description
15:8
00h
RW
Fixed 4KB Range 0xD9000 (FIX4K_D9000): Maps the 4KB range from 0xD9000 to
0xD9FFF
7:0
00h
RW
Fixed 4KB Range 0xD8000 (FIX4K_D8000): Maps the 4KB range from 0xD8000 to
0xD8FFF
MTRR Fixed 4KB Range 0xDC000 (MTRR_FIX4K_DC000)—Offset 4Fh
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_DC000: [Port: 0x03] + 4Fh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
Bit
Range
12.7.2.23
0
0
0
0
12
0
0
0
FIX4K_DE000
0
16
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_DC000
0
24
FIX4K_DF000
0
28
FIX4K_DD000
31
Default &
Access
Description
31:24
00h
RW
Fixed 4KB Range 0xDF000 (FIX4K_DF000): Maps the 4KB range from 0xDF000 to
0xDFFFF
23:16
00h
RW
Fixed 4KB Range 0xDE000 (FIX4K_DE000): Maps the 4KB range from 0xDE000 to
0xDEFFF
15:8
00h
RW
Fixed 4KB Range 0xDD000 (FIX4K_DD000): Maps the 4KB range from 0xDD000 to
0xDDFFF
7:0
00h
RW
Fixed 4KB Range 0xDC000 (FIX4K_DC000): Maps the 4KB range from 0xDC000 to
0xDCFFF
MTRR Fixed 4KB Range 0xE0000 (MTRR_FIX4K_E0000)—Offset 50h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_E0000: [Port: 0x03] + 50h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
November 2014
Document Number: 329676-004US
0
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_E0000
0
20
FIX4K_E1000
0
24
FIX4K_E3000
0
28
FIX4K_E2000
31
Intel® Quark™ SoC X1000
Datasheet
159
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.2.24
Default &
Access
Description
31:24
00h
RW
Fixed 4KB Range 0xE3000 (FIX4K_E3000): Maps the 4KB range from 0xE3000 to
0xE3FFF
23:16
00h
RW
Fixed 4KB Range 0xE2000 (FIX4K_E2000): Maps the 4KB range from 0xE2000 to
0xE2FFF
15:8
00h
RW
Fixed 4KB Range 0xE1000 (FIX4K_E1000): Maps the 4KB range from 0xE1000 to
0xE1FFF
7:0
00h
RW
Fixed 4KB Range 0xE0000 (FIX4K_E0000): Maps the 4KB range from 0xE0000 to
0xE0FFF
MTRR Fixed 4KB Range 0xE4000 (MTRR_FIX4K_E4000)—Offset 51h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_E4000: [Port: 0x03] + 51h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
Bit
Range
12.7.2.25
0
0
0
Default &
Access
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_E4000
0
20
FIX4K_E5000
0
24
FIX4K_E7000
0
28
FIX4K_E6000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xE7000 (FIX4K_E7000): Maps the 4KB range from 0xE7000 to
0xE7FFF
23:16
00h
RW
Fixed 4KB Range 0xE6000 (FIX4K_E6000): Maps the 4KB range from 0xE6000 to
0xE6FFF
15:8
00h
RW
Fixed 4KB Range 0xE5000 (FIX4K_E5000): Maps the 4KB range from 0xE5000 to
0xE5FFF
7:0
00h
RW
Fixed 4KB Range 0xE4000 (FIX4K_E4000): Maps the 4KB range from 0xE4000 to
0xE4FFF
MTRR Fixed 4KB Range 0xE8000 (MTRR_FIX4K_E8000)—Offset 52h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_E8000: [Port: 0x03] + 52h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
160
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
0
0
0
0
0
0
20
0
0
0
Bit
Range
12.7.2.26
0
0
0
0
12
0
0
0
FIX4K_EA000
0
16
0
8
0
0
0
0
4
0
0
0
Default &
Access
0
0
0
0
0
0
FIX4K_E8000
0
24
FIX4K_EB000
0
28
FIX4K_E9000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xEB000 (FIX4K_EB000): Maps the 4KB range from 0xEB000 to
0xEBFFF
23:16
00h
RW
Fixed 4KB Range 0xEA000 (FIX4K_EA000): Maps the 4KB range from 0xEA000 to
0xEAFFF
15:8
00h
RW
Fixed 4KB Range 0xE9000 (FIX4K_E9000): Maps the 4KB range from 0xE9000 to
0xE9FFF
7:0
00h
RW
Fixed 4KB Range 0xE8000 (FIX4K_E8000): Maps the 4KB range from 0xE8000 to
0xE8FFF
MTRR Fixed 4KB Range 0xEC000 (MTRR_FIX4K_EC000)—Offset 53h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_EC000: [Port: 0x03] + 53h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
Bit
Range
12.7.2.27
20
0
0
0
0
FIX4K_EE000
0
Default &
Access
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_EC000
28
0
FIX4K_EF000
0
FIX4K_ED000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xEF000 (FIX4K_EF000): Maps the 4KB range from 0xEF000 to
0xEFFFF
23:16
00h
RW
Fixed 4KB Range 0xEE000 (FIX4K_EE000): Maps the 4KB range from 0xEE000 to
0xEEFFF
15:8
00h
RW
Fixed 4KB Range 0xED000 (FIX4K_ED000): Maps the 4KB range from 0xED000 to
0xEDFFF
7:0
00h
RW
Fixed 4KB Range 0xEC000 (FIX4K_EC000): Maps the 4KB range from 0xEC000 to
0xECFFF
MTRR Fixed 4KB Range 0xF0000 (MTRR_FIX4K_F0000)—Offset 54h
Access Method
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
161
Intel® Quark™ SoC X1000—Host Bridge
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_F0000: [Port: 0x03] + 54h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
Bit
Range
12.7.2.28
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
Default &
Access
0
0
0
0
0
0
FIX4K_F0000
0
20
FIX4K_F1000
0
24
FIX4K_F3000
0
28
FIX4K_F2000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xF3000 (FIX4K_F3000): Maps the 4KB range from 0xF3000 to
0xF3FFF
23:16
00h
RW
Fixed 4KB Range 0xF2000 (FIX4K_F2000): Maps the 4KB range from 0xF2000 to
0xF2FFF
15:8
00h
RW
Fixed 4KB Range 0xF1000 (FIX4K_F1000): Maps the 4KB range from 0xF1000 to
0xF1FFF
7:0
00h
RW
Fixed 4KB Range 0xF0000 (FIX4K_F0000): Maps the 4KB range from 0xF0000 to
0xF0FFF
MTRR Fixed 4KB Range 0xF4000 (MTRR_FIX4K_F4000)—Offset 55h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_F4000: [Port: 0x03] + 55h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
Bit
Range
0
0
0
0
0
Default &
Access
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_F4000
0
20
FIX4K_F5000
0
24
FIX4K_F7000
0
28
FIX4K_F6000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xF7000 (FIX4K_F7000): Maps the 4KB range from 0xF7000 to
0xF7FFF
23:16
00h
RW
Fixed 4KB Range 0xF6000 (FIX4K_F6000): Maps the 4KB range from 0xF6000 to
0xF6FFF
15:8
00h
RW
Fixed 4KB Range 0xF5000 (FIX4K_F5000): Maps the 4KB range from 0xF5000 to
0xF5FFF
7:0
00h
RW
Fixed 4KB Range 0xF4000 (FIX4K_F4000): Maps the 4KB range from 0xF4000 to
0xF4FFF
Intel® Quark™ SoC X1000
Datasheet
162
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.2.29
MTRR Fixed 4KB Range 0xF8000 (MTRR_FIX4K_F8000)—Offset 56h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_F8000: [Port: 0x03] + 56h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
Bit
Range
12.7.2.30
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
Default &
Access
0
0
0
0
0
0
FIX4K_F8000
0
20
FIX4K_F9000
0
24
FIX4K_FB000
0
28
FIX4K_FA000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xFB000 (FIX4K_FB000): Maps the 4KB range from 0xFB000 to
0xFBFFF
23:16
00h
RW
Fixed 4KB Range 0xFA000 (FIX4K_FA000): Maps the 4KB range from 0xFA000 to
0xFAFFF
15:8
00h
RW
Fixed 4KB Range 0xF9000 (FIX4K_F9000): Maps the 4KB range from 0xF9000 to
0xF9FFF
7:0
00h
RW
Fixed 4KB Range 0xF8000 (FIX4K_F8000): Maps the 4KB range from 0xF8000 to
0xF8FFF
MTRR Fixed 4KB Range 0xFC000 (MTRR_FIX4K_FC000)—Offset 57h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_FIX4K_FC000: [Port: 0x03] + 57h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
Bit
Range
0
0
0
0
FIX4K_FE000
0
20
Default &
Access
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FIX4K_FC000
0
24
FIX4K_FF000
0
28
FIX4K_FD000
31
Description
31:24
00h
RW
Fixed 4KB Range 0xFF000 (FIX4K_FF000): Maps the 4KB range from 0xFF000 to
0xFFFFF
23:16
00h
RW
Fixed 4KB Range 0xFE000 (FIX4K_FE000): Maps the 4KB range from 0xFE000 to
0xFEFFF
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
163
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.2.31
Default &
Access
Description
15:8
00h
RW
Fixed 4KB Range 0xFD000 (FIX4K_FD000): Maps the 4KB range from 0xFD000 to
0xFDFFF
7:0
00h
RW
Fixed 4KB Range 0xFC000 (FIX4K_FC000): Maps the 4KB range from 0xFC000 to
0xFCFFF
System Management Range Physical Base
(MTRR_SMRR_PHYSBASE)—Offset 58h
This register may only be written while in SMM. Attempts to write this register outside
of SMM will be ignored.
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_SMRR_PHYSBASE: [Port: 0x03] + 58h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
31:12
11:8
7:0
12.7.2.32
0
0
0
4
0
0
0
0
0
0
0
0
0
SMRR_TYPE
0
24
SMRR_PHYSBASE
0
28
RSV24
31
Default &
Access
Description
00000h
RW
SMRR Physical Base (SMRR_PHYSBASE): Specifies the base address for the System
Management Range. This 20 bit value is extended by 12 bits at the low end to form the
base address
0000b
RO
00h
RW
Reserved (RSV24): Reserved.
SMRR Type (SMRR_TYPE): Specifies the memory type for System Management
Range
System Management Range Physical Mask
(MTRR_SMRR_PHYSMASK)—Offset 59h
This register may only be written while in SMM. Attempts to write this register outside
of SMM will be ignored.
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_SMRR_PHYSMASK: [Port: 0x03] + 59h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
164
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
Bit
Range
Default &
Access
31:12
11
12.7.2.33
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Description
00000h
RW
SMRR Physical Mask (SMRR_PHYSMASK): Specifies a mask value for the System
Management Range. The mask determines the range of the region begin mapped. The
mask value is extended by 12 bits at the low end to form the mask value.
0b
RW
SMRR Valid (SMRR_VALID): Enables the register pair for the System Management
Range when set and disables the register pair when clear.
0000h
RO
10:0
8
RSV25
0
24
SMRR_PHYSMASK
0
28
SMRR_VALID
31
Reserved (RSV25): Reserved.
MTRR Variable Range Physical Base 0 (MTRR_VAR_PHYSBASE0)—
Offset 5Ah
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE0: [Port: 0x03] + 5Ah
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
31:12
11:8
7:0
12.7.2.34
0
0
0
4
0
0
0
RSV26
VAR_PHYSBASE0
0
0
0
0
0
0
0
VAR_TYPE0
31
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE0): Specifies the base address for Variable Range 0.
This 20 bit value is extended by 12 bits at the low end to form the base address
0000b
RO
00h
RW
Reserved (RSV26): Reserved.
Type (VAR_TYPE0): Specifies the memory type for Variable Range 0
MTRR Variable Range Physical Mask 0 (MTRR_VAR_PHYSMASK0)—
Offset 5Bh
Access Method
November 2014
Document Number: 329676-004US
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Datasheet
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Intel® Quark™ SoC X1000—Host Bridge
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK0: [Port: 0x03] + 5Bh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
Bit
Range
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK0): Specifies a mask value for Variable Range 0. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
31:12
0b
RW
11
Valid (VAR_VALID0): Enables the register pair for Variable Range 0 when set and
disables the register pair when clear.
0000h
RO
10:0
12.7.2.35
8
RSV27
0
24
VAR_PHYSMASK0
0
28
VAR_VALID0
31
Reserved (RSV27): Reserved.
MTRR Variable Range Physical Base 1 (MTRR_VAR_PHYSBASE1)—
Offset 5Ch
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE1: [Port: 0x03] + 5Ch
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
31:12
11:8
7:0
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166
0
0
0
4
0
0
0
RSV28
VAR_PHYSBASE1
0
28
0
0
0
0
0
0
VAR_TYPE1
31
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE1): Specifies the base address for Variable Range 1.
This 20 bit value is extended by 12 bits at the low end to form the base address
0000b
RO
00h
RW
Reserved (RSV28): Reserved.
Type (VAR_TYPE1): Specifies the memory type for Variable Range 1
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.2.36
MTRR Variable Range Physical Mask 1 (MTRR_VAR_PHYSMASK1)—
Offset 5Dh
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK1: [Port: 0x03] + 5Dh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
Bit
Range
0
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK1): Specifies a mask value for Variable Range 1. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
31:12
0b
RW
11
Valid (VAR_VALID1): Enables the register pair for Variable Range 1 when set and
disables the register pair when clear.
0000h
RO
10:0
12.7.2.37
8
0
RSV29
28
0
VAR_PHYSMASK1
0
VAR_VALID1
31
Reserved (RSV29): Reserved.
MTRR Variable Range Physical Base 2 (MTRR_VAR_PHYSBASE2)—
Offset 5Eh
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE2: [Port: 0x03] + 5Eh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
31:12
0
RSV30
VAR_PHYSBASE2
0
28
0
0
4
0
0
0
0
0
0
0
0
0
VAR_TYPE2
31
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE2): Specifies the base address for Variable Range 2.
This 20 bit value is extended by 12 bits at the low end to form the base address
November 2014
Document Number: 329676-004US
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Datasheet
167
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
0000b
RO
11:8
12.7.2.38
Reserved (RSV30): Reserved.
00h
RW
7:0
Description
Type (VAR_TYPE2): Specifies the memory type for Variable Range 2
MTRR Variable Range Physical Mask 2 (MTRR_VAR_PHYSMASK2)—
Offset 5Fh
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK2: [Port: 0x03] + 5Fh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:12
11
10:0
12.7.2.39
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV31
0
24
VAR_PHYSMASK2
0
28
VAR_VALID2
31
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK2): Specifies a mask value for Variable Range 2. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
0b
RW
0000h
RO
Valid (VAR_VALID2): Enables the register pair for Variable Range 2 when set and
disables the register pair when clear.
Reserved (RSV31): Reserved.
MTRR Variable Range Physical Base 3 (MTRR_VAR_PHYSBASE3)—
Offset 60h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE3: [Port: 0x03] + 60h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
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0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
0
0
0
0
0
0
0
0
0
0
0
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE3): Specifies the base address for Variable Range 3.
This 20 bit value is extended by 12 bits at the low end to form the base address
31:12
0000b
RO
11:8
Reserved (RSV32): Reserved.
00h
RW
7:0
12.7.2.40
0
4
RSV32
VAR_PHYSBASE3
0
28
VAR_TYPE3
31
Type (VAR_TYPE3): Specifies the memory type for Variable Range 3
MTRR Variable Range Physical Mask 3 (MTRR_VAR_PHYSMASK3)—
Offset 61h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK3: [Port: 0x03] + 61h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:12
11
10:0
12.7.2.41
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV33
0
24
VAR_PHYSMASK3
0
28
VAR_VALID3
31
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK3): Specifies a mask value for Variable Range 3. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
0b
RW
0000h
RO
Valid (VAR_VALID3): Enables the register pair for Variable Range 3 when set and
disables the register pair when clear.
Reserved (RSV33): Reserved.
MTRR Variable Range Physical Base 4 (MTRR_VAR_PHYSBASE4)—
Offset 62h
Access Method
November 2014
Document Number: 329676-004US
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Datasheet
169
Intel® Quark™ SoC X1000—Host Bridge
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE4: [Port: 0x03] + 62h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
0
0
0
0
0
0
0
0
0
0
0
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE4): Specifies the base address for Variable Range 4.
This 20 bit value is extended by 12 bits at the low end to form the base address
31:12
0000b
RO
11:8
Reserved (RSV34): Reserved.
00h
RW
7:0
12.7.2.42
0
4
RSV34
VAR_PHYSBASE4
0
28
VAR_TYPE4
31
Type (VAR_TYPE4): Specifies the memory type for Variable Range 4
MTRR Variable Range Physical Mask 4 (MTRR_VAR_PHYSMASK4)—
Offset 63h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK4: [Port: 0x03] + 63h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:12
11
10:0
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12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV35
0
24
VAR_PHYSMASK4
0
28
VAR_VALID4
31
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK4): Specifies a mask value for Variable Range 4. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
0b
RW
0000h
RO
Valid (VAR_VALID4): Enables the register pair for Variable Range 4 when set and
disables the register pair when clear.
Reserved (RSV35): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.2.43
MTRR Variable Range Physical Base 5 (MTRR_VAR_PHYSBASE5)—
Offset 64h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE5: [Port: 0x03] + 64h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE5): Specifies the base address for Variable Range 5.
This 20 bit value is extended by 12 bits at the low end to form the base address
31:12
0000b
RO
11:8
Reserved (RSV36): Reserved.
00h
RW
7:0
12.7.2.44
0
RSV36
VAR_PHYSBASE5
0
VAR_TYPE5
31
Type (VAR_TYPE5): Specifies the memory type for Variable Range 5
MTRR Variable Range Physical Mask 5 (MTRR_VAR_PHYSMASK5)—
Offset 65h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK5: [Port: 0x03] + 65h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
0
20
0
0
Bit
Range
31:12
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV37
28
0
VAR_PHYSMASK5
0
VAR_VALID5
31
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK5): Specifies a mask value for Variable Range 5. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
November 2014
Document Number: 329676-004US
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Datasheet
171
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
0b
RW
11
12.7.2.45
Valid (VAR_VALID5): Enables the register pair for Variable Range 5 when set and
disables the register pair when clear.
0000h
RO
10:0
Description
Reserved (RSV37): Reserved.
MTRR Variable Range Physical Base 6 (MTRR_VAR_PHYSBASE6)—
Offset 66h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE6: [Port: 0x03] + 66h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
31:12
11:8
7:0
12.7.2.46
0
0
0
4
0
0
0
RSV38
VAR_PHYSBASE6
0
28
0
0
0
0
0
0
VAR_TYPE6
31
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE6): Specifies the base address for Variable Range 6.
This 20 bit value is extended by 12 bits at the low end to form the base address
0000b
RO
00h
RW
Reserved (RSV38): Reserved.
Type (VAR_TYPE6): Specifies the memory type for Variable Range 6
MTRR Variable Range Physical Mask 6 (MTRR_VAR_PHYSMASK6)—
Offset 67h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK6: [Port: 0x03] + 67h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
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Datasheet
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November 2014
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Host Bridge—Intel® Quark™ SoC X1000
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
Bit
Range
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK6): Specifies a mask value for Variable Range 6. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
31:12
0b
RW
11
Valid (VAR_VALID6): Enables the register pair for Variable Range 6 when set and
disables the register pair when clear.
0000h
RO
10:0
12.7.2.47
8
RSV39
0
24
VAR_PHYSMASK6
0
28
VAR_VALID6
31
Reserved (RSV39): Reserved.
MTRR Variable Range Physical Base 7 (MTRR_VAR_PHYSBASE7)—
Offset 68h
Access Method
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSBASE7: [Port: 0x03] + 68h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
31:12
11:8
7:0
12.7.2.48
0
0
0
4
0
0
0
RSV40
VAR_PHYSBASE7
0
28
0
0
0
0
0
0
VAR_TYPE7
31
Default &
Access
Description
00000h
RW
Physical Base (VAR_PHYSBASE7): Specifies the base address for Variable Range 7.
This 20 bit value is extended by 12 bits at the low end to form the base address
0000b
RO
00h
RW
Reserved (RSV40): Reserved.
Type (VAR_TYPE7): Specifies the memory type for Variable Range 7
MTRR Variable Range Physical Mask 7 (MTRR_VAR_PHYSMASK7)—
Offset 69h
Access Method
November 2014
Document Number: 329676-004US
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Datasheet
173
Intel® Quark™ SoC X1000—Host Bridge
Type: Message Bus Register
(Size: 32 bits)
MTRR_VAR_PHYSMASK7: [Port: 0x03] + 69h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
Bit
Range
31:12
11
10:0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Default &
Access
Description
00000h
RW
Physical Mask (VAR_PHYSMASK7): Specifies a mask value for Variable Range 7. The
mask determines the range of the region begin mapped. The mask value is extended by
12 bits at the low end to form the mask value.
0b
RW
0000h
RO
Valid (VAR_VALID7): Enables the register pair for Variable Range 7 when set and
disables the register pair when clear.
Reserved (RSV41): Reserved.
12.7.3
Remote Management Unit (Port 0x04)
Table 75.
Summary of Message Bus Registers—0x04
Offset
Default
Value
Register Name (Register Symbol)
60h
“SPI DMA Count Register (P_CFG_60)—Offset 60h” on page 174
00000000h
61h
“SPI DMA Destination Register (P_CFG_61)—Offset 61h” on page 175
00000000h
62h
“SPI DMA Source Register (P_CFG_62)—Offset 62h” on page 175
00000000h
70h
“Processor Register Block (P_BLK) Base Address (P_CFG_70)—Offset 70h” on page 176
00000000h
71h
“Control Register (P_CFG_71)—Offset 71h” on page 176
00000009h
74h
“Watchdog Control Register (P_CFG_74)—Offset 74h” on page 177
00040000h
B0h
“Thermal Sensor Mode Register (P_CFG_B0)—Offset B0h” on page 178
00000000h
B1h
“Thermal Sensor Temperature Register (P_CFG_B1)—Offset B1h” on page 178
00000000h
B2h
“Thermal Sensor Programmable Trip Point Register (P_CFG_B2)—Offset B2h” on page 179
FFFFFFFFh
12.7.3.1
0
RSV41
0
24
VAR_PHYSMASK7
0
28
VAR_VALID7
31
SPI DMA Count Register (P_CFG_60)—Offset 60h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + 60h
Op Codes:
10h - Read, 11h - Write
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Datasheet
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Host Bridge—Intel® Quark™ SoC X1000
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CFG_SPI_DMA_CNT
0
Bit
Range
Default &
Access
Field Name (ID): Description
0b
RW
SPI DMA Count (CFG_SPI_DMA_CNT): Count of 512 byte block transfers.
Writing this register triggers the start of the transfer of the indicated number of blocks.
Reading this register returns the number of blocks that are remaining to be transferred.
A value of 0 indicates the transfer is complete.
31:0
12.7.3.2
SPI DMA Destination Register (P_CFG_61)—Offset 61h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + 61h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CFG_SPI_DMA_DST
0
28
Bit
Range
31:0
12.7.3.3
Default &
Access
Field Name (ID): Description
00000000h SPI DMA Destination (CFG_SPI_DMA_DST): 32-bit Destination Address of data in
System Memory (eSRAM/DRAM).
RW
SPI DMA Source Register (P_CFG_62)—Offset 62h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + 62h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
November 2014
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Intel® Quark™ SoC X1000—Host Bridge
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CFG_SPI_DMA_SRC
0
28
Bit
Range
31:0
12.7.3.4
Default &
Access
Field Name (ID): Description
00000000h SPI DMA Source (CFG_SPI_DMA_SRC): 32-bit Source Address of data in Legacy
SPI.
RW
Processor Register Block (P_BLK) Base Address (P_CFG_70)—Offset
70h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + 70h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
Bit
Range
12.7.3.5
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
CFG_70_RSV
P_BLK_IO_EN
0
28
Default &
Access
0
0
0
4
0
0
0
0
0
0
0
0
0
P_BLK_IO_BAR
31
Field Name (ID): Description
31
0b
RW
Enable (P_BLK_IO_EN): When set to “1”, decode of the IO range pointed to by the
Base Address is enabled.
30:16
0b
RO
Reserved (CFG_70_RSV): Reserved.
15:0
0b
RW
Base Address (P_BLK_IO_BAR): IO Base Address for the Processor Register Block
(P_BLK) decode range.
Control Register (P_CFG_71)—Offset 71h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + 71h
Op Codes:
10h - Read, 11h - Write
Default: 00000009h
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Datasheet
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November 2014
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Host Bridge—Intel® Quark™ SoC X1000
0
0
0
0
0
0
Bit
Range
12.7.3.6
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
RSVD
0
RSVD
0
RSVD
0
0
RSVD
0
4
RSVD
0
8
RSVD
0
12
LOCK_THRM_CTRL_REGS
0
16
RSVD
0
20
RSVD
0
24
RSVD
0
28
RSVD
31
Field Name (ID): Description
31:16
0b
RO
Reserved (RSVD): Reserved.
15:9
0b
RO
Reserved (RSVD): Reserved.
8
0b
RO
Reserved (RSVD): Reserved.
7
0b
RO
Reserved (RSVD): Reserved.
6
0b
RO
Reserved (RSVD): Reserved.
5
0b
RW/O
4
0b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
0b
RO
Reserved (RSVD): Reserved.
1
0b
RO
Reserved (RSVD): Reserved.
0
1b
RO
Reserved (RSVD): Reserved.
Lock Thermal Control Registers (LOCK_THRM_CTRL_REGS): Setting this bit locks
the thermal control registers (registers 0xB0 and 0xB2).
Watchdog Control Register (P_CFG_74)—Offset 74h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + 74h
Op Codes:
10h - Read, 11h - Write
Default: 00040000h
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Intel® Quark™ SoC X1000—Host Bridge
0
0
0
24
0
0
0
0
20
0
0
0
0
Bit
Range
12.7.3.7
16
0
1
0
0
12
0
0
0
0
8
0
0
DBL_ECC_BIT_ERR
RSVD
0
28
0
0
4
0
0
0
0
0
0
0
0
0
RSVD
31
Default &
Access
Field Name (ID): Description
31:20
0b
RO
Reserved (RSVD): Reserved.
19:18
01b
RW
Double ECC Bit Error (DBL_ECC_BIT_ERR): Double ECC bit error handling selection:
00b: Do nothing
01b: Catastrophic Shutdown
10b: Warm Reset
11b: Send SERR
17:0
0b
RO
Reserved (RSVD): Reserved.
Thermal Sensor Mode Register (P_CFG_B0)—Offset B0h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + B0h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
Bit
Range
31:16
15
14:0
12.7.3.8
Default &
Access
0b
RO
0b
RW/L
0b
RO
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CFG_B0_RSV1
0
24
CFG_B0_RSV2
0
28
THRM_SNSR_EN
31
Field Name (ID): Description
Reserved (CFG_B0_RSV2): Reserved.
Thermal Sensor Enable (THRM_SNSR_EN): Setting to 1 Enables Thermal Sensor
Reserved (CFG_B0_RSV1): Reserved.
Thermal Sensor Temperature Register (P_CFG_B1)—Offset B1h
Access Method
Intel® Quark™ SoC X1000
Datasheet
178
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + B1h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
Bit
Range
0
0
0
0
0
0
0
0
THRM_SENSR_REL_TEMP
0
12
Default &
Access
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:24
0b
RO
Reserved (CFG_B1_RSV2): Reserved.
23:16
0b
RO
Thermal Sensor Relative Temperature (THRM_SENSR_REL_TEMP): The thermal
sensor relative temperature value is an 8-bit signed value relative to the Hot Trip point.
If the Hot Trip point minus the current temperature is greater than +127, this value is
clipped at +127. If the Hot Trip point minus the current temperature is less than -127,
this value is clipped at -127. Otherwise this value is a signed sum magnitude where
bit[23] is the sign and bits[22:16] are the magnitude.
15:8
0b
RO
Reserved (CFG_B1_RSV1): Reserved.
0b
RO
Thermal Sensor Temperature (THRM_SENSR_TEMP): 8-bit Thermal Sensor
Temperature. The temperature in degrees Celsius is calculated by subtracting an offset
of 50 from the 8-bit register value.
The temperature in degrees Celsius corresponds to: 00h: -50
01h: -49
...
FEh: 204
FFh: 205
7:0
12.7.3.9
0
16
THRM_SENSR_TEMP
0
24
CFG_B1_RSV2
0
28
CFG_B1_RSV1
31
Thermal Sensor Programmable Trip Point Register (P_CFG_B2)—
Offset B2h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x04] + B2h
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
November 2014
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179
Intel® Quark™ SoC X1000—Host Bridge
1
1
1
1
1
1
1
1
Bit
Range
1
16
1
1
1
1
12
1
1
1
1
8
1
1
1
1
4
1
1
1
0
1
1
1
1
1
CAT_TRIP_SET_THOLD
1
20
HOT_TRIP_SET_THOLD
1
24
HOT_TRIP_CLEAR_THOLD
1
28
CAT_TRIP_CLEAR_THOLD
31
Default &
Access
Field Name (ID): Description
31:24
FFh
RW/L
Hot Clear Trip Point Threshold (HOT_TRIP_CLEAR_THOLD): Sets the target value
for the hot trip clear point
23:16
FFh
RW/L
Catastrophic Clear Trip Point Threshold (CAT_TRIP_CLEAR_THOLD): Sets the
target value for the catastrophic trip clear point
15:8
FFh
RW/L
Hot Set Trip Point Threshold (HOT_TRIP_SET_THOLD): Sets the target value for
the hot trip set point
7:0
FFh
RW/L
Catastrophic Set Trip Point Threshold (CAT_TRIP_SET_THOLD): Sets the target
value for the catastrophic trip set point
12.7.4
Memory Manager (Port 0x05)
Table 76.
Summary of Message Bus Registers—0x05
Offset
Default
Value
Register ID—Description
1h
“Control (BCTRL)—Offset 1h” on page 181
00000800h
2h
“Write Flush Policy (BWFLUSH)—Offset 2h” on page 182
0C070408h
19h
“Isolated Memory Region Violation Control (BIMRVCTL)—Offset 19h” on page 183
00000000h
31h
“Debug 1 (DEBUG1)—Offset 31h” on page 184
4F08C20Ch
40h
“Isolated Memory Region 0 Low Address (IMR0L)—Offset 40h” on page 186
00000000h
41h
“Isolated Memory Region 0 High Address (IMR0H)—Offset 41h” on page 186
00000000h
42h
“Isolated Memory Region 0 Read Mask (IMR0RM)—Offset 42h” on page 187
BFFFFFFFh
43h
“Isolated Memory Region 0 Write Mask (IMR0WM)—Offset 43h” on page 189
FFFFFFFFh
44h
“Isolated Memory Region 1 Low Address (IMR1L)—Offset 44h” on page 190
00000000h
45h
“Isolated Memory Region 1 High Address (IMR1H)—Offset 45h” on page 191
00000000h
46h
“Isolated Memory Region 1 Read Mask (IMR1RM)—Offset 46h” on page 191
BFFFFFFFh
47h
“Isolated Memory Region 1 Write Mask (IMR1WM)—Offset 47h” on page 193
FFFFFFFFh
48h
“Isolated Memory Region 2 Low Address (IMR2L)—Offset 48h” on page 195
00000000h
49h
“Isolated Memory Region 2 High Address (IMR2H)—Offset 49h” on page 196
00000000h
4Ah
“Isolated Memory Region 2 Read Mask (IMR2RM)—Offset 4Ah” on page 196
BFFFFFFFh
4Bh
“Isolated Memory Region 2 Write Mask (IMR2WM)—Offset 4Bh” on page 198
FFFFFFFFh
4Ch
“Isolated Memory Region 3 Low Address (IMR3L)—Offset 4Ch” on page 200
00000000h
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Datasheet
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November 2014
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Host Bridge—Intel® Quark™ SoC X1000
Table 76.
Summary of Message Bus Registers—0x05 (Continued)
Offset
Default
Value
Register ID—Description
4Dh
“Isolated Memory Region 3 High Address (IMR3H)—Offset 4Dh” on page 200
00000000h
4Eh
“Isolated Memory Region 3 Read Mask (IMR3RM)—Offset 4Eh” on page 201
BFFFFFFFh
4Fh
“Isolated Memory Region 3 Write Mask (IMR3WM)—Offset 4Fh” on page 203
FFFFFFFFh
50h
“Isolated Memory Region 4 Low Address (IMR4L)—Offset 50h” on page 204
00000000h
51h
“Isolated Memory Region 4 High Address (IMR4H)—Offset 51h” on page 205
00000000h
52h
“Isolated Memory Region 4 Read Mask (IMR4RM)—Offset 52h” on page 205
BFFFFFFFh
53h
“Isolated Memory Region 4 Write Mask (IMR4WM)—Offset 53h” on page 207
FFFFFFFFh
54h
“Isolated Memory Region 5 Low Address (IMR5L)—Offset 54h” on page 209
00000000h
55h
“Isolated Memory Region 5 High Address (IMR5H)—Offset 55h” on page 210
00000000h
56h
“Isolated Memory Region 5 Read Mask (IMR5RM)—Offset 56h” on page 210
BFFFFFFFh
57h
“Isolated Memory Region 5 Write Mask (IMR5WM)—Offset 57h” on page 212
FFFFFFFFh
58h
“Isolated Memory Region 6 Low Address (IMR6L)—Offset 58h” on page 214
00000000h
59h
“Isolated Memory Region 6 High Address (IMR6H)—Offset 59h” on page 214
00000000h
5Ah
“Isolated Memory Region 6 Read Mask (IMR6RM)—Offset 5Ah” on page 215
BFFFFFFFh
5Bh
“Isolated Memory Region 6 Write Mask (IMR6WM)—Offset 5Bh” on page 217
FFFFFFFFh
5Ch
“Isolated Memory Region 7 Low Address (IMR7L)—Offset 5Ch” on page 218
00000000h
5Dh
“Isolated Memory Region 7 High Address (IMR7H)—Offset 5Dh” on page 219
00000000h
5Eh
“Isolated Memory Region 7 Read Mask (IMR7RM)—Offset 5Eh” on page 219
BFFFFFFFh
5Fh
“Isolated Memory Region 7 Write Mask (IMR7WM)—Offset 5Fh” on page 221
FFFFFFFFh
81h
“eSRAM Control (ESRAMCTRL)—Offset 81h” on page 223
047F3F91h
82h
“eSRAM Block Page Control (ESRAMPGCTRL_BLOCK)—Offset 82h” on page 224
850000FFh
83h
“eSRAM Correctable Error (ESRAMCERR)—Offset 83h” on page 226
00000000h
84h
“eSRAM Uncorrectable Error (ESRAMUERR)—Offset 84h” on page 226
00000000h
88h
“eSRAM ECC Error Syndrome (ESRAMSDROME)—Offset 88h” on page 227
00000000h
12.7.4.1
Control (BCTRL)—Offset 1h
Access Method
Type: Message Bus Register
(Size: 32 bits)
BCTRL: [Port: 0x05] + 1h
Op Codes:
10h - Read, 11h - Write
Default: 00000800h
November 2014
Document Number: 329676-004US
16
0
0
0
0
12
0
0
0
8
0
1
0
4
0
0
0
0
0
0
0
0
0
0
0
RSVD
0
RSVD
0
RSVD
0
RSVD
20
0
RSVD
0
RSV0
0
RSVD
0
RSV1
24
0
MissValidEntries
0
RSVD
0
RSVD
28
0
RSV2
0
RSVD
31
Intel® Quark™ SoC X1000
Datasheet
181
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
0000h
RO
Reserved (RSV2): Reserved.
12
0b
RO
Reserved (RSVD): Reserved.
11
1b
RO
Reserved (RSVD): Reserved.
10
0b
RO
Reserved (RSVD): Reserved.
9
0b
RO
Reserved (RSV1): Reserved.
8
0b
RW
Miss Valid Entries (MissValidEntries): This mode causes reads to clean valid
Memory Manager buffer entries that have zero reference counts so that they look like
misses instead of hits. It is mostly present for test purposes,
7
0b
RO
Reserved (RSVD): Reserved.
6:5
0h
RO
Reserved (RSV0): Reserved.
4
0b
RO
Reserved (RSVD): Reserved.
3
0b
RO
Reserved (RSVD): Reserved.
2
0b
RO
Reserved (RSVD): Reserved.
1
0b
RO
Reserved (RSVD): Reserved.
0
0b
RO
Reserved (RSVD): Reserved.
31:13
12.7.4.2
Description
Write Flush Policy (BWFLUSH)—Offset 2h
Access Method
Type: Message Bus Register
(Size: 32 bits)
BWFLUSH: [Port: 0x05] + 2h
Op Codes:
10h - Read, 11h - Write
Default: 0C070408h
Intel® Quark™ SoC X1000
Datasheet
182
0
0
0
0
0
1
1
1
0
0
0
0
8
0
1
0
0
4
0
0
0
0
0
1
0
0
0
dram_dirty_hwm
0
12
dram_dirty_lwm
0
DRAMAllEntriesIdle
1
16
DRAMAllEntriesFlushed
1
20
esram_dirty_hwm
0
esram_dirty_lwm
0
24
ESRAMAllEntriesIdle
0
RSV0
0
28
ESRAMAllEntriesFlushed
31
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.4.3
Default &
Access
Description
31:28
0h
RO
Reserved (RSV0): Reserved.
27
1b
RO
eSRAM All Entries Idle (ESRAMAllEntriesIdle): All entries in the Memory Manager
eCACHE tag store have 0 reference counts and are unlocked, indicating that there are
no transactions in progress in this cache
26
1b
RO
eSRAM All Entries Flushed (ESRAMAllEntriesFlushed): All entries in the Memory
Manager eCACHE have been flushed to the eSRAM
25:22
00h
RW
eSRAM Low Water Mark (esram_dirty_lwm): Low Water Mark for Dirty Entries
retained by eCACHE in the Memory Manager
21:18
01h
RW
eSRAM High Water Mark (esram_dirty_hwm): High Water Mark for Dirty Entries
retained by eCACHE in the Memory Manager
17
1b
RO
DRAM All Entries Idle (DRAMAllEntriesIdle): All entries in the Memory Manager
DCACHE entries have 0 reference counts and are unlocked, indicating that the Memory
Manager has no DRAM transactions in progress
16
1b
RO
DRAM All Entries Flushed (DRAMAllEntriesFlushed): All entries in the Memory
Manager DCACHE have been flushed
15:8
04h
RW
DRAM Low Water Mark (dram_dirty_lwm): Low water mark for dirty entries
retained by the Memory Manager
7:0
08h
RW
DRAM High Water Mark (dram_dirty_hwm): High water mark for dirty entries
retained by the Memory Manager
Isolated Memory Region Violation Control (BIMRVCTL)—Offset 19h
This register is used to configure the interrupt and to capture status when an IMR is
violated. Note that the Enable Interrupt on IMR Violation field is reset on an IMR
violation event and this register captures the first violation only. It can be set back to 1,
and if a new violation occurs any status previously captured is overridden with the new
violation details. This register is not secured or locked because the violation interrupt is
not part of securing the region and is only intended to help in debugging IMR
configuration.
Access Method
Type: Message Bus Register
(Size: 32 bits)
BIMRVCTL: [Port: 0x05] + 19h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
November 2014
Document Number: 329676-004US
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
IMRViolationSubAgent
0
12
RSV0
0
16
IMRViolationAgent
0
20
RSV1
0
24
IMRViolationRegion
0
RSV2
28
EnableIMRInt
31
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Datasheet
183
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.4.4
Default &
Access
Description
31
0b
RW
Enable Interrupt on IMR Violation (EnableIMRInt): When set, the Memory
Manager will latch violation information into this register and send an interrupt request
to the Remote Management Unit. This bit is cleared upon triggering and must be reset
by software in order to trigger again. Memory protection is maintained even while the
interrupt/capture mechanism is disabled
30
0b
RO
Reserved (RSV2): Reserved.
IMR Violation Region (IMRViolationRegion): This 14-bit value indicates which
region the last IMR violation occurred on if the IMR interrupt is enabled. A bit of this field
will be asserted for every IMR region, HMBOUND or SMM region violated by the
transaction that caused EnableIMRInt to deassert.
[29]: HMBOUND Violation
[28]: SMM Bound Violation
[27:24]: Reserved
[23]: IMR7 Violation
[22]: IMR6 Violation
[21]: IMR5 Violation
[20]: IMR4 Violation
[19]: IMR3 Violation
[18]: IMR2 Violation
[17]: IMR1 Violation
[16]: IMR0 Violation
29:16
0000h
RO
15:12
0h
RO
Reserved (RSV1): Reserved.
11:8
0h
RO
IMR Violation Agent (IMRViolationAgent): This 4-bit value indicates which agent
caused the last IMR violation if the IMR interrupt is enabled:
0000b : CPU
0001b : Host Bridge Arbiter VC0
0010b : Host Bridge Arbiter VC1
0011b : Reserved
0100b : Reserved
0101b : Reserved
0110b : Reserved
0111b : eSRAM Flush/Init
1000b : Remote Management Unit
7:3
00h
RO
Reserved (RSV0): Reserved.
2:0
0h
RO
IMR Violation Sub Agent (IMRViolationSubAgent): This 3-bit value indicates which
sub-agent caused the last IMR violation, if the IMR interrupt is enabled
000b : Host Bridge Arbiter Sub-Channel 0 (Anonymous)
001b : Host Bridge Arbiter Sub-Channel 1
010b : Host Bridge Arbiter Sub-Channel 2
100b : Host Bridge Arbiter Sub-Channel 3
Debug 1 (DEBUG1)—Offset 31h
Access Method
Type: Message Bus Register
(Size: 32 bits)
DEBUG1: [Port: 0x05] + 31h
Op Codes:
10h - Read, 11h - Write
Default: 4F08C20Ch
Intel® Quark™ SoC X1000
Datasheet
184
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
1
0
0
Default &
Access
0
0
1
0
0
0
0
0
1
1
0
0
RSVD
1
RSVD
0
RSVD
0
0
EnDCACHEPartFill
0
4
RSVD
1
8
RSVD
0
RSVD
0
RSVD
0
RSVD
0
RSVD
1
RSVD
1
RSVD
1
12
RSVD
RSVD
Bit
Range
1
16
RSVD
0
20
RSVD
0
24
RSVD
1
RSVD
RSVD
0
28
RSVD
31
Description
31
0b
RO
Reserved (RSVD): Reserved.
30
1b
RO
Reserved (RSVD): Reserved.
29
0b
RO
Reserved (RSVD): Reserved.
28
0h
RO
Reserved (RSVD): Reserved.
27:24
Fh
RO
Reserved (RSVD): Reserved.
23:20
0h
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
0b
RO
Reserved (RSVD): Reserved.
17
0b
RO
Reserved (RSVD): Reserved.
16
0b
RO
Reserved (RSVD): Reserved.
15
1b
RO
Reserved (RSVD): Reserved.
14
1b
RO
Reserved (RSVD): Reserved.
13
0h
RO
Reserved (RSVD): Reserved.
12
0h
RO
Reserved (RSVD): Reserved.
11:8
2h
RO
Reserved (RSVD): Reserved.
7:4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RW
Enable DCACHE Partial Entries (EnDCACHEPartFill): If the Memory Manager
admitted Request or CPU Snoop Response that has not all Byte Enables set the Entry is
considered Partial. Setting this bit will cause the Memory Manager to fill the partial entry
from DRAM, before it is being flushed to DRAM. This bit needs to be set if the Memory
Controller enables ECC mode, where partial writes are forbidden
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
185
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.4.5
Default &
Access
Description
1
0b
RO
Reserved (RSVD): Reserved.
0
0b
RO
Reserved (RSVD): Reserved.
Isolated Memory Region 0 Low Address (IMR0L)—Offset 40h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR0L: [Port: 0x05] + 40h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
24
0
Bit
Range
0
0
0
0
0
0
0
0
0
0
12
0
Default &
Access
0b
RW/O
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
00h
RO
1:0
0
4
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
0
8
IMR Lock (IMR_LOCK): Setting this bit to “1” locks the IMRX registers, preventing
further updates.
00h
RO
30:24
12.7.4.6
0
16
RSV1
0
20
RSV0
0
IMR_LOCK
0
28
IMRL
31
Reserved (RSV0): Reserved.
Isolated Memory Region 0 High Address (IMR0H)—Offset 41h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR0H: [Port: 0x05] + 41h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
Intel® Quark™ SoC X1000
Datasheet
186
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV0
0
RSV1
0
28
IMRH
31
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
00h
RO
31:24
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
0h
RO
1:0
12.7.4.7
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
Description
Reserved (RSV0): Reserved.
Isolated Memory Region 0 Read Mask (IMR0RM)—Offset 42h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR0RM: [Port: 0x05] + 42h
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
0
RSVD
16
RSVD
20
RSVD
24
RSVD
ESRAM_FLUSH_INIT
1
28
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
Intel® Quark™ SoC X1000
Datasheet
187
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
188
Default &
Access
Description
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.4.8
Isolated Memory Region 0 Write Mask (IMR0WM)—Offset 43h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR0WM: [Port: 0x05] + 43h
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
RSVD
24
PUNIT
ESRAM_FLUSH_INIT
1
28
CPU_SNOOP
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
189
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.4.9
Default &
Access
Description
16
1b
RO
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Reserved (RSVD): Reserved.
Isolated Memory Region 1 Low Address (IMR1L)—Offset 44h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR1L: [Port: 0x05] + 44h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
190
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
0
24
0
0
Bit
Range
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0b
RW/O
0
0
0
0
0
0
0
0
0
0
0
Description
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
00h
RO
1:0
0
0
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
0
4
IMR Lock (IMR_LOCK): Setting this bit to “1” locks the IMRX registers, preventing
further updates.
00h
RO
30:24
0
8
IMRL
Default &
Access
31
12.7.4.10
0
20
RSV1
0
IMR_LOCK
0
28
RSV0
31
Reserved (RSV0): Reserved.
Isolated Memory Region 1 High Address (IMR1H)—Offset 45h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR1H: [Port: 0x05] + 45h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:24
23:2
1:0
12.7.4.11
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
IMRH
RSV1
0
28
Default &
Access
00h
RO
000000h
RW/L
0h
RO
0
0
0
0
0
RSV0
31
Description
Reserved (RSV1): Reserved.
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
Reserved (RSV0): Reserved.
Isolated Memory Region 1 Read Mask (IMR1RM)—Offset 46h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR1RM: [Port: 0x05] + 46h
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
191
Intel® Quark™ SoC X1000—Host Bridge
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
Intel® Quark™ SoC X1000
Datasheet
192
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
0
VC0_SAI_ID0
1
4
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
VC1_SAI_ID1
1
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
0
RSVD
16
RSVD
20
RSVD
24
RSVD
ESRAM_FLUSH_INIT
1
28
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.4.12
Default &
Access
Description
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Isolated Memory Region 1 Write Mask (IMR1WM)—Offset 47h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR1WM: [Port: 0x05] + 47h
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
November 2014
Document Number: 329676-004US
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
PUNIT
24
CPU_SNOOP
28
ESRAM_FLUSH_INIT
31
Intel® Quark™ SoC X1000
Datasheet
193
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
194
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.4.13
Default &
Access
Description
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Isolated Memory Region 2 Low Address (IMR2L)—Offset 48h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR2L: [Port: 0x05] + 48h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31
30:24
23:2
1:0
12
0
0
0
0
8
0
IMRL
RSV1
0
IMR_LOCK
0
28
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV0
31
Default &
Access
Description
0b
RW/O
IMR Lock (IMR_LOCK): This bit locks the IMRX registers, preventing further updates
00h
RO
000000h
RW/L
00h
RO
November 2014
Document Number: 329676-004US
Reserved (RSV1): Reserved.
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
Reserved (RSV0): Reserved.
Intel® Quark™ SoC X1000
Datasheet
195
Intel® Quark™ SoC X1000—Host Bridge
12.7.4.14
Isolated Memory Region 2 High Address (IMR2H)—Offset 49h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR2H: [Port: 0x05] + 49h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
Bit
Range
Default &
Access
00h
RO
31:24
12.7.4.15
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
0h
RO
1:0
0
4
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
0
8
RSV0
0
24
RSV1
0
28
IMRH
31
Reserved (RSV0): Reserved.
Isolated Memory Region 2 Read Mask (IMR2RM)—Offset 4Ah
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR2RM: [Port: 0x05] + 4Ah
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
RSVD
4
0
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
1
RSVD
RSVD
1
RSVD
RSVD
1
RSVD
RSVD
Intel® Quark™ SoC X1000
Datasheet
196
8
1
RSVD
RSVD
Bit
Range
12
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
VC1_SAI_ID1
1
VC1_SAI_ID2
1
RSVD
1
VC1_SAI_ID3
1
RSVD
16
1
RSVD
20
1
RSVD
24
1
RSVD
28
0
RSVD
ESRAM_FLUSH_INIT
1
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
197
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.4.16
Default &
Access
Description
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Isolated Memory Region 2 Write Mask (IMR2WM)—Offset 4Bh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR2WM: [Port: 0x05] + 4Bh
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
Default &
Access
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
Intel® Quark™ SoC X1000
Datasheet
198
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
0
VC0_SAI_ID0
1
4
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
VC1_SAI_ID1
1
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
RSVD
24
PUNIT
ESRAM_FLUSH_INIT
1
28
CPU_SNOOP
31
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
November 2014
Document Number: 329676-004US
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Intel® Quark™ SoC X1000
Datasheet
199
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
12.7.4.17
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
1b
RW/L
0
Description
Isolated Memory Region 3 Low Address (IMR3L)—Offset 4Ch
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR3L: [Port: 0x05] + 4Ch
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
24
0
Bit
Range
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Description
0b
RW/O
IMR Lock (IMR_LOCK): This bit locks the IMRX registers, preventing further updates
31
00h
RO
30:24
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
00h
RO
1:0
12.7.4.18
0
16
RSV1
0
20
RSV0
0
IMR_LOCK
0
28
IMRL
31
Reserved (RSV0): Reserved.
Isolated Memory Region 3 High Address (IMR3H)—Offset 4Dh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR3H: [Port: 0x05] + 4Dh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:24
Intel® Quark™ SoC X1000
Datasheet
200
12
0
0
0
0
8
0
IMRH
RSV1
0
28
Default &
Access
00h
RO
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV0
31
Description
Reserved (RSV1): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
000000h
RW/L
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
23:2
0h
RO
1:0
12.7.4.19
Reserved (RSV0): Reserved.
Isolated Memory Region 3 Read Mask (IMR3RM)—Offset 4Eh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR3RM: [Port: 0x05] + 4Eh
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
0
RSVD
16
RSVD
20
RSVD
24
RSVD
ESRAM_FLUSH_INIT
1
28
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
Intel® Quark™ SoC X1000
Datasheet
201
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
202
Default &
Access
Description
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.4.20
Isolated Memory Region 3 Write Mask (IMR3WM)—Offset 4Fh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR3WM: [Port: 0x05] + 4Fh
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
RSVD
24
PUNIT
ESRAM_FLUSH_INIT
1
28
CPU_SNOOP
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
203
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.4.21
Default &
Access
Description
16
1b
RO
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Reserved (RSVD): Reserved.
Isolated Memory Region 4 Low Address (IMR4L)—Offset 50h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR4L: [Port: 0x05] + 50h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
204
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
0
24
0
0
Bit
Range
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
IMRL
0
8
0
0
Default &
Access
Description
0b
RW/O
IMR Lock (IMR_LOCK): This bit locks the IMRX registers, preventing further updates
31
00h
RO
30:24
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
00h
RO
1:0
12.7.4.22
0
20
RSV1
0
IMR_LOCK
0
28
RSV0
31
Reserved (RSV0): Reserved.
Isolated Memory Region 4 High Address (IMR4H)—Offset 51h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR4H: [Port: 0x05] + 51h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:24
23:2
1:0
12.7.4.23
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
IMRH
RSV1
0
28
Default &
Access
00h
RO
000000h
RW/L
0h
RO
0
0
0
0
0
RSV0
31
Description
Reserved (RSV1): Reserved.
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
Reserved (RSV0): Reserved.
Isolated Memory Region 4 Read Mask (IMR4RM)—Offset 52h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR4RM: [Port: 0x05] + 52h
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
205
Intel® Quark™ SoC X1000—Host Bridge
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
Intel® Quark™ SoC X1000
Datasheet
206
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
0
VC0_SAI_ID0
1
4
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
VC1_SAI_ID1
1
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
0
RSVD
16
RSVD
20
RSVD
24
RSVD
ESRAM_FLUSH_INIT
1
28
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.4.24
Default &
Access
Description
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Isolated Memory Region 4 Write Mask (IMR4WM)—Offset 53h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR4WM: [Port: 0x05] + 53h
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
November 2014
Document Number: 329676-004US
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
PUNIT
24
CPU_SNOOP
28
ESRAM_FLUSH_INIT
31
Intel® Quark™ SoC X1000
Datasheet
207
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
208
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.4.25
Default &
Access
Description
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Isolated Memory Region 5 Low Address (IMR5L)—Offset 54h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR5L: [Port: 0x05] + 54h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31
30:24
23:2
1:0
12
0
0
0
0
8
0
IMRL
RSV1
0
IMR_LOCK
0
28
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV0
31
Default &
Access
Description
0b
RW/O
IMR Lock (IMR_LOCK): This bit locks the IMRX registers, preventing further updates
00h
RO
000000h
RW/L
00h
RO
November 2014
Document Number: 329676-004US
Reserved (RSV1): Reserved.
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
Reserved (RSV0): Reserved.
Intel® Quark™ SoC X1000
Datasheet
209
Intel® Quark™ SoC X1000—Host Bridge
12.7.4.26
Isolated Memory Region 5 High Address (IMR5H)—Offset 55h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR5H: [Port: 0x05] + 55h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
Bit
Range
Default &
Access
00h
RO
31:24
12.7.4.27
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
0h
RO
1:0
0
4
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
0
8
RSV0
0
24
RSV1
0
28
IMRH
31
Reserved (RSV0): Reserved.
Isolated Memory Region 5 Read Mask (IMR5RM)—Offset 56h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR5RM: [Port: 0x05] + 56h
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
RSVD
4
0
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
1
RSVD
RSVD
1
RSVD
RSVD
1
RSVD
RSVD
Intel® Quark™ SoC X1000
Datasheet
210
8
1
RSVD
RSVD
Bit
Range
12
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
VC1_SAI_ID1
1
VC1_SAI_ID2
1
RSVD
1
VC1_SAI_ID3
1
RSVD
16
1
RSVD
20
1
RSVD
24
1
RSVD
28
0
RSVD
ESRAM_FLUSH_INIT
1
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
211
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.4.28
Default &
Access
Description
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Isolated Memory Region 5 Write Mask (IMR5WM)—Offset 57h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR5WM: [Port: 0x05] + 57h
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
Default &
Access
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
Intel® Quark™ SoC X1000
Datasheet
212
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
0
VC0_SAI_ID0
1
4
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
VC1_SAI_ID1
1
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
RSVD
24
PUNIT
ESRAM_FLUSH_INIT
1
28
CPU_SNOOP
31
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
November 2014
Document Number: 329676-004US
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Intel® Quark™ SoC X1000
Datasheet
213
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
12.7.4.29
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
1b
RW/L
0
Description
Isolated Memory Region 6 Low Address (IMR6L)—Offset 58h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR6L: [Port: 0x05] + 58h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
24
0
Bit
Range
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Description
0b
RW/O
IMR Lock (IMR_LOCK): This bit locks the IMRX registers, preventing further updates
31
00h
RO
30:24
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
00h
RO
1:0
12.7.4.30
0
16
RSV1
0
20
RSV0
0
IMR_LOCK
0
28
IMRL
31
Reserved (RSV0): Reserved.
Isolated Memory Region 6 High Address (IMR6H)—Offset 59h
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR6H: [Port: 0x05] + 59h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:24
Intel® Quark™ SoC X1000
Datasheet
214
12
0
0
0
0
8
0
IMRH
RSV1
0
28
Default &
Access
00h
RO
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV0
31
Description
Reserved (RSV1): Reserved.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
000000h
RW/L
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
23:2
0h
RO
1:0
12.7.4.31
Reserved (RSV0): Reserved.
Isolated Memory Region 6 Read Mask (IMR6RM)—Offset 5Ah
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR6RM: [Port: 0x05] + 5Ah
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
0
RSVD
16
RSVD
20
RSVD
24
RSVD
ESRAM_FLUSH_INIT
1
28
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
Intel® Quark™ SoC X1000
Datasheet
215
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
216
Default &
Access
Description
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
12.7.4.32
Isolated Memory Region 6 Write Mask (IMR6WM)—Offset 5Bh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR6WM: [Port: 0x05] + 5Bh
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
RSVD
24
PUNIT
ESRAM_FLUSH_INIT
1
28
CPU_SNOOP
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
217
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
12.7.4.33
Default &
Access
Description
16
1b
RO
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Reserved (RSVD): Reserved.
Isolated Memory Region 7 Low Address (IMR7L)—Offset 5Ch
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR7L: [Port: 0x05] + 5Ch
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
218
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
0
24
0
0
Bit
Range
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
IMRL
0
8
0
0
Default &
Access
Description
0b
RW/O
IMR Lock (IMR_LOCK): This bit locks the IMRX registers, preventing further updates
31
00h
RO
30:24
Reserved (RSV1): Reserved.
000000h
RW/L
23:2
IMR Low Address (IMRL): These bits are compared with bits 31:10 of the incoming
address to determine the lower 1KB aligned value of the protected range
00h
RO
1:0
12.7.4.34
0
20
RSV1
0
IMR_LOCK
0
28
RSV0
31
Reserved (RSV0): Reserved.
Isolated Memory Region 7 High Address (IMR7H)—Offset 5Dh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR7H: [Port: 0x05] + 5Dh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
24
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:24
23:2
1:0
12.7.4.35
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
IMRH
RSV1
0
28
Default &
Access
00h
RO
000000h
RW/L
0h
RO
0
0
0
0
0
RSV0
31
Description
Reserved (RSV1): Reserved.
IMR High Address (IMRH): These bits are compared with bits 31:10 of the incoming
address to determine the upper 1KB aligned value of the protected range
Reserved (RSV0): Reserved.
Isolated Memory Region 7 Read Mask (IMR7RM)—Offset 5Eh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR7RM: [Port: 0x05] + 5Eh
Op Codes:
10h - Read, 11h - Write
Default: BFFFFFFFh
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
219
Intel® Quark™ SoC X1000—Host Bridge
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
Intel® Quark™ SoC X1000
Datasheet
220
1
RSVD
RSVD
Bit
Range
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
0
VC0_SAI_ID0
1
4
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
VC1_SAI_ID1
1
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
0
RSVD
16
RSVD
20
RSVD
24
RSVD
ESRAM_FLUSH_INIT
1
28
PUNIT
31
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Read Access Allowed to
memory delineated by IMRxL and IMRxH
30
0b
RO
29
1b
RW/L
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
Reserved (RSVD): Reserved.
Remote Management Unit (PUNIT): Remote Management Unit Read Access Allowed
to memory delineated by IMRxL and IMRxH
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.4.36
Default &
Access
Description
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Read Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Read Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
Isolated Memory Region 7 Write Mask (IMR7WM)—Offset 5Fh
Access Method
Type: Message Bus Register
(Size: 32 bits)
IMR7WM: [Port: 0x05] + 5Fh
Op Codes:
10h - Read, 11h - Write
Default: FFFFFFFFh
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU0
RSVD
1
CPU_0
RSVD
November 2014
Document Number: 329676-004US
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
VC0_SAI_ID0
1
VC0_SAI_ID1
1
VC0_SAI_ID2
1
VC0_SAI_ID3
1
VC1_SAI_ID0
1
0
VC1_SAI_ID1
1
4
VC1_SAI_ID2
1
8
RSVD
1
12
VC1_SAI_ID3
1
RSVD
16
RSVD
20
PUNIT
24
CPU_SNOOP
28
ESRAM_FLUSH_INIT
31
Intel® Quark™ SoC X1000
Datasheet
221
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
222
Default &
Access
Description
31
1b
RW/L
eSRAM Flush/Init (ESRAM_FLUSH_INIT): eSRAM Flush/Init Write Access Allowed
to memory delineated by IMRxL and IMRxH
30
1b
RW/L
CPU Snoop (CPU_SNOOP): Dirty CPU Snoop Response Write Allowed to memory
delineated by IMRxL and IMRxH. Clean snoop responses are always allowed and does
not cause an IMR violation
29
1b
RW/L
Remote Management Unit (PUNIT): Remote Management Unit Write Access Allowed
to memory delineated by IMRxL and IMRxH
28
1b
RO
Reserved (RSVD): Reserved.
27
1b
RO
Reserved (RSVD): Reserved.
26
1b
RO
Reserved (RSVD): Reserved.
25
1b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
1b
RO
Reserved (RSVD): Reserved.
22
1b
RO
Reserved (RSVD): Reserved.
21
1b
RO
Reserved (RSVD): Reserved.
20
1b
RO
Reserved (RSVD): Reserved.
19
1b
RO
Reserved (RSVD): Reserved.
18
1b
RO
Reserved (RSVD): Reserved.
17
1b
RO
Reserved (RSVD): Reserved.
16
1b
RO
Reserved (RSVD): Reserved.
15
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 3 (VC1_SAI_ID3): Host Bridge Arbiter VC1
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
14
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 2 (VC1_SAI_ID2): Host Bridge Arbiter VC1
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
13
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 1 (VC1_SAI_ID1): Host Bridge Arbiter VC1
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
12
1b
RW/L
Host Bridge Arbiter VC1 Sub-Channel 0 (VC1_SAI_ID0): Host Bridge Arbiter VC1
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
11
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 3 (VC0_SAI_ID3): Host Bridge Arbiter VC0
Sub-Channel 3 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
10
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 2 (VC0_SAI_ID2): Host Bridge Arbiter VC0
Sub-Channel 2 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
9
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 1 (VC0_SAI_ID1): Host Bridge Arbiter VC0
Sub-Channel 1 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
12.7.4.37
Default &
Access
Description
8
1b
RW/L
Host Bridge Arbiter VC0 Sub-Channel 0 (VC0_SAI_ID0): Host Bridge Arbiter VC0
Sub-Channel 0 Write Accesses Allowed to memory delineated by IMRxL and IMRxH.
7
1b
RO
Reserved (RSVD): Reserved.
6
1b
RO
Reserved (RSVD): Reserved.
5
1b
RO
Reserved (RSVD): Reserved.
4
1b
RO
Reserved (RSVD): Reserved.
3
1b
RO
Reserved (RSVD): Reserved.
2
1b
RO
Reserved (RSVD): Reserved.
1
1b
RW/L
CPU (CPU_0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
0
1b
RW/L
CPU (CPU0): CPU Write Access Allowed to memory region delineated by IMRxL and
IMRxH.
Note: Bit[0] and bit [1] of the IMR Read Mask register must always be programmed to
the same value
eSRAM Control (ESRAMCTRL)—Offset 81h
Provides control of attributes which affect all eSRAM pages.
Access Method
Type: Message Bus Register
(Size: 32 bits)
ESRAMCTRL: [Port: 0x05] + 81h
Op Codes:
10h - Read, 11h - Write
Default: 047F3F91h
November 2014
Document Number: 329676-004US
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
RSVD
1
SECDED_ENABLE
1
eSRAM_ENABLE_ALL
0
eSRAM_GLOBAL_CSR_LOCK
0
0
RSV0
0
4
eSRAM_AVAILABLE
1
8
RSV1
0
12
ECC_THRESH_SB_MSG_EN
0
16
ECC_THRESH
0
20
eSRAM_SIZE
0
24
RSV2
0
28
RSVD
31
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Bit
Range
12.7.4.38
Default &
Access
Description
31:27
0h
RO
Reserved (RSV2): Reserved.
26:25
2h
RO
Reserved (RSVD): Reserved.
24:16
07Fh
RO
eSRAM Size (eSRAM_SIZE): eSRAM size in 4k pages ( 0 means 1)
15:8
3Fh
RW/L
ECC Threshold (ECC_THRESH): Total correctable ECC threshold until the eSRAM
Correctable Error Threshold Reached message (opcode 0xD8) is sent to Remote
Management Unit. Valid values are 0x1-0xFF. 0x0 may be used as a test mode to send
the message immediately without waiting for occurrence of any correctable ECC errors.
Once the message has been sent in this way, ESRAMCERR.
CORRECTABLE_ERR_CNT_RST must be written with 1, before another message can be
generated using this test mode. Note that the test mode generation of an eSRAM
Correctable Error Threshold Reached message is not dependent on the value of
ESRAMCTRL.SECDED_ENABLE.
7
1h
RW/L
ECC Threshold Message Enable (ECC_THRESH_SB_MSG_EN): Set to 1 to enable
the message to the Remote Management Unit which is generated when ECC_THRESH
correctable ECC errors have been generated. If this field is 0, no ECC threshold message
will be generated.
6
0h
RO
Reserved (RSV1): Reserved.
5
0h
RO
Reserved (RSV0): Reserved.
4
1h
RO
eSRAM Available (eSRAM_AVAILABLE): Indicates eSRAM is available. Used as
qualifier for eSRAM_SIZE.
3
0h
RW/C
eSRAM Enable All Ranges (eSRAM_ENABLE_ALL): Used during the early BIOS
stage to enable eSRAM mapping into the system address space. Forces all eSRAM pages
which are not already enabled, and are unlocked to be ECC initialized and enabled, and
stays 0x1 until all such pages have been initialized.
NOTE: This is a locking field, locks on ESRAM_GLOBAL_CSR_LOCK.
2
0h
RW
eSRAM Global CSR Lock (eSRAM_GLOBAL_CSR_LOCK): When set to 1, all eSRAM
global and page (4KB and 512KB) registers are locked. A locked page can still be flushed
if FLUSH_PG_ENABLE/BLOCK_FLUSH_PG_ENABLE is set to 1. Once set, this field can
only be cleared by a warm reset. This is a locking field, it is locked by being set to 1.
1
0h
RO
Reserved (RSVD): Reserved.
0
1h
RW/L
SECDED Enable (SECDED_ENABLE): SECDED ECC enable for the eSRAM memory
array.
eSRAM Block Page Control (ESRAMPGCTRL_BLOCK)—Offset 82h
This register allows all eSRAM pages to be mapped and controlled as a single 512KB
block page. If this page is enabled, no 4KB pages may be individually mapped.
Access Method
Type: Message Bus Register
(Size: 32 bits)
ESRAMPGCTRL_BLOCK: [Port: 0x05] + 82h
Op Codes:
10h - Read, 11h - Write
Default: 850000FFh
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0
0
1
0
1
BLOCK_ENABLE_PG
BLOCK_INIT_IN_PROG
RSV1
BLOCK_PG_BUSY
Bit
Range
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
1
1
1
0
1
1
1
1
BLOCK_PG_SYSTEM_ADDRESS_16MB
0
20
RSV0
0
BLOCK_PAGE_CSR_LOCK
24
RSVD
BLOCK_FLUSH_PG_ENABLE
1
28
BLOCK_DISABLE_PG
31
Default &
Access
Description
31
1h
RW/L
Block Flush Page Enable (BLOCK_FLUSH_PG_ENABLE): This field is used to enable
or disable flushing of the block page to DRAM by the S3 entry firmware code. The block
page may be flushed only by the S3 entry firmware code.
30
0h
RO
29
0h
RW/C
Block Disable Page (BLOCK_DISABLE_PG): When written with 0x1 disables block
page decoding by eSRAM. This bit stays 0x1 until the block page has been disabled and
ECC initialized. Note that this is a locking field, which locks on
BLOCK_PAGE_CSR_LOCK=1 and ESRAMCTRL.eSRAM_GLOBAL_CSR_LOCK. This field
should only be used by BIOS code.
28
0h
RW/C
Block Enable Page (BLOCK_ENABLE_PG): When written with 0x1 enables block
page mapping of the eSRAM. When the block page is enabled, address mapping for all
pages will be controlled by the block page address, instead of the 4KB page address
fields. Cleared when the page flush/disable completes. Note that this is a locking field,
locks on BLOCK_PAGE_CSR_LOCK=1 and ESRAMCTRL.eSRAM_GLOBAL_CSR_LOCK.
27
0h
RW
Block Page Register Lock (BLOCK_PAGE_CSR_LOCK): When set to 1, the block
page register (ESRAMPGCTRL_BLOCK) is locked. When locked, the block page may still
be flushed to DRAM by the firmware S3 entry code by setting
BLOCK_FLUSH_PG_ENABLE to 1.
26
1h
RO/V
Block Page Initialization in Progress (BLOCK_INIT_IN_PROG): Reads 0x1 as
long as the block page is being re-initialized following the disable. Note that while page
is being flushed or re-initialized the eSRAM will block the access to the page stalling any
requestor trying to access it. It also stays high until the ECC initialization completes
after the reset.
25
0h
RO
24
1h
RO/V
Block Page Busy (BLOCK_PG_BUSY): Reads 0x1 when the block page is enabled and
stays 0x1 until the block page has been flushed (if flush was to be performed) and
reinitialized following disable. It also stays high until the ECC initialization completes
after the reset.
23:8
0000h
RO
Reserved (RSV0): Reserved.
7:0
FFh
RW/L
Block Page Base Address (BLOCK_PG_SYSTEM_ADDRESS_16MB): Base address
of the 512KB eSRAM block page (bits [31:24] of the system memory address). The
eSRAM block page may only be placed on 16MB boundaries. Writes to this register will
only update the contents when ESRAMPGCTRL_BLOCK.BLOCK_ENABLE_PG is 0. Note
that the value in this register field is locked until the page has been disabled and is free.
November 2014
Document Number: 329676-004US
Reserved (RSVD): Reserved.
Reserved (RSV1): Reserved.
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225
Intel® Quark™ SoC X1000—Host Bridge
12.7.4.39
eSRAM Correctable Error (ESRAMCERR)—Offset 83h
Provides status information for correctable ECC errors.
Access Method
Type: Message Bus Register
(Size: 32 bits)
ESRAMCERR: [Port: 0x05] + 83h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
24
0
0
Bit
Range
31:26
20
0
CORRECTABLE_ERR_CNT_RST
0
0
0
0
16
0
0
0
0
Default &
Access
0h
RO
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Reserved (RSV1): Reserved.
0h
RW/C
Correctable Error Counter Reset (CORRECTABLE_ERR_CNT_RST): Resets the
correctable ECC error counter.
24:17
0h
RO/P
Correctable Error Counter (CORRECTABLE_ERR_CNT): Correctable ECC error
count. Saturates at 8'hFF
0h
RO
0
Description
25
16
12.7.4.40
0
CORRECTABLE_ERR_PG_NUM
0
CORRECTABLE_ERR_PG_DW_OFFSET
0
RSV0
28
0
RSV1
0
CORRECTABLE_ERR_CNT
31
Reserved (RSV0): Reserved.
15:9
0h
RO/P
Correctable Error Page DW Offset (CORRECTABLE_ERR_PG_DW_OFFSET): Page
DW offset for the last Correctable ECC Error
8:0
0h
RO/P
Correctable Error Page Number (CORRECTABLE_ERR_PG_NUM): Page number
for the last Correctable ECC Error
eSRAM Uncorrectable Error (ESRAMUERR)—Offset 84h
Provides status information for the uncorrectable ECC error.
Access Method
Type: Message Bus Register
(Size: 32 bits)
ESRAMUERR: [Port: 0x05] + 84h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
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Host Bridge—Intel® Quark™ SoC X1000
0
0
0
0
0
0
0
0
0
0
Bit
Range
0
0
Default &
Access
0000h
RO
31:18
12.7.4.41
0
12
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
UNCORRECTABLE_ERR_PG_NUM
0
16
UNCORRECTABLE_ERR_PG_DW_OFFSET
0
20
UNCORRECTABLE_ERR_OCCURED
0
24
RSV0
0
28
UNCORRECTABLE_ERR_OCCURED_FLUSH
31
Description
Reserved (RSV0): Reserved.
17
0h
RW/1C/P
Uncorrectable Error Occurred during Flush
(UNCORRECTABLE_ERR_OCCURED_FLUSH): Sticky register field which asserts
when an uncorrectable ECC error has occurred during an eSRAM flush to DRAM. Set by
hardware, cleared by software writing a 1.
16
0h
RW/1C/P
Uncorrectable Error Occurred (UNCORRECTABLE_ERR_OCCURED): Sticky
register field which asserts when an uncorrectable ECC error has occurred. Set by
hardware, cleared by software writing a 1.
15:9
0h
RO/P
Uncorrectable Error Page DW Offset
(UNCORRECTABLE_ERR_PG_DW_OFFSET): Page DW offset for the uncorrectable
ECC Error
8:0
0h
RO/P
Uncorrectable Error Page Number (UNCORRECTABLE_ERR_PG_NUM): Page
number for the uncorrectable ECC Error
eSRAM ECC Error Syndrome (ESRAMSDROME)—Offset 88h
Access Method
Type: Message Bus Register
(Size: 32 bits)
ESRAMSDROME: [Port: 0x05] + 88h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
SYNDROME
0
28
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227
Intel® Quark™ SoC X1000—Host Bridge
Bit
Range
Default &
Access
Description
0h
RO/P
Syndrome (SYNDROME): Syndrome for the last ECC (SECDED) error. For single bit
errors, can be used to decode which bit of the eSRAM read data or ECC code was
incorrect. Bits [7:0] relate to esram_ecc_out[7:0] and esram_data_out[63:0], Bits
[15:8] relate to esram_ecc_out[15:8] and esram_data_out[127:64], Bits [23:16] relate
to esram_ecc_out[23:16] and esram_data_out[191:128], Bits [31:24] relate to
esram_ecc_out[31:24] and esram_data_out[255:192].
31:0
12.7.5
Memory Manager eSRAM (Port 0x05)
Table 77.
Summary of Message Bus Registers—0x05
Offset
0h + [0127]*4h
12.7.5.1
Default
Value
Register Name (Register Symbol)
“eSRAM Page Control Register[0-127] (ESRAMPGCTRL[0-127])—Offset 0h, Count 128, Stride 4h” on
850FFFFFh
page 228
eSRAM Page Control Register[0-127] (ESRAMPGCTRL[0-127])—Offset
0h, Count 128, Stride 4h
This register provides individual per page control and status information.
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset[0-127]: [Port: 0x05] + 0h + [0-127]*4h
Op Codes:
12h - Read, 13h - Write
Default: 850FFFFFh
1
0
1
INIT_IN_PROG
RSV1
PG_BUSY
Bit
Range
31
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Datasheet
228
20
0
0
0
0
16
1
1
1
1
12
1
1
1
1
8
1
1
1
1
4
1
1
1
1
0
1
1
1
1
PG_SYSTEM_ADDRESS_4K
0
RSV0
0
ENABLE_PG
24
0
PAGE_CSR_LOCK
28
0
FLUSH_PG
FLUSH_PG_ENABLE
1
DISABLE_PG
31
Default &
Access
Field Name (ID): Description
1h
RW/L
Flush Page Enable (FLUSH_PG_ENABLE): When PAGE_CSR_LOCK is set to 0,
setting this bit means the page has a corresponding DRAM overlay and will be flushed to
the DDR and disabled when the ESRAMCTRL.eSRAM_Flush_and_Disable is set. When
PAGE_CSR_LOCK is set to 1, setting this bit to 0 will prevent flushes via the FLUSH_PG
field as well as prevent flushing and disabling via
ESRAMCTRL.eSRAM_Flush_and_Disable. Since locked pages which s/w does not want to
flush to DRAM for security reasons, will now remain enabled after a global flush and
disable, software must ensure that traffic to those locked pages is quiesced before
entrance to S3 low power.
November 2014
Document Number: 329676-004US
Host Bridge—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
30
0h
RW/C
Flush Page (FLUSH_PG): Initiates flushing the page to DRAM, the page has to have a
DRAM overlay and can't be mapped on top of physical memory. After being set, reads as
0x1 until the page has been flushed to DRAM. Note that while the page is being flushed,
the eSRAM will block accesses to the page stalling any other requestor trying to access
it.
29
0h
RW/C
Disable Page (DISABLE_PG): When written with 0x1 disables page decoding by
eSRAM. When set in the same cycle as Flush Page, the flushing takes place prior to
disabling and reinitializing. This bit stays 0x1 until the page has been flushed, disabled
and ECC initialized. Note that this is a locking field, locks on PAGE_CSR_LOCK.
28
0h
RW/C
Enable Page (ENABLE_PG): When written with 0x1 enables page decoding by eSRAM.
Same effect will be achieved on all eSRAM page CSRs when the ESRAMCTRL.
eSRAM_Enable_All is set. Cleared when the page flush/disable completes. Note that this
is a locking field, locks on PAGE_CSR_LOCK.
27
0h
RW
Lock Page (PAGE_CSR_LOCK): When set to 1, the per page (ESRAMPGCTRLX)
register for this page is locked. While the page is locked, it may still be flushed via the
FLUSH_PG field of this register or via ESRAMCTRL.eSRAM_Flush_and_Disable if
FLUSH_PG_ENABLE is set to 1.
26
1h
RO/V
Initialisation In Progress (INIT_IN_PROG): Reads 0x1 as long as the page is being
re-initialized following the disable. Note that while page is being flushed or re-initialized
the eSRAM will block the access to the page stalling any requestor trying to access it. It
also stays high until the ECC initialization completes after the reset.
25
0h
RO
24
1h
RO/V
23:20
19:0
0h
RO
1FFFFFh
RW/L
Reserved (RSV1): Reserved.
Page Busy (PG_BUSY): Reads 0x1 when the page is enabled and stays 0x1 until the
page has been flushed (if flush was to be performed) and reinitialized following disable.
It also stays high until the ECC initialization completes after the reset.
Reserved (RSV0): Reserved.
Page 4K Address (PG_SYSTEM_ADDRESS_4K): 20b of base address for the 4K
page. Needs to be stable before the page is enabled and must stay untouched until the
page has been disabled and flushed. Software may pool the PG_BUSY bit to find out the
status of the page allocation, and attempt to allocate address and enable new page only
when the previous deallocation has successfully completed. Another less read intensive
method is using the dynamic pool mechanism as per the global ESRAMPGPOOL register.
Note that the value in this CSR is locked until the page has been disabled and is free.
12.7.6
SoC Unit (Port 0x31)
Table 78.
Summary of Message Bus Registers—0x31
Offset
34h
Register Name (Register Symbol)
“Thermal Sensor Configuration 4 (SCU_TSCFG4_Config)—Offset 34h” on page 229
Default
Value
00057801h
50h
“Sticky Write Once (CFGSTICKY_W1)—Offset 50h” on page 230
00000000h
51h
“Sticky Read/Write (CFGSTICKY_RW)—Offset 51h” on page 231
00000000h
52h
“Non-Sticky Read/Write Once (CFGNONSTICKY_W1)—Offset 52h” on page 231
00000000h
12.7.6.1
Thermal Sensor Configuration 4 (SCU_TSCFG4_Config)—Offset 34h
Access Method
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Intel® Quark™ SoC X1000—Host Bridge
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x31] + 34h
Op Codes:
06h - Read, 07h - Write
Default: 00057801h
Bit
Range
12.7.6.2
0
Default &
Access
0
0
0
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
ts_itsrst
0
0
RSVD
0
4
RSVD
0
8
RSVD
0
12
RSVD
0
16
RSVD
0
20
RSVD
0
24
RSVD
0
28
RSVD
31
Field Name (ID): Description
31:25
0h
RO
Reserved (RSVD): Reserved.
24:23
0h
RO
Reserved (RSVD): Reserved.
22:11
AFh
RO
Reserved (RSVD): Reserved.
10:8
0h
RO
Reserved (RSVD): Reserved.
7
0h
RO
Reserved (RSVD): Reserved.
6:5
0h
RO
Reserved (RSVD): Reserved.
4:3
0h
RO
Reserved (RSVD): Reserved.
2:1
0h
RO
Reserved (RSVD): Reserved.
0
1h
RW
Thermal Sensor Reset (ts_itsrst): Resets all Thermal Sensor registers.
Sticky Write Once (CFGSTICKY_W1)—Offset 50h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x31] + 50h
Op Codes:
06h - Read, 07h - Write
Default: 00000000h
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Host Bridge—Intel® Quark™ SoC X1000
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
STICKY_W1_STRATCH
0
28
Bit
Range
Default &
Access
0000h
RW/O
31:0
12.7.6.3
Field Name (ID): Description
Sticky Write Once Scratchpad (STICKY_W1_STRATCH): Assigned by Software,
write once requires a S0 exit to clear
Sticky Read/Write (CFGSTICKY_RW)—Offset 51h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x31] + 51h
Op Codes:
06h - Read, 07h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
STRICKY_RW_STRATCH
0
28
Bit
Range
31:0
12.7.6.4
Default &
Access
Field Name (ID): Description
0000h
RW/P
Sticky Read/Write Scratchpad (STRICKY_RW_STRATCH): Assigned by Software,
reset by a S0 exit
Non-Sticky Read/Write Once (CFGNONSTICKY_W1)—Offset 52h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x31] + 52h
Op Codes:
06h - Read, 07h - Write
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
NONSTICKY_W1_STRATCH
0
28
Bit
Range
31:0
Default &
Access
0000h
RW/O
Field Name (ID): Description
Non-Sticky Write Once Scratchpad (NONSTICKY_W1_STRATCH): Assigned by
Software, reset by a warm reset while in S0
§§
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System Memory Controller—Intel® Quark™ SoC X1000
13.0
System Memory Controller
The system memory controller supports DDR3 protocol with one 16-bit wide data
channel and up to 2 ranks of memory, allowing for population of up to 2Gbyte of
system memory using 1, 2 or 4 Gbit standard DDR3 devices. It is capable of data rates
up to 800 MT/s.
13.1
Signal Descriptions
See Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 79.
Memory Signals (Sheet 1 of 2)
Signal Name
Direction
Type
DDR3_CK[1:0]
DDR3_CKB[1:0]
O
DDR3
DRAM Differential Clock Pair: (1 pair per Rank)
The differential clock pair is used to latch the command into
DRAM. Each pair corresponds to a rank on the DRAM side.
DDR3_CSB[1:0]
O
DDR3
Chip Select: (1 per Rank). Used to qualify the command on the
command bus for a particular rank.
DDR3_CKE[1:0]
O
DDR3
Clock Enable: (power management - 1 per Rank)
It is used during DRAM power up/power down and self refresh.
DDR3_MA[15:0]
O
DDR3
Memory Address: Multiplexed Memory address bus (Row, Column)
for writing data to memory and reading data from memory. These
signals follow common clock protocol w.r.t. DDR3_CK, DDR3_CKB
pairs.
DDR3_BS[2:0]
O
DDR3
Bank Select: These signals define which banks are selected within
each DRAM rank.
DDR3_RASB
O
DDR3
Row Address Select: Used with DDR3_CASB and DDR3_WEB
(along with DDR3_CSB) to define the DRAM Commands.
DDR3_CASB
O
DDR3
Column Address Select: Used with DDR3_RASB and DDR3_WEB
(along with DDR3_CSB) to define the DRAM Commands.
DDR3_WEB
O
DDR3
Write Enable Control Signal: Used with DDR3_WEB and
DDR3_CASB (along with control signal, DDR3_CSB) to define the
DRAM Commands.
DDR3_DQ[15:0]
I/O
DDR3
Bidirectional Data Lines
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Intel® Quark™ SoC X1000—System Memory Controller
Table 79.
Memory Signals (Sheet 2 of 2)
Signal Name
Direction
Type
Description
DDR_DM[1:0]
O
DDR3
Data Mask: DM is an output mask signal for write data. Output
data is masked when DM is sampled HIGH coincident with that
output data during a Write access. DM is sampled on both edges of
DQS.
DDR3_DQS[1:0]
DDR3_DQSB[1:0]
I/O
DDR3
Data Strobes: DDR3_DQSB[1:0] and its complement signal group
make up a differential strobe pair for each 8 data bits - DQ. The
data is captured at the crossing point of DDR3_DQS[1:0] and its
DDR3_DQSB[1:0] during read and write transactions. For Read,
the Strobe crossover and data are edge aligned, whereas in the
Write command, the strobe crossing is in the centre of the data
window.
DDR3_ODT[1:0]
O
DDR3
ODT signal (One per rank) going to DRAM in order to turn ON the
DRAM ODT during Write.
DDR3_ODTPU
O
Analog
This signal must be terminated to VSS on board (refer to the
Platform Design Guide for resistor value). This external resistor
termination scheme is used for Resistor compensation of DRAM
ODT strength.
DDR3_DQPU
O
Analog
This signal must be terminated to VSS on board (refer to the
Platform Design Guide for resistor value). This external resistor
termination scheme is used for Resistor compensation of DQ
buffers
DDR3_CMDPU
O
Analog
This signal must be terminated to VSS on board (refer to the
Platform Design Guide for resistor value). This external resistor
termination scheme is used for Resistor compensation of CMD
buffers.
DDR3_VREF
I
Analog
DRAM Interface Reference Voltage: This signal voltage level is
used for qualifying logical levels on the DQ bits on reads. The
Memory interface can also use internally generated reference
voltage to qualify the crossing point between logical levels on Data
bits. Internal Vref is a default setting for Memory Interface and
this interface signal and can be tied to VSS on board.
DDR3_ISYSPWRGOOD
I
Asynchronous
CMOS
This signal indicates the status of the DRAM Core power supply.
DDR3_IDRAM_PWROK
I
Asynchronous
CMOS
This signal indicates the status of the DRAM S3 power supply.
Used primarily in the DRAM PHY to determine ACPI S3 power
state.
DDR3_DRAMRSTB
O
This signal is used to reset DRAM devices.
13.2
Features
13.2.1
System Memory Technology Supported
The system memory controller supports the following DDR3 Data Transfer Rates and
DRAM Device Technologies:
• DDR3 Data Transfer Rate: 800 MT/s
• DDR3 (1.5V DRAM interface I/Os)
• DDR3 x8 memory modules
Note:
x8 means that each DRAM component has 8 data lines. Standard 1Gbit, 2Gbit, and
4Gbit technologies and addressing are supported for x8 devices.
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Table 80.
Table 81.
13.2.2
Supported DDR3 DRAM Devices
DRAM
Density
Data Width
Banks
Bank
Address
Row
Address
Column
Address
Page Size
1 Gbit
x8
8
BA[2:0]
A[13:0]
A[9:0]
1 Kbyte
2 Gbit
x8
8
BA[2:0]
A[14:0]
A[9:0]
1 Kbyte
4 Gbit
x8
8
BA[2:0]
A[15:0]
A[9:0]
1 Kbyte
Supported DDR3 Memory Configurations
DRAM Chip
Density
DRAM Device
Width
# of DRAM Devices
per Rank
Rank Size
# of Ranks
Total Memory Size
1 Gbit
x8
2
256 Mbyte
1
256 Mbyte
1 Gbit
x8
2
256 Mbyte
2
512 Mbyte
2 Gbit
x8
2
512 Mbyte
1
512 Mbyte
2 Gbit
x8
2
512 Mbyte
2
1 Gbyte
4 Gbit
x8
2
1 Gbyte
1
1 Gbyte
4 Gbit
x8
2
1 Gbyte
2
2 Gbyte
Rules for Populating Memory Down Ranks
The devices density and width for both ranks must be the same. Rank0 must be always
populated and Rank1 is optional.
13.2.3
DRAM Error Detection & Correction (EDC)
For high reliability applications the system memory controller supports inclusion of
Error Correction Codes (ECC) in DRAM transactions. In ECC mode, the 8th bank of each
rank is allocated for ECC data storage, thus reducing the total available physical
memory for the system by 12.5% or 1/8. Additionally each transaction to memory
requires an associated ECC transaction reducing the useful memory bandwidth.
The algorithm used allows for on-the-fly correction of single bit errors and detection of
double bit errors.
A separate bank is used for ECC data storage to avoid the page-miss (row pre-charge)
time penalty on ECC and next data fetch that would have been introduced in majority
of cases if the ECC was interleaved across banks. The ECC bank can be configured to
always issue RD/WR with Auto Precharge or dynamic page close policy similar to other
data banks. Since the configuration is on a per bank basis, the ECC bank is not required
to have the same policy as other banks.
When ECC is enabled, the Address Map field in the DRAM Rank Population (DRP)—
Offset 0h register MUST be set to 2. In a two ranks system, the size of both ranks can
be the same or different. Therefore, each rank can have different DRAM device width
and density, and thus different rank size. Setting the address map to 2 applies to both
ranks.
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Intel® Quark™ SoC X1000—System Memory Controller
13.2.4
DRAM Data Scrambling
The Memory Controller supports data scrambling. This feature helps in lowering the
MTBF (Mean Time Between Failures) by reducing the probability of occurrence of the
specific bit patterns on the DRAM I/O interface that could cause unpredictable behavior
at the platform design stage, i.e., signal integrity issues.
13.2.5
Power Management
The System Memory Controller Power Management features are detailed in Section 8.5.
13.3
Register Map
See Chapter 5.0, “Register Access Methods” for additional information.
Figure 26.
Register Map
CPU
Core
Host
Bridge
B:0,D:0,F0
Message Bus Space
Port: 0x00
Port: 0x01
Port: 0x02
Port: 0x04
Port: 0x05
Memory
Arbiter
Memory
Controller
Host
Bridge
Remote
Management
Unit
Memory
Manager
13.4
Message Bus Registers
Table 82.
Summary of Message Bus Registers—0x01
Offset
Register Name (Register Symbol)
Default
Value
0h
“DRAM Rank Population (DRP)—Offset 0h” on page 237
00000000h
1h
“DRAM Timing Register 0 (DTR0)—Offset 1h” on page 238
43001110h
2h
“DRAM Timing Register 1 (DTR1)—Offset 2h” on page 240
02690320h
3h
“DRAM Timing Register 2 (DTR2)—Offset 3h” on page 242
00040504h
4h
“DRAM Timing Register 3 (DTR3)—Offset 4h” on page 243
06406205h
5h
“DRAM Timing Register 4 (DTR4)—Offset 5h” on page 244
00000022h
6h
“DRAM Power Management Control 0 (DPMC0)—Offset 6h” on page 245
03000000h
8h
“DRAM Refresh Control (DRFC)—Offset 8h” on page 247
00012CA7h
9h
“DRAM Scheduler Control (DSCH)—Offset 9h” on page 248
00071108h
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Table 82.
Summary of Message Bus Registers—0x01 (Continued)
Offset
Default
Value
Register Name (Register Symbol)
Ah
“DRAM Calibration Control (DCAL)—Offset Ah” on page 249
00001300h
Bh
“DRAM Reset Management Control (DRMC)—Offset Bh” on page 250
00000000h
Ch
“Power Management Status (PMSTS)—Offset Ch” on page 251
00000000h
Fh
“DRAM Control Operation (DCO)—Offset Fh” on page 252
00000000h
4Ah
“Sticky Scratchpad 0 (SSKPD0)—Offset 4Ah” on page 252
00000000h
4Bh
“Sticky Scratchpad 1 (SSKPD1)—Offset 4Bh” on page 253
00000000h
60h
“DRAM ECC Control Register (DECCCTRL)—Offset 60h” on page 253
00000000h
61h
“DRAM ECC Status (DECCSTAT)—Offset 61h” on page 254
00000000h
62h
“DRAM ECC Single Bit Error Count (DECCSBECNT)—Offset 62h” on page 254
00000000h
68h
“DRAM Single Bit ECC Error Captured Address (DECCSBECA)—Offset 68h” on page 255
00000000h
69h
“DRAM Single Bit ECC Error Captured Syndrome (DECCSBECS)—Offset 69h” on page 256
00000000h
6Ah
“DRAM Double Bit ECC Error Captured Address (DECCDBECA)—Offset 6Ah” on page 256
00000000h
6Bh
“DRAM Double Bit ECC Error Captured Syndrome (DECCDBECS)—Offset 6Bh” on page 257
00000000h
70h
“Memory Controller Fuse Status (DFUSESTAT)—Offset 70h” on page 257
00000000h
80h
“Scrambler Seed (DSCRMSEED)—Offset 80h” on page 258
00000000h
13.4.1
DRAM Rank Population (DRP)—Offset 0h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 0h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
Bit
Range
Default &
Access
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RKEN0
0
RKEN1
0
Rsvd_0
20
0
DIMMDWID0
0
DIMMDDEN0
0
Rsvd_1
0
DIMMDWID1
24
0
DIMMDDEN1
0
Rsvd_3
Rsvd_4
0
PRI64BSPLITEN
28
0
MODE32
0
ADDRMAP
31
Field Name (ID): Description
31
0h
RO
30
0h
RW/P/L
16-bit/32-bit Mode Select (MODE32): 0 - Selects 16-bit DRAM Data Interface.
1 - Selects 32-bit DRAM Data Interface.
0000h
RO
Rsvd_3: Reserved
29:16
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Rsvd_4: Reserved
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Bit
Range
Default &
Access
15:14
13
0h
RW/P/L
Address Map Select (ADDRMAP): See Address Mapping section for full description.
0 Map 0
1 Map 1
2 Map 2
Note: The address map select should be set the same for both the Memory Controller
and the Memory Manager.
0h
RW
64B Split Enable (PRI64BSPLITEN): Setting this bit to '1' enables logic to split 64B
PRI transactions to two 32B transactions. This bit must be set if ECC mode is enabled.
12:11
0h
RW/P/L
Rank 1 Device Density (DIMMDDEN1): This sets the density of the DRAM devices
populated in Rank 1.
00 1Gbit
01 2Gbit
10 4Gbit
11 Reserved
10:9
0h
RW/P/L
Rank 1 Device Width (DIMMDWID1): Indicates the width of the DRAM devices
populated in Rank 1.
00 x8
01 Future Support
10 Reserved
11 Reserved
0h
RO
8
13.4.2
Field Name (ID): Description
Rsvd_1: Reserved
7:6
0h
RW/P/L
Rank 0 Device Density (DIMMDDEN0): This sets the density of the DRAM devices
populated in Rank 0.
00 1Gbit
01 2Gbit
10 4Gbit
11 Reserved
5:4
0h
RW/P/L
Rank 0 Device Width (DIMMDWID0): Indicates the width of the DRAM devices
populated in Rank 0.
00 x8
01 Future Support
10 Reserved
11 Reserved
3:2
0h
RO
Rsvd_0: Reserved
1
0h
RW/P/L
Rank Enable 1 (RKEN1): Should be set to 1 when device has 2 ranks to enable the
use of second rank. Otherwise, must be set to 0.
0
0h
RW/P/L
Rank Enable 0 (RKEN0): Should be set to 1 when Rank 0 is populated to enable the
use of this rank. Otherwise, must be set to 0.
DRAM Timing Register 0 (DTR0)—Offset 1h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 1h
Op Codes:
10h - Read, 11h - Write
Default: 43001110h
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0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
DFREQ
0
0
Rsvd_5
0
4
tRP
0
8
tRCD
0
tCL
0
tXS
0
12
Rsvd_8
0
tXSDLL
0
Rsvd_9
1
tZQCS
1
16
Rsvd_10
0
tZQoper
0
Rsvd_11
0
20
Rsvd_12
0
24
PMEDLY
1
CKEDLY
0
28
Rsvd_13
31
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Bit
Range
Default &
Access
Field Name (ID): Description
31:28
4h
RW
Clock Valid To Self-Refresh Exit Delay (CKEDLY): Additional delay between CK/CKB
start and SRX command. This delay is needed for clock to stabilize to meet JEDEC
requirements. Delay is CKEDLY multiples of 256 DRAM Clocks.
0ns to 9,600ns (DDR3-800)
0ns to 7,200ns (Future DDR3-1066)
27:26
0h
RO
Rsvd_13: Reserved
25:24
3h
RW
Power Mode Entry Delay (PMEDLY): The delay, in DRAM clocks, between SR Entry
command and Power-Mode message to DDRIO.
0h - 6 DRAM Clocks.
1h - 8 DRAM Clocks.
2h - 10 DRAM Clocks.
3h - 12 DRAM Clocks.
23
0h
RO
Rsvd_12: Reserved
22
0h
RW
ZQCal Long Delay (tZQoper): The delay, in DRAM clocks, between ZQC-Long
command to any command.
Note: ZQCL command during DRAM Init flow requires longer latency which is controlled
be BIOS.
0h - 256 DRAM Clocks.
1h - 384 DRAM Clocks.
Note: This field defines the ZQ Calibration Long delay during normal operation. It is not
the same as tZQinit, which uses the same ZQCL command but the delay is longer.
tZQinit applies only during power-on initialization of the DRAM devices, and tZQoper
applies during normal operation. BIOS executes the DRAM initialization sequence, so it
has to ensure tZQinit is met, and not the Memory Controller.
21
0h
RO
Rsvd_11: Reserved
20
0h
RW
ZQCal Short Delay (tZQCS): The delay, in DRAM clocks, between a ZQC-Short
command to any command.
0h - 64 DRAM Clocks.
1h - 96 DRAM Clocks.
19
0h
RO
Rsvd_10: Reserved
18
0h
RW
Self-Refresh Exit To DLL Delay (tXSDLL): The delay, in DRAM clocks, between SRX
command to any command requiring locked DLL. Only ZQCL can be sent before tXSDLL
is done.
0h - tXS + 256 DRAM Clocks.
1h - tXS + 384 DRAM Clocks.
17
0h
RO
Rsvd_9: Reserved
16
0h
RW
Self-Refresh Exit Delay (tXS): The delay, in DRAM clocks, between SRX command to
command not requiring locked DLL. The Memory Controller can send a ZQCL command
after tXS. JEDEC defines MAX(5CK, tRFC(min)+10ns) so both values take safety margin.
0h - 256 DRAM Clocks.
1h - 384 DRAM Clocks.
15
0h
RO
Rsvd_8: Reserved
1h
RW
CAS Latency (tCL): Specifies the delay, in DRAM clocks, between the issue of a RD
command and the return of valid data on the DQ bus.
0h - 5 DRAM Clocks (DDR3-800)
1h - 6 DRAM Clocks (DDR3-800)
2h - Reserved
3h - Reserved
4h - Reserved
5h - Reserved
6h - Reserved
7h - Reserved
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Bit
Range
Default &
Access
1h
RW
Activate (RAS) to CAS Delay (tRCD): Specifies the delay, in DRAM clocks, between
an ACT command and a RD/WR command to the same bank.
0h - 5 DRAM Clocks (DDR3-800)
1h - 6 DRAM Clocks (DDR3-800
2h - Reserved
3h - Reserved
4h - Reserved
5h - Reserved
6h - Reserved
7h - Reserved
7:4
1h
RW
Precharge to Activate Delay (tRP): Specifies the delay, in DRAM clocks, between a
PRE command and an ACT command to the same bank.
0h - 5 DRAM Clocks (DDR3-800)
1h - 6 DRAM Clocks (DDR3-800
2h - Reserved
3h - Reserved
4h - Reserved
5h - Reserved
6h - Reserved
7h - Reserved
3:2
0h
RO
Rsvd_5: Reserved
0h
RW
DRAM Frequency (DFREQ): Specifies the DDR3 frequency used by the Memory
Controller for computing proper cycle to cycle timings. Note this configuration has no
impact on the actual DRAM clock.
0h - DDR3-800
1h - Reserved
2h - Reserved
3h - Reserved
Note: This configuration has no impact on the actual DRAM clock frequency.
11:8
1:0
13.4.3
Field Name (ID): Description
DRAM Timing Register 1 (DTR1)—Offset 2h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 2h
Op Codes:
10h - Read, 11h - Write
Default: 02690320h
Bit
Range
1
Default &
Access
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
tWCL
0
0
Rsvd_14
1
tCMD
1
4
Rsvd_15
0
8
tWTP
0
tCCD
1
12
Rsvd_16
0
16
tFAW
0
20
tRAS
0
24
tRRD
0
tRTP
0
Rsvd_18
0
28
Rsvd_17
31
Field Name (ID): Description
0h
RO
Rsvd_18: Reserved
30:28
0h
RW
Read to Precharge Delay (tRTP): The minimal delay between RD command and PRE
command to same bank.
001 - 4 DRAM Clocks (DDR3-800)
010 - 5 DRAM Clocks)
011 - 6 DRAM Clocks
100 - 7 DRAM Clocks
27:26
0h
RO
Rsvd_17: Reserved
31
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Bit
Range
Default &
Access
Field Name (ID): Description
2h
RW
Row Activation to Row Activation Delay (tRRD): The minimal time interval
between 2 ACT commands to any bank in the same DRAM device. Limits peak current
profile.
00 - 4 DRAM Clocks (1KB page DDR3-800), (2KB page DDR3-800)
01 - 5 DRAM Clocks
10 - 6 DRAM Clocks
11 - 7 DRAM Clocks
Note: This timing parameter applies to both Ranks, so set it based on the rank with the
large tRRD value.
6h
RW
Row Activation Period (tRAS): The minimal delay, in DRAM clocks, between ACT
command and PRE command to same bank. At least equal to tRCD + tCWL + tCCD +
tWR 0h -14 DRAM Clocks.
1h -15 DRAM Clocks (DDR3-800)
2h -16 DRAM Clocks.
3h -17 DRAM Clocks.
4h -18 DRAM Clocks.
5h -19 DRAM Clocks.
6h -20 DRAM Clocks
7h -21 DRAM Clocks.
8h -22 DRAM Clocks.
9h -23 DRAM Clocks.
Ah -24 DRAM Clocks
Others - Reserved
19:16
9h
RW
Four Bank Activation Window (tFAW): A rolling time-frame, in which a maximum of
4 ACT commands (per rank) can be sent. Limits peak current profile.
0h - Reserved.
1h - Reserved.
2h - 14 DRAM Clocks.
3h - 16 DRAM Clocks (1KB page DDR3-800).
4h - 18 DRAM Clocks.
5h - 20 DRAM Clocks (2KB page DDR3-800.
6h - 22 DRAM Clocks.
7h - 24 DRAM Clocks .
8h - 26 DRAM Clocks.
9h - 28 DRAM Clocks.
Ah - 30 DRAM Clocks.
Bh - 32 DRAM Clocks
Ch - Reserved.
Dh - Reserved.
Eh - Reserved.
Fh - Reserved.
Note: This timing parameter applies to both Ranks, so set it based on the rank with the
large tFAW value.
15:14
0h
RO
Rsvd_16: Reserved
0h
RW
CAS to CAS delay (tCCD): The minimum delay, in DRAM clocks, between 2 RD/WR
commands.
0h - 4 DRAM Clocks. Functional mode. (DDR3-800).
1h - 12 DRAM Clocks. DFX stretch mode (x2).
2h - 18 DRAM Clocks. DFX stretch mode (x4).
3h - Reserved
3h
RW
Write To Prechange Delay (tWTP): The minimum delay, in DRAM clocks, between a
WR command and a PRE command to the same bank. Value should be computed as 4 +
tWCL + tWR.
1h - 15 DRAM Clocks DDR3-800).
2h - 16 DRAM Clocks.
3h - 17 DRAM Clocks.
4h - 18 DRAM Clocks
5h - 19 DRAM Clocks.
6h - 20 DRAM Clocks.
7h - 21 DRAM Clocks
8h - 22 DRAM Clocks.
Others - Reserved
Note: This is not a JEDEC timing parameter. It is derived from other JEDEC timing
parameters.
25:24
23:20
13:12
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Bit
Range
Default &
Access
0h
RO
Rsvd_15: Reserved
5:4
2h
RW
Command Transport Duration (tCMD): The time period, in DRAM clocks, that a
command occupies the DRAM command bus. 1N is the DDR3 basic requirement. 2N and
3N are extended modes for board signal-integrity.
0h - 1 DRAM Clock (1N).
1h - 2 DRAM Clocks (2N).
2h - 3 DRAM Clocks (3N).
Note: This is a board design timing parameter and not part of JEDEC spec.
3
0h
RO
Rsvd_14: Reserved
0h
RW
CAS Write Latency (tWCL): The delay, in DRAM clocks, between the internal write
command and the availability of the first bit of DRAM input data.
0h - 5 DRAM Clocks (DDR3-800)
1h - 6 DRAM Clocks
2h - 7 DRAM Clocks
3h - 8 DRAM Clocks
7:6
2:0
13.4.4
Field Name (ID): Description
DRAM Timing Register 2 (DTR2)—Offset 3h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 3h
Op Codes:
10h - Read, 11h - Write
Default: 00040504h
0
0
Bit
Range
0
0
0
0
0
0
1
Default &
Access
0
0
0
0
0
0
8
0
1
0
1
4
0
0
0
0
0
0
Rsvd4_DTR2: Reserved
19:16
4h
RW
Read to Write Delay (tRWDR): Read to Write DQ delay, different ranks.
1h - 6 DRAM Clocks.
2h - 7 DRAM Clocks.
3h - 8 DRAM Clocks.
4h - 9 DRAM Clocks.
Note: This is a board design timing parameter and not part of JEDEC spec.
15:11
00h
RO
Rsvd2_DTR2: Reserved
5h
RW
Write to Write Delay (tWWDR): Write to Write DQ delay, different ranks.
0h - Reserved
1h - Reserved
2h - 6 DRAM Clocks.
3h - 7 DRAM Clocks.
4h - 8 DRAM Clocks.
5h - 9 DRAM Clocks.
6h - Reserved
7h - Reserved
Note: This is a board design timing parameter and not part of JEDEC spec.
10:8
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0
0
Field Name (ID): Description
0h
RO
31:20
1
tRRDR
0
12
Rsvd0_DTR2
0
16
tWWDR
0
20
Rsvd2_DTR2
0
24
Rsvd4_DTR2
0
28
tRWDR
31
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System Memory Controller—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
7:3
2:0
13.4.5
Field Name (ID): Description
00h
RO
Rsvd0_DTR2: Reserved
4h
RW
Read to Read Delay (tRRDR): Read to Read DQ delay, different ranks.
0h - Reserved
1h - 6 DRAM Clocks.
2h - 7 DRAM Clocks.
3h - 8 DRAM Clocks.
4h - 9 DRAM Clocks.
Others - Reserved
Note: This is a board design timing parameter and not part of JEDEC spec.
DRAM Timing Register 3 (DTR3)—Offset 4h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 4h
Op Codes:
10h - Read, 11h - Write
Default: 06406205h
Bit
Range
0
0
1
0
0
0
0
Default &
Access
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
1
tWRDR
PWDDLY
1
4
Rsvd0_DTR3
1
8
tRWSR
0
12
Rsvd2_DTR3
0
16
tWRSR
0
20
Rsvd3_DTR3
0
24
Rsvd4_DTR3
0
28
tXP
31
Field Name (ID): Description
31:28
0h
RO
Rsvd4_DTR3: Reserved
27:24
6h
RW
RD/WR command to Power-down Delay (PWDDLY): Non-JEDEC delay for
performance enhancement. Delay = PWDDLY x 4 DRAM Clocks.
23:22
1h
RW
CKR to Command Delay (tXP): Delay from CKE asserted high to any DRAM command
0h - 2 DRAM Clocks (DDR3-800 2N).
1h - 3 DRAM Clocks (DDR3-800 1N).
2h - 4 DRAM Clocks (Future DDR3-1066 1N).
3h - 5 DRAM Clocks.
21:17
0h
RO
Rsvd3_DTR3: Reserved
16:13
3h
RW
Write to Read Command Delay (tWRSR): Write to Read same rank command delay.
Should be set to 4 + tWCL + tWTR
2h - 13 DRAM Clocks (DDR3-800).
3h - 14 DRAM Clocks.
4h - 15 DRAM Clocks.
5h - 16 DRAM Clocks.
6h - 17 DRAM Clocks.
7h - 18 DRAM Clocks.
8h - 19 DRAM Clocks.
9h - 20 DRAM Clocks.
Others - Reserved
Note: This is a board design timing parameter and not part of JEDEC spec.
12
0h
RO
Rsvd2_DTR3: Reserved
November 2014
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Datasheet
243
Intel® Quark™ SoC X1000—System Memory Controller
Bit
Range
Default &
Access
Field Name (ID): Description
11:8
2h
RW
Read to Write Command Delay (tRWSR): Read to Write same rank command delay.
Should be set to tCL - tWCL + 6 + board delay if needed.
0h - 6 DRAM Clocks.
1h - 7 DRAM Clocks.
2h - 8 DRAM Clocks.
3h - 9 DRAM Clocks.
4h - 10 DRAM Clocks.
5h - 11 DRAM Clocks.
Others - Reserved
Note: This is a board design timing parameter and not part of JEDEC spec.
7:3
0h
RO
Rsvd0_DTR3: Reserved
5h
RW
Write to Read Delay (tWRDR): Write to Read DQ delay, different ranks.
0h - Reserved
1h - 6 DRAM Clocks.
2h - 7 DRAM Clocks.
3h - 8 DRAM Clocks.
4h - 9 DRAM Clocks.
5h - 10 DRAM Clocks.
Others - Reserved
Note: This is a board design timing parameter and not part of JEDEC spec.
2:0
13.4.6
DRAM Timing Register 4 (DTR4)—Offset 5h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 5h
Op Codes:
10h - Read, 11h - Write
Default: 00000022h
0
0
0
0
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
4
0
0
1
0
0
0
0
1
0
WRODTSTRT
0
8
Rsvd_22
0
12
WRODTSTOP
0
16
Rsvd_23
0
20
ODTDIS
0
24
RDODTDIS
0
28
TRGSTRDIS
31
Field Name (ID): Description
0h
RW
Rsvr_24 (RDODTDIS): Reserved
16
0h
RW
Disable Write ODT Stretching (TRGSTRDIS): Write target rank is not stretched.
When set, stretched ODT as defined above is not applied to the write target rank and
ODT command is asserted for 6 DRAM clocks. Should not be used when ODT is pulledin.
Note: This bit should be set to 0 for normal operation.
Note: This bit should not be set to 1 when ODT is configured to assert earlier than the
Write command.
15
0h
RW
ODT Disable (ODTDIS): 0 - ODT is enabled. 1 - ODT is disabled
14:7
0h
RO
Rsvd_23: Reserved
31:17
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Datasheet
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System Memory Controller—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
6:4
2h
RW
Write command to ODT de-assert delay (WRODTSTOP): For 1N Command Mode
0h WR+6
1h WR+7
2h WR+8
3h N/A
4h N/A
Others Reserved
For 2N Command Mode
0h N/A
1h WR+6
2h WR+7
3h WR+8
4h N/A
Others Reserved
For 3N Command Mode
0h N/A
1h N/A
2h WR+6
3h WR+7
4h WR+8
Others Reserved
3:2
0h
RO
Rsvd_22: Reserved
2h
RW
Write command to ODT assert delay (WRODTSTRT): JEDEC requires ODT to be
asserted on the same clock with the WR command. The Memory Controller allows to
pull-in by 1 clock in 2N mode and by 1-2 clocks in 3N mode. For most DIMM
configurations, this register should be programmed to same value as tCMD. A value of
tCMD - ODT_PULLIN can be used according to the table below which shows the ODT
command assertion with respect to the WR command assertion.
For 1N Command Mode
0h WR
1h N/A
2h N/A
3h Reserved
For 2N Command Mode
0h WR-1
1h WR
2h N/A
3h Reserved
For 3N Command Mode
0h WR-2
1h WR-1
2h WR
3h Reserved
1:0
13.4.7
Field Name (ID): Description
DRAM Power Management Control 0 (DPMC0)—Offset 6h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 6h
Op Codes:
10h - Read, 11h - Write
Default: 03000000h
November 2014
Document Number: 329676-004US
0
0
0
Rsvd_30
PCLSWKOK
Rsvd_29
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
SREDLY
0
8
RSVD
0
12
Rsvd_28
1
PCLSTO
1
PREAPWDEN
0
DYNSREN
0
16
CLKGTDIS
0
20
DISPWRDN
0
24
Rsvd27
0
REUTCLKGTDIS
Rsvd_31
0
28
ENPHYCLKGATE
31
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245
Intel® Quark™ SoC X1000—System Memory Controller
Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0h
RO
Rsvd_31: Reserved
29
0h
RW
Enable PHY Clock Gate Disable During SR (ENPHYCLKGATE): When set to 1, the
Memory Controller will turn off the 1x and 2x clock trees to the DDRIO PHY during Self
Refresh. The Memory Controller will re-enable the clocks upon Self Refresh exit.
28
0h
RW
MTE Clock Gate Disable (REUTCLKGTDIS): 0h MTE clock is gated when DCO.PMICTL
is set to 0.
1h MTE clock is ungated, overriding the DCO.PMICTL config bit.
Note: The DCO.CPGCLOCK bit overrides this bit.
27:26
0h
RO
Rsvd27: Reserved
25
1h
RW
Disable Power Down (DISPWRDN): Setting this bit to 1 will block CKE high-)low
transitions. May be used by BIOS during init flow and should be set to 0 for functional
mode.
0 - The Memory Controller dynamically controls the CKE pins to place the DRAM device
in power down mode.
1 - The Memory Controller constantly drives the CKE pins high.
24
1h
RW
Clock Gating Disabled (CLKGTDIS): Setting this bit to 0 allows a large number of
internal Memory Controller clocks to be gated when there is no activity in order to save
power. When set to 1, internal clock-gating is disabled.
0 - Enable.
1 - Disable.
Note: This bit should be set to 0 for normal operation.
23
0h
RW
Dynamic Self-Refresh Enable (DYNSREN): Setting this bit to 1, enables automatic
SR command to DRAM and PM message to DDRIO when the PRI bus is idle, all pending
requests have been served and the and PRI status is less than 2, SREDLY has timed-out,
and all JEDEC requirements are satisfied. This register may be changed by BIOS/FW onthe-fly.
22
0h
RO
Rsvd_30: Reserved
21
0h
RW
Close All Pages before Power-Down (PREAPWDEN): Send Precharge All Command
to a Rank before PD-Enter. Setting this bit to 1 will allow sending a PREA command
before PDE command.
0 - Disable.
1 - Enable.
20
0h
RW
Wake Allowed for Page Close Timeout (PCLSWKOK): Setting this bit to 1 indicates
the Memory Controller can send DRAM devices a PD-Exit command in order to close
single bank if the page timer expired. Note this bit applies only to cases where at least
one other bank in the same rank is open but not timed-out. If all banks in the rank
timed-out, a PD-Exit command will be sent regardless of this bit. Must be set to 0 during
init/training mode.
0 - Disable.
1 - Enable.
19
0h
RO
Rsvd_29: Reserved
18:16
0h
RW
Page Close Timeout Period (PCLSTO): Specifies the time frame, in ns, from last
access to a DRAM page until that page may be scheduled for closing (by sending a PRE
command).
0h - Disable page close timer (init/training).
1h - Immediate page close.
2h - 30-60 ns to page close.
3h - 60-120 ns to page close.
4h - 120-240 ns to page close.
5h - 240-480 ns to page close.
6h - 480-960 ns to page close.
7h - 1-2 s to page close.
15:13
0h
RO
Rsvd_28: Reserved
12:8
0h
RO
Reserved (RSVD): Reserved.
Intel® Quark™ SoC X1000
Datasheet
246
November 2014
Document Number: 329676-004US
System Memory Controller—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW
Self-Refresh Entry delay (SREDLY): The delay, in core-clocks, between PRI idle (no
pending requests and PRI status is less than 2) and SR Entry when the Memory
Controller is in Dynamic SR mode.
7:0
13.4.8
DRAM Refresh Control (DRFC)—Offset 8h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 8h
Op Codes:
10h - Read, 11h - Write
Default: 00012CA7h
Bit
Range
0
0
0
0
Default &
Access
0
0
1
0
0
1
0
1
1
0
0
1
0
1
0
0
0
1
1
1
REFWMLO
0
4
REFWMHI
0
8
REFWMPNC
0
tREFI
0
12
Rsvd_34
0
REFCNTMAX
0
16
Rsvd_35
0
20
REFDBTCLR
0
24
Rsvd_36
0
28
REFSKWDIS
31
Field Name (ID): Description
0h
RO
Rsvd_36: Reserved
0h
RW
Clear Refresh Debit before Self Refresh Entry (REFDBTCLR): To ensure that the
Memory Controller sends enough REF commands to the DRAM, it calculates tREFI period
with 2% less than the JEDEC tREFI value. So instead of tREFI equaling 7.8us, it's 7.6us,
which means over 1000 x tREFI interval, the Memory Controller would have sent 20 REF
commands more than required by the JEDEC spec. When this bit is set to 1 and if the
Memory Controller was awake for at least 1000 x tREFI period and then enters Self
Refresh, the Memory Controller clears the refresh counter and enters Self Refresh
without having to send the accumulated REF commands, since it has already issued 20
more REF commands than required by JEDEC.
0h - Disabled.
1h - Enabled.
20
0h
RW
Disable Skewing of Refresh Counting between Ranks (REFSKWDIS): Each rank
has its own refresh counter. By default, incrementing these refresh counters are skewed
by 1/4 the tREFI period. Setting this bit to a 1 disables this feature and all refresh
counters will increment at the same time per tREFI period. Skewing the tREFI counters
can improve performance, since traffic to all ranks does not have to be block to perform
refresh.
0h - counters are updated per rank every tREFI.
1h - all counters are updated every tREFI.
19:18
0h
RO
Rsvd_35: Reserved
17:16
1h
RW
Refresh Max tREFI Interval (REFCNTMAX): The maximum interval between ant two
REF commands per rank. JEDEC allows a maximum of 9 x tREFI intervals.
0h - 6 x tREFI.
1h - 7 x tREFI.
2h - 8 x tREFI.
3h - Reserved.
Should not be changed after initial setting.
15
0h
RO
Rsvd_34: Reserved
31:22
21
November 2014
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Datasheet
247
Intel® Quark™ SoC X1000—System Memory Controller
Bit
Range
14:12
11:8
7:4
3:0
13.4.9
Default &
Access
Field Name (ID): Description
2h
RW
Refresh Period (tREFI): Specifies the average time between sending REF commands
to DRAM. The Memory Controller will guarantee that the average time is met, but
maintains a certain degree of flexibility in the exact REF scheduling in order to increase
overall performance.
0h - Refresh disabled
1h - Reserved for pre-silicon simulation.
2h - 3.9 s (Extended Temperature Range, 85-95 C)
3h - 7.8 s (Normal Temperature Range, 0-85 C)
Ch
RW
Refresh Panic Watermark (REFWMPNC): When the refresh debit counter, per rank,
is greater than this value, the Memory Controller will send a REF command even if there
are some pending requests and regardless of the PRI status level. See DDR3 spec for
Refresh Postponing/Pulling-In flexibility. May be changed to functional value after init
sequence. Value should be greater than, or equal, to REFWMHI.
0-6h - Reserved
7h - Postpone 2 REF commands.
8h - Postpone 3 REF commands.
9h - Postpone 4 REF commands.
Ah - Postpone 5 REF commands.
Bh - Postpone 6 REF commands.
Ch - Postpone 7 REF commands.
Dh - Postpone 8 REF commands.
E-Fh - Reserved.
Ah
RW
Refresh High Watermark (REFWMHI): When the refresh debit counter, per rank, is
greater than this value, the Memory Controller will send a REF command even if there
are some pending requests to the rank but not if the PRI status is equal to 3. See DDR3
spec for Refresh Postponing/Pulling-In flexibility. May be changed to functional value
after init sequence. Value should be greater than, or equal, to REFWMLO.
0-6h - Reserved
7h - Postpone 2 REF commands.
8h - Postpone 3 REF commands.
9h - Postpone 4 REF commands.
Ah - Postpone 5 REF commands.
Bh - Postpone 6 REF commands.
Ch - Postpone 7 REF commands.
Dh - Postpone 8 REF commands.
E-Fh - Reserved.
7h
RW
Refresh Low Watermark (REFWMLO): When the refresh debit counter, per rank, is
greater than this value, the Memory Controller will send a REF command only if there
are no pending requests to the rank and the PRI status is less than 3. See DDR3 spec
for Refresh Postponing/Pulling-In flexibility. May be changed to functional value after init
sequence.
0-6h - Reserved
7h - Postpone 2 REF commands.
8h - Postpone 3 REF commands.
9h - Postpone 4 REF commands.
Ah - Postpone 5 REF commands.
Bh - Postpone 6 REF commands.
Ch - Postpone 7 REF commands.
Dh - Postpone 8 REF commands.
E-Fh - Reserved.
DRAM Scheduler Control (DSCH)—Offset 9h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 9h
Op Codes:
10h - Read, 11h - Write
Default: 00071108h
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Datasheet
248
November 2014
Document Number: 329676-004US
System Memory Controller—Intel® Quark™ SoC X1000
0
0
0
0
0
0
Bit
Range
1
IPREQMAX
Default &
Access
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
Field Name (ID): Description
31:19
0h
RO
Rsvd_40: Reserved
18:16
7h
RW
In-Progress Request Queue Depth (IPREQMAX): Maximal number of In-Progress
Requests stored in the Memory Controller.
Number of pending requests = IPREQMAX+1; Value may be changed after init/training
when PRI is idle.
15:13
0h
RO
Rsvd_39: Reserved
12
1h
RW
Disable New Request Bypass (NEWBYPDIS): Setting this bit to 0 will allow a new
request to bypass the normal Memory Controller internal arbiter when there are no
pending commands.
0h - Enable New Request Bypass.
1h - Disable New Request Bypass.
11:10
0h
RO
Rsvd_38: Reserved
9
0h
RW
Out-of-Order Disabled when PRI status is 3 (OOOST3DIS): Valid only if OOODIS
is 0;
0 - Remain OOO if status goes up to 3
1 - Disable OOO if status goes to 3
May be changed after init/training flow.
8
1h
RW
Disable Out-of-Order (OOODIS): 0h - OOO enabled.
1h - OOO disabled.
Should be disabled during init/training and can be enabled for functional mode.
7:5
0h
RO
Rsvd_37: Reserved
08h
RW
Out-of-Order Aging Threshold (OOOAGETRH): Specifies the number of requests
that can be processed ahead of another request sitting in the In-Progress request
(IPreq) queue before OOO is disabled. Once this threshold is met for any request sitting
in the IPreq queue, OOO is disabled until the aged request is processed. This
mechanism prevents starvation of pending requests in the IPreq queue. Each request
sitting in the IPreq queue has its own age timer. OOOAGETRH sets the default value of
an age timer when a request is loaded into the IPreq queue.
4:0
13.4.10
1
0
OOOAGETRH
0
4
Rsvd_37
0
8
OOODIS
0
12
OOOST3DIS
0
16
Rsvd_38
0
20
NEWBYPDIS
0
24
Rsvd_40
0
28
Rsvd_39
31
DRAM Calibration Control (DCAL)—Offset Ah
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + Ah
Op Codes:
10h - Read, 11h - Write
Default: 00001300h
November 2014
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Datasheet
249
Intel® Quark™ SoC X1000—System Memory Controller
0
0
0
0
0
0
0
0
0
16
0
0
0
0
12
0
0
Bit
Range
0h
RO
13:12
1h
RW/P
13.4.11
1
1
0
0
0
0
0
0
0
0
Field Name (ID): Description
Rsvd_42: Reserved
ZQ Calibration Short Interval (ZQCINT): The time interval, in ms, between ZQCS
commands to a DRAM device. ZQCS commands are sent to a single DRAM device and
commands are distributed and non-overlapping in the interval.
0h - Disabled.
1h - 62s (for pre-silicon simulation only)
2h - 31ms.
3h - 63ms.
4h - 126ms.
5-7h - Reserved.
May be changed on-the-fly in response to thermal events.
0h
RO
7:0
0
0
ZQ Calibration Long (SRXZQCL): Issued After SR Exit Control
0h - ZQCL commands after SRX are sent in parallel.
1h - ZQCL commands are sent serially to ranks.
2h - No ZQCL is sent after SR Exit. (Debug only).
3h Reserved.
3h
RW/P
10:8
0
4
Rsvd_43: Reserved
0h
RO
11
1
SRXZQCL
Default &
Access
31:14
0
8
Rsvd_41
0
20
ZQCINT
0
24
Rsvd_43
0
28
Rsvd_42
31
Rsvd_41: Reserved
DRAM Reset Management Control (DRMC)—Offset Bh
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + Bh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:17
0h
RO
Rsvd_46: Reserved
16
0h
RW
Cold Wake (COLDWAKE): BIOS should set this bit to 1 before sending WAKE
command to Memory Controller after Cold Reset. For S3 Exit, or any other mode in
which the DRAM is in SR, this bit must be set to 0.
Intel® Quark™ SoC X1000
Datasheet
250
0
CKEVAL
0
0
Rsvd0_DRMC
0
CKEMODE
0
4
Rsvd_44
0
8
ODTVAL
0
12
Rsvd1_DRMC
0
16
ODTMODE
0
20
Rsvd_45
0
24
Rsvd_46
0
28
COLDWAKE
31
November 2014
Document Number: 329676-004US
System Memory Controller—Intel® Quark™ SoC X1000
Bit
Range
13.4.12
Default &
Access
Field Name (ID): Description
15:13
0h
RO
Rsvd_45: Reserved
12
0h
RW
ODT Control Mode (ODTMODE): 0 - Memory Controller auto controls the ODT pins
based on DRAM Write transactions.
1 - The value of ODTVAL above directly controls the ODT pins.
11:10
0h
RO
Rsvd1_DRMC: Reserved
9:8
0h
RW
ODT Control Value (ODTVAL): When ODTMODE is set to 1, ODT pins to DRAM are
overridden by ODTVAL. Used only during init flow by BIOS.
7:5
0h
RO
Rsvd_44: Reserved
4
0h
RW
CKE Control Mode (CKEMODE): 0 - Memory Controller auto controls the CKE pins
based on Power-Down and Self Refresh entry and exit
. 1 - The value of CKEVAL directly controls the CKE pins
3:2
0h
RO
Rsvd0_DRMC: Reserved
1:0
0h
RW
CKE Control Value (CKEVAL): When CKEMODE is set to 1, CKE pins to DRAM are
overridden by CKEVAL. Used only during init flow by BIOS.
Power Management Status (PMSTS)—Offset Ch
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + Ch
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
0
16
0
Bit
Range
Default &
Access
31:9
8
7:1
0
0h
RO
0h
RW/P
0h
RO
0h
RW/P
November 2014
Document Number: 329676-004US
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DISR
0
20
Rsvd_47
0
24
Rsvd_48
0
28
WRO
31
Field Name (ID): Description
Rsvd_48: Reserved
Warm Reset Occurred (WRO): The Remote Management Unit writes a 1 to this bit to
indicate to BIOS a warm reset has just occurred. Can write a 0 to clear it. This is also
cleared when powergood = 0. This bit will not clear with reset
Rsvd_47: Reserved
DRAM In Self-Refresh Status (DISR): The Memory Controller sets this bit to a 1
after it has placed the DRAM devices in Self Refresh mode. The Memory Controller clears
this bit when it brings the DRAM devices out of Self Refresh mode. Writing a 1 to this bit,
when the COLDWAKE bit is set to 0, will also clear it. This will not clear with system
reset, but will clear when powergood = 0.
0 - DRAM not guaranteed to be in Self-Refresh.
1 - DRAM in Self-Refresh
Intel® Quark™ SoC X1000
Datasheet
251
Intel® Quark™ SoC X1000—System Memory Controller
13.4.13
DRAM Control Operation (DCO)—Offset Fh
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + Fh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Field Name (ID): Description
31
0h
RW
Memory Controller Initialization Complete (IC): Indicates that initialization of the
Memory Controller has completed. Memory accesses are permitted and maintenance
operation begins. Until this bit is set to a 1, the memory controller will not accept DRAM
requests from the Memory Manager or the MTE.
Note: Set this bit to 1 only when all other Memory Controller registers has been
configured. Usually set at the last configuration step.
30
0h
RO
DDRIO PHY initialization complete (DIOIC): Status indication that DDRIO
initialization is complete.
29
0h
RW
Disable PRI interface (PMIDIS): When this bit is set to 1, the Memory Controller will
not respond to requests from either the Memory Manager or the MTE.
Note: This bit should be set to 1, when issuing DRAM Read and Write commands
through message 68h. It prevents the Memory Controller trying to pull data from the
Memory Manager or the MTE for Writes through message 68h, and also prevents the
Memory Manager and the MTE from taking read data returned from Reads through
message 68h.
28
0h
RW
PRI Control Select (PMICTL): 0 - Memory Controller PRI is connected to Memory
Manager.
1 - Memory Controller PRI is connected to MTE.
When this bit is toggled, the Memory Controller will flush all pending DRAM requests
from the previous unit before taking requests from the new unit
27:9
0h
RO
Rsvd_50: Reserved
8
7:1
0
13.4.14
0
12
DRPLOCK
PMICTL
Bit
Range
0
16
Rsvd_49
0
20
CPGCLOCK
0
24
Rsvd_50
0
PMIDIS
IC
0
28
DIOIC
31
0h
RW/P/L
0h
RO
0h
RW/P/L
MTE Lock (CPGCLOCK): After this bit is set to 1, the MTE is clock gated and locked
and cannot be used. CPGCLOCK can be set only once, and will only reset when
powergood = 0.
Rsvd_49: Reserved
DRP Register Lock (DRPLOCK): Write a 1 to this bit to lock the DRP and DTRC
registers, and to disable the ability to issues the DRAM Read and Write commands
through message 68h. Once locked, the DRP and DTRC registers cannot be written
again. Once set to 1, this bit can only be cleared when powergood = 0.
Sticky Scratchpad 0 (SSKPD0)—Offset 4Ah
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 4Ah
Op Codes:
10h - Read, 11h - Write
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Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
VAL
0
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW/P
General Purpose Scratchpad (VAL): May be used for BIOS for data storage. Value is
preserved in warm-reset.
31:0
13.4.15
Sticky Scratchpad 1 (SSKPD1)—Offset 4Bh
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 4Bh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
VAL
0
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW/P
General Purpose Scratchpad (VAL): May be used for BIOS for data storage. Value is
preserved in warm-reset.
31:0
13.4.16
DRAM ECC Control Register (DECCCTRL)—Offset 60h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 60h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:19
0h
RO
Rsvd_58: Reserved
18
0h
RO
Reserved (RSVD): Reserved.
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0
SBEEN
0
DBEEN
0
0
RSVD
0
4
SYNSEL
0
8
CLRSBECNT
0
12
RSVD
0
16
Rsvd_57
0
20
RSVD
0
24
Rsvd_58
0
28
ENCBGEN
31
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Intel® Quark™ SoC X1000—System Memory Controller
Bit
Range
13.4.17
Default &
Access
Field Name (ID): Description
17
0h
RW
Enable Generation of ECC Check Bits (ENCBGEN): 0 - Disable check bit generation.
1 - Enable check bit generation.
16
0b
RO
Rsvd_57: Reserved
15:8
00h
RO
Reserved (RSVD): Reserved.
7
00h
RW
Clear Single Bit Error Count (CLRSBECNT): Clear ECC Single Bit Error Count:
0 - allow single bit error count to increment.
1 - clear single bit error count.
6:5
00h
RW
Syndrome Select (SYNSEL): ECC Syndrome Bits Select for Observation: The
Syndrome Bits are generated from read data returned from DRAM and used to detect
ECC errors. Each 64 bits of read data is used to generate 8 Syndrome Bits. SYNSEL
selects which set of Syndrome Bits to mux to the DECCSTAT register for observation.
00 - Selects Syndrome Bits from read data [63:0].
01 - Selects Syndrome Bits from read data [127:64].
10 - Selects Syndrome Bits from read data [191:128].
11 - Selects Syndrome Bits from read data [255:192].
4:2
000h
RO
Reserved (RSVD): Reserved.
1
0h
RW
Double Bit Enable (DBEEN): Enable Double Bit Error Detect
0: disable double bit error detect.
1: enable double bit error detect.
0
0h
RW
Single Bit Enable (SBEEN): Enable Single Bit Error Detect and Correct
0: disable single bit error detect and correct.
1: enable single bit error detect and correct.
DRAM ECC Status (DECCSTAT)—Offset 61h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 61h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
13.4.18
Default &
Access
4
0
0
0
0
0
0
0
0
0
ECCSYN
Rsvd_59
0
28
Field Name (ID): Description
31:8
0h
RO
Rsvd_59: Reserved
7:0
0h
RO
ECC Syndrome Bits (ECCSYN): This is the 8 ECC Syndrome Bits selected for
observation. Selection is made through the DECCCTRL register.
DRAM ECC Single Bit Error Count (DECCSBECNT)—Offset 62h
Access Method
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System Memory Controller—Intel® Quark™ SoC X1000
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 62h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
ECCSBECNT
0
28
Bit
Range
Default &
Access
0h
RO
31:0
13.4.19
Field Name (ID): Description
ECC Single Bit Error Count (ECCSBECNT): Write a 1 to the CLRSBECNT bit in the
DECCCTRL register to clear this register.
DRAM Single Bit ECC Error Captured Address (DECCSBECA)—
Offset 68h
Note: Write any value to this register to clear both this register and the DRAM Single
Bit ECC Error Captured Syndrome register
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 68h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
Bit
Range
0
0
0
Default &
Access
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
SBE_COL
0
20
SBE_ROW
0
24
SBE_BANK
0
SBE_RANK
RSVD
0
28
SBE_VLD
31
Field Name (ID): Description
31
0h
RO
30
0h
RO/P
Single Bit ECC Error Valid (SBE_VLD): 0 - No Single Bit ECC Error was detected.
1 - A Single Bit ECC Error was detected.
29
0h
RO/P
Captured Rank Address (SBE_RANK): Captured rank address of a read with a Single
Bit ECC Error
28:26
0h
RO/P
Captured Bank Address (SBE_BANK): Captured bank address of a read with a Single
Bit ECC Error
25:10
0h
RO/P
Captured Row Address (SBE_ROW): Captured row address of a read with a Single
Bit ECC Error
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Reserved (RSVD): Reserved.
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Intel® Quark™ SoC X1000—System Memory Controller
Bit
Range
Default &
Access
0h
RO/P
9:0
13.4.20
Field Name (ID): Description
Captured Column Address (SBE_COL): Captured column address of a read with a
Single Bit ECC Error
DRAM Single Bit ECC Error Captured Syndrome (DECCSBECS)—
Offset 69h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 69h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
SBE_SDROME
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RO/P
Captured Syndrome (SBE_SDROME): Captured syndrome of a read with a Single Bit
ECC Error
31:0
13.4.21
DRAM Double Bit ECC Error Captured Address (DECCDBECA)—
Offset 6Ah
Note: Write any value to this register to clear both this register and the DRAM Double
Bit ECC Error Captured Syndrome register
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 6Ah
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
Bit
Range
31
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0
0
0
Default &
Access
0h
RO
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DBE_COL
0
20
DBE_ROW
0
24
DBE_BANK
0
DBE_RANK
RSVD
0
28
DBE_VLD
31
Field Name (ID): Description
Reserved (RSVD): Reserved.
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System Memory Controller—Intel® Quark™ SoC X1000
Bit
Range
13.4.22
Default &
Access
Field Name (ID): Description
30
0h
RO/P
Double Bit ECC Error Valid (DBE_VLD): 0 - No Double Bit ECC Error was detected.
1 - A Double Bit ECC Error was detected.
29
0h
RO/P
Captured Rank Address (DBE_RANK): Captured rank address of a read with a
Double Bit ECC Error
28:26
0h
RO/P
Captured Bank Address (DBE_BANK): Captured bank address of a read with a
Double Bit ECC Error
25:10
0h
RO/P
Captured Row Address (DBE_ROW): Captured row address of a read with a Double
Bit ECC Error
9:0
0h
RO/P
Captured Column Address (DBE_COL): Captured column address of a read with a
Double Bit ECC Error
DRAM Double Bit ECC Error Captured Syndrome (DECCDBECS)—
Offset 6Bh
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 6Bh
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DBE_SDROME
0
28
Bit
Range
Default &
Access
0h
RO/P
31:0
13.4.23
Field Name (ID): Description
Captured Syndrome (DBE_SDROME): Captured syndrome of a read with a Double
Bit ECC Error
Memory Controller Fuse Status (DFUSESTAT)—Offset 70h
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 70h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
FUSESTAT
0
28
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Intel® Quark™ SoC X1000—System Memory Controller
Bit
Range
Default &
Access
Fuse Status (FUSESTAT): Memory Controller fuse bits are captured in this register.
[0] ECC Disable
[31:1] Reserved
0h
RO
31:0
13.4.24
Field Name (ID): Description
Scrambler Seed (DSCRMSEED)—Offset 80h
Dynamic data scrambler seed register
Access Method
Type: Message Bus Register
(Size: 32 bits)
Offset: [Port: 0x01] + 80h
Op Codes:
10h - Read, 11h - Write
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
Rsvd_71
0
28
Bit
Range
31:18
17:0
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Default &
Access
0h
RO
0h
RW/P
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
SCRMSEED
31
Field Name (ID): Description
Rsvd_71: Reserved
Scrambler Seed (SCRMSEED): Holds 18 bit scrambler seed value used to feed into
LFSR array matrix.
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System Memory Controller—Intel® Quark™ SoC X1000
13.5
Message Bus Commands
Table 78.
Message Opcode Definition
Opcode
Operation
Type
Description
00h
NOP
Msg
No operation
CAh
Wake
Msg
Wakes the memory from Self-Refresh mode or puts the
Memory Controller in working mode after cold-boot.
An ACK is sent after the Wake has completed and
memory is accessible.
MsgD
This message enables accessing the DRAM internal
registers.
Message Data Payload Bits:
31:23 Reserved (set to 0)
22 Rank Address
21:6 Multiplexed Address: Determines the value of
MA[15:0] when the initialization command is sent.
5:3 Bank Address: Determines the value of BA[2:0]
when the initialization command is sent.
2:0 Command (DDR3_RAS_B, DDR3_CAS_B,
DDR3_WE_B): Determines the value driven on
theDDR3_RAS_B, DDR3_CAS_B, and DDR3_WE_B
signals respectively when the initialization command is
sent. The supported commands are listed below:
000 – MRS (Extended) Mode Register Set
001 – Refresh
010 – Precharge (single or all as specified by MA[10])
011 – Bank Activate
100 – Reserved
101 – Reserved
110 – ZQ Calibration (Long/Short as specified by MA[10])
111 – NOP
68h
DRAM Init
§§
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Intel® Quark™ SoC X1000—System Memory Controller
Intel® Quark™ SoC X1000
Datasheet
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PCI Express* 2.0—Intel® Quark™ SoC X1000
14.0
PCI Express* 2.0
There are two lanes and two PCI Express* root ports, each supporting the PCI Express*
Base Specification, Rev. 2.0 at a maximum 2.5 GT/s signaling rate.
14.1
Signal Descriptions
Please see Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 83.
PCI Express* 2.0 Signals
Direction/
Type
Description
PCIE_PETP[1:0]
PCIE_PETN[1:0]
O
PCIe*
PCI Express* Transmit
PCI Express* Transmit pair (P and N) signals. Each pair makes up the
transmit half of a lane.
PCIE_PERP[1:0]
PCIE_PERN[1:0]
I
PCIe*
PCI Express* Receive
PCI Express* Receive pair (P and N) signals. Each pair makes up the
receive half of lane.
PCIE_IRCOMP
IO
Analog
Note: Please check the Platform Design Guide for connection details
for this COMP pin.
PCIE_RBIAS
I
Analog
Note: Please check the Platform Design Guide for connection details
for this BIAS pin.
Signal Name
Note: PCIe reference clocks are supplied by the following:
REF[0/1]_OUTCLKP
REF[0/1]_OUTCLKN
14.2
Features
• Conforms to PCI Express* Base Specification, Rev. 2.0
• 2.5 GT/s operation per root port (limited for power saving)
• Virtual Channel support for VC0
• x1 widths
• Supports 2 x1 Root port configurations
• Interrupts and Events
— Legacy (INTx) and MSI Interrupts
— General Purpose Events
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Intel® Quark™ SoC X1000—PCI Express* 2.0
— Express Card Hot Plug Events
— System Error Events
• Power Management
— Link State support for L0s, L1, and L2
— Powered down in ACPI S3 state - L3
14.2.1
Interrupts and Events
A root port is capable of handling interrupts and events from an end point device. A
root port can also generate its own interrupts for some events, including power
management and hot plug events, and also including error events.
There are two interrupt types a root port receives from an end point device: INTx
(legacy), and MSI. MSIs are automatically passed upstream by the root port, just as
other memory writes would be. INTx messages are delivered to the Legacy Bridge’s
interrupt decoding and routing logic by the root port.
Events and interrupts that are handled by the root port are shown in Table 84, with the
possible interrupts they can deliver to the interrupt decoder/router.
Table 84.
Possible Interrupts Generated From Events/Packets
Packet/Event
Type
INTx
MSI
INTx
Packet
X
X
PM_PME
Packet
X
X
SERR
SCI
SMI
Power Management (PM)
Event
X
X
X
X
Hot Plug (HP)
Event
X
X
X
X
ERR_CORR
Packet
X
ERR_NONFATAL
Packet
X
ERR_FATAL
Packet
X
Internal Error
Event
X
VDM
Packet
GPE
X
Note:
Table 84 lists the possible interrupts and events generated based on packets received,
or events generated in the root port. Configuration is performed by the software to
enable the different interrupts as applicable.
Note:
GPE is reported as SCI by the root port.
14.2.1.1
Express Card Hot Plug Events
Express Card Hot Plug is available based on Presence Detection for each root port.
Note:
A full Hot Plug Controller is not implemented.
Presence detection occurs when a PCI Express* device is plugged in and power is
supplied. The physical layer detects the presence of the device, and the root port sets
the SLCTL_SLSTS.PDS and SLCTL_SLSTS.PDC bits.
When a device is removed and detected by the physical layer, the root port clears the
SLCTL_SLSTS.PDS bit, and sets the SLCTL_SLSTS.PDC bit.
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PCI Express* 2.0—Intel® Quark™ SoC X1000
Interrupts can be generated by the root port when a hot plug event occurs. A hot plug
event is defined as the transition of the SLCTL_SLSTS.PDC bit from 0 to 1. Software
can set the SLCTL_SLSTS.PDE and SLTCTL_SLSTS.HPE bits to allow hot plug events to
generate an interrupt.
If SLCTL_SLSTS.PDE and SLTCTL_SLSTS.HPE are both set, and SLCTL_STSTS.PDC
transitions from 0 to 1, an interrupt is generated.
14.2.1.2
System Error (SERR)
System Error events are supported by both internal and external sources. See the PCI
Express* Base Specification, Rev. 2.0 for details.
14.2.2
Power Management
Each root port’s link supports L0s, L1, and L2/3 link states per PCI Express* Base
Specification, Rev. 2.0. L2/3 is entered on entry to S3.
14.3
References
PCI Express* Base Specification, Rev. 2.0
14.4
Register Map
Each root port supports it’s own extended PCI bridge header in PCI configuration space.
These headers are located on PCI bus 0, device 23, functions 0-1 as shown below.
There are no other registers implemented by the root ports or their controller.
See Chapter 5.0, “Register Access Methods” for details on accessing different register
types.
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Figure 27.
PCI Express Register Map
PCI Space
CPU
Core
Host Bridge
D:0,F:0
PCI
CAM
(I/O)
Bus 0
PCI
ECAM
(Mem)
I2C*/GPIOF:2
PCIe*
D:23
SPI1 F:1
IO Fabric
D:21
SPI0 F:0
RP0 F:0
PCI Express*
PCI Bridge
Headers
D:23,F:0-1
RP0 F:1
Legacy Bridge
D:31, F:0
SDIO/eMMC F:0
HSUART0 F:1
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
MAC0 F:6
MAC1 F:7
14.5
PCI Configuration Registers
Registers listed are for Function 0 (Root Port 0). Function 1 (Root Port 1) contains the
same registers. Differences between Root Ports are noted in the individual registers.
Table 85.
Offset
Start
Summary of PCI Configuration Registers—0/23/0
Offset End
Register Name (Register Symbol)
Default
Value
0h
3h
“Identifiers (ID)—Offset 0h” on page 266
11C38086h
4h
7h
“Primary Status (CMD_PSTS)—Offset 4h” on page 266
00100000h
8h
Bh
“Class Code (RID_CC)—Offset 8h” on page 268
06040000h
Ch
Fh
“Header Type (CLS_PLT_HTYPE)—Offset Ch” on page 268
00810000h
18h
1Bh
“Secondary Latency Timer (BNUM_SLT)—Offset 18h” on page 269
00000000h
1Ch
1Fh
“Secondary Status (IOBL_SSTS)—Offset 1Ch” on page 269
00000000h
20h
23h
“Memory Base and Limit (MBL)—Offset 20h” on page 270
00000000h
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PCI Express* 2.0—Intel® Quark™ SoC X1000
Table 85.
Offset
Start
Summary of PCI Configuration Registers—0/23/0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
24h
27h
“Prefetchable Memory Base and Limit (PMBL)—Offset 24h” on page 271
00010001h
28h
2Bh
“Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h” on page 271
00000000h
2Ch
2Fh
“Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch” on page 272
00000000h
34h
37h
“Capabilities List Pointer (CAPP)—Offset 34h” on page 272
00000040h
3Ch
3Fh
“Bridge Control (INTR_BCTRL)—Offset 3Ch” on page 273
00000000h
40h
43h
“PCI Express Capabilities (CLIST_XCAP)—Offset 40h” on page 274
00428010h
44h
47h
“Device Capabilities (DCAP)—Offset 44h” on page 275
00008000h
48h
4Bh
“Device Status (DCTL_DSTS)—Offset 48h” on page 276
00100000h
4Ch
4Fh
“Link Capabilities (LCAP)—Offset 4Ch” on page 277
00110C01h
50h
53h
“Link Status (LCTL_LSTS)—Offset 50h” on page 279
10010000h
54h
57h
“Slot Capabilities (SLCAP)—Offset 54h” on page 280
00040060h
58h
5Bh
“Slot Status (SLCTL_SLSTS)—Offset 58h” on page 281
00000000h
5Ch
5Fh
“Root Control (RCTL)—Offset 5Ch” on page 283
00000000h
60h
63h
“Root Status (RSTS)—Offset 60h” on page 283
00000000h
64h
67h
“Device Capabilities 2 (DCAP2)—Offset 64h” on page 284
00000016h
68h
6Bh
“Device Status 2 (DCTL2_DSTS2)—Offset 68h” on page 285
00000000h
6Ch
6Fh
“Link Capability 2 (LCAP2)—Offset 6Ch” on page 286
00000000h
70h
73h
“Link Status 2 (LCTL2_LSTS2)—Offset 70h” on page 286
00000001h
74h
77h
“Slot Capabilities 2 (SLCAP2)—Offset 74h” on page 288
00000000h
78h
7Bh
“Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h” on page 288
00000000h
80h
83h
“Message Signaled Interrupt Message Control (MID_MC)—Offset 80h” on page 289
00009005h
84h
87h
“Message Signaled Interrupt Message Address (MA)—Offset 84h” on page 289
00000000h
88h
8Bh
“Message Signaled Interrupt Message Data (MD)—Offset 88h” on page 290
00000000h
90h
93h
“Subsystem Vendor Capability (SVCAP)—Offset 90h” on page 290
0000A00Dh
94h
97h
“Subsystem Vendor IDs (SVID)—Offset 94h” on page 291
00000000h
A0h
A3h
“PCI Power Management Capabilities (PMCAP_PMC)—Offset A0h” on page 291
C8020001h
A4h
A7h
“PCI Power Management Control And Status (PMCS)—Offset A4h” on page 292
00000000h
D0h
D3h
“Channel Configuration (CCFG)—Offset D0h” on page 293
01000000h
D4h
D7h
“Miscellaneous Port Configuration 2 (MPC2)—Offset D4h” on page 294
00000000h
D8h
DBh
“Miscellaneous Port Configuration (MPC)—Offset D8h” on page 295
01110000h
DCh
DFh
“SMI / SCI Status (SMSCS)—Offset DCh” on page 296
00000000h
F4h
F7h
“Message Bus Control (PHYCTL_PHYCTL2_IOSFSBCTL)—Offset F4h” on page 297
000C3043h
100h
103h
“Advanced Error Reporting Capability Header (AECH)—Offset 100h” on page 298
00000000h
104h
107h
“Uncorrectable Error Status (UES)—Offset 104h” on page 299
00000000h
108h
10Bh
“Uncorrectable Error Mask (UEM)—Offset 108h” on page 300
00000000h
10Ch
10Fh
“Uncorrectable Error Severity (UEV)—Offset 10Ch” on page 301
00060011h
110h
113h
“Correctable Error Status (CES)—Offset 110h” on page 302
00000000h
114h
117h
“Correctable Error Mask (CEM)—Offset 114h” on page 303
00002000h
118h
11Bh
“Advanced Error Capabilities and Control (AECC)—Offset 118h” on page 304
00000000h
11Ch
11Fh
“Header Log (HL_DW1)—Offset 11Ch” on page 304
00000000h
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Table 85.
Offset
Start
Summary of PCI Configuration Registers—0/23/0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
120h
123h
“Header Log (HL_DW2)—Offset 120h” on page 305
00000000h
124h
127h
“Header Log (HL_DW3)—Offset 124h” on page 305
00000000h
128h
12Bh
“Header Log (HL_DW4)—Offset 128h” on page 305
00000000h
12Ch
12Fh
“Root Error Command (REC)—Offset 12Ch” on page 306
00000000h
130h
133h
“Root Error Status (RES)—Offset 130h” on page 306
00000000h
134h
137h
“Error Source Identification (ESID)—Offset 134h” on page 307
00000000h
14.5.1
Identifiers (ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 0h
Power Well: Core
Default: 11C38086h
28
0
0
1
24
0
0
0
20
1
1
1
0
0
16
0
0
1
1
12
1
0
0
0
8
0
0
0
DID
0
Bit
Range
14.5.2
4
0
1
0
0
0
0
0
1
1
0
VID
31
Default &
Access
Field Name (ID): Description
31:16
11C3h
RO/V
Device Identification (DID): PCI Device ID
15:0
8086h
RO
Vendor Identification (VID): PCI Vendor ID
Primary Status (CMD_PSTS)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 4h
Power Well: Core
Default: 00100000h
31
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Default &
Access
0b
RWC
0
0
0
0
0
0
0
0
0
0
0
0
MSE
0
IOSE
0
SCE
0
0
BME
0
MWIE
0
PERE
0
VGA_PSE
IS
0
SEE
0
4
WCC
1
ID
0
8
FBE
0
12
RSVD
0
RSVD_2
0
PC66
0
CLIST
RTA
Bit
Range
0
RSVD_1
0
16
DPD
0
20
PFBC
0
PDTS
0
STA
24
SSE
DPE
0
28
RMA
31
Field Name (ID): Description
DPE Detected Parity Error (DPE): Set when the root port receives a command or
data from the backbone with a parity error. This is set even if PCMD.PERE is not set.
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
30
0b
RWC
Signaled System Error (SSE): Set when the root port signals a system error to the
internal SERR# logic.
29
0b
RWC
Received Master Abort (RMA): Set when the root port receives a completion with
unsupported request status from the backbone.
28
0b
RWC
Received Target Abort (RTA): Set when the root port receives a completion with
completer abort from the backbone.
27
0b
RWC
Signaled Target Abort (STA): Set whenever the root port forwards a target abort
received from the downstream device onto the backbone.
26:25
00b
RO
Primary DEVSEL# Timing Status (PDTS): Reserved per PCI-Express spec.
24
0b
RWC
Master Data Parity Error Detected (DPD): Set when the root port receives a
completion with a data parity error on the backbone and PCMD.PERE is set.
23
0b
RO
Primary Fast Back to Back Capable (PFBC): Reserved per PCI-Express spec.
22
0b
RO
Reserved (RSVD_1): Reserved.
21
0b
RO
Primary 66 MHz Capable (PC66): Reserved per PCI-Express spec.
20
1b
RO
Capabilities List (CLIST): Indicates the presence of a capabilities list.
19
0b
RO/V
Interrupt Status (IS): Indicates status of hot plug and power management interrupts
on the root port that result in INTx# message generation. This bit is not set if MSI is
enabled. If MSI is not enabled, this bit is set regardless of the state of CMD.ID.
18:16
000b
RO
Reserved (RSVD_2): Reserved.
15:11
00h
RO
10
0b
RW/RO
Reserved (RSVD): Reserved.
Interrupt Disable (ID): This disables pin-based INTx# interrupts on enabled hot plug
and power management events. This bit has no effect on MSI operation. When set,
internal INTx# messages will not be generated. When cleared, internal INTx# messages
are generated if there is an interrupt for hot plug or power management and MSI is not
enabled. This bit does not affect interrupt forwarding from devices connected to the root
port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal
interrupt controllers if this bit is set.
9
0b
RO
Fast Back to Back Enable (FBE): Reserved per PCI-Express spec.
8
0b
RW
SERR# Enable (SEE): When set, enables the root port to generate an SERR# message
when PSTS.SSE is set.
7
0b
RO
Wait Cycle Control (WCC): Reserved per PCI-Express spec.
6
0b
RW
Parity Error Response Enable (PERE): Indicates that the device is capable of
reporting parity errors as a master on the backbone.
5
0b
RO
VGA Palette Snoop (VGA_PSE): Reserved per PCI-Express spec.
4
0b
RO
Memory Write and Invalidate Enable (MWIE): Reserved per PCI-Express spec.
3
0b
RO
Special Cycle Enable (SCE): Reserved per PCI-Express and PCI bridge spec.
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
14.5.3
Default &
Access
Field Name (ID): Description
2
0b
RW
Bus Master Enable (BME): When set, allows the root port to forward Memory and I/O
Read/Write cycles onto the backbone from a PCI-Express device. When this bit is 0b,
Memory and I/O requests received at a Root Port must be handled as Unsupported
Requests (UR). This bit does not affect forwarding of Completions in either the Upstream
or Downstream direction. The forwarding of Requests other than Memory or I/O
requests is not controlled by this bit.
1
0b
RW
Memory Space Enable (MSE): When set, memory cycles within the range specified by
the memory base and limit registers can be forwarded to the PCI-Express device. When
cleared, these memory cycles are master aborted on the backbone.
0
0b
RW
I/O Space Enable (IOSE): When set, I/O cycles within the range specified by the I/O
base and limit registers can be forwarded to the PCI-Express device. When cleared,
these cycles are master aborted on the backbone.
Class Code (RID_CC)—Offset 8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 8h
Power Well: Core
Default: 06040000h
0
0
24
0
1
1
0
20
0
0
0
Bit
Range
14.5.4
16
0
1
0
0
12
0
0
0
SCC
0
0
8
0
0
0
0
4
0
0
0
Default &
Access
0
0
0
0
0
0
0
0
RID
28
0
BCC
0
PI
31
Field Name (ID): Description
31:24
06h
RO
23:16
04h
RO/V
Sub-Class Code (SCC): The default indicates the device is a PCI-to-PCI bridge.
15:8
00h
RO/V
Programming Interface (PI): This is a read only register.
7:0
00h
RO/V
Revision ID (RID): Indicates the revision of the bridge.
Base Class Code (BCC): Indicates the device is a bridge device.
Header Type (CLS_PLT_HTYPE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + Ch
Default: 00810000h
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268
0
0
0
20
1
0
0
0
16
0
0
0
1
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
LS
24
0
RSVD
0
CT
0
HTYPE
28
0
RSVD0
0
MFD
31
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
31:24
0b
RO
RSVD0: Reserved
23
1b
RO
Multi-function Device (MFD): This bit is '1' to indicate a multi-function device.
22:16
01h
RO/V
15:11
00h
RO
Header Type (HTYPE): The default mode identifies the header layout of the
configuration space, which is a PCI-to-PCI bridge.
Latency Count (CT): Reserved per PCI-Express spec.
000b
RO
10:8
Reserved (RSVD): Reserved.
00h
RW
7:0
14.5.5
Field Name (ID): Description
Line Size (LS): This is read/write but contains no functionality, per PCI-Express spec.
Secondary Latency Timer (BNUM_SLT)—Offset 18h
This register is reserved for a root port per PCI-Express spec.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 18h
Power Well: Core
Default: 00000000h
0
0
0
0
0
0
0
Bit
Range
14.5.6
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
PBN
0
20
SCBN
0
24
SLT
0
28
SBBN
31
Default &
Access
Field Name (ID): Description
31:24
00h
RW/RO
Secondary Latency Timer (SLT): This register is RO and returns 0. This register does
not affect the behavior of any HW logic.
23:16
00h
RW
Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below the
bridge.
15:8
00h
RW
Secondary Bus Number (SCBN): Indicates the bus number the port.
7:0
00h
RW
Primary Bus Number (PBN): Indicates the bus number of the backbone.
Secondary Status (IOBL_SSTS)—Offset 1Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 1Ch
Power Well: Core
Default: 00000000h
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOBC
0
4
IOBA
0
8
IOLC
0
12
IOLA
0
16
RSVD_1
0
SC66
RTA
STA
0
RSVD
0
DPD
0
20
SFBC
0
SDTS
0
Bit
Range
14.5.7
24
RSE
DPE
0
28
RMA
31
Field Name (ID): Description
31
0b
RWC
Detected Parity Error (DPE): Set when the port receives a poisoned TLP.
30
0b
RWC
Received System Error (RSE): Set when the port receives an ERR_FATAL or
ERR_NONFATAL message from the device.
29
0b
RWC
Received Master Abort (RMA): Set when the port receives a completion with
Unsupported Request status from the device.
28
0b
RWC
Received Target Abort (RTA): Set when the port receives a completion with
Completion Abort status from the device.
27
0b
RWC
Signaled Target Abort (STA): Set when the port generates a completion with
Completion Abort status to the device.
26:25
00b
RO/V
Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI-Express spec.
24
0b
RWC
Data Parity Error Detected (DPD): Set when the BCTRL.PERE, and either of the
following two conditions occurs:
Port receives completion marked poisoned.
Port poisons a write request to the secondary side.
23
0b
RO/V
Secondary Fast Back to Back Capable (SFBC): Reserved per PCI-Express spec.
22
0b
RO
Reserved (RSVD): Reserved.
21
0b
RO
Secondary 66 MHz Capable (SC66): Reserved per PCI Express spec.
20:16
00h
RO
Reserved (RSVD_1): Reserved.
15:12
0h
RW
I/O Address Limit (IOLA): I/O Base bits corresponding to address lines 15:12 for
4KB alignment. Bits 11:0 are assumed to be padded to FFFh.
11:8
0h
RO
I/O Limit Address Capability (IOLC): Indicates that the bridge does not support 32bit I/O addressing.
7:4
0h
RW
I/O Base Address (IOBA): I/O Base bits corresponding to address lines 15:12 for
4KB alignment. Bits 11:0 are assumed to be padded to 000h.
3:0
0h
RO
I/O Base Address Capability (IOBC): Indicates that the bridge does not support 32bit I/O addressing.
Memory Base and Limit (MBL)—Offset 20h
Accesses that are within the ranges specified in this register will be sent to the attached
device if CMD.MSE is set. Accesses from the attached device that are outside the
ranges specified will be forwarded to the backbone if CMD.BME is set.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 20h
Power Well: Core
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November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Default: 00000000h
0
24
0
0
0
0
20
0
0
0
0
16
0
Bit
Range
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Default &
Access
Field Name (ID): Description
31:20
000h
RW
Memory Limit (ML): These bits are compared with bits 31:20 of the incoming address
to determine the upper 1MB aligned value of the range.
19:16
0h
RO
Reserved (RSVD): Reserved.
000h
RW
15:4
Memory Base (MB): These bits are compared with bits 31:20 of the incoming address
to determine the lower 1MB aligned value of the range.
0h
RO
3:0
14.5.8
0
RSVD_1
0
MB
28
0
ML
0
RSVD
31
Reserved (RSVD_1): Reserved.
Prefetchable Memory Base and Limit (PMBL)—Offset 24h
Accesses that are within the ranges specified in this register will be sent to the device if
CMD.MSE is set. Accesses from the device that are outside the ranges specified will be
forwarded to the backbone if CMD.BME is set.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 24h
Power Well: Core
Default: 00010001h
0
0
0
0
Bit
Range
31:20
000h
RW
19:16
1h
RO
15:4
3:0
14.5.9
Default &
Access
000h
RW
1h
RO
0
0
0
0
0
16
0
0
0
1
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
1
I64B
0
20
PMB
0
24
PML
0
28
I64L
31
Field Name (ID): Description
Prefetchable Memory Limit (PML): These bits are compared with bits 31:20 of the
incoming address to determine the upper 1MB aligned value of the range.
64-bit Indicator (I64L): Indicates support for 64-bit addressing.
Prefetchable Memory Base (PMB): These bits are compared with bits 31:20 of the
incoming address to determine the lower 1MB aligned value of the range.
64-bit Indicator (I64B): Indicates support for 64-bit addressing.
Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h
Access Method
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Datasheet
271
Intel® Quark™ SoC X1000—PCI Express* 2.0
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 28h
Power Well: Core
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
PMBU
0
28
Bit
Range
31:0
14.5.10
Default &
Access
Field Name (ID): Description
00000000h Prefetchable Memory Base Upper Portion (PMBU): Upper 32-bits of the
prefetchable address base.
RW
Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 2Ch
Power Well: Core
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
PMLU
0
28
Bit
Range
31:0
14.5.11
Default &
Access
Field Name (ID): Description
00000000h Prefetchable Memory Limit Upper Portion (PMLU): Upper 32-bits of the
prefetchable address limit.
RW
Capabilities List Pointer (CAPP)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 34h
Power Well: Core
Default: 00000040h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
RSVD1
0
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Datasheet
272
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
1
0
0
0
0
PTR
31
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
31:8
Default &
Access
0000000h
Reserved (RSVD1): Reserved
RO
Capabilities Pointer (PTR): Indicates that the pointer for the first entry in the
capabilities list.
BIOS can determine which capabilities will be exposed by including or removing them
from the capability linked list.
As this register is RWO, BIOS must write a value to this register, even if it is to re-write
the default value.
Capability Linked List (Default Settings)
Offset Capability Next Pointer
40h PCI Express 80h
80h Message Signaled Interrupt (MSI) 90h
90h Subsystem Vendor A0h
A0h PCI Power Management 00h
Extended PCIe Capability Linked List
Offset Capability Next Pointer
100h Advanced Error Reporting 000h
40h
RWO
7:0
14.5.12
Field Name (ID): Description
Bridge Control (INTR_BCTRL)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 3Ch
Power Well: Core
Default: 00000000h
Bit
Range
31:28
0
V16
VE
Default &
Access
0h
RO
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Field Name (ID): Description
Reserved (RSVD): Reserved.
27
0b
RO/RW
26
0b
RO
25
0b
RO/RW
Secondary Discard Timer (SDT): Reserved per PCI-Express spec.
24
0b
RO/RW
Primary Discard Timer (PDT): Reserved per PCI-Express spec.
23
0b
RO
Fast Back to Back Enable (FBE): Reserved per Express spec.
22
0b
RW
Secondary Bus Reset (SBR): Triggers a Hot Reset on the PCI-Express port.
21
0b
RO/RW
November 2014
Document Number: 329676-004US
0
ILINE
0
IPIN
0
PERE
0
IE
0
SE
0
MAM
16
0
FBE
20
0
SBR
24
0
DTSE
0
PDT
0
DTS
28
0
RSVD
0
SDT
31
Discard Timer SERR# Enable (DTSE): Reserved per PCI-Express spec.
Discard Timer Status (DTS): Reserved per PCI-Express spec.
Master Abort Mode (MAM): Reserved per PCI-Express spec.
Intel® Quark™ SoC X1000
Datasheet
273
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
20
0b
RW
VGA 16-Bit Decode (V16): When set, indicates that the I/O aliases of the VGA range
(see BCTRL.VE definition below), are not enabled, and only the base I/O ranges can be
decoded.
0: Execute 10-bit address decode on VGA I/O accesses.
1: Execute 16-bit address decode on VGA I/O accesses.
19
0b
RW
VGA Enable (VE): When set, the following ranges will be claimed off the backbone by
the root port:
Memory ranges A0000h-BFFFFh
I/O ranges 3B0h-3BBh and 3C0h-3DFh, and all aliases of bits 15:10 in any combination
of 1's
18
0b
RW
ISA Enable (IE): This bit only applies to I/O addresses that are enabled by the I/O
Base and I/O Limit registers and are in the first 64KB of PCI I/O space. If this bit is set,
the root port will block any forwarding from the backbone to the device of I/O
transactions addressing the last 768 bytes in each 1KB block (offsets 100h to 3FFh).
17
0b
RW
SERR# Enable (SE): When set, ERR_COR, ERR_NONFATAL, and ERR_FATAL messages
received are forwarded to the backbone. When cleared, they are not.
16
0b
RW
Parity Error Response Enable (PERE): When set, poisoned write TLPs and
completions indicating poisoned TLPs will set the SSTS.DPD.
00h
RO/V
15:8
00h
RW
7:0
14.5.13
Interrupt Pin (IPIN): Indicates the interrupt pin driven by the root port. At reset, this
register takes on the following values, which reflect the reset state of the D28IP register
in chipset config space:
Port Bits(15:12) Bits(11:08)
1 0h D28IP.P1IP
2 0h D28IP.P2IP
3 0h D28IP.P3IP
4 0h D28IP.P4IP
5 0h D28IP.P5IP
6 0h D28IP.P6IP
7 0h D28IP.P7IP
8 0h D28IP.P8IP
The value that is programmed into D28IP is always reflected in this register.
Interrupt Line (ILINE): Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
PCI Express Capabilities (CLIST_XCAP)—Offset 40h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 40h
Power Well: Core
Default: 00428010h
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
274
0
Default &
Access
0
0
1
0
0
0
0
1
0
1
0
0
0
8
0
0
0
0
4
0
0
0
1
0
0
0
0
0
CID
0
12
NEXT
0
16
CV
0
20
DT
0
24
IMN
RSVD
0
RSVD_1
0
28
SI
31
Field Name (ID): Description
31
0b
RO
Reserved (RSVD): Reserved.
30
0b
RO
Reserved (RSVD_1): This register at one time was for TCS Routing but that was later
removed from the PCIe 2.0 spec.
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
14.5.14
Default &
Access
Field Name (ID): Description
29:25
00h
RO
Interrupt Message Number (IMN): The PCH does not have multiple MSI interrupt
numbers.
24
0b
RWO
Slot Implemented (SI): Indicates whether the root port is connected to a slot. Slot
support is platform specific. BIOS programs this field, and it is maintained until a
platform reset.
23:20
4h
RO
Device / Port Type (DT): Indicates this is a PCI-Express root port.
19:16
2h
RO
Capability Version (CV): Version 2.0 indicates devices compliant to the PCI Express
2.0 specification which incorporates the Register Expansion ECN.
15:8
80h
RWO
Next Capability (NEXT): Indicates the location of the next capability.
The default value of this register is 80h which points to the MSI Capability structure.
BIOS can determine which capabilities will be exposed by including or removing them
from the capability linked list. As this register is RWO, BIOS must write a value to this
register, even if it is to re-write the default value.
7:0
10h
RO
Capability ID (CID): Indicates this is a PCI Express capability.
Device Capabilities (DCAP)—Offset 44h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 44h
Power Well: Core
Default: 00008000h
Bit
Range
31:29
Default &
Access
000b
RO
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MPS
0
PFS
0
ETFS
0
4
E0AL
0
8
E1AL
0
RSVD_4
0
RSVD_3
0
12
RBER
0
16
RSVD_2
0
20
RSVD_1
0
24
CSPV
0
FLRC
0
RSVD
0
28
CSPS
31
Field Name (ID): Description
Reserved (RSVD): Reserved.
28
0b
RO
Function Level Reset Capable (FLRC): Not supported in Root Ports.
27:26
00b
RO
Captured Slot Power Limit Scale (CSPS): Not supported.
25:18
00h
RO
Captured Slot Power Limit Value (CSPV): Not supported.
17:16
00b
RO
Reserved (RSVD_1): Reserved.
15
1b
RO
Role Based Error Reporting (RBER): Indicates that this device implements the
functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 spec.
14
0b
RO
Reserved (RSVD_2): On previous version of the specification this was Power Indicator
Present (PIP).
13
0b
RO
Reserved (RSVD_3): On previous version of the specification this was Attention
Indicator Present (AIP).
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
275
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
0b
RO
12
14.5.15
Field Name (ID): Description
Reserved (RSVD_4): On previous version of the specification this was Attention
Button Present (ABP).
11:9
000b
RO
Endpoint L1 Acceptable Latency (E1AL): Reserved for Root port.
8:6
000b
RO
Endpoint L0 Acceptable Latency (E0AL): Reserved for Root port.
5
0b
RO
Extended Tag Field Supported (ETFS): The PCH root port never needs to initiate a
transaction as a Requester with the Extended Tag bits being set. This bit does not affect
the root port's ability to forward requests as a bridge as the root port always supports
forwarding requests with extended tags.
4:3
00b
RO
Phantom Functions Supported (PFS): No phantom functions supported.
2:0
000b
RO
Max Payload Size Supported (MPS): Indicates the maximum payload size supported
is 128B.
Device Status (DCTL_DSTS)—Offset 48h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 48h
Power Well: Core
Default: 00100000h
Bit
Range
31:22
Intel® Quark™ SoC X1000
Datasheet
276
Default &
Access
000h
RO
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CEE
0
NFE
0
FEE
12
0
URE
0
ERO
0
MPS
0
PFE
1
ETFE
16
0
ENS
0
APME
20
0
MRRS
0
CED
0
RSVD
0
FED
24
0
NFED
0
URD
0
TDP
28
0
RSVD_1
0
APD
31
Field Name (ID): Description
Reserved (RSVD_1): Reserved.
21
0b
RO
Transactions Pending (TDP): This bit has no meaning for the root port since it never
initiates a non-posted request with its own RequesterID.
20
1b
RO
AUX Power Detected (APD): The root port contains AUX power for wakeup.
19
0b
RWC
Unsupported Request Detected (URD): Indicates an unsupported request was
detected.
18
0b
RWC
Fatal Error Detected (FED): Indicates a fatal error was detected. Set when a fatal
error occurred from a data link protocol error, buffer overflow, or malformed TLP.
17
0b
RWC
Non-Fatal Error Detected (NFED): Indicates a non-fatal error was detected. Set
when received a non-fatal error occurred from a poisoned TLP, unexpected completions,
unsupported requests, completer abort, or completer timeout.
16
0b
RWC
Correctable Error Detected (CED): Indicates a correctable error was detected. Set
when received an internal correctable error from receiver errors / framing errors, TLP
CRC error, DLLP CRC error, replay number rollover, or replay timeout.
15
0b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
000b
RO
14:12
11
0b
RO
10
0b
RW/P
Max Read Request Size (MRRS): Hardwired to 0
Enable No Snoop (ENS): Not supported. The root port will never issue non-snoop
requests.
Aux Power PM Enable (APME): Must be RW for OS testing. The OS will set this bit to
'1' if the device connected has detected aux power. It has no effect on the root port
otherwise. This registers is in the resume well.
9
0b
RO
Phantom Functions Enable (PFE): Not supported.
8
0b
RO
Extended Tag Field Enable (ETFE): Not supported.
000b
RO
7:5
Max Payload Size (MPS): The root port only supports 128B payloads.
0b
RO
Enable Relaxed Ordering (ERO): Not supported.
3
0b
RW
Unsupported Request Reporting Enable (URE): When set, allows signaling
ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting
an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked
Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the
Root Control Register when an uncorrectable non-Advisory UR is received with the
severity set by the Uncorrectable Error Severity register.
2
0b
RW
Fatal Error Reporting Enable (FEE): Enables signaling of ERR_FATAL to the Root
Control register due to internally detected errors or error messages received across the
link. Other bits also control the full scope of related error reporting.
1
0b
RW
Non-Fatal Error Reporting Enable (NFE): When set, enables signaling of
ERR_NONFATAL to the Root Control register due to internally detected errors or error
messages received across the link. Other bits also control the full scope of related error
reporting.
0
0b
RW
Correctable Error Reporting Enable (CEE): When set, enables signaling of
ERR_CORR to the Root Control register due to internally detected errors or error
messages received across the link. Other bits also control the full scope of related error
reporting.
4
14.5.16
Field Name (ID): Description
Link Capabilities (LCAP)—Offset 4Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 4Ch
Power Well: Core
Default: 00110C01h
November 2014
Document Number: 329676-004US
16
0
1
0
0
0
1
12
0
0
0
0
8
1
1
0
0
4
0
0
0
0
0
0
0
0
1
SLS
0
MLW
20
0
APMS
0
EL0
0
EL1
0
CPM
24
0
LARC
0
SDERC
0
RSVD_1
28
0
PN
0
RSVD
31
Intel® Quark™ SoC X1000
Datasheet
277
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
00h
RO/V
Port Number (PN): Indicates the port number for the root port. This value is different
for each implemented port:
Port # Value of PN field
1 01h
2 02h
3 03h
4 04h
5 05h
6 06h
7 07h
8 08h
23:22
00b
RO
Reserved (RSVD): Reserved.
21
0b
RO
Reserved (RSVD_1): This port does not support Link Bandwidth Notification
Capability.
20
1b
RO
Link Active Reporting Capable (LARC): This port supports the optional capability of
reporting the DL_Active state of the Data Link Control and Management State Machine.
19
0b
RO
Surprise Down Error Reporting Capable (SDERC): Set to '0' to indicate the PCH
does not support Surprise Down Error Reporting.
18
0b
RO
Clock Power Management (CPM): '0' Indicates that PCH root ports do not support
the CLKREQ# mechanism.
17:15
010b
RWO
L1 Exit Latency (EL1): Indicates an exit latency of 2 s to 4 s.
000b Less than 1 s
001b 1 s to less than 2 s
010b 2 s to less than 4 s
011b 4 s to less than 8 s
100b 8 s to less than 16 s
101b 16 s to less than 32 s
110b 32 s to 64 s
111b More than 64 s
Note: If PXP PLL shutdown is enabled, BIOS should program this latency to comprehend
PLL lock latency.
14:12
000b
RO/V
L0s Exit Latency (EL0): Indicates an exit latency based upon common-clock
configuration:
LCAP.CCC Value
0 MPC.UCEL
1 MPC.CCEL
11b
RWO
Active State Link PM Support (APMS): Indicates the level of active state power
management on this link:
Bits Definition
00 (Reserved)
01 L0s Entry supported
10 Reserved
11 Both L0s and L1 supported
11:10
Intel® Quark™ SoC X1000
Datasheet
278
9:4
000000b
RO/V
Maximum Link Width (MLW): For the root ports, several values can be taken, based
upon the value of the chipset configuration register field RPC.PC1 for ports 1-4 and
RPC.PC2 for ports 5-6:
Port # Value of PN field
RPC.PC1 00 01 10 11
1 01h 02h 02h 04h
2 01h 01h 01h 01h
3 01h 01h 02h 01h
4 01h 01h 01h 01h
Port # Value of PN field
RPC.PC2 00 01 10 11
5 01h 02h 02h 04h
6 01h 01h 01h 01h
7 01h 01h 02h 01h
8 01h 01h 01h 01h
3:0
1h
RO/V
Supported Link Speeds (SLS): Indicates the supported link speeds of the Root Port.
0001b 2.5 GT/s Link speed supported
0010b 5.0 GT/s and 2.5GT/s Link speeds supported
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
14.5.17
Link Status (LCTL_LSTS)—Offset 50h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 50h
Power Well: Core
Default: 10010000h
Bit
Range
0
0
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
ASPM
0
RCBC
12
0
RSVD_1
1
RL
0
LD
0
ES
16
0
CCC
0
ECPM
0
HAWD
0
LABIE
20
0
LBMIE
0
RSVD
0
CLS
0
NLW
0
LT
1
RSVD_2
24
0
LA
28
0
SCC
LABS
0
LBMS
31
Default &
Access
Field Name (ID): Description
0b
RWC
Link Autonomous Bandwidth Status (LABS): This bit is Set by hardware to indicate
that hardware has autonomously changed Link speed or width, without the Port
transitioning through DL_Down status, for reasons other than to attempt to correct
unreliable Link operation.
This bit must be set if the Physical Layer reports a speed or width change was initiated
by the Downstream component that was indicated as an autonomous change.
The default value of this bit is 0b.
30
0b
RWC
Link Bandwidth Management Status (LBMS): This bit is Set by hardware to indicate
that either of the following has occurred without the Port transitioning through DL_Down
status:
* A Link retraining has completed following a write of 1b to the Retrain Link bit
Note: This bit is Set following any write of 1b to the Retrain Link bit, including when the
Link is in the process of retraining for some other reason.
* Hardware has changed Link speed or width to attempt to correct unreliable Link
operation, either through an LTSSM timeout or a higher level process
This bit must be set if the Physical Layer reports a speed or width change was initiated
by the Downstream component that was not indicated as an autonomous change.
The default value of this bit is 0b.
29
0b
RO/V
Link Active (LA): Set to 1b when the Data Link Control and Management State
Machine is in the DL_Active state, 0b otherwise.
28
1b
RO
Slot Clock Configuration (SCC): PCH uses the same reference clock as on the
platform and does not generate its own clock.
27
0b
RO/V
26
0b
RO
31
25:20
000000b
RO/V
November 2014
Document Number: 329676-004US
Link Training (LT): The root port sets this bit whenever link training is occurring, or
that 1b was written to the Retrain Link bit but Link training has not yet begun. It clears
the bit upon completion of link training.
Reserved (RSVD_2): Previously this was defined as Link Training Error (LTE) but
support for this bit was removed from subsequent versions of the PCI Express
specification.
Negotiated Link Width (NLW): For the root ports, this register could take on several
values:
Port # Value of PN field
RPC.PC1 00 01 10 11
1 01h 02h 02h 04h
2 01h 01h 01h 01h
3 01h 01h 02h 01h
4 01h 01h 01h 01h
Port # Value of PN field
RPC.PC2 00 01 10 11
5 01h 02h 02h 04h
6 01h 01h 01h 01h
7 01h 01h 02h 01h
8 01h 01h 01h 01h
The value of this register is undefined if the link has not successfully trained.
Intel® Quark™ SoC X1000
Datasheet
279
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
Current Link Speed (CLS): 0001b Link is 2.5 GT/s Link
0010b Link is 5.0 GT/s Link
The value of this field is undefined if the link is not up.
19:16
1h
RO/V
15:12
0h
RO
Reserved (RSVD): Reserved.
11
0b
RW
Link Autonomous Bandwidth Interrupt Enable (LABIE): When Set, this bit enables
the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status
bit has been Set.
10
0b
RW
Link Bandwidth Management Interrupt Enable (LBMIE): When Set, this bit
enables the generation of an interrupt to indicate that the Link Bandwidth Management
Status bit has been Set. This bit is not applicable and is reserved for Endpoints, PCI
Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches. Functions that do not
implement the Link Bandwidth Notification Capability must hardwire this bit to 0b.
Default value of this bit is 0b.
9
0b
RW
Hardware Autonomous Width Disable (HAWD): When Set, this bit disables
hardware from changing the Link width for reasons other than attempting to correct
unreliable Link operation by reducing Link width. Default value of this bit is 0b.
8
0b
RO
Enable Clock Power Management (ECPM): Reserved. Not supported on PCH Root
Ports.
7
0b
RW
Extended Synch (ES): When set, forces extended transmission of FTS ordered sets in
FTS and extra TS2 at exit from L1 prior to entering L0.
6
0b
RW
Common Clock Configuration (CCC): When set, indicates that the PCH and device
are operating with a distributed common reference clock.
5
0b
WO
Retrain Link (RL): When set, the root port will train its downstream link. This bit
always returns '0' when read. Software uses LSTS.LT and LSTS.LTE to check the status
of training. It is permitted to write 1b to this bit while simultaneously writing modified
values to other fields in this register. If the LTSSM is not already in Recovery or
Configuration, the resulting Link training must use the modified values. If the LTSSM is
already in Recovery or Configuration, the modified values are not required to affect the
Link training that's already in progress.
4
0b
RW
Link Disable (LD): When set, the root port will disable the link by directing the LTSSM
to the Disabled state.
3
0b
RO
Read Completion Boundary Control (RCBC): Indicates the read completion
boundary is 64 bytes.
2
0b
RO
Reserved (RSVD_1): Reserved.
00b
RW
Active State Link PM Control (ASPM): Indicates whether the root port should enter
L0s or L1 or both.
Bits Definition
00 Disabled
01 L0s Entry Enabled
10 L1 Entry Enabled
11 L0s and L1 Entry Enabled
The value of this register is used unless the Root Port ASPM Control Override Enable
register is set, in which case the Root Port ASPM Control Override value is used.
1:0
14.5.18
Field Name (ID): Description
Slot Capabilities (SLCAP)—Offset 54h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 54h
Power Well: Core
Default: 00040060h
Intel® Quark™ SoC X1000
Datasheet
280
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
14.5.19
Default &
Access
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
PCP
0
ABP
0
MSP
0
PIP
0
0
AIP
0
HPS
0
HPC
0
4
SLV__54_7_7
0
8
SLV__54_14_8
0
12
SLS
0
16
EMIP
0
20
NCCS
0
24
PSN__54_31_24
0
28
PSN__54_23_19
31
Field Name (ID): Description
31:24
00h
RWO
Physical Slot Number (PSN__54_31_24): This is a value that is unique to the slot
number. BIOS sets this field and it remains set until a platform reset.
23:19
00h
RWO
Physical Slot Number (PSN__54_23_19): This is a value that is unique to the slot
number. BIOS sets this field and it remains set until a platform reset.
18
1b
RO
No Command Completed Support (NCCS): Set to '1' as this port does not implement
a Hot Plug controller and can handle back-2-back writes to all fields of the slot control
register without delay between successive writes.
17
0b
RO
Electromechanical Interlock Present (EMIP): Set to 0 to indicate that no electromechanical interlock is implemented.
16:15
00b
RWO
Slot Power Limit Scale (SLS): Specifies the scale used for the slot power limit value.
BIOS sets this field and it remains set until a platform reset.
14:8
00h
RWO
Slot Power Limit Value (SLV__54_14_8): Specifies the upper limit (in conjunction
with SLS value), on the upper limit on power supplied by the slot. The two values
together indicate the amount of power in watts allowed for the slot. BIOS sets this field
and it remains set until a platform reset.
7
0b
RWO
Slot Power Limit Value (SLV__54_7_7): Specifies the upper limit (in conjunction
with SLS value), on the upper limit on power supplied by the slot. The two values
together indicate the amount of power in watts allowed for the slot. BIOS sets this field
and it remains set until a platform reset.
6
1b
RWO
Hot Plug Capable (HPC): When set, Indicates that hot plug is supported.
5
1b
RWO
Hot Plug Surprise (HPS): When set, indicates the device may be removed from the
slot without prior notification.
4
0b
RO
Power Indicator Present (PIP): Indicates that a power indicator LED is not present
for this slot.
3
0b
RO
Attention Indicator Present (AIP): Indicates that an attention indicator LED is not
present for this slot.
2
0b
RO
MRL Sensor Present (MSP): Indicates that an MRL sensor is not present.
1
0b
RO
Power Controller Present (PCP): Indicates that a power controller is not
implemented for this slot.
0
0b
RO
Attention Button Present (ABP): Indicates that an attention button is not
implemented for this slot.
Slot Status (SLCTL_SLSTS)—Offset 58h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 58h
Power Well: Core
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
281
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
PFE
0
ABE
0
PDE
0
MSE
0
HPE
0
0
CCE
0
4
AIC
0
PIC
0
PCC
0
EMIC
0
8
DLLSCE
0
RSVD
0
PFD
0
12
ABP
0
MSC
0
CC
0
16
PDC
0
MS
0
PDS
0
20
EMIS
0
24
RSVD_1
0
28
DLLSC
31
Field Name (ID): Description
31:25
00h
RO
Reserved (RSVD_1): Reserved.
24
0b
RWC
Data Link Layer State Changed (DLLSC): This bit is set when the value reported in
Data Link Layer Link Active field of the Link Status register is changed. In response to a
Data Link Layer State Changed event, software must read Data Link Layer Link Active
field of the Link Status register to determine if the link is active before initiating
configuration cycles to the hot plugged device.
23
0b
RO
Electromechanical Interlock Status (EMIS): Reserved as this port does not support
and electromechanical interlock.
22
0b
RO/V
Presence Detect State (PDS): If XCAP.SI is set (indicating that this root port spawns
a slot), then this bit indicates whether a device is connected ('1') or empty ('0'). If
XCAP.SI is cleared, this bit is a '1'.
21
0b
RO
MRL Sensor State (MS): Reserved as the MRL sensor is not implemented.
20
0b
RO
Command Completed (CC): This register is RO as this port does not implement a Hot
Plug Controller.
19
0b
RWC
18
0b
RO
MRL Sensor Changed (MSC): Reserved as the MRL sensor is not implemented.
17
0b
RO
Power Fault Detected (PFD): Reserved as a power controller is not implemented.
16
0b
RO
Attention Button Pressed (ABP): This register is RO as this port does not implement
an attention button.
15:13
Intel® Quark™ SoC X1000
Datasheet
282
000b
RO
Presence Detect Changed (PDC): This bit is set by the root port when the PD bit
changes state.
Reserved (RSVD): Reserved.
12
0b
RW
Data Link Layer State Changed Enable (DLLSCE): When set, this field enables
generation of a hot plug interrupt when the Data Link Layer Link Active field is changed.
11
0b
RO
Electromechanical Interlock Control (EMIC): Reserved as this port does not
support an Electromechanical Interlock.
10
0b
RO
Power Controller Control (PCC): This bit has no meaning for module based hot plug.
9:8
00b
RO
Power Indicator Control (PIC): This register is RO as this port does not implement a
Hot Plug Controller.
7:6
00b
RO
Attention Indicator Control (AIC): This register is RO as this port does not
implement a Hot Plug Controller.
5
0b
RW
Hot Plug Interrupt Enable (HPE): When set, enables generation of a hot plug
interrupt on enabled hot plug events.
4
0b
RO
Command Completed Interrupt Enable (CCE): This register is RO as this port does
not implement a Hot Plug Controller.
3
0b
RW
Presence Detect Changed Enable (PDE): When set, enables the generation of a hot
plug interrupt or wake message when the presence detect logic changes state.
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
14.5.20
Default &
Access
Field Name (ID): Description
2
0b
RO
MRL Sensor Changed Enable (MSE): This register is RO as this port does not
implement a Hot Plug Controller.
1
0b
RO
Power Fault Detected Enable (PFE): This register is RO as this port does not
implement a Hot Plug Controller.
0
0b
RO
Attention Button Pressed Enable (ABE): This register is RO as this port does not
implement a Hot Plug Controller.
Root Control (RCTL)—Offset 5Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 5Ch
Power Well: Core
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:16
15:4
14.5.21
12
0
0
0
0
0
0
0
RSVD
0
8
4
0
0
0
0
0
0
0
0
0
SCE
0
16
SNE
0
20
PIE
0
24
RSVD1
0
28
SFE
31
Field Name (ID): Description
00000h
RO
Reserved (RSVD1): Reserved
000h
RO
Reserved (RSVD): Reserved.
3
0b
RW
PME Interrupt Enable (PIE): When set, enables interrupt generation when RSTS.PS
is in a set state (either due to a '0' to '1' transition, or due to this bit being set with
RSTS.PS already set).
2
0b
RW
System Error on Fatal Error Enable (SFE): When set, an SERR# will be generated if
a fatal error is reported by any of the devices in the hierarchy of this root port, including
fatal errors in this root port. This register is not dependent on CMD.SEE being set.
1
0b
RW
System Error on Non-Fatal Error Enable (SNE): When set, an SERR# will be
generated if a non-fatal error is reported by any of the devices in the hierarchy of this
root port, including non-fatal errors in this root port. This register is not dependent on
CMD.SEE being set.
0
0b
RW
System Error on Correctable Error Enable (SCE): When set, an SERR# will be
generated if a correctable error is reported by any of the devices in the hierarchy of this
root port, including correctable errors in this root port. This register is not dependent on
CMD.SEE being set.
Root Status (RSTS)—Offset 60h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 60h
Power Well: Core
Default: 00000000h
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Intel® Quark™ SoC X1000—PCI Express* 2.0
0
0
0
0
0
0
0
0
0
16
0
0
Bit
Range
Default &
Access
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:18
0000h
RO
Reserved (RSVD): Reserved.
17
0b
RO/V
PME Pending (PP): Indicates another PME is pending when the PME status bit is set.
When the original PME is cleared by software, it will be set again, the requestor ID will
be updated, and this bit will be cleared. PCH root ports have a one deep PME pending
queue.
16
0b
RWC
PME Status (PS): Indicates that PME was asserted by the requestor ID in RID.
Subsequent PMEs are kept pending until this bit is cleared.
PME Requestor ID (RID): Indicates the PCI requestor ID of the last PME requestor.
Valid only when PS is set. PCH root ports are capable of storing the requester ID for two
PM_PME messages, with one active (this register) and a one deep pending queue.
Subsequent PM_PME messages will be dropped.
0000h
RO/V
15:0
14.5.22
0
12
RID
0
20
PP
0
24
RSVD
0
28
PS
31
Device Capabilities 2 (DCAP2)—Offset 64h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 64h
Power Well: Core
Default: 00000016h
0
0
0
0
0
0
0
0
0
16
0
0
0
0
12
0
Bit
Range
Default &
Access
31:12
00000h
RO
0
0
0
LTRMS
0
8
0
0
0
4
0
0
0
1
0
0
1
1
0
CTRS
0
20
CTDS
0
24
RSVD
0
28
RSVD_1
31
Field Name (ID): Description
Reserved (RSVD): Reserved.
11
0b
RWO
LTR Mechanism Supported (LTRMS): A value of 1b indicates support for the optional
Latency Tolerance Reporting (LTR) mechanism capability.
BIOS must write to this register with either a '1' or a '0' to enable/disable the root port
from declaring support for the LTR capability.
10:5
00h
RO
Reserved (RSVD_1): Reserved.
4
1b
RO
Completion Timeout Disable Supported (CTDS): A value of 1b indicates support for
the Completion Timeout Disable mechanism.
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Datasheet
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PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
6h
RO
Completion Timeout Ranges Supported (CTRS): This field indicates device support
for the optional Completion Timeout programmability mechanism. This mechanism
allows system software to modify the Completion Timeout value.
This field is applicable only to Root Ports, Endpoints that issue requests on their own
behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of requests issued on
PCI Express.
For all other devices this field is reserved and must be hardwired to 0000b.
Four time value ranges are defined:
Range A: 50us to 10ms
Range B: 10ms to 250ms
Range C: 250ms to 4s
Range D: 4s to 64s
Bits are set according to the table below to show timeout value ranges supported.
0000b Completion Timeout programming not supported.
0001b Range A
0010b Range B
0011b Ranges A and B
0110b Ranges B and C
0111b Ranges A, B and C
1110b Ranges B, C and D
1111b Ranges A, B, C and D
All other values are reserved.
3:0
14.5.23
Device Status 2 (DCTL2_DSTS2)—Offset 68h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 68h
Power Well: Core
Default: 00000000h
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
Bit
Range
Default &
Access
0
RSVD
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CTV
0
CTD
0
RSVD_1
28
0
RSVD_2
0
LTREN
31
Field Name (ID): Description
31:16
0000h
RO
15:11
00h
RO
Reserved (RSVD): Reserved.
10
0b
RW
LTR Mechanism Enable (LTREN): When Set to 1b, this bit enables the Latency
Tolerance Reporting (LTR) mechanism.
9:5
00h
RO
Reserved (RSVD_1): Reserved.
0b
RW
Completion Timeout Disable (CTD): When set to 1b, this bit disables the Completion
Timeout mechanism.
This field is required for all devices that support the Completion Timeout Disable
Capability.
Software is permitted to set or clear this bit at any time. When set, the Completion
Timeout detection mechanism is disabled.
If there are outstanding requests when the bit is cleared, it is permitted but not required
for hardware to apply the completion timeout mechanism to the outstanding requests. If
this is done, it is permitted to base the start time for each request on either the time
this bit was cleared or the time each request was issued.
Only the value from Port 1 (for ports 1-4) or Port 5 (for ports 5-8) is used.
4
November 2014
Document Number: 329676-004US
Reserved (RSVD_2): Reserved.
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Datasheet
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW
Completion Timeout Value (CTV): In Devices that support Completion Timeout
programmability, this field allows system software to modify the Completion Timeout
value. This field is applicable to Root Ports, Endpoints that issue requests on their own
behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of requests issued on
PCI Express. For all other devices this field is reserved and must be hardwired to 0000b.
A Device that does not support this optional capability must hardwire this field to 0000b
and is required to implement a timeout value in the range 50us to 50ms. Devices that
support Completion Timeout programmability must support the values given below
corresponding to the programmability ranges indicated in the Completion Timeout
Values Supported field.
The PCH targeted configurable ranges are listed below, along with the range allowed by
the PCI Express 2.0 specification.
Defined encodings:
0000b Default range: 40-50ms (spec range 50us to 50ms)
Values available if Range B (10ms to 250ms) programmability range is supported:
0101b 40-50ms (spec range is 16ms to 55ms)
0110b 160-170ms (spec range is 65ms to 210ms)
Values available if Range C (250ms to 4s) programmability range is supported:
1001b 400-500ms (spec range is 260ms to 900ms)
1010b 1.6-1.7s (spec range is 1s to 3.5s)
Values not defined above are Reserved.
Software is permitted to change the value in this field at any time. For requests already
pending when the Completion Timeout Value is changed, hardware is permitted to use
either the new or the old value for the outstanding requests, and is permitted to base
the start time for each request either on when this value was changed or on when each
request was issued.
3:0
14.5.24
Link Capability 2 (LCAP2)—Offset 6Ch
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 6Ch
Power Well: Core
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSVD
0
Bit
Range
31:0
14.5.25
Default &
Access
Field Name (ID): Description
00000000h
Reserved (RSVD): Reserved.
RO
Link Status 2 (LCTL2_LSTS2)—Offset 70h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 70h
Power Well: Core
Default: 00000001h
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Datasheet
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November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
TLS
0
EC
0
SD
0
4
HASD
0
TM
0
8
EMC
0
12
CD
0
16
CSOS
0
20
RSVD
0
24
RSVD_1
0
28
CDL
31
Field Name (ID): Description
0000h
RO
Reserved (RSVD_1): Reserved.
16
0b
RO/V
Current De-emphasis Level (CDL): When the Link is operating at 5 GT/s speed, this
bit reflects the level of de-emphasis.
Encodings:
1b -3.5 dB
0b -6 dB
The value in this bit is undefined when the Link is operating at 2.5 GT/s speed.
15:13
000b
RO
Reserved (RSVD): Reserved.
12
0b
RW/P
Compliance De-emphasis (CD): This bit sets the de-emphasis level in
Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s, the setting of this bit has no effect.
The default value of this bit is 0b.
This bit is intended for debug, compliance testing purposes. System firmware and
software is allowed to modify this bit only during debug or compliance testing.
11
0b
RW/P
Compliance SOS (CSOS): When set to 1b, the LTSSM is required to send SKP Ordered
Sets periodically in between the (modified) compliance patterns.
The default value of this bit is 0b.
0b
RW/P
Enter Modified Compliance (EMC): When this bit is set to 1b, the device transmits
Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.
Default value of this bit is 0b.
This register is intended for debug, compliance testing purposes only. System firmware
and software is allowed to modify this register only during debug or compliance testing.
In all other cases, the system must ensure that this register is set to the default value.
000b
RW/P
Transmit Margin (TM): This field controls the value of the nondeemphasized voltage
level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM
Polling.Configuration substate (see PCI Express Chapter 4 for details of how the
Transmitter voltage level is determined in various states).
Encodings:
000b Normal operating range
001b 800-1200 mV for full swing and 400-700 mV for half-swing
010b-(n-1) Values must be monotonic with a non-zero slope. The value of n must be
greater than 3 and less than 7. At least two of these must be below the normal
operating range of n : 200-400 mV for full-swing and 100-200 mV for half-swing
n-111b reserved
For a Multi-Function device associated with an Upstream Port, the field in Function 0 is
of type RWS, and only Function 0 controls the component's Link behavior. In all other
Functions of that device, this field is of type RsvdP.
Default value of this field is 000b.
Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to
000b.
This register is intended for debug, compliance testing purposes only. System firmware
and software is allowed to modify this register only during debug or compliance testing.
In all other cases, the system must ensure that this register is set to the default value.
0b
RW/P
Selectable De-emphasis (SD): When the Link is operating at 5.0 GT/s speed, this bit
selects the level of de-emphasis for an Upstream component.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, the setting of this bit has no effect.
31:17
10
9:7
6
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Datasheet
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
5
0b
RO
4
0b
RW/P
14.5.26
Hardware Autonomous Speed Disable (HASD): This port cannot autonomously
change speeds.
Enter Compliance (EC): Software is permitted to force a Link to enter Compliance
mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in
both components on a Link and then initiating a hot reset on the Link.
Default value of this bit following Fundamental Reset is 0b.
1h
RW/F/P
3:0
Field Name (ID): Description
Target Link Speed (TLS): This field sets an upper limit on Link operational speed by
restricting the values advertised by the upstream component in its training sequences.
Slot Capabilities 2 (SLCAP2)—Offset 74h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 74h
Power Well: Core
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSVD
0
Bit
Range
31:0
14.5.27
Default &
Access
Field Name (ID): Description
00000000h
Reserved (RSVD): Reserved.
RO
Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 78h
Power Well: Core
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
Bit
Range
Default &
Access
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:16
0000h
RO
Reserved (RSVD_1): Reserved.
15:0
0000h
RO
Reserved (RSVD): Reserved.
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Datasheet
288
0
8
RSVD
RSVD_1
0
28
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PCI Express* 2.0—Intel® Quark™ SoC X1000
14.5.28
Message Signaled Interrupt Message Control (MID_MC)—Offset
80h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 80h
Power Well: Core
Default: 00009005h
0
0
Bit
Range
0
0
0
16
0
0
0
Default &
Access
0
12
1
0
0
1
8
0
0
0
0
4
0
0
0
0
0
0
1
0
1
Field Name (ID): Description
31:24
00h
RO
Reserved (RSVD): Reserved.
23
0b
RO
64-Bit Address Capable (C64): Capable of generating a 32-bit message only.
22:20
000b
RW
Multiple Message Enable (MME): These bits are RW for software compatibility, but
only one message is ever sent by the root port.
19:17
000b
RO
Multiple Message Capable (MMC): Only one message is required.
0b
RW
MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not used
to generate interrupts. CMD.BME must be set for an MSI to be generated. If CMD.BME is
cleared, and this bit is set, no interrupts (not even pin based) are generated.
15:8
90h
RWO
Next Pointer (NEXT): Indicates the location of the next capability in the list.
The default value of this register is 90h which points to the Subsystem Vendor capability
structure.
BIOS can determine which capabilities will be exposed by including or removing them
from the capability linked list.
As this register is RWO, BIOS must write a value to this register, even if it is to re-write
the default value.
7:0
05h
RO
Capability ID (CID): Capabilities ID indicates MSI.
16
14.5.29
20
0
CID
0
NEXT
24
0
MSIE
0
MME
0
MMC
28
0
RSVD
0
C64
31
Message Signaled Interrupt Message Address (MA)—Offset 84h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 84h
Power Well: Core
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
ADDR
0
28
November 2014
Document Number: 329676-004US
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSVD
31
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Datasheet
289
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
31:2
Default &
Access
00000000h Address (ADDR): Lower 32 bits of the system specified message address, always DW
aligned.
RW
00b
RO
1:0
14.5.30
Field Name (ID): Description
Reserved (RSVD): Reserved.
Message Signaled Interrupt Message Data (MD)—Offset 88h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 88h
Power Well: Core
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
Default &
Access
00000h
RO
31:16
14.5.31
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
Reserved (RSVD1): Reserved
Data (DATA): This 16-bit field is programmed by system software if MSI is enabled. Its
content is driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI
memory write transaction.
0000h
RW
15:0
0
4
DATA
RSVD1
0
28
Subsystem Vendor Capability (SVCAP)—Offset 90h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 90h
Power Well: Core
Default: 0000A00Dh
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
Bit
Range
31:16
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Default &
Access
00000h
RO
12
1
0
1
0
8
0
0
0
0
NEXT
RSVD1
0
4
0
0
0
0
0
1
1
0
1
CID
31
Field Name (ID): Description
Reserved (RSVD1): Reserved
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
14.5.32
Default &
Access
Field Name (ID): Description
15:8
A0h
RWO
Next Capability (NEXT): Indicates the location of the next capability in the list.
The default value of this register is A0h which points to the PCI Power Management
capability structure.
BIOS can determine which capabilities will be exposed by including or removing them
from the capability linked list.
As this register is RWO, BIOS must write a value to this register, even if it is to re-write
the default value.
7:0
0Dh
RO
Capability Identifier (CID): Value of 0Dh indicates this is a PCI bridge subsystem
vendor capability.
Subsystem Vendor IDs (SVID)—Offset 94h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 94h
Power Well: Core
Default: 00000000h
28
0
0
0
24
0
0
0
20
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
SID
0
Bit
Range
14.5.33
0
4
0
0
0
0
0
0
0
0
0
SVID
31
Default &
Access
Field Name (ID): Description
31:16
0000h
RWO
Subsystem Identifier (SID): Indicates the subsystem as identified by the vendor.
This field is write once and is locked down until a bridge reset occurs (not the PCI bus
reset).
15:0
0000h
RWO
Subsystem Vendor Identifier (SVID): Indicates the manufacturer of the subsystem.
This field is write once and is locked down until a bridge reset occurs (not the PCI bus
reset).
PCI Power Management Capabilities (PMCAP_PMC)—Offset A0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + A0h
Power Well: Core
Default: C8020001h
Bit
Range
31:27
0
0
0
0
0
1
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
1
CID
0
12
NEXT
0
VS
0
PMEC
0
DSI
1
16
RSVD
0
20
AC
0
D1S
1
24
PMES
1
28
D2S
31
Default &
Access
Field Name (ID): Description
11001b
RO
PME Support (PMES): Indicates PME# is supported for states D0, D3HOT and
D3COLD. The root port does not generate PME#, but reporting that it does is necessary
for legacy Microsoft operating systems to enable PME# in devices connected behind this
root port.
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Document Number: 329676-004US
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Datasheet
291
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
26
0b
RO
D2 Support (D2S): The D2 state is not supported.
25
0b
RO
D1 Support (D1S): The D1 state is not supported.
000b
RO
24:22
Aux Current (AC): Reports 375mA maximum suspend well current required when in
the D3COLD state.
21
0b
RO
Device Specific Initialization (DSI): Indicates that no device-specific initialization is
required.
20
0b
RO
Reserved (RSVD): Reserved.
19
0b
RO
PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#.
010b
RO
Version (VS): Indicates support for Revision 1.1 of the PCI Power Management
Specification.
18:16
14.5.34
Field Name (ID): Description
15:8
00h
RO
Next Capability (NEXT): Indicates this is the last item in the list.
7:0
01h
RO
Capability Identifier (CID): Value of 01h indicates this is a PCI power management
capability.
PCI Power Management Control And Status (PMCS)—Offset A4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + A4h
Power Well: Core
Default: 00000000h
Bit
Range
0
0
0
0
0
0
0
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PS
0
0
RSVD_1
0
4
PMEE
0
8
DSEL
0
DSC
0
12
PMES
0
16
RSVD
0
20
BPCE
0
24
DTA
0
28
B23S
31
Field Name (ID): Description
31:24
00h
RO
Data (DTA): Reserved
23
0b
RO
Bus Power / Clock Control Enable (BPCE): Reserved per PCI Express specification.
22
0b
RO
B2/B3 Support (B23S): Reserved per PCI Express specification.
21:16
00h
RO
Reserved (RSVD): Reserved.
15
0b
RO
PME Status (PMES): Indicates a PME was received on the downstream link.
14:13
00b
RO
Data Scale (DSC): Reserved
Intel® Quark™ SoC X1000
Datasheet
292
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
0h
RO
12:9
7:2
1:0
14.5.35
Data Select (DSEL): Reserved
PME Enable (PMEE): Indicates PME is enabled. The root port takes no action on this
bit, but it must be RW for legacy Microsoft operating systems to enable PME# on devices
connected to this root port. This register resides in the resume well and is not reset on a
resume from S3/S4/S5.
The reset for this register is RSMRST# which is not asserted during a Warm Reset.
0b
RW/W
8
Field Name (ID): Description
00h
RO
Reserved (RSVD_1): Reserved.
00b
RW
Power State (PS): This field is used both to determine the current power state of the
root port and to set a new power state. The values are:
00 D0 state
11 D3HOT state
When in the D3HOT state, the controller's configuration space is available, but the I/O
and memory spaces are not. Type 1 configuration cycles are also not accepted.
Interrupts are not required to be blocked as software will disable interrupts prior to
placing the port into D3HOT.
If software attempts to write a '10' or '01' to these bits, the write will be ignored.
Channel Configuration (CCFG)—Offset D0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + D0h
Power Well: Core
Default: 01000000h
Bit
Range
Default &
Access
0
0
0
0b
RO
Reserved (RSVD): Reserved.
30
0b
RO
Reserved (RSVD): Reserved.
29:25
00h
RO
Reserved (RSVD): Reserved.
1b
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
31
24
0
4
RSVD
0
RSVD
0
RSVD
0
RSVD
0
8
RSVD
0
RSVD
0
UPRS
0
RSVD
1
12
UNRS
0
16
RSVD
0
RSVD
0
20
UPSD
0
24
RSVD
0
RSVD
0
RSVD
0
28
UNSD
31
Upstream Posted Split Disable (UPSD): When '0', upstream posted memory
requests will be split on boundaries defined by the UPRS bit in this register.
When '1', upstream posted memory requests will not be split and will be presented to
the backbone as received from the link.
This register has no effect on posted messages which are never split.
BIOS must program this bit to '0'.
23
0b
RW
Upstream Non-Posted Split Disable (UNSD): When '0', upstream non-posted
requests will be split on boundaries defined by the UNRS bit in this register.
When '1', upstream non-posted requests will not be split and will be presented to the
backbone as received from the link.
BIOS must program this bit to '0'.
November 2014
Document Number: 329676-004US
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Datasheet
293
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
22:18
00h
RO
Reserved (RSVD): Reserved.
17
0b
RO
Reserved (RSVD): Reserved.
16
0b
RO
Reserved (RSVD): Reserved.
Upstream Non-Posted Request Size (UNRS): Sets the size for splitting upstream
memory read requests. Requests will be split on naturally aligned addresses.
When '0', requests are split at 128 byte boundaries.
When '1', requests are split at 64 byte boundaries. This field is only used if the UNSD bit
is '0'.
0b
RW
15
BIOS must program this bit to '1'.
Upstream Posted Request Size (UPRS): Sets the size for splitting upstream memory
write requests. Requests will be split on naturally aligned addresses.
When '0', requests are split at 128 byte boundaries.
When '1', requests are split at 64 byte boundaries. This field is only used if the UPSD bit
is '0'.
This register has no effect on posted messages which are never split.
0b
RW
14
BIOS must program this bit to '1'.
14.5.36
13:12
00b
RO
Reserved (RSVD): Reserved.
11
0b
RO
Reserved (RSVD): Reserved.
10
0b
RO
Reserved (RSVD): Reserved.
9
0b
RO
Reserved (RSVD): Reserved.
8
0b
RO
Reserved (RSVD): Reserved.
7:0
00h
RO
Reserved (RSVD): Reserved.
Miscellaneous Port Configuration 2 (MPC2)—Offset D4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + D4h
Power Well: Core
Default: 00000000h
0
0
0
0
0
0
Bit
Range
31:12
Intel® Quark™ SoC X1000
Datasheet
294
Default &
Access
00000h
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
0
RSVD
0
0
RSVD
0
RSVD
0
4
RSVD
0
8
RSVD
0
12
RSVD
0
16
RSVD
0
20
IPF
0
24
RSVD
0
28
RSVD
31
Field Name (ID): Description
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
Packet Fast Transmit Mode (IPF): When set, the PCIe transmit block will move the
packet header from the Tx buffer to the retry buffer without waiting for the
corresponding data to be available.
When cleared, the packet transfer to the retry buffer will not occur until the Tx buffer
has the entire data phase available.
11
0b
RW
10
0b
RO
Reserved (RSVD): Reserved.
9
0b
RO
Reserved (RSVD): Reserved.
8
0b
RO
Reserved (RSVD): Reserved.
7
0b
RO
Reserved (RSVD): Reserved.
6:5
00b
RO
Reserved (RSVD): Reserved.
4
0b
RO
Reserved (RSVD): Reserved.
3:2
00b
RO
Reserved (RSVD): Reserved.
1
0b
RO
Reserved (RSVD): Reserved.
0
0b
RO
Reserved (RSVD): Reserved.
BIOS must program this bit to 1.
14.5.37
Miscellaneous Port Configuration (MPC)—Offset D8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + D8h
Power Well: Core
Default: 01110000h
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
HPME
RSVD
1
PMME
RSVD
0
RSVD
RSVD
0
RSVD
RSVD
Default &
Access
16
0
RSVD
RSVD
Bit
Range
1
RSVD
0
RSVD
0
RSVD
0
RSVD
1
RSVD
0
CCEL
0
UCEL
0
RSVD
20
0
RSVD
24
0
RSVD
28
0
HPCE
PMCE
0
RSVD
31
Field Name (ID): Description
31
0b
RW
Power Management SCI Enable (PMCE): Enables the root port to generate SCI
whenever a power management event is detected.
30
0b
RW
Hot Plug SCI Enable (HPCE): Enables the root port to generate SCI whenever a hot
plug event is detected.
29
0b
RO
Reserved (RSVD): Reserved.
28
0b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
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Datasheet
295
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
27
0b
RO
Reserved (RSVD): Reserved.
26
0b
RO
Reserved (RSVD): Reserved.
25
0b
RO
Reserved (RSVD): Reserved.
24
1b
RO
Reserved (RSVD): Reserved.
23
0b
RO
Reserved (RSVD): Reserved.
22
0b
RO
Reserved (RSVD): Reserved.
21
0b
RO
Reserved (RSVD): Reserved.
20:18
100b
RW
Unique Clock Exit Latency (UCEL): This value represents the L0s Exit Latency for
unique-clock configurations (LCAP.CCC = '0'). It defaults to 512ns to less than 1us, but
may be overridden by BIOS.
17:15
010b
RW
Common Clock Exit Latency (CCEL): This value represents the L0s Exit Latency for
common-clock configurations (LCAP.CCC = '1'). It defaults to 128ns to less than 256ns,
but may be overridden by BIOS.
14
0b
RO
Reserved (RSVD): Reserved.
13
0b
RO
Reserved (RSVD): Reserved.
12
0b
RO
Reserved (RSVD): Reserved.
11:8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Reserved (RSVD): Reserved.
000b
RO
Reserved (RSVD): Reserved.
3
0b
RO
Reserved (RSVD): Reserved.
2
0b
RO
Reserved (RSVD): Reserved.
1
0b
RW
Hot Plug SMI Enable (HPME): Enables the root port to generate SMI whenever a hot
plug event is detected.
0
0b
RW
Power Management SMI Enable (PMME): Enables the root port to generate SMI
whenever a power management event is detected.
6:4
14.5.38
Field Name (ID): Description
SMI / SCI Status (SMSCS)—Offset DCh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + DCh
Power Well: Core
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
296
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PMMS
0
4
HPPDM
0
8
RSVD
0
12
Default &
Access
Field Name (ID): Description
31
0b
RWC
Power Management SCI Status (PMCS): This bit is set if the root port PME control
logic needs to generate an interrupt, and this interrupt has been routed to generate an
SCI.
30
0b
RWC
Hot Plug SCI Status (HPCS): This bit is set if the hot plug controller needs to
generate an interrupt, and has this interrupt been routed to generate an SCI.
29:5
14.5.39
0
16
RSVD
0
20
RSVD
0
24
HPCS
0
PMCS
0
28
HPLAS
31
0000000h
Reserved (RSVD): Reserved.
RO
Hot Plug Link Active State Changed SMI Status (HPLAS): This bit is set when
SLSTS.LASC transitions from '0' to '1', and MPC.HPME is set. When this bit is set, an
SMI# will be generated.
4
0b
RWC
3
0b
RO
Reserved (RSVD): Reserved.
2
0b
RO
Reserved (RSVD): Reserved.
1
0b
RWC
Hot Plug Presence Detect SMI Status (HPPDM): This bit is set when SLSTS.PDC
transitions from '0' to '1', and MPC.HPME is set. When this bit is set, an SMI# will be
generated.
0
0b
RWC
Power Management SMI Status (PMMS): This bit is set when RSTS.PS transitions
from '0' to '1', and MPC.PMME is set.
Message Bus Control (PHYCTL_PHYCTL2_IOSFSBCTL)—Offset
F4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + F4h
Default: 000C3043h
Bit
Range
Default &
Access
16
1
1
0
0
0
1
1
8
0
0
0
4
0
0
1
0
0
0
0
0
1
1
Field Name (ID): Description
31:24
0b
RO
RSVD0: Reserved
23:20
0h
RO
Reserved (RSVD): Reserved.
19:18
11b
RO
Reserved (RSVD): Reserved.
November 2014
Document Number: 329676-004US
12
0
RSVD
0
RSVD
0
RSVD
0
RSVD
20
0
RSVD
0
RSVD
0
RSVD
0
RSVD
24
0
RSVD
0
RSVD
0
SBIC
28
0
RSVD0
0
RSVD
31
Intel® Quark™ SoC X1000
Datasheet
297
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
Message Bus Idle Counter (SBIC): This register provides configuration flexibility to
govern when the Message Bus interface transitions to IDLE.
17:16
00b
RW
15:14
00b
RO
Reserved (RSVD): Reserved.
13:12
11b
RO
Reserved (RSVD): Reserved.
000b
RO
Reserved (RSVD): Reserved.
8
0b
RO
Reserved (RSVD): Reserved.
7
0b
RO
Reserved (RSVD): Reserved.
6:5
10b
RO
Reserved (RSVD): Reserved.
4
0b
RO
Reserved (RSVD): Reserved.
3:2
00b
RO
Reserved (RSVD): Reserved.
1:0
11b
RO
Reserved (RSVD): Reserved.
11:9
14.5.40
Field Name (ID): Description
BIOS must program this field to 11b to prevent transitions to IDLE on the Message Bus
interface.
Advanced Error Reporting Capability Header (AECH)—Offset
100h
The AER capability can optionally be included or excluded from the capabilities list. The
full AER is supported.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 100h
Power Well: Core
Default: 00000000h
0
0
0
0
0
Bit
Range
Default &
Access
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CID
0
24
NCO
0
28
CV
31
Field Name (ID): Description
31:20
000h
RWO
Next Capability Offset (NCO): Set to 000h as this is the last capability in the list.
19:16
0h
RWO
Capability Version (CV): For systems that support AER, BIOS should write a 1h to this
register else it should write 0
Intel® Quark™ SoC X1000
Datasheet
298
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0000h
RWO
Capability ID (CID): For systems that support AER, BIOS should write a 0001h to this
register else it should write 0
15:0
14.5.41
Uncorrectable Error Status (UES)—Offset 104h
This register must maintain its state through a platform reset. It loses its state upon
loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 104h
Power Well: Core
Default: 00000000h
Bit
Range
Default &
Access
31:22
000h
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TE
0
0
RSVD_2
0
SDE
0
4
DLPE
0
8
RSVD_1
0
PT
0
CT
0
FCPE
0
CA
0
12
UC
0
RO
0
EE
0
16
MT
0
20
AVS
0
24
RSVD
0
28
URE
31
Field Name (ID): Description
Reserved (RSVD): Reserved.
21
0b
RO
ACS Violation Status (AVS): Reserved. Access Control Services are not supported.
20
0b
RWC/P
Unsupported Request Error Status (URE): Indicates an unsupported request was
received.
19
0b
RO
18
0b
RWC/P
Malformed TLP Status (MT): Indicates a malformed TLP was received.
17
0b
RWC/P
Receiver Overflow Status (RO): Indicates a receiver overflow occurred.
16
0b
RWC/P
Unexpected Completion Status (UC): Indicates an unexpected completion was
received.
15
0b
RWC/P
Completer Abort Status (CA): Indicates a completer abort was received.
14
0b
RWC/P
Completion Timeout Status (CT): Indicates a completion timed out. This is signaled
if Completion Timeout is enabled and a completion fails to return within the amount of
time specified by the Completion Timeout Value.
13
0b
RO
12
0b
RWC/P
ECRC Error Status (EE): ECRC is not supported.
Flow Control Protocol Error Status (FCPE): Not supported.
Poisoned TLP Status (PT): Indicates a poisoned TLP was received.
11:6
00h
RO
Reserved (RSVD_1): Reserved.
5
0b
RO
Surprise Down Error Status (SDE): Surprise Down is not supported.
November 2014
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Datasheet
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
0b
RWC/P
4
Reserved (RSVD_2): Reserved.
0b
RO
0
14.5.42
Data Link Protocol Error Status (DLPE): Indicates a data link protocol error
occurred.
000b
RO
3:1
Field Name (ID): Description
Training Error Status (TE): Not supported.
Uncorrectable Error Mask (UEM)—Offset 108h
When set, the corresponding error in the UES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled. This register is
only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 108h
Power Well: Core
Default: 00000000h
Bit
Range
31:22
Intel® Quark™ SoC X1000
Datasheet
300
Default &
Access
000h
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TE
0
0
RSVD_2
0
SDE
0
4
DLPE
0
8
RSVD_1
0
PT
0
CT
0
FCPE
0
UC
0
12
CM
0
RO
0
EE
0
16
MT
0
20
AVS
0
24
RSVD
0
28
URE
31
Field Name (ID): Description
Reserved (RSVD): Reserved.
21
0b
RO
20
0b
RW/P
19
0b
RO
18
0b
RW/P
Malformed TLP Mask (MT): Mask for malformed TLPs.
17
0b
RW/P
Receiver Overflow Mask (RO): Mask for receiver overflows.
16
0b
RW/P
Unexpected Completion Mask (UC): Mask for unexpected completions.
15
0b
RW/P
Completer Abort Mask (CM): Mask for completer abort.
14
0b
RW/P
Completion Timeout Mask (CT): Mask for completion timeouts.
13
0b
RO
ACS Violation Status (AVS): Reserved. Access Control Services are not supported.
Unsupported Request Error Mask (URE): Mask for uncorrectable errors.
ECRC Error Mask (EE): ECRC is not supported.
Flow Control Protocol Error Mask (FCPE): Not supported.
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
0b
RW/P
12
Poisoned TLP Mask (PT): Mask for poisoned TLPs.
11:6
00h
RO
Reserved (RSVD_1): Reserved.
5
0b
RO
Surprise Down Error Mask (SDE): Surprise Down is not supported.
4
0b
RW/P
Data Link Protocol Error Mask (DLPE): Mask for data link protocol errors.
3:1
000b
RO
Reserved (RSVD_2): Reserved.
0b
RO
0
14.5.43
Field Name (ID): Description
Training Error Mask (TE): Not supported.
Uncorrectable Error Severity (UEV)—Offset 10Ch
This register gives the option to make an uncorrectable error fatal or non-fatal. An
error is fatal if the bit is set. An error is non-fatal if the bit is cleared. This register is
only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 10Ch
Power Well: Core
Default: 00060011h
Bit
Range
31:22
Default &
Access
000h
RO
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
Field Name (ID): Description
Reserved (RSVD): Reserved.
21
0b
RO
20
0b
RW/P
19
0b
RO
18
1b
RW/P
Malformed TLP Severity (MT): Severity for malformed TLP reception.
17
1b
RW/P
Receiver Overflow Severity (RO): Severity for receiver overflow occurrences.
16
0b
RW/P
Unexpected Completion Severity (UC): Severity for unexpected completion
reception.
November 2014
Document Number: 329676-004US
0
TE
1
0
RSVD_2
1
SDE
0
4
DLPE
0
8
RSVD_1
0
PT
0
CT
0
FCPE
0
CA
0
12
UC
0
RO
0
EE
0
16
MT
0
20
AVS
0
24
RSVD
0
28
URE
31
ACS Violation Severity (AVS): Reserved. Access Control Services are not supported.
Unsupported Request Error Severity (URE): Severity for unsupported request
reception.
ECRC Error Severity (EE): ECRC is not supported.
Intel® Quark™ SoC X1000
Datasheet
301
Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
15
0b
RW/P
Completer Abort Severity (CA): Severity for completer abort.
14
0b
RW/P
Completion Timeout Severity (CT): Severity for completion timeout.
13
0b
RO
12
0b
RW/P
Flow Control Protocol Error Severity (FCPE): Not supported.
Poisoned TLP Severity (PT): Severity for poisoned TLP reception.
11:6
00h
RO
Reserved (RSVD_1): Reserved.
5
0b
RO
Surprise Down Error Severity (SDE): Surprise Down is not supported.
4
1b
RW/P
Data Link Protocol Error Severity (DLPE): Severity for data link protocol errors.
3:1
000b
RO
Reserved (RSVD_2): Reserved.
1b
RO
0
14.5.44
Field Name (ID): Description
Training Error Severity (TE): TE not supported. This bit is left as RO='1' for ease of
implementation.
Correctable Error Status (CES)—Offset 110h
This register is only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 110h
Power Well: Core
Default: 00000000h
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RE
0
0
RSVD_2
0
4
BT
0
8
BD
0
12
RNR
0
16
RSVD_1
0
20
RTT
0
24
RSVD
0
28
ANFES
31
Field Name (ID): Description
31:14
00000h
RO
Reserved (RSVD): Reserved.
13
0b
RWC/P
Advisory Non-Fatal Error Status (ANFES): When set, indicates that a Advisory NonFatal Error occurred.
12
0b
RWC/P
Replay Timer Timeout Status (RTT): Indicates the replay timer timed out.
11:9
8
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Datasheet
302
000b
RO
0b
RWC/P
Reserved (RSVD_1): Reserved.
Replay Number Rollover Status (RNR): Indicates the replay number rolled over.
November 2014
Document Number: 329676-004US
PCI Express* 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
7
0b
RWC/P
Bad DLLP Status (BD): Indicates a bad DLLP was received.
6
0b
RWC/P
Bad TLP Status (BT): Indicates a bad TLP was received.
00h
RO
5:1
Reserved (RSVD_2): Reserved.
0b
RWC/P
0
14.5.45
Field Name (ID): Description
Receiver Error Status (RE): Indicates a receiver error occurred.
Correctable Error Mask (CEM)—Offset 114h
When set, the corresponding error in the CES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled. This register is
only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 114h
Power Well: Core
Default: 00002000h
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:14
00000h
RO
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
RE
0
0
RSVD_2
0
4
BT
0
8
BD
0
12
RNR
0
16
RSVD_1
0
20
RTT
0
24
RSVD
0
28
ANFEM
31
Field Name (ID): Description
Reserved (RSVD): Reserved.
13
1b
RW/P
Advisory Non-Fatal Error Mask (ANFEM): When set, masks Advisory Non-Fatal
errors from (a) signaling ERR_COR to the device control register and (b) updating the
Uncorrectable Error Status register.
This register is set by default to enable compatibility with software that does not
comprehend Role-Based Error Reporting.
12
0b
RW/P
Replay Timer Timeout Mask (RTT): Mask for replay timer timeout.
11:9
000b
RO
Reserved (RSVD_1): Reserved.
8
0b
RW/P
Replay Number Rollover Mask (RNR): Mask for replay number rollover.
7
0b
RW/P
Bad DLLP Mask (BD): Mask for bad DLLP reception.
6
0b
RW/P
Bad TLP Mask (BT): Mask for bad TLP reception.
5:1
00h
RO
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Reserved (RSVD_2): Reserved.
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Bit
Range
Default &
Access
0b
RW/P
0
14.5.46
Field Name (ID): Description
Receiver Error Mask (RE): Mask for receiver errors.
Advanced Error Capabilities and Control (AECC)—Offset 118h
This register is only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 118h
Power Well: Core
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
Bit
Range
Default &
Access
000000h
RO
31:9
14.5.47
0
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
Reserved (RSVD): Reserved.
8
0b
RO
ECRC Check Enable (ECE): ECRC is not supported.
7
0b
RO
ECRC Check Capable (ECC): ECRC is not supported.
6
0b
RO
ECRC Generation Enable (EGE): ECRC is not supported.
5
0b
RO
ECRC Generation Capable (EGC): ECRC is not supported.
00000b
RO/V/P
4:0
4
FEP
0
12
EGE
0
16
EGC
0
20
ECE
0
24
RSVD
0
28
ECC
31
First Error Pointer (FEP): Identifies the bit position of the first error reported in the
Uncorrectable Error Status Register.
Header Log (HL_DW1)—Offset 11Ch
These registers report the header for the TLP corresponding to a detected error. This
register is only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 11Ch
Power Well: Core
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DW1
0
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Bit
Range
31:0
14.5.48
Default &
Access
Field Name (ID): Description
00000000h
4th DWord of TLP (DW1): Byte12 and Byte13 and Byte14 and Byte15
RO/V/P
Header Log (HL_DW2)—Offset 120h
These registers report the header for the TLP corresponding to a detected error. This
register is only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 120h
Power Well: Core
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DW2
0
28
Bit
Range
31:0
14.5.49
Default &
Access
Field Name (ID): Description
00000000h
3rd DWord of TLP (DW2): Byte8 and Byte9 and Byte10 and Byte11
RO/V/P
Header Log (HL_DW3)—Offset 124h
These registers report the header for the TLP corresponding to a detected error. This
register is only reset by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 124h
Power Well: Core
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DW2
0
Bit
Range
31:0
14.5.50
Default &
Access
Field Name (ID): Description
00000000h
2nd DWord of TLP (DW2): Byte4 and Byte5 and Byte6 and Byte7
RO/V/P
Header Log (HL_DW4)—Offset 128h
These registers report the header for the TLP corresponding to a detected error. This
register is only reset by a loss of core power.
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Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 128h
Power Well: Core
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
DW1
0
28
Bit
Range
Default &
Access
31:0
14.5.51
Field Name (ID): Description
00000000h
1st DWord of TLP (DW1): Byte0 and Byte1 and Byte2 and Byte3
RO/V/P
Root Error Command (REC)—Offset 12Ch
This register allows errors to generate interrupts.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 12Ch
Power Well: Core
Default: 00000000h
0
0
0
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
Default &
Access
31:3
14.5.52
4
0
0
0
0
0
0
0
0
0
CERE
0
20
FERE
0
24
RSVD
0
28
NERE
31
Field Name (ID): Description
00000000h
Reserved (RSVD): Reserved.
RO
2
0b
RW
Fatal Error Reporting Enable (FERE): When set, the root port will generate an
interrupt when a fatal error is reported by the attached device.
1
0b
RW
Non-fatal Error Reporting Enable (NERE): When set, the root port will generate an
interrupt when a non-fatal error is reported by the attached device.
0
0b
RW
Correctable Error Reporting Enable (CERE): When set, the root port will generate
an interrupt when a correctable error is reported by the attached device.
Root Error Status (RES)—Offset 130h
This register can track more than one error and set the multiple bits if a second or
subsequent error occurs and the first has not been serviced. This register is only reset
by a loss of core power.
Access Method
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PCI Express* 2.0—Intel® Quark™ SoC X1000
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 130h
Power Well: Core
Default: 00000000h
0
0
0
0
0
0
Bit
Range
Default &
Access
00h
RO
31:27
14.5.53
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CR
0
0
MCR
0
4
ENR
0
8
FUF
0
12
MENR
0
16
FEMR
0
20
RSVD
0
24
AEMN
0
28
NFEMR
31
Field Name (ID): Description
Advanced Error Interrupt Message Number (AEMN): Reserved. There is only one
error interrupt allocated.
26:7
00000h
RO
Reserved (RSVD): Reserved.
6
0b
RWC/P
Fatal Error Message Received (FEMR): Set when one or more Fatal Uncorrectable
Error Messages have been received.
5
0b
RWC/P
Non-Fatal Error Messages Received (NFEMR): Set when one or more Non-Fatal
Uncorrectable error messages have been received.
4
0b
RWC/P
First Uncorrectable Fatal (FUF): Set when the first Uncorrectable Error message
received is for a fatal error.
3
0b
RWC/P
Multiple ERR_FATAL/NONFATAL Received (MENR): Set when either a fatal or a
non-fatal error is received and the ENR bit is already set.
2
0b
RWC/P
ERR_FATAL/NONFATAL Received (ENR): Set when either a fatal or a non-fatal error
message is received.
1
0b
RWC/P
Multiple ERR_COR Received (MCR): Set when a correctable error message is
received and the CR bit is already set.
0
0b
RWC/P
ERR_COR Received (CR): Set when a correctable error message is received.
Error Source Identification (ESID)—Offset 134h
Identifies the source (Requester ID) of the first correctable and uncorrectable (NonFatal / Fatal) errors reported in the Root Error Status register. This register is only reset
by a loss of core power.
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
Offset: [B:0, D:23, F:0] + 134h
Power Well: Core
Default: 00000000h
28
0
0
0
24
0
0
0
0
EFNFSID
0
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20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
ECSID
31
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Intel® Quark™ SoC X1000—PCI Express* 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RO/V/P
ERR_FATAL/NONFATAL Source Identification (EFNFSID): Loaded with the
Requester ID indicated in the received ERR_FATAL or ERR_NONFATAL Message with the
ERR_FATAL/NONFATAL Received register is not already set.
15:0
0000h
RO/V/P
ERR_COR Source Identification (ECSID): Loaded with the Requester ID indicated in
the received ERR_COR Message with the ERR_COR Received register is not already set.
§§
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
15.0
10/100 Mbps Ethernet
The Intel® Quark™ SoC X1000 provides two 10/100 Mbps Ethernet controllers. Each
controller includes a MAC but not a PHY. The integrated controller is compatible with an
industry standard, RMII based Ethernet PHY.
15.1
Signal Descriptions
See Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 86.
10/100 Ethernet Interface Signals
Signal Name
15.2
Direction/
Type
Description
RMII_REF_CLK
I
50 MHz reference clock for the RMII interface
MAC[0/1]_TXDATA[1:0]
O
RMII Transmit data
MAC[0/1]_TXEN
O
RMII Transmit data enable
MAC[0/1]_RXDATA[1:0]
I
RMII Receive data
MAC[0/1]_RXDV
I
RMII Receive data valid
MAC[0/1]_MDC
O
Management data clock
MAC[0/1]_MDIO
I/O
Management data
Features:
• 10 and 100 Mbps data transfer rates with RMII interface to communicate with an
external Fast Ethernet PHY
• Compliant with RMII specification version 1.2 from RMII consortium
• Full-duplex operation:
— IEEE* 802.3x flow control automatic transmission of zero-quanta pause frame
on flow control input de-assertion
— Optional forwarding of received pause control frames to the user application
• Half-duplex operation:
— CSMA/CD Protocol support
• Preamble and start-of-frame data (SFD) insertion in transmit path
• Preamble and SFD deletion in the receive path
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
• Automatic CRC and pad generation controllable on a per-frame basis
• Automatic Pad and CRC Stripping options for receive frames
• Flexible address filtering modes:
— 64-bit hash filter for multicast and unicast (DA) addresses
— Option to pass all multicast addressed frames
— Promiscuous mode to pass all frames without any filtering for network
monitoring
— Pass all incoming packets (as per filter) with a status report
• Programmable frame length.
• Programmable Interframe Gap (IFG) (40-96 bit times in steps of 8)
• Option to transmit frames with reduced preamble size
• Separate 32-bit status for transmit and receive packets
• IEEE 802.1Q VLAN tag detection for reception frames
• Additional frame filtering:
— VLAN tag-based: hash-based filtering
• Separate transmission, reception, and control interfaces to the application
• Little-endian configuration for transmit and receive paths
• 32-bit data transfer interface on system-side
• Network statistics with RMON/MIB Counters (RFC2819/RFC2665)
• Enhanced receive module for checking IPv4 header checksum and TCP, UDP, or
ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type 2)
• Support Ethernet frame time stamping as described in IEEE 1588-2002 and
IEEE 1588-2008 The 64-bit timestamps are given in the transmit or receive status
of each frame
• MDIO master interface for PHY device configuration and management
• CRC replacement, source address field insertion or replacement, and VLAN
insertion, replacement, and deletion in transmitted frames with per-frame control
15.3
References
• IEEE 802.3TM Ethernet: http://standards.ieee.org/about/get/802/802.3.html
• Alert Standard Format Specification, Version 1.03: http://www.dmtf.org/standards/
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
15.4
Register Map
Figure 28.
Ethernet Register Map
PCI Space
CPU
Core
Host Bridge
D:0,F:0
PCI
CAM
(I/O)
Bus 0
MBAR
PCI
ECAM
(Mem)
PCIe*
D:23
SPI1 F:1
I2C*/GPIOF:2
IO Fabric
D:21
SPI0 F:0
Memory
Space
Ethernet
PCI Header
D:20,F:6, F7
RP0 F:0
Ethernet
Mem
Registers
RP0 F:1
Legacy Bridge
D:31, F:0
SDIO/eMMC F:0
HSUART0 F:1
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
MAC0 F:6
MAC1 F:7
See Chapter 5.0, “Register Access Methods” for additional information.
15.5
PCI Configuration Registers
Registers listed are for Function 6 (MAC 0). Function 7 (MAC 1) contain the same
registers. Differences between MACs are noted in individual registers.
Table 87.
Offset Start
Summary of PCI Configuration Registers—0/20/6
Offset End
Register ID—Description
Default
Value
0h
1h
“Vendor ID (VENDOR_ID)—Offset 0h” on page 312
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 313
0937h
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 313
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 314
0010h
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Table 87.
Offset Start
Summary of PCI Configuration Registers—0/20/6 (Continued)
Offset End
Default
Value
Register ID—Description
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 315
02000010h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 315
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 315
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 316
80h
Fh
Fh
“BIST (BIST)—Offset Fh” on page 316
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 317
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 317
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 318
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 318
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 318
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 319
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 319
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 320
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 320
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 320
00h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 321
01h
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 321
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 321
4803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 322
0008h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 323
00h
86h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 323
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 324
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 324
00h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 324
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 325
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 325
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 326
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 326
00000000h
15.5.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:6] + 0h
Default: 8086h
15
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
value
1
12
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Bit
Range
Default &
Access
8086h
RO
15: 0
15.5.2
Description
Vendor ID (value): PCI Vendor ID for Intel
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:6] + 2h
Default: 0937h
0
8
1
0
0
4
1
0
0
1
1
0
0
1
1
0
0
0
RSVD
0
MEMen
12
0
1
value
0
MasEn
15
Bit
Range
Default &
Access
0937h
RO
15: 0
15.5.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:6] + 4h
Default: 0000h
8
0
0
0
0
4
0
0
0
RSVD
0
SERREn
0
RSVD
12
0
RSVD0
0
IntrDis
15
0
0
0
Bit
Range
Default &
Access
15: 11
0h
RO
RSVD0 (RSVD0): Reserved
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
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Document Number: 329676-004US
Description
Intel® Quark™ SoC X1000
Datasheet
313
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
15.5.4
Default &
Access
Description
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
0
0h
RO
Reserved (RSVD): Reserved.
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:6] + 6h
Default: 0010h
Bit
Range
Default &
Access
0
1
0
0
0
0
RSVD1
0
IntrStatus
0
hasCapList
0
capable_66Mhz
4
0
RSVD
0
FastB2B
0
DEVSEL
0
RSVD
8
0
RSVD
0
RcdMasAb
0
SigSysErr
12
0
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
15.5.5
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:6] + 8h
Default: 02000010h
0
0
0
1
0
0
0
0
15.5.6
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
1
0
0
0
0
0
rev_id
0
20
progIntf
0
24
classCode
0
28
subClassCode
31
Bit
Range
Default &
Access
31: 24
02h
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
00h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
00h
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:6] + Ch
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
15.5.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:6] + Dh
Default: 00h
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7
4
0
0
0
0
0
0
0
value
0
0
15.5.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
HEADER_TYPE: [B:0, D:20, F:6] + Eh
Default: 80h
7
4
0
0
0
Bit
Range
15.5.9
0
0
0
0
cfgHdrFormat
multiFnDev
1
0
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:6] + Fh
Default: 00h
7
4
7
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Default &
Access
0h
RO
0
0
0
0
0
0
comp_code
BIST_capable
Bit
Range
0
RSVD
0
start_bist
0
Description
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
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Bit
Range
15.5.10
Default &
Access
Description
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
3: 0
0h
RO
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:6] + 10h
Default: 00000000h
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
15.5.11
0
4
0
0
0
0
0
0
0
0
0
isIO
0
memType
0
prefetchable
28
0
address
0
RSVD
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:6] + 28h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
0h
RO
31: 0
15.5.12
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:6] + 2Ch
Default: 0000h
15
12
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
value
0
Bit
Range
Default &
Access
0h
RO
15: 0
15.5.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:6] + 2Eh
Default: 0000h
15
12
0
0
0
8
0
0
0
4
0
0
0
0
0
0
value
0
Bit
Range
15: 0
15.5.14
Default &
Access
0h
RO
Description
Subsystem ID (value): PCI Subsystem ID
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset
30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:6] + 30h
Default: 00000000h
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0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
15.5.15
0
0
0
0
0
0
0
RSVD
ROM_base_addr
0
28
0
AddrDecodeEn
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:6] + 34h
Default: 00000080h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
0
0
Bit
Range
15.5.16
0
0
0
0
0
0
value
RSVD0
0
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_LINE: [B:0, D:20, F:6] + 3Ch
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.5.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:6] + 3Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
15.5.18
Bit
Range
Default &
Access
Description
7: 0
03h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:6] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
15.5.19
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MIN_GNT (value): Hardwired to 0
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:6] + 3Fh
Default: 00h
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7
4
0
0
0
0
0
0
0
0
1
value
0
0
15.5.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:6] + 80h
Default: 01h
7
4
0
0
0
0
0
0
value
0
15.5.21
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:6] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
0
value
1
15.5.22
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
November 2014
Document Number: 329676-004US
PMC: [B:0, D:20, F:6] + 82h
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Default: 4803h
15.5.23
0
4
0
0
0
0
0
0
0
1
1
version
0
PME_clock
0
RSVD
8
1
DSI
0
aux_curr
0
D1_support
12
1
PME_support
0
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
09h
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset
84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:6] + 84h
Default: 0008h
0
0
0
0
0
0
0
0
1
0
0
0
power_state
0
0
RSVD
0
4
Description
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
15
14: 13
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Datasheet
322
RSVD
Default &
Access
PME_en
Bit
Range
Data_select
Data_scale
0
8
PME_status
0
12
no_soft_reset
15
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Bit
Range
15.5.24
Default &
Access
Description
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—
Offset 86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:6] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
15.5.25
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset
87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:6] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
Bit
Range
Default &
Access
7: 0
0h
RO
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Document Number: 329676-004US
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.5.26
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:6] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
15.5.27
Bit
Range
Default &
Access
7: 0
05h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:6] + A1h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
15.5.28
Bit
Range
Default &
Access
Description
7: 0
00h
RO
Next Capability Pointer (value): Hardwired to 0 as this is the last capability structure
in the chain
Message Control (MESSAGE_CTRL)—Offset A2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_CTRL: [B:0, D:20, F:6] + A2h
Default: 0100h
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0
0
1
0
0
0
0
0
0
0
0
MSIEnable
0
0
multiMsgCap
0
4
multiMsgEn
0
8
bit64Cap
0
RSVD0
0
12
perVecMskCap
15
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
15.5.29
Default &
Access
Description
15: 9
0h
RO
RSVD0 (RSVD0): Reserved
8
1h
RO
Per Vector Masking Capable (perVecMskCap): Hardwired to 1 to indicate the
function supports PVM
7
0h
RO
64 bit Address Capabale (bit64Cap): This bit is hardwired to 0 to indicate that the
function is not capable of sending a 64-bit message address.
6: 4
0h
RW
Multi-Message Enable (multiMsgEn): As only one vector is supported per function,
software should only write a value of 0x0 to this field
3: 1
0h
RO
Multiple Message Enable (multiMsgCap): This field is hardwired to 0x0 to indicate
that the function is requesting a single vector
0
0h
RW
MSI Enable (MSIEnable): Set to enable MSI to request service. If set then it's
prohibited to use the INTx pin. System configuration software sets this bit to enable
MSI.
Message Address (MESSAGE_ADDR)—Offset A4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
MESSAGE_ADDR: [B:0, D:20, F:6] + A4h
Default: 00000000h
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
address
0
24
Bit
Range
15.5.30
0
0
RSVD0
31
Default &
Access
Description
31: 2
0h
RW
Message Address (address): If the Message Enable bit (bit 0 of the Message Control
register) is set, the contents of this register specify the DWORD-aligned address
(AD[31:2]) for the MSI memory write transaction. AD[1:0] are driven to zero during the
address phase. This field is read/write
1: 0
0h
RO
RSVD0 (RSVD0): Reserved
Message Data (MESSAGE_DATA)—Offset A8h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_DATA: [B:0, D:20, F:6] + A8h
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
MsgData
0
12
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
Description
0h
RW
Data Field (MsgData): System-specified message data. If the Message Enable bit (bit
0 of the Message Control register) is set, the message data is driven onto the lower
word (AD[15:0]) of the memory write transactions data phase. AD[31:16] are driven to
zero during the memory write transactions data phase. C/BE[3::0]# are asserted during
the data phase of the memory write transaction. None of the message bits will be
changed by hardware
15: 0
15.5.31
Mask Bits for MSI (PER_VEC_MASK)—Offset ACh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_MASK: [B:0, D:20, F:6] + ACh
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Bit
Range
15.5.32
0
MSIMask
RSVD0
0
28
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RW
Vector 0 Mask (MSIMask): Mask Bit for Vector 0. If this bit is set, the function will not
send MSI messages
Pending Bits for MSI (PER_VEC_PEND)—Offset B0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_PEND: [B:0, D:20, F:6] + B0h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RO
Vector 0 Pending (value): Pending Bit for Vector 0.
Intel® Quark™ SoC X1000
Datasheet
326
0
4
value
RSVD0
0
28
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
15.6
Memory Mapped Registers
Table 88.
Summary of Memory Mapped I/O Registers—BAR0
Offset
Start
Offset End
Default
Value
Register Name (Register Symbol)
0h
3h
“MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h” on page 331
00008000h
4h
7h
“MAC Frame Filter (Register 1) (GMAC_REG_1)—Offset 4h” on page 334
00000000h
8h
Bh
“Hash Table High Register (Register 2) (GMAC_REG_2)—Offset 8h” on page 336
00000000h
Ch
Fh
“Hash Table Low Register (Register 3) (GMAC_REG_3)—Offset Ch” on page 336
00000000h
10h
13h
“GMII Address Register (Register 4) (GMAC_REG_4)—Offset 10h” on page 337
00000000h
14h
17h
“GMII Data Register (Register 5) (GMAC_REG_5)—Offset 14h” on page 338
00000000h
18h
1Bh
“Flow Control Register (Register 6) (GMAC_REG_6)—Offset 18h” on page 339
00000000h
1Ch
1Fh
“VLAN Tag Register (Register 7) (GMAC_REG_7)—Offset 1Ch” on page 340
00000000h
20h
23h
“Version Register (Register 8) (GMAC_REG_8)—Offset 20h” on page 341
00001037h
24h
27h
“Debug Register (Register 9) (GMAC_REG_9)—Offset 24h” on page 342
00000000h
38h
3Bh
“Interrupt Register (Register 14) (GMAC_REG_14)—Offset 38h” on page 343
00000000h
00000000h
3Ch
3Fh
“Interrupt Mask Register (Register 15) (GMAC_REG_15)—Offset 3Ch” on page 344
40h
43h
“MAC Address0 High Register (Register 16) (GMAC_REG_16)—Offset 40h” on page 345 8000FFFFh
44h
47h
“MAC Address0 Low Register (Register 17) (GMAC_REG_17)—Offset 44h” on page 345
FFFFFFFFh
100h
103h
“MMC Control Register (Register 64) (GMAC_REG_64)—Offset 100h” on page 346
00000000h
104h
107h
“MMC Receive Interrupt Register (MMC_INTR_RX)—Offset 104h” on page 347
00000000h
108h
10Bh
“MMC Transmit Interrupt Register (MMC_INTR_TX)—Offset 108h” on page 349
00000000h
10Ch
10Fh
“MMC Receive Interrupt Mask Register (MMC_INTR_MASK_RX)—Offset 10Ch” on
page 351
00000000h
110h
113h
“MMC Transmit Interrupt Mask Register (MMC_INTR_MASK_TX)—Offset 110h” on
page 353
00000000h
114h
117h
“MMC Transmit Good Bad Octet Counter Register (TXOCTETCOUNT_GB)—Offset 114h”
on page 355
00000000h
118h
11Bh
“MMC Transmit Good Bad Frame Counter Register (TXFRAMECOUNT_GB)—Offset 118h”
00000000h
on page 355
11Ch
11Fh
“MMC Transmit Broadcast Good Frame Counter Register (TXBROADCASTFRAMES_G)—
Offset 11Ch” on page 356
00000000h
120h
123h
“MMC Transmit Multicast Good Frame Counter Register (TXMULTICASTFRAMES_G)—
Offset 120h” on page 356
00000000h
124h
127h
“MMC Transmit 64 Octet Good Bad Frame Counter Register (TX64OCTETS_GB)—Offset
124h” on page 357
00000000h
128h
12Bh
“MMC Transmit 65 to 127 Octet Good Bad Frame Counter Register
(TX65TO127OCTETS_GB)—Offset 128h” on page 357
00000000h
12Ch
12Fh
“MMC Transmit 128 to 255 Octet Good Bad Frame Counter Register
(TX128TO255OCTETS_GB)—Offset 12Ch” on page 358
00000000h
130h
133h
“MMC Transmit 256 to 511 Octet Good Bad Frame Counter Register
(TX256TO511OCTETS_GB)—Offset 130h” on page 358
00000000h
134h
137h
“MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Register
(TX512TO1023OCTETS_GB)—Offset 134h” on page 358
00000000h
138h
13Bh
“MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Register
(TX1024TOMAXOCTETS_GB)—Offset 138h” on page 359
00000000h
13Ch
13Fh
“MMC Transmit Unicast Good Bad Frame Counter Register (TXUNICASTFRAMES_GB)—
Offset 13Ch” on page 359
00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
327
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Table 88.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
140h
143h
“MMC Transmit Multicast Good Bad Frame Counter Register
(TXMULTICASTFRAMES_GB)—Offset 140h” on page 360
00000000h
144h
147h
“MMC Transmit Broadcast Good Bad Frame Counter Register
(TXBROADCASTFRAMES_GB)—Offset 144h” on page 360
00000000h
148h
14Bh
“MMC Transmit Underflow Error Frame Counter Register (TXUNDERFLOWERROR)—
Offset 148h” on page 361
00000000h
14Ch
14Fh
“MMC Transmit Single Collision Good Frame Counter Register (TXSINGLECOL_G)—
Offset 14Ch” on page 361
00000000h
150h
153h
“MMC Transmit Multiple Collision Good Frame Counter Register (TXMULTICOL_G)—
Offset 150h” on page 362
00000000h
154h
157h
“MMC Transmit Deferred Frame Counter Register (TXDEFERRED)—Offset 154h” on
page 362
00000000h
158h
15Bh
“MMC Transmit Late Collision Frame Counter Register (TXLATECOL)—Offset 158h” on
page 362
00000000h
15Ch
15Fh
“MMC Transmit Excessive Collision Frame Counter Register (TXEXESSCOL)—Offset
15Ch” on page 363
00000000h
160h
163h
“MMC Transmit Carrier Error Frame Counter Register (TXCARRIERERROR)—Offset 160h”
00000000h
on page 363
164h
167h
“MMC Transmit Good Bad Octet Counter Register (TXOCTETCOUNT_GB)—Offset 114h”
on page 355
168h
16Bh
“MMC Transmit Good Bad Frame Counter Register (TXFRAMECOUNT_GB)—Offset 118h”
00000000h
on page 355
16Ch
16Fh
“MMC Transmit Excessive Deferral Frame Counter Register (TXEXCESSDEF)—Offset
16Ch” on page 365
00000000h
170h
173h
“MMC Transmit Pause Frame Counter Register (TXPAUSEFRAMES)—Offset 170h” on
page 365
00000000h
174h
177h
“MMC Transmit VLAN Good Frame Counter Register (TXVLANFRAMES_G)—Offset 174h”
00000000h
on page 366
178h
17Bh
“MMC Transmit Oversize Good Frame Counter Register (TXOVERSIZE_G)—Offset 178h”
00000000h
on page 366
180h
183h
“MMC Receive Good Bad Frame Counter Register (RXFRAMECOUNT_GB)—Offset 180h”
on page 366
00000000h
184h
187h
“MMC Receive Good Bad Octet Counter Register (RXOCTETCOUNT_GB)—Offset 184h”
on page 367
00000000h
188h
18Bh
“MMC Receive Good Bad Octet Counter Register (RXOCTETCOUNT_GB)—Offset 184h”
on page 367
00000000h
18Ch
18Fh
“MMC Receive Broadcast Good Frame Counter Register (RXBROADCASTFRAMES_G)—
Offset 18Ch” on page 368
00000000h
190h
193h
“MMC Receive Multicast Good Frame Counter Register (RXMULTICASTFRAMES_G)—
Offset 190h” on page 368
00000000h
194h
197h
“MMC Receive CRC Error Frame Counter Register (RXCRCERROR)—Offset 194h” on
page 369
00000000h
198h
19Bh
“MMC Receive Alignment Error Frame Counter Register (RXALIGNMENTERROR)—Offset
00000000h
198h” on page 369
19Ch
19Fh
“MMC Receive Runt Frame Counter Register (RXRUNTERROR)—Offset 19Ch” on
page 370
00000000h
1A0h
1A3h
“MMC Receive Jabber Error Frame Counter Register (RXJABBERERROR)—Offset 1A0h”
on page 370
00000000h
1A4h
1A7h
“MMC Receive Undersize Good Frame Counter Register (RXUNDERSIZE_G)—Offset
1A4h” on page 370
00000000h
Intel® Quark™ SoC X1000
Datasheet
328
00000000h
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Table 88.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
1A8h
1ABh
“MMC Receive Oversize Good Frame Counter Register (RXOVERSIZE_G)—Offset 1A8h”
on page 371
00000000h
1ACh
1AFh
“MMC Receive 64 Octet Good Bad Frame Counter Register (RX64OCTETS_GB)—Offset
1ACh” on page 371
00000000h
1B0h
1B3h
“MMC Receive 65 to 127 Octet Good Bad Frame Counter Register
(RX65TO127OCTETS_GB)—Offset 1B0h” on page 372
00000000h
1B4h
1B7h
“MMC Receive 128 to 255 Octet Good Bad Frame Counter Register
(RX128TO255OCTETS_GB)—Offset 1B4h” on page 372
00000000h
1B8h
1BBh
“MMC Receive 256 to 511 Octet Good Bad Frame Counter Register
(RX256TO511OCTETS_GB)—Offset 1B8h” on page 373
00000000h
1BCh
1BFh
“MMC Receive 512 to 1023 Octet Good Bad Frame Counter Register
(RX512TO1023OCTETS_GB)—Offset 1BCh” on page 373
00000000h
1C0h
1C3h
“MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Register
(RX1024TOMAXOCTETS_GB)—Offset 1C0h” on page 374
00000000h
1C4h
1C7h
“MMC Receive Unicast Good Frame Counter Register (RXUNICASTFRAMES_G)—Offset
1C4h” on page 374
00000000h
1C8h
1CBh
“MMC Receive Length Error Frame Counter Register (RXLENGTHERROR)—Offset 1C8h”
on page 374
00000000h
1CCh
1CFh
“MMC Receive Out Of Range Error Frame Counter Register (RXOUTOFRANGETYPE)—
Offset 1CCh” on page 375
00000000h
1D0h
1D3h
“MMC Receive Pause Frame Counter Register (RXPAUSEFRAMES)—Offset 1D0h” on
page 375
00000000h
1D4h
1D7h
“MMC Receive FIFO Overflow Frame Counter Register (RXFIFOOVERFLOW)—Offset
1D4h” on page 376
00000000h
1D8h
1DBh
“MMC Receive VLAN Good Bad Frame Counter Register (RXVLANFRAMES_GB)—Offset
1D8h” on page 376
00000000h
1DCh
1DFh
“MMC Receive Watchdog Error Frame Counter Register (RXWATCHDOGERROR)—Offset
1DCh” on page 377
00000000h
1E0h
1E3h
“MMC Receive Error Frame Counter Register (RXRCVERROR)—Offset 1E0h” on page 377 00000000h
1E4h
1E7h
“MMC Receive Control Frame Counter Register (RXCTRLFRAMES_G)—Offset 1E4h” on
page 378
00000000h
200h
203h
“MMC IPC Receive Checksum Offload Interrupt Mask Register
(MMC_IPC_INTR_MASK_RX)—Offset 200h” on page 378
00000000h
208h
20Bh
“MMC Receive Checksum Offload Interrupt Register (MMC_IPC_INTR_RX)—Offset 208h”
00000000h
on page 380
210h
213h
“MMC Receive IPV4 Good Frame Counter Register (RXIPV4_GD_FRMS)—Offset 210h”
on page 382
00000000h
214h
217h
“MMC Receive IPV4 Header Error Frame Counter Register (RXIPV4_HDRERR_FRMS)—
Offset 214h” on page 383
00000000h
218h
21Bh
“MMC Receive IPV4 No Payload Frame Counter Register (RXIPV4_NOPAY_FRMS)—Offset
00000000h
218h” on page 383
21Ch
21Fh
“MMC Receive IPV4 Fragmented Frame Counter Register (RXIPV4_FRAG_FRMS)—Offset
00000000h
21Ch” on page 384
220h
223h
“MMC Receive IPV4 UDP Checksum Disabled Frame Counter Register
(RXIPV4_UDSBL_FRMS)—Offset 220h” on page 384
00000000h
224h
227h
“MMC Receive IPV6 Good Frame Counter Register (RXIPV6_GD_FRMS)—Offset 224h”
on page 384
00000000h
228h
22Bh
“MMC Receive IPV6 Header Error Frame Counter Register (RXIPV6_HDRERR_FRMS)—
Offset 228h” on page 385
00000000h
22Ch
22Fh
“MMC Receive IPV6 No Payload Frame Counter Register (RXIPV6_NOPAY_FRMS)—Offset
00000000h
22Ch” on page 385
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
329
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Table 88.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
230h
233h
“MMC Receive UDP Good Frame Counter Register (RXUDP_GD_FRMS)—Offset 230h” on
00000000h
page 386
234h
237h
“MMC Receive UDP Error Frame Counter Register (RXUDP_ERR_FRMS)—Offset 234h” on
00000000h
page 386
238h
23Bh
“MMC Receive TCP Good Frame Counter Register (RXTCP_GD_FRMS)—Offset 238h” on
page 387
23Ch
23Fh
“MMC Receive TCP Error Frame Counter Register (RXTCP_ERR_FRMS)—Offset 23Ch” on
00000000h
page 387
240h
243h
“MMC Receive ICMP Good Frame Counter Register (RXICMP_GD_FRMS)—Offset 240h”
on page 388
244h
247h
“MMC Receive ICMP Error Frame Counter Register (RXICMP_ERR_FRMS)—Offset 244h”
00000000h
on page 388
250h
253h
“MMC Receive IPV4 Good Octet Counter Register (RXIPV4_GD_OCTETS)—Offset 250h”
on page 388
254h
257h
“MMC Receive IPV4 Header Error Octet Counter Register (RXIPV4_HDRERR_OCTETS)—
00000000h
Offset 254h” on page 389
258h
25Bh
“MMC Receive IPV4 No Payload Octet Counter Register (RXIPV4_NOPAY_OCTETS)—
Offset 258h” on page 389
00000000h
25Ch
25Fh
“MMC Receive IPV4 Fragmented Octet Counter Register (RXIPV4_FRAG_OCTETS)—
Offset 25Ch” on page 390
00000000h
260h
263h
“MMC Receive IPV4 UDP Checksum Disabled Octet Counter Register
(RXIPV4_UDSBL_OCTETS)—Offset 260h” on page 390
00000000h
264h
267h
“MMC Receive IPV6 Good Octet Counter Register (RXIPV6_GD_OCTETS)—Offset 264h”
on page 391
00000000h
268h
26Bh
“MMC Receive IPV6 Good Octet Counter Register (RXIPV6_HDRERR_OCTETS)—Offset
268h” on page 391
00000000h
26Ch
26Fh
“MMC Receive IPV6 Header Error Octet Counter Register (RXIPV6_NOPAY_OCTETS)—
Offset 26Ch” on page 392
00000000h
270h
273h
“MMC Receive IPV6 No Payload Octet Counter Register (RXUDP_GD_OCTETS)—Offset
270h” on page 392
00000000h
274h
277h
“MMC Receive UDP Good Octet Counter Register (RXUDP_ERR_OCTETS)—Offset 274h”
on page 392
00000000h
278h
27Bh
“MMC Receive TCP Good Octet Counter Register (RXTCP_GD_OCTETS)—Offset 278h” on
00000000h
page 393
27Ch
27Fh
“MMC Receive TCP Error Octet Counter Register (RXTCP_ERR_OCTETS)—Offset 27Ch”
on page 393
280h
283h
“MMC Receive ICMP Good Octet Counter Register (RXICMP_GD_OCTETS)—Offset 280h”
00000000h
on page 394
284h
287h
“MMC Receive ICMP Error Octet Counter Register (RXICMP_ERR_OCTETS)—Offset
284h” on page 394
584h
587h
“VLAN Tag Inclusion or Replacement Register (Register 353) (GMAC_REG_353)—Offset
00000000h
584h” on page 395
588h
58Bh
“VLAN Hash Table Register (Register 354) (GMAC_REG_354)—Offset 588h” on
page 396
00000000h
700h
703h
“Timestamp Control Register (Register 448) (GMAC_REG_448)—Offset 700h” on
page 396
00002000h
704h
707h
“Sub-Second Increment Register (Register 449) (GMAC_REG_449)—Offset 704h” on
page 398
00000000h
708h
70Bh
“System Time - Seconds Register (Register 450) (GMAC_REG_450)—Offset 708h” on
page 398
00000000h
Intel® Quark™ SoC X1000
Datasheet
330
00000000h
00000000h
00000000h
00000000h
00000000h
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Table 88.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
70Ch
70Fh
“System Time - Nanoseconds Register (Register 451) (GMAC_REG_451)—Offset 70Ch”
00000000h
on page 399
710h
713h
“System Time - Seconds Update Register (Register 452) (GMAC_REG_452)—Offset
710h” on page 399
714h
717h
“System Time - Nanoseconds Update Register (Register 453) (GMAC_REG_453)—Offset
00000000h
714h” on page 400
718h
71Bh
“Timestamp Addend Register (Register 454) (GMAC_REG_454)—Offset 718h” on
page 400
00000000h
71Ch
71Fh
“Target Time Seconds Register (Register 455) (GMAC_REG_455)—Offset 71Ch” on
page 401
00000000h
720h
723h
“Target Time Nanoseconds Register (Register 456) (GMAC_REG_456)—Offset 720h” on
00000000h
page 401
724h
727h
“System Time - Higher Word Seconds Register (Register 457) (GMAC_REG_457)—
Offset 724h” on page 402
00000000h
728h
72Bh
“Timestamp Status Register (Register 458) (GMAC_REG_458)—Offset 728h” on
page 403
00000000h
00020101h
00000000h
1000h
1003h
“Bus Mode Register (Register 0) (DMA_REG_0)—Offset 1000h” on page 404
1004h
1007h
“Transmit Poll Demand Register (Register 1) (DMA_REG_1)—Offset 1004h” on page 406 00000000h
1008h
100Bh
“Receive Poll Demand Register (Register 2) (DMA_REG_2)—Offset 1008h” on page 406 00000000h
100Ch
100Fh
“Receive Descriptor List Address Register (Register 3) (DMA_REG_3)—Offset 100Ch” on
00000000h
page 407
1010h
1013h
“Transmit Descriptor List Address Register (Register 4) (DMA_REG_4)—Offset 1010h”
on page 407
00000000h
1014h
1017h
“Status Register (Register 5) (DMA_REG_5)—Offset 1014h” on page 408
00000000h
1018h
101Bh
“Operation Mode Register (Register 6) (DMA_REG_6)—Offset 1018h” on page 411
00000000h
101Ch
101Fh
“Interrupt Enable Register (Register 7) (DMA_REG_7)—Offset 101Ch” on page 414
00000000h
1020h
1023h
“Missed Frame and Buffer Overflow Counter Register (Register 8) (DMA_REG_8)—Offset
00000000h
1020h” on page 415
1024h
1027h
“Receive Interrupt Watchdog Timer Register (Register 9) (DMA_REG_9)—Offset 1024h”
00000000h
on page 416
102Ch
102Fh
“AHB Status Register (Register 11) (DMA_REG_11)—Offset 102Ch” on page 416
00000000h
1048h
104Bh
“Current Host Transmit Descriptor Register (Register 18) (DMA_REG_18)—Offset
1048h” on page 417
00000000h
104Ch
104Fh
“Current Host Receive Descriptor Register (Register 19) (DMA_REG_19)—Offset 104Ch”
00000000h
on page 417
1050h
1053h
“Current Host Transmit Buffer Address Register (Register 20) (DMA_REG_20)—Offset
1050h” on page 418
00000000h
1054h
1057h
“Current Host Receive Buffer Address Register (Register 21) (DMA_REG_21)—Offset
1054h” on page 418
00000000h
1058h
105Bh
“HW Feature Register (Register 22) (DMA_REG_22)—Offset 1058h” on page 419
4B0F3915h
15.6.1
MAC Configuration Register (Register 0) (GMAC_REG_0)—
Offset 0h
The MAC Configuration register establishes receive and transmit operating modes.
Access Method
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
331
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00008000h
Bit
Range
31
30:28
27
26:24
Default &
Access
0b
RO
0
0
0
0
0
0
0
0
PRELEN
0
TE
0
RE
0
0
DC
0
BL
0
ACS
0
DR
0
4
LUD
1
IPC
0
LM
0
8
DM
0
DO
0
FES
0
RSV0
0
12
DCRS
0
16
IFG
0
JE
0
JD
0
BE
0
WD
0
20
Field Name (ID): Description
Reserved (RSV3): Reserved.
000b
RW
Source Address Insertion or Replacement Control (SARC): This field controls the
source address insertion or replacement for all transmitted frames.
When Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers
(registers 16 and 17) in the SA field of all transmitted frames based on the values of Bits
[29:28]:
- 2b0x: SA insertion is controlled by the internal signal from the MTL layer.
- 2b10: if Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers
(registers 16 and 17) in the SA field of all transmitted frames.
- 2b11: if Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers
(registers 16 and 17) in the SA field of all transmitted frames.
NOTE:Changes to this field take effect only on the start of a frame. If you write this
register field when a frame is being transmitted, only the subsequent frame can use the
updated value, that is, the current frame does not use the updated value.
0b
RW
IEEE 802.3as support for 2K packets Enable (PE2K): When set, the MAC considers
all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (Jumbo
Enable) is not set, the MAC considers all received frames of size more than 2K bytes as
Giant frames. When this bit is reset and Bit 20 (Jumbo Enable) is not set, the MAC
considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as
Giant frames. When Bit 20 (Jumbo Enable) is set, setting this bit has no effect on Giant
Frame status.
000b
RO
Reserved (RSV1): Reserved.
23
0b
RW
Watchdog Disable (WD): When this bit is set, the MAC disables the watchdog timer
on the receiver. The MAC can receive frames of up to 16,384 bytes.
When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set
high) of the frame being received. The MAC cuts off any bytes received after 2,048
bytes.
22
0b
RW
Jabber Disable (JD): When this bit is set, the MAC disables the jabber timer on the
transmitter. The MAC can transfer frames of up to 16,384 bytes. When this bit is reset,
the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of
data (10,240 if JE is set high) during transmission.
21
0b
RW
Reserved (BE): Reserved.
20
0b
RW
Jumbo Frame Enable (JE): When this bit is set, the MAC allows Jumbo frames of
9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error
in the receive frame status.
000b
RW
Inter-Frame Gap (IFG): These bits control the minimum IFG between frames during
transmission.
000: 96 bit times
001: 88 bit times
010: 80 bit times
111: 40 bit times
In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG
= 100). Lower values are not considered.
19:17
Intel® Quark™ SoC X1000
Datasheet
332
0
24
RSV1
0
SARC
0
RSV3
0
28
PE2K
31
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
16
0b
RW
Disable Carrier Sense During Transmission (DCRS): When set high, this bit makes
the MAC transmitter ignore the MII CRS signal during frame transmission in the halfduplex mode. This request results in no errors generated because of Loss of Carrier or
No Carrier during such transmission. When this bit is low, the MAC transmitter
generates such errors because of Carrier Sense and can even abort the transmissions.
15
1b
RO
GMII/MII configuration (RSV0): This bit identifies the supported interface:
0: GMII (1000 Mbps)
1: MII (10/100 Mbps)
14
0b
RW
RMII Speed (FES): This bit selects the speed in the RMII interface:
0: 10 Mbps
1: 100 Mbps
13
0b
RW
Disable Receive Own (DO): When this bit is set, the MAC disables the reception of
frames when the gmii_txen_o is asserted in the half-duplex mode. When this bit is
reset, the MAC receives all packets that are given by the PHY while transmitting.
This bit is not applicable if the MAC is operating in the full-duplex mode.
12
0b
RW
Loopback Mode (LM): When this bit is set, the MAC operates in the loopback mode at
MII.
11
0b
RW
Duplex Mode (DM): When this bit is set, the MAC operates in the full-duplex mode
where it can transmit and receive simultaneously.
0b
RW
Checksum Offload (IPC): When this bit is set, the MAC calculates the 16-bit ones
complement of the ones complement sum of all received Ethernet frame payloads. It
also checks whether the IPv4 Header checksum (assumed to be bytes 2526 or 2930
(VLAN-tagged) of the received Ethernet frame) is correct for the received frame and
gives the status in the receive status word. The MAC also appends the 16-bit checksum
calculated for the IP header datagram payload (bytes after the IPv4 header) and
appends it to the Ethernet frame transferred to the application (when Type 2 COE is
deselected).
When this bit is reset, this function is disabled.
As Type 2 COE (Checksum Offload Engine) is supported, this bit, when set, enables the
IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum
checking. When this bit is reset, the COE function in the receiver is disabled and the
corresponding PCE and IP HCE status bits are always cleared.
9
0b
RW
Disable Retry (DR): When this bit is set, the MAC attempts only one transmission.
When a collision occurs on the MII interface, the MAC ignores the current frame
transmission and reports a Frame Abort with excessive collision error in the transmit
frame status.
When this bit is reset, the MAC attempts retries based on the settings of the BL field
(Bits [6:5]). This bit is applicable only in the half-duplex mode.
8
0b
RO
Reserved (LUD): Reserved.
7
0b
RW
Automatic Pad or CRC Stripping (ACS): When this bit is set, the MAC strips the Pad
or FCS (Frame Check Sequence) field on the incoming frames only if the value of the
length field is less than 1,536 bytes. All received frames with length field greater than or
equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field.
When this bit is reset, the MAC passes all incoming frames, without modifying them, to
the Host.
00b
RW
Back-Off Limit (BL): The Back-Off limit determines the random integer number (r) of
slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before
rescheduling a transmission attempt during retries after a collision. This bit is applicable
only in the half-duplex mode.
00: k = min (n, 10)
01: k = min (n, 8)
10: k = min (n, 4)
11: k = min (n, 1)
where n = retransmission attempt. The random integer r takes the value in the range 0
(= r ( kth power of 2
10
6:5
November 2014
Document Number: 329676-004US
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Datasheet
333
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
Field Name (ID): Description
4
0b
RW
Deferral Check (DC): When this bit is set, the deferral check function is enabled in the
MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit
set in the transmit frame status, when the transmit state machine is deferred for more
than 24,288 bit times in the 10 or 100 Mbps mode. If the Jumbo frame mode is enabled
in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral
begins when the transmitter is ready to transmit, but is prevented because of an active
carrier sense signal (CRS) on MII. Defer time is not cumulative. When the transmitter
defers for 10,000 bit times, it transmits, collides, backs off, and then defers again after
completion of back-off. The deferral timer resets to 0 and restarts.
When this bit is reset, the deferral check function is disabled and the MAC defers until
the CRS signal goes inactive. This bit is applicable only in the half-duplex mode.
3
0b
RW
Transmitter Enable (TE): When this bit is set, the transmit state machine of the MAC
is enabled for transmission on the MII. When this bit is reset, the MAC transmit state
machine is disabled after the completion of the transmission of the current frame, and
does not transmit any further frames.
2
0b
RW
Receiver Enable (RE): When this bit is set, the receiver state machine of the MAC is
enabled for receiving frames from the MII. When this bit is reset, the MAC receive state
machine is disabled after the completion of the reception of the current frame, and does
not receive any further frames from the MII.
00b
RW
Preamble Length for Transmit Frames (PRELEN): These bits control the number of
preamble bytes that are added to the beginning of every Transmit frame. The preamble
reduction occurs only when the MAC is operating in the full-duplex mode.
2'b00: 7 bytes of preamble
2'b01: 5 byte of preamble
2'b10: 3 bytes of preamble
2'b11: reserved
1:0
15.6.2
MAC Frame Filter (Register 1) (GMAC_REG_1)—Offset 4h
The MAC Frame Filter register contains the filter controls for receiving frames. Some of
the controls from this register go to the address check block of the MAC, which
performs the first level of address filtering. The second level of filtering is performed on
the incoming frame, based on other controls such as Pass Bad Frames and Pass Control
Frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR
0
HUC
0
HMC
0
PM
0
DAIF
0
0
DBF
0
4
PCF
0
8
SAF
0
12
SAIF
0
16
HPF
0
20
RSV0
0
RSV1
0
24
RA
0
28
VTFE
31
Default &
Access
Field Name (ID): Description
31
0b
RW
Receive All (RA): When this bit is set, the MAC Receiver module passes all received
frames, irrespective of whether they pass the address filter or not, to the Application.
The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in
the Receive Status Word.
When this bit is reset, the Receiver module passes only those frames to the Application
that pass the SA or DA address filter.
30:17
0b
RO
Reserved (RSV1): Reserved.
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Datasheet
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November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Default &
Access
Bit
Range
16
15:11
0b
RW
00000b
RO
Field Name (ID): Description
VLAN Tag Filter Enable (VTFE): When set, this bit enables the MAC to drop VLAN
tagged frames that do not match the VLAN Tag comparison.
When reset, the MAC forwards all frames irrespective of the match status of the VLAN
Tag.
Reserved (RSV0): Reserved.
10
0b
RW
Hash or Perfect Filter (HPF): When this bit is set, it configures the address filter to
pass a frame if it matches either the perfect filtering or the hash filtering as set by the
HMC or HUC bits.
When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches
the Hash filter.
9
0b
RW
Source Address Filter Enable (SAF): When this bit is set, the MAC compares the SA
field of the received frames with the values programmed in the enabled SA registers. If
the comparison matches, then the SA Match bit of RxStatus Word is set high. When this
bit is set high and the SA filter fails, the MAC drops the frame.
When this bit is reset, the MAC forwards the received frame to the application and with
the updated SA Match bit of the RxStatus depending on the SA address comparison.
8
0b
RW
SA Inverse Filtering (SAIF): When this bit is set, the Address Check block operates in
inverse filtering mode for the SA address comparison. The frames whose SA matches
the SA registers are marked as failing the SA Address filter.
When this bit is reset, frames whose SA does not match the SA registers are marked as
failing the SA Address filter.
7:6
00b
RW
Pass Control Frames (PCF): These bits control the forwarding of all control frames
(including unicast and multicast PAUSE frames).
00: MAC filters all control frames from reaching the application.
01: MAC forwards all control frames except PAUSE control frames to application even if
they fail the Address filter.
10: MAC forwards all control frames to application even if they fail the Address Filter.
11: MAC forwards control frames that pass the Address Filter.
The following conditions should be true for the PAUSE control frames processing:
Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting
Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.
Condition 2: The destination address (DA) of the received frame matches the special
multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control
Register) is set.
Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is
0x0001.
NOTE:
This field should be set to 01 only when the Condition 1 is true, that is, the MAC is
programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise,
the PAUSE frame filtering may be inconsistent. When Condition 1 is false, the PAUSE
frames are considered as generic control frames. Therefore, to pass all control frames
(including PAUSE control frames) when the full-duplex mode and flow control is not
enabled, you should set the PCF field to 10 or 11 (as required by the application).
5
0b
RW
Disable Broadcast Frames (DBF): When this bit is set, the AFM module filters all
incoming broadcast frames. In addition, it overrides all other filter settings.
When this bit is reset, the AFM module passes all received broadcast frames.
4
0b
RW
Pass All Multicast (PM): When set, this bit indicates that all received frames with a
multicast destination address (first bit in the destination address field is '1') are passed.
When reset, filtering of multicast frame depends on HMC bit.
3
0b
RW
DA Inverse Filtering (DAIF): When this bit is set, the Address Check block operates
in inverse filtering mode for the DA address comparison for both unicast and multicast
frames.
When reset, normal filtering of frames is performed.
2
0b
RW
Hash Multicast (HMC): When set, MAC performs destination address filtering of
received multicast frames according to the hash table.
When reset, the MAC performs a perfect destination address filtering for multicast
frames, that is, it compares the DA field with the values programmed in DA registers.
1
0b
RW
Hash Unicast (HUC): When set, MAC performs destination address filtering of unicast
frames according to the hash table.
When reset, the MAC performs a perfect destination address filtering for unicast frames,
that is, it compares the DA field with the values programmed in DA registers.
November 2014
Document Number: 329676-004US
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
15.6.3
Promiscuous Mode (PR): When this bit is set, the Address Filter module passes all
incoming frames regardless of its destination or source address. The SA or DA Filter
Fails status bits of the Receive Status Word are always cleared when PR is set.
0b
RW
0
Field Name (ID): Description
Hash Table High Register (Register 2) (GMAC_REG_2)—Offset
8h
The Hash Table High register contains the higher 32 bits of the Hash table. The 64-bit
Hash table is used for group address filtering. For hash filtering, the contents of the
destination address in the incoming frame is passed through the CRC logic, and the
upper 6 bits of the CRC register are used to index the contents of the Hash table. The
most significant bit determines the register to be used (Hash Table High or Hash Table
Low), and the other 5 bits determine which bit within the register. A hash value of
5b'00000 selects Bit 0 of the selected register, and a value of 5b'11111 selects Bit 31 of
the selected register. The hash value of the destination address is calculated in the
following way: 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8
for the steps to calculate CRC32). 2. Perform bitwise reversal for the value obtained in
Step 1. 3. Take the upper 6 bits from the value obtained in Step 2. For example, if the
DA of the incoming frame is received as 0x1F52419CB6AF (0x1F is the first byte
received on MII interface), then the internally calculated 6-bit Hash value is 0x2C and
Bit 12 of Hash Table High register is checked for filtering. If the DA of the incoming
frame is received as 0xA00A98000045, then the calculated 6-bit Hash value is 0x07
and Bit 7 of Hash Table Low register is checked for filtering. If the corresponding bit
value of the register is 1'b1, the frame is accepted. Otherwise, it is rejected. If the PM
(Pass All Multicast) bit is set in Register 1, then all multicast frames are accepted
regardless of the multicast hash values.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
HTH
0
28
Bit
Range
31:0
15.6.4
Default &
Access
Field Name (ID): Description
00000000h
Hash Table High (HTH): This field contains the upper 32 bits of the Hash table.
RW
Hash Table Low Register (Register 3) (GMAC_REG_3)—Offset
Ch
The Hash Table Low register contains the lower 32 bits of the Hash table.
Access Method
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Datasheet
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November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
HTL
0
28
Bit
Range
31:0
15.6.5
Default &
Access
Field Name (ID): Description
00000000h
Hash Table Low (HTL): This field contains the lower 32 bits of the Hash table.
RW
GMII Address Register (Register 4) (GMAC_REG_4)—Offset 10h
The GMII Address register controls the management cycles to the external PHY through
the management interface.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 10h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
12
0
0
PA
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
GB
0
16
GW
0
20
CR
0
24
RSV0
0
28
GR
31
Field Name (ID): Description
31:16
0000h
RO
15:11
00000b
RW
Physical Layer Address (PA): This field indicates which of the 32 possible PHY
devices are being accessed.
10:6
00000b
RW
GMII Register (GR): These bits select the desired GMII register in the selected PHY
device.
November 2014
Document Number: 329676-004US
Reserved (RSV0): Reserved.
Intel® Quark™ SoC X1000
Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
Field Name (ID): Description
0000b
RW
CSR Clock Range (CR): The CSR Clock Range selection determines the frequency of
the serial management clock (MDC) according to the system clock (clk_csr_i) frequency
used in your design, which is 133MHz. When Bit[5] = 0 allowed values are:
- 0001: The frequency of the clk_csr_i clock is 100-150 MHz and the MDC clock is
clk_csr_i/62.
- 0010: The frequency of the clk_csr_i clock is 20-35 MHz and the MDC clock is
clk_csr_i/16.
- 0011: The frequency of the clk_csr_i clock is 35-60 MHz and the MDC clock is
clk_csr_i/26.
- 0100: The frequency of the clk_csr_i clock is 150-250 MHz and the MDC clock is
clk_csr_i/102.
- 0100: The frequency of the clk_csr_i clock is 250-300 MHz and the MDC clock is
clk_csr_i/124.
- 0110 and 0111: Reserved
Based on a system clock of 133MHz, the CR value that ensures the MDC clock is
approximately between the frequency range 1.0 MHz - 2.5 MHz is 0010
When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3
specified frequency limit of 2.5 MHz and program a clock divider of lower value.
Program the following values only if the interfacing chips support faster MDC clocks:
- 1000: clk_csr_i/4
- 1001: clk_csr_i/6
- 1010: clk_csr_i/8
- 1011: clk_csr_i/10
- 1100: clk_csr_i/12
- 1101: clk_csr_i/14
- 1110: clk_csr_i/16
- 1111: clk_csr_i/18
0b
RW
GMII Write (GW): When set, this bit indicates to the PHY that this is a Write operation
using the GMII Data register. If this bit is not set, it indicates that this is a Read
operation, that is, placing the data in the GMII Data register.
0b
RW
GMII Busy (GB): This bit should read logic 0 before writing to Register 4 and Register
5. During a PHY register access, the software sets this bit to 1'b1 to indicate that a Read
or Write access is in progress.
The Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII
Data) should be kept valid until the MAC clears this bit during a PHY Write operation.
Similarly for a read operation, the contents of Register 5 are not valid until this bit is
cleared.
The subsequent read or write operation should happen only after the previous operation
is complete. Because there is no acknowledgment from the PHY to MAC after a read or
write operation is completed, there is no change in the functionality of this bit even
when the PHY is not present.
5:2
1
0
15.6.6
GMII Data Register (Register 5) (GMAC_REG_5)—Offset 14h
The GMII Data register stores Write data to be written to the PHY register located at
the address specified in Register 4 (GMII Address Register). This register also stores
the Read data from the PHY register located at the address specified by Register 4.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 14h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
RSV0
0
28
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Datasheet
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20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
GD
31
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
15.6.7
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Reserved (RSV0): Reserved.
15:0
0000h
RW
GMII Data (GD): This field contains the 16-bit data value read from the PHY after a
Management Read operation or the 16-bit data value to be written to the PHY before a
Management Write operation.
Flow Control Register (Register 6) (GMAC_REG_6)—Offset 18h
The Flow Control register controls the generation and reception of the Control (Pause
Command) frames by the MAC's Flow control module. A Write to a register with the
Busy bit set to '1' triggers the Flow Control block to generate a Pause Control frame.
The fields of the control frame are selected as specified in the 802.3x specification, and
the Pause Time value from this register is used in the Pause Time field of the control
frame. The Busy bit remains set until the control frame is transferred onto the cable.
The Host must make sure that the Busy bit is cleared before writing to the register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 18h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:16
0000h
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFE
0
0
FCB_BPA
0
4
UP
0
8
RFE
0
12
PLT
0
16
RSV0
0
20
DZPQ
0
24
PT
0
28
RSV1
31
Field Name (ID): Description
Pause Time (PT): This field holds the value to be used in the Pause Time field in the
transmit control frame. If the Pause Time bits is configured to be double-synchronized
to the MII clock domain, then consecutive writes to this register should be performed
only after at least four clock cycles in the destination clock domain.
15:8
00h
RO
Reserved (RSV1): Reserved.
7
0b
RW
Disable Zero-Quanta Pause (DZPQ): When this bit is set, it disables the automatic
generation of the Zero-Quanta Pause Control frames on the de-assertion of the flowcontrol signal from the FIFO layer. When this bit is reset, normal operation with
automatic Zero-Quanta Pause Control frame generation is enabled.
6
0b
RO
Reserved (RSV0): Reserved.
November 2014
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
Field Name (ID): Description
5:4
00b
RW
Pause Low Threshold (PLT): This field configures the threshold of the PAUSE timer at
which the flow-control signal from the FIFO layer is checked for automatic
retransmission of PAUSE Frame.
The threshold values should be always less than the Pause Time configured in
Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second
PAUSE frame is automatically transmitted if the flow-control signal from the FIFO layer
is asserted at 228 (256 - 28) slot times after the first PAUSE frame is transmitted.
The following list provides the threshold values for different values:
00: The threshold is Pause time minus 4 slot times (PT - 4 slot times).
01: The threshold is Pause time minus 28 slot times (PT - 28 slot times).
10: The threshold is Pause time minus 144 slot times (PT - 144 slot times).
11: The threshold is Pause time minus 256 slot times (PT - 256 slot times).
The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII
interface.
3
0b
RW
Unicast Pause Frame Detect (UP): When this bit is set, then in addition to the
detecting Pause frames with the unique multicast address, the MAC detects the Pause
frames with the station's unicast address specified in the MAC Address0 High Register
and MAC Address0 Low Register. When this bit is reset, the MAC detects only a Pause
frame with the unique multicast address specified in the 802.3x standard.
2
0b
RW
Receive Flow Control Enable (RFE): When this bit is set, the MAC decodes the
received Pause frame and disables its transmitter for a specified (Pause) time. When
this bit is reset, the decode function of the Pause frame is disabled.
0b
RW
Transmit Flow Control Enable (TFE): In the full-duplex mode, when this bit is set,
the MAC enables the flow control operation to transmit Pause frames. When this bit is
reset, the flow control operation in the MAC is disabled, and the MAC does not transmit
any Pause frames.
In half-duplex mode, when this bit is set, the MAC enables the back-pressure operation.
When this bit is reset, the back-pressure feature is disabled.
0b
RW
Flow Control Busy or Backpressure Activate (FCB_BPA): This bit initiates a Pause
Control frame in the full-duplex mode and activates the backpressure function in the
half-duplex mode if the TFE bit is set.
In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow
Control register. To initiate a Pause control frame, the Application must set this bit to
1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a
frame transmission is in progress. After the completion of Pause control frame
transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be
written to until this bit is cleared.
In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is
asserted by the MAC. During backpressure, when the MAC receives a new frame, the
transmitter starts sending a JAM pattern resulting in a collision. This control register bit
is logically ORed with the flow-control signal from the FIFO layer for the backpressure
function. When the MAC is configured for the full-duplex mode, the BPA is automatically
disabled.
1
0
15.6.8
VLAN Tag Register (Register 7) (GMAC_REG_7)—Offset 1Ch
The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames.
The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with
16'h8100, and the following two bytes are compared with the VLAN tag. If a match
occurs, the MAC sets the received VLAN bit in the receive frame status. The legal length
of the frame is increased from 1,518 bytes to 1,522 Bytes.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
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Datasheet
340
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
0
0
0
0
0
0
Bit
Range
31:20
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
Reserved (RSV0): Reserved.
19
0b
RW
VLAN Tag Hash Table Match Enable (VTHM): When set, the most significant four
bits of the VLAN tags CRC are used to index the content of Register 354 (VLAN Hash
Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the
index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set,
the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is
reset, the CRC of the 16-bit VLAN tag is used for comparison.
When reset, the VLAN Hash Match operation is not performed.
18
0b
RW
Enable S-VLAN (ESVL): When this bit is set, the MAC transmitter and receiver also
consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames.
17
0b
RW
VLAN Tag Inverse Match Enable (VTIM): When set, this bit enables the VLAN Tag
inverse matching. The frames that do not have matching VLAN Tag are marked as
matched.
When reset, this bit enables the VLAN Tag perfect matching. The frames with matched
VLAN Tag are marked as matched.
0b
RW
Enable 12-Bit VLAN Tag Comparison (ETV): When this bit is set, a 12-bit VLAN
identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag.
Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLANtagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received
frame are used for hash-based VLAN filtering.
When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame
are used for comparison and VLAN hash filtering.
0000h
RW
VLAN Tag Identifier for Receive Frames (VL): This field contains the 802.1Q VLAN
tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the
frames being received for VLAN frames. The following list describes the bits of this field:
Bits [15:13]: User Priority
Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
Bits[11:0]: VLAN tag's VLAN Identifier (VID) field
When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL
(VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes
for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or
0x88a8 as VLAN frames.
16
15:0
15.6.9
Default &
Access
000h
RO
0
8
VL
0
12
ETV
0
16
ESVL
0
20
VTIM
0
24
RSV0
0
28
VTHM
31
Version Register (Register 8) (GMAC_REG_8)—Offset 20h
The Version registers identifies the version of the MAC. This register contains two
bytes: one identifies the core IP release number, and the other that identifies the user
release.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 20h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00001037h
November 2014
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
0
0
0
24
0
0
0
20
0
0
0
0
0
16
0
0
0
0
12
0
0
0
1
Bit
Range
Default &
Access
0000h
RO
31:16
15.6.10
8
0
0
0
0
4
0
0
1
USERVER
RSV0
0
28
0
1
0
1
1
1
SNPSVER
31
Field Name (ID): Description
RSV0: Reserved
15:8
10h
RO
User-defined Version (1.0) (USERVER): Reserved.
7:0
37h
RO
Synopsys-defined Version (3.7) (SNPSVER): Reserved.
Debug Register (Register 9) (GMAC_REG_9)—Offset 24h
The Debug register gives the status of all main modules of the transmit and receive
data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and
FIFOs are empty) and no activity is going on in the data-paths.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 24h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
31:25
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RPESTS
0
RFCFCSTS
0
RSV0
0
0
RWCSTS
0
RRCSTS
0
4
RSV1
0
8
RXFSTS
0
12
RSV2
0
TPESTS
0
TFCSTS
0
16
TXPAUSED
0
TRCSTS
0
TWCSTS
0
20
RSV3
0
24
RSV4
0
28
TXFSTS
31
Field Name (ID): Description
0000000b
Reserved (RSV4): Reserved.
RO
24
0b
RO
MTL Tx FIFO Not Empty Status (TXFSTS): When high, this bit indicates that the MTL
Tx FIFO is not empty and some data is left for transmission.
23
0b
RO
Reserved (RSV3): Reserved.
22
0b
RO
MTL Tx FIFO Write Controller Active Status (TWCSTS): When high, this bit
indicates that the MTL Tx FIFO Write Controller is active and transferring data to the Tx
FIFO.
21:20
00b
RO
MTL Tx FIFO Read Controller Status (TRCSTS): This field indicates the state of the
Tx FIFO Read Controller:
00: IDLE state
01: READ state (transferring data to MAC transmitter)
10: Waiting for TxStatus from MAC transmitter
11: Writing the received TxStatus or flushing the Tx FIFO
Intel® Quark™ SoC X1000
Datasheet
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November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0b
RO
MAC transmitter in PAUSE (TXPAUSED): When high, this bit indicates that the MAC
transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not
schedule any frame for transmission.
18:17
00b
RO
MAC Transmit Frame Controller Status (TFCSTS): This field indicates the state of
the MAC Transmit Frame Controller module:
00: IDLE state
01: Waiting for Status of previous frame or IFG or backoff period to be over
10: Generating and transmitting a PAUSE control frame (in the full-duplex mode)
11: Transferring input frame for transmission
16
0b
RO
MAC MII Transmit Protocol Engine Status (TPESTS): When high, this bit indicates
that the MAC MII transmit protocol engine is actively transmitting data and is not in the
IDLE state.
19
15:10
15.6.11
000000b
RO
Reserved (RSV2): Reserved.
9:8
00b
RO
MTL Rx FIFO Fill-level Status (RXFSTS): This field gives the status of the fill-level of
the Rx FIFO:
00: Rx FIFO Empty
01: Rx FIFO fill level is below the flow-control deactivate threshold
10: Rx FIFO fill level is above the flow-control activate threshold
11: Rx FIFO Full
7
0b
RO
Reserved (RSV1): Reserved.
6:5
00b
RO
MTL Rx FIFO Read Controller State (RRCSTS): This field gives the state of the Rx
FIFO read Controller:
00: IDLE state
01: Reading frame data
10: Reading frame status (or timestamp)
11: Flushing the frame data and status
4
0b
RO
MTL Rx FIFO Write Controller Active Status (RWCSTS): When high, this bit
indicates that the MTL Rx FIFO Write Controller is active and is transferring a received
frame to the FIFO.
3
0b
RO
Reserved (RSV0): Reserved.
2:1
00b
RO
MAC Receive Frame Controller FIFO Status (RFCFCSTS): When high, this field
indicates the active state of the small FIFO Read and Write controllers of the MAC
Receive Frame Controller Module.
0
0b
RO
MAC MII Receive Protocol Engine Status (RPESTS): When high, this bit indicates
that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.
Interrupt Register (Register 14) (GMAC_REG_14)—Offset 38h
The Interrupt Status register identifies the events in the MAC that can generate
interrupt.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 38h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
343
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
000000h
RO
31:10
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
Reserved (RSV4): Reserved.
9
0b
RO
Timestamp Interrupt Status (TSIS): When the Advanced Timestamp feature is
enabled, this bit is set when any of the following conditions is true:
The system time value equals or exceeds the value specified in the Target Time High
and Low registers.
There is an overflow in the seconds register.
The Auxiliary snapshot trigger is asserted.
This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status Register).
If default Timestamping is enabled, when set, this bit indicates that the system time
value is equal to or exceeds the value specified in the Target Time registers. In this
mode, this bit is cleared after the completion of the read of this bit. In all other modes,
this bit is reserved.
8
0b
RO
Reserved (RSV2): Reserved.
7
0b
RO
MMC Receive Checksum Offload Interrupt Status (MMCRXIPIS): This bit is set
high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt
Register. This bit is cleared when all the bits in this interrupt register are cleared.
6
0b
RO
MMC Transmit Interrupt Status (MMCTXIS): This bit is set high when an interrupt is
generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in
this interrupt register are cleared.
5
0b
RO
MMC Receive Interrupt Status (MMCRXIS): This bit is set high when an interrupt is
generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in
this interrupt register are cleared.
4
0b
RO
MMC Interrupt Status (MMCIS): This bit is set high when any of the Bits [7:5] is set
high and cleared only when all of these bits are low.
0000b
RO
3:0
15.6.12
0
0
RSV0
0
4
MMCIS
0
8
MMCTXIS
0
12
MMCRXIS
0
16
MMCRXIPIS
0
20
TSIS
0
24
RSV4
0
28
RSV2
31
Reserved (RSV0): Reserved.
Interrupt Mask Register (Register 15) (GMAC_REG_15)—Offset
3Ch
The Interrupt Mask Register bits enable you to mask the interrupt signal because of the
corresponding event in the Interrupt Status Register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 3Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
Intel® Quark™ SoC X1000
Datasheet
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0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RSV0
0
24
RSV3
0
28
TSIM
31
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
000000h
RO
31:10
15.6.13
Field Name (ID): Description
Reserved (RSV3): Reserved.
9
0b
RW
Timestamp Interrupt Mask (TSIM): When set, this bit disables the assertion of the
interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14
(Interrupt Status Register). This bit is valid only when IEEE1588 timestamping is
enabled. In all other modes, this bit is reserved.
8:0
0b
RO
Reserved (RSV0): Reserved.
MAC Address0 High Register (Register 16) (GMAC_REG_16)—
Offset 40h
The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address
of the station. The first DA byte that is received on the MII interface corresponds to the
LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566
is received (0x11 in lane 0 of the first column) on the MII as the destination address,
then the MacAddress0 Register [47:0] is compared with 0x665544332211. Using the
standard IEEE 802 format for printing MAC-48 addresses this corresponds to
11:22:33:44:55:66 where 0x11 is the LS byte (Bits [7:0]) of the MAC Address Low
register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 40h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 8000FFFFh
0
0
0
24
0
0
0
Bit
Range
31
30:16
15:0
15.6.14
0
20
0
0
0
0
16
0
0
0
0
12
1
1
1
1
8
1
RSV0
AE
1
28
Default &
Access
1b
RO
0000h
RO
ffffh
RW
1
1
1
4
1
1
1
1
0
1
1
1
1
ADDRHI
31
Field Name (ID): Description
Address Enable (AE): This bit is always set to 1.
Reserved (RSV0): Reserved.
MAC Address0 High (ADDRHI): This field contains the upper 16 bits (47:32) of the
first 6-byte MAC address. The MAC uses this field for filtering the received frames and
inserting the MAC address in the Transmit Flow Control (PAUSE) Frames.
MAC Address0 Low Register (Register 17) (GMAC_REG_17)—
Offset 44h
The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC address
of the station.
Access Method
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 44h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: FFFFFFFFh
31
1
1
1
24
1
1
1
1
20
1
1
1
1
16
1
1
1
1
12
1
1
1
1
8
1
1
1
1
4
1
1
1
1
0
1
1
1
1
ADDRLO
1
28
Bit
Range
Default &
Access
Field Name (ID): Description
ffffffffh
RW
MAC Address0 Low (ADDRLO): This field contains the lower 32 bits of the first 6-byte
MAC address. This is used by the MAC for filtering the received frames and inserting the
MAC address in the Transmit Flow Control (PAUSE) Frames.
31:0
15.6.15
MMC Control Register (Register 64) (GMAC_REG_64)—Offset
100h
The MMC Control register establishes the operating mode of the management counters.
NOTE: The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset).
Therefore, when the Software tries to set both bits in the same write cycle, all counters
are cleared and the bit 4 is not set.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 100h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:9
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346
000000h
RO
0
0
0
0
0
0
0
UCDBC
0
0
0
0
0
0
0
0
0
0
CNTRST
0
4
CNTSTOPRO
0
8
RSTONRD
0
12
CNTPRST
0
16
CNTFREEZ
0
20
CNTPRSTLVL
0
24
RSV1
0
28
RSV0
31
Field Name (ID): Description
Reserved (RSV1): Reserved.
8
0b
RW
Update MMC Counters for Dropped Broadcast Frames (UCDBC): When set, this
bit enables MAC to update all the related MMC Counters for Broadcast frames dropped
due to setting of DBF bit (Disable Broadcast Frames) of MAC Filter Register at offset
0x0004. When reset, MMC Counters are not updated for dropped Broadcast frames.
7:6
00b
RO
Reserved (RSV0): Reserved.
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
15.6.16
Default &
Access
Field Name (ID): Description
5
0b
RW
Full-Half Preset (CNTPRSTLVL): When low and bit 4 is set, all MMC counters get
preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - 16). When this bit is
high and bit 4 is set, all MMC counters get preset to almost-full value. All octet counters
get preset to 0xFFFF_F800 (full - 2KBytes) and all frame-counters gets preset to
0xFFFF_FFF0 (full - 16). For 16-bit counters, the almost-half preset values are 0x7800
and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset
values for the 16-bit counters are 0xF800 and 0xFFF0.
4
0b
RW
Counters Preset (CNTPRST): When this bit is set, all counters are initialized or preset
to almost full or almost half according to bit 5. This bit is cleared automatically after 1
clock cycle. This bit, along with bit 5, is useful for debugging and testing the assertion of
interrupts because of MMC counter becoming half-full or full.
3
0b
RW
MMC Counter Freeze (CNTFREEZ): When this bit is set, it freezes all MMC counters to
their current value. Until this bit is reset to 0, no MMC counter is updated because of any
transmitted or received frame. If any MMC counter is read with the Reset on Read bit
set, then that counter is also cleared in this mode
2
0b
RW
Reset on Read (RSTONRD): When this bit is set, the MMC counters are reset to zero
after Read (self-clearing after reset). The counters are cleared when the least significant
byte lane (bits[7:0]) is read.
1
0b
RW
Counters Stop Rollover (CNTSTOPRO): When this bit is set, after reaching
maximum value, the counter does not roll over to zero.
0
0b
RW
Counters Reset (CNTRST): When this bit is set, all counters are reset. This bit is
cleared automatically after one clock cycle.
MMC Receive Interrupt Register (MMC_INTR_RX)—Offset 104h
The MMC Receive Interrupt Register maintains the interrupt generated from all of the
receive statistic counters. An interrupt bit is cleared when the respective MMC counter
that caused the interrupt is read.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 104h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
31:26
Default &
Access
000000b
RO
November 2014
Document Number: 329676-004US
0
0
0
0
0
0
0
0
0
0
0
0
0
RXOSIZEGFIS
RXUSIZEGFIS
RXJABERFIS
RXRUNTFIS
RXALGNERFIS
RXCRCERFIS
RXMCGFIS
RXBCGFIS
RXGOCTIS
0
0
RXGBOCTIS
0
RXGBFRMIS
0
RX64OCTGBFIS
0
RX65T127OCTGBFIS
0
0
RX128T255OCTGBFIS
0
4
RX256T511OCTGBFIS
0
8
RX512T1023OCTGBFIS
0
RXUCGFIS
0
12
RX1024TMAXOCTGBFIS
0
RXLENERFIS
0
RXORANGEFIS
0
RXFOVFIS
0
16
RXPAUSFIS
0
RXWDOGFIS
0
20
RXVLANGBFIS
0
RXRCVERRFIS
0
24
RSV0
0
28
RXCTRLFIS
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
Intel® Quark™ SoC X1000
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
348
Default &
Access
Field Name (ID): Description
25
0b
RO
MMC Receive Control Frame Counter Interrupt Status (RXCTRLFIS): This bit is
set when the rxctrlframes_g counter reaches half of the maximum value or the
maximum value.
24
0b
RO
MMC Receive Error Frame Counter Interrupt Status (RXRCVERRFIS): This bit is
set when the rxrcverror counter reaches half of the maximum value or the maximum
value.
23
0b
RO
MMC Receive Watchdog Error Frame Counter Interrupt Status (RXWDOGFIS):
This bit is set when the rxwatchdog error counter reaches half of the maximum value or
the maximum value.
22
0b
RO
MMC Receive VLAN Good Bad Frame Counter Interrupt Status (RXVLANGBFIS):
This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or
the maximum value.
21
0b
RO
MMC Receive FIFO Overflow Frame Counter Interrupt Status (RXFOVFIS): This
bit is set when the rxfifooverflow counter reaches half of the maximum value or the
maximum value.
20
0b
RO
MMC Receive Pause Frame Counter Interrupt Status (RXPAUSFIS): This bit is set
when the rxpauseframes counter reaches half of the maximum value or the maximum
value.
19
0b
RO
MMC Receive Out Of Range Error Frame Counter Interrupt Status
(RXORANGEFIS): This bit is set when the rxoutofrangetype counter reaches half of the
maximum value or the maximum value.
18
0b
RO
MMC Receive Length Error Frame Counter Interrupt Status (RXLENERFIS): This
bit is set when the rxlengtherror counter reaches half of the maximum value or the
maximum value.
17
0b
RO
MMC Receive Unicast Good Frame Counter Interrupt Status (RXUCGFIS): This
bit is set when the rxunicastframes_g counter reaches half of the maximum value or the
maximum value.
16
0b
RO
MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt
Status (RX1024TMAXOCTGBFIS): This bit is set when the rx1024tomaxoctets_gb
counter reaches half of the maximum value or the maximum value.
15
0b
RO
MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
(RX512T1023OCTGBFIS): This bit is set when the rx512to1023octets_gb counter
reaches half of the maximum value or the maximum value.
14
0b
RO
MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status
(RX256T511OCTGBFIS): This bit is set when the rx256to511octets_gb counter
reaches half of the maximum value or the maximum value.
13
0b
RO
MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status
(RX128T255OCTGBFIS): This bit is set when the rx128to255octets_gb counter
reaches half of the maximum value or the maximum value.
12
0b
RO
MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status
(RX65T127OCTGBFIS): This bit is set when the rx65to127octets_gb counter reaches
half of the maximum value or the maximum value.
11
0b
RO
MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status
(RX64OCTGBFIS): This bit is set when the rx64octets_gb counter reaches half of the
maximum value or the maximum value.
10
0b
RO
MMC Receive Oversize Good Frame Counter Interrupt Status (RXOSIZEGFIS):
This bit is set when the rxoversize_g counter reaches half of the maximum value or the
maximum value.
9
0b
RO
MMC Receive Undersize Good Frame Counter Interrupt Status (RXUSIZEGFIS):
This bit is set when the rxundersize_g counter reaches half of the maximum value or the
maximum value.
8
0b
RO
MMC Receive Jabber Error Frame Counter Interrupt Status (RXJABERFIS): This
bit is set when the rxjabbererror counter reaches half of the maximum value or the
maximum value.
7
0b
RO
MMC Receive Runt Frame Counter Interrupt Status (RXRUNTFIS): This bit is set
when the rxrunterror counter reaches half of the maximum value or the maximum
value.
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
15.6.17
Default &
Access
Field Name (ID): Description
6
0b
RO
MMC Receive Alignment Error Frame Counter Interrupt Status (RXALGNERFIS):
This bit is set when the rxalignmenterror counter reaches half of the maximum value or
the maximum value.
5
0b
RO
MMC Receive CRC Error Frame Counter Interrupt Status (RXCRCERFIS): This bit
is set when the rxcrcerror counter reaches half of the maximum value or the maximum
value.
4
0b
RO
MMC Receive Multicast Good Frame Counter Interrupt Status (RXMCGFIS): This
bit is set when the rxmulticastframes_g counter reaches half of the maximum value or
the maximum value.
3
0b
RO
MMC Receive Broadcast Good Frame Counter Interrupt Status (RXBCGFIS): This
bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or
the maximum value.
2
0b
RO
MMC Receive Good Octet Counter Interrupt Status (RXGOCTIS): This bit is set
when the rxoctetcount_g counter reaches half of the maximum value or the maximum
value.
1
0b
RO
MMC Receive Good Bad Octet Counter Interrupt Status (RXGBOCTIS): This bit is
set when the rxoctetcount_gb counter reaches half of the maximum value or the
maximum value.
0
0b
RO
MMC Receive Good Bad Frame Counter Interrupt Status (RXGBFRMIS): This bit
is set when the rxframecount_gb counter reaches half of the maximum value or the
maximum value.
MMC Transmit Interrupt Register (MMC_INTR_TX)—Offset 108h
The maintains the interrupt generated from all of the transmit statistic counters. An
interrupt bit is cleared when the respective MMC counter that caused the interrupt is
read.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 108h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
31:26
25
Default &
Access
000000b
RO
0b
RO
November 2014
Document Number: 329676-004US
0
0
0
0
0
0
0
0
0
0
0
TX65T127OCTGBFIS
TX64OCTGBFIS
TXMCGFIS
TXBCGFIS
TXGBFRMIS
TXGBOCTIS
0
TX128T255OCTGBFIS
0
TX256T511OCTGBFIS
0
TX512T1023OCTGBFIS
0
0
TXUCGBFIS
0
4
TX1024TMAXOCTGBFIS
0
TXBCGBFIS
0
TXMCGBFIS
0
TXSCOLGFIS
0
8
TXUFLOWERFIS
0
TXDEFFIS
0
12
TXMCOLGFIS
0
TXEXCOLFIS
0
TXLATCOLFIS
0
TXGOCTIS
0
16
TXCARERFIS
0
TXGFRMIS
0
TXPAUSFIS
0
TXEXDEFFIS
0
20
TXVLANGFIS
0
24
RSV0
0
28
TXOSIZEGFIS
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
MMC Transmit Oversize Good Frame Counter Interrupt Status (TXOSIZEGFIS):
This bit is set when the txoversize_g counter reaches half of the maximum value or the
maximum value.
Intel® Quark™ SoC X1000
Datasheet
349
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
350
Default &
Access
Field Name (ID): Description
24
0b
RO
MMC Transmit VLAN Good Frame Counter Interrupt Status (TXVLANGFIS): This
bit is set when the txvlanframes_g counter reaches half of the maximum value or the
maximum value.
23
0b
RO
MMC Transmit Pause Frame Counter Interrupt Status (TXPAUSFIS): This bit is
set when the txpauseframeserror counter reaches half of the maximum value or the
maximum value.
22
0b
RO
MMC Transmit Excessive Deferral Frame Counter Interrupt Status
(TXEXDEFFIS): This bit is set when the txexcessdef counter reaches half of the
maximum value or the maximum value.
21
0b
RO
MMC Transmit Good Frame Counter Interrupt Status (TXGFRMIS): This bit is set
when the txframecount_g counter reaches half of the maximum value or the maximum
value.
20
0b
RO
MMC Transmit Good Octet Counter Interrupt Status (TXGOCTIS): This bit is set
when the txoctetcount_g counter reaches half of the maximum value or the maximum
value.
19
0b
RO
MMC Transmit Carrier Error Frame Counter Interrupt Status (TXCARERFIS):
This bit is set when the txcarriererror counter reaches half of the maximum value or the
maximum value.
18
0b
RO
MMC Transmit Excessive Collision Frame Counter Interrupt Status
(TXEXCOLFIS): This bit is set when the txexesscol counter reaches half of the
maximum value or the maximum value.
17
0b
RO
MMC Transmit Late Collision Frame Counter Interrupt Status (TXLATCOLFIS):
This bit is set when the txlatecol counter reaches half of the maximum value or the
maximum value.
16
0b
RO
MMC Transmit Deferred Frame Counter Interrupt Status (TXDEFFIS): This bit is
set when the txdeferred counter reaches half of the maximum value or the maximum
value.
15
0b
RO
MMC Transmit Multiple Collision Good Frame Counter Interrupt Status
(TXMCOLGFIS): This bit is set when the txmulticol_g counter reaches half of the
maximum value or the maximum value.
14
0b
RO
MMC Transmit Single Collision Good Frame Counter Interrupt Status
(TXSCOLGFIS): This bit is set when the txsinglecol_g counter reaches half of the
maximum value or the maximum value.
13
0b
RO
MMC Transmit Underflow Error Frame Counter Interrupt Status
(TXUFLOWERFIS): This bit is set when the txunderflowerror counter reaches half of
the maximum value or the maximum value.
12
0b
RO
MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status
(TXBCGBFIS): This bit is set when the txbroadcastframes_gb counter reaches half of
the maximum value or the maximum value.
11
0b
RO
MMC Transmit Multicast Good Bad Frame Counter Interrupt Status
(TXMCGBFIS): The bit is set when the txmulticastframes_gb counter reaches half of
the maximum value or the maximum value.
10
0b
RO
MMC Transmit Unicast Good Bad Frame Counter Interrupt Status (TXUCGBFIS):
This bit is set when the txunicastframes_gb counter reaches half of the maximum value
or the maximum value.
9
0b
RO
MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt
Status (TX1024TMAXOCTGBFIS): This bit is set when the tx1024tomaxoctets_gb
counter reaches half of the maximum value or the maximum value.
8
0b
RO
MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
(TX512T1023OCTGBFIS): This bit is set when the tx512to1023octets_gb counter
reaches half of the maximum value or the maximum value.
7
0b
RO
MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status
(TX256T511OCTGBFIS): This bit is set when the tx256to511octets_gb counter
reaches half of the maximum value or the maximum value.
6
0b
RO
MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status
(TX128T255OCTGBFIS): This bit is set when the tx128to255octets_gb counter
reaches half of the maximum value or the maximum value.
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
15.6.18
Default &
Access
Field Name (ID): Description
5
0b
RO
MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status
(TX65T127OCTGBFIS): This bit is set when the tx65to127octets_gb counter reaches
half the maximum value, and also when it reaches the maximum value.
4
0b
RO
MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status
(TX64OCTGBFIS): This bit is set when the tx64octets_gb counter reaches half of the
maximum value or the maximum value.
3
0b
RO
MMC Transmit Multicast Good Frame Counter Interrupt Status (TXMCGFIS):
This bit is set when the txmulticastframes_g counter reaches half of the maximum value
or the maximum value.
2
0b
RO
MMC Transmit Broadcast Good Frame Counter Interrupt Status (TXBCGFIS):
This bit is set when the txbroadcastframes_g counter reaches half of the maximum
value or the maximum value.
1
0b
RO
MMC Transmit Good Bad Frame Counter Interrupt Status (TXGBFRMIS): This bit
is set when the txframecount_gb counter reaches half of the maximum value or the
maximum value.
0
0b
RO
MMC Transmit Good Bad Octet Counter Interrupt Status (TXGBOCTIS): This bit
is set when the txoctetcount_gb counter reaches half of the maximum value or the
maximum value.
MMC Receive Interrupt Mask Register (MMC_INTR_MASK_RX)—
Offset 10Ch
The MMC Receive Interrupt Mask Register maintains the mask for the interrupt
generated from all of the receive statistic counters.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 10Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
31:26
Default &
Access
000000b
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
RXOSIZEGFIM
RXUSIZEGFIM
RXJABERFIM
RXRUNTFIM
RXALGNERFIM
RXCRCERFIM
RXMCGFIM
RXBCGFIM
RXGOCTIM
0
0
RXGBOCTIM
0
RXGBFRMIM
0
RX64OCTGBFIM
0
RX65T127OCTGBFIM
0
0
RX128T255OCTGBFIM
0
4
RX256T511OCTGBFIM
0
8
RX512T1023OCTGBFIM
0
RXUCGFIM
0
12
RX1024TMAXOCTGBFIM
0
RXLENERFIM
0
RXORANGEFIM
0
RXFOVFIM
0
16
RXPAUSFIM
0
RXWDOGFIM
0
RXVLANGBFIM
0
20
RXRCVERRFIM
0
24
RSV0
0
28
RXCTRLFIM
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
25
0b
RW
MMC Receive Control Frame Counter Interrupt Mask (RXCTRLFIM): Setting this
bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum
value or the maximum value.
24
0b
RW
MMC Receive Error Frame Counter Interrupt Mask (RXRCVERRFIM): Setting this
bit masks the interrupt when the rxrcverror counter reaches half of the maximum value
or the maximum value.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
351
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
352
Default &
Access
Field Name (ID): Description
23
0b
RW
MMC Receive Watchdog Error Frame Counter Interrupt Mask (RXWDOGFIM):
Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the
maximum value or the maximum value.
22
0b
RW
MMC Receive VLAN Good Bad Frame Counter Interrupt Mask (RXVLANGBFIM):
Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of
the maximum value or the maximum value.
21
0b
RW
MMC Receive FIFO Overflow Frame Counter Interrupt Mask (RXFOVFIM):
Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the
maximum value or the maximum value.
20
0b
RW
MMC Receive Pause Frame Counter Interrupt Mask (RXPAUSFIM): Setting this
bit masks the interrupt when the rxpauseframes counter reaches half of the maximum
value or the maximum value.
19
0b
RW
MMC Receive Out Of Range Error Frame Counter Interrupt Mask
(RXORANGEFIM): Setting this bit masks the interrupt when the rxoutofrangetype
counter reaches half of the maximum value or the maximum value.
18
0b
RW
MMC Receive Length Error Frame Counter Interrupt Mask (RXLENERFIM):
Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the
maximum value or the maximum value.
17
0b
RW
MMC Receive Unicast Good Frame Counter Interrupt Mask (RXUCGFIM): Setting
this bit masks the interrupt when the rxunicastframes_g counter reaches half of the
maximum value or the maximum value.
16
0b
RW
MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
(RX1024TMAXOCTGBFIM): Setting this bit masks the interrupt when the
rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum
value.
15
0b
RW
MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
(RX512T1023OCTGBFIM): Setting this bit masks the interrupt when the
rx512to1023octets_gb counter reaches half of the maximum value or the maximum
value.
14
0b
RW
MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
(RX256T511OCTGBFIM): Setting this bit masks the interrupt when the
rx256to511octets_gb counter reaches half of the maximum value or the maximum
value.
13
0b
RW
MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
(RX128T255OCTGBFIM): Setting this bit masks the interrupt when the
rx128to255octets_gb counter reaches half of the maximum value or the maximum
value.
12
0b
RW
MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
(RX65T127OCTGBFIM): Setting this bit masks the interrupt when the
rx65to127octets_gb counter reaches half of the maximum value or the maximum value.
11
0b
RW
MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask
(RX64OCTGBFIM): Setting this bit masks the interrupt when the rx64octets_gb
counter reaches half of the maximum value or the maximum value.
10
0b
RW
MMC Receive Oversize Good Frame Counter Interrupt Mask (RXOSIZEGFIM):
Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the
maximum value or the maximum value.
9
0b
RW
MMC Receive Undersize Good Frame Counter Interrupt Mask (RXUSIZEGFIM):
Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the
maximum value or the maximum value.
8
0b
RW
MMC Receive Jabber Error Frame Counter Interrupt Mask (RXJABERFIM):
Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the
maximum value or the maximum value.
7
0b
RW
MMC Receive Runt Frame Counter Interrupt Mask (RXRUNTFIM): Setting this bit
masks the interrupt when the rxrunterror counter reaches half of the maximum value or
the maximum value.
6
0b
RW
MMC Receive Alignment Error Frame Counter Interrupt Mask (RXALGNERFIM):
Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of
the maximum value or the maximum value.
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
15.6.19
Default &
Access
Field Name (ID): Description
5
0b
RW
MMC Receive CRC Error Frame Counter Interrupt Mask (RXCRCERFIM): Setting
this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum
value or the maximum value.
4
0b
RW
MMC Receive Multicast Good Frame Counter Interrupt Mask (RXMCGFIM):
Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half
of the maximum value or the maximum value.
3
0b
RW
MMC Receive Broadcast Good Frame Counter Interrupt Mask (RXBCGFIM):
Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half
of the maximum value or the maximum value.
2
0b
RW
MMC Receive Good Octet Counter Interrupt Mask (RXGOCTIM): Setting this bit
masks the interrupt when the rxoctetcount_g counter reaches half of the maximum
value or the maximum value.
1
0b
RW
MMC Receive Good Bad Octet Counter Interrupt Mask (RXGBOCTIM): Setting
this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the
maximum value or the maximum value.
0
0b
RW
MMC Receive Good Bad Frame Counter Interrupt Mask (RXGBFRMIM): Setting
this bit masks the interrupt when the rxframecount_gb counter reaches half of the
maximum value or the maximum value.
MMC Transmit Interrupt Mask Register
(MMC_INTR_MASK_TX)—Offset 110h
The MMC Transmit Interrupt Mask Register maintains the mask for the interrupt
generated from all of the transmit statistic counters.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 110h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
31:26
Default &
Access
000000b
RO
0
0
0
0
0
0
0
0
0
0
0
TX65T127OCTGBFIM
TX64OCTGBFIM
TXMCGFIM
TXBCGFIM
TXGBFRMIM
TXGBOCTIM
0
TX128T255OCTGBFIM
0
TX256T511OCTGBFIM
0
TX512T1023OCTGBFIM
0
0
TXUCGBFIM
0
4
TX1024TMAXOCTGBFIM
0
TXBCGBFIM
0
TXMCGBFIM
0
TXSCOLGFIM
0
8
TXUFLOWERFIM
0
TXDEFFIM
0
12
TXMCOLGFIM
0
TXEXCOLFIM
0
TXLATCOLFIM
0
TXGOCTIM
0
16
TXCARERFIM
0
TXGFRMIM
0
TXPAUSFIM
0
TXEXDEFFIM
0
20
TXVLANGFIM
0
24
RSV0
0
28
TXOSIZEGFIM
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
25
0b
RW
MMC Transmit Oversize Good Frame Counter Interrupt Mask (TXOSIZEGFIM):
Setting this bit masks the interrupt when the txoversize_g counter reaches half of the
maximum value or the maximum value.
24
0b
RW
MMC Transmit VLAN Good Frame Counter Interrupt Mask (TXVLANGFIM):
Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the
maximum value or the maximum value.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
353
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Intel® Quark™ SoC X1000
Datasheet
354
Default &
Access
Field Name (ID): Description
23
0b
RW
MMC Transmit Pause Frame Counter Interrupt Mask (TXPAUSFIM): Setting this
bit masks the interrupt when the txpauseframes counter reaches half of the maximum
value or the maximum value.
22
0b
RW
MMC Transmit Excessive Deferral Frame Counter Interrupt Mask
(TXEXDEFFIM): Setting this bit masks the interrupt when the txexcessdef counter
reaches half of the maximum value or the maximum value.
21
0b
RW
MMC Transmit Good Frame Counter Interrupt Mask (TXGFRMIM): Setting this bit
masks the interrupt when the txframecount_g counter reaches half of the maximum
value or the maximum value.
20
0b
RW
MMC Transmit Good Octet Counter Interrupt Mask (TXGOCTIM): Setting this bit
masks the interrupt when the txoctetcount_g counter reaches half of the maximum
value or the maximum value.
19
0b
RW
MMC Transmit Carrier Error Frame Counter Interrupt Mask (TXCARERFIM):
Setting this bit masks the interrupt when the txcarriererror counter reaches half of the
maximum value or the maximum value.
18
0b
RW
MMC Transmit Excessive Collision Frame Counter Interrupt Mask
(TXEXCOLFIM): Setting this bit masks the interrupt when the txexcesscol counter
reaches half of the maximum value or the maximum value.
17
0b
RW
MMC Transmit Late Collision Frame Counter Interrupt Mask (TXLATCOLFIM):
Setting this bit masks the interrupt when the txlatecol counter reaches half of the
maximum value or the maximum value.
16
0b
RW
MMC Transmit Deferred Frame Counter Interrupt Mask (TXDEFFIM): Setting this
bit masks the interrupt when the txdeferred counter reaches half of the maximum value
or the maximum value.
15
0b
RW
MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
(TXMCOLGFIM): Setting this bit masks the interrupt when the txmulticol_g counter
reaches half of the maximum value or the maximum value.
14
0b
RW
MMC Transmit Single Collision Good Frame Counter Interrupt Mask
(TXSCOLGFIM): Setting this bit masks the interrupt when the txsinglecol_g counter
reaches half of the maximum value or the maximum value.
13
0b
RW
MMC Transmit Underflow Error Frame Counter Interrupt Mask
(TXUFLOWERFIM): Setting this bit masks the interrupt when the txunderflowerror
counter reaches half of the maximum value or the maximum value.
12
0b
RW
MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask
(TXBCGBFIM): Setting this bit masks the interrupt when the txbroadcastframes_gb
counter reaches half of the maximum value or the maximum value.
11
0b
RW
MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask
(TXMCGBFIM): Setting this bit masks the interrupt when the txmulticastframes_gb
counter reaches half of the maximum value or the maximum value.
10
0b
RW
MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask (TXUCGBFIM):
Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half
of the maximum value or the maximum value.
9
0b
RW
MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt
Mask (TX1024TMAXOCTGBFIM): Setting this bit masks the interrupt when the
tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum
value.
8
0b
RW
MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
(TX512T1023OCTGBFIM): Setting this bit masks the interrupt when the
tx512to1023octets_gb counter reaches half of the maximum value or the maximum
value.
7
0b
RW
MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
(TX256T511OCTGBFIM): Setting this bit masks the interrupt when the
tx256to511octets_gb counter reaches half of the maximum value or the maximum
value.
6
0b
RW
MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
(TX128T255OCTGBFIM): Setting this bit masks the interrupt when the
tx128to255octets_gb counter reaches half of the maximum value or the maximum
value.
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
15.6.20
Default &
Access
Field Name (ID): Description
5
0b
RW
MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
(TX65T127OCTGBFIM): Setting this bit masks the interrupt when the
tx65to127octets_gb counter reaches half of the maximum value or the maximum value.
4
0b
RW
MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask
(TX64OCTGBFIM): Setting this bit masks the interrupt when the tx64octets_gb
counter reaches half of the maximum value or the maximum value.
3
0b
RW
MMC Transmit Multicast Good Frame Counter Interrupt Mask (TXMCGFIM):
Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half
of the maximum value or the maximum value.
2
0b
RW
MMC Transmit Broadcast Good Frame Counter Interrupt Mask (TXBCGFIM):
Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half
of the maximum value or the maximum value.
1
0b
RW
MMC Transmit Good Bad Frame Counter Interrupt Mask (TXGBFRMIM): Setting
this bit masks the interrupt when the txframecount_gb counter reaches half of the
maximum value or the maximum value.
0
0b
RW
MMC Transmit Good Bad Octet Counter Interrupt Mask (TXGBOCTIM): Setting
this bit masks the interrupt when the txoctetcount_gb counter reaches half of the
maximum value or the maximum value.
MMC Transmit Good Bad Octet Counter Register
(TXOCTETCOUNT_GB)—Offset 114h
Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad
frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 114h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.21
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Good Bad Frame Counter Register
(TXFRAMECOUNT_GB)—Offset 118h
Number of good and bad frames transmitted, exclusive of retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 118h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
355
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.22
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Broadcast Good Frame Counter Register
(TXBROADCASTFRAMES_G)—Offset 11Ch
Number of good broadcast frames transmitted.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 11Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.23
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Multicast Good Frame Counter Register
(TXMULTICASTFRAMES_G)—Offset 120h
Number of good multicast frames transmitted.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 120h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Intel® Quark™ SoC X1000
Datasheet
356
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.24
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit 64 Octet Good Bad Frame Counter Register
(TX64OCTETS_GB)—Offset 124h
Number of good and bad frames transmitted with length 64 bytes, exclusive of
preamble and retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 124h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.25
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit 65 to 127 Octet Good Bad Frame Counter
Register (TX65TO127OCTETS_GB)—Offset 128h
Number of good and bad frames transmitted with length between 65 and 127
(inclusive) bytes, exclusive of preamble and retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 128h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
357
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.26
MMC Transmit 128 to 255 Octet Good Bad Frame Counter
Register (TX128TO255OCTETS_GB)—Offset 12Ch
Number of good and bad frames transmitted with length between 128 and 255
(inclusive) bytes, exclusive of preamble and retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 12Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.27
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit 256 to 511 Octet Good Bad Frame Counter
Register (TX256TO511OCTETS_GB)—Offset 130h
Number of good and bad frames transmitted with length between 256 and 511
(inclusive) bytes, exclusive of preamble and retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 130h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.28
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit 512 to 1023 Octet Good Bad Frame Counter
Register (TX512TO1023OCTETS_GB)—Offset 134h
Number of good and bad frames transmitted with length between 512 and 1,023
(inclusive) bytes, exclusive of preamble and retried frames.
Access Method
Intel® Quark™ SoC X1000
Datasheet
358
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 134h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.29
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter
Register (TX1024TOMAXOCTETS_GB)—Offset 138h
Number of good and bad frames transmitted with length between 1,024 and maxsize
(inclusive) bytes, exclusive of preamble and retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 138h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.30
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Unicast Good Bad Frame Counter Register
(TXUNICASTFRAMES_GB)—Offset 13Ch
Number of good and bad unicast frames transmitted.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 13Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
359
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.31
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Multicast Good Bad Frame Counter Register
(TXMULTICASTFRAMES_GB)—Offset 140h
Number of good and bad multicast frames transmitted.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 140h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.32
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Broadcast Good Bad Frame Counter Register
(TXBROADCASTFRAMES_GB)—Offset 144h
Number of good and bad broadcast frames transmitted.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 144h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Intel® Quark™ SoC X1000
Datasheet
360
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.33
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Underflow Error Frame Counter Register
(TXUNDERFLOWERROR)—Offset 148h
Number of frames aborted because of frame underflow error.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 148h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.34
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Single Collision Good Frame Counter Register
(TXSINGLECOL_G)—Offset 14Ch
Number of successfully transmitted frames after a single collision in the half-duplex
mode.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 14Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
361
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.35
MMC Transmit Multiple Collision Good Frame Counter Register
(TXMULTICOL_G)—Offset 150h
Number of successfully transmitted frames after multiple collisions in the half-duplex
mode.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 150h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.36
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Deferred Frame Counter Register
(TXDEFERRED)—Offset 154h
Number of successfully transmitted frames after a deferral in the half-duplex mode.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 154h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.37
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Late Collision Frame Counter Register
(TXLATECOL)—Offset 158h
Number of frames aborted because of late collision error.
Access Method
Intel® Quark™ SoC X1000
Datasheet
362
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 158h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.38
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Excessive Collision Frame Counter Register
(TXEXESSCOL)—Offset 15Ch
Number of frames aborted because of excessive (16) collision errors.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 15Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.39
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Carrier Error Frame Counter Register
(TXCARRIERERROR)—Offset 160h
Number of frames aborted because of carrier sense error (no carrier or loss of carrier).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 160h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
363
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.40
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Good Octet Counter Register
(TXOCTETCOUNT_G)—Offset 164h
Number of bytes transmitted, exclusive of preamble, in good frames only.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 164h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.41
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Good Frame Counter Register
(TXFRAMECOUNT_G)—Offset 168h
Number of good frames transmitted.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 168h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Intel® Quark™ SoC X1000
Datasheet
364
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.42
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Excessive Deferral Frame Counter Register
(TXEXCESSDEF)—Offset 16Ch
Number of frames aborted because of excessive deferral error (deferred for more than
two max-sized frame times).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 16Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.43
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Pause Frame Counter Register
(TXPAUSEFRAMES)—Offset 170h
Number of good PAUSE frames transmitted.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 170h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
365
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.44
MMC Transmit VLAN Good Frame Counter Register
(TXVLANFRAMES_G)—Offset 174h
Number of good VLAN frames transmitted, exclusive of retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 174h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.45
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Transmit Oversize Good Frame Counter Register
(TXOVERSIZE_G)—Offset 178h
Number of frames transmitted without errors and with length greater than the maxsize
(1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of
Register 0 (MAC Configuration Register)).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 178h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.46
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Good Bad Frame Counter Register
(RXFRAMECOUNT_GB)—Offset 180h
Number of good and bad frames received.
Access Method
Intel® Quark™ SoC X1000
Datasheet
366
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 180h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.47
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Good Bad Octet Counter Register
(RXOCTETCOUNT_GB)—Offset 184h
Number of bytes received, exclusive of preamble, in good and bad frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 184h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.48
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Good Octet Counter Register
(RXOCTETCOUNT_G)—Offset 188h
Number of bytes received, exclusive of preamble, only in good frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 188h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
367
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.49
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Broadcast Good Frame Counter Register
(RXBROADCASTFRAMES_G)—Offset 18Ch
Number of good broadcast frames received.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 18Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.50
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Multicast Good Frame Counter Register
(RXMULTICASTFRAMES_G)—Offset 190h
Number of good multicast frames received.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 190h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
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Datasheet
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November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.51
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive CRC Error Frame Counter Register
(RXCRCERROR)—Offset 194h
Number of frames received with CRC error.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 194h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.52
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Alignment Error Frame Counter Register
(RXALIGNMENTERROR)—Offset 198h
Number of frames received with alignment (dribble) error.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 198h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
369
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.53
MMC Receive Runt Frame Counter Register (RXRUNTERROR)—
Offset 19Ch
Number of frames received with runt ((64 bytes and CRC error) error.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 19Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.54
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Jabber Error Frame Counter Register
(RXJABBERERROR)—Offset 1A0h
Number of giant frames received with length (including CRC) greater than 1,518 bytes
(1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled,
then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered
as giant frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1A0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.55
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Undersize Good Frame Counter Register
(RXUNDERSIZE_G)—Offset 1A4h
Number of frames received with length less than 64 bytes, without any errors.
Access Method
Intel® Quark™ SoC X1000
Datasheet
370
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1A4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.56
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Oversize Good Frame Counter Register
(RXOVERSIZE_G)—Offset 1A8h
Number of frames received without errors, with length greater than the maxsize (1,518
or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC
Configuration Register)).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1A8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.57
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive 64 Octet Good Bad Frame Counter Register
(RX64OCTETS_GB)—Offset 1ACh
Number of good and bad frames received with length 64 bytes, exclusive of preamble.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1ACh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
371
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.58
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive 65 to 127 Octet Good Bad Frame Counter Register
(RX65TO127OCTETS_GB)—Offset 1B0h
Number of good and bad frames received with length between 65 and 127 (inclusive)
bytes, exclusive of preamble.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1B0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.59
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive 128 to 255 Octet Good Bad Frame Counter
Register (RX128TO255OCTETS_GB)—Offset 1B4h
Number of good and bad frames received with length between 128 and 255 (inclusive)
bytes, exclusive of preamble.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1B4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Intel® Quark™ SoC X1000
Datasheet
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November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.60
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive 256 to 511 Octet Good Bad Frame Counter
Register (RX256TO511OCTETS_GB)—Offset 1B8h
Number of good and bad frames received with length between 256 and 511 (inclusive)
bytes, exclusive of preamble.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1B8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.61
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive 512 to 1023 Octet Good Bad Frame Counter
Register (RX512TO1023OCTETS_GB)—Offset 1BCh
Number of good and bad frames received with length between 512 and 1,023
(inclusive) bytes, exclusive of preamble.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1BCh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
373
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.62
MMC Receive 1024 to Maximum Octet Good Bad Frame Counter
Register (RX1024TOMAXOCTETS_GB)—Offset 1C0h
Number of good and bad frames received with length between 1,024 and maxsize
(inclusive) bytes, exclusive of preamble and retried frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1C0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.63
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Unicast Good Frame Counter Register
(RXUNICASTFRAMES_G)—Offset 1C4h
Number of received good unicast frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1C4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.64
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Length Error Frame Counter Register
(RXLENGTHERROR)—Offset 1C8h
Number of frames received with length error (Length type field doesn't match frame
size), for all frames with valid length field.
Access Method
Intel® Quark™ SoC X1000
Datasheet
374
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1C8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.65
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Out Of Range Error Frame Counter Register
(RXOUTOFRANGETYPE)—Offset 1CCh
Number of frames received with length field not equal to the valid frame size (greater
than 1,500 but less than 1,536).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1CCh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.66
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Pause Frame Counter Register
(RXPAUSEFRAMES)—Offset 1D0h
Number of good and valid PAUSE frames received.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1D0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
375
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.67
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive FIFO Overflow Frame Counter Register
(RXFIFOOVERFLOW)—Offset 1D4h
Number of missed received frames because of FIFO overflow.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1D4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.68
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive VLAN Good Bad Frame Counter Register
(RXVLANFRAMES_GB)—Offset 1D8h
Number of good and bad VLAN frames received.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1D8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Intel® Quark™ SoC X1000
Datasheet
376
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.69
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Watchdog Error Frame Counter Register
(RXWATCHDOGERROR)—Offset 1DCh
Number of frames received with error because of watchdog timeout error (frames with
a data load larger than 2,048 bytes).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1DCh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.70
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive Error Frame Counter Register (RXRCVERROR)—
Offset 1E0h
Number of frames received with Receive error or Frame Extension error on the MII
interface.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1E0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
377
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.71
MMC Receive Control Frame Counter Register
(RXCTRLFRAMES_G)—Offset 1E4h
Number of received good control frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1E4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
Default &
Access
31:0
15.6.72
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC IPC Receive Checksum Offload Interrupt Mask Register
(MMC_IPC_INTR_MASK_RX)—Offset 200h
The MMC IPC Receive Checksum Offload Interrupt Mask maintains the mask for the
interrupt generated from the receive IPC statistic counters.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 200h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
RXIPV4GFIM
0
RXIPV4HERFIM
0
RXIPV4FRAGFIM
0
RXIPV4NOPAYFIM
0
RXIPV6GFIM
0
0
RXIPV4UDSBLFIM
0
RXIPV6HERFIM
0
RXUDPGFIM
0
4
RXIPV6NOPAYFIM
0
RXTCPGFIM
RXIPV4HEROIM
0
RXUDPERFIM
RXIPV4FRAGOIM
0
RXTCPERFIM
0
RXICMPGFIM
0
8
RXICMPERFIM
0
12
RSV0
0
RXIPV4GOIM
0
RXIPV4NOPAYOIM
0
RXIPV6GOIM
0
16
RXIPV4UDSBLOIM
0
RXIPV6HEROIM
0
RXUDPGOIM
0
20
RXIPV6NOPAYOIM
0
RXTCPGOIM
0
RXUDPEROIM
0
RXTCPEROIM
24
RXICMPGOIM
0
RSV1
0
28
RXICMPEROIM
31
Field Name (ID): Description
31:30
0b
RO
Reserved (RSV1): Reserved.
29
0b
RW
MMC Receive ICMP Error Octet Counter Interrupt Mask (RXICMPEROIM):
Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of
the maximum value or the maximum value.
28
0b
RW
MMC Receive ICMP Good Octet Counter Interrupt Mask (RXICMPGOIM): Setting
this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the
maximum value or the maximum value.
Intel® Quark™ SoC X1000
Datasheet
378
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
27
0b
RW
MMC Receive TCP Error Octet Counter Interrupt Mask (RXTCPEROIM): Setting
this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the
maximum value or the maximum value.
26
0b
RW
MMC Receive TCP Good Octet Counter Interrupt Mask (RXTCPGOIM): Setting
this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the
maximum value or the maximum value.
25
0b
RW
MMC Receive UDP Good Octet Counter Interrupt Mask (RXUDPEROIM): Setting
this bit masks the interrupt when the rxudp_err_octets counter reaches half of the
maximum value or the maximum value.
24
0b
RW
MMC Receive IPV6 No Payload Octet Counter Interrupt Mask (RXUDPGOIM):
Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of
the maximum value or the maximum value.
23
0b
RW
MMC Receive IPV6 Header Error Octet Counter Interrupt Mask
(RXIPV6NOPAYOIM): Setting this bit masks the interrupt when the
rxipv6_nopay_octets counter reaches half of the maximum value or the maximum
value.
22
0b
RW
MMC Receive IPV6 Good Octet Counter Interrupt Mask (RXIPV6HEROIM):
Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half
of the maximum value or the maximum value.
21
0b
RW
MMC Receive IPV6 Good Octet Counter Interrupt Mask (RXIPV6GOIM): Setting
this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the
maximum value or the maximum value.
20
0b
RW
MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
(RXIPV4UDSBLOIM): Setting this bit masks the interrupt when the
rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value.
19
0b
RW
MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
(RXIPV4FRAGOIM): Setting this bit masks the interrupt when the rxipv4_frag_octets
counter reaches half of the maximum value or the maximum value.
18
0b
RW
MMC Receive IPV4 No Payload Octet Counter Interrupt Mask
(RXIPV4NOPAYOIM): Setting this bit masks the interrupt when the
rxipv4_nopay_octets counter reaches half of the maximum value or the maximum
value.
17
0b
RW
MMC Receive IPV4 Header Error Octet Counter Interrupt Mask
(RXIPV4HEROIM): Setting this bit masks the interrupt when the rxipv4_hdrerr_octets
counter reaches half of the maximum value or the maximum value.
16
0b
RW
MMC Receive IPV4 Good Octet Counter Interrupt Mask (RXIPV4GOIM): Setting
this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the
maximum value or the maximum value.
15:14
00b
RO
Reserved (RSV0): Reserved.
13
0b
RW
MMC Receive ICMP Error Frame Counter Interrupt Mask (RXICMPERFIM):
Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of
the maximum value or the maximum value.
12
0b
RW
MMC Receive ICMP Good Frame Counter Interrupt Mask (RXICMPGFIM): Setting
this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the
maximum value or the maximum value.
11
0b
RW
MMC Receive TCP Error Frame Counter Interrupt Mask (RXTCPERFIM): Setting
this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the
maximum value or the maximum value.
10
0b
RW
MMC Receive TCP Good Frame Counter Interrupt Mask (RXTCPGFIM): Setting
this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the
maximum value or the maximum value.
9
0b
RW
MMC Receive UDP Error Frame Counter Interrupt Mask (RXUDPERFIM): Setting
this bit masks the interrupt when the rxudp_err_frms counter reaches half of the
maximum value or the maximum value.
November 2014
Document Number: 329676-004US
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
15.6.73
Default &
Access
Field Name (ID): Description
8
0b
RW
MMC Receive UDP Good Frame Counter Interrupt Mask (RXUDPGFIM): Setting
this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the
maximum value or the maximum value.
7
0b
RW
MMC Receive IPV6 No Payload Frame Counter Interrupt Mask
(RXIPV6NOPAYFIM): Setting this bit masks the interrupt when the
rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value.
6
0b
RW
MMC Receive IPV6 Header Error Frame Counter Interrupt Mask
(RXIPV6HERFIM): Setting this bit masks the interrupt when the rxipv6_hdrerr_frms
counter reaches half of the maximum value or the maximum value.
5
0b
RW
MMC Receive IPV6 Good Frame Counter Interrupt Mask (RXIPV6GFIM): Setting
this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the
maximum value or the maximum value.
4
0b
RW
MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
(RXIPV4UDSBLFIM): Setting this bit masks the interrupt when the rxipv4_udsbl_frms
counter reaches half of the maximum value or the maximum value.
3
0b
RW
MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask
(RXIPV4FRAGFIM): Setting this bit masks the interrupt when the rxipv4_frag_frms
counter reaches half of the maximum value or the maximum value.
2
0b
RW
MMC Receive IPV4 No Payload Frame Counter Interrupt Mask
(RXIPV4NOPAYFIM): Setting this bit masks the interrupt when the
rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value.
1
0b
RW
MMC Receive IPV4 Header Error Frame Counter Interrupt Mask
(RXIPV4HERFIM): Setting this bit masks the interrupt when the rxipv4_hdrerr_frms
counter reaches half of the maximum value or the maximum value.
0
0b
RW
MMC Receive IPV4 Good Frame Counter Interrupt Mask (RXIPV4GFIM): Setting
this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the
maximum value or the maximum value.
MMC Receive Checksum Offload Interrupt Register
(MMC_IPC_INTR_RX)—Offset 208h
The MMC Receive Checksum Offload Interrupt register maintains the interrupts
generated when receive IPC statistic counters reach half their maximum values, and
when they cross their maximum values. When Counter Stop Rollover is set, then
interrupts are set but the counter remains at all-ones. When the MMC IPC counter that
caused the interrupt is read, its corresponding interrupt bit is cleared.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 208h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
380
0
0
0
0
0
0
0
RXIPV4GFIS
0
RXIPV4HERFIS
0
RXIPV4FRAGFIS
0
RXIPV4NOPAYFIS
0
RXIPV6GFIS
0
0
RXIPV4UDSBLFIS
0
RXIPV6HERFIS
RXIPV4GOIS
0
RXUDPGFIS
RXIPV4HEROIS
0
4
RXIPV6NOPAYFIS
RXIPV4FRAGOIS
0
RXTCPGFIS
0
RXUDPERFIS
0
RXTCPERFIS
0
RXICMPGFIS
0
8
RXICMPERFIS
0
12
RSV0
0
RXIPV4NOPAYOIS
0
RXIPV6GOIS
0
16
RXIPV4UDSBLOIS
0
RXIPV6HEROIS
0
RXUDPGOIS
0
20
RXIPV6NOPAYOIS
0
RXTCPGOIS
0
RXUDPEROIS
0
RXTCPEROIS
0
24
RXICMPGOIS
RSV1
0
28
RXICMPEROIS
31
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Document Number: 329676-004US
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Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0b
RO
Reserved (RSV1): Reserved.
29
0b
RO
MMC Receive ICMP Error Octet Counter Interrupt Status (RXICMPEROIS): This
bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the
maximum value.
28
0b
RO
MMC Receive ICMP Good Octet Counter Interrupt Status (RXICMPGOIS): This
bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the
maximum value.
27
0b
RO
MMC Receive TCP Error Octet Counter Interrupt Status (RXTCPEROIS): This bit
is set when the rxtcp_err_octets counter reaches half of the maximum value or the
maximum value.
26
0b
RO
MMC Receive TCP Good Octet Counter Interrupt Status (RXTCPGOIS): This bit is
set when the rxtcp_gd_octets counter reaches half of the maximum value or the
maximum value.
25
0b
RO
MMC Receive UDP Error Octet Counter Interrupt Status (RXUDPEROIS): This bit
is set when the rxudp_err_octets counter reaches half of the maximum value or the
maximum value.
24
0b
RO
MMC Receive UDP Good Octet Counter Interrupt Status (RXUDPGOIS): This bit
is set when the rxudp_gd_octets counter reaches half of the maximum value or the
maximum value.
23
0b
RO
MMC Receive IPV6 No Payload Octet Counter Interrupt Status
(RXIPV6NOPAYOIS): This bit is set when the rxipv6_nopay_octets counter reaches
half of the maximum value or the maximum value.
22
0b
RO
MMC Receive IPV6 Header Error Octet Counter Interrupt Status
(RXIPV6HEROIS): This bit is set when the rxipv6_hdrerr_octets counter reaches half
of the maximum value or the maximum value.
21
0b
RO
MMC Receive IPV6 Good Octet Counter Interrupt Status (RXIPV6GOIS): This bit
is set when the rxipv6_gd_octets counter reaches half of the maximum value or the
maximum value.
20
0b
RO
MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status
(RXIPV4UDSBLOIS): This bit is set when the rxipv4_udsbl_octets counter reaches
half of the maximum value or the maximum value.
19
0b
RO
MMC Receive IPV4 Fragmented Octet Counter Interrupt Status
(RXIPV4FRAGOIS): This bit is set when the rxipv4_frag_octets counter reaches half of
the maximum value or the maximum value.
18
0b
RO
MMC Receive IPV4 No Payload Octet Counter Interrupt Status
(RXIPV4NOPAYOIS): This bit is set when the rxipv4_nopay_octets counter reaches
half of the maximum value or the maximum value.
17
0b
RO
MMC Receive IPV4 Header Error Octet Counter Interrupt Status
(RXIPV4HEROIS): This bit is set when the rxipv4_hdrerr_octets counter reaches half
of the maximum value or the maximum value.
16
0b
RO
MMC Receive IPV4 Good Octet Counter Interrupt Status (RXIPV4GOIS): This bit
is set when the rxipv4_gd_octets counter reaches half of the maximum value or the
maximum value.
15:14
00b
RO
Reserved (RSV0): Reserved.
13
0b
RO
MMC Receive ICMP Error Frame Counter Interrupt Status (RXICMPERFIS): This
bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the
maximum value.
12
0b
RO
MMC Receive ICMP Good Frame Counter Interrupt Status (RXICMPGFIS): This
bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the
maximum value.
11
0b
RO
MMC Receive TCP Error Frame Counter Interrupt Status (RXTCPERFIS): This bit
is set when the rxtcp_err_frms counter reaches half of the maximum value or the
maximum value.
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
381
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
15.6.74
Default &
Access
Field Name (ID): Description
10
0b
RO
MMC Receive TCP Good Frame Counter Interrupt Status (RXTCPGFIS): This bit is
set when the rxtcp_gd_frms counter reaches half of the maximum value or the
maximum value.
9
0b
RO
MMC Receive UDP Error Frame Counter Interrupt Status (RXUDPERFIS): This bit
is set when the rxudp_err_frms counter reaches half of the maximum value or the
maximum value.
8
0b
RO
MMC Receive UDP Good Frame Counter Interrupt Status (RXUDPGFIS): This bit
is set when the rxudp_gd_frms counter reaches half of the maximum value or the
maximum value.
7
0b
RO
MMC Receive IPV6 No Payload Frame Counter Interrupt Status
(RXIPV6NOPAYFIS): This bit is set when the rxipv6_nopay_frms counter reaches half
of the maximum value or the maximum value.
6
0b
RO
MMC Receive IPV6 Header Error Frame Counter Interrupt Status
(RXIPV6HERFIS): This bit is set when the rxipv6_hdrerr_frms counter reaches half of
the maximum value or the maximum value.
5
0b
RO
MMC Receive IPV6 Good Frame Counter Interrupt Status (RXIPV6GFIS): This bit
is set when the rxipv6_gd_frms counter reaches half of the maximum value or the
maximum value.
4
0b
RO
MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status
(RXIPV4UDSBLFIS): This bit is set when the rxipv4_udsbl_frms counter reaches half
of the maximum value or the maximum value.
3
0b
RO
MMC Receive IPV4 Fragmented Frame Counter Interrupt Status
(RXIPV4FRAGFIS): This bit is set when the rxipv4_frag_frms counter reaches half of
the maximum value or the maximum value.
2
0b
RO
MMC Receive IPV4 No Payload Frame Counter Interrupt Status
(RXIPV4NOPAYFIS): This bit is set when the rxipv4_nopay_frms counter reaches half
of the maximum value or the maximum value.
1
0b
RO
MMC Receive IPV4 Header Error Frame Counter Interrupt Status
(RXIPV4HERFIS): This bit is set when the rxipv4_hdrerr_frms counter reaches half of
the maximum value or the maximum value.
0
0b
RO
MMC Receive IPV4 Good Frame Counter Interrupt Status (RXIPV4GFIS): This bit
is set when the rxipv4_gd_frms counter reaches half of the maximum value or the
maximum value.
MMC Receive IPV4 Good Frame Counter Register
(RXIPV4_GD_FRMS)—Offset 210h
Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 210h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Intel® Quark™ SoC X1000
Datasheet
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November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.75
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 Header Error Frame Counter Register
(RXIPV4_HDRERR_FRMS)—Offset 214h
Number of IPv4 datagrams received with header (checksum, length, or version
mismatch) errors.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 214h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.76
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 No Payload Frame Counter Register
(RXIPV4_NOPAY_FRMS)—Offset 218h
Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP
payload processed by the Checksum engine.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 218h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
November 2014
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Datasheet
383
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.77
MMC Receive IPV4 Fragmented Frame Counter Register
(RXIPV4_FRAG_FRMS)—Offset 21Ch
Number of good IPv4 datagrams with fragmentation.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 21Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.78
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 UDP Checksum Disabled Frame Counter
Register (RXIPV4_UDSBL_FRMS)—Offset 220h
Number of good IPv4 datagrams received that had a UDP payload with checksum
disabled.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 220h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.79
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV6 Good Frame Counter Register
(RXIPV6_GD_FRMS)—Offset 224h
Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads.
Access Method
Intel® Quark™ SoC X1000
Datasheet
384
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 224h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.80
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV6 Header Error Frame Counter Register
(RXIPV6_HDRERR_FRMS)—Offset 228h
Number of IPv6 datagrams received with header errors (length or version mismatch).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 228h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.81
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV6 No Payload Frame Counter Register
(RXIPV6_NOPAY_FRMS)—Offset 22Ch
Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP
payload. This includes all IPv6 datagrams with fragmentation or security extension
headers.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 22Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
November 2014
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Intel® Quark™ SoC X1000
Datasheet
385
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.82
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive UDP Good Frame Counter Register
(RXUDP_GD_FRMS)—Offset 230h
Number of good IP datagrams with a good UDP payload. This counter is not updated
when the rxipv4_udsbl_frms counter is incremented.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 230h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.83
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive UDP Error Frame Counter Register
(RXUDP_ERR_FRMS)—Offset 234h
Number of good IP datagrams whose UDP payload has a checksum error.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 234h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Intel® Quark™ SoC X1000
Datasheet
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November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
31:0
15.6.84
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive TCP Good Frame Counter Register
(RXTCP_GD_FRMS)—Offset 238h
Number of good IP datagrams with a good TCP payload.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 238h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.85
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive TCP Error Frame Counter Register
(RXTCP_ERR_FRMS)—Offset 23Ch
Number of good IP datagrams whose TCP payload has a checksum error.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 23Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.86
MMC Receive ICMP Good Frame Counter Register
(RXICMP_GD_FRMS)—Offset 240h
Number of good IP datagrams with a good ICMP payload.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 240h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.87
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive ICMP Error Frame Counter Register
(RXICMP_ERR_FRMS)—Offset 244h
Number of good IP datagrams whose ICMP payload has a checksum error.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 244h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.88
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 Good Octet Counter Register
(RXIPV4_GD_OCTETS)—Offset 250h
Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP
data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in
the octet counters listed below).
Access Method
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Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 250h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.89
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 Header Error Octet Counter Register
(RXIPV4_HDRERR_OCTETS)—Offset 254h
Number of bytes received in IPv4 datagrams with header errors (checksum, length,
version mismatch). The value in the Length field of IPv4 header is used to update this
counter.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 254h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.90
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 No Payload Octet Counter Register
(RXIPV4_NOPAY_OCTETS)—Offset 258h
Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP
payload. The value in the IPv4 headers Length field is used to update this counter.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 258h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.91
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 Fragmented Octet Counter Register
(RXIPV4_FRAG_OCTETS)—Offset 25Ch
Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4
headers Length field is used to update this counter.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 25Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.92
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV4 UDP Checksum Disabled Octet Counter
Register (RXIPV4_UDSBL_OCTETS)—Offset 260h
Number of bytes received in a UDP segment that had the UDP checksum disabled. This
counter does not count IP Header bytes.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 260h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
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Bit
Range
31:0
15.6.93
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV6 Good Octet Counter Register
(RXIPV6_GD_OCTETS)—Offset 264h
Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6
data.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 264h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.94
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV6 Good Octet Counter Register
(RXIPV6_HDRERR_OCTETS)—Offset 268h
Number of bytes received in IPv6 datagrams with header errors (length, version
mismatch). The value in the IPv6 headers Length field is used to update this counter.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 268h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
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Intel® Quark™ SoC X1000
Datasheet
391
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.95
MMC Receive IPV6 Header Error Octet Counter Register
(RXIPV6_NOPAY_OCTETS)—Offset 26Ch
Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP
payload. The value in the IPv6 headers Length field is used to update this counter.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 26Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.96
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive IPV6 No Payload Octet Counter Register
(RXUDP_GD_OCTETS)—Offset 270h
Number of bytes received in a good UDP segment. This counter (and the counters
below) does not count IP header bytes.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 270h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
CNT
0
Bit
Range
31:0
15.6.97
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive UDP Good Octet Counter Register
(RXUDP_ERR_OCTETS)—Offset 274h
Number of bytes received in a UDP segment that had checksum errors.
Access Method
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Datasheet
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Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 274h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.98
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive TCP Good Octet Counter Register
(RXTCP_GD_OCTETS)—Offset 278h
Number of bytes received in a good TCP segment.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 278h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
15.6.99
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
MMC Receive TCP Error Octet Counter Register
(RXTCP_ERR_OCTETS)—Offset 27Ch
Number of bytes received in a TCP segment with checksum errors.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 27Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
15.6.100 MMC Receive ICMP Good Octet Counter Register
(RXICMP_GD_OCTETS)—Offset 280h
Number of bytes received in a good ICMP segment.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 280h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
15.6.101 MMC Receive ICMP Error Octet Counter Register
(RXICMP_ERR_OCTETS)—Offset 284h
Number of bytes received in an ICMP segment with checksum errors.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 284h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CNT
0
28
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Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h
Counter value (CNT): Reserved.
RO
15.6.102 VLAN Tag Inclusion or Replacement Register (Register 353)
(GMAC_REG_353)—Offset 584h
The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or
replacement in the transmit frames.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 584h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
Bit
Range
31:20
Default &
Access
000h
RO
0
0
0
0
0
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
VLT
0
16
VLC
0
20
VLP
0
24
RSV0
0
28
CSVL
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
19
0b
RW
C-VLAN or S-VLAN (CSVL): When this bit is set, S-VLAN type (0x88A8) is inserted or
replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, CVLAN type (0x8100) is inserted or replaced in the transmitted frames.
18
0b
RW
VLAN Priority Control (VLP): When this bit is set, the control Bits [17:16] are used
for VLAN deletion, insertion, or replacement. When this bit is reset, the internal control
signal from the MTL layer is used, and Bits [17:16] are ignored.
00b
RW
VLAN Tag Control in Transmit Frames (VLC): 2'b00: No VLAN tag deletion,
insertion, or replacement
2'b01: VLAN tag deletion. The MAC removes the VLAN type (bytes 13 and 14) and VLAN
tag (bytes 15 and 16) of all transmitted frames with VLAN tags.
2'b10: VLAN tag insertion. The MAC inserts VLT in bytes 15 and 16 of the frame after
inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is
performed on all transmitted frames, irrespective of whether they already have a VLAN
tag.
2'b11: VLAN tag replacement. The MAC replaces VLT in bytes 15 and 16 of all VLAN-type
transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8).
NOTE: Changes to this field take effect only on the start of a frame. If you write this
register field when a frame is being transmitted, only the subsequent frame can use the
updated value, that is, the current frame does not use the updated value.
0000h
RW
VLAN Tag for Transmit Frames (VLT): This field contains the value of the VLAN tag
to be inserted or replaced. The value must only be changed when the transmit lines are
inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the
CFI/DEI, and Bits[11:0] are the VLAN tags VID field.
17:16
15:0
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.103 VLAN Hash Table Register (Register 354) (GMAC_REG_354)—
Offset 588h
The 16-bit Hash table is used for group address filtering based on VLAN tag when Bit
18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering, the content of
the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16 (ETV) of VLAN Tag Register) in
the incoming frame is passed through the CRC logic and the upper four bits of the
calculated CRC are used to index the contents of the VLAN Hash table. For example, a
hash value of 4b'1000 selects Bit 8 of the VLAN Hash table. The hash value of the
destination address is calculated in the following way: 1. Calculate the 32-bit CRC for
the VLAN tag or ID (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). 2.
Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper four bits
from the value obtained in Step 2. If the corresponding bit value of the register is 1'b1,
the frame is accepted. Otherwise, it is rejected.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 588h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
0
4
0
0
0
0
0
0
0
0
0
VLHT
RSV0
0
28
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Reserved (RSV0): Reserved.
15:0
0000h
RW
VLAN Hash Table (VLHT): This field contains the 16-bit VLAN Hash Table.
15.6.104 Timestamp Control Register (Register 448) (GMAC_REG_448)—
Offset 700h
This register controls the operation of the System Time generator and the processing of
PTP packets for timestamping in the Receiver.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 700h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00002000h
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Datasheet
396
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
TSENA
0
TSCFUPDT
0
TSINIT
0
TSTRIG
0
TSUPDT
0
0
TSADDREG
0
4
RSV0
0
TSENALL
0
TSCTRLSSR
0
TSIPENA
0
8
TSVER2ENA
0
TSIPV6ENA
0
TSIPV4ENA
0
12
TSEVNTENA
0
16
TSMSTRENA
0
20
SNAPTYPSEL
0
24
RSV4
0
28
TSENMACADDR
31
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Bit
Range
Default &
Access
Field Name (ID): Description
31:19
0b
RO
Reserved (RSV4): Reserved.
18
0b
RW
Enable MAC address for PTP Frame Filtering (TSENMACADDR): When set, the DA
MAC address (that matches any MAC Address register) is used to filter the PTP frames
when PTP is directly sent over Ethernet.
17:16
00b
RW
Select PTP packets for Taking Snapshots (SNAPTYPSEL): These bits along with
Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken.
15
0b
RW
Enable Snapshot for Messages Relevant to Master (TSMSTRENA): When set, the
snapshot is taken only for the messages relevant to the master node. Otherwise, the
snapshot is taken for the messages relevant to the slave node.
14
0b
RW
Enable Timestamp Snapshot for Event Messages (TSEVNTENA): When set, the
timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req,
or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce,
Management, and Signaling.
13
1b
RW
Enable Processing of PTP Frames Sent over IPv4-UDP (TSIPV4ENA): When set,
the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets.
When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This
bit is set by default.
12
0b
RW
Enable Processing of PTP Frames Sent Over IPv6-UDP (TSIPV6ENA): When set,
the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When
this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets.
11
0b
RW
Enable Processing of PTP over Ethernet Frames (TSIPENA): When set, the MAC
receiver processes the PTP packets encapsulated directly in the Ethernet frames. When
this bit is clear, the MAC ignores the PTP over Ethernet packets.
10
0b
RW
Enable PTP packet Processing for Version 2 Format (TSVER2ENA): When set, the
PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets
are processed using the version 1 format.
9
0b
RW
Timestamp Digital or Binary Rollover Control (TSCTRLSSR): When set, the
Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond
accuracy) and increments the timestamp (High) seconds. When reset, the rollover value
of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be
programmed correctly depending on the PTP reference clock frequency and the value of
this bit.
8
0b
RW
Enable Timestamp for All Frames (TSENALL): When set, the timestamp snapshot is
enabled for all frames received by the MAC.
7:6
00b
RO
Reserved (RSV0): Reserved.
5
0b
RW
Addend Reg Update (TSADDREG): When set, the content of the Timestamp Addend
register is updated in the PTP block for fine correction. This is cleared when the update
is completed. This register bit should be zero before setting it.
4
0b
RW
Timestamp Interrupt Trigger Enable (TSTRIG): When set, the timestamp interrupt
is generated when the System Time becomes greater than the value written in the
Target Time register. This bit is reset after the generation of the Timestamp Trigger
Interrupt.
3
0b
RW
Timestamp Update (TSUPDT): When set, the system time is updated (added or
subtracted) with the value specified in Register 452 (System Time - Seconds Update
Register) and Register 453 (System Time - Nanoseconds Update Register).
This bit should be read zero before updating it. This bit is reset when the update is
completed in hardware. The Timestamp Higher Word register (if enabled during core
configuration) is not updated.
2
0b
RW
Timestamp Initialize (TSINIT): When set, the system time is initialized (overwritten)
with the value specified in the Register 452 (System Time - Seconds Update Register)
and Register 453 (System Time - Nanoseconds Update Register).
This bit should be read zero before updating it. This bit is reset when the initialization is
complete. The Timestamp Higher Word register (if enabled during core configuration)
can only be initialized.
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
Field Name (ID): Description
1
0b
RW
Timestamp Fine or Coarse Update (TSCFUPDT): When set, this bit indicates that
the system times update should be done using the fine update method. When reset, it
indicates the system timestamp update should be done using the Coarse method.
0
0b
RW
Timestamp Enable (TSENA): When set, the timestamp is added for the transmit and
receive frames. When disabled, timestamp is not added for the transmit and receive
frames and the Timestamp Generator is also suspended. You need to initialize the
Timestamp (system time) after enabling this mode. On the receive side, the MAC
processes the 1588 frames only if this bit is set.
15.6.105 Sub-Second Increment Register (Register 449)
(GMAC_REG_449)—Offset 704h
In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this register is
added to the system time every clock cycle of the internal 50MHz PTP reference clock.
In the Fine Update mode, the value in this register is added to the system time
whenever the Accumulator gets an overflow.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 704h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
31:8
7:0
Default &
Access
000000h
RO
00h
RW
4
0
0
0
0
0
0
0
0
0
SSINC
RSV0
0
28
Field Name (ID): Description
Reserved (RSV0): Reserved.
Sub-second Increment Value (SSINC): The value programmed in this field is
accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second
register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program
20 (0x14) when the System Time-Nanoseconds register has an accuracy of 1 ns
(TSCTRLSSR bit is set). When TSCTRLSSR is clear, the Nanoseconds register has a
resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is
derived by 20ns/0.465.
15.6.106 System Time - Seconds Register (Register 450)
(GMAC_REG_450)—Offset 708h
The System Time -Seconds register, along with System-TimeNanoseconds register,
indicates the current value of the system time maintained by the MAC. Though it is
updated on a continuous basis, there is some delay from the actual time because of
clock domain transfer latencies.
Access Method
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Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 708h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
12
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TSS
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h Timestamp Second (TSS): The value in this field indicates the current value in
seconds of the System Time maintained by the MAC.
RO
15.6.107 System Time - Nanoseconds Register (Register 451)
(GMAC_REG_451)—Offset 70Ch
The value in this field has the sub second representation of time, with an accuracy of
0.46 ns. When TSCTRLSSR is set, each bit represents 1 ns and the maximum value is
0x3B9A_C9FF, after which it rolls-over to zero.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 70Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TSSS
RSV0
0
28
Bit
Range
31
30:0
Default &
Access
0b
RO
Field Name (ID): Description
Reserved (RSV0): Reserved.
Timestamp Sub Seconds (TSSS): The value in this field has the sub second
00000000h representation of time, with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in
Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum
RO
value is 0x3B9A_C9FF, after which it rolls-over to zero.
15.6.108 System Time - Seconds Update Register (Register 452)
(GMAC_REG_452)—Offset 710h
The System Time - Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the
MAC. You must write both of these registers before setting the TSINIT or TSUPDT bits
in the Timestamp Control register.
Access Method
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 710h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
12
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TSS
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h Timestamp Second (TSS): The value in this field indicates the time in seconds to be
initialized or added to the system time.
RW
15.6.109 System Time - Nanoseconds Update Register (Register 453)
(GMAC_REG_453)—Offset 714h
The System Time - Nanoseconds Update register, along with the System Time Seconds Update register, initializes or updates the system time maintained by the MAC.
You must write both of these registers before setting the TSINIT or TSUPDT bits in the
Timestamp Control register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 714h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TSSS
ADDSUB
0
28
Bit
Range
31
30:0
Default &
Access
Field Name (ID): Description
0b
RW
Add or subtract time (ADDSUB): When this bit is set, the time value is subtracted
with the contents of the update register. When this bit is reset, the time value is added
with the contents of the update register.
Timestamp Sub Second (TSSS): The value in this field has the sub second
00000000h representation of time, with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in
Register 448 (Timestamp Control Register), each bit represents 1 ns and the
RW
programmed value should not exceed 0x3B9A_C9FF.
15.6.110 Timestamp Addend Register (Register 454) (GMAC_REG_454)—
Offset 718h
This register value is used only when the system time is configured for Fine Update
mode (TSCFUPDT bit in Register 448). This register content is added to a 32-bit
accumulator in every clock cycle (of the internal 50MHz PTP reference clock) and the
system time is updated whenever the accumulator overflows.
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 718h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TSAR
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h Timestamp Addend (TSAR): This field indicates the 32-bit time value to be added to
the Accumulator register to achieve time synchronization.
RW
15.6.111 Target Time Seconds Register (Register 455)
(GMAC_REG_455)—Offset 71Ch
The Target Time Seconds register, along with Target Time Nanoseconds register, is used
to schedule an interrupt event (Register 458[1] when Advanced Timestamping is
enabled; otherwise, TS interrupt bit in Register14[9]) when the system time exceeds
the value programmed in these registers.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 71Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TSTR
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
Target Time Seconds (TSTR): This field stores the time in seconds. When the
00000000h timestamp value matches or exceeds both Target Timestamp registers, then based on
Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal
RW
output and generates an interrupt (if enabled).
15.6.112 Target Time Nanoseconds Register (Register 456)
(GMAC_REG_456)—Offset 720h
This register is present only when the IEEE 1588 Timestamp feature is selected without
external timestamp input.
Access Method
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Datasheet
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 720h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TTSLO
TRGTBUSY
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
0b
RO
Target Time Register Busy (TRGTBUSY): The MAC sets this bit when the PPSCMD
field (Bits[3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011.
Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the
Target Time Registers to the PTP clock domain.
The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock
domain The application must not update the Target Time Registers when this bit is read
as 1. Otherwise, the synchronization of the previous programmed time gets corrupted.
This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not
selected.
31
30:0
Target Timestamp Low (TTSLO): The Target Time Nanoseconds register, along with
00000000h Target Time Seconds register, is used to schedule an interrupt event (Register 458[1]
when Advanced Timestamping is enabled; otherwise, TS interrupt bit in Register14[9])
RW
when the system time exceeds the value programmed in these registers.
15.6.113 System Time - Higher Word Seconds Register (Register 457)
(GMAC_REG_457)—Offset 724h
Contains the most significant 16-bits of the timestamp seconds value.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 724h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
RSV0
0
28
Bit
Range
Default &
Access
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TSHWR
31
Field Name (ID): Description
31:16
0000h
RO
Reserved (RSV0): Reserved.
15:0
0000h
RW
Timestamp Higher Word (TSHWR): This field contains the most significant 16-bits of
the timestamp seconds value. The register is directly written to initialize the value. This
register is incremented when there is an overflow from the 32-bits of the System Time Seconds register.
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
15.6.114 Timestamp Status Register (Register 458) (GMAC_REG_458)—
Offset 728h
All non reserved bits are cleared when the host reads this register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 728h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:10
0b
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TSSOVF
0
TSTARGT
0
AUXTSTRIG
0
0
TSTARGT1
0
4
TSTRGTERR
0
8
TSTARGT2
0
12
TSTRGTERR1
0
16
TSTARGT3
0
20
TSTRGTERR2
0
24
RSV0
0
28
TSTRGTERR3
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
9
0b
RO/CR
Timestamp Target Time Error (TSTRGTERR3): This bit is set when the target time,
being programmed in Register 496 and Register 497, is already elapsed. This bit is
cleared when read by the application.
8
0b
RO/CR
Timestamp Target Time Reached for Target Time PPS3 (TSTARGT3): When set,
this bit indicates that the value of system time is greater than or equal to the value
specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3
Target Time Low Register).
7
0b
RO/CR
Timestamp Target Time Error (TSTRGTERR2): This bit is set when the target time,
being programmed in Register 488 and Register 489, is already elapsed. This bit is
cleared when read by the application.
6
0b
RO/CR
Timestamp Target Time Reached for Target Time PPS2 (TSTARGT2): When set,
this bit indicates that the value of system time is greater than or equal to the value
specified in Register 488 (PPS2 Target Time High Register) and Register 489 (PPS2
Target Time Low Register).
5
0b
RO/CR
Timestamp Target Time Error (TSTRGTERR1): This bit is set when the target time,
being programmed in Register 480 and Register 481, is already elapsed. This bit is
cleared when read by the application.
4
0b
RO/CR
Timestamp Target Time Reached for Target Time PPS1 (TSTARGT1): When set,
this bit indicates that the value of system time is greater than or equal to the value
specified in Register 480 (PPS1 Target Time High Register) and Register 481 (PPS1
Target Time Low Register).
3
0b
RO/CR
Timestamp Target Time Error (TSTRGTERR): This bit is set when the target time,
being programmed in Target Time Registers, is already elapsed. This bit is cleared when
read by the application.
2
0b
RO
1
0b
RO/CR
Timestamp Target Time Reached (TSTARGT): When set, this bit indicates that the
value of system time is greater or equal to the value specified in the Register 455
(Target Time Seconds Register) and Register 456 (Target Time Nanoseconds Register).
0
0b
RO/CR
Timestamp Seconds Overflow (TSSOVF): When set, this bit indicates that the
seconds value of the timestamp (when supporting version 2 format) has overflowed
beyond 32'hFFFF_FFFF.
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Reserved (AUXTSTRIG): Reserved.
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15.6.115 Bus Mode Register (Register 0) (DMA_REG_0)—Offset 1000h
The Bus Mode register establishes the bus operating modes for the DMA.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1000h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00020101h
Bit
Range
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
DA
0
SWR
0
0
DSL
USP
Default &
Access
0
4
ATDS
0
8
PBL
0
12
PR
0
16
FB
0
RPBL
0
PBL8X
20
MB
0
24
AAL
0
PRWG
RIX
0
RSV0
0
28
TXPR
31
Field Name (ID): Description
31
0b
RW
RIX: Rebuild INCRx Burst
When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing
bus grant), the AHB master interface rebuilds the pending beats of any burst
transfer initiated with INCRx. The AHB master interface rebuilds the beats with a
combination of specified bursts with INCRx and SINGLE. By default, the AHB
master interface rebuilds pending beats of an EBT with an unspecified (INCR)
burst.
This bit is valid only in the GMAC-AHB configuration. It is reserved in all other
configuration.
30
0b
RO
Reserved (RSV0): Reserved.
29:28
00b
RO
Channel Priority Weights (PRWG): This field sets the priority weights for Channel 0
during the round-robin arbitration between the DMA channels for the system bus.
00: The priority weight is 1.
01: The priority weight is 2.
10: The priority weight is 3.
11: The priority weight is 4.
27
0b
RW
Transmit Priority (TXPR): When set, this bit indicates that the transmit DMA has
higher priority than the receive DMA during arbitration for the system-side bus.
26
0b
RW
Mixed Burst (MB): When this bit is set high and the FB bit is low, the AHB Master
interface starts all bursts of length more than 16 with INCR (undefined burst) whereas it
reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.
NOTE: for bandwidth reason, it is recommended to avoid using mixed bursts.
Recommended setting is MB=0, FB=1.
25
0b
RW
Address Aligned Beats (AAL): When this bit is set high and the FB bit is equal to 1,
the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit
is equal to 0, the first burst (accessing the data buffer's start address) is not aligned,
but subsequent bursts are aligned to the address.
24
0b
RW
8xPBL Mode (PBL8X): When set high, this bit multiplies the programmed PBL value
(Bits[22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8,
16, 32, 64, 128, and 256 beats depending on the PBL value.
NOTE: This bit function is not backward compatible. Before release 3.50a, this bit was
4xPBL.
23
0b
RW
Use Separate PBL (USP): When set high, this bit configures the Rx DMA to use the
value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to
the Tx DMA operations.
When reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines.
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Bit
Range
22:17
16
15:14
13:8
7
6:2
1
0
Default &
Access
Field Name (ID): Description
000001b
RW
Rx DMA PBL (RPBL): This field indicates the maximum number of beats to be
transferred in one Rx DMA transaction. This is the maximum value that is used in a
single block Read or Write.
The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a
Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and
32. Any other value results in undefined behavior. This field is valid and applicable only
when USP is set high.
0b
RW
Fixed Burst (FB): This bit controls whether the AHB or AXI Master interface performs
fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4,
INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or
AXI interface uses SINGLE and INCR burst transfer operations.
NOTE: for bandwidth reason, it is recommended to avoid using mixed bursts.
Recommended setting is MB=0, FB=1.
00b
RW
Priority Ratio (PR): These bits control the priority ratio in the weighted round-robin
arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA)
is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset
or set.
00: The Priority Ratio is 1:1.
01: The Priority Ratio is 2:1.
10: The Priority Ratio is 3:1.
11: The Priority Ratio is 4:1.
000001b
RW
Programmable Burst Length (PBL): These bits indicate the maximum number of
beats to be transferred in one DMA transaction. This is the maximum value that is used
in a single block Read or Write. The DMA always attempts to burst as specified in PBL
each time it starts a Burst transfer on the host bus. PBL can be programmed with
permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined
behavior. When USP is set high, this PBL value is applicable only for Tx DMA
transactions. If the number of beats to be transferred is more than 32, then perform the
following steps:
1. Set the 8xPBL mode.
2. Set the PBL.
For example, if the maximum number of beats to be transferred is 64, then first set
8xPBL to 1 and then set PBL to 8.
All values up to 256 are allowed using a combination of PBL and 8xPBL. All PBL values
are supported in the full-duplex mode and half-duplex modes.
0b
RW
Alternate (Enhanced) Descriptor Size (ATDS): When set, the size of the alternate
descriptor increases to 32 bytes (8 DWORDS). This is required when the Advanced
Timestamp feature or the IPC Full Offload Engine (Type 2) is enabled in the receiver. The
enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum
Offload (Type 2) features are not enabled. In such cases, you can use the 16 bytes
descriptor to save 4 bytes of memory.
When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). This bit preserves
the backward compatibility for the descriptor size.
00000b
RW
Descriptor Skip Length (DSL): This bit specifies the number of Word, Dword, or
Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained
descriptors. The address skipping starts from the end of current descriptor to the start
of next descriptor. When the DSL value is equal to zero, then the descriptor table is
taken as contiguous by the DMA in Ring mode.
0b
RW
DMA Arbitration Scheme (DA): This bit specifies the arbitration scheme between the
transmit and receive paths of Channel 0.
0: Weighted round-robin with Rx:Tx or Tx:Rx. The priority between the paths is
according to the priority specified in bits 15:14 (PR) and priority weights specified in Bit
27 (TXPR).
1: Fixed priority. The transmit path has priority over receive path when Bit 27 (TXPR) is
set. Otherwise, receive path has priority over the transmit path.
1b
RW
Software Reset (SWR): When this bit is set, the MAC DMA Controller resets the logic
and all internal registers of the MAC. It is cleared automatically after the reset operation
has completed in all of the MAC clock domains. Before reprogramming any register of
the MAC, you should read a zero (0) value in this bit .
NOTE: The reset operation is completed only when all resets in all active clock domains
are de-asserted. Therefore, it is essential that all the PHY inputs clocks (applicable for
the selected PHY interface) are present for the software reset completion.
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15.6.116 Transmit Poll Demand Register (Register 1) (DMA_REG_1)—
Offset 1004h
The Transmit Poll Demand register enables the Tx DMA to check whether or not the
DMA owns the current descriptor. The Transmit Poll Demand command is given to wake
up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the Suspend mode
because of an Underflow error in a transmitted frame or the unavailability of
descriptors owned by it. You can give this command anytime and the Tx DMA resets
this command when it again starts fetching the current descriptor from host memory.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1004h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
TPD
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
Transmit Poll Demand (TPD): When these bits are written with any value, the DMA
00000000b reads the current descriptor pointed to by Register 18 (Current Host Transmit Descriptor
31:0
Register). If that descriptor is not available (owned by the Host), the transmission
RW
returns to the Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is
asserted. If the descriptor is available, the transmission resumes.
15.6.117 Receive Poll Demand Register (Register 2) (DMA_REG_2)—
Offset 1008h
The Receive Poll Demand register enables the receive DMA to check for new
descriptors. This command is used to wake up the Rx DMA from the Suspend state. The
RxDMA can go into the Suspend state only because of the unavailability of descriptors it
owns.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1008h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
RPD
0
28
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
Receive Poll Demand (RPD): When these bits are written with any value, the DMA
00000000b reads the current descriptor pointed to by Register 19 (Current Host Receive Descriptor
31:0
Register). If that descriptor is not available (owned by the Host), the reception returns
RW
to the Suspended state and the Bit 7 (RU) of Register 5 (Status Register) is not
asserted. If the descriptor is available, the Rx DMA returns to the active state.
15.6.118 Receive Descriptor List Address Register (Register 3)
(DMA_REG_3)—Offset 100Ch
The Receive Descriptor List Address register points to the start of the Receive
Descriptor List. The descriptor lists reside in the host's physical memory space and
must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The
DMA internally converts it to bus width aligned address by making the corresponding
LS bits low. Writing to this register is permitted only when reception is stopped. When
stopped, this register must be written to before the receive Start command is given.
You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR) is set
to zero in Register 6 (Operation Mode Register). When stopped, this register can be
written with a new descriptor list address. When you set the SR bit to 1, the DMA takes
the newly programmed descriptor base address. If this register is not changed when
the SR bit is set to 0, then the DMA takes the descriptor address where it was stopped
earlier.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 100Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
RDESLA_32BIT
0
28
Bit
Range
31:2
1:0
Default &
Access
0
0
0
0
0
0
RSV0
31
Field Name (ID): Description
Start of Receive List (RDESLA_32BIT): This field contains the base address of the
00000000h first descriptor in the Receive Descriptor list. The LSB bits (1:0) for 32-bit bus width are
ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are readRW
only (RO).
00b
RO
Reserved (RSV0): Reserved.
15.6.119 Transmit Descriptor List Address Register (Register 4)
(DMA_REG_4)—Offset 1010h
The Transmit Descriptor List Address register points to the start of the Transmit
Descriptor List. The descriptor lists reside in the host's physical memory space and
must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The
DMA internally converts it to bus width aligned address by making the corresponding
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
LSB to low. You can write to this register only when the Tx DMA has stopped, that is,
Bit 13 (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this
register can be written with a new descriptor list address. When you set the ST bit to 1,
the DMA takes the newly programmed descriptor base address. If this register is not
changed when the ST bit is set to 0, then the DMA takes the descriptor address where
it was stopped earlier.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1010h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
TDESLA_32BIT
0
28
Bit
Range
Default &
Access
31:2
0
0
RSV0
31
Field Name (ID): Description
Start of Transmit List (TDESLA_32BIT): This field contains the base address of the
00000000h first descriptor in the Transmit Descriptor list. The LSB bits (1:0) for 32-bit bus width are
ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are
RW
read-only (RO).
00b
RO
1:0
Reserved (RSV0): Reserved.
15.6.120 Status Register (Register 5) (DMA_REG_5)—Offset 1014h
The Status register contains all status bits that the DMA reports to the host. The
Software driver reads this register during an interrupt service routine or polling. Most of
the fields in this register cause the host to be interrupted. The bits of this register are
not cleared when read. Writing 1'b1 to (unreserved) Bits[16:0] of this register clears
these bits and writing 1'b0 has no effect. Each field (Bits[16:0]) can be masked by
masking the appropriate bit in Register 7 (Interrupt Enable Register).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1014h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
TI
0
TPS
0
TU
0
TJT
0
OVF
0
RI
0
UNF
0
0
RU
0
4
RPS
0
ETI
0
8
RWT
0
RSV0
0
FBI
0
ERI
0
AIS
GLI
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Datasheet
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0
12
NIS
0
16
RS
0
20
TS
0
EB
0
GMI
0
24
TTI
RSV2
0
28
RSV1
31
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Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0b
RO
Reserved (RSV2): Reserved.
29
0b
RO
Timestamp Trigger Interrupt (TTI): This bit indicates an interrupt event in the
Timestamp Generator block of MAC. The software must read the corresponding registers
in the MAC to get the exact cause of interrupt and clear its source to reset this bit to
1'b0. When this bit is high, the interrupt signal from the MAC subsystem is high.
28
0b
RO
Reserved (RSV1): Reserved.
27
0b
RO
MAC MMC Interrupt (GMI): This bit reflects an interrupt event in the MAC
Management Counters (MMC) module. The software must read the corresponding
registers in the MAC to get the exact cause of interrupt and clear the source of interrupt
to make this bit as 1'b0. The interrupt signal from the MAC subsystem is high when this
bit is high.
26
0b
RO
Reserved (GLI): Reserved.
25:23
22:20
19:17
16
000b
RO
Error Bits (EB): This field indicates the type of error that caused a Bus Error, for
example, error response on the AHB or AXI interface. This field is valid only when Bit 13
(FBI) is set. This field does not generate an interrupt.
* Bit 23
1'b1: Error during data transfer by the Tx DMA
1'b0: Error during data transfer by the Rx DMA
* Bit 24
1'b1: Error during read transfer
1'b0: Error during write transfer
* Bit 25
1'b1: Error during descriptor access
1'b0: Error during data buffer access
000b
RO
Transmit Process State (TS): This field indicates the Transmit DMA FSM state. This
field does not generate an interrupt.
3'b000: Stopped; Reset or Stop Transmit Command issued
3'b001: Running; Fetching Transmit Transfer Descriptor
3'b010: Running; Waiting for status
3'b011: Running; Reading Data from host memory buffer and queuing it to transmit
buffer (Tx FIFO)
3'b100: TIME_STAMP write state
3'b101: Reserved for future use
3'b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow
3'b111: Running; Closing Transmit Descriptor
000b
RO
Received Process State (RS): This field indicates the Receive DMA FSM state. This
field does not generate an interrupt.
3'b000: Stopped: Reset or Stop Receive Command issued
3'b001: Running: Fetching Receive Transfer Descriptor
3'b010: Reserved for future use
3'b011: Running: Waiting for receive packet
3'b100: Suspended: Receive Descriptor Unavailable
3'b101: Running: Closing Receive Descriptor
3'b110: TIME_STAMP write state
3'b111: Running: Transferring the receive packet data from receive buffer to host
memory
0b
RW
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Document Number: 329676-004US
Normal Interrupt Summary (NIS): Normal Interrupt Summary bit value is the logical
OR of the following when the corresponding interrupt bits are enabled in Register 7
(Interrupt Enable Register):
Register 5[0]: Transmit Interrupt
Register 5[2]: Transmit Buffer Unavailable
Register 5[6]: Receive Interrupt
Register 5[14]: Early Receive Interrupt
Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the
Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing 1 to this bit) each time a
corresponding bit, which causes NIS to be set, is cleared.
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
Field Name (ID): Description
15
0b
RW
Abnormal Interrupt Summary (AIS): Abnormal Interrupt Summary bit value is the
logical OR of the following when the corresponding interrupt bits are enabled in Register
7 (Interrupt Enable Register):
Register 5[1]: Transmit Process Stopped
Register 5[3]: Transmit Jabber Timeout
Register 5[4]: Receive FIFO Overflow
Register 5[5]: Transmit Underflow
Register 5[7]: Receive Buffer Unavailable
Register 5[8]: Receive Process Stopped
Register 5[9]: Receive Watchdog Timeout
Register 5[10]: Early Transmit Interrupt
Register 5[13]: Fatal Bus Error
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This is a sticky bit and must be cleared each time a corresponding bit, which causes AIS
to be set, is cleared.
14
0b
RW
Early Receive Interrupt (ERI): This bit indicates that the DMA had filled the first data
buffer of the packet. Bit 6 (RI) of this register automatically clears this bit.
13
0b
RW
Fatal Bus Error Interrupt (FBI): This bit indicates that a bus error occurred, as
described in Bits[25:23]. When this bit is set, the corresponding DMA engine disables all
of its bus accesses.
12:11
00b
RO
Reserved (RSV0): Reserved.
10
0b
RW
Early Transmit Interrupt (ETI): This bit indicates that the frame to be transmitted is
fully transferred to the MTL Transmit FIFO.
9
0b
RW
Receive Watchdog Timeout (RWT): This bit is asserted when a frame with length
greater than 2,048 bytes is received (10, 240 when Jumbo Frame mode is enabled).
8
0b
RW
Receive Process Stopped (RPS): This bit is asserted when the Receive Process enters
the Stopped state.
7
0b
RW
Receive Buffer Unavailable (RU): This bit indicates that the host owns the Next
Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is
suspended. To resume processing Receive descriptors, the host should change the
ownership of the descriptor and issue a Receive Poll Demand command. If no Receive
Poll Demand is issued, the Receive Process resumes when the next recognized incoming
frame is received. This bit is set only when the previous Receive Descriptor is owned by
the DMA.
6
0b
RW
Receive Interrupt (RI): This bit indicates that the frame reception is complete. When
reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in
the last Descriptor, and the specific frame status information is updated in the
descriptor. The reception remains in the Running state.
5
0b
RW
Transmit Underflow (UNF): This bit indicates that the Transmit Buffer had an
Underflow during frame transmission. Transmission is suspended and an Underflow
Error TDES0[1] is set.
4
0b
RW
Receive Overflow (OVF): This bit indicates that the Receive Buffer had an Overflow
during frame reception. If the partial frame is transferred to the application, the
overflow status is set in RDES0[11].
3
0b
RW
Transmit Jabber Timeout (TJT): This bit indicates that the Transmit Jabber Timer
expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the
Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is
aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout
TDES0[14] flag to assert.
2
0b
RW
Transmit Buffer Unavailable (TU): This bit indicates that the host owns the Next
Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is
suspended. Bits[22:20] explain the Transmit Process state transitions.
To resume processing Transmit descriptors, the host should change the ownership of the
descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command.
1
0b
RW
Transmit Process Stopped (TPS): This bit is set when the transmission is stopped.
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0b
RW
Transmit Interrupt (TI): This bit indicates that the frame transmission is complete.
When transmission is complete, the Bit 31 (Interrupt on Completion) of TDES1 is reset
in the first descriptor, and the specific frame status information is updated in the
descriptor.
0
15.6.121 Operation Mode Register (Register 6) (DMA_REG_6)—Offset
1018h
The Operation Mode register establishes the Transmit and Receive operating modes and
commands. This register should be the last CSR to be written as part of the DMA
initialization.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1018h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SR
0
RSV0
0
0
OSF
0
RTC
0
RSV1
FTF
0
FEF
TSF
Default &
Access
0
FUF
0
4
EFC
0
8
RFA
0
RFD
0
ST
0
12
TTC
0
16
RSV5
0
RFD_2
0
DFF
0
RFA_2
0
20
DT
0
24
RSV8
0
28
RSF
31
Field Name (ID): Description
31:27
0h
RO
Reserved (RSV8): Reserved.
26
0b
RW
Disable Dropping of TCP/IP Checksum Error Frames (DT): When this bit is set,
the MAC does not drop the frames which only have errors detected by the Receive
Checksum Offload engine. Such frames do not have any errors (including FCS error) in
the Ethernet frame received by the MAC but have errors only in the encapsulated
payload. When this bit is reset, all error frames are dropped if the FEF bit is reset.
25
0b
RW
Receive Store and Forward (RSF): When this bit is set, the MTL reads a frame from
the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits.
When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the
threshold specified by the RTC bits.
24
0b
RW
Disable Flushing of Received Frames (DFF): When this bit is set, the Rx DMA does
not flush any frames because of the unavailability of receive descriptors or buffers as it
does normally when this bit is reset.
0b
RW
MSB of Threshold for Activating Flow Control (RFA_2): If the Rx FIFO depth is 8
KB or more, this bit (when set) provides additional threshold levels for activating the
flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit)
along with the RFA (Bits[10:9]) gives the following thresholds for activating flow
control:
100: Full minus 5 KB, that is, FULL - 5KB
101: Full minus 6 KB, that is, FULL - 6KB
110: Full minus 7 KB, that is, FULL - 7KB
111: Reserved
23
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Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
Bit
Range
Default &
Access
Field Name (ID): Description
22
0b
RW
MSB of Threshold for Deactivating Flow Control (RFD_2): If the Rx FIFO size is 8
KB or more, this bit (when set) provides additional threshold levels for deactivating the
flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit)
along with the RFD (Bits[12:11]) gives the following thresholds for deactivating flow
control:
100: Full minus 5 KB, that is, FULL - 5KB
101: Full minus 6 KB, that is, FULL - 6KB
110: Full minus 7 KB, that is, FULL - 7KB
111: Reserved
21
0b
RW
Transmit Store and Forward (TSF): When this bit is set, transmission starts when a
full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values
specified in Bits[16:14] are ignored. This bit should be changed only when the
transmission is stopped.
0b
RW
Flush Transmit FIFO (FTF): When this bit is set, the transmit FIFO controller logic is
reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is
cleared internally when the flushing operation is completed. The Operation Mode
register should not be written to until this bit is cleared. The data which is already
accepted by the MAC transmitter is not flushed. It is scheduled for transmission and
results in underflow and runt frame transmission.
NOTE: The flush operation is complete only when the Tx FIFO is emptied of its contents
and all the pending Transmit Status of the transmitted frames are accepted by the host.
To complete this flush operation, the PHY transmit clock is required to be active.
20
19:17
16:14
13
12:11
Intel® Quark™ SoC X1000
Datasheet
412
000b
RO
Reserved (RSV5): Reserved.
000b
RW
Transmit Threshold Control (TTC): These bits control the threshold level of the MTL
Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is
larger than the threshold. In addition, full frames with a length less than the threshold
are also transmitted. These bits are used only when Bit 21 (TSF) is reset.
000: 64
001: 128
010: 192
011: 256
100: 40
101: 32
110: 24
111: 16
0b
RW
Start or Stop Transmission Command (ST): When this bit is set, transmission is
placed in the Running state, and the DMA checks the Transmit List at the current
position for a frame to be transmitted. Descriptor acquisition is attempted either from
the current position in the list, which is the Transmit List Base Address set by Register 4
(Transmit Descriptor List Address Register), or from the position retained when
transmission was stopped previously. If the DMA does not own the current descriptor,
transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of
Register 5 (Status Register) is set. The Start Transmission command is effective only
when transmission is stopped. If the command is issued before setting Register 4
(Transmit Descriptor List Address Register), then the DMA behavior is unpredictable.
When this bit is reset, the transmission process is placed in the Stopped state after
completing the transmission of the current frame. The Next Descriptor position in the
Transmit List is saved, and it becomes the current position when transmission is
restarted. To change the list address, you need to program Register 4 (Transmit
Descriptor List Address Register) with a new value when this bit is reset. The new value
is considered when this bit is set again. The stop transmission command is effective only
when the transmission of the current frame is complete or the transmission is in the
Suspended state.
00b
RW
Threshold for Deactivating Flow Control (RFD): These bits control the threshold
(Fill-level of Rx FIFO) at which the flow control is de-asserted after activation (in halfduplex and full-duplex).
00: Full minus 1 KB, that is, FULL - 1KB
01: Full minus 2 KB, that is, FULL - 2KB
10: Full minus 3 KB, that is, FULL - 3KB
11: Full minus 4 KB, that is, FULL - 4KB
The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or
more, an additional bit (RFD[2]) is used for more threshold levels as described in Bit 22.
November 2014
Document Number: 329676-004US
10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
10:9
00b
RW
Threshold for Activating Flow Control (RFA): These bits control the threshold (Fill
level of Rx FIFO) at which the flow control is activated (in half-duplex and full-duplex).
00: Full minus 1 KB, that is, FULL - 1KB
01: Full minus 2 KB, that is, FULL - 2KB
10: Full minus 3 KB, that is, FULL - 3KB
11: Full minus 4 KB, that is, FULL - 4KB
These values only apply to Rx FIFOs of 4 KB or more when the EFC bit is set high. If the
Rx FIFO is 8 KB or more, an additional bit (RFA[2]) is used for more threshold levels as
described in Bit 23.
8
0b
RW
Enable HW Flow Control (EFC): When this bit is set, the flow control signal operation
based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is
disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than
4 KB.
0b
RW
Forward Error Frames (FEF): When this bit is reset, the Rx FIFO drops frames with
error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
overflow). However, if the start byte (write) pointer of a frame is already transferred to
the read controller side (in Threshold mode), then the frame is not dropped.
When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If
the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then
the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is
reset and the Rx FIFO overflows when a partial frame is written, then a partial frame
may be forwarded to the DMA.
6
0b
RW
Forward Undersized Good Frames (FUF): When set, the Rx FIFO forwards
Undersized frames (frames with no Error and length less than 64 bytes) including padbytes and CRC.
When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is
already transferred because of the lower value of Receive Threshold, for example, RTC =
01.
5
0b
RO
Reserved (RSV1): Reserved.
4:3
00b
RW
Receive Threshold Control (RTC): These two bits control the threshold level of the
MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL
Receive FIFO is larger than the threshold. In addition, full frames with length less than
the threshold are transferred automatically.
These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is
set to 1.
00: 64
01: 32
10: 96
11: 128
2
0b
RW
Operate on Second Frame (OSF): When this bit is set, it instructs the DMA to process
the second frame of the Transmit data even before the status for the first frame is
obtained.
1
0b
RW
Start or Stop Receive (SR): When this bit is set, the Receive process is placed in the
Running state. The DMA attempts to acquire the descriptor from the Receive list and
processes the incoming frames. The descriptor acquisition is attempted from the current
position in the list, which is the address set by Register 3 (Receive Descriptor List
Address Register) or the position retained when the Receive process was previously
stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7
(Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive
command is effective only when the reception has stopped. If the command is issued
before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is
unpredictable.
When this bit is cleared, the Rx DMA operation is stopped after the transfer of the
current frame. The next descriptor position in the Receive list is saved and becomes the
current position after the Receive process is restarted. The Stop Receive command is
effective only when the Receive process is in either the Running (waiting for receive
packet) or in the Suspended state.
0
0b
RO
Reserved (RSV0): Reserved.
7
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Intel® Quark™ SoC X1000
Datasheet
413
Intel® Quark™ SoC X1000—10/100 Mbps Ethernet
15.6.122 Interrupt Enable Register (Register 7) (DMA_REG_7)—Offset
101Ch
The Interrupt Enable register enables the interrupts reported by Register 5 (Status
Register). Setting a bit to 1'b1 enables a corresponding interrupt. After a hardware or
software reset, all interrupts are disabled.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 101Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
Bit
Range
Default &
Access
31:17
0000h
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIE
0
TSE
0
TJE
0
TUE
0
OVE
0
RIE
0
0
UNE
0
RSE
0
4
RUE
0
ETE
0
8
RWE
0
RSV0
0
12
FBE
0
16
AIE
0
20
ERE
0
24
RSV1
0
28
NIE
31
Field Name (ID): Description
Reserved (RSV1): Reserved.
0b
RW
Normal Interrupt Summary Enable (NIE): When this bit is set, normal interrupt
summary is enabled. When this bit is reset, normal interrupt summary is disabled. This
bit enables the following interrupts in Register 5 (Status Register):
Register 5[0]: Transmit Interrupt
Register 5[2]: Transmit Buffer Unavailable
Register 5[6]: Receive Interrupt
Register 5[14]: Early Receive Interrupt
15
0b
RW
Abnormal Interrupt Summary Enable (AIE): When this bit is set, abnormal
interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is
disabled. This bit enables the following interrupts in Register 5 (Status Register):
Register 5[1]: Transmit Process Stopped
Register 5[3]: Transmit Jabber Timeout
Register 5[4]: Receive Overflow
Register 5[5]: Transmit Underflow
Register 5[7]: Receive Buffer Unavailable
Register 5[8]: Receive Process Stopped
Register 5[9]: Receive Watchdog Timeout
Register 5[10]: Early Transmit Interrupt
Register 5[13]: Fatal Bus Error
14
0b
RW
Early Receive Interrupt Enable (ERE): When this bit is set with Normal Interrupt
Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset,
the Early Receive Interrupt is disabled.
13
0b
RW
Fatal Bus Error Enable (FBE): When this bit is set with Abnormal Interrupt Summary
Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal
Bus Error Enable Interrupt is disabled.
12:11
00b
RO
Reserved (RSV0): Reserved.
10
0b
RW
Early Transmit Interrupt Enable (ETE): When this bit is set with an Abnormal
Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this
bit is reset, the Early Transmit Interrupt is disabled.
9
0b
RW
Receive Watchdog Timeout Enable (RWE): When this bit is set with Abnormal
Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled.
When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled.
8
0b
RW
Receive Stopped Enable (RSE): When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is
reset, the Receive Stopped Interrupt is disabled.
16
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Bit
Range
Default &
Access
Field Name (ID): Description
7
0b
RW
Receive Buffer Unavailable Enable (RUE): When this bit is set with Abnormal
Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled.
When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled.
6
0b
RW
Receive Interrupt Enable (RIE): When this bit is set with Normal Interrupt Summary
Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive
Interrupt is disabled.
5
0b
RW
Underflow Interrupt Enable (UNE): When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is
reset, the Underflow Interrupt is disabled.
4
0b
RW
Overflow Interrupt Enable (OVE): When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is
reset, the Overflow Interrupt is disabled.
3
0b
RW
Transmit Jabber Timeout Enable (TJE): When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this
bit is reset, the Transmit Jabber Timeout Interrupt is disabled.
2
0b
RW
Transmit Buffer Unavailable Enable (TUE): When this bit is set with Normal
Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is
enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled.
1
0b
RW
Transmit Stopped Enable (TSE): When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit
is reset, the Transmission Stopped Interrupt is disabled.
0
0b
RW
Transmit Interrupt Enable (TIE): When this bit is set with Normal Interrupt
Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the
Transmit Interrupt is disabled.
15.6.123 Missed Frame and Buffer Overflow Counter Register (Register
8) (DMA_REG_8)—Offset 1020h
The DMA maintains two counters to track the number of frames missed during
reception.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1020h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
0
0
0
OVFCNTOVF
0
Bit
Range
31:29
28
0
20
0
0
Default &
Access
000b
RO
0b
RO
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0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
MISFRMCNT
0
24
MISCNTOVF
0
RSV0
0
28
OVFFRMCNT
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
FIFO Overflow Counter Overflow (OVFCNTOVF): Reserved.
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Bit
Range
Default &
Access
FIFO Overflow Counter (OVFFRMCNT): This field indicates the number of frames
missed by the application due to buffer overflow conditions and runt frames (good
frames of less than 64 bytes) dropped by the MTL. The counter is cleared when this
register is read with the LS Byte enabled.
000h
RO
27:17
0b
RO
16
Missed Frame Counter Overflow (MISCNTOVF): Reserved.
Missed Frame Counter (MISFRMCNT): This field indicates the number of frames
missed by the controller because of the Host Receive Buffer being unavailable. This
counter is incremented each time the DMA discards an incoming frame. The counter is
cleared when this register is read with the LS Byte enabled.
0000h
RO
15:0
Field Name (ID): Description
15.6.124 Receive Interrupt Watchdog Timer Register (Register 9)
(DMA_REG_9)—Offset 1024h
This register, when written with non-zero value, enables the watchdog timer for the
Receive Interrupt (Bit 6) of Register 5 (Status Register).
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1024h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
31:8
7:0
Default &
Access
000000h
RO
00h
RW
4
0
0
0
0
0
0
0
0
0
RIWT
RSV0
0
28
Field Name (ID): Description
Reserved (RSV0): Reserved.
RI Watchdog Timer Count (RIWT): This bit indicates the number of system clock
cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets
triggered with the programmed value after the Rx DMA completes the transfer of a
frame for which the RI status bit is not set because of the setting in the corresponding
descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the
timer is stopped. The watchdog timer is reset when the RI bit is set high because of
automatic setting of RI as per RDES1[31] of any received frame.
15.6.125 AHB Status Register (Register 11) (DMA_REG_11)—Offset
102Ch
This register provides the active status of the AHB master interface interface's read and
write channels. This register is useful for debugging purposes.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 102Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
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Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:1
0
AXWHSTS
RSV0
0
Field Name (ID): Description
00000000h
Reserved (RSV0): Reserved.
RO
0b
RO
0
AHB Master Status (AXWHSTS): This bit indicates that the AHB master interface
FSMs are in the non-idle state.
15.6.126 Current Host Transmit Descriptor Register (Register 18)
(DMA_REG_18)—Offset 1048h
The Current Host Transmit Descriptor register points to the start address of the current
Transmit Descriptor read by the DMA.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1048h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CURTDESAPTR
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h Host Transmit Descriptor Address Pointer (CURTDESAPTR): Cleared on Reset.
Pointer updated by the DMA during operation.
RO
15.6.127 Current Host Receive Descriptor Register (Register 19)
(DMA_REG_19)—Offset 104Ch
The Current Host Receive Descriptor register points to the start address of the current
Receive Descriptor read by the DMA.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 104Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
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Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CURRDESAPTR
0
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h Host Receive Descriptor Address Pointer (CURRDESAPTR): Cleared on Reset.
Pointer updated by the DMA during operation.
RO
15.6.128 Current Host Transmit Buffer Address Register (Register 20)
(DMA_REG_20)—Offset 1050h
The Current Host Transmit Buffer Address register points to the current Transmit Buffer
Address being read by the DMA.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1050h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CURTBUFAPTR
0
28
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h Host Transmit Buffer Address Pointer (CURTBUFAPTR): Cleared on Reset. Pointer
updated by the DMA during operation.
RO
15.6.129 Current Host Receive Buffer Address Register (Register 21)
(DMA_REG_21)—Offset 1054h
The Current Host Receive Buffer Address register points to the current Receive Buffer
address being read by the DMA.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1054h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
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Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
12
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
CURRBUFAPTR
0
Bit
Range
31:0
Default &
Access
Field Name (ID): Description
00000000h Host Receive Buffer Address Pointer (CURRBUFAPTR): Cleared on Reset. Pointer
updated by the DMA during operation.
RO
15.6.130 HW Feature Register (Register 22) (DMA_REG_22)—Offset
1058h
This register indicates the presence of the optional features or functions of the MAC.
Set field indicates the feature is supported. The software driver can use this register to
dynamically enable or disable the programs related to the optional blocks.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1058h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:6] + 10h
Default: 4B0F3915h
Bit
Range
31
30:28
27
Default &
Access
0b
RO
100b
RO
1b
RO
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0
1
0
1
0
1
MIISEL
0
0
GMIISEL
0
HDSEL
1
HASHSEL
0
EXTHASHEN
4
0
PCSSEL
1
ADDMACADRSEL
1
SMASEL
1
L3L4FLTREN
8
0
MGKSEL
0
RWKSEL
12
1
MMCSEL
1
TSVER1SEL
1
EEESEL
16
1
TSVER2SEL
0
AVSEL
0
TXCOESEL
0
RXTYP1COE
20
0
RXTYP2COE
1
RXCHCNT
1
TXCHCNT
0
RXFIFOSIZE
24
1
ENHDESSEL
0
INTTSEN
ACTPHYIF
0
SAVLANINS
28
1
RSV0
0
FLEXIPPSEN
31
Field Name (ID): Description
Reserved (RSV0): Reserved.
Active or Selected PHY interface (ACTPHYIF): This field indicates the supported
PHY interface:
0000: GMII or MII
0001: RGMII
0010: SGMII
0011: TBI
0100: RMII
0101: RTBI
0110: SMII
0111: RevMII
All Others: Reserved
Source Address or VLAN Insertion (SAVLANINS): Reserved.
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Bit
Range
Default &
Access
Field Name (ID): Description
26
0b
RO
Flexible Pulse-Per-Second Output (FLEXIPPSEN): Reserved.
25
1b
RO
Timestamping with Internal System Time (INTTSEN): Reserved.
24
1b
RO
Alternate (Enhanced Descriptor) (ENHDESSEL): Reserved.
23:22
00b
RO
Number of additional Tx channels (TXCHCNT): Reserved.
21:20
00b
RO
Number of additional Rx channels (RXCHCNT): Reserved.
19
1b
RO
Rx FIFO > 2,048 Bytes (RXFIFOSIZE): Reserved.
18
1b
RO
IP Checksum Offload (Type 2) in Rx (RXTYP2COE): Reserved.
17
1b
RO
IP Checksum Offload (Type 1) in Rx (RXTYP1COE): Reserved.
16
1b
RO
Checksum Offload in Tx (TXCOESEL): Reserved.
15
0b
RO
AV Feature (AVSEL): Reserved.
14
0b
RO
Energy Efficient Ethernet (EEESEL): Reserved.
13
1b
RO
IEEE 1588-2008 Advanced Timestamp (TSVER2SEL): Reserved.
12
1b
RO
Only IEEE 1588-2002 Timestamp (TSVER1SEL): Reserved.
11
1b
RO
RMON Module (MMCSEL): Reserved.
10
0b
RO
PMT Magic Packet (MGKSEL): Reserved.
9
0b
RO
PMT Remote Wakeup (RWKSEL): Reserved.
8
1b
RO
SMA (MDIO) Interface (SMASEL): Reserved.
7
0b
RO
L3L4FLTREN: Reserved.
6
0b
RO
PCS registers (PCSSEL): Reserved.
5
0b
RO
Multiple MAC Address Registers (ADDMACADRSEL): Reserved.
4
1b
RO
HASH Filter (HASHSEL): Reserved.
3
0b
RO
Expanded DA Hash Filter (EXTHASHEN): Reserved.
2
1b
RO
Half-Duplex support (HDSEL): Reserved.
1
0b
RO
1000 Mbps Support (GMIISEL): Reserved.
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Bit
Range
Default &
Access
0
15.7
1b
RO
Field Name (ID): Description
10 and 100 Mbps Support (MIISEL): Reserved.
MAC Descriptor Details
This section provides bit-field definitions of the current transmit and receive descriptor
registers described in Section 15.6, specifically:
• Current Host Transmit Descriptor Register (Register 18) (DMA_REG_18)—Offset
1048h
• Current Host Receive Descriptor Register (Register 19) (DMA_REG_19)—Offset
104Chh
15.7.1
Descriptor Overview
The descriptor structure has 8 DWORDS (32-bytes). The features of the descriptor
structure are:
• The descriptor structure is implemented to support buffers of up to 8 KB (useful for
Jumbo frames).
• There is a re-assignment of control and status bits in TDES0, TDES1, RDES0
(Advanced timestamp or IPC full offload configuration), and RDES1.
• The transmit descriptor stores the timestamp in TDES6 and TDES7.
• This receive descriptor structure is also used for storing the extended status
(RDES4) and timestamp (RDES6 and RDES7).
• You can select one of the following options for descriptor structure:
— If timestamping is enabled in Register 448 (Timestamp Control Register) or
Checksum Offload is enabled in Register 0 (MAC Configuration Register), the
software needs to allocate 32-bytes (8 DWORDS) of memory for every
descriptor. For this, the software should set Bit 7 (Alternate Descriptor Size) of
Register 0 (Bus Mode Register).
— If timestamping or Checksum Offload is not enabled, the extended descriptors
(DES4 to DES7) are not required. Therefore, the software can use alternate
descriptors with the default size of 16 bytes.
15.7.2
Descriptor Endianness
The descriptor addresses must be aligned to the bus width (Word, DWord, or LWord for
32-bit bus). The data bus is configured for little-endian format.
The structure of the descriptor with respect to the data bus endianness is as follows:
• Data Bus Endianness: Little-endian
• Descriptor Endianness: Same-endian
• Data Bus: 32-bit data bus
15.7.3
Transmit Descriptor
The transmit descriptor structure is shown in Figure 29. The application software must
program the control bits TDES0[31:18] during descriptor initialization. When the DMA
updates the descriptor, it writes back all the control bits except the OWN bit (which it
clears) and updates the status bits[7:0]. The contents of the transmitter descriptor
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word 0 (TDES0) through word 3 (TDES3) are given in Table 89 through Table 91,
respectively.
The snapshot of the timestamp to be taken can be enabled for a given frame by setting
Bit 25 (TTSE) of TDES0. When the descriptor is closed (that is, when the OWN bit is
cleared), the timestamp is written into TDES6 and TDES7. This is indicated by the
status Bit 17 (TTSS) of TDES0 shown in Figure 29. The contents of TDES6 and TDES7
are mentioned in Table 93 and Table 94.
Figure 29.
Transmit Descriptor Fields
The DMA always reads or fetches four DWORDS of the descriptor from system memory
to obtain the buffer and control information as shown in Figure 30. When the AV
feature is enabled, TDES0 has additional control bits[6:3] for Channel 1 and Channel 2.
For Channel 0, Bits [6:3] are ignored. Bits [6:3] are described in Table 89.
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Figure 30.
Transmit Descriptor Fetch (Read)
Table 89.
Transmit Descriptor Word 0 (TDES0) (Sheet 1 of 3)
Bit
Description
31
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it
indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes
the frame transmission or when the buffers allocated in the descriptor are read completely. The
ownership bit of the frame’s first descriptor must be set after all subsequent descriptors belonging
to the same frame have been set. This avoids a possible race condition between fetching a
descriptor and the driver setting an ownership bit.
30
IC: Interrupt on Completion
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present frame has been
transmitted.
29
LS: Last Segment
When set, this bit indicates that the buffer contains the last segment of the frame. When this bit is
set, the TBS1 or TBS2 field in TDES1 should have a non-zero value.
28
FS: First Segment
When set, this bit indicates that the buffer contains the first segment of a frame.
27
DC: Disable CRC
When this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end of the
transmitted frame. This is valid only when the first segment (TDES0[28]) is set.
26
DP: Disable Pad
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this
bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the
CRC field is added despite the state of the DC (TDES0[27]) bit. This is valid only when the first
segment (TDES0[28]) is set.
25
TTSE: Transmit Timestamp Enable
When set, this bit enables IEEE1588 hardware timestamping for the transmit frame referenced by
the descriptor. This field is valid only when the Enable IEEE1588 Timestamping option is selected
during core configuration and the First Segment control bit (TDES0[28]) is set.
24
CRCR: CRC Replacement Control
When set, the MAC replaces the last four bytes of the transmitted packet with recalculated CRC
bytes. The host should ensure that the CRC bytes are present in the frame being transferred from
the Transmit Buffer. This bit is valid when the Enable SA, VLAN, and CRC Insertion on TX option is
selected during core configuration and the First Segment control bit (TDES0[28]) is set.
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Table 89.
Transmit Descriptor Word 0 (TDES0) (Sheet 2 of 3)
Bit
Description
23:22
CIC: Checksum Insertion Control
These bits control the checksum calculation and insertion. The following list describes the bit
encoding:
• 2’b00: Checksum Insertion Disabled.
• 2’b01: Only IP header checksum calculation and insertion are enabled.
• 2’b10: IP header checksum and payload checksum calculation and insertion are enabled, but
pseudo-header checksum is not calculated in hardware.
• 2’b11: IP Header checksum and payload checksum calculation and insertion are enabled, and
pseudo-header checksum is calculated in hardware.
This field is valid when the Enable Transmit Full TCP/IP Checksum (Type 2) option is selected during
core configuration and the First Segment control bit (TDES0[28]) is set.
21
TER: Transmit End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to
the base address of the list, creating a descriptor ring.
20
TCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address
rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t
care” value. TDES0[21] takes precedence over TDES0[20].
19:18
VLIC: VLAN Insertion Control When set, these bits request the MAC to perform VLAN tagging or
untagging before transmitting the frames. If the frame is modified for VLAN tags, the MAC
automatically recalculates and replaces the CRC bytes.
The following list describes the values of these bits:
• 2'b00: Do not add a VLAN tag.
• 2'b01: Remove the VLAN tag from the frames before transmission. This option should be used
only with the VLAN frames.
• 2'b10: Insert a VLAN tag with the tag value programmed in Register 353 (VLAN Tag Inclusion or
Replacement Register).
• 2'b11: Replace the VLAN tag in frames with the Tag value programmed in Register 353 (VLAN
Tag Inclusion or Replacement Register). This option should be used only with the VLAN frames.
These bits are valid when the Enable SA, VLAN, and CRC Insertion on TX option is selected during
core configuration and the First Segment control bit (TDES0[28]) is set.
17
TTSS: Transmit Timestamp Status
This field is used as a status bit to indicate that a timestamp was captured for the described transmit
frame. When this bit is set, TDES2 and TDES3 have a timestamp value captured for the transmit
frame. This field is only valid when the descriptor’s Last Segment control bit (TDES0[29]) is set.
16
IHE: IP Header Error
When set, this bit indicates that the MAC transmitter detected an error in the IP datagram header.
The transmitter checks the header length in the IPv4 packet against the number of header bytes
received from the application and indicates an error status if there is a mismatch. For IPv6 frames,
a header error is reported if the main header length is not 40 bytes. Furthermore, the Ethernet
Length/Type field value for an IPv4 or IPv6 frame must match the IP header version received with
the packet. For IPv4 frames, an error status is also indicated if the Header Length field has a value
less than 0x5.
15
ES: Error Summary
Indicates the logical OR of the following bits:
• TDES0[14]: Jabber Timeout
• TDES0[13]: Frame Flush
• TDES0[11]: Loss of Carrier
• TDES0[10]: No Carrier
• TDES0[9]: Late Collision
• TDES0[8]: Excessive Collision
• TDES0[2]: Excessive Deferral
• TDES0[1]: Underflow Error
• TDES0[16]: IP Header Error
• TDES0[12]: IP Payload Error
14
JT: Jabber Timeout
When set, this bit indicates the MAC transmitter has experienced a jabber time-out. This bit is only
set when Bit 22 (Jabber Disable) of Register 0 (MAC Configuration Register) is not set.
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Table 89.
Transmit Descriptor Word 0 (TDES0) (Sheet 3 of 3)
Bit
Description
13
FF: Frame Flushed
When set, this bit indicates that the DMA or MTL flushed the frame because of a software Flush
command given by the CPU.
12
IPE: IP Payload Error
When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP
datagram payload.
The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual
number of TCP, UDP, or ICMP packet bytes received from the application and issues an error status
in case of a mismatch.
11
LC: Loss of Carrier
When set, this bit indicates that a loss of carrier occurred during frame transmission (that is, the
gmii_crs_i signal was inactive for one or more transmit clock periods during frame transmission).
This is valid only for the frames transmitted without collision when the MAC operates in the halfduplex mode.
10
NC: No Carrier
When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during
transmission.
9
LC: Late Collision
When set, this bit indicates that frame transmission is aborted because of a collision occurring after
the collision window (64 byte-times, including preamble, in MII mode and 512 byte-times, including
preamble and carrier extension, in GMII mode). This bit is not valid if the Underflow Error bit is set.
8
EC: Excessive Collision
When set, this bit indicates that the transmission was aborted after 16 successive collisions while
attempting to transmit the current frame. If Bit 9 (Disable Retry) bit in the Register 0 (MAC
Configuration Register) is set, this bit is set after the first collision, and the transmission of the
frame is aborted.
7
VF: VLAN Frame
When set, this bit indicates that the transmitted frame is a VLAN-type frame.
6:3
CC: Collision Count (Status field)
These status bits indicate the number of collisions that occurred before the frame was transmitted.
This count is not valid when the Excessive Collisions bit (TDES0[8]) is set. The core updates this
status field only in the half-duplex mode.
-orSLOTNUM: Slot Number Control Bits in AV Mode
These bits indicate the slot interval in which the data should be fetched from the corresponding
buffers addressed by TDES2 or TDES3.
When the transmit descriptor is fetched, the DMA compares the slot number value in this field with
the slot interval maintained in the core (Register 11xx). It fetches the data from the buffers only if
there is a match in values. These bits are valid only for AV channels (not Channel 0).
2
ED: Excessive Deferral
When set, this bit indicates that the transmission has ended because of excessive deferral of over
24,288 bit times (155,680 bits times in 1,000-Mbps mode or if Jumbo Frame is enabled) if Bit 4
(Deferral Check) bit in Register 0 (MAC Configuration Register) is set high.
1
UF: Underflow Error
When set, this bit indicates that the MAC aborted the frame because the data arrived late from the
Host memory. Underflow Error indicates that the DMA encountered an empty transmit buffer while
transmitting the frame. The transmission process enters the Suspended state and sets both
Transmit Underflow (Register 5[5]) and Transmit Interrupt (Register 5[0]).
0
DB: Deferred Bit
When set, this bit indicates that the MAC defers before transmission because of the presence of
carrier. This bit is valid only in the half-duplex mode.
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Table 90.
Transmit Descriptor Word 1 (TDES1)
Bit
Description
31:29
SAIC: SA Insertion Control
These bits request the MAC to add or replace the Source Address field in the Ethernet frame with
the value given in the MAC Address 0 register. If the Source Address field is modified in a frame, the
MAC automatically recalculates and replaces the CRC bytes.
The Bit 31 specifies the MAC Address Register (1 or 0) value that is used for Source Address
insertion or replacement. The following list describes the values of Bits[30:29]:
• 2'b00: Do not include the source address.
• 2'b01: Include or insert the source address. For reliable transmission, the application must
provide frames without source addresses.
• 2'b10: Replace the source address. For reliable transmission, the application must provide
frames with source addresses.
• 2'b11: Reserved
These bits are valid in the GMAC-DMA, GMAC-AXI, and GMAC-AHB configurations when the Enable
SA, VLAN, and CRC Insertion on TX is selected during core configuration and when the First
Segment control bit (TDES0[28]) is set.
28:16
TBS2: Transmit Buffer 2 Size
This field indicates the second data buffer size in bytes. This field is not valid if TDES0[20] is set.
15:13
12:0
Table 91.
Reserved
TBS1: Transmit Buffer 1 Size
These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this
buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).
Transmit Descriptor 2 (TDES2)
Bit
31:0
Table 92.
Description
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address
alignment.
Transmit Descriptor 3 (TDES3)
Bit
31:0
Table 93.
Description
Buffer 2 Address Pointer (Next Descriptor Address)
Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second
Address Chained (TDES1[24]) bit is set, this address contains the pointer to the physical memory
where the Next Descriptor is present. The buffer address pointer must be aligned to the bus width
only when TDES1[24] is set. (LSBs are ignored internally.)
Transmit Descriptor 6 (TDES6)
Bit
Description
31:0
TTSL: Transmit Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the timestamp captured for the
corresponding transmit frame. This field has the timestamp only if the Last Segment bit (LS) in the
descriptor is set and Timestamp status (TTSS) bit is set.
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Table 94.
Transmit Descriptor 7 (TDES7)
Bit
31:0
15.7.4
Description
TTSH: Transmit Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for the
corresponding receive frame. This field has the timestamp only if the Last Segment bit (LS) in the
descriptor is set and Timestamp status (TTSS) bit is set.
Receive Descriptor
The structure of the received descriptor is shown in Figure 31. It has 32 bytes of
descriptor data (8 DWORDs).
Figure 31.
Receive Descriptor Fields
The contents of RDES0 are identified in Table 95. The contents of RDES1 through
RDES3 are identified in Table 96 through Table 98, respectively.
Note:
Some of the bit functions of RDES0 are not backward compatible to Release 3.41a and
previous versions. These bits are Bit 7, Bit 0, and Bit 5. The function of Bit 5 is
backward compatible to Release 3.30a and previous versions.
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Table 95.
Receive Descriptor Fields (RDES0) (Sheet 1 of 2)
Bit
Description
31
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA of the DWC_gmac. When this
bit is reset, this bit indicates that the descriptor is owned by the Host. The DMA clears this bit either
when it completes the frame reception or when the buffers that are associated with this descriptor
are full.
30
AFM: Destination Address Filter Fail
When set, this bit indicates a frame that failed in the DA Filter in the MAC.
29:16
FL: Frame Length
These bits indicate the byte length of the received frame that was transferred to host memory
(including CRC). This field is valid when Last Descriptor (RDES0[8]) is set and either the Descriptor
Error (RDES0[14]) or Overflow Error bits are reset. The frame length also includes the two bytes
appended to the Ethernet frame when IP checksum calculation (Type 1) is enabled and the received
frame is not a MAC control frame.
This field is valid when Last Descriptor (RDES0[8]) is set. When the Last Descriptor and Error
Summary bits are not set, this field indicates the accumulated number of bytes that have been
transferred for the current frame.
15
ES: Error Summary
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header or Payload Error
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
14
DE: Descriptor Error
When set, this bit indicates a frame truncation caused by a frame that does not fit within the current
descriptor buffers, and that the DMA does not own the Next Descriptor. The frame is truncated. This
field is valid only when the Last Descriptor (RDES0[8]) is set.
13
SAF: Source Address Filter Fail
When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC.
12
LE: Length Error
When set, this bit indicates that the actual length of the frame received and that the Length/ Type
field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset.
11
OE: Overflow Error
When set, this bit indicates that the received frame was damaged because of buffer overflow in
MTL. Note: This bit is set only when the DMA transfers a partial frame to the application. This
happens only when the Rx FIFO is operating in the threshold mode. In the store-and-forward mode,
all partial frames are dropped completely in Rx FIFO.
10
VLAN: VLAN Tag
When set, this bit indicates that the frame to which this descriptor is pointing is a VLAN frame
tagged by the MAC. The VLAN tagging depends on checking the VLAN fields of received frame based
on the VLAN Tag Register (Register 7) (GMAC_REG_7)—Offset 1Ch setting.
9
FS: First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of
the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second
buffer is also 0, the next Descriptor contains the beginning of the frame.
8
LS: Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the
frame.
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Table 95.
Table 96.
Receive Descriptor Fields (RDES0) (Sheet 2 of 2)
Bit
Description
7
Timestamp Available, IP Checksum Error (Type1), or Giant Frame
When Advanced Timestamp feature is present, when set, this bit indicates that a snapshot of the
Timestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last
Descriptor bit (RDES0[8]) is set.
When IP Checksum Engine (Type 1) is selected, this bit, when set, indicates that the 16-bit IPv4
Header checksum calculated by the core did not match the received checksum bytes.
Otherwise, this bit, when set, indicates the Giant Frame Status. Giant frames are larger than 1,518byte (or 1,522-byte for VLAN or 2,000-byte when Bit 27 (2KPE) of MAC Configuration register is
set) normal frames and larger than 9,018-byte (9,022-byte for VLAN) frame when Jumbo Frame
processing is enabled.
6
LC: Late Collision
When set, this bit indicates that a late collision has occurred while receiving the frame in the halfduplex mode.
5
FT: Frame Type
When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is greater
than or equal to 16’h0600). When this bit is reset, it indicates that the received frame is an
IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes.
4
RWT: Receive Watchdog Timeout
When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current
frame and the current frame is truncated after the Watchdog Timeout.
3
RE: Receive Error
When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_i is asserted
during frame reception. This error also includes carrier extension error in the GMII and half-duplex
mode. Error can be of less or no extension, or error (rxd ≠ 0f) during extension.
2
DE: Dribble Bit Error
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd
nibbles). This bit is valid only in the MII Mode.
1
CE: CRC Error
When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received
frame. This field is valid only when the Last Descriptor (RDES0[8]) is set.
0
Extended Status Available/Rx MAC Address
When either Advanced Timestamp or IP Checksum Offload (Type 2) is present, this bit, when set,
indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only when
the Last Descriptor bit (RDES0[8]) is set.
When Advance Timestamp Feature or IPC Full Offload is not selected, this bit indicates Rx MAC
Address status. When set, this bit indicates that the Rx MAC Address registers value (1 to 15)
matched the frame’s DA field. When reset, this bit indicates that the Rx MAC Address Register 0
value matched the DA field.
Receive Descriptor Fields 1 (RDES1) (Sheet 1 of 2)
Bit
Description
31
DIC: Disable Interrupt on Completion
When set, this bit prevents setting the Status Register’s RI bit (CSR5[6]) for the received frame
ending in the buffer indicated by this descriptor. This, in turn, disables the assertion of the interrupt
to Host because of RI for that frame.
30:29
Reserved
28:16
RBS2: Receive Buffer 2 Size
These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, 8,
or 16, depending on the bus widths (32, 64, or 128, respectively), even if the value of RDES3
(buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple
of 4, 8, or 16, the resulting behavior is undefined. This field is not valid if RDES1[14] is set.
15
RER: Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to
the base address of the list, creating a descriptor ring.
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Table 96.
Receive Descriptor Fields 1 (RDES1) (Sheet 2 of 2)
Bit
Description
14
RCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address
rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t care”
value. RDES1[15] takes precedence over RDES1[14].
13
12:0
Table 97.
Table 98.
Reserved
RBS1: Receive Buffer 1 Size
Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8, or 16,
depending upon the bus widths (32, 64, or 128), even if the value of RDES2 (buffer1 address
pointer) is not aligned. When the buffer size is not a multiple of 4, 8, or 16, the resulting behavior is
undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor
depending on the value of RCH (Bit 14).
Receive Descriptor Fields 2 (RDES2)
Bit
Description
31:0
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There are no limitations on the buffer address
alignment except for the following condition: The DMA uses the configured value for its address
generation when the RDES2 value is used to store the start of frame. The DMA performs a write
operation with the RDES2[3:0, 2:0, or 1:0] bits as 0 during the transfer of the start of frame but the
frame data is shifted as per the actual Buffer address pointer. The DMA ignores RDES2[3:0, 2:0, or
1:0] (corresponding to bus width of 128, 64, or 32) if the address pointer is to a buffer where the
middle or last part of the frame is stored.
Receive Descriptor Fields 3 (RDES3)
Bit
Description
31:0
Buffer 2 Address Pointer (Next Descriptor Address)
These bits indicate the physical address of Buffer 2 when a descriptor ring structure is used. If the
Second Address Chained (RDES1[24]) bit is set, this address contains the pointer to the physical
memory where the Next Descriptor is present.
If RDES1[24] is set, the buffer (Next Descriptor) address pointer must be bus width-aligned
(RDES3[3, 2, or 1:0] = 0, corresponding to a bus width of 128, 64, or 32. LSBs are ignored
internally.) However, when RDES1[24] is reset, there are no limitations on the RDES3 value, except
for the following condition: The DMA uses the configured value for its buffer address generation
when the RDES3 value is used to store the start of frame. The DMA ignores RDES3 [3, 2, or 1:0]
(corresponding to a bus width of 128, 64, or 32) if the address pointer is to a buffer where the
middle or last part of the frame is stored.
The status written is as shown in Table 99. The status is written only when there is
status related to IPC or timestamp available. The availability of extended status is
indicated by Bit 0 of RDES0. This status is available only when the Advance Timestamp
or IPC Full Offload feature is selected.
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Table 99.
Receive Descriptor Fields 4 (RDES4) (Sheet 1 of 2)
Bit
Description
31:28
Reserved
27:26
Layer 3 and Layer 4 Filter Number Matched
These bits indicate the number of the Layer 3 and Layer 4 Filter that matched the received frame.
• 00: Filter 0
• 01: Filter 1
• 10: Filter 2
• 11: Filter 3
This field is valid only when Bit 24 or Bit 25 is set high. When more than one filter matches, these
bits give only the lowest filter number.
25
Layer 4 Filter Match
When set, this bit indicates that the received frame matches one of the enabled Layer 4 Port
Number fields. This status is given only when one of the following conditions is true:
• Layer 3 fields are not enabled and all enabled Layer 4 fields match.
• All enabled Layer 3 and Layer 4 filter fields match.
When more than one filter matches, this bit gives the layer 4 filter status of filter indicated by Bits
[27:26].
24
Layer 3 Filter Match
When set, this bit indicates that the received frame matches one of the enabled Layer 3 IP Address
fields.
This status is given only when one of the following conditions is true:
• All enabled Layer 3 fields match and all enabled Layer 4 fields are bypassed.
• All enabled filter fields match.
When more than one filter matches, this bit gives the layer 3 filter status of filter indicated by Bits
[27:26].
23:21
Reserved
20:18
VLAN Tag Priority Value
These bits give the VLAN tag’s user value in the received packet. These bits are valid only when the
RDES4 Bits 16 and 17 are set.
These bits are available only when you select the AV feature.
17
AV Tagged Packet Received
When set, this bit indicates that an AV tagged packet is received. Otherwise, this bit indicates that
an untagged AV packet is received. This bit is valid when Bit 16 is set.
This bit is available only when you select the AV feature.
16
AV Packet Received
When set, this bit indicates that an AV packet is received. This bit is available only when you select
the AV feature.
15
Reserved
14
Timestamp Dropped
When set, this bit indicates that the timestamp was captured for this frame but got dropped in the
MTL Rx FIFO because of overflow. This bit is available only when you select the Advanced
Timestamp feature. Otherwise, this bit is reserved.
13
PTP Version
When set, this bit indicates that the received PTP message is having the IEEE 1588 version 2
format. When reset, it has the version 1 format. This bit is available only when you select the
Advanced Timestamp feature. Otherwise, this bit is reserved.
12
PTP Frame Type
When set, this bit indicates that the PTP message is sent directly over Ethernet. When this bit is not
set and the message type is non-zero, it indicates that the PTP message is sent over UDP-IPv4 or
UDP-IPv6. The information about IPv4 or IPv6 can be obtained from Bits 6 and 7.
This bit is available only when you select the Advanced Timestamp feature.
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Table 99.
Receive Descriptor Fields 4 (RDES4) (Sheet 2 of 2)
Bit
11:8
Description
Message Type
These bits are encoded to give the type of the message received.
• 0000: No PTP message received
• 0001: SYNC (all clock types)
• 0010: Follow_Up (all clock types)
• 0011: Delay_Req (all clock types)
• 0100: Delay_Resp (all clock types)
• 0101: Pdelay_Req (in peer-to-peer transparent clock)
• 0110: Pdelay_Resp (in peer-to-peer transparent clock)
• 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)
• 1000: Announce • 1001: Management
• 1010: Signaling • 1011-1110: Reserved
• 1111: PTP packet with Reserved message type
These bits are available only when you select the Advance Timestamp feature.
Note: Values 1000, 1001, and 1010 are not backward compatible with release 3.50a.
7
IPv6 Packet Received
When set, this bit indicates that the received packet is an IPv6 packet. This bit is updated only when
Bit 10 (IPC) of MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h) is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
6
IPv4 Packet Received
When set, this bit indicates that the received packet is an IPv4 packet. This bit is updated only when
Bit 10 (IPC) of MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h) is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
5
IP Checksum Bypassed
When set, this bit indicates that the checksum offload engine is bypassed. This bit is available when
you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
4
IP Payload Error
When set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP
checksum) that the core calculated does not match the corresponding checksum field in the
received segment. It is also set when the TCP, UDP, or ICMP segment length does not match the
payload length value in the IP Header field. This bit is valid when either Bit 7 or Bit 6 is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
3
IP Header Error
When set, this bit indicates that either the 16-bit IPv4 header checksum calculated by the core does
not match the received checksum bytes, or the IP datagram version is not consistent with the
Ethernet Type value. This bit is valid when either Bit 7 or Bit 6 is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
2:0
IP Payload Type
These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive
Checksum Offload Engine (COE). The COE also sets these bits to 2'b00 if it does not process the IP
datagram’s payload due to an IP header error or fragmented IP.
• 3'b000: Unknown or did not process IP payload
• 3'b001: UDP
• 3'b010: TCP
• 3'b011: ICMP
• 3’b1xx: Reserved
This bit is valid when either Bit 7 or Bit 6 is set. This bit is available when you select the Enable
Receive Full TCP/IP Checksum (Type 2) feature.
RDES6 and RDES7 contain the snapshot of the timestamp. The availability of the
snapshot of the timestamp in RDES6 and RDES7 is indicated by Bit 7 in the RDES0
descriptor. The contents of RDES6 and RDES7 are identified in Table 100 and Table 101,
respectively.
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Table 100.
Table 101.
Receive Descriptor Fields 6 (RDES6)
Bit
Description
31:0
RTSL: Receive Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the timestamp captured for the
corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive
frame which is indicated by Last Descriptor status bit (RDES0[8]).
Receive Descriptor Fields 7 (RDES7)
Bit
Description
31:0
RTSH: Receive Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for the
corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive
frame which is indicated by Last Descriptor status bit (RDES0[8]).
§§
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USB 2.0—Intel® Quark™ SoC X1000
16.0
USB 2.0
The Intel® Quark™ SoC X1000 USB subsystem provides a two-port USB 2.0 Host
Controller and one USB 2.0 Device port.
16.1
Signal Descriptions
See Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 102.
Signals
Signal Name
USBH[0/1]_DP
USBH[0/1]_DN
Direction/
Type
I/O
Description
Universal Serial Bus Host Port 0 and Port 1. Differentials: Bus Data/
Address/Command Bus
USBH0_OC_B
USBH1_OC_B
I
Over current Indicators: These signals set corresponding bits in the USB
controller to indicate that an over current condition has occurred.
Overcurrent indicators are provided for both Host ports.
USBH0_PWR_EN
USBH1_PWR_EN
O
Power Enable signal to the USB host port
USBD_DP
USBD_DN
I/O
Universal Serial Bus Device Port. Differentials: Bus Data/ Address/
Command Bus
OUSBCOMP
O
RCOMP OUT. Note: Please check the Platform Design Guide for connection
details for this COMP pin.
IUSBCOMP
I
RCOMP IN. Note: Please check the Platform Design Guide for connection
details for this COMP pin.
16.2
Features
16.2.1
USB2.0 Host Controller Features
• 2-Port USB 2.0 Host Controller compatible with the following standards:
— Universal Serial Bus Specification (Revision 2.0, April 27, 2000)
— Enhanced Host Controller Interface Specification for Universal Serial Bus
(Revision1.0, March 12, 2002)
— EHCI 1.1 Addendum (Revision v0.6, October 2007)
— OpenHCI: Open Host Controller Interface Specification for USB (Release 1.0a,
September 14, 1999)
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Intel® Quark™ SoC X1000—USB 2.0
• EHCI features
Supported:
— 512-byte Packet Buffer depth for in/out data buffering
— Programmable Packet Buffer depth
— Extended capability pointer (EECP = 8’hC0)
— Programmable frame list flag
— 32-bit only addressing capability
— Per port power control
— PCI Power Management
Not supported:
— Descriptor/data prefetching
— Asynchronous schedule park capability
— HSIC functionality
— Link Power Management (LPM) ECN
• OHCI features
Supported:
— One OHCI companion controller
— Per port power control
Not supported:
— Keyboard/Mouse legacy interface
16.2.2
USB2.0 Device Features
• High-speed (480 Mbps) and full-speed (12 Mbps) operation
• 3 logical endpoints in addition to logical endpoint 0
• 1 configuration in addition to configuration 0
• Enables user-configurable endpoint information
• Multiple data packets for each OUT endpoint (Multiple Receive FIFO).
• Both DMA option and Slave-Only modes
• True scatter-gather DMA implementation
• Descriptor-based memory structures in application memory when in DMA mode
16.3
References
• USB 2.0 specification at http://www.usb.org/developers/docs
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16.4
Register Map
Figure 32.
USB Register Map
Memory Space
EHCI Host
PCI Header
D:20,F:3
PCI Space
CPU
Core
MBAR
Host Bridge
D:0,F:0
EHCI Host
Mem
Registers
PCI
CAM
(I/O)
Bus 0
PCIe*
D:23
SPI1 F:1
I2C*/GPIO F:2
IO Fabric
D:21
SPI0 F:0
Memory Space
OHCI Host
PCI Header
D:20,F:4
PCI
ECAM
(Mem)
RP0 F:0
MBAR
RP0 F:1
OHCI Host
Mem
Registers
Legacy Bridge
D:31, F:0
SDIO/eMMC F:0
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
Memory Space
USB Device
PCI Header
D:20,F:2
HSUART0 F:1
MBAR
MAC0 F:6
USB Device
Mem
Registers
MAC1 F:7
See Chapter 5.0, “Register Access Methods” for additional information.
16.5
PCI Configuration Registers
16.5.1
USB Device
Table 103.
Summary of PCI Configuration Registers—0/20/2
Offset Start
0h
Offset End
1h
Register ID—Description
“Vendor ID (VENDOR_ID)—Offset 0h” on page 438
Default
Value
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 439
0939h
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 439
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 440
0010h
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Intel® Quark™ SoC X1000—USB 2.0
Table 103.
Offset Start
Summary of PCI Configuration Registers—0/20/2 (Continued)
Offset End
Default
Value
Register ID—Description
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 440
0C03FE10h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 441
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 441
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 442
80h
Fh
Fh
“BIST (BIST)—Offset Fh” on page 442
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 443
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 443
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 444
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 444
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 444
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 445
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 445
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 446
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 446
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 446
00h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 447
01h
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 447
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 447
4803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 448
0008h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 449
00h
86h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 449
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 450
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 450
00h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 450
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 451
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 451
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 452
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 452
00000000h
16.5.1.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:2] + 0h
Default: 8086h
15
12
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
value
1
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Bit
Range
Default &
Access
8086h
RO
15: 0
16.5.1.2
Description
Vendor ID (value): PCI Vendor ID for Intel
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:2] + 2h
Default: 0939h
15
0
0
0
8
1
0
0
4
1
0
0
1
0
1
1
0
0
1
value
0
12
Bit
Range
Default &
Access
0939h
RO
15: 0
16.5.1.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:2] + 4h
Default: 0000h
0
0
0
0
0
0
0
0
0
RSVD
0
MEMen
0
0
MasEn
0
4
RSVD
0
SERREn
0
8
RSVD
0
RSVD0
0
12
IntrDis
15
Bit
Range
Default &
Access
15: 11
0h
RO
RSVD0 (RSVD0): Reserved
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
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Description
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
0h
RO
0
16.5.1.4
Description
Reserved (RSVD): Reserved.
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:2] + 6h
Default: 0010h
Bit
Range
16.5.1.5
Default &
Access
0
1
0
0
0
0
RSVD1
0
IntrStatus
0
0
hasCapList
0
capable_66Mhz
0
RSVD
0
FastB2B
0
4
RSVD
0
DEVSEL
0
8
RSVD
0
RcdMasAb
0
SigSysErr
12
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
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USB 2.0—Intel® Quark™ SoC X1000
Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:2] + 8h
Default: 0C03FE10h
0
1
1
0
0
0
0
0
16.5.1.6
0
16
0
0
1
1
12
1
1
1
1
8
1
1
1
0
4
0
0
0
1
0
0
0
0
0
rev_id
0
20
progIntf
0
24
classCode
0
28
subClassCode
31
Bit
Range
Default &
Access
31: 24
0Ch
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
03h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
FEh
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:2] + Ch
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.1.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:2] + Dh
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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Intel® Quark™ SoC X1000—USB 2.0
16.5.1.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
HEADER_TYPE: [B:0, D:20, F:2] + Eh
Default: 80h
7
4
0
0
0
Bit
Range
16.5.1.9
0
0
0
0
cfgHdrFormat
multiFnDev
1
0
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:2] + Fh
Default: 00h
7
4
0
0
Default &
Access
0
0
Description
7
0h
RO
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
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442
0
comp_code
BIST_capable
Bit
Range
0
RSVD
0
start_bist
0
0
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16.5.1.10
Bit
Range
Default &
Access
3: 0
0h
RO
Description
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
16.5.1.11
0
0
0
0
RSVD
0
4
0
0
0
0
0
isIO
0
20
memType
0
24
address
0
28
prefetchable
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:2] + 28h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
28
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Bit
Range
Default &
Access
0h
RO
31: 0
16.5.1.12
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:2] + 2Ch
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
12
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.1.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:2] + 2Eh
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
12
Bit
Range
15: 0
16.5.1.14
Default &
Access
0h
RO
Description
Subsystem ID (value): PCI Subsystem ID
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:2] + 30h
Default: 00000000h
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0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
16.5.1.15
0
0
0
0
0
0
0
RSVD
ROM_base_addr
0
28
0
AddrDecodeEn
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:2] + 34h
Default: 00000080h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
0
0
RSVD0
0
28
Bit
Range
16.5.1.16
0
0
0
0
0
0
value
31
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_LINE: [B:0, D:20, F:2] + 3Ch
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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16.5.1.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:2] + 3Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
7: 0
16.5.1.18
Default &
Access
Description
03h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:2] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.1.19
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MIN_GNT (value): Hardwired to 0
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:2] + 3Fh
Default: 00h
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USB 2.0—Intel® Quark™ SoC X1000
7
4
0
0
0
0
0
0
0
value
0
0
16.5.1.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:2] + 80h
Default: 01h
7
4
0
0
0
0
0
0
1
value
0
0
16.5.1.21
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:2] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
value
1
0
16.5.1.22
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
November 2014
Document Number: 329676-004US
PMC: [B:0, D:20, F:2] + 82h
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Intel® Quark™ SoC X1000—USB 2.0
Default: 4803h
16.5.1.23
0
4
0
0
0
0
0
0
0
1
1
version
0
PME_clock
0
RSVD
8
1
DSI
0
aux_curr
0
D1_support
12
1
PME_support
0
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
09h
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset 84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:2] + 84h
Default: 0008h
0
0
0
0
0
1
0
0
0
power_state
0
RSVD
0
0
no_soft_reset
0
RSVD
0
Data_select
0
4
Data_scale
0
8
PME_status
0
12
PME_en
15
Bit
Range
Default &
Access
Description
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
15
14: 13
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Datasheet
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Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.1.24
Default &
Access
Description
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:2] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.1.25
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset 87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:2] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
Default &
Access
7: 0
0h
RO
November 2014
Document Number: 329676-004US
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
Intel® Quark™ SoC X1000
Datasheet
449
Intel® Quark™ SoC X1000—USB 2.0
16.5.1.26
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:2] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
16.5.1.27
Bit
Range
Default &
Access
7: 0
05h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:2] + A1h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.1.28
Bit
Range
Default &
Access
Description
7: 0
00h
RO
Next Capability Pointer (value): Hardwired to 0 as this is the last capability structure
in the chain
Message Control (MESSAGE_CTRL)—Offset A2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_CTRL: [B:0, D:20, F:2] + A2h
Default: 0100h
Intel® Quark™ SoC X1000
Datasheet
450
0
0
1
0
0
0
0
0
0
0
0
MSIEnable
0
0
multiMsgCap
0
4
multiMsgEn
0
8
bit64Cap
0
RSVD0
0
12
perVecMskCap
15
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.1.29
Default &
Access
Description
15: 9
0h
RO
RSVD0 (RSVD0): Reserved
8
1h
RO
Per Vector Masking Capable (perVecMskCap): Hardwired to 1 to indicate the
function supports PVM
7
0h
RO
64 bit Address Capabale (bit64Cap): This bit is hardwired to 0 to indicate that the
function is not capable of sending a 64-bit message address.
6: 4
0h
RW
Multi-Message Enable (multiMsgEn): As only one vector is supported per function,
software should only write a value of 0x0 to this field
3: 1
0h
RO
Multiple Message Enable (multiMsgCap): This field is hardwired to 0x0 to indicate
that the function is requesting a single vector
0
0h
RW
MSI Enable (MSIEnable): Set to enable MSI to request service. If set then it's
prohibited to use the INTx pin. System configuration software sets this bit to enable
MSI.
Message Address (MESSAGE_ADDR)—Offset A4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
MESSAGE_ADDR: [B:0, D:20, F:2] + A4h
Default: 00000000h
31
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
Bit
Range
16.5.1.30
0
0
RSVD0
address
0
24
Default &
Access
Description
31: 2
0h
RW
Message Address (address): If the Message Enable bit (bit 0 of the Message Control
register) is set, the contents of this register specify the DWORD-aligned address
(AD[31:2]) for the MSI memory write transaction. AD[1:0] are driven to zero during the
address phase. This field is read/write
1: 0
0h
RO
RSVD0 (RSVD0): Reserved
Message Data (MESSAGE_DATA)—Offset A8h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_DATA: [B:0, D:20, F:2] + A8h
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
MsgData
0
12
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Datasheet
451
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Description
0h
RW
Data Field (MsgData): System-specified message data. If the Message Enable bit (bit
0 of the Message Control register) is set, the message data is driven onto the lower
word (AD[15:0]) of the memory write transactions data phase. AD[31:16] are driven to
zero during the memory write transactions data phase. C/BE[3::0]# are asserted during
the data phase of the memory write transaction. None of the message bits will be
changed by hardware
15: 0
16.5.1.31
Mask Bits for MSI (PER_VEC_MASK)—Offset ACh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_MASK: [B:0, D:20, F:2] + ACh
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
RSVD0
0
28
Bit
Range
16.5.1.32
0
MSIMask
31
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RW
Vector 0 Mask (MSIMask): Mask Bit for Vector 0. If this bit is set, the function will not
send MSI messages
Pending Bits for MSI (PER_VEC_PEND)—Offset B0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_PEND: [B:0, D:20, F:2] + B0h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
RSVD0
0
28
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RO
Vector 0 Pending (value): Pending Bit for Vector 0.
Intel® Quark™ SoC X1000
Datasheet
452
0
4
value
31
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Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
16.5.2
USB EHCI
Table 104.
Summary of PCI Configuration Registers—0/20/3
Offset Start
0h
Offset End
1h
Default
Value
Register ID—Description
“Vendor ID (VENDOR_ID)—Offset 0h” on page 438
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 439
0939h
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 439
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 440
0010h
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 440
0C032010h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 441
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 441
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 442
80h
Fh
Fh
“BIST (BIST)—Offset Fh” on page 457
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 458
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 459
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 459
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 459
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 460
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 460
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 460
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 461
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 461
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 462
00h
60h
60h
“Serial Bus Release Number Register (SBRN)—Offset 60h” on page 462
20h
61h
61h
“Frame Length Adjustment Register (FLADJ)—Offset 61h” on page 462
20h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 463
01h
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 463
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 463
F803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 464
0008h
86h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 465
00h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 465
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 465
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 466
C0h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 466
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 467
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 467
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 468
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 468
00000000h
C0h
C3h
“USB Legacy Support Extended Capability (USBLEGSUP)—Offset C0h” on
page 468
00000001h
C4h
C7h
“USB Legacy Support Control/Status (USBLEGCTLSTS)—Offset C4h” on page 469
00000000h
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Intel® Quark™ SoC X1000—USB 2.0
16.5.2.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:3] + 0h
Default: 8086h
15
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
1
0
0
1
value
1
12
Bit
Range
Default &
Access
8086h
RO
15: 0
16.5.2.2
Description
Vendor ID (value): PCI Vendor ID for Intel
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:3] + 2h
Default: 0939h
15
12
0
0
0
8
1
0
0
4
1
0
0
1
1
0
value
0
Bit
Range
Default &
Access
0939h
RO
15: 0
16.5.2.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:3] + 4h
Default: 0000h
Bit
Range
Default &
Access
15: 11
0h
RO
Intel® Quark™ SoC X1000
Datasheet
454
0
0
0
0
0
0
0
0
0
RSVD
0
MEMen
0
0
MasEn
0
4
RSVD
0
SERREn
0
8
RSVD
0
RSVD0
0
12
IntrDis
15
Description
RSVD0 (RSVD0): Reserved
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.2.4
Default &
Access
Description
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
0
0h
RO
Reserved (RSVD): Reserved.
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:3] + 6h
Default: 0010h
Bit
Range
Default &
Access
0
1
0
0
0
0
RSVD1
0
0
IntrStatus
0
hasCapList
0
capable_66Mhz
0
RSVD
0
FastB2B
0
4
RSVD
0
DEVSEL
0
8
RSVD
0
RcdMasAb
0
SigSysErr
12
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
November 2014
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Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.5.2.5
Default &
Access
Description
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:3] + 8h
Default: 0C032010h
0
1
1
0
0
0
0
0
16.5.2.6
0
16
0
0
1
1
12
0
0
1
0
8
0
0
0
0
4
0
0
0
1
0
0
0
0
0
rev_id
0
20
progIntf
0
24
classCode
0
28
subClassCode
31
Bit
Range
Default &
Access
31: 24
0Ch
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
03h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
20h
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:3] + Ch
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
Intel® Quark™ SoC X1000
Datasheet
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USB 2.0—Intel® Quark™ SoC X1000
16.5.2.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:3] + Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.2.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
HEADER_TYPE: [B:0, D:20, F:3] + Eh
Default: 80h
7
4
0
0
multiFnDev
Bit
Range
16.5.2.9
0
0
0
0
0
cfgHdrFormat
1
0
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:3] + Fh
Default: 00h
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457
Intel® Quark™ SoC X1000—USB 2.0
7
4
0
0
0
0
0
0
comp_code
RSVD
BIST_capable
Bit
Range
16.5.2.10
0
start_bist
0
0
Default &
Access
Description
7
0h
RO
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
3: 0
0h
RO
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:3] + 10h
Default: 00000000h
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
4
0
RSVD
0
0
0
0
0
0
0
0
0
isIO
0
memType
28
0
address
0
prefetchable
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Intel® Quark™ SoC X1000
Datasheet
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USB 2.0—Intel® Quark™ SoC X1000
16.5.2.11
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:3] + 28h
Default: 00000000h
31
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
24
Bit
Range
Default &
Access
0h
RO
31: 0
16.5.2.12
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:3] + 2Ch
Default: 0000h
15
12
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.2.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:3] + 2Eh
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
12
Bit
Range
15: 0
Default &
Access
0h
RO
November 2014
Document Number: 329676-004US
Description
Subsystem ID (value): PCI Subsystem ID
Intel® Quark™ SoC X1000
Datasheet
459
Intel® Quark™ SoC X1000—USB 2.0
16.5.2.14
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:3] + 30h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
16.5.2.15
0
0
0
0
0
0
0
RSVD
ROM_base_addr
0
28
0
AddrDecodeEn
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:3] + 34h
Default: 00000080h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
16.5.2.16
4
1
0
0
0
0
0
0
0
0
value
RSVD0
0
28
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
Intel® Quark™ SoC X1000
Datasheet
460
INTR_LINE: [B:0, D:20, F:3] + 3Ch
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.2.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:3] + 3Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
7: 0
16.5.2.18
Default &
Access
Description
04h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:3] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
Default &
Access
7: 0
0h
RO
November 2014
Document Number: 329676-004US
Description
MIN_GNT (value): Hardwired to 0
Intel® Quark™ SoC X1000
Datasheet
461
Intel® Quark™ SoC X1000—USB 2.0
16.5.2.19
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:3] + 3Fh
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
value
0
0
16.5.2.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Serial Bus Release Number Register (SBRN)—Offset 60h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
SBRN: [B:0, D:20, F:3] + 60h
Default: 20h
7
4
0
1
0
0
0
0
SBRN
0
16.5.2.21
Bit
Range
Default &
Access
Description
7: 0
20h
RO
Serial Bus Specification Release Number (SBRN): Serial Bus Specification Release
Number.
Frame Length Adjustment Register (FLADJ)—Offset 61h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
FLADJ: [B:0, D:20, F:3] + 61h
Default: 20h
7
4
0
1
0
RSVD0
Bit
Range
Default &
Access
7: 6
0h
RO
Intel® Quark™ SoC X1000
Datasheet
462
0
0
0
0
0
FLADJ
0
Description
RSVD0 (RSVD0): Reserved
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
16.5.2.22
Bit
Range
Default &
Access
5: 0
20h
RW
Description
Frame Length Timing Value (FLADJ): Each decimal value change to this register
corresponds to 16 highspeed bit times. The SOF cycle time (number of SOF counter
clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this
field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000.
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:3] + 80h
Default: 01h
7
4
0
0
0
0
0
0
1
value
0
0
16.5.2.23
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:3] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
0
value
1
16.5.2.24
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMC: [B:0, D:20, F:3] + 82h
Default: F803h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
463
Intel® Quark™ SoC X1000—USB 2.0
16.5.2.25
0
0
0
0
0
0
0
1
1
version
0
PME_clock
0
RSVD
1
0
DSI
1
4
aux_curr
1
D1_support
1
8
PME_support
1
12
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
1Fh
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset 84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:3] + 84h
Default: 0008h
0
0
0
0
0
1
0
0
0
power_state
0
RSVD
0
0
no_soft_reset
0
RSVD
0
Data_select
0
4
Data_scale
0
8
PME_status
0
12
PME_en
15
Bit
Range
Default &
Access
Description
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
14: 13
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
15
Intel® Quark™ SoC X1000
Datasheet
464
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.2.26
Default &
Access
Description
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:3] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.2.27
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset 87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:3] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.2.28
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
465
Intel® Quark™ SoC X1000—USB 2.0
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:3] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
16.5.2.29
Bit
Range
Default &
Access
7: 0
05h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:3] + A1h
Default: C0h
7
4
1
0
0
0
0
0
0
value
1
0
16.5.2.30
Bit
Range
Default &
Access
Description
7: 0
C0h
RO
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xC0 to point to the USB Legacy Support Extended
Capability Structure
Message Control (MESSAGE_CTRL)—Offset A2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_CTRL: [B:0, D:20, F:3] + A2h
Default: 0100h
Bit
Range
15: 9
Intel® Quark™ SoC X1000
Datasheet
466
0
0
1
0
Default &
Access
0h
RO
0
0
0
0
0
0
0
MSIEnable
0
0
multiMsgCap
0
4
multiMsgEn
0
8
bit64Cap
0
RSVD0
0
12
perVecMskCap
15
Description
RSVD0 (RSVD0): Reserved
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.2.31
Default &
Access
Description
8
1h
RO
Per Vector Masking Capable (perVecMskCap): Hardwired to 1 to indicate the
function supports PVM
7
0h
RO
64 bit Address Capabale (bit64Cap): This bit is hardwired to 0 to indicate that the
function is not capable of sending a 64-bit message address.
6: 4
0h
RW
Multi-Message Enable (multiMsgEn): As only one vector is supported per function,
software should only write a value of 0x0 to this field
3: 1
0h
RO
Multiple Message Enable (multiMsgCap): This field is hardwired to 0x0 to indicate
that the function is requesting a single vector
0
0h
RW
MSI Enable (MSIEnable): Set to enable MSI to request service. If set then it's
prohibited to use the INTx pin. System configuration software sets this bit to enable
MSI.
Message Address (MESSAGE_ADDR)—Offset A4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
MESSAGE_ADDR: [B:0, D:20, F:3] + A4h
Default: 00000000h
31
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
Bit
Range
16.5.2.32
0
0
RSVD0
address
0
24
Default &
Access
Description
31: 2
0h
RW
Message Address (address): If the Message Enable bit (bit 0 of the Message Control
register) is set, the contents of this register specify the DWORD-aligned address
(AD[31:2]) for the MSI memory write transaction. AD[1:0] are driven to zero during the
address phase. This field is read/write
1: 0
0h
RO
RSVD0 (RSVD0): Reserved
Message Data (MESSAGE_DATA)—Offset A8h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_DATA: [B:0, D:20, F:3] + A8h
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
MsgData
0
12
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
467
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Description
0h
RW
Data Field (MsgData): System-specified message data. If the Message Enable bit (bit
0 of the Message Control register) is set, the message data is driven onto the lower
word (AD[15:0]) of the memory write transactions data phase. AD[31:16] are driven to
zero during the memory write transactions data phase. C/BE[3::0]# are asserted during
the data phase of the memory write transaction. None of the message bits will be
changed by hardware
15: 0
16.5.2.33
Mask Bits for MSI (PER_VEC_MASK)—Offset ACh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_MASK: [B:0, D:20, F:3] + ACh
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
RSVD0
0
28
Bit
Range
16.5.2.34
0
MSIMask
31
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RW
Vector 0 Mask (MSIMask): Mask Bit for Vector 0. If this bit is set, the function will not
send MSI messages
Pending Bits for MSI (PER_VEC_PEND)—Offset B0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_PEND: [B:0, D:20, F:3] + B0h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
RSVD0
0
28
Bit
Range
16.5.2.35
Default &
Access
0
value
31
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RO
Vector 0 Pending (value): Pending Bit for Vector 0.
USB Legacy Support Extended Capability (USBLEGSUP)—Offset C0h
Access Method
Intel® Quark™ SoC X1000
Datasheet
468
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Type: PCI Configuration Register
(Size: 32 bits)
USBLEGSUP: [B:0, D:20, F:3] + C0h
Default: 00000001h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
1
Bit
Range
Default &
Access
31: 25
0h
RO
RSVD0 (RSVD0): Reserved
0b
RW
HC OS Owned Semaphore (HC_OS_Owned_Semaphore): System software sets
this bit to request ownership of the EHCI controller. Ownership is obtained when this bit
reads as one and the HC BIOS Owned Semaphore bit reads as zero.
00h
RO
Reserved (RSVD): Reserved.
16
0b
RW
HC BIOS Owned Semaphore (HC_BIOS_Owned_Semaphore): The BIOS sets this
bit to establish ownership of the EHCI controller. System BIOS will set this bit to a zero
in response to a request for ownership of the EHCI controller by system software.
15: 8
0h
RO
Next EHCI Extended Capability Pointer (NXT_CAP_PTR): This field points to the
PCI configuration space offset of the next extended capability pointer. A value of 00h
indicates the end of the extended capability list.
7: 0
01h
RO
Capability ID (CAP_ID): This field identifies the extended capability. A value of 01h
identifies the capability as Legacy Support. This extended capability requires one
additional 32-bit register for control/status information, and this register is located at
offset EECP+04h.
24
23: 17
16.5.2.36
0
8
CAP_ID
0
12
NXT_CAP_PTR
0
16
HC_BIOS_Owned_Semaphore
0
20
RSVD
0
24
RSVD0
0
28
HC_OS_Owned_Semaphore
31
Description
USB Legacy Support Control/Status (USBLEGCTLSTS)—Offset C4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
USBLEGCTLSTS: [B:0, D:20, F:3] + C4h
Default: 00000000h
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
469
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SMI_USB_ERROR_EN
0
SMI_USB_COMPLETE_EN
0
SMI_PORT_CHANGE_DETECT_EN
0
SMI_FRAME_LIST_ROLLOVER_EN
0
0
SMI_ASYNC_ADVANCE_EN
0
4
SMI_HOST_SYSTEM_ERROR_EN
0
8
RSVD
0
SMI_OS_OWNR_CHANGE_EN
0
SMI_BAR_EN
0
12
SMI_PCI_CMD_EN
0
SMI_USB_ERROR
0
SMI_USB_COMPLETE
0
SMI_PORT_CHANGE_DETECT
0
SMI_FRAME_LIST_ROLLOVER
0
16
SMI_ASYNC_ADVANCE
0
20
SMI_HOST_SYSTEM_ERROR
0
24
RSVD
0
SMI_OS_OWNR_CHANGE
SMI_BAR
0
28
SMI_PCI_CMD
31
Description
31
0b
RW
SMI on BAR (SMI_BAR): This bit is set to one whenever the Base Address Register
(BAR) is written.
30
0b
RW
SMI on PCI Command (SMI_PCI_CMD): This bit is set to one whenever the PCI
Command Register is written.
29
0b
RW
SMI on OS Ownership Change (SMI_OS_OWNR_CHANGE): This bit is set to one
whenever the HC OS Owned Semaphore bit in the USBLEGSUP register transitions from
1 to a 0 or 0 to a 1
00h
RO
Reserved (RSVD): Reserved.
21
0b
RO
SMI on Async Advance (SMI_ASYNC_ADVANCE): Shadow bit of the Interrupt on
Async Advance bit in the USBSTS register see Section 2.3.2 for definition. To set this bit
to a zero, system software must write a one to the Interrupt on Async Advance bit in the
USBSTS register.
20
0b
RO
SMI on Host System Error (SMI_HOST_SYSTEM_ERROR): Shadow bit of Host
System Error bit in the USBSTS register, see Section 2.3.2 for definition and effects of
the events associated with this bit being set to a one. To set this bit to a zero, system
software must write a one to the Host System Error bit in the USBSTS register.
19
0b
RO
SMI on Frame List Rollover (SMI_FRAME_LIST_ROLLOVER): Shadow bit of Frame
List Rollover bit in the USBSTS register see Section 2.3.2 for definition. To set this bit to
a zero, system software must write a one to the Frame List Rollover bit in the USBSTS
register.
18
0b
RO
SMI on Port Change Detect (SMI_PORT_CHANGE_DETECT): Shadow bit of Port
Change Detect bit in the USBSTS register see Section 2.3.2 for definition. To set this bit
to a zero, system software must write a one to the Port Change Detect bit in the
USBSTS register.
17
0b
RO
SMI on USB Error (SMI_USB_ERROR): Shadow bit of USB Error Interrupt
(USBERRINT) bit in the USBSTS register see Section 2.3.2 for definition. To set this bit
to a zero, system software must write a one to the USB Error Interrupt bit in the
USBSTS register.
16
0b
RO
SMI on USB Complete (SMI_USB_COMPLETE): Shadow bit of USB Interrupt
(USBINT) bit in the USBSTS register see Section 2.3.2 for definition. To set this bit to a
zero, system software must write a one to the USB Interrupt bit in the USBSTS register.
15
0b
RW
SMI on BAR Enable (SMI_BAR_EN): When this bit is one and SMI on BAR is one,
then the host controller will issue an SMI.
14
0b
RW
SMI on PCI Command Enable (SMI_PCI_CMD_EN): When this bit is one and SMI
on PCI Command is one, then the host controller will issue an SMI.
13
0b
RW
SMI on OS Ownership Enable (SMI_OS_OWNR_CHANGE_EN): When this bit is a
one AND the OS Ownership Change bit is one, the host controller will issue an SMI.
28: 22
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Datasheet
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November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
12: 6
00h
RO
Reserved (RSVD): Reserved.
5
0b
RW
SMI on Async Advance Enable (SMI_ASYNC_ADVANCE_EN): When this bit is a
one, and the SMI on Async Advance bit (above) in this register is a one, the host
controller will issue an SMI immediately
4
0b
RW
SMI on Host System Error Enable (SMI_HOST_SYSTEM_ERROR_EN): When this
bit is a one, and the SMI on Host System Error bit (above) in this register is a one, the
host controller will issue an SMI immediately
3
0b
RW
SMI on Frame List Rollover Enable (SMI_FRAME_LIST_ROLLOVER_EN): When
this bit is a one, and the SMI on Frame List Rollover bit (above) in this register is a one,
the host controller will issue an SMI immediately.
2
0b
RW
SMI on Port Change Enable (SMI_PORT_CHANGE_DETECT_EN): When this bit is
a one, and the SMI on Port Change Detect bit (above) in this register is a one, the host
controller will issue an SMI immediately.
1
0b
RW
SMI on USB Error Enable (SMI_USB_ERROR_EN): When this bit is a one, and the
SMI on USB Error bit (above) in this register is a one, the host controller will issue an
SMI immediately.
0
0b
RW
USB SMI Enable (SMI_USB_COMPLETE_EN): When this bit is a one, and the SMI on
USB Complete bit (above) in this register is a one, the host controller will issue an SMI
immediately.
16.5.3
USB OHCI
Table 105.
Summary of PCI Configuration Registers—0/20/4
Offset Start
Offset End
Default
Value
Register ID—Description
0h
1h
“Vendor ID (VENDOR_ID)—Offset 0h” on page 438
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 439
093Ah
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 439
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 440
0010h
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 440
0C031010h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 441
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 441
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 442
80h
Fh
Fh
“BIST (BIST)—Offset Fh” on page 442
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 443
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 443
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 444
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 444
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 444
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 460
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 460
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 461
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 461
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 462
00h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 463
01h
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Intel® Quark™ SoC X1000—USB 2.0
Table 105.
Offset Start
Summary of PCI Configuration Registers—0/20/4 (Continued)
Offset End
Default
Value
Register ID—Description
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 463
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 463
4803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 464
0008h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 465
00h
86h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 465
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 465
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 466
00h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 466
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 467
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 467
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 485
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 468
00000000h
16.5.3.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:4] + 0h
Default: 8086h
15
12
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
value
1
Bit
Range
Default &
Access
8086h
RO
15: 0
16.5.3.2
Description
Vendor ID (value): PCI Vendor ID for Intel
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:4] + 2h
Default: 093Ah
15
0
0
0
8
1
0
0
4
1
0
0
1
1
0
1
0
1
0
value
0
12
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Datasheet
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November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
093Ah
RO
15: 0
16.5.3.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:4] + 4h
Default: 0000h
16.5.3.4
0
0
0
0
0
0
0
0
0
RSVD
0
MEMen
0
0
MasEn
0
4
RSVD
0
SERREn
0
RSVD
0
8
RSVD0
0
12
IntrDis
15
Bit
Range
Default &
Access
15: 11
0h
RO
RSVD0 (RSVD0): Reserved
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
0
0h
RO
Reserved (RSVD): Reserved.
Description
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:4] + 6h
Default: 0010h
November 2014
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Datasheet
473
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.5.3.5
Default &
Access
0
0
1
0
0
0
0
RSVD1
0
IntrStatus
0
0
hasCapList
DEVSEL
0
capable_66Mhz
0
RSVD
0
FastB2B
0
4
RSVD
0
8
RSVD
0
RcdMasAb
0
SigSysErr
12
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:4] + 8h
Default: 0C031010h
0
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474
24
1
1
0
0
20
0
0
0
0
16
0
0
1
1
12
0
0
0
1
8
0
0
0
0
4
0
0
0
1
0
0
0
0
0
rev_id
0
progIntf
28
0
classCode
0
subClassCode
31
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
16.5.3.6
Bit
Range
Default &
Access
31: 24
0Ch
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
03h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
10h
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:4] + Ch
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:4] + Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
November 2014
Document Number: 329676-004US
HEADER_TYPE: [B:0, D:20, F:4] + Eh
Intel® Quark™ SoC X1000
Datasheet
475
Intel® Quark™ SoC X1000—USB 2.0
Default: 80h
7
4
0
0
0
multiFnDev
Bit
Range
16.5.3.9
0
0
0
0
0
cfgHdrFormat
1
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:4] + Fh
Default: 00h
7
4
0
16.5.3.10
0
0
0
0
0
0
comp_code
RSVD
BIST_capable
Bit
Range
0
start_bist
0
Default &
Access
Description
7
0h
RO
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
3: 0
0h
RO
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:4] + 10h
Default: 00000000h
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USB 2.0—Intel® Quark™ SoC X1000
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
8
0
0
0
0
16.5.3.11
4
0
0
0
0
0
0
0
0
0
isIO
0
16
memType
0
20
prefetchable
0
24
address
0
28
RSVD
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:4] + 28h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
28
Bit
Range
31: 0
16.5.3.12
Default &
Access
0h
RO
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:4] + 2Ch
Default: 0000h
November 2014
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Datasheet
477
Intel® Quark™ SoC X1000—USB 2.0
15
12
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
8
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.3.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:4] + 2Eh
Default: 0000h
15
12
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
8
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.3.14
Description
Subsystem ID (value): PCI Subsystem ID
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:4] + 30h
Default: 00000000h
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
AddrDecodeEn
0
24
ROM_base_addr
0
28
RSVD
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Intel® Quark™ SoC X1000
Datasheet
478
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
16.5.3.15
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:4] + 34h
Default: 00000080h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
0
0
RSVD0
0
28
Bit
Range
16.5.3.16
0
0
0
0
0
0
value
31
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_LINE: [B:0, D:20, F:4] + 3Ch
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.3.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:4] + 3Dh
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
November 2014
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Datasheet
479
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
7: 0
16.5.3.18
Default &
Access
Description
01h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:4] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
value
0
0
16.5.3.19
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MIN_GNT (value): Hardwired to 0
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:4] + 3Fh
Default: 00h
7
4
0
0
0
0
0
0
value
0
16.5.3.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:4] + 80h
Default: 01h
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Datasheet
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November 2014
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USB 2.0—Intel® Quark™ SoC X1000
7
4
0
0
0
0
0
0
1
value
0
0
16.5.3.21
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:4] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
value
1
0
16.5.3.22
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMC: [B:0, D:20, F:4] + 82h
Default: 4803h
0
0
0
0
0
0
0
1
1
version
0
0
PME_clock
0
RSVD
1
DSI
0
4
aux_curr
0
8
D1_support
1
PME_support
0
12
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
09h
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
November 2014
Document Number: 329676-004US
Intel® Quark™ SoC X1000
Datasheet
481
Intel® Quark™ SoC X1000—USB 2.0
16.5.3.23
Bit
Range
Default &
Access
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Description
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset 84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:4] + 84h
Default: 0008h
0
0
0
0
0
0
0
0
0
0
1
0
RSVD
0
4
0
0
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
14: 13
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
15
Intel® Quark™ SoC X1000
Datasheet
482
power_state
Description
RSVD
Default &
Access
PME_en
Bit
Range
Data_select
Data_scale
0
8
PME_status
0
12
no_soft_reset
15
November 2014
Document Number: 329676-004US
USB 2.0—Intel® Quark™ SoC X1000
16.5.3.24
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:4] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.3.25
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset 87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:4] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.26
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:4] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
Bit
Range
Default &
Access
7: 0
05h
RO
November 2014
Document Number: 329676-004US
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Intel® Quark™ SoC X1000
Datasheet
483
Intel® Quark™ SoC X1000—USB 2.0
16.5.3.27
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:4] + A1h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.28
Bit
Range
Default &
Access
Description
7: 0
00h
RO
Next Capability Pointer (value): Hardwired to 0 as this is the last capability