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AS5043
Data Sheet - Pin Configuration
AS5043
Data Sheet
Programmable 360° Magnetic Angle Encoder
with Absolute SSI and Analog Outputs
3 Key Features
ƒ
ƒ
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ƒ
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360° contactless high resolution angular position
encoding
User programmable zero position
Two 10-bit absolute outputs:
Serial digital interface and
Versatile analog output
programmable angular range up to 360°
programmable ratiometric output voltage range
Failure detection mode for magnet field strength
and loss of power supply
Serial read-out of multiple interconnected
AS5043 devices using daisy chain mode
Mode input for optimizing noise vs. speed
Alignment mode for magnet placement guidance
Wide temperature range: - 40°C to + 125°C
Small package: SSOP 16 (5.3mm x 6.2mm)
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The AS5043 is a contactless magnetic angle encoder for
accurate measurement up to 360°.
It is a system-on-chip, combining integrated Hall
elements, analog front end and digital signal processing
in a single device.
The AS5043 provides a digital 10-bit as well as a
programmable analog output that is directly proportional
to the angle of a magnet, rotating over the chip.
The analog output can be configured in many ways,
including user programmable angular range, adjustable
output voltage range, voltage or current output, etc..
An internal voltage regulator allows operation of the
AS5043 from 3.3V or 5.0V supplies.
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1 General Description
2 Benefits
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Complete system-on-chip
ƒ
Flexible system solution provides absolute output,
both digital and analog
ƒ
Angle measurement with software programmable
range up to 360°
ƒ
High reliability due to non-contact magnetic sensing
ƒ
Ideal for applications in harsh environments
ƒ
Robust system, tolerant to magnet misalignment,
airgap variations, temperature variations and
external magnetic fields
ƒ
No calibration required
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4 Applications
The AS5043 is ideal for applications with an angular
travel range from a few degrees up to a full turn of
360°, such as
- Industrial applications:
- Contactless rotary position sensing
- Robotics
- Valve Controls
- Automotive applications:
- Throttle position sensors
- Gas / brake pedal position sensing
- Headlight position control
Front panel rotary switches
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Replacement of potentiometers
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Figure 1: Typical Arrangement of AS5043 and Magnet
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Revision 1.80
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AS5043
Data Sheet - Pin Configuration
5 Pin Configuration
1
16
VDD5V
Mode
2
15
VDD3V3
CSn
3
14
NC
CLK
4
13
NC
NC
5
12
Vout
DO
6
11
FB
VSS
7
10
DACout
Prog_DI
8
9
DACref
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MagRngn
Package = SSOP16 (16 lead Shrink Small Outline Package)
Type
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Table 1: Pin Description SSOP16
Pin Symbol
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Figure 2: AS5043 Pin Configuration SSOP16
Description
1
MagRngn DO_OD
Magnet Field Magnitude RaNGe warning; active low, indicates that the magnetic field
strength is outside of the recommended limits.
2
Mode
DI_PD, ST
Mode input. Select between low noise (low, connect to VSS) and high speed (high,
connect to VDD5V) mode at power up. Internal pull-down resistor.
3
CSn
DI_PU, ST
Chip Select, active low; Schmitt-Trigger input, internal pull-up resistor (~50kΩ)
4
CLK
DI,ST
Clock Input of Synchronous Serial Interface; Schmitt-Trigger input
5
NC
-
6
DO
DO_T
7
VSS
S
8
Prog_DI
DI_PD
9
DACref
AI
10
DACout
AO
11
FB
AI
12
Vout
AO
13
NC
-
14
NC
must be left unconnected
Data Output of Synchronous Serial Interface
Negative Supply Voltage (GND)
OTP Programming Input and Data Input for Daisy Chain mode. Internal pull-down resistor
(~74kΩ).
Should be connected to VSS if programming is not used
DAC Reference voltage input for external reference
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DAC output (unbuffered, Ri ~8kΩ)
Feedback, OPAMP inverting input
OPAMP output
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Must be left unconnected
-
Must be left unconnected
VDD3V3
S
3V-Regulator Output for internal core, regulated from VDD5V.Connect to VDD5V for 3V
supply voltage. Do not load externally.
16
VDD5V
S
Positive Supply Voltage, 3.0 to 5.5 V
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15
DO_OD digital output open drain
DI_PD digital input pull-down
DI_PU digital input pull-up
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S
DO_T
ST
supply pin
digital output /tri-state
Schmitt-trigger input
Revision 1.80
AI
AO
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analog input
analog output
digital input
2 – 36
AS5043
Data Sheet - Pin Configuration
5.1 Pin Description
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Pins 7, 15 and 16 are supply pins, pins 5, 13 and 14 are for internal use and must be left open.
Pin 1 is the magnetic field strength indicator, MagRNGn. It is an open-drain output that is pulled to VSS when the
magnetic field is out of the recommended range (45mT to 75mT). The chip will still continue to operate, but with reduced
performance, when the magnetic field is out of range. When this pin is low, the analog output at pins #10 and #12 will be
0V to indicate the out-of-range condition.
Pin 2 MODE allows switching between filtered (slow) and unfiltered (fast mode). This pin must be tied to VSS or VDD5V,
and must not be switched after power up. See section 0.
Pin 3 Chip Select (CSn; active low) selects a device for serial data transmission over the SSI interface. A “logic high” at
CSn forces output DO to digital tri-state.
Pin 4 CLK is the clock input for serial data transmission over the SSI interface (see section 1)
Pin 6 DO (Data Out) is the serial data output during data transmission over the SSI interface (see section 1)
Pin 8 PROG_DI is used to program the different operation modes, as well as the zero-position in the OTP register.
This pin is also used as a digital input to shift serial data through the device in Daisy Chain Configuration, (see page 9).
Pin 9 DACref is the external voltage reference input for the Digital-to-Analog Converter (DAC). If selected, the analog
output voltage on pin 12 (Vout) will be ratiometric to the voltage on this pin.
Pin10 DACout is the unbuffered output of the DAC. This pin may be used to connect an external OPAMP, etc. to the
DAC.
Pin 11 FB (Feedback) is the inverting input of the OPAMP buffer stage.
Access to this pin allows various OPAMP configurations.
Pin 12 Vout is the analog output pin. The analog output is a DC voltage, ratiometric to VDD5V (3.0 – 5.5V) or an external
voltage source and proportional to the angle.
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AS5043
Data Sheet – Functional Description
6 Functional Description
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The AS5043 is manufactured in a CMOS standard process and uses a spinning current Hall technology for sensing the
magnetic field distribution across the surface of the chip.
The integrated Hall elements are placed in a circle around the center of the device and deliver a voltage representation of
the magnetic field perpendicular to the surface of the IC.
Through Sigma-Delta Analog / Digital Conversion and Digital Signal-Processing (DSP) algorithms, the AS5043 provides
accurate high-resolution absolute angular position information. For this purpose a Coordinate Rotation Digital Computer
(CORDIC) calculates the angle and the magnitude of the Hall array signals.
The DSP is also used indicate movements of the magnet towards or away from the chip and to indicate, when the
magnetic field is outside of the recommended range (status bits = MagInc, MagDec; hardware pin = MagRngn).
A small low cost diametrically magnetized (two-pole) standard magnet, centered over the chip, is used as the input
device.
The AS5043 senses the orientation of the magnetic field and calculates a 10-bit binary code. This code can be accessed
via a Synchronous Serial Interface (SSI). In addition, the absolute angular representation is converted to an analog
signal, ratiometric to the supply voltage.
The analog output can be configured in many ways, such as 360°/180°/90° or 45° angular range, external or internal DAC
reference voltage, 0-100%*VDD or 10-90% *VDD analog output range, external or internal amplifier gain setting.
The various output modes as well as a user programmable zero position can be programmed in an OTP register. As long
as no programming voltage is applied to pin PROG, the new setting may be overwritten at any time and will be reset to
default when power is cycled. To make the setting permanent, the OTP register must be programmed by applying a
programming voltage.
The AS5043 is tolerant to magnet misalignment and unwanted external magnetic fields due to differential measurement
technique and Hall sensor conditioning circuitry.
It is also tolerant to airgap and temperature variations due to Sin-/Cos- signal evaluation.
Figure 3: AS5043 Block Diagram
MagRNGn
Mode
Sin
Ang
Cos
Mag
DO
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CSn
CLK
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DACref
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Vout
+
DACout
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FB
10
Prog_DI
Revision 1.80
4 – 36
AS5043
Data Sheet – 3.3V / 5V Operation
7 3.3V / 5V Operation
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The AS5043 operates either at 3.3V ±10% or at 5V ±10%. This is made possible by an internal 3.3V Low-Dropout (LDO)
Voltage regulator. The core supply voltage is always taken from the LDO output, as the internal blocks are always
operating at 3.3V.
For 3.3V operation, the LDO must be bypassed by connecting VDD3V3 with VDD5V (see Figure 4 ).
For 5V operation, the 5V supply is connected to pin VDD5V, while VDD3V3 (LDO output) must be buffered by a 1...10µF
capacitor, which should be placed close to the supply pin.
The VDD3V3 output is intended for internal use only. It should not be loaded with an external load.
The voltage levels of the digital interface I/O’s correspond to the voltage at pin VDD5V, as the I/O buffers are supplied
from this pin (see Figure 4).
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Figure 4: Connections for 5V / 3.3V Supply Voltages
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A buffer capacitor of 100nF is recommended in both cases close to pin VDD5V. Note that pin VDD3V3 must always be
buffered by a capacitor. It must not be left floating, as this may cause an instable internal 3.3V supply voltage which may
lead to larger than normal jitter of the measured angle.
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AS5043
Data Sheet – 10-bit Absolute Synchronous Serial Interface (SSI)
8 10-bit Absolute Synchronous Serial Interface (SSI)
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The serial data transmission timing is outlined in Figure 5: if CSn changes to logic low, Data Out (DO) will change from
high impedance (tri-state) to logic high and the read-out sequence will be initiated.
After a minimum time tCLK FE, data is latched into the output shift register with the first falling edge of CLK.
Each subsequent rising CLK edge shifts out one bit of data.
The serial word contains 16 bits, the first 10 bits are the angular information D[9:0], the subsequent 6 bits contain system
information, about the validity of data such as OCF, COF, LIN, Parity and Magnetic Field status (increase / decrease / out
of range) .
A subsequent measurement is initiated by a logic “high” pulse at CSn with a minimum duration of tCSn.
Data transmission may be terminated at any time by pulling CSn = high.
8.1 Serial Data Contents
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D9:D0 absolute angular position data (MSB is clocked out first).
OCF (Offset Compensation Finished), logic high indicates that the Offset Compensation Algorithm has finished and data
is valid.
COF (Cordic Overflow), logic high indicates an out of range error in the CORDIC part. When this bit is set, the data at
D9:D0 is invalid. The absolute output maintains the last valid angular value.
This alarm may be resolved by bringing the magnet within the X-Y-Z tolerance limits.
LIN (Linearity Alarm), logic high indicates that the input field generates a critical output linearity.
When this bit is set, the data at D9:D0 may still be used, but may contain invalid data. This warning may be resolved by
bringing the magnet within the X-Y-Z tolerance limits.
Data D9:D0 is valid, when the status bits have the following configurations:
Table 2: Status Bit Outputs
OCF
1
COF
0
LIN
0
Mag
INC
Mag
DEC
0
0
0
1
1
0
Parity
even checksum of bits 1:15
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MagInc, (Magnitude Increase) becomes HIGH, when the magnet is pushed towards the IC, thus the magnetic field
strength is increasing.
MagDec, (Magnitude Decrease) becomes HIGH, when the magnet is pulled away from the IC, thus the magnetic field
strength is decreasing.
Both signals HIGH indicate a magnetic field that is out of the allowed range (see Table 3).
Note: Pin 1 (MagRngn) is a combination of MagInc and MagDec. It is active low via an open drain output and requires an
external pull-up resistor. If the magnetic field is in range, this output is turned off. (logic “high”).
Even Parity bit for transmission error detection of bits 1…15 (D9…D0, OCF, COF, LIN, MagInc, MagDec)
The absolute angular output is always set to a resolution of 10 bit / 360°. Placing the magnet above the chip, angular
values increase in clockwise direction by default.
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Figure 5: Synchronous Serial Interface with Absolute Angular Position Data
CSn
t CLK FE
T CLK / 2
t CSn
1
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CLK
DO
t DO active
D9
t DO valid
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D8
8
D7
D6
D5
D4
D3
1
16
D2
D1
D0
OCF
COF
LIN
Mag
INC
Status Bits
Angular Position Data
Revision 1.80
Mag
DEC
t CLK FE
Even
PAR
D9
t DO Tristate
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AS5043
Data Sheet – 10-bit Absolute Synchronous Serial Interface (SSI)
8.2 Z-Axis Range Indication (Push Button Feature, Red/Yellow/Green Indicator)
The AS5043 provides several options of detecting movement and distance of the magnet in the vertical (Z-) direction.
Signal indicators MagINC, MagDEC and LIN are available as status bits in the serial data stream, while MagRngn is an
open-drain output that indicates an out-of range status (on in YELLOW or RED range). Additionally, the analog output
provides a safety feature in the form that it will be turned off when the magnetic field is too strong or too weak (RED
range). The serial data is always available, the red/yellow/green status is indicated by the status bits as shown below:
SSI Status Bits
Hardware Pins
Mag
INC
Mag
DEC
LIN
Mag
Rngn
0
0
0
Off
0
1
0
Off
1
0
0
Off
1
1
0
On
1
On
enabled
Distance increase, GREEN range; Pull-function. This state is dynamic and only
active while the magnet is moving away from the chip.
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enabled
No distance change
Magnetic Input Field OK (GREEN range, ~45…75mT)
Distance decrease, GREEN range; Push- function. This state is dynamic and only
active while the magnet is moving towards the chip.
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1
enabled
enabled
YELLOW Range: Magnetic field is ~ 25…45mT or ~75…135mT. The AS5043 may
still be operated in this range, but with slightly reduced accuracy.
disabled
RED Range: Magnetic field is ~<25mT or >~135mT. The analog output will be
turned off in this range by default. It can be enabled permanently by OTP
programming (see 11.1.2).
It is still possible to use the absolute serial interface in the red range, but not
recommended.
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1
Description
Analog
Output
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Table 3: Magnetic Field Strength Indicators
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AS5043
Data Sheet – Mode Input Pin
9 Mode Input Pin
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The absolute angular position is sampled at a rate of 10.4kHz (t=96µs) in fast mode and at a rate of 2.6kHz (t=384µs) in
slow mode.
These modes are selected by pin MODE (#2) during the power up of the AS5043. This pin activates or deactivates an
internal filter, which is used to reduce the digital jitter and consequently the analog output noise.
Activating the filter by pulling Mode = LOW reduces the transition noise to <0.03° rms. At the same time, the sampling
rate is reduced to 2.6kHz and the signal propagation delay is increased to 384µs. This mode is recommended for high
precision, low speed and ≤360° applications.
Deactivating the filter by setting Mode = HIGH increases the sampling rate to 10.4kHz and reduces the signal propagation
delay to 96µs. The transition noise will increase to <0.06° rms. This mode is recommended for higher speed and full scale
= 360° applications.
Switching the MODE pin affects the following parameters:
Slow Mode
(Pin MODE = 0)
Parameter
2.61 kHz
10.42 kHz
(383µs)
(95.9µs)
Transition noise (1 sigma)
≤ 0.03° rms
≤ 0.06° rms
Propagation delay
384µs
96µs
20ms
80ms
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Sampling rate
Fast Mode
(Pin MODE = 1)
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Table 4: Mode Pin Settings
Startup time
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The MODE pin should be set at power-up. A change of the mode during operation is not allowed.
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AS5043
Data Sheet – Daisy Chain Mode
10 Daisy Chain Mode
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The Daisy Chain Mode allows connection of several AS5043’s in series, while still keeping just one digital input for data
transfer (see “Data IN” in Figure 6 ). This mode is accomplished by connecting the data output (DO; pin 9) to the data
input (PROG; pin 8) of the subsequent device. An RC filter must be implemented between each PROG pin of device n
and DO pin of device n+1, to prevent then encoders to enter the alignment mode, in case of ESD discharge, long cables,
not conform signal levels or shape. Using the values R=100R and C=1nF allow a max. CLK frequency of 1MHz on the
whole chain. The serial data of all connected devices is read from the DO pin of the first device in the chain. The length of
the serial bit stream increases with every connected device, it is
n * (16+1) bits:
e.g. 34 bit for two devices, 51 bit for three devices, etc…
The last data bit of the first device (Parity) is followed by a dummy bit and the first data bit of the second device (D9),
etc… (see Figure 7).
CLK
CSn
CSn
CLK
CLK
DO
DI
CSn
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CSn
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Figure 6: Daisy Chain Hardware Configuration
100R
PROG
DO
100R
PROG
PROG
GND
GND
GND
AS5043
DO
1nF
1nF
MCU
CLK
AS5043
AS5043
Figure 7: Daisy Chain Data Transfer Timing Diagram
CSn
t C LK F E
T C LK /2
1
C LK
DO
8
D9
D7
D6
t D O valid
D5
D4
D3
D2
D1
D0
OCF
A ngular P osition D ata
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t D O active
D8
16
COF
LIN
M ag
IN C
S tatus B its
D evice
1
2
D9
D8
3
D7
A ngular P osition D ata
2 nd D evice
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DEC PAR
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9 – 36
AS5043
Data Sheet – Analog Output
11 Analog Output
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The analog output Vout provides an analog voltage that is proportional to the angle of the rotating magnet and ratiometric
to the supply voltage VDD5V (max.5.5V). It can source or sink currents up to ±1mA in normal operation (up to 66mA short
circuit current).
The analog output block consists of a digital angular range selector, a 10-bit Digital-to-Analog converter and an OPAMP
buffer stage (see Figure 14).
The digital range selector allows a preselection of the angular range for 360°,180°,90° or 45° (see Table 5). Fine-tuning of
the angular range can be accomplished by adjusting the gain of the OPAMP buffer stage.
The reference voltage for the Digital-to-Analog converter (DAC) can be taken internally from VDD5V / 2. In this mode, the
output voltage is ratiometric to the supply voltage.
Alternatively, an external DAC reference can be applied at pin DACref (#9). In this mode, the analog output is ratiometric
to the external reference voltage.
An on-chip diagnostic feature turns the analog output off in case of an error (broken supply or magnetic field out of range;
see Table 3).
The DAC output can be accessed directly at pin #10 DACout.
The addition of an OPAMP to the DAC output allows a variety of user configurable options, such as variable output
voltage ranges and variable output voltage versus angle response. By adding an external transistor, the analog voltage
output can be buffered to allow output currents up to hundred milliamperes or more.
Furthermore, the OPAMP can be configured as constant current source.
As an OTP option, the DAC can be configured to 2 different output ranges:
a) 0……100% VDACref. The reference point may be either taken from VDD5V/2 or from the external DACref input. The
0…100% range allows easy replacement of potentiometers. Due to the nature of rail-to-rail outputs, the linearity will
degrade at output voltages that are close to the supply rails.
b) 10…..90% VDACref. This range allows better linearity, as the OPAMP is not driven to the rails. Furthermore, this mode
allows failure detection, when the analog output voltage is outside of the normal operating range of 10…90%VDD, as in
the case of broken supply or when the magnetic field is out of range and the analog output is turned off.
11.1 Analog Output Voltage Modes
The Analog output voltage modes are programmable by OTP. Depending on the application, the analog output can be
selected as rail-to-rail output or as clamped output with 10%-90% VDD5V.
The output is ratiometric to the supply voltage (VDD5V), which can range from 3.0V to 5.5V. If the DAC reference is
switched to an external reference (pin DACref), the output is ratiometric to the external reference.
11.1.1 Full Scale Mode
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This output mode provides a ratiometric DAC output of (0% to 100%)x Vref *), amplified by the OPAMP stage (default =
internal 2x gain, see Figure 14)
Figure 8: Analog Output, Full Scale Mode (shown for 360°mode)
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Note: For simplification, Figure 8 describes
a linear output voltage from rail to rail (0V to
VDD). In practice, this is not feasible due to
saturation effects of the OPAMP output
driver transistors. The actual curve will be
rounded towards the supply rails (as
indicated in Figure 8)
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Vref
100%
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analog
output
voltage
0V
0°
90°
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180°
270°
angle
360°
Revision 1.80
Note: Figure 8 and are shown for 360°
operation. See Table 5 (page 16) for further
angular range programming options.
10 – 36
AS5043
Data Sheet – Analog Output
11.1.2 Diagnostic Output Mode
Figure 9: Diagnostic Output Mode
90%
analog
output
voltage
normal
operating
area
In Diagnostic Output Mode (see Figure 9)
the analog output of the internal DAC ranges
*)
from 10% - 90% Vref . In an error case,
either when the supply is interrupted or
when the magnetic field is in the “red” range,
(see Table 3) the output is switched to 0V
and thus indicates the error condition.
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In an error case, the output
voltage is in the grey area
Vref
100%
10%
It is possible to enable the analog output
permanently (it will not be switched off even
if the magnetic field is out of range). To
enable this feature an OTP bit in the factory setting must be set. The corresponding bit is FS6. See application note
AS5040-20 (Extended features of OTP programming) for further details. The application note is available for download at
the austriamicrosystems website.
0°
180°
90°
360°
270°
angle
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The analog and digital outputs will have the following conditions:
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0%
Status
Normal operation
DAC Output Voltage
10% - 90% Vref
Magnetic field out of range
Broken positive power supply
*)
*)
< 10% Vref ,
DAC output is switched to 0V
SSI Digital Output
#0 - #1023 (0°-360°), MagRngn = 1
#0 - #1023 (0°-360°)
out of range is signaled in status bits:
MagInc=MagDec=LIN=1, MagRngn= 0
< 10% VDD**)
(VOUT pull down resistor at receiving side)
Broken power supply ground
< 10% VDD**)
(VOUT pull down resistor at receiving side)
Broken positive power supply
> 90% VDD**)
with pull down resistor at DO (receiving
side), all bits read by the SSI will be “0”s, indicating a non-valid output
(VOUT pull up resistor at receiving side)
Broken power supply ground
> 90% VDD**)
(VOUT pull up resistor at receiving side)
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*) Vref = internal: ½ * VDD5V (pin #16) or external: VDACref (pin#9), depending on Ref_extEN bit in OTP (0=int., 1=ext.)
**) VDD = positive supply voltage at receiving side (3.0 – 5.5V)
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11 – 36
AS5043
Data Sheet – Programming the AS5043
12 Programming the AS5043
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After power-on, programming the AS5043 is enabled with the rising edge of CSn and Prog = logic high. 16 bit
configuration data must be serially shifted into the OTP register via the Prog-pin. The first “CCW” bit is followed by the
zero position data (MSB first) and the Analog Output Mode setting as shown in Table 5. Data must be valid at the rising
edge of CLK (see Figure 10). Following this sequence, the voltage at pin Prog must be raised to the programming voltage
VPROG (see Figure 10). 16 CLK pulses (tPROG) must be applied to program the fuses. To exit the programming mode, the
chip must be reset by a power-on-reset. The programmed data is available after the next power-up.
Note: During the programming process, the transitions in the programming current may cause high voltage spikes
generated by the inductance of the connection cable. To avoid these spikes and possible damage to the IC, the
connection wires, especially the signals PROG and VSS must be kept as short as possible. The maximum wire length
between the VPROG switching transistor and pin PROG (see Figure 12) should not exceed 50mm (2 inches).
To suppress eventual voltage spikes, a 10nF ceramic capacitor should be connected close to pins PROG and VSS. This
capacitor is only required for programming, it is not required for normal operation. The clock timing tclk must be selected at
a proper rate to ensure that the signal PROG is stable at the rising edge of CLK (see Figure 10). Additionally, the
programming supply voltage should be buffered with a 10µF capacitor mounted close to the switching transistor. This
capacitor aids in providing peak currents during programming. The specified programming voltage at pin PROG is 7.3 –
7.5V (see section 19.7). To compensate for the voltage drop across the VPROG switching transistor, the applied
programming voltage may be set slightly higher (7.5 - 8.0V, see Figure 12).
OTP Register Contents:
CCW
Counter Clockwise Bit
ccw=0 – angular value increases with clockwise rotation
ccw=1 – angular value increases with counterclockwise rotation
Z [9:0]: Programmable Zero / Index Position
FB_intEN: OPAMP gain setting: 0=external, 1=internal
RefExtEN: DAC reference: 0=internal, 1=external
Analog output span: 0=0-100%,
1=10-90%*VDD
ClampMd EN:
Output Range (OR0, OR1):
Analog Output Range Selection
[1:0]
00 = 360°
01 = 180°
10 = 90°
11 = 45°
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Figure 10: Programming Access – OTP Write Cycle (section of)
CSn
CCW
ch
Prog
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tDatain
Z9
Z8
Z7
Z6
Z5
1
CLKPROG
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tProg enable
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tDatain valid
Z4
Z3
Z2
Z1
Z0
FB_int
EN
RefExt
EN
Clamp
Md En
Output
Range1
8
Output
Range0
16
tclk
see text
Zero Position
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Analog Modes
12 – 36
AS5043
Data Sheet – Programming the AS5043
Figure 11: Complete OTP Programming Sequence
Write Data
Programming Mode
Power Off
CSn
7.5V
VDD
VProgOff
0V
Data
Prog
1
16
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CLKPROG
tPrgH
tPrgR
tPROG
tPROG finished
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tLoad PROG
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Figure 12: OTP Programming Hardware Connection of AS5043 (shown with AS5043 demoboard)
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12.1 Zero Position Programming
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The AS5043 allows easy assembly of the system, as the actual angle of the magnet does not need to be considered. By
OTP programming, any position can be assigned as the new permanent zero position with an accuracy of 0.35° (all
modes).
Using the same procedure, the AS5043 can be calibrated to assign a given output voltage to a given angle. With this
approach, all offset errors (DAC + OPAMP) are also compensated for the calibrated position.
Essentially, for a given mechanical position, the angular measurement system is electrically rotated (by changing the
Zero Position value in the OTP register), until the output matches the desired mechanical position.
The example in Figure 13 below shows a configuration for 5V supply voltage and 10%-90% output voltage range. It
adjusted by Zero Position Programming to provide an analog output voltage of 2.0 Volts at an angle of 180°. The slope of
the curve may be further adjusted by changing the gain of the OPAMP output stage and by selecting the desired angular
range (360°/180°/90°/45°).
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AS5043
Data Sheet – Programming the AS5043
Figure 13: Zero Position Programming (shown for 360° mode)
VDD5V
5V
analog
output
voltage
the output can be electrically rotated to
match a given output voltage to any
mechanical position
0°
90°
180°
270°
Mechanical
360° angle
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0V
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2V
12.2 Analog Mode Programming
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The analog output can be configured in many ways:
It consists of three major building blocks,
a digital range preselector,
a 10-bit Digital-to-Analog-Converter (DAC)
and an OP-AMP buffer stage.
In the default configuration (all OTP bits = 0), the analog output is set for 360° operation, internal DAC reference
(VDD5V/2), external OPAMP gain, 0-100% ratiometric to VDD5V.
Shown below is a typical example for a 0°-360° range, 0-5V output. The complete application requires only one external
component, a buffer capacitor at VDD3V3 and has only 3 connections VDD, VSS and Vout (connectors 1-3).
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Note: the default setting for the OPAMP feedback path is:FB_intEn=0=external. The external resistors Rf and Rg must be
installed. In the programmed state (FB_intEn=1=internal), these resistors do not need to be installed as the feedback
path is internal (Rf_int and Rg_int).
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AS5043
Data Sheet – Programming the AS5043
Figure 14: Analog Output Block Diagram
Magnetic field range alarm. Active
low. Leave open or connect to
VSS if not used
Mode pin.
Default = open
(low noise)
1
AS5043
External DAC reference pin.
Leave open or connect to
VSS if not used
16
15
REF_extEN
VDD3V3
+
LDO
3.3V
1=ext
0=int
10
Vref
OR0
Range
Selector
10bit
digital
DAC
DACout
0 - 100% VDD5V /2
+
10bit
analog
VOUT
-
ClampMdEN
0=ext
0= 0-100% * Vref (def.)
1= 10-90% * Vref
FB_intEN
4
6
Digital serial
interface, 10bit/360°.
Leave open if not
used. CSn and CLK
may also be tied to
VSS if not used
PROG
8
Vout
12
Rf_int
30k
2
Rf
Rg_int
30k
FB
3
DAC output pin.
Leave open if not used
RLmin
= 4k7
for OTP
programming and
alignment mode
only. Leave open
or connect to VSS
if not used
NC NC
5
13
NC
Rg
11
OP-Amp feedback pin.
Leave open if not used.
VSS
7
14
Test pins.
Leave open
CL
<100pF
1=int
Gain = 2x (int)
CSn CLK DO
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DSP
0
1
0
1
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OR1
360°
180°
90°
45°
1-10µF
VDD5V / 2
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0
0
1
1
VDD
Connect pins 15 and
16 for VDD= 3.0-3.6V.
Do NOT connect for
VDD = 4.5-5.5V !
VDD5V
DACref
Mode
MagRngn
1
9
2
3
VSS
VDD
Vout
0
360°angle
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12.2.1 Angular Range Selector
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The Angular Range selector allows a digital pre-selection of the angular range. The AS5043 can be configured for a full
scale angular range of 45°, 90°, 180° or 360°. In addition, the Output voltage versus angle response can be fine-tuned by
setting the gain of the OP-AMP with external resistors and the maximum output voltage can be set in the DAC.
The combination of these options allows to configure the operation range of the AS5043 for all angles up to 360° and
output voltages up to 5.5V.
The response curve for the analog output is linear for the selected range (45°/90°/180°/360°). In addition, the slope is
mirrored at 180° for 45°- and 90°- modes and has a step response at 270° for the 180°-mode. This allows the AS5043 to
be used in a variety of applications. In these three modes, the output remains at Vout,max and Vout,min to avoid a sudden
output change when the mechanical angle is rotated beyond the selected analog range. In 360°-mode, a jitter between
Vout,max and Vout,min at the 360° point is also prevented due to a hysteresis.
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AS5043
Data Sheet – Programming the AS5043
Table 5: Digital Range Selector Programming Option
Output
Output
Range1
Range0
Mode
Note
3 6 0 ° a n g u la r ra n g e (d e fa u lt)
1023
analog resolution= 10bit
(1024 steps) over 360°
0
0
0
0°
512
180°
256
90°
768
270°
1 0 2 4 a n g le *)
360°
analog step size:
1LSB = 0.35°
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0
default mode,
1 8 0 ° a n g u la r ra n g e
1023
0
1
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analog resolution= 10bit
(1024 steps) over 180°
Analog step size:
0
0°
256
90°
512
180°
768
270°
1024
360°
a n g le
1LSB = 0.175°
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0
9 0 ° a n g u la r ra n g e
1023
1
analog resolution= 10bit
(1024 steps) over 90°
0
0
0
0°
256
90°
512
180°
768
270°
1024
360°
a n g le
Analog step size:
1LSB = 0.088°
4 5 ° a n g u la r ra n g e
511
analog resolution=
1
9 bit (512 steps) over 45°
1
0 128 256
0° 45° 90°
512
180°
640
225°
1024
360°
a n g le
Analog step size:
1LSB = 0.088°
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0
*) Note: the resolution on the digital SSI interface is always 10bit (0.35°/step) over 360°, independent on analog mode
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12.3 Repeated OTP Programming
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Although a single AS5043 OTP register bit can be programmed only once (from 0 to 1), it is possible to program other,
unprogrammed bits in subsequent programming cycles. However, a bit that has already been programmed should not be
programmed twice. Therefore it is recommended that bits that are already programmed are set to “0” during a
programming cycle.
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12.4 Non-permanent Programming
It is also possible to re-configure the AS5043 in a non-permanent way by overwriting the OTP register.
This procedure is essentially a “Write Data” sequence (see Figure 10) without a subsequent OTP programming cycle.
The “Write Data” sequence may be applied at any time during normal operation. This configuration remains set while the
power supply voltage is above the power-on reset level (see 19.5).
See Application Note AN5000-20 for further information.
12.5 Digital-to-Analog Converter (DAC)
The DAC has a resolution of 10bit (1024 steps) and can be configured for the following options.
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AS5043
Data Sheet – Programming the AS5043
Internal or external reference
The default DAC reference is the voltage at pin #16 (VDD5V) divided by 2 (see Figure 13). Using this reference, a system
that has an output voltage ratiometric to the supply voltage can be built.
Optionally, an external reference source, applied at pin#9 (DACref) can be used. This programming option is useful for
applications requiring a precise output voltage that is independent of supply fluctuations, for current sink outputs or for
applications with a dynamic reference, e.g. attenuation of audio signals.
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0-100% or 10-90% full scale range
The reference voltage for the DAC is buffered internally. The recommended range for the external reference voltage is
0.2V to (VDD3V3 -0.2)V.
The DAC output voltage will be switched to 0V, when the magnetic field is out of range, when the MagInc and MagDec
indicators are both =1 and the MagRngn-pin (#1) will go low.
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The default full scale output voltage range is 0-100%*VDD5V. Due to limitations in the output stage of an OP-Amp buffer,
it cannot drive the output voltage from 0-100% rail-to-rail. Without load, the minimum output voltage at 0° will be a few
millivolts higher than 0V and the maximum output voltage will be slightly lower than VDD5V. With increasing load, the
voltage drops will increase accordingly.
As a programming option, an output range of 10-90%*VDD5V can be selected. In this mode, there is no saturation at the
upper and lower output voltage limits like in the 0-100% mode and it allows failure detection as the output voltage will be
outside the 10-90% limits, when the magnetic field is in the “red” range (Vout=0V, see Table 3) or when the supply to the
chip is interrupted (Vout=0V or VDD5V).
The unbuffered output of the DAC is accessible at pin #10 (DACout). This output must not be loaded.
12.6 OP-AMP Stage
The DAC output is buffered by a non-inverting Op-Amp stage. The amplifier is supplied by VDD5V (pin #16) and can
hence provide output voltages up to 5V.
By allowing access to the inverting input of the Op-Amp and with the addition of a few discrete components it can be
configured in many ways, like high current buffer, current sink output, adjustable angle range, etc...
Per default, the gain of the Op-Amp must be set by two external resistors (see Figure 13). Optionally, the fixed internal
gain setting (2x) may be programmed by OTP, eliminating the need for external resistors.
12.6.1 Output Noise
Vnoise ,Vout =
TN ∗ VDD 5V
+ Vnoise ,OPAMP
360
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where:
Vnoise, Vout
TN
VDD5V
Vnoise,OPAMP
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The Noise level at the analog output depends on two states of the digital angular output:
a) the digital angular output value is stable
In this case, the output noise is the figure given as Vnoise in paragraph 19.3.6. Note that the noise level is given
for the default gain of 2x For other gains, it must be scaled accordingly.
b) the digital output is at the edge of a step
In this case, the digital output may jitter between two adjacent values. The rate of jitter is specified as transition
noise (parameter TN in paragraph 19.5). The resulting output noise is calculated by:
= noise level at pin Vout in Vrms
= transition noise (in °rms; see 19.5)
= Supply voltage VDD5V in V
= noise level of OPAMP
(paragraph 19.3.6) in Vrms
12.7 Application Examples
See Application Note AN5043-10 for AS5043 Application Examples.
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AS5043
Data Sheet – Analog Readback Mode
13 Analog Readback Mode
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Non-volatile programming (OTP) uses on-chip zener diodes, which become permanently low resistive when subjected to
a specified reverse current.
The quality of the programming process depends on the amount of current that is applied during the programming
process (up to 130mA). This current must be provided by an external voltage source. If this voltage source cannot
provide adequate power, the zener diodes may not be programmed properly.
In order to verify the quality of the programmed bits, an analog level can be read for each zener diode, giving an
indication whether this particular bit was properly programmed or not.
To put the AS5043 in Analog Readback Mode, a digital sequence must be applied to pins CSn, PROG and CLK as
shown in Figure 15. The digital level for this pin depends on the supply configuration (3.3V or 5V; see section 1, page 5).
The second rising edge on CSn (OutpEN) changes pin PROG to a digital output and the log. high signal at pin PROG
must be removed to avoid collision of outputs (grey area in Figure 15).
The following falling slope of CSn changes pin PROG to an analog output, providing a reference voltage Vref, that must be
saved as a reference for the calculation of the subsequent programmed and unprogrammed OTP bits.
Following this step, each rising slope of CLK outputs one bit of data in the reverse order as during programming.
(see Figure 15: Output Range OR0 and -1 , ClampMdEn, RefExtEn, FB_IntEn, Z0…Z9, ccw)
During analog readback, the capacitor at pin PROG (see Figure 12) should be removed to allow a fast readout rate.
The measured analog voltage for each bit must be subtracted from the previously measured Vref, and the resulting value
gives an indication on the quality of the programmed bit: a reading of <100mV indicates a properly programmed bit and a
reading of >1V indicates a properly unprogrammed bit.
A reading between 100mV and 1V indicates a faulty bit, which may result in an undefined digital value, when the OTP is
read at power-up.
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Following the 16 clock (after reading bit “ccw”), the chip must be reset by disconnecting the power supply.
Figure 15: Analog OTP Register Read
P ro g E N
O u tpE N
CSn
In te rn al
te st bit
dig it al
PROG
P o w e r-o n R e s e t;
c yc le su p ply
A n a log R e a d b a ck D ata a t P R O G
V re f
V p ro gra m m ed
O R0 O R1
C la m p R ef E xt
M dEN
EN
V u n p rog ram m e d Z 5
Z6
Z7
Z8
Z9
c cw
P rog ch an g es t o O u tp u t
1
CLK
t L oa d P ro g
16
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C L K A re ad
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AS5043
Data Sheet – Alignment Mode
14 Alignment Mode
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The alignment mode simplifies centering the magnet over the chip to gain maximum accuracy and XY-alignment
tolerance.
This electrical centering method allows a wider XY-alignment tolerance (0.485mm radius) than mechanical centering
(0.25mm radius) as it eliminates the placement tolerance of the die within the IC package (+/- 0.235mm).
Alignment mode can be enabled with the falling edge of CSn while PROG = logic high (Figure 15). The Data bits D9-D0
of the SSI change to a 10-bit displacement amplitude output. A high value indicates large X or Y displacement, but also
higher absolute magnetic field strength. The magnet is properly aligned, when the difference between highest and lowest
value over one full turn is at a minimum.
Under normal conditions, a properly aligned magnet will result in a reading of less than 32 over a full turn.
Stronger magnets or short gaps between magnet and IC may show values larger than 32. These magnets are still
properly aligned as long as the difference between highest and lowest value over one full turn is at a minimum.
The MagInc and MagDec indicators will be = 1 when the alignment mode reading is < 32. At the same time, hardware pin
MagRngn (#1) will be pulled to VSS.
The Alignment mode can be reset to normal operation mode by a power-on-reset (cycle power supply) or by a falling
edge of CSn with PROG=low (see Figure 16).
Figure 17: Exiting Alignment Mode
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Figure 16: Enabling the Alignment Mode
PROG
PROG
AlignMode enable
CSn
CSn
exit AlignMode
Read-out
via SSI
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2µs 2µs
min. min.
Read-out
via SSI
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Revision 1.80
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AS5043
Data Sheet – Choosing the Proper Magnet
15 Choosing the Proper Magnet
Typically the magnet should be 6mm in diameter and ≥2.5mm in height. Magnetic materials such as rare earth AlNiCo,
SmCo5 or NdFeB are recommended.
The magnet’s field strength perpendicular to the die surface should be verified using a gauss-meter. The magnetic field
Bv at a given distance, along a concentric circle with a radius of 1.1mm (R1), should be in the range of ±45mT…±75mT.
(see Figure 18).
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Figure 18: Typical Magnet and Magnetic Field Distribution
N
S
Vertical field
component
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Magnet axis
Magnet axis
R1
Vertical field
component
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typ. 6mm diameter
Bv
(45…75mT)
0
360
360
N
S
R1 concentric circle;
radius 1.1mm
15.1 Physical Placement of the Magnet
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The best linearity can be achieved by placing the center of the magnet exactly over the defined center of the IC package
as shown in Figure 19.
Figure 19: Defined IC Center and Magnet Displacement Radius
3.9 mm
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3.9 mm
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1
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2.433 mm
Defined
center
Rd
2.433 mm
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Area of recommended maximum
magnet misalignment
Revision 1.80
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AS5043
Data Sheet – Choosing the Proper Magnet
15.1.1 Magnet Placement
Figure 20: Vertical Placement of the Magnet
N
Package surface
z
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Die surface
S
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The magnet’s center axis should be aligned within a displacement radius Rd of 0.25mm from the defined center of the IC
with reference to the edge of pin #1 (see Figure 19). This radius includes the placement tolerance of the chip within the
SSOP-16 package (+/- 0.235mm).
The displacement radius Rd is 0.485mm with reference to the center of the chip (see section Alignment Mode).
The vertical distance should be chosen such that the magnetic field on the die surface is within the specified limits (see
Figure 18). The typical distance “z” between the magnet and the package surface is 0.5mm to 1.8mm with the
recommended magnet (6mm x 3mm). Larger gaps are possible, as long as the required magnetic field strength stays
within the defined limits.
A magnetic field outside the specified range may still produce usable results, but the out-of-range condition will be
indicated by MagRngn (pin 1), which will be pulled low. At this condition, the angular data is still available over the digital
serial interface (SSI), but the analog output will be turned off.
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0.576mm ± 0.1mm
1.282mm ± 0.15mm
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21 – 36
AS5043
Data Sheet – Simulation Modelling
16 Simulation Modelling
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Figure 21: Arrangement of Hall Sensor Array on Chip (principle)
With reference to Figure 21, a diametrically magnetized permanent magnet is placed above or below the surface of the
AS5043. The chip uses an array of Hall sensors to sample the vertical vector of a magnetic field distributed across the
device package surface. The area of magnetic sensitivity is a circular locus of 1.1mm radius with respect to the center of
the die. The Hall sensors in the area of magnetic sensitivity are grouped and configured such that orthogonally related
components of the magnetic fields are sampled differentially.
The differential signal Y1-Y2 will give a sine vector of the magnetic field. The differential signal X1-X2 will give an
orthogonally related cosine vector of the magnetic field.
The angular displacement (Θ) of the magnetic source with reference to the Hall sensor array may then be modelled by:
Θ = arctan
(Y 1 − Y 2) ± 0.5°
( X 1 − X 2)
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The ±0.5° angular error assumes a magnet optimally aligned over the center of the die and is a result of gain mismatch
errors of the AS5043. Placement tolerances of the die within the package are ±0.235mm in X and Y direction, using a
reference point of the edge of pin #1 (Figure 21).
In order to neglect the influence of external disturbing magnetic fields, a robust differential sampling and ratiometric
calculation algorithm has been implemented. The differential sampling of the sine and cosine vectors removes any
common mode error due to DC components introduced by the magnetic source itself or external disturbing magnetic
fields. A ratiometric division of the sine and cosine vectors removes the need for an accurate absolute magnitude of the
magnetic field and thus accurate Z-axis alignment of the magnetic source.
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The recommended differential input range of the magnetic field strength (B(X1-X2),B(Y1-Y2)) is ±75mT at the surface of the
die. In addition to this range, an additional offset of ±5mT, caused by unwanted external stray fields is allowed.
The chip will continue to operate, but with degraded output linearity, if the signal field strength is outside the
recommended range. Too strong magnetic fields will introduce errors due to saturation effects in the internal
preamplifiers. Too weak magnetic fields will introduce errors due to noise becoming more dominant.
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AS5043
Data Sheet – Failure Diagnostics
17 Failure Diagnostics
The AS5043 also offers several diagnostic and failure detection features:
17.1 Magnetic Field Strength Diagnosis
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By software: the MagInc and MagDec status bits will both be high when the magnetic field is out of range.
By hardware: Pin #1 (MagRngn) is a logical NAND-ed combination of the MagInc and MagDec status bits. It is an opendrain output and will be turned on (= low with external pull-up resistor) when the magnetic field is out of range.
By hardware: Pin #12 (Vout) is the analog output of the DAC and OP-Amp. The analog output will be 0V, when the
magnetic field is out of range (all analog modes).
17.2 Power Supply Failure Detection
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By software: If the power supply to the AS5043 is interrupted, the digital data read by the SSI will be all “0”s. Data is only
valid, when bit OCF is high, hence a data stream with all “0”s is invalid. To ensure adequate low levels in the failure case,
a pull-down resistor (~10kΩ) should be added between pin DO and VSS at the receiving side
By hardware: The MagRngn pin is an open drain output and requires an external pull-up resistor. In normal operation,
this pin is high ohmic and the output is high. In a failure case, either when the magnetic field is out of range or the power
supply is missing, this output will become low. To ensure an adequate low level in case of a broken power supply to the
AS5043, the pull-up resistor (~10kΩ) must be connected to the positive supply at pin 16 (VDD5V).
.
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AS5043
Data Sheet – Angular Output Tolerances
18 Angular Output Tolerances
18.1 Accuracy; Digital Outputs
Accuracy is defined as the error between measured angle and actual angle. It is influenced by several factors:
ƒ
the non-linearity of the analog-digital converters,
ƒ
internal gain and mismatch errors,
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ƒ
non-linearity due to misalignment of the magnet
As a sum of all these errors, the accuracy with centered magnet = (Errmax – Errmin)/2 is specified as better than ±0.5
degrees @ 25°C (see Figure 23).
Misalignment of the magnet further reduces the accuracy. Figure 22 shows an example of a 3D-graph displaying nonlinearity over XY-misalignment. The center of the square XY-area corresponds to a centered magnet (see dot in the
center of the graph). The X- and Y- axis extends to a misalignment of ±1mm in both directions. The total misalignment
area of the graph covers a square of 2x2 mm (79x79mil) with a step size of 100µm.
For each misalignment step, the measurement as shown in Figure 23 is repeated and the accuracy
(Errmax – Errmin)/2 (e.g. 0.25° in Figure 23) is entered as the Z-axis in the 3D-graph.
18.2 Accuracy; Analog Output
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The analog output has the same accuracy as the digital output with the addition of the nonlinearities of the DAC and the
OPAMP (+/-1LSB; see Table 5 and 0).
Figure 22: Example of Linearity Error over XY Misalignment
Linearity Error over XY-misalignment [°]
6
5
4
°
3
800
500
2
200
1
-100
-800
-1000
-1000
-400
0
-600
y
-700
-200
200
600
400
1000
x
-400
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800
0
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The maximum non-linearity error on this example is better than ±1 degree (inner circle) over a misalignment radius of
~0.7mm. For volume production, the placement tolerance of the IC within the package (±0.235mm) must also be taken
into account.
The total nonlinearity error over process tolerances, temperature and a misalignment circle radius of 0.25mm is specified
better than ±1.4 degrees.
The magnet used for this measurement was a cylindrical NdFeB (Bomatec® BMN-35H) magnet with 6mm diameter and
2.5mm in height.
www.austriamicrosystems.com
Revision 1.80
24 – 36
AS5043
Data Sheet – Angular Output Tolerances
Figure 23: Example of Linearity Error over 360°
Linearity Error with Centered Magnet [degrees]
0.5
0.4
0.3
0.2
Err max
0
-0.1
1
55
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id
transition noise
0.1
109 163 217 271 325 379 433 487 541 595 649 703 757 811 865 919 973
Err min
-0.2
lv
-0.3
-0.4
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-0.5
18.3 Transition Noise
ca
Transition noise is defined as the jitter in the transition between two steps.
Due to the nature of the measurement principle (Hall sensors + Preamplifier + ADC), there is always a certain degree of
noise involved.
This transition noise voltage results in an angular transition noise at the outputs. It is specified as 0.06 degrees rms
*1
*1
(1 sigma) in fast mode (pin MODE = high) and 0.03 degrees rms (1 sigma) in slow mode (pin MODE = low or open).
These values are the repeatability of an indicated angle at a given mechanical position.
The transition noise has different implications on the type of output that is used:
ƒ
absolute output; SSI interface:
The transition noise of the absolute output can be reduced by the user by applying an averaging of readings. An
averaging of 4 readings will reduce the transition noise by 6dB or 50%, e.g. from 0.03°rms to 0.015°rms (1
sigma) in slow mode
ƒ
analog output:
Ideally, the analog output should have a jitter that is less than one digit. In 360° mode, both fast or slow mode
may be selected for adequate low jitter.
In 180°, 90° or 45° mode, where the step sizes are smaller, slow mode should be selected to reduce the output
jitter.
*1
ni
: statistically, 1 sigma represents 68.27% of readings,
3 sigma represents 99.73% of readings.
18.4 High Speed Operation
ch
18.4.1 Sampling Rate
Te
The AS5043 samples the angular value at a rate of 10.42k samples per second (ksps) in fast mode and 2.61ksps in slow
mode.
Consequently, a new reading is performed each 96µs. (fast mode) or 384µs (slow mode).
At a stationary position of the magnet, this sampling rate creates no additional error.
Absolute Mode:
With the given sampling rates, the number of samples (n) per turn for a magnet rotating at high speed can be calculated
by
n=
60
for fast mode
rpm ⋅ 96 μs
www.austriamicrosystems.com
Revision 1.80
25 – 36
AS5043
Data Sheet – Angular Output Tolerances
n=
60
for slow mode
rpm ⋅ 384 μs
In practice, there is no upper speed limit. The only restriction is that there will be fewer samples per revolution as the
speed increases.
Regardless of the rotational speed, the absolute angular value is always sampled at the highest resolution.
Fast Mode
(Pin Mode = 1)
Slow Mode
610rpm = 1024 samples / turn
610rpm = 256 samples / turn
1220rpm = 512 samples / turn
1220rpm = 128 samples / turn
2441rpm = 256 samples / turn
2441rpm = 64 samples / turn
etc…
etc…
lv
(Pin Mode = 0 or open)
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Table 6: Speed Performance
18.5 Output Delays
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The propagation delay is the delay between the time that the sample is taken until it is available as angular data. This
delay is 96µs in fast mode (pin Mode = high) and 384µs in slow mode (pin Mode = low or open).
The analog output produces no further delay, the output voltage will be updated as soon as it is available. Using the SSI
interface for data transmission, an additional delay must be considered, caused by the asynchronous sampling
(0….1/fsample) and the time it takes the external control unit to read and process the angular data from the AS5043.
18.5.1 Angular Error Caused by Propagation Delay
A rotating magnet will cause an angular error caused by the propagation delay.
This error increases linearly with speed:
e sampling (deg) = 6 ∗ rpm ∗ pr.delay
where
esampling = angular error [°]
rpm = rotating speed [rpm]
prop.delay = propagation delay [seconds]
ca
Note: since the propagation delay is known, it can be automatically compensated by the control unit processing the data
from the AS5043.
18.6 Internal Timing Tolerance
ni
The AS5043 does not require an external ceramic resonator or quartz. All internal clock timings for the AS5043 are
generated by an on-chip RC oscillator. This oscillator is factory trimmed to ±5% accuracy at room temperature (±10%
over full temperature range). This tolerance influences the ADC sampling rate:
ch
18.6.1 Absolute Output; SSI Interface
Te
A new angular value is updated every
96µs +/- 5% (Mode = 1) or
384µs +/- 5% (Mode = 0 or open)
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Revision 1.80
26 – 36
AS5043
Data Sheet – Angular Output Tolerances
18.7 Temperature
18.7.1 Magnetic Temperature Coefficient
One of the major benefits of the AS5043 compared to linear Hall sensors is that it is much less sensitive to temperature.
While linear Hall sensors require a compensation of the magnet’s temperature coefficients, the AS5043 automatically
compensates for the varying magnetic field strength over temperature. The magnet’s temperature drift does not need to
be considered, as the AS5043 operates with magnetic field strengths from ±45…±75mT.
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Example:
A NdFeB magnet has a field strength of 75mT @ –40°C and a temperature coefficient of -0.12% per Kelvin. The
temperature change is from –40° to +125° = 165K.
The magnetic field change is: 165 x -0.12% = -19.8%, which corresponds to 75mT at –40°C and 60mT at 125°C .
The AS5043 can compensate for this temperature related field strength change automatically, no user adjustment is
required.
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18.7.2 Accuracy over Temperature
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The influence of temperature in the absolute accuracy is very low. While the accuracy is ≤ ±0.5° at room temperature, it
may increase to ≤±0.9° due to increasing noise at high temperatures.
18.7.3 Timing Tolerance over Temperature
Te
ch
ni
ca
The internal RC oscillator is factory trimmed to ±5%. Over temperature, this tolerance may increase to ±10%. Generally,
the timing tolerance has no influence in the accuracy or resolution of the system, as it is used mainly for internal clock
generation.
www.austriamicrosystems.com
Revision 1.80
27 – 36
AS5043
Data Sheet – Electrical Characteristics
19 Electrical Characteristics
19.1 Absolute Maximum Ratings (non operating)
Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under
“Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Min
Max
Unit
VDD5V
-0.3
7
V
Pin VDD5V
5
V
Pin VDD3V3
VDD3V3
Input pin voltage
Vin
Input current (latchup immunity)
Storage temperature
Pins MagRngn, Mode, CSn, CLK, DO,
DACout, FB, Vout
-0.3
VDD5V +0.3
-0.3
5
-0.3
7.5
-100
100
mA
Norm: JEDEC 78
±2
kV
Norm: MIL 883 E method 3015
125
°C
Min – 67°F ; Max +257°F
260
°C
t=20 to 40s, Norm: IPC/JEDEC
J-Std-020C
Lead finish 100% Sn “matte tin”
85
%
ESD
V
Pin DACref
Pin PROG_DI
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Electrostatic discharge
Iscr
Note
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DC supply voltage
Symbol
lv
Parameter
Tstrg
Body temperature (Lead-free
package)
-55
TBody
Humidity non-condensing
H
5
19.2 Operating Conditions
Parameter
Symbol Min Typ Max Unit Note
Ambient temperature
Tamb
Supply current
-40
Isupp
Supply voltage at pin VDD5V
°C
16
21
mA
Voltage regulator output voltage at pin
VDD3V3
4.5
5.0
5.5
V
VDD3V3 3.0
3.3
3.6
V
Supply voltage at pin VDD5V
VDD5V
3.0
3.3
3.6
V
Supply voltage at pin VDD3V3
VDD3V3 3.0
3.3
3.6
V
ca
VDD5V
125
-40°F…+257°F
5V Operation
3.3V Operation
(pin VDD5V and VDD3V3 connected)
ni
19.3 DC Characteristics for Digital Inputs and Outputs
19.3.1 CMOS Schmitt-Trigger Inputs: CLK, CSn (internal Pull-up), Mode (internal Pull-down)
ch
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted)
Symbol
Min
High level input voltage
VIH
0.7 * VDD5V
Low level input voltage
VIL
Te
Parameter
Schmitt Trigger hysteresis
Max
V
0.3 * VDD5V
VIon- VIoff
1
ILEAK
-1
1
Pull-up low level input current
IiL
-30
-100
Pull-down high level input current
IiH
30
100
Input leakage current
www.austriamicrosystems.com
Revision 1.80
Unit
Note
Normal operation
V
V
Pin CLK, VDD5V = 5.0V
µA
Pin CSn, VDD5V= 5.0V
Pin Mode, VDD5V= 5.0V
28 – 36
AS5043
Data Sheet – Electrical Characteristics
19.3.2 CMOS Input: Program Input (Prog)
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless
otherwise noted)
Symbol
Min
Max
Unit
High level input voltage
VIH
0.7 * VDD5V
5
V
High level input voltage
VPROG
Low level input voltage
VIL
0.3 * VDD5V
V
Pull-down high level input current
IiL
100
µA
See “programming
conditions”
V
Note
During programming
VDD5V: 5.5V
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Parameter
19.3.3 CMOS Output Open Drain: MagRngn
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless
otherwise noted)
Symbol
Output current
Max
Unit
VOL
VSS+0.4
V
IO
4
2
mA
IOZ
1
µA
Note
VDD5V: 4.5V
VDD5V: 3V
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Low level output voltage
Min
lv
Parameter
Open drain leakage current
19.3.4 Tristate CMOS Output: DO
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted)
Parameter
Symbol
Min
High level output voltage
VOH
VDD5V –0.5
Low level output voltage
VOL
VSS+0.4
V
IO
4
2
mA
mA
IOZ
1
µA
Output current
Tri-state leakage current
Max
Unit
Note
V
VDD5V: 4.5V
VDD5V: 3V
19.3.5 Digital-to-Analog Converter
Parameter
Symbol
Typ
Max
0……100% Vref (default)
ClampMdEn = 0
(default)
10…..90% Vref
ClampMdEn = 1
Vref
VOUTM2
0.10 *Vref
0.90 *Vref
V
8
kΩ
Unbuffered Pin DACout (#10)
VDD3V3 - 0.2
V
DAC reference = external:
Pin: DACref (#9)
RefExt EN = 1
VDD5V / 2
V
DAC reference = internal
RefExtEn = 0
(default)
ROut,DAC
DAC reference
voltage (DAC full
scale range)
Te
V
0
ch
Output resistance
OTP Setting
VOUTM1
ni
Output range
Unit Note
bit
10
ca
Resolution
Min
0.2
Vref
Integral nonlinearity
INLDAC
+/- 1.5
Differential nonlinearity
DNLDAC
+/- 0.5
Analog output
hysteresis
www.austriamicrosystems.com
Hyst
LSB Non-Linearity of DAC and
OPAMP; -40….+125°C,
for all analog modes:
LSB 1LSB = Vref / 1024
1
LSB All analog modes
2
LSB
Revision 1.80
At 360°-0° transition,
360° mode only
OR1,OR0 = 00
(default)
29 – 36
AS5043
Data Sheet – Electrical Characteristics
19.3.6 OPAMP Output Stage
Min
VDD5V
3.0
CL
RL
4.7
A0
92
VosOP
-5
Open Loop Gain
Offset Voltage RTI
Typ
Max
Unit
5.5
V
100
pF
kΩ
130
144
dB
5
mV
0.05 *
VDD5V
V
Output Range Low
VoutL
Output Range High
VoutH
0.95 *
VDD5V
Isink
4.8
50
Isource
4.6
66
Vnoise
160
Current capability sink
Current capability source
3.3V operation
3 sigma
Linear range of analog output
V
220
490
Permanent short circuit current:
Vout to VDD5V
Permanent short circuit current:
mA
Vout to VSS
Over full temperature range;
µVrms
BW= 1Hz…10MHz,Gain = 2x
Internal; OTP: FB_int EN = 1
External OTP: FB_int EN = 0
(default)
With external resistors, pins Vout
[#12] and FB [#11]: see Figure 14
mA
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Output noise
Note
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Power Supply Range
Parallel Load
Capacitance
Parallel Load Resistance
Symbol
lv
Parameter
2
OPAMP gain (noninverting)
Gain
1
4
19.4 Magnetic Input Specification
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless
otherwise noted)
Two-pole cylindrical diametrically magnetised source:
Parameter
Diameter
Thickness
Symbol
Min
Typ
dmag
4
6
tmag
2.5
Bpk
45
Max
Unit
Note
mm
Recommended magnet: Ø 6mm x 2.5mm for
cylindrical magnets
mm
mT
Required vertical component of the magnetic
field strength on the die’s surface, measured
along a concentric circle with a radius of 1.1mm
± 10
mT
Constant magnetic stray field
5
%
Including offset gradient
fmag_abs
10
Hz
Absolute mode: 600 rpm @ readout of 1024
positions (see table 6)
(rotational speed of
magnet)
fmag_inc
166
Hz
Incremental mode: no missing pulses at
rotational speeds of up to 10,000 rpm (see
table 6)
Displacement radius
Disp
0.25
mm
Max. offset between defined device center and
magnet axis
Magnetic offset
Boff
ni
Field non-linearity
ca
75
Magnetic input field
amplitude
Te
ch
Input frequency
Recommended magnet
material and
temperature drift
www.austriamicrosystems.com
-0.12
-0.035
Revision 1.80
NdFeB (Neodymium Iron Boron)
%/K
SmCo (Samarium Cobalt)
30 – 36
AS5043
Data Sheet – Electrical Characteristics
19.5 Electrical System Specifications
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation)
unless otherwise noted)
Parameter
Symbol
*
Min
Typ
Max
Unit
Note
RES
10
bit
0.352 deg
Integral non-linearity
(optimum) *
INLopt
± 0.5
deg
Maximum error with respect to the best line
fit. Verified at optimum magnet placement,
Tamb =25 °C.
Integral non-linearity
(optimum) *
INLtemp
± 0.9
deg
Maximum error with respect to the best line
fit. Verified at optimum magnet placement ,
Tamb = -40 to +125°C
Integral non-linearity*
INL
± 1.4
deg
Over displacement tolerance with 6mm
diameter magnet, Tamb = -40 to +125°C
Differential non-linearity*
DNL
±
0.176
deg
10bit, no missing codes
1 sigma, fast mode (pin MODE = 1)
0.03
Deg
RMS
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Resolution
Transition noise*
0.06
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TN
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Best line fit = (Errmax – Errmin) / 2
1 sigma, slow mode (pin MODE=0 or open)
Power-on reset thresholds
On voltage; 300mV typ.
hysteresis
Off voltage; 300mV typ.
hysteresis
Power-up time,
Von
1,37
2.2
2.9
V
Voff
1.08
1.9
2.6
V
20
Until offset compensation
finished, OCF = 1, Angular
Data valid
384
2.74
2.35
2.61
2.87
9.90
10.42
10.94
9.38
10.42
fS,mode0
ni
fS,mode1
CLK
>0
fast mode (pin MODE=1)
µs
kHz
Tamb = 25°C, slow mode (pin MODE=0 or
open)
Tamb = -40 to +125°C, slow mode (pin
MODE=0 or open)
Tamb = 25°C, fast mode (pin MODE = 1)
kHz
Tamb = -40 to +125°C, : fast mode
(pin MODE = 1)
MHz
Max. clock frequency to read out serial data
11.46
1
slow mode (pin MODE=0 or open)
ch
Read-out frequency
slow mode (pin MODE=0 or open)
96
tdelay
2.61
Internal sampling rate for
absolute output
fast mode (pin MODE=1)
80
2.48
Internal sampling rate for
absolute output:
DC supply voltage 3.3V (VDD3V3)
ms
tPwrUp
ca
System propagation delay
absolute output : delay of
ADC and DSP
DC supply voltage 3.3V (VDD3V3)
Te
*) digital interface
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Revision 1.80
31 – 36
AS5043
Data Sheet – Electrical Characteristics
Figure 24: Integral and Differential Non-Linearity (exaggerated curve)
α 10bit code
1023
1023
Actual curve
TN
2
DNL+1LSB
1
Ideal curve
512
0
360 °
180°
α [degrees]
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0°
lv
512
al
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INL
0.35°
0
Integral Non-Linearity (INL) is the maximum deviation between actual position and indicated position.
Differential Non-Linearity (DNL) is the maximum deviation of the step length from one position to the next.
Transition Noise (TN) is the repeatability of an indicated position.
19.6 Timing Characteristics
Synchronous Serial Interface (SSI)
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless
otherwise noted)
Parameter
Symbol
Data output activated
(logic high)
Min
Typ
t DO active
Max
Unit
Note
100
ns
Time between falling edge of CSn and data
output activated
First data shifted to output
register
tCLK FE
500
ns
Time between falling edge of CSn and first
falling edge of CLK
Start of data output
T CLK / 2
500
ns
Rising edge of CLK shifts out one bit at a time
Data output tristate
413
ns
Time between rising edge of CLK and data
output valid
t DO tristate
100
ns
After the last bit DO changes back to “tristate”
ns
CSn = high; To initiate read-out of next
angular position
MHz
Clock frequency to read out serial data
t CSn
500
fCLK
>0
ni
Pulse width of CSn
t DO valid
ca
Data output valid
1
ch
Read-out frequency
19.7 Programming Conditions
Te
(operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless
otherwise noted)
Parameter
Symbol
Min
Programming enable time
t Prog enable
2
µs
Write data start
t Data in
2
µs
Write data valid
t Data in valid
250
ns
www.austriamicrosystems.com
Typ
Revision 1.80
Max
Unit Note
Time between rising edge at Prog
pin and rising edge of CSn
Write data at the rising edge of
CLKPROG
32 – 36
AS5043
Data Sheet – Electrical Characteristics
Parameter
Symbol
Min
Load programming data
t Load PROG
3
µs
t PrgR
0
µs
t PrgH
0
Hold time of VPROG after CLK
PROG
Write data – programming
CLK PROG
CLK pulse width
5
µs
250
kHz
2.2
µs
During programming; 16 clock
cycles
µs
Programmed data is available after
next power-on
7.5
V
Must be switched off after zapping
1
V
Line must be discharged to this
level
I PROG
130
mA
During programming
CLKAread
100
kHz
Analog readback mode
Vprogrammed
100
mV
CLK PROG
t PROG
1.8
t PROG finished
2
Programming voltage
V PROG
7.3
Programming voltage off level
V ProgOff
0
Hold time of Vprog after
programming
Programming current
2
7.4
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Analog read CLK
Unit Note
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PROG
Max
lv
Rise time of VPROG before CLK
Typ
Programmed zener voltage
(log.1)
Vunprogrammed
1
V
VRef-VPROG during analog readback
mode (see 13)
Te
ch
ni
ca
Unprogrammed zener voltage
(log. 0)
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Revision 1.80
33 – 36
AS5043
Data Sheet – Package Drawings and Markings
20 Package Drawings and Markings
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Figure 25: 16-Lead Shrink Small Outline Package SSOP-16
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AYWWIZZ
AS5043
Marking: AYWWIZZ
Dimensions
mm
inch
Symbol
Typ
Max
Min
Typ
Max
A
1.73
1.86
1.99
.068
.073
.078
A1
0.05
0.13
0.21
.002
.005
.008
A2
1.68
1.73
1.78
.066
.068
.070
b
0.25
0.315
0.38
.010
.012
.015
c
0.09
-
0.20
.004
-
.008
D
6.07
6.20
6.33
.239
.244
.249
E
7.65
7.8
7.9
.301
.307
.311
E1
5.2
5.3
5.38
.205
.209
.212
e
0.65
K
0°
-
L
0.63
0.75
ca
Min
.0256
0°
-
8°
0.95
.025
.030
.037
JEDEC Package Outline Standard:
MO - 150 AC
Thermal Resistance Rth(j-a):
typ. 151 K/W in still air, soldered on PCB
IC’s marked with a white dot or the letters
“ES” denote Engineering samples
ch
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8°
A: Pb-Free Identifier
Y: Last Digit of Manufacturing Year
WW: Manufacturing Week
I: Plant Identifier
ZZ: Traceability Code
21 Packing Options
Te
Delivery:
Tape and Reel (1 reel = 2000 devices)
Tubes (1 box = 100 tubes á 77 devices)
Order # AS5043ASSU
Order # AS5043ASST
www.austriamicrosystems.com
for delivery in tubes
for delivery in tape and reel
Revision 1.80
34 – 36
AS5043
Data Sheet – Recommended PCB Footprint
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22 Recommended PCB Footprint
Recommended Footprint Data
inch
0.355
0.242
0.018
0.025
0.197
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mm
9.02
6.16
0.46
0.65
5.01
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A
B
C
D
E
www.austriamicrosystems.com
Revision 1.80
35 – 36
AS5043
Data Sheet – Contact Information
Copyrights
Copyright © 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated,
stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
This product is protected by U.S. Patent No. 7,095,228.
Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in
its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the
information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore,
prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining
equipment are specifically not recommended without additional processing by austriamicrosystems AG for each
application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems
AG rendering of technical or other services.
Contact Information
Te
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
www.austriamicrosystems.com
Revision 1.80
36 – 36
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