S25FL512S - Spansion

S25FL512S - Spansion
S25FL512S
512 Mbit (64 Mbyte) MirrorBit® Flash Non-Volatile Memory
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface with Multi-I/O
Data Sheet
S25FL512S Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion®
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FL512S_00
Revision 09
Issue Date January 21, 2015
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Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S25FL512S
S25FL512S_00_09 January 21, 2015
S25FL512S
512 Mbit (64 Mbyte) MirrorBit® Flash Non-Volatile Memory
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface with Multi-I/O
Data Sheet
Features
 Density
 Security features
– 512 Mbits (64 Mbytes)
 Serial Peripheral Interface (SPI)
–
–
–
–
SPI Clock polarity and phase modes 0 and 3
Double Data Rate (DDR) option
Extended Addressing: 32-bit address
Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
 READ Commands
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or
erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
 Spansion® 65 nm MirrorBit Technology with Eclipse™
Architecture
 Core Supply Voltage: 2.7V to 3.6V
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
– AutoBoot - power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information.
 Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock systems
 Erase (0.5 to 0.65 Mbytes/s)
– Uniform 256-kbyte sectors
 Cycling Endurance
 I/O Supply Voltage: 1.65V to 3.6V
– SO16 and FBGA packages
 Temperature Range:
– Industrial (-40°C to +85°C)
– Automotive In-Cabin (-40°C to +105°C)
 Packages (all Pb-free)
– 16-lead SOIC (300 mil)
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options
– Known Good Die and Known Tested Die
– 100,000 Program-Erase Cycles on any sector typical
 Data Retention
– 20 Year Data Retention typical
Publication Number S25FL512S_00
Revision 09
Issue Date January 21, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
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Performance Summary
Table 1.1 Maximum Read Rates with the Same Core and I/O Voltage (VIO = VCC = 2.7V to 3.6V)
Clock Rate
(MHz)
Command
Mbytes/s
Read
50
6.25
Fast Read
133
16.6
Dual Read
104
26
Quad Read
104
52
Table 1.2 Maximum Read Rates with Lower I/O Voltage (VIO = 1.65V to 2.7V, VCC = 2.7V to 3.6V)
Clock Rate
(MHz)
Mbytes/s
Read
50
6.25
Fast Read
66
8.25
Dual Read
66
16.5
Quad Read
66
33
Command
Table 1.3 Maximum Read Rates DDR (VIO = VCC = 3V to 3.6V)
Clock Rate
(MHz)
Mbytes/s
Fast Read DDR
80
20
Dual Read DDR
80
40
Quad Read DDR
80
80
Command
Table 1.4 Typical Program and Erase Rates
Operation
kbytes/s
Page Programming (512-byte page buffer - Uniform Sector Option)
1500
256-kbyte Logical Sector Erase (Uniform Sector Option)
500
Table 1.5 Current Consumption
Operation
4
Current (mA)
Serial Read 50 MHz
16 (max)
Serial Read 133 MHz
33 (max)
Quad Read 104 MHz
61 (max)
Program
100 (max)
Erase
100 (max)
Standby
0.07 (typ)
S25FL512S
S25FL512S_00_09 January 21, 2015
Data
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Table of Contents
Features
1.
Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Migration Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
15
15
Hardware Interface
3.
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Input/Output Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Address and Data Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Chip Select (CS#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Serial Input (SI) / IO0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
Serial Output (SO) / IO1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
Write Protect (WP#) / IO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
Hold (HOLD#) / IO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Core Voltage Supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Versatile I/O Power Supply (VIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Supply and Signal Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Not Connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 Reserved for Future Use (RFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 Do Not Use (DNU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
17
17
18
18
18
18
19
19
19
19
19
20
20
4.
Signal Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
SPI Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Interface States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Configuration Register Effects on the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
27
32
32
5.
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Power-Up and Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
34
36
6.
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
SDR AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
DDR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
37
38
41
45
7.
Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
SOIC 16-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2
FAB024 24-Ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3
FAC024 24-Ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
50
52
Software Interface
8.
Address Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Flash Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3
ID-CFI Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4
JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) Space. . . . . . . . . . . . . . .
8.5
OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 21, 2015 S25FL512S_00_09
S25FL512S
54
54
54
54
55
55
57
5
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9.
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
Secure Silicon Region (OTP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Write Enable Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
Advanced Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
65
65
66
67
10.
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.1 Command Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.2 Identification Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.3 Register Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4 Read Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5 Program Flash Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.6 Erase Flash Array Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.7 One Time Program Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.8 Advanced Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.9 Reset Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.10 Embedded Algorithm Performance Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.
Software Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 Serial Flash Discoverable Parameters (SFDP) Address Map . . . . . . . . . . . . . . . . . . . . . . .
11.3 Device ID and Common Flash Interface (ID-CFI) Address Map . . . . . . . . . . . . . . . . . . . . .
11.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
119
120
123
138
141
Ordering Information
6
12.
Ordering Information FL512S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.
Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
14.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
S25FL512S
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Data
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Figures
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Figure 4.8
Figure 4.9
Figure 4.10
Figure 4.11
Figure 4.12
Figure 4.13
Figure 4.14
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Figure 6.15
Figure 6.16
Figure 7.1
Figure 7.2
Figure 7.3
Figure 8.1
Figure 9.1
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10
Figure 10.11
HOLD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Master and Memory Devices on the SPI Bus — Single Bit Data Path . . . . . . . . . . . . . .
Bus Master and Memory Devices on the SPI Bus — Dual Bit Data Path . . . . . . . . . . . . . . .
Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path . . . . . . . . . . . . . .
SPI SDR Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI DDR Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand Alone Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Bit Wide Input Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Bit Wide Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Bit Wide I/O Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Bit Wide I/O Command with Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad Output Command without Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR Fast Read with EHPLC = 00b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR Dual I/O Read with EHPLC = 01b and DLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR Quad I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveform Element Meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Low at the End of POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset High at the End of POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POR followed by Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Single Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Single Bit Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI SDR MIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WP# Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI DDR Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI DDR Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI DDR Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Lead SOIC Package, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-Ball BGA, 4 x 6 Ball Footprint (FAC024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Sector Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ_ID (90h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Identification (RDID 9Fh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Electronic Signature (RES ABh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . .
RSFDP Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Status Register-1 (RDSR1 05h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . .
Read Status Register-2 (RDSR2 07h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . .
Read Configuration Register (RDCR 35h) Command Sequence . . . . . . . . . . . . . . . . . . . . .
Read Bank Register (BRRD 16h) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Register Write (BRWR 17h) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BRAC (B9h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Registers (WRR 01h) Command Sequence – 8 data bits . . . . . . . . . . . . . . . . . . . . . .
January 21, 2015 S25FL512S_00_09
S25FL512S
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20
20
20
21
22
24
24
24
24
24
25
25
25
25
26
26
26
34
34
35
35
37
37
37
38
39
39
40
42
43
43
43
44
44
46
46
47
48
50
52
56
67
77
78
79
79
80
80
80
81
81
82
82
7
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Figure 10.12
Figure 10.13
Figure 10.14
Figure 10.15
Figure 10.16
Figure 10.17
Figure 10.18
Figure 10.19
Figure 10.20
Figure 10.21
Figure 10.22
Figure 10.23
Figure 10.24
Figure 10.25
Figure 10.26
Figure 10.27
Figure 10.28
Figure 10.29
Figure 10.30
Figure 10.31
Figure 10.32
Figure 10.33
Figure 10.34
Figure 10.35
Figure 10.36
Figure 10.37
Figure 10.38
Figure 10.39
Figure 10.40
Figure 10.41
Figure 10.42
Figure 10.43
Figure 10.44
Figure 10.45
Figure 10.46
Figure 10.47
Figure 10.48
Figure 10.49
Figure 10.50
Figure 10.51
Figure 10.52
Figure 10.53
Figure 10.54
Figure 10.55
Figure 10.56
Figure 10.57
Figure 10.58
8
S hee t
Write Registers (WRR 01h) Command Sequence – 16 data bits . . . . . . . . . . . . . . . . . . . . . 82
Write Enable (WREN 06h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Write Disable (WRDI 04h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Clear Status Register (CLSR 30h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
AutoBoot Sequence (CR1[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
AutoBoot Sequence (CR1[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
AutoBoot Register Read (ABRD 14h) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
AutoBoot Register Write (ABWR) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Program NVDLR (PNVDLR 43h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Write VDLR (WVDLR 4Ah) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
DLP Read (DLPRD 41h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Read Command Sequence (READ 03h or 13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Fast Read (FAST_READ 0Bh or 0Ch) Command Sequence with Read Latency . . . . . . . . . 90
Fast Read Command (FAST_READ 0Bh or 0Ch) Sequence without Read Latency . . . . . . 91
Dual Output Read Command Sequence (3-Byte Address, 3Bh [ExtAdd=0], LC=10b). . . . . 91
Dual Output Read Command Sequence
(4-Byte Address, 3Ch or 3Bh [ExtAdd=1, LC=10b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Dual Output Read Command Sequence
(4-Byte Address, 3Ch or 3Bh [ExtAdd=1, LC=11b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence with Read Latency . . . 93
Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence without Read Latency 93
Dual I/O Read Command Sequence (3-Byte Address, BBh [ExtAdd=0], HPLC=00b) . . . . . 94
Dual I/O Read Command Sequence (4-Byte Address, BBh [ExtAdd=1], HPLC=10b) . . . . . 95
Dual I/O Read Command Sequence
(4-Byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Continuous Dual I/O Read Command Sequence
(4-Byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Quad I/O Read Command Sequence (3-Byte Address, EBh [ExtAdd=0], LC=00b) . . . . . . . 96
Continuous Quad I/O Read Command Sequence (3-Byte Address), LC=00b . . . . . . . . . . . 97
Quad I/O Read Command Sequence
(4-Byte Address, ECh or EBh [ExtAdd=1], LC=00b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Continuous Quad I/O Read Command Sequence (4-Byte Address), LC=00b . . . . . . . . . . . 97
DDR Fast Read Initial Access (3-Byte Address, 0Dh [ExtAdd=0, EHPLC=11b]) . . . . . . . . . 99
Continuous DDR Fast Read Subsequent Access
(3-Byte Address [ExtAdd=0, EHPLC=11b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
DDR Fast Read Initial Access (4-Byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b). . . . 99
Continuous DDR Fast Read Subsequent Access
(4-Byte Address [ExtAdd=1], EHPLC=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
DDR Fast Read Subsequent Access (4-Byte Address, HPLC=01b) . . . . . . . . . . . . . . . . . . 100
DDR Dual I/O Read Initial Access
(4-Byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b) . . . . . . . . . . . . . . . . . . . . . . . . . .101
Continuous DDR Dual I/O Read Subsequent Access (4-Byte Address, EHPLC= 01b) . . . 101
DDR Dual I/O Read (4-Byte Address, BEh or BDh [ExtAdd=1], HPLC=00b) . . . . . . . . . . . 102
DDR Quad I/O Read Initial Access (3-Byte Address, EDh [ExtAdd=0], HPLC=11b). . . . . . 103
Continuous DDR Quad I/O Read Subsequent Access (3-Byte Address,HPLC=11b) . . . . . 104
DDR Quad I/O Read Initial Access
(4-Byte Address, EEh or EDh [ExtAdd=1], EHPLC=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Continuous DDR Quad I/O Read Subsequent Access (4-Byte Address, EHPLC=01b) . . . 104
Page Program (PP 02h or 4PP 12h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . 105
Quad 512-byte Page Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Program Suspend (PGSP 85h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.55 Program Resume (PGRS 8Ah) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . 107
Sector Erase (SE D8h or 4SE DCh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 108
Bulk Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Erase Suspend (ERSP 75h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Erase Resume (ERRS 7Ah) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
S25FL512S
S25FL512S_00_09 January 21, 2015
Data
Figure 10.59
Figure 10.60
Figure 10.61
Figure 10.62
Figure 10.63
Figure 10.64
Figure 10.65
Figure 10.66
Figure 10.67
Figure 10.68
Figure 10.69
Figure 10.70
Figure 10.71
Figure 10.72
Figure 10.73
Figure 10.74
She et
Page Program (OTPP 42h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read OTP (OTPR 4Bh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASPRD Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASPP (2Fh) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DYBRD Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DYBWR (E1h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPBRD (E2h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPBP (E3h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPB Erase (PPBE E4h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPB Lock Register Read Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPB Lock Bit Write (PLBWR A6h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .
Password Read (PASSRD E7h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Password Program (PASSP E8h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .
Password Unlock (PASSU E9h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Reset (RESET F0h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Bit (MBR FFh) Reset Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 21, 2015 S25FL512S_00_09
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111
112
112
112
113
113
114
114
115
115
115
116
116
117
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S hee t
Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Table 2.1
Table 3.1
Table 4.1
Table 5.1
Table 5.2
Table 5.3
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 7.1
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Table 8.8
Table 8.9
Table 8.10
Table 8.11
Table 8.12
Table 8.13
Table 8.14
Table 8.15
Table 8.16
Table 8.17
Table 8.18
Table 9.1
Table 9.2
Table 9.3
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
10
Maximum Read Rates with the Same Core and I/O Voltage (VIO = VCC = 2.7V to 3.6V) . . . . 4
Maximum Read Rates with Lower I/O Voltage (VIO = 1.65V to 2.7V, VCC = 2.7V to 3.6V) . . . 4
Maximum Read Rates DDR (VIO = VCC = 3V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Program and Erase Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
FL Generations Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interface States Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-Up / Power-Down Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hardware Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . 41
AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V) . . . . . . . . . . 42
AC Characteristics DDR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Model Specific Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
S25FL512S Sector and Memory Address Map, Uniform 256-kbyte Sectors. . . . . . . . . . . . . 54
OTP Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Status Register-1 (SR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Configuration Register (CR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Latency Codes for SDR High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Latency Codes for DDR High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Latency Codes for SDR Enhanced High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Latency Codes for DDR Enhanced High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Status Register-2 (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
AutoBoot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Bank Address Register (BAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ASP Register (ASPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Password Register (PASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PPB Lock Register (PPBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PPB Access Register (PPBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DYB Access Register (DYBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Non-Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Upper Array Start of Protection (TBPROT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Lower Array Start of Protection (TBPROT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Sector Protection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Bank Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
S25FL512S Command Set (sorted by function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Read_ID Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RES Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Block Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Commands Allowed During Program or Erase Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Program and Erase Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Program Suspend AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Erase Suspend AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
S25FL512S Instruction Set (sorted by instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SFDP Overview Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SFDP Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Manufacturer and Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
CFI System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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S25FL512S_00_09 January 21, 2015
Data
Table 11.7
Table 11.8
Table 11.9
Table 11.10
Table 11.11
Table 11.12
Table 11.13
Table 11.14
Table 11.15
Table 11.16
Table 11.17
Table 11.18
Table 11.19
Table 11.20
Table 11.21
Table 11.22
Table 11.23
Table 11.24
Table 11.25
Table 11.26
Table 11.27
Table 11.28
Table 11.29
Table 11.30
Table 11.31
Table 11.32
She et
Device Geometry Definition for 512-Mbit Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CFI Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Header . . . . . . . . . . . . . . . . . . . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 0 . . . . . . . . . . . . . . . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 80h Address Options . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing . . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) . . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - HPLC DDR . . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU . . . . . . . . . . . . . . . . .
CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B . . .
Status Register-1 (SR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register (CR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register-2 (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Address Register (BAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASP Register (ASPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Password Register (PASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPB Lock Register (PPBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPB Access Register (PPBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DYB Access Register (DYBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASP Register Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 21, 2015 S25FL512S_00_09
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124
125
126
126
126
127
127
127
128
130
131
133
134
134
138
139
139
139
140
140
140
140
140
141
141
141
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2. Overview
2.1
General Description
The Spansion S25FL512S device is a flash non-volatile memory product using:
 MirrorBit technology - that stores two data bits in each memory array transistor
 Eclipse architecture - that dramatically improves program and erase performance
 65 nm process lithography
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial
input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit
(Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition,
the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that
transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) to be
programmed in one operation, resulting in faster effective programming and erase than prior generation SPI
program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at
the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can
match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal
count dramatically.
The S25FL512S product offers high densities coupled with the flexibility and fast performance required by a
variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.
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Data
2.2
She et
Migration Notes
2.2.1
Features Comparison
The S25FL512S device is command set and footprint compatible with prior generation FL-K and FL-P
families.
Table 2.1 FL Generations Comparison
Parameter
Technology Node
FL-K
FL-P
FL-S
90 nm
90 nm
65 nm
Architecture
Floating Gate
MirrorBit
MirrorBit Eclipse
Release Date
In Production
In Production
In Production
Density
4 Mb - 128 Mb
32 Mb - 256 Mb
512 Mb
x1, x2, x4
x1, x2, x4
x1, x2, x4
2.7V - 3.6V / 1.65V - 3.6V VIO
Bus Width
Supply Voltage
2.7V - 3.6V
2.7V - 3.6V
6 MB/s (50 MHz)
5 MB/s (40 MHz)
6 MB/s (50 MHz)
Fast Read Speed (SDR)
13 MB/s (104 MHz)
13 MB/s (104 MHz)
17 MB/s (133 MHz)
Dual Read Speed (SDR)
26 MB/s (104 MHz)
20 MB/s (80 MHz)
26 MB/s (104 MHz)
Quad Read Speed (SDR)
52 MB/s (104 MHz)
40 MB/s (80 MHz)
52 MB/s (104 MHz)
Fast Read Speed (DDR)
-
-
20 MB/s (80 MHz)
Dual Read Speed (DDR)
-
-
40 MB/s (80 MHz)
Quad Read Speed (DDR)
-
-
80 MB/s (80 MHz)
Normal Read Speed (SDR)
Program Buffer Size
Erase Sector Size
256B
256B
512B
4 kB / 32 kB / 64 kB
64 kB / 256 kB
256 kB
Parameter Sector Size
Sector Erase Time (typ.)
Page Programming Time (typ.)
4 kB
4 kB
—
30 ms (4 kB), 150 ms (64 kB)
500 ms (64 kB)
520 ms (256 kB)
700 µs (256B)
1500 µs (256B)
340 µs (512B)
768B (3 x 256B)
506B
1024B
Advanced Sector Protection
No
No
Yes
Auto Boot Mode
No
No
Yes
OTP
Erase Suspend/Resume
Yes
No
Yes
Program Suspend/Resume
Yes
No
Yes
–40°C to +85°C
–40°C to +85°C / +105°C
–40°C to +85°C / +105°C
Operating Temperature
Notes:
1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
3. 64 kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. Refer to individual data sheets for further details.
2.2.2
2.2.2.1
Known Differences from Prior Generations
Error Reporting
Prior generation FL memories either do not have error status bits or do not set them if program or erase is
attempted on a protected sector. The FL-S family does have error reporting status bits for program and erase
operations. These can be set when there is an internal failure to program or erase or when there is an attempt
to program or erase a protected sector. In either case the program or erase operation did not complete as
requested by the command.
2.2.2.2
Secure Silicon Region (OTP)
The size and format (address map) of the One Time Program area is different from prior generations. The
method for protecting each portion of the OTP area is different. For additional details see Secure Silicon
Region (OTP) on page 65.
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S hee t
Configuration Register Freeze Bit
The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior
generations. In the FL-S family it also locks the state of the configuration register TBPARM bit CR1[2],
TBPROT bit CR1[5], and the Secure Silicon Region (OTP) area.
2.2.2.4
Sector Erase Commands
The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.
The command for erasing a 4-kbyte sector is not supported in the 512-Mbit density FL-S device.
The erase command for 64-kbyte sectors is not supported in the 512-Mbit density FL-S device.
2.2.2.5
Deep Power Down
The Deep Power Down (DPD) function is not supported in FL-S family devices.
The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can
issue the former DPD command, to access a new bank address register. The bank address register allows
SPI memory controllers that do not support more than 24 bits of address, the ability to provide higher order
address bits for commands, as needed to access the larger address space of the 256-Mbit density FL-S
device. For additional information see Extended Address on page 54.
2.2.2.6
New Features
The FL-S family introduces several new features to SPI category memories:
 Extended address for access to higher memory density.
 AutoBoot for simpler access to boot code following power up.
 Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO
instructions when repeating the same type of read command.
 Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher
clock rate read commands.
 DDR read commands for SIO, DIO, and QIO.
 Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to
the Advanced Sector Protection feature found in several other Spansion parallel interface NOR memory
families.
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Data
2.3
2.4
2.4.1
She et
Glossary
Command
All information transferred between the host system and memory during one period while
CS# is low. This includes the instruction (sometimes called an operation code or opcode) and
any required address, mode bits, latency cycles, or data.
DDP
(Dual Die Package)
Two die stacked within the same package to increase the memory capacity of a single
package. Often also referred to as a Multi-Chip Package (MCP).
DDR
(Double Data Rate)
When input and output are latched on every edge of SCK.
Flash
The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that
erases large blocks of memory bits in parallel, making the erase operation much faster than
early EEPROM.
High
A signal voltage level ≥ VIH or a logic level representing a binary one (1).
Instruction
The 8 bit code indicating the function to be performed by a command (sometimes called an
operation code or opcode). The instruction is always the first 8 bits transferred from host
system to the memory in any command.
Low
A signal voltage level ≤ VIL or a logic level representing a binary zero (0).
LSB
(Least Significant Bit)
Generally the right most bit, with the lowest order of magnitude value, within a group of bits of
a register or data value.
MSB
(Most Significant Bit)
Generally the left most bit, with the highest order of magnitude value, within a group of bits of
a register or data value.
Non-Volatile
No power is needed to maintain data stored in the memory.
OPN
(Ordering Part Number)
The alphanumeric string specifying the memory device type, density, package, factory nonvolatile configuration, etc. used to select the desired device.
Page
512 bytes aligned and length group of data.
PCB
Printed Circuit Board.
Register Bit References
Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB:
bit_range_LSB].
SDR
(Single Data Rate)
When input is latched on the rising edge and output on the falling edge of SCK.
Sector
Erase unit size 256 kbytes.
Write
An operation that changes data within volatile or non-volatile registers bits or non-volatile
flash memory. When changing non-volatile data, an erase and reprogramming of any
unchanged non-volatile data is done, as part of the operation, such that the non-volatile data
is modified by the write operation, in the same way that volatile data is modified – as a single
operation. The non-volatile data appears to the host system to be updated by the single write
command, without the need for separate commands for erase and reprogram of adjacent, but
unaffected data.
Other Resources
Links to Software
http://www.spansion.com/Support/Pages/Support.aspx
2.4.2
Links to Application Notes
http://www.spansion.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx
2.4.3
Specification Bulletins
Specification bulletins provide information on temporary differences in feature description or parametric
variance since the publication of the last full data sheet. Contact your local sales office for details. Obtain the
latest list of company locations and contact information at:
http://www.spansion.com/About/Pages/Locations.aspx
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Hardware Interface
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals
that require a large number of signal connections and larger package size. The large number of connections
increase power consumption due to so many signals switching and the larger package increases cost.
The S25FL512S device reduces the number of signals for connection to the host system by serially
transferring all control, address, and data information over 4 to 6 signals. This reduces the cost of the memory
package, reduces signal switching power, and either reduces the host connection count or frees host
connectors for use in providing other features.
The S25FL512S device uses the industry standard single bit Serial Peripheral Interface (SPI) and also
supports optional extension commands for two bit (Dual) and four bit (Quad) wide serial transfers. This
multiple width interface is called SPI Multi-I/O or SPI-MIO.
3. Signal Descriptions
3.1
Input/Output Summary
Table 3.1 Signal List
Signal Name
Type
Description
Input
Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the
host system if not used.
SCK
Input
Serial Clock.
CS#
Input
Chip Select.
RESET#
SI / IO0
I/O
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1
I/O
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
WP# / IO2
I/O
Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal
pull-up resistor and may be left unconnected in the host system if not used for Quad
commands.
HOLD# / IO3
I/O
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode.
The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used for Quad commands.
VCC
Supply
Core Power Supply.
VIO
Supply
Versatile I/O Power Supply.
VSS
Supply
Ground.
NC
Unused
Not Connected. No device internal signal is connected to the package connector nor is
there any future plan to use the connector for a signal. The connection may safely be
used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal
connected to an NC must not have voltage levels higher than VIO.
Reserved
Reserved for Future Use. No device internal signal is currently connected to the
package connector but there is potential future use of the connector for a signal. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may
take advantage of future enhanced features in compatible footprint devices.
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Spansion for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive
when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for
PCB signal routing channels. Do not connect any host system signal to this connection.
RFU
DNU
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S25FL512S_00_09 January 21, 2015
Data
3.2
She et
Address and Data Configuration
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only
on the SI signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will
be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,
and IO3.
Dual or Quad Input/Output (I/O) commands send information from the host to the memory as bit pairs on IO0
and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs
on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
3.3
RESET#
The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a
command. When RESET# is driven to logic low (VIL) for at least a period of tRP, the device:
 terminates any operation in progress,
 tristates all outputs,
 resets the volatile bits in the Configuration Register,
 resets the volatile bits in the Status Registers,
 resets the Bank Address Register to zero,
 loads the Program Buffer with all ones,
 reloads all internal configuration information necessary to bring the device to standby mode,
 and resets the internal Control Unit to standby state.
RESET# causes the same initialization process as is performed when power comes up and requires tPU time.
RESET# may be asserted low at any time. To ensure data integrity any operation that was interrupted by a
hardware reset should be reinitiated once the device is ready to accept a command sequence.
When RESET# is first asserted Low, the device draws ICC1 (50 MHz value) during tPU. If RESET# continues
to be held at VSS the device draws CMOS standby current (ISB).
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.
The RESET# input is not available on all packages options. When not available the RESET# input of the
device is tied to the inactive state, inside the package.
3.4
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data
input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in
SDR commands, and after every edge in DDR commands.
3.5
Chip Select (CS#)
The chip select signal indicates when a command for the device is in process and the other signals are
relevant for the memory device. When the CS# signal is at the logic high state, the device is not selected and
all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or
Write Registers (WRR) embedded operation is in progress, the device will be in the Standby Power mode.
Driving the CS# input to logic low state enables the device, placing it in the Active Power mode. After Powerup, a falling edge on CS# is required prior to the start of any command.
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3.6
S hee t
Serial Input (SI) / IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data
to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses,
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out
data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
3.7
Serial Output (SO) / IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of
the serial SCK clock signal.
SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to
be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the
falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
3.8
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), during a WRR command and while the Status Register Write Disable (SRWD)
bit of the Status Register is set to a 1, it is not possible to write to the Status and Configuration Registers. This
prevents any alteration of the Block Protect (BP2, BP1, BP0) and TBPROT bits of the Status Register. As a
consequence, all the data bytes in the memory area that are protected by the Block Protect and TBPROT
bits, are also hardware protected against data modification if WP# is Low during a WRR command.
The WP# function is not available when the Quad mode is enabled (CR[1]=1). The WP# function is replaced
by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values
are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR
commands, and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistor; when unconnected, WP# is at VIH and may be left unconnected in the
host system if not used for Quad mode.
3.9
Hold (HOLD#) / IO3
The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the
device or stopping the serial clock.
To enter the Hold condition, the device must be selected by driving the CS# input to the logic low state. It is
recommended that the user keep the CS# input low state during the entire duration of the Hold condition. This
is to ensure that the state of the interface logic remains unchanged from the moment of entering the Hold
condition. If the CS# input is driven to the logic high state while the device is in the Hold condition, the
interface logic of the device will be reset. To restart communication with the device, it is necessary to drive
HOLD# to the logic high state while driving the CS# signal into the logic low state. This prevents the device
from going back into the Hold condition.
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with
SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic
low state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the HOLD#
signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in
progress.
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care.
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the
SCK signal being at the logic low state. If the rising edge does not coincide with the SCK signal being at the
logic low state, the Hold condition ends whenever the SCK signal reaches the logic low state.
The HOLD# function is not available when the Quad mode is enabled (CR1[1] =1). The Hold function is
replaced by IO3 for input and output during Quad mode for receiving addresses, and data to be programmed
(values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK,
in SDR commands, and on every edge of SCK, in DDR commands).
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The HOLD# signal has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad mode.
Figure 3.1 HOLD Mode Operation
CS#
SCK
HOLD#
Hold Condition
Standard Use
SI_or_IO_(during_input)
3.10
Valid Input
SO_or_IO_(internal)
A
SO_or_IO_(external)
A
Don't Care
Hold Condition
Non-standard Use
Valid Input
B
B
C
B
C
Don't Care
Valid Input
D
E
D
E
Core Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal
functions including read, program, and erase. The voltage may vary from 2.7V to 3.6V.
3.11
Versatile I/O Power Supply (VIO)
The Versatile I/O (VIO) supply is the voltage source for all device input receivers and output drivers and allows
the host system to set the voltage levels that the device tolerates on all inputs and drives on outputs (address,
control, and IO signals). The VIO range is 1.65V to VCC. VIO cannot be greater than VCC.
For example, a VIO of 1.65V - 3.6V allows for I/O at the 1.8V, 2.5V or 3V levels, driving and receiving signals
to and from other 1.8V, 2.5V or 3V devices on the same data bus. VIO may be tied to VCC so that interface
signals operate at the same voltage as the core of the device. VIO is not available in all package options,
when not available the VIO supply is tied to VCC internal to the package.
During the rise of power supplies the VIO supply voltage must remain less than or equal to the VCC supply
voltage. However, the VIO supply voltage must also be above VCC -200 mV until the VIO supply voltage is
> 1.65V, i.e. the VIO supply voltage must not lag behind the VCC supply voltage by more than 200 mV during
power up, until the VIO supply voltage reaches its minimum operating level.
This supply is not available in all package options. For a backward compatible SO16 footprint, the VIO supply
is tied to VCC inside the package; thus, the IO will function at VCC level.
3.12
Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output
drivers.
3.13
Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the
connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit
Board (PCB). However, any signal connected to an NC must not have voltage levels higher than VIO.
3.14
Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but is there potential future use of
the connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may
take advantage of future enhanced features in compatible footprint devices.
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Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by
Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU
signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor
and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB
signal routing channels. Do not connect any host system signal to these connections.
3.16
Block Diagrams
Figure 3.2 Bus Master and Memory Devices on the SPI Bus — Single Bit Data Path
HOLD#
HOLD#
WP#
WP#
SI
SO
SI
SO
SCK
CS2#
CS1#
SCK
CS2#
CS1#
FL-S
Flash
FL-S
Flash
SPI
Bus Master
Figure 3.3 Bus Master and Memory Devices on the SPI Bus — Dual Bit Data Path
HOLD#
HOLD#
WP#
WP#
IO1
IO1
IO0
IO0
SCK
CS2#
CS1#
SCK
CS2#
CS1#
FL-S
Flash
FL-S
Flash
SPI
Bus Master
Figure 3.4 Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path
IO3
IO3
IO2
IO1
IO0
SCK
CS2#
CS1#
IO2
IO1
IO0
SCK
CS2#
CS1#
FL-S
Flash
SPI
Bus Master
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4.
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Signal Protocols
4.1
4.1.1
SPI Clock Modes
Single Data Rate (SDR)
The S25FL512S device can be driven by an embedded microcontroller (bus master) in either of the two
following clocking modes.
 Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
 Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and
the output data is always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and not
transferring any data.
 SCK will stay at logic low state with CPOL = 0, CPHA = 0
 SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 4.1 SPI SDR Modes Supported
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
CS#
SI
MSB
SO
MSB
Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by
showing SCK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0
with SCK low at the fall of CS#. In such a case, mode 3 timing simply means clock is high at the fall of CS# so
no SCK rising edge set up or hold time to the falling edge of CS# is needed for mode 3.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode 0
the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling
edge of SCK because SCK is already low at the beginning of a command.
4.1.2
Double Data Rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are
always latched on the rising edge of clock, the same as in SDR commands. However, the address and input
data that follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is
latched on the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first
bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to
the next falling edge of SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from
the falling edge of CS# to the first falling edge of SCK because SCK is already low at the beginning of a
command.
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Figure 4.2 SPI DDR Modes Supported
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
CS#
Transfer_Phase
SI
Instruction
Inst. 7
Address
Inst. 0
A31 A30
Mode
A0
M7 M6
M0
SO
D0 D1
DLP7
4.2
Read
Data
Dummy / DLP
DLP0
Command Protocol
All communication between the host system and S25FL512S memory device is in the form of units called
commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be
performed. Commands may also have an address, instruction modifier, latency period, data transfer to the
memory, or data transfer from the memory. All instruction, address, and data information is transferred
serially between the host system and memory device.
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back
to the host serially on the SO signal.
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be
returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,
and IO3.
Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1
or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0
and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Commands are structured as follows:
 Each command begins with CS# going low and ends with CS# returning high. The memory device is
selected by the host driving the Chip Select (CS#) signal low throughout a command.
 The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
 Each command begins with an 8-bit (byte) instruction. The instruction is always presented only as a single
bit serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each
SCK rising edge. The instruction selects the type of information transfer or device operation to be
performed.
 The instruction may be stand alone or may be followed by address bits to select a location within one of
several address spaces in the device. The instruction determines the address space used. The address
may be either a 24-bit or a 32-bit byte boundary, address. The address transfers occur on SCK rising edge,
in SDR commands, or on every SCK edge, in DDR commands.
 The width of all transfers following the instruction are determined by the instruction sent. Following
transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done
in 2-bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per
(quad) transfer on the IO0-IO3 signals. Within the dual or quad groups the least significant bit is on IO0.
More significant bits are placed in significance order on each higher numbered IO signal. Single bits or
parallel bit groups are transferred in most to least significant bit order.
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 Some instructions send an instruction modifier called mode bits, following the address, to indicate that the
next command will be of the same type with an implied, rather than an explicit, instruction. The next
command thus does not provide an instruction byte, only a new address and mode bits. This reduces the
time needed to send each command when the same command type is repeated in a sequence of
commands. The mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge,
in DDR commands.
 The address or mode bits may be followed by write data to be stored in the memory device or by a read
latency period before read data is returned to the host.
 Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR
commands.
 SCK continues to toggle during any read access latency period. The latency may be zero to several SCK
cycles (also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are
driven from the outputs on SCK falling edge at the end of the last read latency cycle. The first read data
bits are considered transferred to the host on the following SCK rising edge. Each following transfer occurs
on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
 If the command returns read data to the host, the device continues sending data transfers until the host
takes the CS# signal high. The CS# signal can be driven high after any transfer in the read data sequence.
This will terminate the command.
 At the end of a command that does not return data, the host drives the CS# input high. The CS# signal
must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is
transferred. That is, the CS# signal must be driven high when the number of clock cycles after CS# signal
was driven low is an exact multiple of eight cycles. If the CS# signal does not go high exactly at the eight
SCK cycle boundary of the instruction or write data, the command is rejected and not executed.
 All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first.
The data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the
lowest address byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e.
the byte address increments.
 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded
operations) are ignored. The embedded operation will continue to execute without any affect. A very
limited set of commands are accepted during an embedded operation. These are discussed in the
individual command descriptions.
 Depending on the command, the time for execution varies. A command to read status information from an
executing command is available to determine when the command completes execution and whether the
command was successful.
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Command Sequence Examples
Figure 4.3 Stand Alone Instruction Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Figure 4.4 Single Bit Wide Input Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
Figure 4.5 Single Bit Wide Output Command
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
Instruction
Data 1
Data 2
Figure 4.6 Single Bit Wide I/O Command without Latency
CS#
SCK
SI
7
6
5
4 3
2
1 0 31
1 0
SO
7
Instruction
Phase
Address
6 5
4 3 2
Data 1
1
0
7 6
5
4 3 2 1 0
Data 2
Figure 4.7 Single Bit Wide I/O Command with Latency
CS#
SCK
SI
7
6
5
4 3
2
1 0 31
1 0
SO
Phase
24
7 6
Instruction
Address
S25FL512S
Dummy Cycles
5
4 3 2 1 0
Data 1
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Data
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Figure 4.8 Dual Output Command
CS#
SCK
IO0
7 6 5 4 3 2 1 0
IO1
Phase
Instruction
30 28 26
0
6 4 2 0 6 4 2 0
31 29 27
1
7 5 3 1 7 5 3 1
Address
6 Dummy
Data 1
Data 2
Figure 4.9 Quad Output Command without Latency
CS#
SCK
IO0
7 6 5 4 3 2 1 0 31
1 0 4 0 4 0 4 0 4 0 4 0 4
IO1
5 1 5 1 5 1 5 1 5 1 5
IO2
6 2 6 2 6 2 6 2 6 2 6
IO3
7 3 7 3 7 3 7 3 7 3 7
Phase
Instruction
Address
Data 1 Data 2 Data 3
Data 4
Data 5 ...
Figure 4.10 Dual I/O Command
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
0 30
31
Instruction
Phase
2
0
6
3 1
Address
7
Dummy
4
2
0
6
5 3
Data 1
1
7
4
2
0
5 3
Data 2
1
Figure 4.11 Quad I/O Command
CS#
SCK
IO0
7
0 28
4
0
4
4
0
4
0
4
0
4
0
IO1
29
5
1
5
5
1
5
1
5
1
5
1
IO2
30
6
2
6
6
2
6
2
6
2
6
2
IO3
31
7
3
7
3
7
3
7 3
D4
Phase
January 21, 2015 S25FL512S_00_09
6
5
4
3
Instruction
2
1
7 3 7
Address Mode
S25FL512S
Dummy
D1
D2
D3
25
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Figure 4.12 DDR Fast Read with EHPLC = 00b
CS#
SCK
SI
7
6
5
4
3
2
1
0
3130
0 7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction
Phase
Address
Mode
Dummy
Data 1
Data 2
Figure 4.13 DDR Dual I/O Read with EHPLC = 01b and DLP
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
Instruction
Phase
0
30 28
0
6
4
2
0
7 6
5 4
3
2
1 0
6
4
2
0
6
31 29
1
7
5
3
1
7 6
5 4
3
2
1 0
7
5
3
1
7
Address
Mode
Dum
DLP
Data 1
Figure 4.14 DDR Quad I/O Read
CS#
SCK
IO0
2824201612 8
4 0 40
7 65 4 3 2 1 0 4 0 40
IO1
2925211713 9
5 1 51
7 65 4 3 2 1 0 5 1 51
IO2
302622181410 6
2 62
7 65 4 3 2 1 0 6 2 62
IO3
312723191511 7
3 73
7 65 4 3 2 1 0 7 3 73
Phase
7
6
5
4
3
Instruction
2
1
0
Address
Mode
Dummy
DLP
D1 D2
Additional sequence diagrams, specific to each command, are provided in Section 10., Commands
on page 71.
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4.3
She et
Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 4.1 Interface States Summary
VCC
VIO
RESET#
SCK
CS#
HOLD# /
IO3
WP# /
IO2
SO /
IO1
SI /
IO0
< VCC (low)
≤ VCC
X
X
X
X
X
Z
X
< VCC (cut-off)
≤ VCC
X
X
X
X
X
Z
X
Power-On (Cold) Reset
≥ VCC (min)
≥ VIO (min)
≤ VCC
X
X
X
X
X
Z
X
Hardware (Warm) Reset
≥ VCC (min)
≥ VIO (min)
≤ VCC
HL
X
X
X
X
Z
X
Interface Standby
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
X
HH
X
X
Z
X
Instruction Cycle
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HH
HV
Z
HV
Hold Cycle
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HV or HT
HL
HL
X
X
X
Single Input Cycle
Host to Memory Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HH
X
Z
HV
Single Latency (Dummy)
Cycle
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HH
X
Z
X
Single Output Cycle
Memory to Host Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HH
X
MV
X
Dual Input Cycle
Host to Memory Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HH
X
HV
HV
Dual Latency (Dummy)
Cycle
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HH
X
X
X
Dual Output Cycle
Memory to Host Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HH
X
MV
MV
QPP Address Input Cycle
Host to Memory Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
X
X
X
HV
Quad Input Cycle
Host to Memory Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HV
HV
HV
HV
Quad Latency (Dummy)
Cycle
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
X
X
X
X
Quad Output Cycle
Memory to Host Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
MV
MV
MV
MV
DDR Single Input Cycle
Host to Memory Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
X
X
X
HV
DDR Dual Input Cycle
Host to Memory Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
X
X
HV
HV
DDR Quad Input Cycle
Host to Memory Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
HV
HV
HV
HV
DDR Latency (Dummy)
Cycle
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
MV or Z
MV or
Z
MV or
Z
MV or
Z
DDR Single Output Cycle
Memory to Host Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
Z
Z
MV
X
DDR Dual Output Cycle
Memory to Host Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
Z
Z
MV
MV
DDR Quad Output Cycle
Memory to Host Transfer
≥ VCC (min)
≥ VIO (min)
≤ VCC
HH
HT
HL
MV
MV
MV
MV
Interface State
Power-Off
Low Power
Hardware Data
Protection
Legend:
Z
= no driver - floating signal
HL = Host driving VIL
HH = Host driving VIH
HV = either HL or HH
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27
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X
HT
ML
MH
MV
4.3.1
S hee t
= HL or HH or Z
= toggling between HL and HH
= Memory driving VIL
= Memory driving VIH
= either ML or MH
Power-Off
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off.
The device does not react to external signals, and is prevented from performing any program or erase
operation.
4.3.2
Low Power Hardware Data Protection
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and
erase operations can not start when the core supply voltage is out of the operating range.
4.3.3
Power-On (Cold) Reset
When the core voltage supply remains at or below the VCC (low) voltage for ≥ tPD time, then rises
to ≥ VCC (Minimum) the device will begin its Power-On Reset (POR) process. POR continues until the end of
tPU. During tPU the device does not react to external input signals nor drive any outputs. Following the end of
tPU the device transitions to the Interface Standby state and can accept commands. For additional information
on POR see Power-On (Cold) Reset on page 38.
4.3.4
Hardware (Warm) Reset
Some of the device package options provide a RESET# input. When RESET# is driven low for tRP time the
device starts the hardware reset process. The process continues for tRPH time. Following the end of both tRPH
and the reset hold time following the rise of RESET# (tRH) the device transitions to the Interface Standby state
and can accept commands. For additional information on hardware reset see POR followed by Hardware
Reset on page 39.
4.3.5
Interface Standby
When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface
waits for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes low
to begin a new command.
While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is
in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the
algorithm when the entire device returns to standby current draw.
4.3.6
Instruction Cycle
When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device
captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the
device captures the next lower significance bit of the 8 bit instruction. The host keeps RESET# high, CS# low,
HOLD# high, and drives Write Protect (WP#) signal as needed for the instruction. However, WP# is only
relevant during instruction cycles of a WRR command and is otherwise ignored.
Each instruction selects the address space that is operated on and the transfer format used during the
remainder of the command. The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O,
DDR Single I/O, DDR Dual I/O, or DDR Quad I/O. The expected next interface state depends on the
instruction received.
Some commands are stand alone, needing no address or data transfer to or from the memory. The host
returns CS# high after the rising edge of SCK for the eighth bit of the instruction in such commands. The next
interface state in this case is Interface Standby.
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4.3.7
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Hold
When Quad mode is not enabled (CR[1]=0) the HOLD# / IO3 signal is used as the HOLD# input. The host
keeps RESET# high, HOLD# low, SCK may be at a valid level or continue toggling, and CS# is low. When
HOLD# is low a command is paused, as though SCK were held low. SI / IO0 and SO / IO1 ignore the input
level when acting as inputs and are high impedance when acting as outputs during hold state. Whether these
signals are input or output depends on the command and the point in the command sequence when HOLD#
is asserted low.
When HOLD# returns high the next state is the same state the interface was in just before HOLD# was
asserted low.
When Quad mode is enabled the HOLD# / IO3 signal is used as IO3.
During DDR commands the HOLD# and WP# inputs are ignored.
4.3.8
Single Input Cycle - Host to Memory Transfer
Several commands transfer information after the instruction on the single serial input (SI) signal from host to
the memory device. The dual output, and quad output commands send address to the memory using only SI
but return read data using the I/O signals. The host keeps RESET# high, CS# low, HOLD# high, and drives SI
as needed for the command. The memory does not drive the Serial Output (SO) signal.
The expected next interface state depends on the instruction. Some instructions continue sending address or
data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly
to Single, Dual, or Quad Output.
4.3.9
Single Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and
HOLD# high. The Write Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles
or the host may leave SI floating. The memory does not use any data driven on SI / I/O0 or other I/O signals
during the latency cycles. In dual or quad read commands, the host must stop driving the I/O signals on the
falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during
latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive
at the end of the latency cycles. This prevents driver conflict between host and memory when the signal
direction changes. The memory does not drive the Serial Output (SO) or I/O signals during the latency cycles.
The next interface state depends on the command structure i.e. the number of latency cycles, and whether
the read is single, dual, or quad width.
4.3.10
Single Output Cycle - Memory to Host Transfer
Several commands transfer information back to the host on the single Serial Output (SO) signal. The host
keeps RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory
ignores the Serial Input (SI) signal. The memory drives SO with data.
The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the
command.
4.3.11
Dual Input Cycle - Host to Memory Transfer
The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host
keeps RESET# high, CS# low, HOLD# high. The Write Protect (WP#) signal is ignored. The host drives
address on SI / IO0 and SO / IO1.
The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are
latency cycles needed or Dual Output Cycle if no latency is required.
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4.3.12
S hee t
Dual Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and
HOLD# high. The Write Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals
during these cycles or the host may leave SI / IO0 and SO / IO1 floating. The memory does not use any data
driven on SI / IO0 and SO / IO1 during the latency cycles. The host must stop driving SI / IO0 and SO / IO1
on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them
during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory
begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when
the signal direction changes. The memory does not drive the SI / IO0 and SO / IO1 signals during the latency
cycles.
The next interface state following the last latency cycle is a Dual Output Cycle.
4.3.13
Dual Output Cycle - Memory to Host Transfer
The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps
RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory drives
data on the SI / IO0 and SO / IO1 signals during the dual output cycles.
The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the
command.
4.3.14
QPP or QOR Address Input Cycle
The Quad Page Program and Quad Output Read commands send address to the memory only on IO0. The
other IO signals are ignored because the device must be in Quad mode for these commands thus the Hold
and Write Protect features are not active. The host keeps RESET# high, CS# low, and drives IO0.
For QPP the next interface state following the delivery of address is the Quad Input Cycle.
For QOR the next interface state following address is a Quad Latency Cycle if there are latency cycles
needed or Quad Output Cycle if no latency is required.
4.3.15
Quad Input Cycle - Host to Memory Transfer
The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad
Page Program command transfers four data bits to the memory in each cycle. The host keeps RESET# high,
CS# low, and drives the IO signals.
For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency
Cycle if there are latency cycles needed or Quad Output Cycle if no latency is required. For Quad Page
Program the host returns CS# high following the delivery of data to be programmed and the interface returns
to standby state.
4.3.16
Quad Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low. The
host may drive the IO signals during these cycles or the host may leave the IO floating. The memory does not
use any data driven on IO during the latency cycles. The host must stop driving the IO signals on the falling
edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency
cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the
end of the latency cycles. This prevents driver conflict between host and memory when the signal direction
changes. The memory does not drive the IO signals during the latency cycles.
The next interface state following the last latency cycle is a Quad Output Cycle.
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4.3.17
She et
Quad Output Cycle - Memory to Host Transfer
The Quad Output Read and Quad I/O Read return data to the host four bits in each cycle. The host keeps
RESET# high, and CS# low. The memory drives data on IO0-IO3 signals during the Quad output cycles.
The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the
command.
4.3.18
DDR Single Input Cycle - Host to Memory Transfer
The DDR Fast Read command sends address, and mode bits to the memory only on the IO0 signal. One bit
is transferred on the rising edge of SCK and one bit on the falling edge in each cycle. The host keeps
RESET# high, and CS# low. The other IO signals are ignored by the memory.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
4.3.19
DDR Dual Input Cycle - Host to Memory Transfer
The DDR Dual I/O Read command sends address, and mode bits to the memory only on the IO0 and IO1
signals. Two bits are transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The
host keeps RESET# high, and CS# low. The IO2 and IO3 signals are ignored by the memory.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
4.3.20
DDR Quad Input Cycle - Host to Memory Transfer
The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four
bits are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps
RESET# high, and CS# low.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
4.3.21
DDR Latency Cycle
DDR Read commands may have one to several latency cycles during which read data is read from the main
flash memory array before transfer to the host. The number of latency cycles are determined by the Latency
Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high and CS#
low. The host may not drive the IO signals during these cycles. So that there is sufficient time for the host
drivers to turn off before the memory begins to drive. This prevents driver conflict between host and memory
when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning
Pattern (DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer
than five latency cycles so that there is at least one cycle of high impedance for turn around of the IO signals
before the memory begins driving the DLP. When there are more than 4 cycles of latency the memory does
not drive the IO signals until the last four cycles of latency.
The next interface state following the last latency cycle is a DDR Single, Dual, or Quad Output Cycle,
depending on the instruction.
4.3.22
DDR Single Output Cycle - Memory to Host Transfer
The DDR Fast Read command returns bits to the host only on the SO / IO1 signal. One bit is transferred on
the rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# high, and CS#
low. The other IO signals are not driven by the memory.
The next interface state continues to be DDR Single Output Cycle until the host returns CS# to high ending
the command.
4.3.23
DDR Dual Output Cycle - Memory to Host Transfer
The DDR Dual I/O Read command returns bits to the host only on the IO0 and IO1 signals. Two bits are
transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET#
high, and CS# low. The IO2 and IO3 signals are not driven by the memory.
The next interface state continues to be DDR Dual Output Cycle until the host returns CS# to high ending the
command.
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4.3.24
S hee t
DDR Quad Output Cycle - Memory to Host Transfer
The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on
the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS#
low.
The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the
command.
4.4
Configuration Register Effects on the Interface
The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency
code selects the number of mode bit and latency cycles for each type of instruction.
The configuration register bit 1 (CR1[1]) selects whether Quad mode is enabled to ignore HOLD# and WP#
and allow Quad Page Program, Quad Output Read, and Quad I/O Read commands. Quad mode must also
be selected to allow Read DDR Quad I/O commands.
4.5
Data Protection
Some basic protection against unintended changes to stored data are provided and controlled purely by the
hardware design. These are described below. Other software managed protection methods are discussed in
the software section (page 54) of this document.
4.5.1
Power-Up
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off.
The device does not react to external signals, and is prevented from performing any program or erase
operation. Program and erase operations continue to be prevented during the Power-on Reset (POR)
because no command is accepted until the exit from POR to the Interface Standby state.
4.5.2
Low Power
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and
erase operations can not start when the core supply voltage is out of the operating range.
4.5.3
Clock Pulse Count
The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse
count that is a multiple of eight before executing them. A command not having a multiple of 8 clock pulse
count is ignored and no error status is set for the command.
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5.
She et
Electrical Specifications
5.1
Absolute Maximum Ratings
Table 5.1 Absolute Maximum Ratings
Storage Temperature Plastic Packages
–65°C to +150°C
Ambient Temperature with Power Applied
–65°C to +125°C
VCC
–0.5V to +4.0V
VIO (Note 1)
–0.5V to +4.0V
Input Voltage with Respect to Ground (VSS) (Note 2)
Output Short Circuit Current (Note 3)
–0.5V to +(VIO + 0.5V)
100 mA
Notes:
1. VIO must always be less than or equal VCC + 200 mV.
2. See Input Signal Overshoot on page 34 for allowed maximums during signal transition.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
5.2
Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
5.2.1
Temperature Ranges
Industrial (I) Devices
Ambient Temperature (TA) ....................................... –40°C to +85°C
Automotive (A) In-Cabin
Ambient Temperature (TA) ....................................... –40°C to +105°C
Automotive operating and performance parameters will be determined by device characterization and may
vary from standard industrial temperature range devices as currently shown in this specification.
5.2.2
Power Supply Voltages
Some package options provide access to a separate input and output buffer power supply called VIO.
Packages which do not provide the separate VIO connection, internally connect the device VIO to VCC. For
these packages the references to VIO are then also references to VCC.
VCC ……………2.7V to 3.6V
VIO ...................1.65V to VCC + 200 mV
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5.2.3
S hee t
Input Signal Overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VIO. During voltage
transitions, inputs or I/Os may overshoot VSS to –2.0V or overshoot to VIO +2.0V, for periods up to 20 ns.
Figure 5.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
VIL
- 2.0V
20 ns
Figure 5.2 Maximum Positive Overshoot Waveform
20 ns
VIO + 2.0V
VIH
20 ns
5.3
20 ns
Power-Up and Power-Down
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on
VCC) until VCC reaches the correct value as follows:
 VCC (min) at power-up, and then for a further delay of tPU
 VSS at power-down
A simple pull-up resistor (generally of the order of 100 kΩ) on Chip Select (CS#) can usually be used to insure
safe and proper power-up and power-down.
The device ignores all instructions until a time delay of tPU has elapsed after the moment that VCC rises above
the minimum VCC threshold. See Figure 5.3. However, correct operation of the device is not guaranteed if
VCC returns below VCC (min) during tPU. No command should be sent to the device until the end of tPU.
After power-up (tPU), the device is in Standby mode (not Deep Power Down mode), draws CMOS standby
current (ISB), and the WEL bit is reset.
During power-down or voltage drops below VCC (cut-off), the voltage must drop below VCC (low) for a period
of tPD for the part to initialize correctly on power-up. See Figure 5.4. If during a voltage drop the VCC stays
above VCC (cut-off) the part will stay initialized and will work correctly when VCC is again above VCC (min). In
the event Power-on Reset (POR) did not complete correctly after power up, the assertion of the RESET#
signal or receiving a software reset command (RESET) will restart the POR process.
Normal precautions must be taken for supply rail decoupling to stabilize the VCC supply at the device. Each
device in a system should have the VCC rail decoupled by a suitable capacitor close to the package supply
connection (this capacitor is generally of the order of 0.1 µf).
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Table 5.2 Power-Up / Power-Down Voltage and Timing
Symbol
VCC (min)
VCC (cut-off)
VCC (low)
Parameter
Min
Max
Unit
VCC (minimum operation voltage)
2.7
V
VCC (Cut 0ff where re-initialization is needed)
2.4
V
VCC (low voltage for initialization to occur)
VCC (Low voltage for initialization to occur at embedded)
1.0
2.3
V
tPU
VCC (min) to Read operation
tPD
VCC (low) time
300
1.0
µs
µs
Figure 5.3 Power-Up
VCC
VCC(max)
VCC(min)
tPU
Full Device Access
Time
Figure 5.4 Power-Down and Voltage Drop
VCC
VCC(max)
No Device Access Allowed
VCC(min)
tPU
VCC(cut-off)
Device Access
Allowed
VCC(low)
tPD
Time
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5.4
S hee t
DC Characteristics
Applicable within operating ranges.
Table 5.3 DC Characteristics
Symbol
Parameter
Test Conditions
Min
Typ (1)
Max
Unit
VIL
Input Low Voltage
-0.5
0.2 x VIO
V
VIH
Input High Voltage
0.7 x VIO
VIO+0.4
V
VOL
Output Low Voltage
IOL = 1.6 mA, VCC = VCC min
0.15 x VIO
V
VOH
Output High Voltage
IOH = –0.1 mA
ILI
Input Leakage Current
VCC = VCC Max, VIN = VIH or VIL
0.85 x VIO
±2
µA
V
ILO
Output Leakage
Current
VCC = VCC Max, VIN = VIH or VIL
±2
µA
ICC1
Active Power Supply
Current (READ)
Serial [email protected] MHz
Serial [email protected] MHz
Quad SDR @ 80 MHz
Quad SDR @104 MHz
Quad DDR @ 66 MHz
Quad DDR @80 MHz
Outputs unconnected during read data
return(2)
ICC2
Active Power Supply
Current (Page
Program)
CS# = VIO
100
mA
ICC3
Active Power Supply
Current (WRR)
CS# = VIO
100
mA
ICC4
Active Power Supply
Current (SE)
CS# = VIO
100
mA
ICC5
Active Power Supply
Current (BE)
CS# = VIO
100
mA
ISB (Industrial)
Standby Current
RESET#, CS# = VIO; SI, SCK = VIO or VSS,
Industrial Temp
70
100
µA
ISB (Automotive)
Standby Current
RESET#, CS# = VIO; SI, SCK = VIO or VSS,
Automotive Temp
70
300
µA
16
33/35 (3)
50
61
75
90
mA
Notes:
1. Typical values are at TAI = 25°C and VCC = VIO = 3V.
2. Output switching current is not included.
3. Industrial temperature range / Automotive In-Cabin temperature range.
5.4.1
Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in an Active Power mode until all program, erase, and write operations
have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB.
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6.
6.1
She et
Timing Specifications
Key to Switching Waveforms
Figure 6.1 Waveform Element Meanings
Input
Valid at logic high or low
High Impedance
Any change permitted
Logic High Logic Low
Valid at logic high or low
High Impedance
Changing, state unknown
Logic High Logic Low
Symbol
Output
Figure 6.2 Input, Output, and Timing Reference Levels
Input Levels
Output Levels
VIO + 0.4V
0.7 x VIO
0.5 x VIO
0.85 x VIO
Timing Reference Level
0.2 x VIO
0.15 x VIO
- 0.5V
6.2
AC Test Conditions
Figure 6.3 Test Setup
Device
Under
Test
CL
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Table 6.1 AC Measurement Conditions
Symbol
Parameter
Min
CL
Load Capacitance
Max
Unit
30
pF
15 (4)
Input Rise and Fall Times
2.4
ns
Input Pulse Voltage
0.2 x VIO to 0.8 VIO
V
Input Timing Ref Voltage
0.5 VIO
V
Output Timing Ref
Voltage
0.5 VIO
V
Notes:
1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).
4. DDR Operation.
6.2.1
Capacitance Characteristics
Table 6.2 Capacitance
Parameter
Test Conditions
Max
Unit
CIN
Input Capacitance (applies to SCK, CS#, RESET#)
1 MHz, TA = 25°C
Min
8
pF
COUT
Output Capacitance (applies to All I/O)
1 MHz, TA = 25°C
8
pF
Note:
1. For more information on capacitance, please consult the IBIS models.
6.3
6.3.1
Reset
Power-On (Cold) Reset
The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the
moment that VCC rises above the minimum VCC threshold. See Figure 5.3 on page 35, Table 5.2 on page 35,
and Table 6.3 on page 40. The device must not be selected (CS# to go high with VIO) during power-up (tPU),
i.e. no commands may be sent to the device until the end of tPU. RESET# is ignored during POR. If RESET#
is low during POR and remains low through and beyond the end of tPU, CS# must remain high until tRH after
RESET# returns high. RESET# must return high for greater than tRS before returning low to initiate a
hardware reset.
Figure 6.4 Reset Low at the End of POR
VCC
VIO
tPU
RESET#
If RESET# is low at tPU end
tRH
CS#
38
CS# must be high at tPU end
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Figure 6.5 Reset High at the End of POR
VCC
VIO
tPU
RESET#
If RESET# is high at tPU end
tPU
CS# may stay high or go low at tPU end
CS#
Figure 6.6 POR followed by Hardware Reset
VCC
VIO
tPU
tRS
RESET#
tPU
CS#
6.3.2
Hardware (Warm) Reset
When the RESET# input transitions from VIH to VIL the device will reset register states in the same manner as
power-on reset but, does not go through the full reset process that is performed during POR. The hardware
reset process requires a period of tRPH to complete. If the POR process did not complete correctly for any
reason during power-up (tPU), RESET# going low will initiate the full POR process instead of the hardware
reset process and will require tPU to complete the POR process.
The RESET# input provides a hardware method of resetting the flash memory device to standby state.
 RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset.
 When RESET# is driven low for at least a minimum period of time (tRP), the device terminates any
operation in progress, tri-states all outputs, and ignores all read/write commands for the duration of tRPH.
The device resets the interface to standby state.
 If CS# is low at the time RESET# is asserted, CS# must return high during tRPH before it can be asserted
low again after tRH.
 Hardware Reset is only offered in 16-lead SOIC and BGA packages.
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Figure 6.7 Hardware Reset
tRP
RESET#
Any prior reset
tRH
tRPH
tRH
tRS
tRPH
CS#
Table 6.3 Hardware Reset Parameters
Parameter
Description
Limit
Time
Unit
tRS
Reset Setup Prior Reset end and RESET# high before RESET# low
Min
50
ns
tRPH
Reset Pulse Hold - RESET# low to CS# low
Min
35
µs
tRP
RESET# Pulse Width
Min
200
ns
tRH
Reset Hold - RESET# high before CS# low
Min
50
ns
Notes:
1. RESET# Low is optional and ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset
state and tRH will determine when CS# may go Low.
2. Sum of tRP and tRH must be equal to or greater than tRPH.
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6.4
She et
SDR AC Characteristics
Table 6.4 AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V)
Symbol
Parameter
Min
Max
Unit
DC
50 (7)
MHz
SCK Clock Frequency for single commands as
shown in Table 10.2 on page 74 (4)
DC
133 (7)
MHz
FSCK, C
SCK Clock Frequency for the following dual and
quad commands: DOR, 4DOR, QOR, 4QOR, DIOR,
4DIOR, QIOR, 4QIOR
DC
104 (7)
MHz
FSCK, QPP
SCK Clock Frequency for the QPP, 4QPP commands
DC
80 (7)
MHz
1/ FSCK
∞
FSCK, R
SCK Clock Frequency for READ and 4READ
instructions
FSCK, C
PSCK
SCK Clock Period
Typ
tWH, tCH
Clock High Time (5)
45% PSCK
ns
tWL, tCL
Clock Low Time (5)
45% PSCK
ns
tCRT, tCLCH
Clock Rise Time (slew rate)
0.1
V/ns
tCFT, tCHCL
Clock Fall Time (slew rate)
0.1
V/ns
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50
ns
tCS
tCSS
CS# Active Setup Time (relative to SCK)
3
tCSH
CS# Active Hold Time (relative to SCK)
3
tSU
Data in Setup Time
2
ns
tHD
Data in Hold Time
2
ns
tV
Clock Low to Output Valid
ns
3000 (6)
ns
8.0 (2)
7.65 (3)
6.5 (4)
ns
8
ns
tHO
Output Hold Time
2
tDIS
Output Disable Time
0
tWPS
WP# Setup Time
20 (1)
tWPH
WP# Hold Time
100 (1)
ns
ns
ns
tHLCH
HOLD# Active Setup Time (relative to SCK)
3
ns
tCHHH
HOLD# Active Hold Time (relative to SCK)
3
ns
tHHCH
HOLD# Non Active Setup Time (relative to SCK)
3
ns
tCHHL
HOLD# Non Active Hold Time (relative to SCK)
3
ns
tHZ
HOLD# enable to Output Invalid
8
ns
tLZ
HOLD# disable to Output Valid
8
ns
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Full VCC range (2.7 - 3.6V) and CL = 30 pF.
3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF.
4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF.
5. ±10% duty cycle is supported for frequencies ≤ 50 MHz.
6. Maximum value only applies during Program/Erase Suspend/Resume commands.
7. For Automotive In-Cabin temperature range (-40°C to +105°C), all SCK frequencies are 5% slower than the max values shown.
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Table 6.5 AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V)
Symbol
Parameter
Min
FSCK, R
SCK Clock Frequency for READ, 4READ instructions
FSCK, C
SCK Clock Frequency for all others (3)
PSCK
SCK Clock Period
Typ
Max
Unit
DC
50 (6)
MHz
DC
66 (6)
MHz
1/ FSCK
∞
tWH, tCH
Clock High Time (4)
45% PSCK
tWL, tCL
Clock Low Time (4)
45% PSCK
ns
Clock Rise Time (slew rate)
0.1
V/ns
tCRT, tCLCH
tCFT, tCHCL
ns
Clock Fall Time (slew rate)
0.1
V/ns
tCS
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50
ns
tCSS
CS# Active Setup Time (relative to SCK)
10
ns
tCSH
CS# Active Hold Time (relative to SCK)
3
tSU
Data in Setup Time
5
tHD
Data in Hold Time
4
tV
3000 (5)
ns
ns
ns
14.5 (2)
12.0 (3)
Clock Low to Output Valid
ns
tHO
Output Hold Time
2
tDIS
Output Disable Time
0
ns
tWPS
WP# Setup Time
20 (1)
ns
tWPH
WP# Hold Time
100 (1)
ns
tHLCH
HOLD# Active Setup Time (relative to SCK)
5
ns
tCHHH
HOLD# Active Hold Time (relative to SCK)
5
ns
14
ns
tHHCH
HOLD# Non Active Setup Time (relative to SCK)
5
ns
tCHHL
HOLD# Non Active Hold Time (relative to SCK)
5
ns
tHZ
HOLD# enable to Output Invalid
14
ns
tLZ
HOLD# disable to Output Valid
14
ns
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. CL = 30 pF.
3. CL = 15 pF.
4. ±10% duty cycle is supported for frequencies ≤ 50 MHz.
5. Maximum value only applies during Program/Erase Suspend/Resume commands.
6. For Automotive In-Cabin temperature range (-40°C to +105°C), all SCK frequencies are 5% slower than the max values shown.
6.4.1
Clock Timing
Figure 6.8 Clock Timing
PSCK
tCH
tCL
VIH min
VIO / 2
VIL max
tCFT
tCRT
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6.4.2
She et
Input / Output Timing
Figure 6.9 SPI Single Bit Input Timing
tCS
CS#
tCSH
tCSH
tCSS
tCSS
SCK
tSU
tHD
SI
MSB IN
LSB IN
SO
Figure 6.10 SPI Single Bit Output Timing
tCS
CS#
SCK
SI
tLZ
SO
tHO
tV
MSB OUT
tDIS
LSB OUT
Figure 6.11 SPI SDR MIO Timing
tCS
CS#
tCSS
tCSH
tCSS
SCK
tSU
tLZ
tHD
IO
January 21, 2015 S25FL512S_00_09
MSB IN
LSB IN
S25FL512S
MSB OUT
.
tHO
tV
tDIS
LSB OUT
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Figure 6.12 Hold Timing
CS#
SCK
tCHHH
tHLCH
tHLCH
tHHCH
tCHHL
tCHHH
tCHHL
HOLD#
Hold Condition
Hold Condition
Standard Use
Non-standard Use
SI_or_IO_(during_input)
tHZ
SO_or_IO_(during_output)
A
tLZ
B
B
tHZ
tLZ
C
D
E
Figure 6.13 WP# Input Timing
CS#
tWPS
tWPH
WP#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
44
WRR Instruction
S25FL512S
Input Data
S25FL512S_00_09 January 21, 2015
Data
6.5
She et
DDR AC Characteristics
Table 6.6 AC Characteristics DDR Operation
66 MHz
Symbol
80 MHz
Parameter
Unit
Min
Typ
Max
Min
Typ
Max
FSCK, R
SCK Clock Frequency for DDR
READ instruction
DC
66 (3)
DC
80 (3)
MHz
PSCK, R
SCK Clock Period for DDR READ
instruction
15
∞
12.5
∞
ns
tWH, tCH
Clock High Time
45% PSCK
45% PSCK
ns
tWL, tCL
Clock Low Time
45% PSCK
45% PSCK
ns
tCS
CS# High Time (Read
Instructions)
10
10
ns
tCSS
CS# Active Setup Time (relative to
SCK)
3
3
ns
tCSH
CS# Active Hold Time (relative to
SCK)
3
3
ns
tSU
IO in Setup Time
2
tHD
IO in Hold Time
2
Clock Low to Output Valid
0
tHO
Output Hold Time
0
tDIS
Output Disable Time
tLZ
Clock to Output Low Impedance
tO_SKEW
First Output to last Output data
valid time
tV
3000 (2)
1.5
6.5 (1)
1.5
8
600
0
ns
ns
6.5 (1)
1.5
8
0
3000 (2)
1.5
ns
ns
8
ns
8
ns
600
ps
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
3. For Automotive In-Cabin temperature range (-40°C to +105°C), all SCK frequencies are 5% slower than the max values shown.
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S hee t
DDR Input Timing
Figure 6.14 SPI DDR Input Timing
tCS
CS#
tCSH
tCSS
tCSH
tCSS
SCK
tHD
tSU
tHD
tSU
SI_or_IO
MSB IN
LSB IN
SO
6.5.2
DDR Output Timing
Figure 6.15 SPI DDR Output Timing
tCS
CS#
SCK
SI
tLZ
SO_or_IO
46
tHO
tV
MSB
tV
tDIS
LSB
S25FL512S
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Data
She et
Figure 6.16 SPI DDR Data Valid Window
PSCK
tCL
tCH
SCK
tV
tV
tO_SKEW
tOTT
Slow
D1
IO0
Slow
D2
IO1
IO2
Fast
D1
IO3
IO_valid
Fast
D2
D1
Valid
D2
Valid
tDV
tDV
Notes:
1. tCLH is the shorter duration of tCL or tCH.
2. tO_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all IO signals.
3. tOTT is the maximum Output Transition Time from one valid data value to the next valid data value on each IO.
4. tOTT is dependent on system level considerations including:
a.
b.
c.
d.
Memory device output impedance (drive strength).
System level parasitics on the IOs (primarily bus capacitance).
Host memory controller input VIH and VIL levels at which 0 to 1 and 1 to 0 transitions are recognized.
As an example, assuming that the above considerations result a memory output slew rate of 2V/ns and a 3V transition (from 1 to 0 or
0 to 1) is required by the host, the tOTT would be:
tOTT = 3V/(2V/ns) = 1.5 ns
e. tOTT is not a specification tested by Spansion, it is system dependent and must be derived by the system designer based on the above
considerations.
5. The minimum data valid window (tDV) can be calculated as follows:
a. As an example, assuming:
i. 80 MHz clock frequency = 12.5 ns clock period
ii. DDR operations are specified to have a duty cycle of 45% or higher
iii. tCLH = 0.45*PSCK = 0.45x12.5 ns = 5.625 ns
iv. tO_SKEW = 600 ps
v. tOTT = 1.5 ns
b. tDV = tCLH - tO_SKEW - tOTT
c. tDV = 5.625 ns - 600 ps - 1.5 ns = 3.525 ns
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7. Physical Interface
Table 7.1 Model Specific Connections
VIO / RFU
RESET# / RFU
Versatile I/O or RFU - Some device models bond this connector to the device I/O power supply, other
models bond the device I/O supply to Vcc within the package leaving this package connector unconnected.
RESET# or RFU - Some device models bond this connector to the device RESET# signal, other models
bond the RESET# signal to Vcc within the package leaving this package connector unconnected.
Note:
Refer to Table 3.1, Signal List on page 16 for signal descriptions.
7.1
7.1.1
SOIC 16-Lead Package
SOIC 16 Connection Diagram
Figure 7.1 16-Lead SOIC Package, Top View
48
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
RESET#/RFU
3
14
VIO/RFU
DNU
4
13
NC
DNU
5
12
DNU
RFU
6
11
DNU
CS#
7
10
VSS
SO/IO1
8
9
S25FL512S
WP#/IO2
S25FL512S_00_09 January 21, 2015
Data
7.1.2
She et
SOIC 16 Physical Diagram
S03016 — 16-Lead Wide Plastic Small Outline Package (300-mil Body Width)
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7.2.1
S hee t
FAB024 24-Ball BGA Package
Connection Diagram
Figure 7.2 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View
1
2
3
4
5
NC
NC
RESET#/
RFU
NC
DNU
SCK
VSS
VCC
NC
DNU
CS#
RFU
WP#/IO2
NC
DNU
SO/IO1
NC
NC
A
B
C
D
SI/IO0 HOLD#/IO3
NC
E
NC
VIO/RFU
NC
Note:
Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use either package.
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7.2.2
She et
FAB024 Physical Diagram
FAB024 — 24-Ball BGA (8 x 6 mm) Package
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7.3
7.3.1
S hee t
FAC024 24-Ball BGA Package
Connection Diagram
Figure 7.3 24-Ball BGA, 4 x 6 Ball Footprint (FAC024), Top View
1
2
3
4
NC
NC
NC
RESET#/
RFU
DNU
SCK
VSS
VCC
DNU
CS#
RFU
WP#/IO2
DNU
SO/IO1
NC
NC
NC
VIO/RFU
NC
NC
NC
NC
A
B
C
D
SI/IO0 HOLD#/IO3
E
F
Note:
1. Signal connections are in the same relative positions as FAB024 BGA, allowing a single PCB footprint to use either package.
52
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7.3.2
She et
FAC024 Physical Diagram
FAC024 — 24-Ball BGA (6 x 8 mm) Package
NOTES:
PACKAGE
FAC024
JEDEC
N/A
1.
8.00 mm x 6.00 mm NOM
PACKAGE
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
DxE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.25
---
---
A2
0.70
---
0.90
NOTE
PROFILE
BALL HEIGHT
BODY THICKNESS
D
8.00 BSC.
BODY SIZE
E
6.00 BSC.
BODY SIZE
D1
5.00 BSC.
MATRIX FOOTPRINT
E1
3.00 BSC.
MATRIX FOOTPRINT
MD
6
MATRIX SIZE D DIRECTION
ME
4
MATRIX SIZE E DIRECTION
N
24
BALL COUNT
Øb
0.35
0.40
e
1.00 BSC.
SD/ SE
0.5/0.5
0.45
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
7
BALL DIAMETER
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
BALL PITCHL
SOLDER BALL PLACEMENT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
DEPOPULATED SOLDER BALLS
J
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
PACKAGE OUTLINE TYPE
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3642 F16-038.9 \ 09.10.09
7.3.3
Special Handling Instructions for FBGA Packages
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
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Software Interface
This section discusses the features and behaviors most relevant to host system software that interacts with
the S25FL512S memory device.
8. Address Space Maps
8.1
8.1.1
Overview
Extended Address
The S25FL512S device supports 32-bit addresses to enable higher density devices than allowed by previous
generation (legacy) SPI devices that supported only 24-bit addresses. A 24-bit byte resolution address can
access only 16 Mbytes (128 Mbits) of maximum density. A 32-bit byte resolution address allows direct
addressing of up to a 4 Gbytes (32 Gbits) of address space.
Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit
addresses are enabled in three ways:
 Bank address register — a software (command) loadable internal register that supplies the high order bits
of address when legacy 24-bit addresses are in use.
 Extended address mode — a bank address register bit that changes all legacy commands to expect 32 bits
of address supplied from the host system.
 New commands — that perform both legacy and new functions, which expect 32-bit address.
The default condition at power-up and after reset, is the Bank address register loaded with zeros and the
extended address mode set for 24-bit addresses. This enables legacy software compatible access to the first
128 Mbits of a device.
8.1.2
Multiple Address Spaces
Many commands operate on the main flash memory array. Some commands operate on address spaces
separate from the main flash array. Each separate address space uses the full 32-bit address but may only
define a small portion of the available address space.
8.2
Flash Memory Array
The main flash array is divided into erase units called sectors. The sectors are organized as uniform
256-kbyte sectors.
Table 8.1 S25FL512S Sector and Memory Address Map, Uniform 256-kbyte Sectors
Sector Size (kbyte)
256
Sector Count
Sector Range
Address Range (8-bit)
Notes
SA00
00000000h-0003FFFFh
Sector Starting Address
:
:
—
SA255
03FC0000h-03FFFFFFh
Sector Ending Address
256
Note: This is a condensed table that uses a sector as a reference. There are address ranges that are not
explicitly listed. All 256-kB sectors have the pattern XXXX0000h-XXXXFFFFh.
8.3
ID-CFI Address Space
The RDIDJ command (9Fh) reads information from a separate flash memory address space for device
identification (ID) and Common Flash Interface (CFI) information. See Device ID and Common Flash
Interface (ID-CFI) Address Map on page 123 for the tables defining the contents of the ID-CFI address space.
The ID-CFI address space is programmed by Spansion and read-only for the host system.
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8.4
She et
JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) Space.
The RSFDP command (5Ah) reads information from a separate Flash memory address space for device
identification, feature, and configuration information, in accord with the JEDEC JESD216B standard for Serial
Flash Discoverable Parameters. The ID-CFI address space is incorporated as one of the SFDP parameters.
See Section 11.2, Serial Flash Discoverable Parameters (SFDP) Address Map on page 120 for the table
defining the contents of the SFDP address space. The SFDP address space is programmed by Spansion and
is read-only for the host system
8.5
OTP Address Space
Each S25FL512S memory device has a 1024-byte One Time Program (OTP) address space that is separate
from the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length
regions.
In the 32-byte region starting at address zero:
 The 16 lowest address bytes are programmed by Spansion with a 128-bit random number. Only Spansion
is able to program these bytes.
 The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to
permanently protect each region from programming. The bytes are erased when shipped from Spansion.
After an OTP region is programmed, it can be locked to prevent further programming, by programming the
related protection bit in the OTP Lock Bytes.
 The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in
these RFU bytes may be programmed by the host system but it must be understood that a future device
may use those bits for protection of a larger OTP space. The bytes are erased when shipped from
Spansion.
The remaining regions are erased when shipped from Spansion, and are available for programming of
additional permanent data.
Refer to Figure 8.1, OTP Address Space on page 56 for a pictorial representation of the OTP memory space.
The OTP memory space is intended for increased system security. OTP values, such as the random number
programmed by Spansion, can be used to “mate” a flash component with the system CPU/ASIC to prevent
device substitution.
The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming
when set to 1. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit
to prevent further OTP memory space programming during the remainder of normal power-on system
operation.
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Figure 8.1 OTP Address Space
32 Byte OTP Region 31
32 Byte OTP Region 30
32 Byte OTP Region 29
.
.
.
When programmed to
“0” each lock bit
protects its related 32
byte region from any
further programming
32 Byte OTP Region 3
32 Byte OTP Region 2
32 Byte OTP Region 1
32 Byte OTP Region 0
...
Lock Bits 31 to 0
Contents of Region 0
{
Reserved
Byte 1F
Lock Bytes
16 Byte Random Number
Byte 10
Byte 0
Table 8.2 OTP Address Map
Region
Byte Address Range (Hex)
Contents
000
Least Significant Byte of
Spansion Programmed Random
Number
...
...
00F
Most Significant Byte of
Spansion Programmed Random
Number
010 to 013
Region Locking Bits
Byte 10 [bit 0] locks region 0
from programming when = 0
...
Byte 13 [bit 7] locks region 31
from programming when = 0
All bytes = FF
014 to 01F
Reserved for Future Use (RFU)
All bytes = FF
Region 1
020 to 03F
Available for User Programming
All bytes = FF
Region 2
040 to 05F
Available for User Programming
All bytes = FF
...
...
Available for User Programming
All bytes = FF
Region 31
3E0 to 3FF
Available for User Programming
All bytes = FF
Region 0
56
S25FL512S
Initial Delivery State (Hex)
Spansion Programmed Random
Number
S25FL512S_00_09 January 21, 2015
Data
8.6
She et
Registers
Registers are small groups of memory cells used to configure how the S25FL512-S memory device operates
or to report the status of device operations. The registers are accessed by specific commands. The
commands (and hexadecimal instruction codes) used for each register are noted in each register description.
The individual register bits may be volatile, non-volatile, or One Time Programmable (OTP). The type for
each bit is noted in each register description. The default state shown for each bit refers to the state after
power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the
default state is the value of the bit when the device is shipped from Spansion. Non-volatile bits have the same
cycling (erase and program) endurance as the main flash array.
8.6.1
Status Register 1 (SR1)
Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN
06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h).
Table 8.3 Status Register-1 (SR1)
Bits
Field
Name
Function
Type
Default State
Description
7
SRWD
Status Register
Write Disable
Non-Volatile
0
1 = Locks state of SRWD, BP, and configuration register
bits when WP# is low by ignoring WRR command
0 = No protection, even when WP# is low
6
P_ERR
Programming
Error Occurred
Volatile, Read only
0
1 = Error occurred.
0 = No Error
5
E_ERR
Erase Error
Occurred
Volatile, Read only
0
1 = Error occurred
0 = No Error
Block
Protection
Volatile if CR1[3]=1,
Non-Volatile if
CR1[3]=0
4
BP2
3
BP1
2
BP0
1 if CR1[3]=1,
0 when
shipped from
Spansion
Protects selected range of sectors (Block) from Program
or Erase
1
WEL
Write Enable
Latch
Volatile
0
1 = Device accepts Write Registers (WRR), program or
erase commands
0 = Device ignores Write Registers (WRR), program or
erase commands
This bit is not affected by WRR, only WREN and WRDI
commands affect this bit
0
WIP
Write in
Progress
Volatile, Read only
0
1 = Device Busy, a Write Registers (WRR), program,
erase or other operation is in progress
0 = Ready Device is in standby mode and can accept
commands
The Status Register contains both status and control bits:
Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when
this bit is set to 1 and the WP# input is driven low. In this mode, the SRWD, BP2, BP1, and BP0 bits of the
Status Register become read-only bits and the Write Registers (WRR) command is no longer accepted for
execution. If WP# is high the SRWD bit and BP bits may be changed by the WRR command. If SRWD is 0,
WP# has no effect and the SRWD bit and BP bits may be changed by the WRR command. The SRWD bit
has the same non-volatile endurance as the main flash array.
Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure
indication. When the Program Error bit is set to a 1 it indicates that there was an error in the last program
operation. This bit will also be set when the user attempts to program within a protected main memory sector
or locked OTP region. When the Program Error bit is set to a 1 this bit can be reset to 0 with the Clear Status
Register (CLSR) command. This is a read-only bit and is not affected by the WRR command.
Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure
indication. When the Erase Error bit is set to a 1 it indicates that there was an error in the last erase operation.
This bit will also be set when the user attempts to erase an individual protected main memory sector. The
Bulk Erase command will not set E_ERR if a protected sector is found during the command execution. When
the Erase Error bit is set to a 1 this bit can be reset to 0 with the Clear Status Register (CLSR) command. This
is a read-only bit and is not affected by the WRR command.
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Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be softwareprotected against program and erase commands. The BP bits are either volatile or non-volatile, depending on
the state of the BP non-volatile bit (BPNV) in the configuration register. When one or more of the BP bits is set
to 1, the relevant memory area is protected against program and erase. The Bulk Erase (BE) command can
be executed only when the BP bits are cleared to 0’s. See Block Protection on page 66 for a description of
how the BP bit values select the memory array area protected. The BP bits have the same non-volatile
endurance as the main flash array.
Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to 1 to enable program, write, or erase
operations as a means to provide protection against inadvertent changes to memory or register values. The
Write Enable (WREN) command execution sets the Write Enable Latch to a 1 to allow any program, erase, or
write commands to execute afterwards. The Write Disable (WRDI) command can be used to set the Write
Enable Latch to a 0 to prevent all program, erase, and write commands from execution. The WEL bit is
cleared to 0 at the end of any successful program, write, or erase operation. Following a failed operation the
WEL bit may remain set and should be cleared with a WRDI command following a CLSR command. After a
power down/power up sequence, hardware reset, or software reset, the Write Enable Latch is set to a 0 The
WRR command does not affect this bit.
Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase
operation, or any other operation, during which a new operation command will be ignored. When the bit is set
to a 1 the device is busy performing an operation. While WIP is 1, only Read Status (RDSR1 or RDSR2),
Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status Register (CLSR), and Software Reset
(RESET) commands may be accepted. ERSP and PGSP will only be accepted if memory array erase or
program operations are in progress. The status register E_ERR and P_ERR bits are updated while WIP = 1.
When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains
busy and unable to receive new operation commands. A Clear Status Register (CLSR) command must be
received to return the device to standby mode. When the WIP bit is cleared to 0 no operation is in progress.
This is a read-only bit.
8.6.2
Configuration Register 1 (CR1)
Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The
Configuration Register bits can be changed using the WRR command with sixteen input cycles.
The configuration register controls certain interface and data protection functions.
Table 8.4 Configuration Register (CR1)
Bits
Field Name
7
LC1
6
LC0
5
TBPROT
4
Type
Latency Code
Non-Volatile
Default
State
0
0
Description
Selects number of initial read latency cycles
See Latency Code Tables
1 = BP starts at bottom (Low address)
0 = BP starts at top (High address)
Configures Start of
Block Protection
OTP
0
RFU
RFU
RFU
0
Reserved for Future Use
3
BPNV
Configures BP2-0 in
Status Register
OTP
0
1 = Volatile
0 = Non-Volatile
2
RFU
RFU
RFU
0
Reserved for Future Use
QUAD
Puts the device into
Quad I/O operation
Non-Volatile
0
1 = Quad
0 = Dual or Serial
FREEZE
Lock current state of
BP2-0 bits in Status
Register, TBPROT in
Configuration
Register, and OTP
regions
Volatile
0
1 = Block Protection and OTP locked
0 = Block Protection and OTP un-locked
1
0
58
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Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between
the end of address and the start of read data output for all read commands.
Some read commands send mode bits following the address to indicate that the next command will be of the
same type with an implied, rather than an explicit, instruction. The next command thus does not provide an
instruction byte, only a new address and mode bits. This reduces the time needed to send each command
when the same command type is repeated in a sequence of commands.
Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array
before data can be returned to the host system. Some read commands require additional latency cycles as
the SCK frequency is increased.
The following latency code tables provide different latency settings that are configured by Spansion. The High
Performance versus the Enhanced High Performance settings are selected by the ordering part number.
Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not
supported at the frequency shown. Read is supported only up to 50 MHz but the same latency value is
assigned in each latency code and the command may be used when the device is operated at ≤ 50 MHz with
any latency code setting. Similarly, only the Fast Read command is supported up to 133 MHz but the same
10b latency code is used for Fast Read up to 133 MHz and for the other dual and quad read commands up to
104 MHz. It is not necessary to change the latency code from a higher to a lower frequency when operating at
lower frequencies where a particular command is supported. The latency code values for a higher frequency
can be used for accesses at lower frequencies.
The High Performance settings provide latency options that are the same or faster than alternate source SPI
memories. These settings provide mode bits only for the Quad I/O Read command.
The Enhanced High Performance settings similarly provide latency options the same or faster than additional
alternate source SPI memories and adds mode bits for the Dual I/O Read, DDR Fast Read, and DDR
Dual I/O Read commands.
Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the
start of read data, if there are 5 or more dummy cycles. See Read Memory Array Commands on page 89 for
more information on the DLP.
Table 8.5 Latency Codes for SDR High Performance
Freq.
(MHz)
LC
Read
Fast Read
Read Dual Out
Read Quad Out
Dual I/O Read
(03h, 13h)
(0Bh, 0Ch)
(3Bh, 3Ch)
(6Bh, 6Ch)
(BBh, BCh)
Quad I/O Read
(EBh, ECh)
Mode
Dummy
Mode
Dummy
Mode
Dummy
Mode
Dummy
Mode
Dummy
Mode
Dummy
≤ 50
11
0
0
0
0
0
0
0
0
0
4
2
1
≤ 80
00
-
-
0
8
0
8
0
8
0
4
2
4
≤ 90
01
-
-
0
8
0
8
0
8
0
5
2
4
≤104
10
-
-
0
8
0
8
0
8
0
6
2
5
≤133
10
-
-
0
8
-
-
-
-
-
-
-
-
Table 8.6 Latency Codes for DDR High Performance
Freq.
(MHz)
DDR Fast Read
DDR Dual I/O Read
(0Dh, 0Eh)
(BDh, BEh)
LC
Read DDR Quad I/O
(EDh, EEh)
Mode
Dummy
Mode
Dummy
Mode
Dummy
≤ 50
11
0
4
0
4
1
3
≤ 66
00
0
5
0
6
1
6
≤ 66
01
0
6
0
7
1
7
≤ 66
10
0
7
0
8
1
8
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Table 8.7 Latency Codes for SDR Enhanced High Performance
Read
Freq.
(MHz)
LC
Fast Read
(03h, 13h)
Read Dual Out
(0Bh, 0Ch)
Read Quad Out
(3Bh, 3Ch)
Dual I/O Read
(6Bh, 6Ch)
(BBh, BCh)
Quad I/O Read
(EBh, ECh)
Mode
Dummy
Mode
Dummy
Mode
Dummy
Mode
Dummy
Mode
Dummy
Mode
Dummy
≤ 50
11
0
0
0
0
0
0
0
0
4
0
2
1
≤ 80
00
-
-
0
8
0
8
0
8
4
0
2
4
≤ 90
01
-
-
0
8
0
8
0
8
4
1
2
4
≤104
10
-
-
0
8
0
8
0
8
4
2
2
5
≤133
10
-
-
0
8
-
-
-
-
-
-
-
-
Table 8.8 Latency Codes for DDR Enhanced High Performance
Freq.
(MHz)
DDR Fast Read
DDR Dual I/O Read
(0Dh, 0Eh)
(BDh, BEh)
LC
Read DDR Quad I/O
(EDh, EEh)
Mode
Dummy
Mode
Dummy
Mode
Dummy
≤ 50
11
4
1
2
2
1
3
≤ 66
00
4
2
2
4
1
6
≤ 66
01
4
4
2
5
1
7
≤ 66
10
4
5
2
6
1
8
≤ 80
00
4
2
2
4
1
6
≤ 80
01
4
4
2
5
1
7
≤ 80
10
4
5
2
6
1
8
Note:
1. When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides 5 or more dummy cycles
should be selected to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP. It is
recommended to use LC 10 for DDR Fast Read, LC 01 for DDR Dual IO Read, and LC 00 for DDR Quad IO Read, if the Data Learning
Pattern (DLP) for DDR is used.
Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits
BP2, BP1, and BP0 in the Status Register. As described in the status register section, the BP2-0 bits allow
the user to optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to the entire array.
When TBPROT is set to a 0 the Block Protection is defined to start from the top (maximum address) of the
array. When TBPROT is set to a 1 the Block Protection is defined to start from the bottom (zero address) of
the array. The TBPROT bit is OTP and set to a 0 when shipped from Spansion. If TBPROT is programmed to
1, an attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).
The desired state of TBPROT must be selected during the initial configuration of the device during system
manufacture; before the first program or erase operation on the main flash array. TBPROT must not be
programmed after programming or erasing is done in the main flash array.
CR1[4]: Reserved for Future Use
Block Protection Non-Volatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2-0 bits in the
Status Register are volatile or non-volatile. The BPNV bit is OTP and cleared to a0 with the BP bits cleared to
000 when shipped from Spansion. When BPNV is set to a 0 the BP2-0 bits in the Status Register are nonvolatile. When BPNV is set to a 1 the BP2-0 bits in the Status Register are volatile and will be reset to binary
111 after POR, hardware reset, or command reset. If BPNV is programmed to 1, an attempt to change it back
to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).
CR1[2]: Reserved for Future Use.
Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit Quad mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The WP# and HOLD# inputs are not
monitored for their normal functions and are internally set to high (inactive). The commands for Serial, Dual
Output, and Dual I/O Read still function normally but, there is no need to drive WP# and Hold# inputs for
those commands when switching between commands using different data path widths. The QUAD bit must
be set to one when using Read Quad Out, Quad I/O Read, Read DDR Quad I/O, and Quad Page Program
commands. The QUAD bit is non-volatile.
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Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to 1, locks the current state of the BP2-0 bits
in Status Register, the TBPROT and TBPARM bits in the Configuration Register, and the OTP address
space. This prevents writing, programming, or erasing these areas. As long as the FREEZE bit remains
cleared to logic 0 the other bits of the Configuration Register, including FREEZE, are writable, and the OTP
address space is programmable. Once the FREEZE bit has been written to a logic 1 it can only be cleared to
a logic 0 by a power-off to power-on cycle or a hardware reset. Software reset will not affect the state of the
FREEZE bit. The FREEZE bit is volatile and the default state of FREEZE after power-on is 0. The FREEZE bit
can be set in parallel with updating other values in CR1 by a single WRR command.
8.6.3
Status Register 2 (SR2)
Related Commands: Read Status Register 2 (RDSR2 07h).
Table 8.9 Status Register-2 (SR2)
Bits
Field Name
Function
7
RFU
Reserved
Type
Default State
6
RFU
Reserved
0
Reserved for Future Use
5
RFU
Reserved
0
Reserved for Future Use
4
RFU
Reserved
0
Reserved for Future Use
3
RFU
Reserved
0
Reserved for Future Use
2
RFU
Reserved
0
Reserved for Future Use
0
Description
Reserved for Future Use
1
ES
Erase Suspend
Volatile, Read only
0
1 = In erase suspend mode
0 = Not in erase suspend mode
0
PS
Program
Suspend
Volatile, Read only
0
1 = In program suspend mode
0 = Not in program suspend mode
Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase
Suspend mode. This is a status bit that cannot be written. When Erase Suspend bit is set to 1, the device is in
erase suspend mode. When Erase Suspend bit is cleared to 0, the device is not in erase suspend mode.
Refer to Erase Suspend and Resume Commands (75h) (7Ah) for details about the Erase Suspend/Resume
commands.
Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in
Program Suspend mode. This is a status bit that cannot be written. When Program Suspend bit is set to 1, the
device is in program suspend mode. When the Program Suspend bit is cleared to 0, the device is not in
program suspend mode. Refer to Program Suspend (PGSP 85h) and Resume (PGRS 8Ah) on page 106 for
details.
8.6.4
AutoBoot Register
Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).
The AutoBoot Register provides a means to automatically read boot code as part of the power on reset,
hardware reset, or software reset process.
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Table 8.10 AutoBoot Register
8.6.5
Bits
Field Name
Function
Type
Default State
31 to 9
ABSA
AutoBoot Start
Address
Non-Volatile
000000h
8 to 1
ABSD
AutoBoot Start Delay
Non-Volatile
00h
0
ABE
AutoBoot Enable
Non-Volatile
0
Description
512 byte boundary address for the start of
boot code access
Number of initial delay cycles between CS#
going low and the first bit of boot code being
transferred
1 = AutoBoot is enabled
0 = AutoBoot is not enabled
Bank Address Register
Related Commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read
(BRRD 16h) and Bank Register Write (BRWR 17h).
The Bank Address register supplies additional high order bits of the main flash array byte boundary address
for legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high
bits of address (above A23) for all 3-byte address commands when EXTADD=0. The Bank Address is not
used when EXTADD = 1 and traditional 3-byte address commands are instead required to provide all four
bytes of address.
Table 8.11 Bank Address Register (BAR)
Bits
7
Field Name
EXTADD
Function
Extended Address
Enable
Type
Default State
Volatile
0b
Description
1 = 4-byte (32-bits) addressing required from command.
0 = 3-byte (24-bits) addressing from command + Bank
Address
6 to 2
RFU
Reserved
Volatile
00000b
1
BA25
Bank Address
Volatile
0
Reserved for Future Use
A25 for 512 Mb device
0
BA24
Bank Address
Volatile
0
A24 for 512 Mb device
Extended Address (EXTADD) BAR[7]: EXTADD controls the address field size for legacy SPI commands. By
default (power up reset, hardware reset, and software reset), it is cleared to 0 for 3 bytes (24 bits) of address.
When set to 1, the legacy commands will require 4 bytes (32 bits) for the address field. This is a volatile bit.
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8.6.6
She et
ASP Register (ASPR)
Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh).
The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced
Sector Protection (ASP) features.
Table 8.12 ASP Register (ASPR)
Function
Type
Default
State
Bits
Field Name
Description
15 to 9
RFU
Reserved
OTP
1
Reserved for Future Use
8
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
7
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
6
RFU
Reserved
OTP
1
Reserved for Future Use
5
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
4
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
3
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
2
PWDMLB
Password
Protection Mode
Lock Bit
OTP
1
0 = Password Protection Mode permanently enabled.
1 = Password Protection Mode not permanently enabled.
1
PSTMLB
Persistent
Protection Mode
Lock Bit
OTP
1
0 = Persistent Protection Mode permanently enabled.
1 = Persistent Protection Mode not permanently enabled.
0
RFU
Reserved
OTP
1
Reserved for Future Use
Note:
1. Default value depends on ordering part number, see Initial Delivery State on page 141.
Reserved for Future Use (RFU) ASPR[15:3, 0].
Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password
Protection Mode is permanently selected.
Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent
Protection Mode is permanently selected. PWDMLB and PSTMLB are mutually exclusive, only one may be
programmed to zero.
8.6.7
Password Register (PASS)
Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h).
Table 8.13 Password Register (PASS)
8.6.8
Bits
Field
Name
Function
Type
Default State
Description
63 to 0
PWD
Hidden
Password
OTP
FFFFFFFFFFFFFFFFh
Non-volatile OTP storage of 64-bit password. The password is
no longer readable after the password protection mode is
selected by programming ASP register bit 2 to zero.
PPB Lock Register (PPBL)
Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h)
Table 8.14 PPB Lock Register (PPBL)
Bits
Field Name
Function
Type
Default State
7 to 1
RFU
Reserved
Volatile
00h
0
PPBLOCK
Protect PPB Array
Volatile
Persistent Protection Mode = 1
Password Protection Mode = 0
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S25FL512S
Description
Reserved for Future Use
0 = PPB array protected until next power cycle
or hardware reset
1 = PPB array may be programmed or erased.
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PPB Access Register (PPBAR)
Related Commands: PPB Read (PPBRD E2h)
Table 8.15 PPB Access Register (PPBAR)
Bits
7 to 0
8.6.10
Field Name
PPB
Function
Type
Read or Program per
sector PPB
Non-volatile
Default
State
FFh
Description
00h = PPB for the sector addressed by the PPBRD or
PPBP command is programmed to 0, protecting that
sector from program or erase operations.
FFh = PPB for the sector addressed by the PPBRD or
PPBP command is erased to 1, not protecting that
sector from program or erase operations.
DYB Access Register (DYBAR)
Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h).
Table 8.16 DYB Access Register (DYBAR)
Bits
7 to 0
8.6.11
Field Name
DYB
Function
Read or Write
per sector DYB
Type
Default State
Volatile
FFh
Description
00h = DYB for the sector addressed by the DYBRD or DYBP
command is cleared to 0, protecting that sector from program or
erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBP
command is set to 1, not protecting that sector from program or
erase operations.
SPI DDR Data Learning Registers
Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern
Read (DLPRD 41h).
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as
an 8-bit Volatile Data Learning Register (VDLR). When shipped from Spansion, the NVDLR value is 00h.
Once programmed, the NVDLR cannot be reprogrammed or erased; a copy of the data pattern in the NVDLR
will also be written to the VDLR. The VDLR can be written to at any time, but on reset or power cycles the
data pattern will revert back to what is in the NVDLR. During the learning phase described in the SPI DDR
modes, the DLP will come from the VDLR. Each IO will output the same DLP value for every clock edge. For
example, if the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0;
subsequently, the 2nd clock edge all I/O’s will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR
commands.
Table 8.17 Non-Volatile Data Learning Register (NVDLR)
Bits
7 to 0
Field Name
NVDLP
Function
Non-Volatile
Data Learning
Pattern
Type
Default State
OTP
00h
Description
OTP value that may be transferred to the host during DDR read
command latency (dummy) cycles to provide a training pattern to
help the host more accurately center the data capture point in the
received data bits.
Table 8.18 Volatile Data Learning Register (NVDLR)
Bits
7 to 0
64
Field Name
VDLP
Function
Volatile Data
Learning
Pattern
Type
Default State
Volatile
Takes the
value of
NVDLR
during POR
or Reset
S25FL512S
Description
Volatile copy of the NVDLP used to enable and deliver the Data
Learning Pattern (DLP) to the outputs. The VDLP may be changed
by the host during system operation.
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Data
9.
She et
Data Protection
9.1
Secure Silicon Region (OTP)
The device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash
array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.
The OTP memory space is intended for increased system security. OTP values can “mate” a flash
component with the system CPU/ASIC to prevent device substitution. See OTP Address Space on page 55,
One Time Program Array Commands on page 111, and OTP Read (OTPR 4Bh): on page 111.
9.1.1
Reading OTP Memory Space
The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-kB
OTP address range will yield indeterminate data.
9.1.2
Programming OTP Memory Space
The protocol of the OTP programming command is the same as Page Program. The OTP Program command
can be issued multiple times to any given OTP address, but this address space can never be erased. The
valid address range for OTP Program is depicted in Figure 8.1, OTP Address Space on page 56. OTP
Program operations outside the valid OTP address range will be ignored and the WEL in SR1 will remain high
(set to 1). OTP Program operations while FREEZE = 1 will fail with P_ERR in SR1 set to 1.
9.1.3
Spansion Programmed Random Number
Spansion standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to
0xF) with a 128-bit random number using the Linear Congruential Random Number Method. The seed value
for the algorithm is a random number concatenated with the day and time of tester insertion.
9.1.4
Lock Bytes
The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the
highest address region related to the byte. The next higher address byte similarly protects the next higher 8
regions. The LSB bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest
address region. In other words, the LSB of location 0x10 protects all the Lock Bytes and RFU bytes in the
lowest address region from further programming. See Section 8.5, OTP Address Space on page 55.
9.2
Write Enable Command
The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data.
The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes)
during power-up, hardware reset, or after the device completes the following commands:
– Reset
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Registers (WRR)
– Quad-input Page Programming (QPP)
– OTP Byte Programming (OTPP)
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S hee t
Block Protection
The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register
TBPROT bit can be used to protect an address range of the main flash array from program and erase
operations. The size of the range is determined by the value of the BP bits and the upper or lower starting
point of the range is selected by the TBPROT bit of the configuration register.
Table 9.1 Upper Array Start of Protection (TBPROT = 0)
Status Register Content
Protected Fraction of Memory Array
Protected Memory (kbytes)
FL512S
512 Mb
BP2
BP1
BP0
0
0
0
None
0
0
0
1
Upper 64th
1024
0
1
0
Upper 32nd
2048
0
1
1
Upper 16th
4096
1
0
0
Upper 8th
8192
1
0
1
Upper 4th
16384
1
1
0
Upper Half
32768
1
1
1
All Sectors
65536
Table 9.2 Lower Array Start of Protection (TBPROT = 1)
Status Register Content
Protected Fraction of Memory Array
Protected Memory (kbytes)
FL512S
512 Mb
None
0
1024
BP2
BP1
BP0
0
0
0
0
0
1
Lower 64th
0
1
0
Lower 32nd
2048
0
1
1
Lower 16th
4096
1
0
0
Lower 8th
8192
1
0
1
Lower 4th
16384
1
1
0
Lower Half
32768
1
1
1
All Sectors
65536
When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still
be used to protect sectors not protected by the Block Protection scheme. In the case that both ASP and Block
Protection are used on the same sector the logical OR of ASP and Block Protection related to the sector is
used. Recommendation: ASP and Block Protection should not be used concurrently. Use one or the other,
but not both.
9.3.1
Freeze bit
Bit0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register
1 and the TBPROT bit in the Configuration Register to their value at the time the FREEZE bit is set to 1. Once
the FREEZE bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is
executed. As long as the FREEZE bit is cleared to logic 0 the status register BP bits and the TBPROT bit of
the Configuration Register are writable. The FREEZE bit also protects the entire OTP memory space from
programming when set to 1. Any attempt to change the BP bits with the WRR command while FREEZE = 1 is
ignored and no error status is set.
9.3.2
Write Protect Signal
The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit provide
hardware input signal controlled protection. When WP# is Low and SRWD is set to 1 the Status and
Configuration register is protected from alteration. This prevents disabling or changing the protection defined
by the Block Protect bits.
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Advanced Sector Protection
Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software
methods used to disable or enable programming or erase operations, individually, in any or all sectors. An
overview of these methods is shown in Figure 9.1, Advanced Sector Protection Overview on page 67.
Block Protection and ASP protection settings for each sector are logically OR’d to define the protection for
each sector, i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. Refer
to Block Protection on page 66 for full details of the BP2-0 bits.
Figure 9.1 Advanced Sector Protection Overview
ASP Register
One Time Programmable
Password Method Persistent Method
(ASPR[2]=0)
6.) Password Method requires a
password to set PPB Lock to “1”
to enable program or erase of
PPB bits
(ASPR[1]=0)
7.) Persistent Method only allows
PPB Lock to be cleared to “0” to
prevent program or erase of PPB
bits. Power off or hardware reset
required to set PPB Lock to “1”
64 -bit Password
(One Time Protect)
4.) PPB Lock bit is volatile and
defaults to “1” (persistent
mode).or “0” (password mode)
upon reset
PBB Lock Bit
“0” = PPBs locked
Memory Array
“1”=PPBs unlocked
Persistent
Protection Bits
Bit
(PPB)
Dynamic
Protection Bits
Bit
(DYB)
Sector 0
PPB 0
DYB 0
Sector 1
PPB 1
DYB 1
Sector 2
PPB 2
DYB 2
Sector N -2
PPB N -2
DYB N -2
Sector N -1
PPB N -1
DYB N -1
Sector N
PPB N
DYB N
1.) N = Highest Address Sector,
Sector
a sector is protected if its PPB =”0”
or its DYB = “0”
2.) PPB are programmed individually
but erased as a group
5.) PPB Lock = “0” locks all PPBs
to their current state
3.) DYB are volatile bits
Every main flash array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it.
When either bit is 0, the sector is protected from program and erase operations.
The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for
managing the state of the PPB Lock bit, Persistent Protection and Password Protection.
The Persistent Protection method sets the PPB Lock bit to 1 during POR, or Hardware Reset so that the PPB
bits are unprotected by a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB.
There is no command in the Persistent Protection method to set the PPB Lock bit to 1, therefore the PPB
Lock bit will remain at 0 until the next power-off or hardware reset. The Persistent Protection method allows
boot code the option of changing sector protection by programming or erasing the PPB, then protecting the
PPB from further change for the remainder of normal system operation by clearing the PPB Lock bit to 0. This
is sometimes called Boot-code controlled sector protection.
The Password method clears the PPB Lock bit to 0 during POR, or Hardware Reset to protect the PPB. A
64-bit password may be permanently programmed and hidden for the password method. A command can be
used to provide a password for comparison with the hidden password. If the password matches, the PPB
Lock bit is set to 1 to unprotect the PPB. A command can be used to clear the PPB Lock bit to 0. This method
requires use of a password to control PPB protection.
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The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP
Register so as to permanently select the method used.
9.4.1
ASP Register
The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP)
features. See Table 8.12, ASP Register (ASPR) on page 63.
As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors
unprotected, when power is applied. The device programmer or host system must then choose which sector
protection method to use. Programming either of the, one-time programmable, Protection Mode Lock Bits,
locks the part permanently in the selected mode:
 ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.
 ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.
 ASPR[2:1] = 01 = Password Protection Mode permanently selected.
 ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure.
ASP register programming rules:
 If the password mode is chosen, the password must be programmed prior to setting the Protection Mode
Lock Bits.
 Once the Protection Mode is selected, the Protection Mode Lock Bits are permanently protected from
programming and no further changes to the ASP register is allowed.
The programming time of the ASP Register is the same as the typical page programming time. The system
can determine the status of the ASP register programming operation by reading the WIP bit in the Status
Register. See Status Register 1 (SR1) on page 57 for information on WIP.
After selecting a sector protection method, each sector can operate in each of the following states:
 Dynamically Locked — A sector is protected and can be changed by a simple command.
 Persistently Locked — A sector is protected and cannot be changed if its PPB Bit is 0.
 Unlocked — The sector is unprotected and can be changed by a simple command.
9.4.2
Persistent Protection Bits
The Persistent Protection Bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is
related to each sector. When a PPB is 0, its related sector is protected from program and erase operations.
The PPB are programmed individually but must be erased as a group, similar to the way individual words may
be programmed in the main array but an entire sector must be erased at the same time. The PPB have the
same program and erase endurance as the main flash memory array. Preprogramming and verification prior
to erasure are handled by the device.
Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical
sector erase time. During PPB bit programming and PPB bit erasing, status is available by reading the Status
register. Reading of a PPB bit requires the initial access time of the device.
Notes:
1. Each PPB is individually programmed to 0 and all are erased to 1 in parallel.
2. If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails without programming or erasing the PPB.
3. The state of the PPB for a given sector can be verified by using the PPB Read command.
9.4.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYB only
control the protection for sectors that have their PPB set to 1. By issuing the DYB Write command, a DYB is
cleared to 0 or set to 1, thus placing each sector in the protected or unprotected state respectively. This
feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy
removal of protection when changes are needed. The DYBs can be set or cleared as often as needed as they
are volatile bits.
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PPB Lock Bit (PPBL[0])
The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs and when set
to 1, it allows the PPBs to be changed.
The PLBWR command is used to clear the PPB Lock bit to 0. The PPB Lock Bit must be cleared to 0 only
after all the PPBs are configured to the desired settings.
In Persistent Protection mode, the PPB Lock is set to 1 during POR or a hardware reset. When cleared to 0,
no software command sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can
set the PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or a hardware reset. The PPB
Lock bit can only be set to 1 by the Password Unlock command.
9.4.5
Sector Protection States Summary
Each sector can be in one of the following protection states:
 Unlocked — The sector is unprotected and protection can be changed by a simple command. The
protection state defaults to unprotected after a power cycle, software reset, or hardware reset.
 Dynamically Locked — A sector is protected and protection can be changed by a simple command. The
protection state is not saved across a power cycle or reset.
 Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock Bit is set
to 1. The protection state is non-volatile and saved across a power cycle or reset. Changing the protection
state requires programming and or erase of the PPB bits
Table 9.3 Sector Protection States
Protection Bit Values
Sector State
9.4.6
PPB Lock
PPB
DYB
1
1
1
Unprotected – PPB and DYB are changeable
1
1
0
Protected – PPB and DYB are changeable
1
0
1
Protected – PPB and DYB are changeable
1
0
0
Protected – PPB and DYB are changeable
0
1
1
Unprotected – PPB not changeable, DYB is changeable
0
1
0
Protected – PPB not changeable, DYB is changeable
0
0
1
Protected – PPB not changeable, DYB is changeable
0
0
0
Protected – PPB not changeable, DYB is changeable
Persistent Protection Mode
The Persistent Protection method sets the PPB Lock bit to 1 during POR or Hardware Reset so that the PPB
bits are unprotected by a device hardware reset. Software reset does not affect the PPB Lock bit. The
PLBWR command can clear the PPB Lock bit to 0 to protect the PPB. There is no command to set the PPB
Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.
9.4.7
Password Protection Mode
Password Protection Mode allows an even higher level of security than the Persistent Sector Protection
Mode, by requiring a 64-bit password for unlocking the PPB Lock bit. In addition to this password
requirement, after power up and hardware reset, the PPB Lock bit is cleared to 0 to ensure protection at
power-up. Successful execution of the Password Unlock command by entering the entire password clears the
PPB Lock bit, allowing for sector PPB modifications.
Password Protection Notes:
 Once the Password is programmed and verified, the Password Mode (ASPR[2]=0) must be set in order to
prevent reading the password.
 The Password Program Command is only capable of programming ‘0’s. Programming a 1 after a cell is
programmed as a 0 results in the cell left as a 0 with no programming error set.
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 The password is all 1’s when shipped from Spansion. It is located in its own memory space and is
accessible through the use of the Password Program and Password Read commands.
 All 64-bit password combinations are valid as a password.
 The Password Mode, once programmed, prevents reading the 64-bit password and further password
programming. All further program and read commands to the password region are disabled and these
commands are ignored. There is no means to verify what the password is after the Password Mode Lock
Bit is selected. Password verification is only allowed before selecting the Password Protection mode.
 The Protection Mode Lock Bits are not erasable.
 The exact password must be entered in order for the unlocking function to occur. If the password unlock
command provided password does not match the hidden internal password, the unlock operation fails in
the same manner as a programming operation on a protected sector. The P_ERR bit is set to one and the
WIP Bit remains set. In this case it is a failure to change the state of the PPB Lock bit because it is still
protected by the lack of a valid password.
 The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This
makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit
combinations in an attempt to correctly match a password. The Read Status Register 1 command may be
used to read the WIP bit to determine when the device has completed the password unlock command or is
ready to accept a new password command. When a valid password is provided the password unlock
command does not insert the 100 µs delay before returning the WIP bit to zero.
 If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.
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10. Commands
All communication between the host system and the S25FL512S memory device is in the form of units called
commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be
performed. Commands may also have an address, instruction modifier, latency period, data transfer to the
memory, or data transfer from the memory. All instruction, address, and data information is transferred
serially between the host system and memory device.
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back
to the host serially on SO signal.
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be
returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,
and IO3.
Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1
or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0
and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Commands are structured as follows:
 Each command begins with an eight bit (byte) instruction.
 The instruction may be stand alone or may be followed by address bits to select a location within one of
several address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.
 The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data
information to be done one, two, or four bits in parallel. This enables a trade off between the number of
signal connections (IO bus width) and the speed of information transfer. If the host system can support a
two or four bit wide IO bus the memory performance can be increased by using the instructions that
provide parallel two bit (dual) or parallel four bit (quad) transfers.
 The width of all transfers following the instruction are determined by the instruction sent.
 All sIngle bits or parallel bit groups are transferred in most to least significant bit order.
 Some instructions send instruction modifier (mode) bits following the address to indicate that the next
command will be of the same type with an implied, rather than an explicit, instruction. The next command
thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed
to send each command when the same command type is repeated in a sequence of commands.
 The address or mode bits may be followed by write data to be stored in the memory device or by a read
latency period before read data is returned to the host.
 Read latency may be zero to several SCK cycles (also referred to as dummy cycles).
 All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted
into the device with the most significant byte first. All data is transferred with the lowest address byte sent
first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address
increments.
 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded
operations) are ignored. The embedded operation will continue to execute without any affect. A very
limited set of commands are accepted during an embedded operation. These are discussed in the
individual command descriptions. While a program, erase, or write operation is in progress, it is
recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the
device, to ensure the new command can be accepted.
 Depending on the command, the time for execution varies. A command to read status information from an
executing command is available to determine when the command completes execution and whether the
command was successful.
 Although host software in some cases is used to directly control the SPI interface signals, the hardware
interfaces of the host system and the memory device generally handle the details of signal relationships
and timing. For this reason, signal relationships and timing are not covered in detail within this software
interface focused section of the document. Instead, the focus is on the logical sequence of bits transferred
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in each command rather than the signal timing and relationships. Following are some general signal
relationship descriptions to keep in mind. For additional information on the bit level format and signal timing
relationships of commands, see Command Protocol on page 22.
– The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single
bit wide transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and
memory alternately drive the IO0-IO3 signals during Dual and Quad transfers.
– All commands begin with the host selecting the memory by driving CS# low before the first rising edge
of SCK. CS# is kept low throughout a command and when CS# is returned high the command ends.
Generally, CS# remains low for eight bit transfer multiples to transfer byte granularity information.
Some commands will not be accepted if CS# is returned high not at an 8 bit boundary.
10.1
Command Set Summary
10.1.1
Extended Addressing
To accommodate addressing above 128 Mb, there are three options:
1. New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.
72
Instruction Name
Description
Code (Hex)
4FAST_READ
Read Fast (4-byte Address)
0C
4READ
Read (4-byte Address)
13
4DOR
Read Dual Out (4-byte Address)
3C
4QOR
Read Quad Out (4-byte Address)
6C
4DIOR
Dual I/O Read (4-byte Address)
BC
4QIOR
Quad I/O Read (4-byte Address)
EC
4DDRFR
Read DDR Fast (4-byte Address)
0E
4DDRDIOR
DDR Dual I/O Read (4-byte Address)
BE
4DDRQIOR
DDR Quad I/O Read (4-byte Address)
EE
4PP
Page Program (4-byte Address)
12
4QPP
Quad Page Program (4-byte Address)
34
4SE
Erase 256 kB (4-byte Address)
DC
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2. For backward compatibility to the 3-byte address instructions, the standard instructions can be
used in conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7]
is cleared to 0 (following power up and hardware reset), to enable 3-byte (24-bit) addressing. When
set to 1, the legacy commands are changed to require 4 bytes (32 bits) for the address field. The
following instructions can be used in conjunction with EXTADD bit to switch from 3 bytes to 4 bytes
of address field.
Instruction Name
Description
Code (Hex)
READ
Read (3-byte Address)
03
FAST_READ
Read Fast (3-byte Address)
0B
DOR
Read Dual Out (3-byte Address)
3B
QOR
Read Quad Out (3-byte Address)
6B
DIOR
Dual I/O Read (3-byte Address)
BB
QIOR
Quad I/O Read (3-byte Address)
EB
DDRFR
Read DDR Fast (3-byte Address)
0D
DDRDIOR
DDR Dual I/O Read (3-byte Address)
BD
DDRQIOR
DDR Quad I/O Read (3-byte Address)
ED
PP
Page Program (3-byte Address)
02
QPP
Quad Page Program (3-byte Address)
32
SE
Erase 256 kB (3-byte Address)
D8
3. For backward compatibility to the 3-byte addressing, the standard instructions can be used in
conjunction with the Bank Address Register:
a. The Bank Address Register is used to switch between 128-Mbit (16-Mbyte) banks of memory,
The standard 3-byte address selects an address within the bank selected by the Bank Address
Register.
i. The host system writes the Bank Address Register to access beyond the first 128 Mbits of
memory.
ii. This applies to read, erase, and program commands.
b. The Bank Register provides the high order (4th) byte of address, which is used to address the
available memory at addresses greater than 16 Mbytes.
c. Bank Register bits are volatile.
i. On power up, the default is Bank0 (the lowest address 16 Mbytes).
d. For Read, the device will continuously transfer out data until the end of the array.
i. There is no bank to bank delay.
ii. The Bank Address Register is not updated.
iii. The Bank Address Register value is used only for the initial address of an access.
Table 10.1 Bank Address Map
Bank Address Register Bits
Bank
Memory Array Address Range (Hex)
Bit 1
Bit 0
0
0
0
00000000
00FFFFFF
0
1
1
01000000
01FFFFFF
1
0
2
02000000
02FFFFFF
1
1
3
03000000
03FFFFFF
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Table 10.2 S25FL512S Command Set (sorted by function) (Sheet 1 of 2)
Function
Instruction
Value (Hex)
Maximum
Frequency
(MHz)(1)
Read Electronic Manufacturer Signature
90
133
RDID
Read ID (JEDEC Manufacturer ID and JEDEC CFI)
9F
133
RES
Command
Name
READ_ID
(REMS)
Read Device
Identification
Register Access
Command Description
Read Electronic Signature
AB
50
RSFDP
Read Serial Flash Discoverable Parameters
5A
133
RDSR1
Read Status Register-1
05
133
RDSR2
Read Status Register-2
07
133
RDCR
Read Configuration Register-1
35
133
WRR
Write Register (Status-1, Configuration-1)
01
133
WRDI
Write Disable
04
133
WREN
Write Enable
06
133
CLSR
Clear Status Register-1 - Erase/Prog. Fail Reset
30
133
ABRD
AutoBoot Register Read
14
133
(QUAD=0)
104
(QUAD=1)
ABWR
AutoBoot Register Write
15
133
BRRD
Bank Register Read
16
133
BRWR
Bank Register Write
17
133
BRAC
Bank Register Access
(Legacy Command formerly used for Deep Power Down)
B9
133
133
Data Learning Pattern Read
41
PNVDLR
DLPRD
Program NV Data Learning Register
43
133
WVDLR
Write Volatile Data Learning Register
4A
133
READ
Read (3- or 4-byte address)
03
50
4READ
Read (4-byte address)
13
50
FAST_READ
Fast Read (3- or 4-byte address)
0B
133
4FAST_READ
Fast Read (4-byte address)
0C
133
DDRFR
DDR Fast Read (3- or 4-byte address)
0D
80
4DDRFR
DDR Fast Read (4-byte address)
0E
80
DOR
Read Dual Out (3- or 4-byte address)
3B
104
4DOR
Read Dual Out (4-byte address)
3C
104
QOR
Read Quad Out (3- or 4-byte address)
6B
104
4QOR
Read Quad Out (4-byte address)
6C
104
DIOR
Dual I/O Read (3- or 4-byte address)
BB
104
4DIOR
Dual I/O Read (4-byte address)
BC
104
Read Flash Array
Program Flash
Array
74
DDRDIOR
DDR Dual I/O Read (3- or 4-byte address)
BD
80
4DDRDIOR
DDR Dual I/O Read (4-byte address)
BE
80
QIOR
Quad I/O Read (3- or 4-byte address)
EB
104
4QIOR
Quad I/O Read (4-byte address)
EC
104
80
DDRQIOR
DDR Quad I/O Read (3- or 4-byte address)
ED
4DDRQIOR
DDR Quad I/O Read (4-byte address)
EE
80
PP
Page Program (3- or 4-byte address)
02
133
4PP
Page Program (4-byte address)
12
133
QPP
Quad Page Program (3- or 4-byte address)
32
80
QPP
Quad Page Program - Alternate instruction (3- or 4-byte address)
38
80
4QPP
Quad Page Program (4-byte address)
34
80
PGSP
Program Suspend
85
133
PGRS
Program Resume
8A
133
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Table 10.2 S25FL512S Command Set (sorted by function) (Sheet 2 of 2)
Function
Erase Flash
Array
Command
Name
Advanced Sector
Protection
Instruction
Value (Hex)
Maximum
Frequency
(MHz)(1)
133
BE
Bulk Erase
60
BE
Bulk Erase (alternate command)
C7
133
SE
Erase 256 kB (3- or 4-byte address)
D8
133
4SE
Erase 256 kB (4-byte address)
DC
133
Erase Suspend
75
133
ERRS
Erase Resume
7A
133
OTPP
OTP Program
42
133
ERSP
One Time
Program Array
Command Description
OTPR
OTP Read
4B
133
DYBRD
DYB Read
E0
133
DYBWR
DYB Write
E1
133
PPBRD
PPB Read
E2
133
PPBP
PPB Program
E3
133
PPBE
PPB Erase
E4
133
ASPRD
ASP Read
2B
133
ASP Program
2F
133
ASPP
PLBRD
PPB Lock Bit Read
A7
133
PLBWR
PPB Lock Bit Write
A6
133
PASSRD
Password Read
E7
133
PASSP
Password Program
E8
133
PASSU
Password Unlock
E9
133
RESET
Software Reset
F0
133
MBR
Mode Bit Reset
FF
133
MPM
Reserved for Multi-I/O-High Perf Mode (MPM)
A3
133
Reset
Reserved for
Future Use
RFU
Reserved-18
Reserved
18
RFU
Reserved-E5
Reserved
E5
RFU
Reserved-E6
Reserved
E6
Note:
1. For Automotive In-Cabin temperature range (-40°C to +105°C), all Maximum frequency values are 5% slower than the Max values shown.
10.1.2
Read Device Identification
There are multiple commands to read information about the device manufacturer, device type, and device
features. SPI memories from different vendors have used different commands and formats for reading
information about the memories. The S25FL512S device supports the three most common device information
commands.
10.1.3
Register Read or Write
There are multiple registers for reporting embedded operation status or controlling device configuration
options. There are commands for reading or writing these registers. Registers contain both volatile and nonvolatile bits. Non-volatile bits in registers are automatically erased and programmed as a single (write)
operation.
10.1.3.1
Monitoring Operation Status
The host system can determine when a write, program, erase, suspend or other embedded operation is
complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status
Register-1 command provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR)
bits in the status register indicate whether the most recent program or erase command has not completed
successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the
device remains busy. Under this condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET
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commands are valid commands. A Clear Status Register (CLSR) followed by a Write Disable (WRDI)
command must be sent to return the device to standby state. CLSR clears the WIP, P_ERR, and E_ERR bits.
WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software Reset (RESET) may be used to return
the device to standby state.
10.1.3.2
Configuration
There are commands to read, write, and protect registers that control interface path width, interface timing,
interface address length, and some aspects of data protection.
10.1.4
Read Flash Array
Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from
incrementally higher byte addresses until the host ends the data transfer by driving CS# input High. If the byte
address reaches the maximum address of the memory array, the read will continue at address zero of the
array.
There are several different read commands to specify different access latency and data path widths. Double
Data Rate (DDR) commands also define the address and data bit relationship to both SCK edges:
 The Read command provides a single address bit per SCK rising edge on the SI signal with read data
returning a single bit per SCK falling edge on the SO signal. This command has zero latency between the
address and the returning data but is limited to a maximum SCK rate of 50 MHz.
 Other read commands have a latency period between the address and returning data but can operate at
higher SCK frequencies. The latency depends on the configuration register latency code.
 The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data
returning a single bit per SCK falling edge on the SO signal and may operate up to 133 MHz.
 Dual or Quad Output read commands provide address a single bit per SCK rising edge on the SI / IO0
signal with read data returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.
 Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data
returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.
 Fast (Single), Dual, or Quad Double Data Rate read commands provide address one bit, two bits or four
bits per every SCK edge with read data returning one bit, two bits, or four bits of data per every SCK edge
on the IO0-IO3 signals. Double Data Rate (DDR) operation is only supported for core and I/O voltages of
3 to 3.6V.
10.1.5
Program Flash Array
Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The
Page Program command accepts from 1 byte up to 512 consecutive bytes of data (page) to be programmed
in one operation. Programming means that bits can either be left at 1, or programmed from 1 to 0. Changing
bits from 0 to 1 requires an erase operation.
10.1.6
Erase Flash Array
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. A bit needs to be first erased to 1 before programming can change it to a 0. While bits can be individually
programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE)
level.
10.1.7
OTP, Block Protection, and Advanced Sector Protection
There are commands to read and program a separate One TIme Programmable (OTP) array for permanent
data such as a serial number. There are commands to control a contiguous group (block) of flash memory
array sectors that are protected from program and erase operations. There are commands to control which
individual flash memory array sectors are protected from program and erase operations.
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10.1.8
She et
Reset
There is a command to reset to the default conditions present after power on to the device. There is a
command to reset (exit from) the Enhanced Performance Read Modes.
10.1.9
Reserved
Some instructions are reserved for future use. In this generation of the S25FL512S some of these command
instructions may be unused and not affect device operation, some may have undefined results.
Some commands are reserved to ensure that a legacy or alternate source device command is allowed
without affect. This allows legacy software to issue some commands that are not relevant for the current
generation S25FL512S device with the assurance these commands do not cause some unexpected action.
Some commands are reserved for use in special versions of the FL-S not addressed by this document or for
a future generation. This allows new host memory controller designs to plan the flexibility to issue these
command instructions. The command format is defined if known at the time this document revision is
published.
10.2
Identification Commands
10.2.1
Read Identification - REMS (Read_ID or REMS 90h)
The READ_ID command identifies the Device Manufacturer ID and the Device ID. The command is also
referred to as Read Electronic Manufacturer and device Signature (REMS). READ-ID (REMS) is only
supported for backward compatibility and should not be used for new software designs. New software
designs should instead make use of the RDID command.
The command is initiated by shifting on SI the instruction code “90h” followed by a 24-bit address of 00000h.
Following this, the Manufacturer ID and the Device ID are shifted out on SO starting at the falling edge of SCK
after address. The Manufacturer ID and the Device ID are always shifted out with the MSB first. If the 24-bit
address is set to 000001h, then the Device ID is read out first followed by the Manufacturer ID. The
Manufacturer ID and Device ID output data toggles between address 000000H and 000001H until terminated
by a low to high transition on CS# input. The maximum clock frequency for the READ_ID command is
133 MHz.
Figure 10.1 READ_ID (90h) Command Sequence
CS#
SCK
SI
7
6
5
4 3
2
1 0 23
1 0
SO
Phase
7
Instruction (90h)
Address
6 5 4 3 2 1
Manufacturer ID
0
7 6
5 4 3 2 1 0
Device ID
Table 10.3 Read_ID Values
Device
Manufacturer ID (hex)
Device ID (hex)
S25FL512S
01
19
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Read Identification (RDID 9Fh):
The Read Identification (RDID) command provides read access to manufacturer identification, device
identification, and Common Flash Interface (CFI) information. The manufacturer identification is assigned by
JEDEC. The CFI structure is defined by JEDEC standard. The device identification and CFI values are
assigned by Spansion.
The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows
a vendor-specified software flash management program (driver) to be used for entire families of flash devices.
Software support can then be device-independent, JEDEC manufacturer ID independent, forward and
backward-compatible for the specified flash device families. System vendors can standardize their flash
drivers for long-term software compatibility by using the CFI values to configure a family driver from the CFI
information of the device in use.
Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect
on execution of the program, erase, or write cycle that is in progress.
The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte
of manufacturer identification, two bytes of device identification, extended device identification, and CFI
information will be shifted sequentially out on SO. As a whole this information is referred to as ID-CFI. See IDCFI Address Space on page 54 for the detail description of the ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data.
The RDID command sequence is terminated by driving CS# to the logic high state anytime during data
output.
The maximum clock frequency for the RDID command is 133 MHz.
Figure 10.2 Read Identification (RDID 9Fh) Command Sequence
CS#
SCK
SI
7
6
5
4
3
SO
Phase
10.2.3
2
1
0
7
6
5
Instruction
4
3
Data 1
2
1
0
7
6
5
4
3
2
1
0
Data N
Read Electronic Signature (RES) (ABh):
The RES command is used to read a single byte Electronic Signature from SO. RES is only supported for
backward compatibility and should not be used for new software designs. New software designs should
instead make use of the RDID command.
The RES instruction is shifted in followed by three dummy bytes onto SI. After the last bit of the three dummy
bytes are shifted into the device, a byte of Electronic Signature will be shifted out of SO. Each bit is shifted out
by the falling edge of SCK. The maximum clock frequency for the RES command is 50 MHz.
The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles.
The RES command sequence is terminated by driving CS# to the logic high state anytime during data output.
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Figure 10.3 Read Electronic Signature (RES ABh) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0 23
1 0
SO
7 6 5 4 3 2 1 0
Phase
Instruction (ABh)
Dummy
Device ID
Table 10.4 RES Values
10.2.4
Device
Device ID (hex)
S25FL512S
19
Read Serial Flash Discoverable Parameters (RSFDP 5Ah)
The command is initiated by shifting on SI the instruction code ‘5Ah’, followed by a 24-bit address of 000000h,
followed by eight dummy cycles. The SFDP bytes are then shifted out on SO starting at the falling edge of
SCK after the eight dummy cycles. The SFDP bytes are always shifted out with the MSB first. If the 24-bit
address is set to any other value, the selected location in the SFDP space is the starting point of the data
read. This enables random access to any parameter in the SFDP space. The maximum clock frequency for
the RSFDP command is 133 MHz.
Figure 10.4 RSFDP Command Sequence
CS#
SCK
SI
7
6
5
4 3
2
1 0 23
1 0
SO
Phase
10.3
7 6
Instruction
Address
Dummy Cycles
5
4
3
2 1
0
Data 1
Register Access Commands
10.3.1
Read Status Register-1 (RDSR1 05h):
The Read Status Register-1 (RDSR1) command allows the Status Register-1 contents to be read from SO.
The Status Register-1 contents may be read at any time, even while a program, erase, or write operation is in
progress. It is possible to read the Status Register-1 continuously by providing multiples of eight clock cycles.
The status is updated for each eight cycle read. The maximum clock frequency for the RDSR1 (05h)
command is 133 MHz.
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Figure 10.5 Read Status Register-1 (RDSR1 05h) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
10.3.2
Instruction
Status
Updated Status
Read Status Register-2 (RDSR2 07h):
The Read Status Register (RDSR2) command allows the Status Register-2 contents to be read from SO. The
Status Register-2 contents may be read at any time, even while a program, erase, or write operation is in
progress. It is possible to read the Status Register-2 continuously by providing multiples of eight clock cycles.
The status is updated for each eight cycle read. The maximum clock frequency for the RDSR2 command is
133 MHz.
Figure 10.6 Read Status Register-2 (RDSR2 07h) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
10.3.3
Instruction
Status
Updated Status
Read Configuration Register (RDCR 35h):
The Read Configuration Register (RDCR) command allows the Configuration Register contents to be read
from SO. It is possible to read the Configuration Register continuously by providing multiples of eight clock
cycles. The Configuration Register contents may be read at any time, even while a program, erase, or write
operation is in progress.
Figure 10.7 Read Configuration Register (RDCR 35h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.3.4
7
6
Instruction
5
4
3
Register Read
2
1
0
7
6
5
4
3
2
1
0
Repeat Register Read
Bank Register Read (BRRD 16h)
The Read the Bank Register (BRRD) command allows the Bank address Register contents to be read from
SO. The instruction is first shifted in from SI. Then the 8-bit Bank Register is shifted out on SO. It is possible
to read the Bank Register continuously by providing multiples of eight clock cycles. The maximum operating
clock frequency for the BRRD command is 133 MHz.
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Figure 10.8 Read Bank Register (BRRD 16h) Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
10.3.5
6
Instruction
Phase
5
4
3
2
1
0
7
Register Read
6
5
4
3
2
1
0
Repeat Register Read
Bank Register Write (BRWR 17h)
The Bank Register Write (BRWR) command is used to write address bits above A23, into the Bank Address
Register (BAR). The command is also used to write the Extended address control bit (EXTADD) that is also in
BAR[7]. BAR provides the high order addresses needed by devices having more than 128 Mbits (16 Mbytes),
when using 3-byte address commands without extended addressing enabled (BAR[7] EXTADD = 0).
Because this command is part of the addressing method and is not changing data in the flash memory, this
command does not require the WREN command to precede it.
The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in
length.
The BRWR command has no effect on the P_ERR, E_ERR or WIP bits of the Status and Configuration
Registers. Any bank address bit reserved for the future should always be written as a 0.
Figure 10.9 Bank Register Write (BRWR 17h) Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
10.3.6
Instruction
Input Data
Bank Register Access (BRAC B9h):
The Bank Register Read and Write commands provide full access to the Bank Address Register (BAR) but
they are both commands that are not present in legacy SPI memory devices. Host system SPI memory
controller interfaces may not be able to easily support such new commands. The Bank Register Access
(BRAC) command uses the same command code and format as the Deep Power Down (DPD) command that
is available in legacy SPI memories. The FL-S family does not support a DPD feature but assigns this legacy
command code to the BRAC command to enable write access to the Bank Address Register for legacy
systems that are able to send the legacy DPD (B9h) command.
When the BRAC command is sent, the FL-S family device will then interpret an immediately following Write
Register (WRR) command as a write to the lower address bits of the BAR. A WREN command is not used
between the BRAC and WRR commands. Only the lower two bits of the first data byte following the WRR
command code are used to load BAR[1:0]. The upper bits of that byte and the content of the optional WRR
command second data byte are ignored. Following the WRR command the access to BAR is closed and the
device interface returns to the standby state. The combined BRAC followed by WRR command sequence has
no affect on the value of the ExtAdd bit (BAR[7]).
Commands other than WRR may immediately follow BRAC and execute normally. However, any command
other than WRR, or any other sequence in which CS# goes low and returns high, following a BRAC
command, will close the access to BAR and return to the normal interpretation of a WRR command as a write
to Status Register-1 and the Configuration Register.
The BRAC + WRR sequence is allowed only when the device is in standby, program suspend, or erase
suspend states. This command sequence is illegal when the device is performing an embedded algorithm or
when the program (P_ERR) or erase (E_ERR) status bits are set to 1.
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Figure 10.10 BRAC (B9h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.3.7
Instruction
Write Registers (WRR 01h):
The Write Registers (WRR) command allows new values to be written to both the Status Register-1 and
Configuration Register. Before the Write Registers (WRR) command can be accepted by the device, a Write
Enable (WREN) command must be received. After the Write Enable (WREN) command has been decoded
successfully, the device will set the Write Enable Latch (WEL) in the Status Register to enable any write
operations.
The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The
Status Register is one data byte in length.
The Write Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR
operation. Any Status or Configuration Register bit reserved for the future must be written as a 0.
CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the
Write Registers (WRR) command is not executed. If CS# is driven high after the eighth cycle then only the
Status Register-1 is written; otherwise, after the sixteenth cycle both the Status and Configuration Registers
are written. When the configuration register QUAD bit CR[1] is 1, only the WRR command format with 16 data
bits may be used.
As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated.
While the Write Registers (WRR) operation is in progress, the Status Register may still be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed Write
Registers (WRR) operation, and is a 0 when it is completed. When the Write Registers (WRR) operation is
completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the WRR command
is 133 MHz.
Figure 10.11 Write Registers (WRR 01h) Command Sequence – 8 data bits
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Status Register-1
Figure 10.12 Write Registers (WRR 01h) Command Sequence – 16 data bits
CS#
SCK
SI
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SO
Phase
82
Instruction
Input Status Register-1
S25FL512S
Input Configuration Register
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The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1,
and BP0) bits to define the size of the area that is to be treated as read-only. The Write Registers (WRR)
command also allows the user to set the Status Register Write Disable (SRWD) bit to a 1 or a 0. The Status
Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow the BP bits to be hardware
protected.
When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is
possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been
set by a Write Enable (WREN) command, regardless of the whether Write Protect (WP#) signal is driven to
the logic high or logic low state.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be
considered, depending on the state of Write Protect (WP#):
 If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and
Configuration Registers provided that the Write Enable Latch (WEL) bit has previously been set to a “1” by
initiating a Write Enable (WREN) command.
 If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and
Configuration Registers even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write
Enable (WREN) command. Attempts to write to the Status and Configuration Registers are rejected, and
are not accepted for execution. As a consequence, all the data bytes in the memory area that are protected
by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected by WP#.
The WP# hardware protection can be provided:
 by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic
low state;
 or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable
(SRWD) bit to a 1.
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high
state. If WP# is permanently tied high, hardware protection of the BP bits can never be activated.
Table 10.5 Block Protection Modes
WP#
SRWD
Bit
1
1
1
0
0
0
0
1
Memory Content
Mode
Write Protection of Registers
Protected Area
Unprotected Area
Software
Protected
Status and Configuration Registers are Writable (if
WREN command has set the WEL bit). The values
in the SRWD, BP2, BP1, and BP0 bits and those in
the Configuration Register can be changed
Protected against
Page Program, Quad
Input Program,
Sector Erase, and
Bulk Erase
Ready to accept
Page Program, Quad
Input Program and
Sector Erase
commands
Hardware
Protected
Status and Configuration Registers are Hardware
Write Protected. The values in the SRWD, BP2,
BP1, and BP0 bits and those in the Configuration
Register cannot be changed
Protected against
Page Program,
Sector Erase, and
Bulk Erase
Ready to accept
Page Program or
Erase commands
Notes:
1. The Status Register originally shows 00h when the device is first shipped from Spansion to the customer.
2. Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP# becomes IO2; therefore, it
cannot be utilized.
The WRR command has an alternate function of loading the Bank Address Register if the command
immediately follows a BRAC command. See Bank Register Access (BRAC B9h): on page 81.
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Write Enable (WREN 06h)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1])
to a 1. The Write Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN) command to
enable write, program and erase commands.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched
in on SI, the write enable operation will not be executed.
Figure 10.13 Write Enable (WREN 06h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.3.9
Instruction
Write Disable (WRDI 04h):
The Write Disable (WRDI) command sets the Write Enable Latch (WEL) bit of the Status Register-1 (SR1[1])
to a 0.
The Write Enable Latch (WEL) bit may be set to a 0 by issuing the Write Disable (WRDI) command to disable
Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR), OTP Program (OTPP), and
other commands, that require WEL be set to 1 for execution. The WRDI command can be used by the user to
protect memory areas against inadvertent writes that can possibly corrupt the contents of the memory. The
WRDI command is ignored during an embedded operation while WIP bit =1.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched
in on SI, the write disable operation will not be executed.
Figure 10.14 Write Disable (WRDI 04h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
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Clear Status Register (CLSR 30h):
The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It
is not necessary to set the WEL bit before the Clear SR command is executed. The Clear SR command will
be accepted even when the device remains busy with WIP set to 1, as the device does remain busy when
either error bit is set. The WEL bit will be unchanged after this command is executed.
Figure 10.15 Clear Status Register (CLSR 30h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.3.11
Instruction
AutoBoot
SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command.
And, in order to read boot code from an SPI device, the host memory controller or processor must supply the
read command from a hardwired state machine or from some host processor internal ROM code.
Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time
to start reading boot code.
The AutoBoot feature allows the host memory controller to take boot code from an S25FL512S device
immediately after the end of reset, without having to send a read command. This saves 32 or more cycles and
simplifies the logic needed to initiate the reading of boot code.
 As part of the power up reset, hardware reset, or command reset process the AutoBoot feature
automatically starts a read access from a pre-specified address. At the time the reset process is
completed, the device is ready to deliver code from the starting address. The host memory controller only
needs to drive CS# signal from high to low and begin toggling the SCK signal. The S25FL512S device will
delay code output for a pre-specified number of clock cycles before code streams out.
– The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is
needed by the host.
– The host cannot send commands during this time.
– If ABSD = 0, the maximum SCK frequency is 50 MHz.
– If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is 0 or 104 MHz if the
QUAD bit is set to 1.
 The starting address of the boot code is selected by the value programmed into the AutoBoot Start
Address (ABSA) field of the AutoBoot Register which specifies a 512 byte boundary aligned location; the
default address is 00000000h.
– Data will continuously shift out until CS# returns high.
 At any point after the first data byte is transferred, when CS# returns high, the SPI device will reset to
standard SPI mode; able to accept normal command operations.
– A minimum of one byte must be transferred.
– AutoBoot mode will not initiate again until another power cycle or a reset occurs.
 An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.
The AutoBoot register bits are non-volatile and provide:
 The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the
ABSA field is 23 bits for devices up to 32-Gbit.
 The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.
 The AutoBoot Enable.
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If the configuration register QUAD bit CR1[1] is set to 1, the boot code will be provided 4 bits per cycle in the
same manner as a Read Quad Out command. If the QUAD bit is 0 the code is delivered serially in the same
manner as a Read command.
Figure 10.16 AutoBoot Sequence (CR1[1]=0)
CS#
SCK
SI
SO
Phase
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Wait States (ABSD)
Data 1
Data N
Figure 10.17 AutoBoot Sequence (CR1[1]=1)
CS#
SCK
IO0
4 0 4 0 4 0 4 0 4 0 4
IO1
5 1 5 1 5 1 5 1 5 1 5
IO2
6 2 6 2 6 2 6 2 6 2 6
IO3
7 3 7 3 7 3 7 3 7 3 7
Phase
10.3.12
Wait States (ABSD)
Data 1 Data 2 Data 3 Data 4 Data 5 ...
AutoBoot Register Read (ABRD 14h)
The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on
SO, least significant byte first, most significant bit of each byte first. It is possible to read the AutoBoot
Register continuously by providing multiples of 32 clock cycles. If the QUAD bit CR1[1] is cleared to 0, the
maximum operating clock frequency for ABRD command is 133 MHz. If the QUAD bit CR1[1] is set to 1, the
maximum operating clock frequency for ABRD command is 104 MHz.
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Figure 10.18 AutoBoot Register Read (ABRD 14h) Command
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
10.3.13
Instruction
Data 1
Data N
AutoBoot Register Write (ABWR 15h)
Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write
operations.
The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first,
most significant bit of each byte first. The ABWR data is 32 bits in length.
The ABWR command has status reported in Status Register-1 as both an erase and a programming
operation. An E_ERR or a P_ERR may be set depending on whether the erase or programming phase of
updating the register fails.
CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR
command is not executed. As soon as CS# is driven to the logic high state, the self-timed ABWR operation is
initiated. While the ABWR operation is in progress, Status Register-1 may be read to check the value of the
Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ABWR operation, and
is a 0. when it is completed. When the ABWR cycle is completed, the Write Enable Latch (WEL) is set to a 0.
The maximum clock frequency for the ABWR command is 133 MHz.
Figure 10.19 AutoBoot Register Write (ABWR) Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
SO
Phase
10.3.14
Instruction
Input Data 1
Program NVDLR (PNVDLR 43h)
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the
PNVDLR command is not executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR
operation is initiated. While the PNVDLR operation is in progress, the Status Register may be read to check
the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed
PNVDLR cycle, and is a 0. when it is completed. The PNVDLR operation can report a program error in the
P_ERR bit of the status register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is
set to a 0 The maximum clock frequency for the PNVDLR command is 133 MHz.
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Figure 10.20 Program NVDLR (PNVDLR 43h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
10.3.15
Instruction
Input Data
Write VDLR (WVDLR 4Ah)
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the
WVDLR command is not executed. As soon as CS# is driven to the logic high state, the WVDLR operation is
initiated with no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.
Figure 10.21 Write VDLR (WVDLR 4Ah) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
10.3.16
Instruction
Input Data
Data Learning Pattern Read (DLPRD 41h)
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP
continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the
DLPRD command is 133 MHz.
Figure 10.22 DLP Read (DLPRD 41h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
SO
Phase
88
2
1
0
7
6
Instruction
5
4
3
Data 1
S25FL512S
2
1
0
7
6
5
4
3
2
1
0
Data N
S25FL512S_00_09 January 21, 2015
Data
10.4
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Read Memory Array Commands
Read commands for the main flash array provide many options for prior generation SPI compatibility or
enhanced performance SPI:
 Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate
commands (SDR).
 Some SDR commands transfer address one bit per rising edge of SCK and return data 1, 2, or 4 bits of
data per rising edge of SCK. These are called Read or Fast Read for 1-bit data; Dual Output Read for 2-bit
data, and Quad Output for 4-bit data.
 Some SDR commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called
Dual I/O for 2 bit and Quad I/O for 4 bit.
 Some commands transfer address and data on both the rising edge and falling edge of SCK. These are
called Double Data Rate (DDR) commands.
 There are DDR commands for 1, 2, or 4 bits of address or data per SCK edge. These are called Fast DDR
for 1-bit, Dual I/O DDR for 2-bit, and Quad I/O DDR for 4-bit per edge transfer.
All of these commands begin with an instruction code that is transferred one bit per SCK rising edge. The
instruction is followed by either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring
address or data 2 or 4 bits per clock edge are called Multiple I/O (MIO) commands. For FL-S devices at
256 Mbits or higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in
the memory array. These device have a bank address register that is used with 3-byte address commands to
supply the high order address bits beyond the address from the host system. The default bank address is
zero. Commands are provided to load and read the bank address register. These devices may also be
configured to take a 4-byte address from the host system with the traditional 3-byte address commands. The
4-byte address mode for traditional commands is activated by setting the External Address (EXTADD) bit in
the bank address register to 1.
The Quad I/O commands provide a performance improvement option controlled by mode bits that are sent
following the address bits. The mode bits indicate whether the command following the end of the current read
will be another read of the same type, without an instruction at the beginning of the read. These mode bits
give the option to eliminate the instruction cycles when doing a series of Quad I/O read accesses.
A device ordering option provides an enhanced high performance option by adding a similar mode bit scheme
to the DDR Fast Read, Dual I/O, and Dual I/O DDR commands, in addition to the Quad I/O command.
Some commands require delay cycles following the address or mode bits to allow time to access the memory
array. The delay cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory
thus any data provided by the host during these cycles is “don’t care” and the host may also leave the SI
signal at high impedance during the dummy cycles. When MIO commands are used the host must stop
driving the IO signals (outputs are high impedance) before the end of last dummy cycle. When DDR
commands are used the host must not drive the I/O signals during any dummy cycle. The number of dummy
cycles varies with the SCK frequency or performance option selected via the Configuration Register 1 (CR1)
Latency Code (LC). Dummy cycles are measured from SCK falling edge to next SCK falling edge. SPI
outputs are traditionally driven to a new value on the falling edge of each SCK. Zero dummy cycles means the
returning data is driven by the memory on the same falling edge of SCK that the host stops driving address or
mode bits.
The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on
all data outputs, in the dummy cycles immediately before the start of data. The DLP can help the host
memory controller determine the phase shift from SCK to data edges so that the memory controller can
capture data at the center of the data eye.
When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides 1 or more
dummy cycles should be selected to allow additional time for the host to stop driving before the memory starts
driving data, to minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC
that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to
stop driving before the memory starts driving the 4 cycle DLP.
Each read command ends when CS# is returned High at any point during data return. CS# must not be
returned High during the mode or dummy cycles before data returns as this may cause mode bits to be
captured incorrectly; making it indeterminate as to whether the device remains in enhanced high performance
read mode.
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10.4.1
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Read (Read 03h or 4READ 13h):
The instruction
 03h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 03h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 13h is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock
frequency for the READ command is 50 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Figure 10.23 Read Command Sequence (READ 03h or 13h)
CS#
SCK
SI
7
6
5
4 3
2
1 0 A
1 0
SO
7
Phase
10.4.2
Instruction
Address
6 5
4
3 2
1
0
7 6
5
Data 1
4
3
2 1 0
Data N
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch):
The instruction
 0Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 0Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 0Ch is followed by a 4-byte address (A31-A0)
The address is followed by zero or eight dummy cycles depending on the latency code set in the
Configuration Register. The dummy cycles allow the device internal circuits additional time for accessing the
initial address location. During the dummy cycles the data value on SO is “don’t care” and may be high
impedance. Then the memory contents, at the address given, are shifted out on SO.
The maximum operating clock frequency for FAST READ command is 133 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Figure 10.24 Fast Read (FAST_READ 0Bh or 0Ch) Command Sequence with Read Latency
CS#
SCK
SI
7
6
5
4 3
2
1 0 A
1 0
SO
Phase
90
7 6
Instruction
Address
S25FL512S
Dummy Cycles
5
4 3
2 1 0
Data 1
S25FL512S_00_09 January 21, 2015
Data
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Figure 10.25 Fast Read Command (FAST_READ 0Bh or 0Ch) Sequence without Read Latency
CS#
SCK
SI
7
6
5
4 3
2
1 0 A
1 0
SO
7
Phase
10.4.3
Instruction
6 5
Address
4
3 2
1
Data 1
0
7 6
5
4
3
2 1 0
Data N
Dual Output Read (DOR 3Bh or 4DOR 3Ch):
The instruction
 3Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 3Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 3Ch is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1
(SO). Two bits are shifted out at the SCK frequency by the falling edge of the SCK signal.
The maximum operating clock frequency for the Dual Output Read command is 104 MHz. For Dual Output
Read commands, there are zero or eight dummy cycles required after the last address bit is shifted into SI
before data begins shifting out of IO0 and IO1. This latency period (i.e., dummy cycles) allows the device’s
internal circuitry enough time to read from the initial address. During the dummy cycles, the data value on SI
is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of
SCK (refer to Table 8.7, Latency Codes for SDR Enhanced High Performance on page 60).
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Figure 10.26 Dual Output Read Command Sequence (3-Byte Address, 3Bh [ExtAdd=0], LC=10b)
CS#
SCK
IO0
7 6 5 4 3 2 1 0
23 22 21
0
6 4 2 0 6 4 2 0
IO1
Phase
January 21, 2015 S25FL512S_00_09
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Instruction
Address
S25FL512S
8 Dummy Cycles
Data 1
Data 2
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Figure 10.27 Dual Output Read Command Sequence
(4-Byte Address, 3Ch or 3Bh [ExtAdd=1, LC=10b])
CS#
SCK
IO0
7 6 5 4 3 2 1 0
31 30 29
0
6 4 2 0 6 4 2 0
IO1
7 5 3 1 7 5 3 1
Phase
Instruction
Address 8 Dummy Cycles
Data 1
Data 2
Figure 10.28 Dual Output Read Command Sequence
(4-Byte Address, 3Ch or 3Bh [ExtAdd=1, LC=11b])
CS#
SCK
IO0
7 6 5 4 3 2 1 0
31 30 29
IO1
Phase
10.4.4
0 6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
Instruction
Address Data 1
Data 2
Quad Output Read (QOR 6Bh or 4QOR 6Ch):
The instruction
 6Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 6Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 6Ch is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out four bits at a time through IO0-IO3. Each
nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The maximum operating clock frequency for Quad Output Read command is 104 MHz. For Quad Output
Read Mode, there may be dummy cycles required after the last address bit is shifted into SI before data
begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry
enough time to set up for the initial address. During the dummy cycles, the data value on IO0-IO3 is a “don’t
care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK
(refer to Table 8.7, Latency Codes for SDR Enhanced High Performance on page 60).
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
The QUAD bit of Configuration Register must be set (CR Bit1=1) to enable the Quad mode capability.
92
S25FL512S
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Data
She et
Figure 10.29 Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence with Read Latency
CS#
SCK
IO0
76543210A
10
40404040404
IO1
51515151515
IO2
62626262626
IO3
73737373737
Phase
Instruction
Address
Dummy
D1 D2 D3 D4 D5
Figure 10.30 Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence without Read Latency
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
IO1
7
6
5
4
3
2
1
0
A
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
7 3
Data 5
...
IO3
Phase
10.4.5
Instruction
Address
0
7 3 7 3 7 3 7 3
Data 1 Data 2 Data 3 Data 4
7
Dual I/O Read (DIOR BBh or 4DIOR BCh):
The instruction
 BBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 BBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar
to the Dual Output Read command but takes input of the address two bits per SCK rising edge. In some
applications, the reduced address input time might allow for code execution in place (XIP) i.e. directly from
the memory device.
The maximum operating clock frequency for Dual I/O Read is 104 MHz.
For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and
SO before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the
latency code table used for this command, either the High Performance LC (HPLC) table or the Enhanced
High Performance LC (EHPLC) table. The HPLC table does not provide cycles for mode bits so each Dual I/
O Read command starts with the 8 bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the
initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high
impedance. The number of dummy cycles is determined by the frequency of SCK (Table 8.7, Latency Codes
for SDR Enhanced High Performance on page 60). The number of dummy cycles is set by the LC bits in the
Configuration Register (CR1).
The EHPLC table does provide cycles for mode bits so a series of Dual I/O Read commands may eliminate
the 8-bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the
following command will also be a Dual I/O Read command. The first Dual I/O Read command in a series
starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a
latency period. If the mode bit pattern is Axh the next command is assumed to be an additional Dual I/O Read
January 21, 2015 S25FL512S_00_09
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command that does not provide instruction bits. That command starts with address, followed by mode bits,
followed by latency.
The Enhanced High Performance feature removes the need for the instruction sequence and greatly
improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual
I/O Read command through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits
3-0) of the Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh, then the
device remains in Dual I/O Enhanced High Performance Read Mode and the next address can be entered
(after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in
Figure 10.34; thus, eliminating eight cycles for the command sequence. The following sequences will release
the device from Dual I/O Enhanced High Performance Read mode; after which, the device can accept
standard SPI commands:
1. During the Dual I/O Enhanced High Performance Command Sequence, if the Mode bits are any
value other than Axh, then the next time CS# is raised high the device will be released from Dual
I/O Read Enhanced High Performance Read mode.
During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and IO1)
are not set for a valid instruction sequence, then the device will be released from Dual I/O Enhanced High
Performance Read mode. Note that the four mode bit cycles are part of the device’s internal circuitry latency
time to access the initial address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out
clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins
to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention,
for the host system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t
care” mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time
through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Figure 10.31 Dual I/O Read Command Sequence (3-Byte Address, BBh [ExtAdd=0], HPLC=00b)
CS#
SCK
IO0
7 6 5 4 3 2 1 0
IO1
Phase
94
Instruction
22 20 18
0
6 4 2 0 6 4 2 0
23 21 19
1
7 5 3 1 7 5 3 1
Address
S25FL512S
4 Dummy
Data 1
Data 2
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Data
She et
Figure 10.32 Dual I/O Read Command Sequence (4-Byte Address, BBh [ExtAdd=1], HPLC=10b)
CS#
SCK
IO0
7 6 5 4 3 2 1 0
IO1
Phase
30 28 26
0
6 4 2 0 6 4 2 0
31 29 27
1
7 5 3 1 7 5 3 1
Instruction
Address
6 Dummy
Data 1
Data 2
Figure 10.33 Dual I/O Read Command Sequence
(4-Byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b)
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
Instruction
Phase
0 30
2
0
6
31
3 1
Address
7
4
2
0
5 3
Mode
1
6
7
Dum
4
2
0
6
5 3 1
Data 1
7
4
2
0
5 3 1
Data 2
Figure 10.34 Continuous Dual I/O Read Command Sequence
(4-Byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b)
CS#
SCK
IO0
6
IO1
7
Phase
10.4.6
4
2
0
30
5 3
Data N
1
31
2
3
Address
0
6
4
2
0
6
1
7
5 3
Mode
1
7
Dum
4
2
0
6
5 3
Data 1
1
7
4
2
0
5 3
Data 2
1
Quad I/O Read (QIOR EBh or 4QIOR ECh):
The instruction
 EBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 EBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It is similar to the Quad
Output Read command but allows input of the address bits four bits per serial SCK clock. In some
applications, the reduced instruction overhead might allow for code execution (XIP) directly from the
S25FL512S device. The QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad
capability of the S25FL512S device.
The maximum operating clock frequency for Quad I/O Read is 104 MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before
data begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal
circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3
are “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of
SCK and the latency code table (refer to Table 8.7, Latency Codes for SDR Enhanced High Performance
January 21, 2015 S25FL512S_00_09
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on page 60). There are different ordering part numbers that select the latency code table used for this
command, either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC)
table. The number of dummy cycles is set by the LC bits in the Configuration Register (CR1). However, both
latency code tables use the same latency values for the Quad I/O Read command.
Following the latency period, the memory contents at the address given, is shifted out four bits at a time
through IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled
through the setting of the Mode bits (after the address sequence, as shown in Figure 10.35 on page 96 or
Figure 10.37 on page 97). This added feature removes the need for the instruction sequence and greatly
improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next
Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits
3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O
High Performance Read Mode and the next address can be entered (after CS# is raised high and then
asserted low) without requiring the EBh or ECh instruction, as shown in Figure 10.36 on page 97 or
Figure 10.38 on page 97; thus, eliminating eight cycles for the command sequence. The following sequences
will release the device from Quad I/O High Performance Read mode; after which, the device can accept
standard SPI commands:
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh,
then the next time CS# is raised high the device will be released from Quad I/O High Performance
Read mode.
During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0-IO3) are
not set for a valid instruction sequence, then the device will be released from Quad I/O High Performance
Read mode. Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the
device’s internal circuitry latency time to access the initial address after the last address cycle that is clocked
into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data
out clock. At higher clock speeds the time available to turn off the host outputs before the memory device
begins to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0-IO3 signal
contention, for the host system to turn off the IO0-IO3 signal outputs (make them high impedance) during the
last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Figure 10.35 Quad I/O Read Command Sequence (3-Byte Address, EBh [ExtAdd=0], LC=00b)
CS#
SCK
IO0
0 20
4
0
4
0
4
0
4
0
4
0
4
0
IO1
21
5
1
5
1
5
1
5
1
5
1
5
1
IO2
22
6
2
6
2
6
2
6
2
6
2
6
2
IO3
23
7
3
7
3
7
3
7
3
7
3
7
3
Phase
96
7
6
5
4
3
Instruction
2
1
Address
S25FL512S
Mode
Dummy
D1
D2
D3
D4
S25FL512S_00_09 January 21, 2015
Data
She et
Figure 10.36 Continuous Quad I/O Read Command Sequence (3-Byte Address), LC=00b
CS#
SCK
IO0
4
0
4
0
20
4
0
4
0
4
0
4
0
6
4
2
0
IO1
5
1
5
1
21
5
1
5
1
5
1
5
1
7
5
3
1
IO2
6
2
6
2
22
6
2
6
2
6
2
6
1
7
5
3
1
IO3
7 3
DN-1
7 3
DN
23
3
7 3
Mode
7
3
7
1
D2
7
5
3
Phase
7
Address
Dummy
D1
D3
1
D4
Figure 10.37 Quad I/O Read Command Sequence
(4-Byte Address, ECh or EBh [ExtAdd=1], LC=00b)
CS#
SCK
IO0
0 28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
7
6
5
4
3
2
1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
31
7 3 7 3
Address
Mode
7
3
D1
7
3
D2
7
3
D3
Instruction
Phase
Dummy
7 3
D4
Figure 10.38 Continuous Quad I/O Read Command Sequence (4-Byte Address), LC=00b
CS#
SCK
IO0
4
0
4
0
28
4
0
4
0
4
0
4
0
6
4
2
0
IO1
5
1
5
1
29
5
1
5
1
5
1
5
1
7
5
3
1
IO2
6
2
6
2
30
6
2
6
2
6
2
6
1
7
5
3
1
IO3
7 3
DN-1
7 3
DN
31
3
7 3
Mode
7
3
7
1
7
5
3
Phase
10.4.7
7
Address
Dummy
D1
D2
D3
1
D4
DDR Fast Read (DDRFR 0Dh, 4DDRFR 0Eh)
The instruction
 0Dh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 0Dh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 0Eh is followed by a 4-byte address (A31-A0)
The DDR Fast Read command improves throughput by transferring address and data on both the falling and
rising edge of SCK. It is similar to the Fast Read command but allows transfer of address and data on every
edge of the clock.
The maximum operating clock frequency for DDR Fast Read command is 80 MHz.
For the DDR Fast Read command, there is a latency required after the last address bits are shifted into SI
before data begins shifting out of SO. There are different ordering part numbers that select the latency code
table used for this command, either the High Performance LC (HPLC) table or the Enhanced High
January 21, 2015 S25FL512S_00_09
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97
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Performance LC (EHPLC) table. The HPLC table does not provide cycles for mode bits so each DDR Fast
Read command starts with the 8-bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the
initial address. During the dummy cycles, the data value on SI is “don’t care” and may be high impedance.
The number of dummy cycles is determined by the frequency of SCK (Table 8.7, Latency Codes for SDR
Enhanced High Performance on page 60). The number of dummy cycles is set by the LC bits in the
Configuration Register (CR1).
Then the memory contents, at the address given, is shifted out, in DDR fashion, one bit at a time on each
clock edge through SO. Each bit is shifted out at the SCK frequency by the rising and falling edge of the SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
The EHPLC table does provide cycles for mode bits so a series of DDR Fast Read commands may eliminate
the 8-bit instruction after the first DDR Fast Read command sends a mode bit pattern of complementary first
and second Nibbles, e.g. A5h, 5Ah, 0Fh, etc., that indicates the following command will also be a DDR Fast
Read command. The first DDR Fast Read command in a series starts with the 8-bit instruction, followed by
address, followed by four cycles of mode bits, followed by a latency period. If the mode bit pattern is
complementary the next command is assumed to be an additional DDR Fast Read command that does not
provide instruction bits. That command starts with address, followed by mode bits, followed by latency.
When the EHPLC table is used, address jumps can be done without the need for additional DDR Fast Read
instructions. This is controlled through the setting of the Mode bits (after the address sequence, as shown in
Figure 10.39 on page 99 and Figure 10.41 on page 99. This added feature removes the need for the eight bit
SDR instruction sequence to reduce initial access time (improves XIP performance). The Mode bits control
the length of the next DDR Fast Read operation through the inclusion or exclusion of the first byte instruction
code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and
Ah) then the next address can be entered (after CS# is raised high and then asserted low) without requiring
the 0Dh or 0Eh instruction, as shown in Figure 10.40 and Figure 10.42, thus, eliminating eight cycles from the
command sequence. The following sequences will release the device from this continuous DDR Fast Read
mode; after which, the device can accept standard SPI commands:
1. During the DDR Fast Read Command Sequence, if the Mode bits are not complementary the next
time CS# is raised high the device will be released from the continuous DDR Fast Read mode.
2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (SI)
are not set for a valid instruction sequence, then the device will be released from DDR Fast Read
mode.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
The HOLD function is not valid during any part of a Fast DDR Command.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four IOs on a x4
device, both IOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover
both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period
of time (two half clocks) followed by a high going transition (001) and the complementary low going transition
(110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by
a high going transition (101) and the complementary low going transition (010). The DC transitions will
typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow
the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See Section 8.6.11, SPI DDR Data Learning
Registers on page 64 for more details.
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Figure 10.39 DDR Fast Read Initial Access (3-Byte Address, 0Dh [ExtAdd=0, EHPLC=11b])
CS#
SCK
SI
7
6
5
4
3
2
1
0
2322
0 7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
Instruction
Address
Mode
Dummy
Data 1
Data 2
Figure 10.40 Continuous DDR Fast Read Subsequent Access
(3-Byte Address [ExtAdd=0, EHPLC=11b])
CS#
SCK
IO0
23
1
0
7
6
5
4
3
2
1
0
IO1
7
Phase
Address
Mode
6
5
4
Dum
3
2
1
0
7
Data 1
6
D2
Figure 10.41 DDR Fast Read Initial Access (4-Byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b)
CS#
SCK
SI
7
6
5
4
3
2
1
0
31
1 0 7 6 5 4 3 2 1 0
SO
76 54 3 2 10 7 6 5 4 3 2 1 0 7 6
Phase
Instruction
Address
Mode
DLP
Data 1
D2
Note:
1. Example DLP of 34h (or 00110100).
Figure 10.42 Continuous DDR Fast Read Subsequent Access
(4-Byte Address [ExtAdd=1], EHPLC=01b)
CS#
SCK
SI
SO
Phase
31
1 0 7 6 5 4 3 2 1 0
7 6
Address
Mode
5 4
3 2 1 0
DLP
7 6 5 4 3 2 1 0 7 6
Data 1
D2
Note:
1. Example DLP of 34h (or 00110100).
January 21, 2015 S25FL512S_00_09
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Figure 10.43 DDR Fast Read Subsequent Access (4-Byte Address, HPLC=01b)
CS#
SCK
SI
SO
Phase
10.4.8
7
6
5
4
3
2
1
0
3.
1 0
7 6 5 4 3 2 1 0 7 6
Instruction
Address
Dummy
Data 1
D2
DDR Dual I/O Read (BDh, BEh)
The instruction
 BDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 BDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 BEh is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out, in a DDR fashion, two bits at a time on each
clock edge through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency by the rising and
falling edge of the SCK signal.
The DDR Dual I/O Read command improves throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is
similar to the Dual I/O Read command but transfers two address, mode, or data bits on every edge of the
clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly
from the S25FL512S device.
The maximum operating clock frequency for DDR Dual I/O Read command is 80 MHz.
For DDR Dual I/O Read commands, there is a latency required after the last address bits are shifted into IO0
and IO1, before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select
the latency code table used for this command, either the High Performance LC (HPLC) table or the Enhanced
High Performance LC (EHPLC) table. The number of latency (dummy) clocks is determined by the frequency
of SCK (refer to Table 8.6, Latency Codes for DDR High Performance on page 59 or Table 8.8, Latency
Codes for DDR Enhanced High Performance on page 60). The number of dummy cycles is set by the LC bits
in the Configuration Register (CR1).
The HPLC table does not provide cycles for mode bits so each Dual I/O command starts with the 8 bit
instruction, followed by address, followed by a latency period. This latency period allows the device’s internal
circuitry enough time to access the initial address. During these latency cycles, the data value on SI (IO0) and
SO (IO1) are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is enabled the
host system must not drive the IO signals during the dummy cycles. The IO signals must be left high
impedance by the host so that the memory device can drive the DLP during the dummy cycles.
The EHPLC table does provide cycles for mode bits so a series of Dual I/O DDR commands may eliminate
the 8 bit instruction after the first command sends a complementary mode bit pattern, as shown in
Figure 10.44 and Figure 10.46 on page 102. This added feature removes the need for the eight bit SDR
instruction sequence and dramatically reduces initial access times (improves XIP performance). The Mode
bits control the length of the next DDR Dual I/O Read operation through the inclusion or exclusion of the first
byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are
complementary (i.e. 5h and Ah) the device transitions to Continuous DDR Dual I/O Read Mode and the next
address can be entered (after CS# is raised high and then asserted low) without requiring the BDh or BEh
instruction, as shown in Figure 10.45 on page 101, and thus, eliminating eight cycles from the command
sequence. The following sequences will release the device from Continuous DDR Dual I/O Read mode; after
which, the device can accept standard SPI commands:
1. During the DDR Dual I/O Read Command Sequence, if the Mode bits are not complementary the
next time CS# is raised high and then asserted low the device will be released from DDR Dual I/O
Read mode.
2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input
(IO0 and IO1) are not set for a valid instruction sequence, then the device will be released from
DDR Dual I/O Read mode.
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The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
The HOLD function is not valid during Dual I/O DDR commands.
Note that the memory devices may drive the IOs with a preamble prior to the first data value. The preamble is
a data learning pattern (DLP) that is used by the host controller to optimize data capture at higher
frequencies. The preamble DLP drives the IO bus for the four clock cycles immediately before data is output.
The host must be sure to stop driving the IO bus prior to the time that the memory starts outputting the
preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host
drives a clock edge to when the corresponding data value returns from the memory device. The host
controller will skew the data capture point during the preamble period to optimize timing margins and then use
the same skew time to capture the data during the rest of the read operation. The optimized capture point will
be determined during the preamble period of every read operation. This optimization strategy is intended to
compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4
device, both SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover
both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period
of time (two half clocks) followed by a high going transition (001) and the complementary low going transition
(110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by
a high going transition (101) and the complementary low going transition (010). The DC transitions will
typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow
the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See Section 8.6.11, SPI DDR Data Learning
Registers on page 64 for more details.
Figure 10.44 DDR Dual I/O Read Initial Access
(4-Byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b)
CS#
SCK
IO0
7
6
5
4
3
2
1
0
IO1
Phase
Instruction
30 28
0
6
4
2
0
7 6
5 4
3
2
1 0
6
4
2
0
6
31 29
1
7
5
3
1
7 6
5 4
3
2
1 0
7
5
3
1
7
Address
Mode
Dum
DLP
Data 1
Figure 10.45 Continuous DDR Dual I/O Read Subsequent Access (4-Byte Address, EHPLC= 01b)
CS#
SCK
IO0
IO1
Phase
30
2
0
6
4
2
0
7
6
4
5
3
2 1
0
6
4
2
0
6
31
3
1
7
5
3
1
7
6
4
5
3
2 1
0
7
5
3
1
7
January 21, 2015 S25FL512S_00_09
Address
Mode
Dummy
S25FL512S
DLP
Data 1
D2
101
D at a
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Figure 10.46 DDR Dual I/O Read (4-Byte Address, BEh or BDh [ExtAdd=1], HPLC=00b)
CS#
SCK
IO0
IO1
Phase
10.4.9
7
6
5
4
3
2
1
0
Instruction
30
2 0
6 4 2 0 6
31
3 1
7 5 3 1 7
Address
Dummy
Data 1
D2
DDR Quad I/O Read (EDh, EEh)
The Read DDR Quad I/O command improves throughput with four I/O signals - IO0-IO3. It is similar to the
Quad I/O Read command but allows input of the address four bits on every edge of the clock. In some
applications, the reduced instruction overhead might allow for code execution (XIP) directly from the
S25FL512S device. The QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad
capability.
The instruction
 EDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 EDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 EEh is followed by a 4-byte address (A31-A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a
DDR fashion, with four bits at a time on each clock edge through IO0-IO3.
The maximum operating clock frequency for Read DDR Quad I/O command is 80 MHz.
For Read DDR Quad I/O, there is a latency required after the last address and mode bits are shifted into the
IO0-IO3 signals before data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the
device’s internal circuitry enough time to access the initial address. During these latency cycles, the data
value on IO0-IO3 are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is
enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must be left
high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
There are different ordering part numbers that select the latency code table used for this command, either the
High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The number of
dummy cycles is determined by the frequency of SCK (refer to Table 8.6, Latency Codes for DDR High
Performance on page 59). The number of dummy cycles is set by the LC bits in the Configuration Register
(CR1).
Both latency tables provide cycles for mode bits so a series of Quad I/O DDR commands may eliminate the 8
bit instruction after the first command sends a complementary mode bit pattern, as shown in Figure 10.47 and
Figure 10.49. This feature removes the need for the eight bit SDR instruction sequence and dramatically
reduces initial access times (improves XIP performance). The Mode bits control the length of the next Read
DDR Quad I/O operation through the inclusion or exclusion of the first byte instruction code. If the upper
nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device
transitions to Continuous Read DDR Quad I/O Mode and the next address can be entered (after CS# is
raised high and then asserted low) without requiring the EDh or EEh instruction, as shown in Figure 10.48
on page 104 and Figure 10.50 on page 104 thus, eliminating eight cycles from the command sequence. The
following sequences will release the device from Continuous Read DDR Quad I/O mode; after which, the
device can accept standard SPI commands:
1. During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the
next time CS# is raised high and then asserted low the device will be released from Read DDR
Quad I/O mode.
2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input
(IO0, IO1, IO2, and IO3) are not set for a valid instruction sequence, then the device will be
released from Read DDR Quad I/O mode.
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The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
The HOLD function is not valid during Quad I/O DDR commands.
Note that the memory devices drive the IOs with a preamble prior to the first data value. The preamble is a
pattern that is used by the host controller to optimize data capture at higher frequencies. The preamble drives
the IO bus for the four clock cycles immediately before data is output. The host must be sure to stop driving
the IO bus prior to the time that the memory starts outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host
drives a clock edge to when the corresponding data value returns from the memory device. The host
controller will skew the data capture point during the preamble period to optimize timing margins and then use
the same skew time to capture the data during the rest of the read operation. The optimized capture point will
be determined during the preamble period of every read operation. This optimization strategy is intended to
compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4
device, both SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover
both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period
of time (two half clocks) followed by a high going transition (001) and the complementary low going transition
(110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by
a high going transition (101) and the complementary low going transition (010). The DC transitions will
typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow
the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See SPI DDR Data Learning Registers
on page 64 for more details.
Figure 10.47 DDR Quad I/O Read Initial Access (3-Byte Address, EDh [ExtAdd=0], HPLC=11b)
CS#
SCK
IO0
7
6
5
4
3
20 16 12 8 4
0 4 0
7 6
5 4 3
2 1 0
4 0 4 0
IO1
21 17 13 9 5
1 5 1
7 6
5 4 3
2 1 0
5 1 5 1
IO2
22 18 14 10 6
2 6 2
7 6
5 4 3
2 1 0
6 2 6 2
23 19 15 11 7
3 7 3
7 6
5 4 3
2 1 0
7 3 7 3
IO3
Phase
January 21, 2015 S25FL512S_00_09
Instruction
2
1
0
Address
S25FL512S
Mode
Dummy
DLP
D1
D2
103
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Figure 10.48 Continuous DDR Quad I/O Read Subsequent Access (3-Byte Address,HPLC=11b)
CS#
SCK
IO0
IO1
IO2
IO3
Phase
20 16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
21 17 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
22 18 14 10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
23 19 15 11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Address
Mode
Dummy
D1
D2
D3
D4
D5
Figure 10.49 DDR Quad I/O Read Initial Access
(4-Byte Address, EEh or EDh [ExtAdd=1], EHPLC=01b)
CS#
SCK
IO0
IO1
IO2
IO3
Phase
7
6
5
4
3
2
1
0
2. 2. 2. 1. 1.
8 4 0 4 0
7 6 5 4 3 21 0 4 0 4 0
2. 2. 2. 1. 1.
9 5 1 5 1
7 6 5 4 3 21 0 5 1 5 1
3. 2. 2. 1. 1. 1.
6 2 6 2
7 6 5 4 3 21 0 6 2 6 2
3. 2. 2. 1. 1. 1.
7 3 7 3
7 6 5 4 3 21 0 7 3 7 3
Instruction
Address
Mod .
Dummy
DLP
D1 D2
Note:
1. Example DLP of 34h (or 00110100).
Figure 10.50 Continuous DDR Quad I/O Read Subsequent Access (4-Byte Address, EHPLC=01b)
CS#
SCK
IO0
IO1
IO2
IO3
Phase
28 24 20 16 12 8 4
0 4
0
7 6
5 4
3
2 1 0
4
0 4
0 4
29 25 21 17 13 9 5
1 5
1
7 6
5 4
3
2 1 0
5
1 5
1 5
30 26 22 18 14 10 6
2 6
2
7 6
5 4
3
2 1 0
6
2 6
2 6
31 27 23 19 15 11 7
3 7
3
7 6
5 4
3
2 1 0
7
3 7
3 7
Address
Mode
Dummy
DLP
D1
D2
Note:
1. Example DLP of 34h (or 00110100).
10.5
Program Flash Array Commands
10.5.1
10.5.1.1
Program Granularity
Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming
command to move data from the buffer to the memory array. This sets an upper limit on the amount of data
that can be programmed with a single programming command. Page Programming allows up to a page size
(512 bytes) to be programmed in one operation. The page is aligned on the page size address boundary. It is
possible to program from one bit up to a page size in each Page programming operation. It is recommended
that a multiple of 16 byte length and aligned Program Blocks be written. For the very best performance,
programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each Page being
programmed only once.
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10.5.1.2
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Single Byte Programming
Single Byte Programming allows full backward compatibility to the standard SPI Page Programming (PP)
command by allowing a single byte to be programmed anywhere in the memory array.
10.5.2
Page Program (PP 02h or 4PP 12h):
The Page Program (PP) commands allows bytes to be programmed in the memory (changing bits from 1 to
0). Before the Page Program (PP) commands can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
The instruction
 02h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 02h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 12h is followed by a 4-byte address (A31-A0)
and at least one data byte on SI. Up to a page can be provided on SI after the 3-byte address with instruction
02h or 4-byte address with instruction 12h has been provided. If the 9 least significant address bits (A8-A0)
are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the
start address of the same page (from the address whose 9 least significant bits (A8-A0) are all zero) i.e. the
address wraps within the page aligned address boundaries. This is a result of only requiring the user to enter
one single page address to cover the entire page boundary.
If less than a page of data is sent to the device, these data bytes will be programmed in sequence, starting at
the provided address within the page, without having any affect on the other bytes of the same page.
For optimized timings, using the Page Program (PP) command to load the entire page size program buffer
within the page boundary will save overall programming time versus loading less than a page size into the
program buffer.
The programming process is managed by the flash memory device internal control logic. After a programming
command is issued, the programming operation status can be checked using the Read Status Register-1
command. The WIP bit (SR1[0]) will indicate when the programming operation is completed. The P_ERR bit
(SR1[6]) will indicate if an error occurs in the programming operation that prevents successful completion of
programming.
Figure 10.51 Page Program (PP 02h or 4PP 12h) Command Sequence
CS#
SCK
SI
7
6 5
4 3
2
1 0
A
5
4 3
2 1
0
7 6
5 4
3 2
1
0 7
6 5
4
3 2
1 0
SO
Phase
10.5.3
Instruction
Address
Input Data 1
Input Data 2
Quad Page Program (QPP 32h or 38h, or 4QPP 34h)
The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing
bits from 1 to 0). The Quad-input Page Program (QPP) command allows up to a page size (512 bytes) of data
to be loaded into the Page Buffer using four signals: IO0-IO3. QPP can improve performance for PROM
Programmer and applications that have slower clock speeds (< 12 MHz) by loading 4 bits of data per clock
cycle. Systems with faster clock speeds do not realize as much benefit for the QPP command since the
inherent page program time becomes greater than the time it takes to clock-in the data. The maximum
frequency for the QPP command is 80 MHz.
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To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD=1). A
Write Enable command must be executed before the device will accept the QPP command (Status Register1, WEL=1).
The instruction
 32h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 32h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 38h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 38h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 34h is followed by a 4-byte address (A31-A0)
and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory
locations.
QPP requires programming to be done one full page at a time. While less than a full page of data may be
loaded for programming, the entire page is considered programmed, any locations not filled with data will be
left as ones, the same page must not be programmed more than once.
All other functions of QPP are identical to Page Program. The QPP command sequence is shown in the
figure below.
Figure 10.52 Quad 512-byte Page Program Command Sequence
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
Data 5
...
Phase
10.5.4
7
6
5
4
3
2
1
0
Instruction
A
1
Address
0
Data 1 Data 2
Data 3
Data 4
Program Suspend (PGSP 85h) and Resume (PGRS 8Ah)
The Program Suspend command allows the system to interrupt a programming operation and then read from
any other non-erase-suspended sector or non-program-suspended-page. Program Suspend is valid only
during a programming operation.
Commands allowed after the Program Suspend command is issued:
 Read Status Register 1 (RDSR1 05h)
 Read Status Register 2 (RDSR2 07h)
The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the
programming operation has stopped. The Program Suspend Status bit in the Status Register-2 (SR2[0]) can
be used to determine if a programming operation has been suspended or was completed at the time WIP
changes to 0. The time required for the suspend operation to complete is tPSL, see Table 10.8, Program
Suspend AC Parameters on page 118.
See Table 10.6, Commands Allowed During Program or Erase Suspend on page 110 for the commands
allowed while programming is suspend.
The Program Resume command 8Ah must be written to resume the programming operation after a Program
Suspend. If the programming operation was completed during the suspend operation, a resume command is
not needed and has no effect if issued. Program Resume commands will be ignored unless a Program
operation is suspended.
After a Program Resume command is issued, the WIP bit in the Status Register-1 will be set to a 1 and the
programming operation will resume. Program operations may be interrupted as often as necessary e.g. a
program suspend command could immediately follow a program resume command but, in order for a
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program operation to progress to completion there must be some periods of time between resume and the
next suspend command greater than or equal to tPRS. See Table 10.8, Program Suspend AC Parameters
on page 118.
Figure 10.53 Program Suspend (PGSP 85h) Command Sequence
tPSL
CS#
SCK
SI
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SO
Phase
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Suspend Instruction
Status
Read Status Instruction
Phase
Instr. During Suspend
Repeat Status Read Until Suspended
Figure 10.54 10.55 Program Resume (PGRS 8Ah) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.6
Instruction
Erase Flash Array Commands
10.6.1
Sector Erase (SE D8h or 4SE DCh):
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the
Sector Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable
any write operations.
The instruction
 D8h [ExtAdd=0] is followed by a 3-byte address (A23-A0), or
 D8h [ExtAdd=1] is followed by a 4-byte address (A31-A0), or
 DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been
latched in on SI. This will initiate the erase cycle, which involves the pre-programming and erase of the
chosen sector. If CS# is not driven high after the last bit of address, the sector erase operation will not be
executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal
erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the
operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a0 when
the erase cycle has been completed.
A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection
bits or ASP, will not be executed and will set the E_ERR status.
ASP has a PPB and a DYB protection bit for each sector.
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Figure 10.55 Sector Erase (SE D8h or 4SE DCh) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
10.6.2
Instruction
Address
Bulk Erase (BE 60h or C7h):
The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array.
Before the BE command can be accepted by the device, a Write Enable (WREN) command must be issued
and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory
array. If CS# is not driven high after the last bit of instruction, the BE operation will not be executed.
As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in
progress, the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has
been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase
cycle has been completed.
A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0’s. If the BP
bits are not zero, the BE command is not executed and E_ERR is not set. The BE command will skip any
sectors protected by the DYB or PPB and the E_ERR status will not be set.
Figure 10.56 Bulk Erase Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.6.3
Instruction
Erase Suspend and Resume Commands (ERSP 75h or ERRS 7Ah)
The Erase Suspend command, allows the system to interrupt a sector erase operation and then read from or
program data to, any other sector. Erase Suspend is valid only during a sector erase operation. The Erase
Suspend command is ignored if written during the Bulk Erase operation.
When the Erase Suspend command is written during the sector erase operation, the device requires a
maximum of tESL (erase suspend latency) to suspend the erase operation and update the status bits. See
Table 10.9, Erase Suspend AC Parameters on page 118.
Commands allowed after the Erase Suspend command is issued:
 Read Status Register 1 (RDSR1 05h)
 Read Status Register 2 (RDSR2 07h)
The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the erase
operation has stopped. The Erase Suspend bit in Status Register-2 (SR2[1]) can be used to determine if an
erase operation has been suspended or was completed at the time WIP changes to 0.
If the erase operation was completed during the suspend operation, a resume command is not needed and
has no effect if issued. Erase Resume commands will be ignored unless an Erase operation is suspended.
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See Table 10.6, Commands Allowed During Program or Erase Suspend on page 110 for the commands
allowed while erase is suspend.
After the erase operation has been suspended, the sector enters the erase-suspend mode. The system can
read data from or program data to the device. Reading at any address within an erase-suspended sector
produces undetermined data.
A WREN command is required before any command that will change non-volatile data, even during erase
suspend.
The WRR and PPB Erase commands are not allowed during Erase Suspend, it is therefore not possible to
alter the Block Protection or PPB bits during Erase Suspend. If there are sectors that may need programming
during Erase suspend, these sectors should be protected only by DYB bits that can be turned off during
Erase Suspend. However, WRR is allowed immediately following the BRAC command; in this special case
the WRR is interpreted as a write to the Bank Address Register, not a write to SR1 or CR1.
If a program command is sent for a location within an erase suspended sector the program operation will fail
with the P_ERR bit set.
After an erase-suspended program operation is complete, the device returns to the erase-suspend mode.
The system can determine the status of the program operation by reading the WIP bit in the Status Register,
just as in the standard program operation.
The Erase Resume command 7Ah must be written to resume the erase operation if an Erase is suspend.
Erase Resume commands will be ignored unless an Erase is Suspend.
After an Erase Resume command is sent, the WIP bit in the status register will be set to a 1 and the erase
operation will continue. Further Resume commands are ignored.
Erase operations may be interrupted as often as necessary e.g. an erase suspend command could
immediately follow an erase resume command but, in order for an erase operation to progress to completion
there must be some periods of time between resume and the next suspend command greater than or equal to
tERS. See Table 10.9, Erase Suspend AC Parameters on page 118.
Figure 10.57 Erase Suspend (ERSP 75h) Command Sequence
tESL
CS#
SCK
SI
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SO
Phase
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Suspend Instruction
Phase
Status
Read Status Instruction
Instr. During Suspend
Repeat Status Read Until Suspended
Figure 10.58 Erase Resume (ERRS 7Ah) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
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Table 10.6 Commands Allowed During Program or Erase Suspend
Instruction
Name
Instruction
Code
(Hex)
Allowed
During
Erase
Suspend
Allowed
During
Program
Suspend
BRAC
B9
X
X
Bank address register may need to be changed during a suspend to reach a
sector for read or program.
BRRD
16
X
X
Bank address register may need to be changed during a suspend to reach a
sector for read or program.
BRWR
17
X
X
Bank address register may need to be changed during a suspend to reach a
sector for read or program.
CLSR
30
X
Clear status may be used if a program operation fails during erase suspend.
DYBRD
E0
X
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
DYBWR
E1
X
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
ERRS
7A
X
DDRFR
0D
X
Required to resume from erase suspend.
X
All array reads allowed in suspend.
4DDRFR
0E
X
X
All array reads allowed in suspend.
FAST_READ
0B
X
X
All array reads allowed in suspend.
4FAST_READ
0C
X
X
All array reads allowed in suspend.
MBR
FF
X
X
May need to reset a read operation during suspend.
PGRS
8A
X
X
Needed to resume a program operation. A program resume may also be used
during nested program suspend within an erase suspend.
PGSP
85
X
Program suspend allowed during erase suspend.
PP
02
X
Required for array program during erase suspend.
4PP
12
X
Required for array program during erase suspend.
PPBRD
E2
X
Allowed for checking persistent protection before attempting a program
command during erase suspend.
QPP
32, 38
X
Required for array program during erase suspend.
4QPP
34
X
Required for array program during erase suspend.
4READ
13
X
X
RDCR
35
X
X
DIOR
BB
X
X
All array reads allowed in suspend.
4DIOR
BC
X
X
All array reads allowed in suspend.
All array reads allowed in suspend.
DOR
3B
X
X
All array reads allowed in suspend.
4DOR
3C
X
X
All array reads allowed in suspend.
DDRDIOR
BD
X
X
All array reads allowed in suspend.
4DDRDIOR
BE
X
X
All array reads allowed in suspend.
DDRQIOR
ED
X
X
All array reads allowed in suspend.
DDRQIOR4
EE
X
X
All array reads allowed in suspend.
QIOR
EB
X
X
All array reads allowed in suspend.
4QIOR
EC
X
X
All array reads allowed in suspend.
QOR
6B
X
X
All array reads allowed in suspend.
4QOR
6C
X
X
All array reads allowed in suspend.
RDSR1
05
X
X
Needed to read WIP to determine end of suspend process.
RDSR2
110
Comment
07
X
X
Needed to read suspend status to determine whether the operation is
suspended or complete.
READ
03
X
X
All array reads allowed in suspend.
RESET
F0
X
X
Reset allowed anytime.
WREN
06
X
WRR
01
X
Required for program command within erase suspend.
X
Bank register may need to be changed during a suspend to reach a sector
needed for read or program. WRR is allowed when following BRAC.
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10.7
She et
One Time Program Array Commands
10.7.1
OTP Program (OTPP 42h):
The OTP Program command programs data in the One Time Program region, which is in a different address
space from the main array data. The OTP region is 1024 bytes so, the address bits from A23 to A10 must be
zero for this command. Refer to Section 8.5, OTP Address Space on page 55 for details on the OTP region.
The protocol of the OTP Program command is the same as the Page Program command. Before the OTP
Program command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write
operations.
To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to 1.
Each region in the OTP memory space can be programmed one or more times, provided that the region is not
locked. Attempting to program zeros in a region that is locked will fail with the P_ERR bit in SR1 set to 1
Programming ones, even in a protected area does not cause an error and does not set P_ERR. Subsequent
OTP programming can be performed only on the un-programmed bits (that is, 1 data).
Figure 10.59 Page Program (OTPP 42h) Command Sequence
CS#
SCK
SI
7
6 5
4 3
2
1 0 23
5
4 3
2 1
0
7 6
5 4
3 2
1
0 7
6 5
4
3 2
1 0
SO
Instruction
Phase
10.7.2
Address
Input Data 1
Input Data 2
OTP Read (OTPR 4Bh):
The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits
from A23 to A10 must be zero for this command. Refer to OTP Address Space on page 55 for details on the
OTP region. The protocol of the OTP Read command is similar to the Fast Read command except that it will
not wrap to the starting address after the OTP address is at its maximum; instead, the data beyond the
maximum OTP address will be undefined. Also, the OTP Read command is not affected by the latency code.
The OTP read command always has one dummy byte of latency as shown below.
Figure 10.60 Read OTP (OTPR 4Bh) Command Sequence
CS#
SCK
SI
7
6
5
4 3
2
1 0 23
1 0
SO
Phase
10.8
7 6
Instruction
Address
Dummy Cycles
5
4 3
2 1 0
Data 1
Advanced Sector Protection Commands
10.8.1
ASP Read (ASPRD 2Bh)
The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP
register contents is shifted out on the serial output SO, least significant byte first. Each bit is shifted out at the
SCK frequency by the falling edge of the SCK signal. It is possible to read the ASP register continuously by
providing multiples of 16 clock cycles. The maximum operating clock frequency for the ASP Read (ASPRD)
command is 133 MHz.
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Figure 10.61 ASPRD Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
Phase
10.8.2
6
Instruction
5
4
3
2
1
0
7
Register Read
6
5
4
3
2
1
0
Repeat Register Read
ASP Program (ASPP 2Fh)
Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN)
command must be issued. After the Write Enable (WREN) command has been decoded, the device will set
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data
bytes on SI, least significant byte first. The ASP Register is two data bytes in length.
The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the
ASPP command is not executed. As soon as CS# is driven to the logic high state, the self-timed ASPP
operation is initiated. While the ASPP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ASPP
operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable Latch
(WEL) is set to a 0.
Figure 10.62 ASPP (2Fh) Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
10.8.3
Instruction
Input ASPR Low Byte
Input ASPR High Byte
DYB Read (DYBRD E0h)
The instruction E0h is latched into SI by the rising edge of the SCK signal. Followed by the 32-bit address
selecting location zero within the desired sector (note, the high order address bits not used by a particular
density device must be zero). Then the 8-bit DYB access register contents are shifted out on the serial output
SO. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read
the same DYB access register continuously by providing multiples of eight clock cycles. The address of the
DYB register does not increment so this is not a means to read the entire DYB array. Each location must be
read with a separate DYB Read command. The maximum operating clock frequency for READ command is
133 MHz.
Figure 10.63 DYBRD Command Sequence
CS#
SCK
SI
7
6
5
4 3
2
1 0 31
1 0
SO
Phase
112
7
Instruction
Address
S25FL512S
6 5
4
3 2
Register
1
0
7 6
5
4
3
2 1 0
Repeat Register
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Data
10.8.4
She et
DYB Write (DYBWR E1h)
Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command
must be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
The DYBWR command is entered by driving CS# to the logic low state, followed by the instruction, the 32-bit
address selecting location zero within the desired sector (note, the high order address bits not used by a
particular density device must be zero), then the data byte on SI. The DYB Access Register is one data byte
in length.
The DYBWR command affects the P_ERR and WIP bits of the Status and Configuration Registers in the
same manner as any other programming operation. CS# must be driven to the logic high state after the eighth
bit of data has been latched in. If not, the DYBWR command is not executed. As soon as CS# is driven to the
logic high state, the self-timed DYBWR operation is initiated. While the DYBWR operation is in progress, the
Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress
(WIP) bit is a 1 during the self-timed DYBWR operation, and is a 0 when it is completed. When the DYBWR
operation is completed, the Write Enable Latch (WEL) is set to a 0.
Figure 10.64 DYBWR (E1h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
31
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
10.8.5
Instruction
Address
Input Data
PPB Read (PPBRD E2h)
The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 32-bit address
selecting location zero within the desired sector (note, the high order address bits not used by a particular
density device must be zero) Then the 8-bit PPB access register contents are shifted out on SO.
It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles.
The address of the PPB register does not increment so this is not a means to read the entire PPB array. Each
location must be read with a separate PPB Read command. The maximum operating clock frequency for the
PPB Read command is 133 MHz.
Figure 10.65 PPBRD (E2h) Command Sequence
CS#
SCK
SI
7
6
5
4 3
2
1 0 31
1 0
SO
Phase
10.8.6
7
Instruction
Address
6 5
4
3 2
Register
1
0
7 6
5
4
3
2 1 0
Repeat Register
PPB Program (PPBP E3h)
Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN)
command must be issued. After the Write Enable (WREN) command has been decoded, the device will set
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PPBP command is entered by driving CS# to the logic low state, followed by the instruction, followed by
the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used
by a particular density device must be zero).
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The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP
command is not executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is
initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the
Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PPBP operation, and
is a 0 when it is completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to a
0.
Figure 10.66 PPBP (E3h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
31
1
0
SO
Phase
10.8.7
Instruction
Address
PPB Erase (PPBE E4h)
The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by
the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the
Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of
the entire PPB memory array. Without CS# being driven to the logic high state after the eighth bit of the
instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to
check if the operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress
and a 0 when the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.
Figure 10.67 PPB Erase (PPBE E4h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.8.8
Instruction
PPB Lock Bit Read (PLBRD A7h)
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is
possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock
Register contents may only be read when the device is in standby state with no other operation in progress. It
is recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new
command to the device.
114
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Figure 10.68 PPB Lock Register Read Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
Phase
10.8.9
6
Instruction
5
4
3
2
1
0
7
Register Read
6
5
4
3
2
1
0
Repeat Register Read
PPB Lock Bit Write (PLBWR A6h)
The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR
command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by
the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the
PLBWR command is not executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR
operation is initiated. While the PLBWR operation is in progress, the Status Register may still be read to
check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed
PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed, the Write
Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.
Figure 10.69 PPB Lock Bit Write (PLBWR A6h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.8.10
Instruction
Password Read (PASSRD E7h)
The correct password value may be read only after it is programmed and before the Password Mode has
been selected by programming the Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the
Password Protection Mode is selected the PASSRD command is ignored.
The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO,
least significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK frequency by
the falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of
64 clock cycles. The maximum operating clock frequency for the PASSRD command is 133 MHz.
Figure 10.70 Password Read (PASSRD E7h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
SO
Phase
10.8.11
2
1
0
7
6
Instruction
5
4
3
Data 1
2
1
0
7
6
5
4
3
2
1
0
Data N
Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded, the device sets the Write Enable Latch (WEL) to enable the PASSP operation.
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The password can only be programmed before the Password Mode is selected by programming the
Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is
selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the
PASSP command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSP
operation is initiated. While the PASSP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSP
cycle, and is a 0 when it is completed. The PASSP command can report a program error in the P_ERR bit of
the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The
maximum clock frequency for the PASSP command is 133 MHz.
Figure 10.71 Password Program (PASSP E8h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
10.8.12
Instruction
Input Password High Byte
Input Password Low Byte
Password Unlock (PASSU E9h)
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the
PASSU command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSU
operation is initiated. While the PASSU operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSU
cycle, and is a 0 when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register,
an error is reported by setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is
necessary to use the CLSR command to clear the status register, the RESET command to software reset the
device, or drive the RESET# input low to initiate a hardware reset, in order to return the P_ERR and WIP bits
to 0. This returns the device to standby state, ready for new commands such as a retry of the PASSU
command.
If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU
command is 133 MHz.
Figure 10.72 Password Unlock (PASSU E9h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
116
Instruction
Input Password Low Byte
S25FL512S
Input Password High Byte
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10.9
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Reset Commands
10.9.1
Software Reset Command (RESET F0h)
The Software Reset command (RESET) restores the device to its initial power up state, except for the volatile
FREEZE bit in the Configuration register CR1[1] and the volatile PPB Lock bit in the PPB Lock Register. The
Freeze bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the
FREEZE bit and set the PPB Lock bit to its protection mode selected power on state, a full power-on-reset
sequence or hardware reset must be done. Note that the non-volatile bits in the configuration register,
TBPROT, TBPARM, and BPNV, retain their previous state after a Software Reset. The Block Protection bits
BP2, BP1, and BP0, in the status register will only be reset if they are configured as volatile via the BPNV bit
in the Configuration Register (CR1[3]) and FREEZE is cleared to zero . The software reset cannot be used to
circumvent the FREEZE or PPB Lock bit protection mechanisms for the other security configuration bits. The
reset command is executed when CS# is brought to high state and requires tRPH time to execute.
Figure 10.73 Software Reset (RESET F0h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
10.9.2
Instruction
Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command can be used to return the device from continuous high performance
read mode back to normal standby awaiting any new command. Because some device packages lack a
hardware RESET# input and a device that is in a continuous high performance read mode may not recognize
any normal SPI command, a system hardware reset or software reset command may not be recognized by
the device. It is recommended to use the MBR command after a system reset when the RESET# signal is not
available or, before sending a software reset, to ensure the device is released from continuous high
performance read mode.
The MBR command sends Ones on SI or IO0 for 8 SCK cycles. IO1 to IO3 are “don’t care” during these
cycles.
Figure 10.74 Mode Bit (MBR FFh) Reset Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
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10.10 Embedded Algorithm Performance Tables
Table 10.7 Program and Erase Performance
Symbol
Typ (1)
Max (2)
Unit
tW
WRR Write Time
Parameter
Min
560
2000
ms
tPP
Page Programming (512 bytes)
340
750/1300 (3)
µs
tSE
Sector Erase Time
(256-kB logical sectors = 4 x 64 kB physical sectors)
520
2600
ms
tBE
Bulk Erase Time (S25FL512S)
103
460
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C; 100,000 cycles max.
3. Industrial temperature range / Automotive In-Cabin temperature range.
Table 10.8 Program Suspend AC Parameters
Parameter
Min
Typical
Program Suspend Latency (tPSL)
Program Resume to next Program
Suspend (tPRS)
Max
40
0.06
100
Unit
Comments
µs
The time from Program Suspend command until
the WIP bit is 0
µs
Minimum is the time needed to issue the next
Program Suspend command but ≥ typical periods
are needed for Program to progress to completion
Table 10.9 Erase Suspend AC Parameters
Parameter
Min
Typical
Erase Suspend Latency (tESL)
Erase Resume to next Erase Suspend
(tERS)
118
Max
45
0.06
100
S25FL512S
Unit
Comments
µs
The time from Erase Suspend command until
the WIP bit is 0
µs
Minimum is the time needed to issue the next
Erase Suspend command but ≥ typical periods
are needed for the Erase to progress to
completion
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11. Software Interface Reference
11.1
Command Summary
Table 11.1 S25FL512S Instruction Set (sorted by instruction) (Sheet 1 of 2)
Instruction
(Hex)
Command Name
01
WRR
02
PP
03
Command Description
Maximum Frequency
(MHz)
Write Register (Status-1, Configuration-1)
133
Page Program (3- or 4-byte address)
133
READ
Read (3- or 4-byte address)
50
04
WRDI
Write Disable
133
05
RDSR1
Read Status Register-1
133
06
WREN
Write Enable
133
07
RDSR2
Read Status Register-2
133
0B
FAST_READ
Fast Read (3- or 4-byte address)
133
0C
4FAST_READ
Fast Read (4-byte address)
133
0D
DDRFR
DDR Fast Read (3- or 4-byte address)
80
0E
4DDRFR
DDR Fast Read (4-byte address)
80
Page Program (4-byte address)
133
12
4PP
13
4READ
Read (4-byte address)
50
14
ABRD
AutoBoot Register Read
133
15
ABWR
AutoBoot Register Write
133
16
BRRD
Bank Register Read
133
17
BRWR
Bank Register Write
133
18
Reserved-18
Reserved
2B
ASPRD
ASP Read
133
2F
ASPP
ASP Program
133
30
CLSR
Clear Status Register - Erase/Program Fail Reset
133
32
QPP
Quad Page Program (3- or 4-byte address)
80
34
4QPP
Quad Page Program (4-byte address)
80
35
RDCR
Read Configuration Register-1
133
38
QPP
Quad Page Program (3- or 4-byte address)
80
3B
DOR
Read Dual Out (3- or 4-byte address)
104
3C
4DOR
Read Dual Out (4-byte address)
104
41
DLPRD
42
OTPP
Data Learning Pattern Read
133
OTP Program
43
133
PNVDLR
Program NV Data Learning Register
4A
133
WVDLR
Write Volatile Data Learning Register
133
OTP Read
133
4B
OTPR
5A
RSFDP
60
BE
6B
QOR
6C
75
Read Serial Flash Discoverable Parameters
133
Bulk Erase
133
Read Quad Out (3- or 4-byte address)
104
4QOR
Read Quad Out (4-byte address)
104
ERSP
Erase Suspend
133
7A
ERRS
Erase Resume
133
85
PGSP
Program Suspend
133
8A
PGRS
Program Resume
133
90
READ_ID (REMS)
Read Electronic Manufacturer Signature
133
9F
RDID
Read ID (JEDEC Manufacturer ID and JEDEC CFI)
133
A3
MPM
Reserved for Multi-I/O-High Perf Mode (MPM)
133
A6
PLBWR
PPB Lock Bit Write
133
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Table 11.1 S25FL512S Instruction Set (sorted by instruction) (Sheet 2 of 2)
Instruction
(Hex)
Command Name
A7
PLBRD
AB
RES
B9
11.2
Maximum Frequency
(MHz)
Command Description
PPB Lock Bit Read
133
Read Electronic Signature
50
BRAC
Bank Register Access
(Legacy Command formerly used for Deep Power Down)
133
BB
DIOR
Dual I/O Read (3- or 4-byte address)
104
BC
4DIOR
Dual I/O Read (4-byte address)
104
BD
DDRDIOR
DDR Dual I/O Read (3- or 4-byte address)
80
BE
4DDRDIOR
DDR Dual I/O Read (4-byte address)
80
C7
BE
Bulk Erase (alternate command)
133
D8
SE
Erase 256 kB (3- or 4-byte address)
133
DC
4SE
Erase 256 kB (4-byte address)
133
E0
DYBRD
DYB Read
133
E1
DYBWR
DYB Write
133
E2
PPBRD
PPB Read
133
E3
PPBP
PPB Program
133
133
E4
PPBE
PPB Erase
E5
Reserved-E5
Reserved
E6
Reserved-E6
Reserved
E7
PASSRD
Password Read
133
E8
PASSP
Password Program
133
E9
PASSU
Password Unlock
133
EB
QIOR
Quad I/O Read (3- or 4-byte address)
104
EC
4QIOR
Quad I/O Read (4-byte address)
104
ED
DDRQIOR
DDR Quad I/O Read (3- or 4-byte address)
80
EE
4DDRQIOR
DDR Quad I/O Read (4-byte address)
80
F0
RESET
Software Reset
133
FF
MBR
Mode Bit Reset
133
Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure and
provides a pointer to each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B
standard. Two optional parameter tables for Sector Map and 4 Byte Address Instructions follow the Basic
Flash table. Spansion provides an additional parameter by pointing to the ID-CFI address space i.e. the
ID-CFI address space is a sub-set of the SFDP address space. The parameter tables portion of the SFDP
data structure are located within the ID-CFI address space and is thus both a CFI parameter and an SFDP
parameter. In this way both SFDP and ID-CFI information can be accessed by either the RSFDP or RDID
commands.
Table 11.2 SFDP Overview Map
Byte Address
0000h
,,,
1000h
...
1120h
...
120
Description
Location zero within JEDEC JESD216B SFDP space – start of SFDP header
Remainder of SFDP header followed by undefined space
Location zero within ID-CFI space – start of ID-CFI parameter tables
ID-CFI parameters
Start of SFDP parameter which is also one of the CFI parameter tables
Remainder of SFDP parameter tables followed by either more CFI parameters or undefined space
S25FL512S
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Data
11.2.1
She et
Field Definitions
Table 11.3 SFDP Header (Sheet 1 of 2)
Relative Byte
Address
SFDP Dword
Address
00h
01h
SFDP Header
1st DWORD
Data
Description
53h
This is the entry point for Read SFDP (5Ah) command i.e. location zero within SFDP space
ASCII “S”
46h
ASCII “F”
02h
44h
ASCII “D”
03h
50h
ASCII “P”
06h
SFDP Minor Revision (06h = JEDEC JESD216 Revision B) This revision is backward
compatible with all prior minor revisions. Minor revisions are changes that define previously
reserved fields, add fields to the end, or that clarify definitions of existing fields. Increments
of the minor revision value indicate that previously reserved parameter fields may have been
assigned a new definition or entire Dwords may have been added to the parameter table.
However, the definition of previously existing fields is unchanged and therefore remain
backward compatible with earlier SFDP parameter table revisions. Software can safely
ignore increments of the minor revision number, as long as only those parameters the
software was designed to support are used i.e. previously reserved fields and additional
Dwords must be masked or ignored . Do not do a simple compare on the minor revision
number, looking only for a match with the revision number that the software is designed to
handle. There is no problem with using a higher number minor revision.
05h
01h
SFDP Major Revision This is the original major revision. This major revision is compatible
with all SFDP reading and parsing software.
06h
05h
Number of Parameter Headers (zero based, 05h = 6 parameters)
07h
FFh
Unused
08h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
00h
Parameter Minor Revision (00h = JESD216) - This older revision parameter header is
provided for any legacy SFDP reading and parsing software that requires seeing a minor
revision 0 parameter header. SFDP software designed to handle later minor revisions
should continue reading parameter headers looking for a higher numbered minor revision
that contains additional parameters for that software revision.
0Ah
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is
compatible with this major revision.
0Bh
09h
Parameter Table Length (in double words = Dwords = 4 byte units) 09h = 9 Dwords
20h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI Flash parameter
byte offset = 1120h
04h
SFDP Header
2nd DWORD
09h
Parameter
Header 0 1st
DWORD
0Ch
0Dh
Parameter
Header 0 2nd
DWORD
11h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
0Fh
FFh
Parameter ID MSB (FFh = JEDEC defined legacy Parameter ID)
10h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
05h
Parameter Minor Revision (05h = JESD216 Revision A) - This older revision parameter
header is provided for any legacy SFDP reading and parsing software that requires seeing a
minor revision 5 parameter header. SFDP software designed to handle later minor revisions
should continue reading parameter headers looking for a later minor revision that contains
additional parameters.
12h
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is
compatible with this major revision.
13h
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
14h
20h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI Flash parameter
byte offset = 1120h address
11h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
0Eh
11h
15h
16h
Parameter
Header 1 1st
DWORD
Parameter
Header 1 2nd
DWORD
17h
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
18h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
06h
Parameter Minor Revision (06h = JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is
compatible with this major revision.
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
19h
1Ah
Parameter
Header 2 1st
DWORD
1Bh
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Table 11.3 SFDP Header (Sheet 2 of 2)
Relative Byte
Address
SFDP Dword
Address
1Ch
1Dh
1Eh
Parameter
Header 2 2nd
DWORD
Description
20h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI Flash parameter
byte offset = 1120h address
11h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
1Fh
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
20h
81h
Parameter ID LSB (81h = SFDP Sector Map Parameter)
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that
recognizes this parameter’s ID is compatible with this major revision.
02h
Parameter Table Length (in double words = Dwords = 4 byte units) 02h = 2 Dwords
60h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC parameter byte offset =
1160h
11h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
84h
Parameter ID LSB (00h = SFDP 4 Byte Address Instructions Parameter)
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that
recognizes this parameter’s ID is compatible with this major revision.
2Bh
02h
Parameter Table Length (in double words = Dwords = 4 byte units) (2h = 2 Dwords)
2Ch
68h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC parameter byte offset =
1168h
21h
22h
Parameter
Header 3 1st
DWORD
23h
24h
25h
26h
Parameter
Header 3 2nd
DWORD
27h
28h
29h
2Ah
2Dh
2Eh
Parameter
Header 4 1st
DWORD
Parameter
Header 4 2nd
DWORD
2Fh
30h
31h
32h
Parameter
Header 5 1st
DWORD
33h
34h
35h
36h
37h
122
Data
Parameter
Header 5 2nd
DWORD
11h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
01h
Parameter ID LSB (Spansion Vendor Specific ID-CFI parameter) Legacy Manufacturer ID
01h = AMD / Spansion
01h
Parameter Minor Revision (01h = ID-CFI updated with SFDP Rev B table)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that
recognizes this parameter’s ID is compatible with this major revision.
5Ch
Parameter Table Length (in double words = Dwords = 4 byte units) CFI starts at 1000h, the
final SFDP parameter (CFI ID = A5) starts at 111Eh (SFDP starting point of 1120h -2hB of
CFI parameter header), for a length of 11EhB excluding the CFI A5 parameter. The final CFI
A5 parameter adds an additional 52hB for a total of 11Eh + 82h = 170hB. 170hB/4 = 5Ch
Dwords.
00h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) Entry point for ID-CFI parameter is
byte offset = 1000h relative to SFDP location zero.
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
01h
Parameter ID MSB (01h = JEDEC JEP106 Bank Number 1)
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Device ID and Common Flash Interface (ID-CFI) Address Map
11.3.1
Field Definitions
Table 11.4 Manufacturer and Device ID
Byte Address
Data
Description
00h
01h
01h
02h (512 Mb)
Manufacturer ID for Spansion
Device ID Most Significant Byte - Memory Interface Type
02h
20h (512 Mb)
Device ID Least Significant Byte - Density
ID-CFI Length - number bytes following. Adding this value to the
current location of 03h gives the address of the last valid location in
the ID-CFI address map. A value of 00h indicates the entire 512-byte
ID-CFI space must be read because the actual length of the ID-CFI
information is longer than can be indicated by this legacy single byte
field. The value is OPN dependent.
03h
xxh
04h
00h (Uniform 256-kB sectors)
05h
80h (FL-S Family)
06h
xxh
07h
xxh
ASCII characters for Model
Refer to Ordering Information on page 142 for the model number
definitions.
08h
xxh
Reserved
Sector Architecture
Family ID
09h
xxh
Reserved
0Ah
xxh
Reserved
0Bh
xxh
Reserved
0Ch
xxh
Reserved
0Dh
xxh
Reserved
0Eh
xxh
Reserved
0Fh
xxh
Reserved
Table 11.5 CFI Query Identification String
Byte Address
Data
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
FL-P backward compatible command set ID
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
53h
46h
Alternate OEM Command Set
ASCII characters “FS” for SPI (F) interface, S Technology
19h
1Ah
51h
00h
Address for Alternate OEM Extended Table
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Table 11.6 CFI System Interface String
Byte Address
Data
Description
1Bh
27h
VCC Min. (erase/program): 100 millivolts
1Ch
36h
VCC Max. (erase/program): 100 millivolts
1Dh
00h
VPP Min. voltage (00h = no VPP present)
1Eh
00h
VPP Max. voltage (00h = no VPP present)
1Fh
06h
Typical timeout per single byte program 2N µs
20h
09h (512B page)
Typical timeout for Min. size Page program 2N µs
(00h = not supported)
21h
09h (256 kB)
Typical timeout per individual sector erase 2N ms
22h
11h (512 Mb)
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
02h
Max. timeout for byte program 2N times typical
24h
02h
Max. timeout for page program 2N times typical
25h
03h
Max. timeout per individual sector erase 2N times typical
26h
03h
Max. timeout for full chip erase 2N times typical
(00h = not supported)
Table 11.7 Device Geometry Definition for 512-Mbit Device
Byte Address
124
Data
Description
27h
1Ah (512 Mb)
28h
02h
29h
01h
2Ah
09h
2Bh
00h
2Ch
01h
2Dh
FFh
2Eh
00h
2Fh
00h
30h
04h
31h thru 3Fh
FFh
N
Device Size = 2 bytes;
Flash Device Interface Description;
0000h = x8 only
0001h = x16 only
0002h = x8/x16 capable
0003h = x32 only
0004h = Single I/O SPI, 3-byte address
0005h = Multi I/O SPI, 3-byte address
0102h = Multi I/O SPI, 3- or 4-byte address
Max. number of bytes in multi-byte write = 2N
(0000 = not supported
0009h = 512B page)
Number of Erase Block Regions within device
1 = Uniform Device, 2 = Boot Device
Erase Block Region 1 Information (refer to JEDEC JEP137)
32 sectors = 32-1 = 001Fh
4-kB sectors = 256 bytes x 0010h
RFU
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Table 11.8 CFI Primary Vendor-Specific Extended Query
Byte Address
Data
40h
50h
Description
41h
52h
42h
49h
43h
31h
Major version number = 1, ASCII
44h
33h
Minor version number = 3, ASCII
Query-unique ASCII string “PRI”
Address Sensitive Unlock (Bits 1-0)
00b = Required
01b = Not Required
45h
21h
Process Technology (Bits 5-2)
0000b = 0.23 µm Floating Gate
0001b = 0.17 µm Floating Gate
0010b = 0.23 µm MirrorBit
0011b = 0.11 µm Floating Gate
0100b = 0.11 µm MirrorBit
0101b = 0.09 µm MirrorBit
1000b = 0.065 µm MirrorBit
46h
02h
Erase Suspend
0 = Not Supported
1 = Read Only
2 = Read and Program
47h
01h
Sector Protect
00 = Not Supported
00h
Temporary Sector Unprotect
00 = Not Supported
X = Number of sectors in group
48h
01 = Supported
Sector Protect/Unprotect Scheme
04 = High Voltage Method
05 = Software Command Locking Method
08 = Advanced Sector Protection Method
09 = Secure
49h
08h
4Ah
00h
Simultaneous Operation
00 = Not Supported
01h
Burst Mode (Synchronous sequential read) support
00 = Not Supported
X = Number of Sectors
4Bh
01 = Supported
Page Mode Type, model dependent
00 = Not Supported
4Ch
xxh
01 = 4 Word Read Page
02 = 8 Read Word Page
03 = 256-Byte Program Page
04 = 512-Byte Program Page
4Dh
00h
ACC (Acceleration) Supply Minimum
00 = Not Supported, 100 mV
4Eh
00h
ACC (Acceleration) Supply Maximum
00 = Not Supported, 100 mV
4Fh
07h
WP# Protection
01 = Whole Chip
04 = Uniform Device with Bottom WP Protect
05 = Uniform Device with Top WP Protect
07 = Uniform Device with Top or Bottom Write Protect (user select)
50h
01h
Program Suspend
00 = Not Supported
01 = Supported
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The Alternate Vendor-Specific Extended Query provides information related to the expanded command set
provided by the FL-S family. The alternate query parameters use a format in which each parameter begins
with an identifier byte and a parameter length byte. Driver software can check each parameter ID and can use
the length value to skip to the next parameter if the parameter is not needed or not recognized by the
software.
Table 11.9 CFI Alternate Vendor-Specific Extended Query Header
Byte Address
Data
Description
51h
41h
52h
4Ch
53h
54h
54h
32h
Major version number = 2, ASCII
55h
30h
Minor version number = 0, ASCII
Query-unique ASCII string “ALT”
Table 11.10 CFI Alternate Vendor-Specific Extended Query Parameter 0
Parameter Relative
Byte Address
Offset
Data
00h
00h
Parameter ID (Ordering Part Number)
01h
10h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
53h
ASCII “S” for manufacturer (Spansion)
03h
32h
04h
35h
Description
ASCII “25” for Product Characters (Single Die SPI)
05h
46h
06h
4Ch
07h
35h (512 Mb)
08h
31h (512 Mb)
ASCII “FL” for Interface Characters (SPI 3 Volt)
09h
32h (512 Mb)
0Ah
53h
0Bh
xxh
0Ch
xxh
0Dh
xxh
0Eh
xxh
0Fh
xxh
10h
xxh
11h
xxh
ASCII characters for density
ASCII “S” for Technology (65nm MirrorBit)
Reserved for Future Use (RFU)
Table 11.11 CFI Alternate Vendor-Specific Extended Query Parameter 80h Address Options
Parameter Relative
Byte Address
Offset
Data
00h
80h
Parameter ID (Ordering Part Number)
01h
01h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
F0h
Bits 7:4 - Reserved = 1111b
Bit 3 - AutoBoot support - Ye s= 0b, No = 1b
Bit 2 - 4-byte address instructions supported - Yes = 0b, No = 1b
Bit 1 - Bank address + 3-byte address instructions supported - Yes = 0b, No = 1b
Bit 0 - 3-byte address instructions supported - Yes = 0b, No = 1b
02h
126
Description
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Table 11.12 CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands
Parameter Relative
Byte Address
Offset
Data
00h
84h
Parameter ID (Suspend Commands
01h
08h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
85h
Program suspend instruction code
03h
28h
Program suspend latency maximum (µs)
04h
8Ah
Program resume instruction code
05h
64h
Program resume to next suspend typical (µs)
06h
75h
Erase suspend instruction code
07h
28h
Erase suspend latency maximum (µs)
08h
7Ah
Erase resume instruction code
09h
64h
Erase resume to next suspend typical (µs)
Description
Table 11.13 CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection
Parameter Relative
Byte Address
Offset
Data
00h
88h
Parameter ID (Data Protection)
01h
04h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
0Ah
OTP size 2N bytes, FFh = not supported
03h
01h
OTP address map format, 01h = FL-S format, FFh = not supported
04h
xxh
Block Protect Type, model dependent
00h = FL-P, FL-S, FFh = not supported
05h
xxh
Advanced Sector Protection type, model dependent
01h = FL-S ASP
Description
Table 11.14 CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing
Parameter Relative
Byte Address
Offset
Data
00h
8Ch
Parameter ID (Reset Timing)
06h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
01h
Description
02h
96h
POR maximum value
03h
01h
POR maximum exponent 2N µs
04h
23h
Hardware Reset maximum value, FFh = not supported
05h
00h
Hardware Reset maximum exponent 2N µs
06h
23h
Software Reset maximum value, FFh = not supported
07h
00h
Software Reset maximum exponent 2N µs
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Table 11.15 CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) (Sheet 1 of 2)
Parameter Relative
Byte Address
Offset
Data
00h
90h
Parameter ID (Latency Code Table)
56h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
01h
128
Description
02h
06h
Number of rows
03h
0Eh
Row length in bytes
04h
46h
Start of header (row 1), ASCII “F” for frequency column header
05h
43h
ASCII “C” for Code column header
06h
03h
Read 3-byte address instruction
07h
13h
Read 4-byte address instruction
08h
0Bh
Read Fast 3-byte address instruction
09h
0Ch
Read Fast 4-byte address instruction
0Ah
3Bh
Read Dual Out 3-byte address instruction
0Bh
3Ch
Read Dual Out 4-byte address instruction
0Ch
6Bh
Read Quad Out 3-byte address instruction
0Dh
6Ch
Read Quad Out 4-byte address instruction
0Eh
BBh
Dual I/O Read 3-byte address instruction
0Fh
BCh
Dual I/O Read 4-byte address instruction
10h
EBh
Quad I/O Read 3-byte address instruction
11h
ECh
Quad I/O Read 4-byte address instruction
12h
32h
Start of row 2, SCK frequency limit for this row (50 MHz)
13h
03h
Latency Code for this row (11b)
14h
00h
Read mode cycles
15h
00h
Read latency cycles
16h
00h
Read Fast mode cycles
17h
00h
Read Fast latency cycles
18h
00h
Read Dual Out mode cycles
19h
00h
Read Dual Out latency cycles
1Ah
00h
Read Quad Out mode cycles
1Bh
00h
Read Quad Out latency cycles
1Ch
00h
Dual I/O Read mode cycles
1Dh
04h
Dual I/O Read latency cycles
1Eh
02h
Quad I/O Read mode cycles
1Fh
01h
Quad I/O Read latency cycles
20h
50h
Start of row 3, SCK frequency limit for this row (80 MHz)
21h
00h
Latency Code for this row (00b)
22h
FFh
Read mode cycles (FFh = command not supported at this frequency)
23h
FFh
Read latency cycles
24h
00h
Read Fast mode cycles
25h
08h
Read Fast latency cycles
26h
00h
Read Dual Out mode cycles
27h
08h
Read Dual Out latency cycles
28h
00h
Read Quad Out mode cycles
29h
08h
Read Quad Out latency cycles
2Ah
00h
Dual I/O Read mode cycles
2Bh
04h
Dual I/O Read latency cycles
2Ch
02h
Quad I/O Read mode cycles
2Dh
04h
Quad I/O Read latency cycles
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Table 11.15 CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) (Sheet 2 of 2)
Parameter Relative
Byte Address
Offset
Data
2Eh
5Ah
Start of row 4, SCK frequency limit for this row (90 MHz)
2Fh
01h
Latency Code for this row (01b)
30h
FFh
Read mode cycles (FFh = command not supported at this frequency)
31h
FFh
Read latency cycles
32h
00h
Read Fast mode cycles
33h
08h
Read Fast latency cycles
34h
00h
Read Dual Out mode cycles
Description
35h
08h
Read Dual Out latency cycles
36h
00h
Read Quad Out mode cycles
37h
08h
Read Quad Out latency cycles
38h
00h
Dual I/O Read mode cycles
39h
05h
Dual I/O Read latency cycles
3Ah
02h
Quad I/O Read mode cycles
3Bh
04h
Quad I/O Read latency cycles
3Ch
68h
Start of row 5, SCK frequency limit for this row (104 MHz)
3Dh
02h
Latency Code for this row (10b)
3Eh
FFh
Read mode cycles (FFh = command not supported at this frequency)
3Fh
FFh
Read latency cycles
40h
00h
Read Fast mode cycles
41h
08h
Read Fast latency cycles
42h
00h
Read Dual Out mode cycles
43h
08h
Read Dual Out latency cycles
44h
00h
Read Quad Out mode cycles
45h
08h
Read Quad Out latency cycles
46h
00h
Dual I/O Read mode cycles
47h
06h
Dual I/O Read latency cycles
48h
02h
Quad I/O Read mode cycles
49h
05h
Quad I/O Read latency cycles
4Ah
85h
Start of row 6, SCK frequency limit for this row (133 MHz)
4Bh
02h
Latency Code for this row (10b)
4Ch
FFh
Read mode cycles (FFh = command not supported at this frequency)
4Dh
FFh
Read latency cycles
4Eh
00h
Read Fast mode cycles
4Fh
08h
Read Fast latency cycles
50h
FFh
Read Dual Out mode cycles
51h
FFh
Read Dual Out latency cycles
52h
FFh
Read Quad Out mode cycles
53h
FFh
Read Quad Out latency cycles
54h
FFh
Dual I/O Read mode cycles
55h
FFh
Dual I/O Read latency cycles
56h
FFh
Quad I/O Read mode cycles
57h
FFh
Quad I/O Read latency cycles
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Table 11.16 CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - HPLC DDR
130
Parameter Relative
Byte Address
Offset
Data
00h
9Ah
Parameter ID (Latency Code Table)
01h
2Ah
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
Description
02h
05h
Number of rows
03h
08h
Row length in bytes
04h
46h
Start of header (row 1), ASCII “F” for frequency column header
05h
43h
ASCII “C” for Code column header
06h
0Dh
Read Fast DDR 3-byte address instruction
07h
0Eh
Read Fast DDR 4-byte address instruction
08h
BDh
DDR Dual I/O Read 3-byte address instruction
09h
BEh
DDR Dual I/O Read 4-byte address instruction
0Ah
EDh
Read DDR Quad I/O 3-byte address instruction
0Bh
EEh
Read DDR Quad I/O 4-byte address instruction
0Ch
32h
Start of row 2, SCK frequency limit for this row (50 MHz)
0Dh
03h
Latency Code for this row (11b)
0Eh
00h
Read Fast DDR mode cycles
0Fh
04h
Read Fast DDR latency cycles
10h
00h
DDR Dual I/O Read mode cycles
11h
04h
DDR Dual I/O Read latency cycles
12h
01h
Read DDR Quad I/O mode cycles
13h
03h
Read DDR Quad I/O latency cycles
14h
42h
Start of row 3, SCK frequency limit for this row (66 MHz)
15h
00h
Latency Code for this row (00b)
16h
00h
Read Fast DDR mode cycles
17h
05h
Read Fast DDR latency cycles
18h
00h
DDR Dual I/O Read mode cycles
19h
06h
DDR Dual I/O Read latency cycles
1Ah
01h
Read DDR Quad I/O mode cycles
1Bh
06h
Read DDR Quad I/O latency cycles
1Ch
42h
Start of row 4, SCK frequency limit for this row (66 MHz)
1Dh
01h
Latency Code for this row (01b)
1Eh
00h
Read Fast DDR mode cycles
1Fh
06h
Read Fast DDR latency cycles
20h
00h
DDR Dual I/O Read mode cycles
21h
07h
DDR Dual I/O Read latency cycles
22h
01h
Read DDR Quad I/O mode cycles
23h
07h
Read DDR Quad I/O latency cycles
24h
42h
Start of row 5, SCK frequency limit for this row (66 MHz)
25h
02h
Latency Code for this row (10b)
26h
00h
Read Fast DDR mode cycles
27h
07h
Read Fast DDR latency cycles
28h
00h
DDR Dual I/O Read mode cycles
29h
08h
DDR Dual I/O Read latency cycles
2Ah
01h
Read DDR Quad I/O mode cycles
2Bh
08h
Read DDR Quad I/O latency cycles
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Table 11.17 CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Sheet 1 of 2)
Parameter Relative
Byte Address
Offset
Data
00h
90h
Parameter ID (Latency Code Table)
56h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
01h
Description
02h
06h
Number of rows
03h
0Eh
Row length in bytes
04h
46h
Start of header (row 1), ASCII “F” for frequency column header
05h
43h
ASCII “C” for Code column header
06h
03h
Read 3-byte address instruction
07h
13h
Read 4-byte address instruction
08h
0Bh
Read Fast 3-byte address instruction
09h
0Ch
Read Fast 4-byte address instruction
0Ah
3Bh
Read Dual Out 3-byte address instruction
0Bh
3Ch
Read Dual Out 4-byte address instruction
0Ch
6Bh
Read Quad Out 3-byte address instruction
0Dh
6Ch
Read Quad Out 4-byte address instruction
0Eh
BBh
Dual I/O Read 3-byte address instruction
0Fh
BCh
Dual I/O Read 4-byte address instruction
10h
EBh
Quad I/O Read 3-byte address instruction
11h
ECh
Quad I/O Read 4-byte address instruction
12h
32h
Start of row 2, SCK frequency limit for this row (50 MHz)
13h
03h
Latency Code for this row (11b)
14h
00h
Read mode cycles
15h
00h
Read latency cycles
16h
00h
Read Fast mode cycles
17h
00h
Read Fast latency cycles
18h
00h
Read Dual Out mode cycles
19h
00h
Read Dual Out latency cycles
1Ah
00h
Read Quad Out mode cycles
1Bh
00h
Read Quad Out latency cycles
1Ch
04h
Dual I/O Read mode cycles
1Dh
00h
Dual I/O Read latency cycles
1Eh
02h
Quad I/O Read mode cycles
1Fh
01h
Quad I/O Read latency cycles
20h
50h
Start of row 3, SCK frequency limit for this row (80 MHz)
21h
00h
Latency Code for this row (00b)
22h
FFh
Read mode cycles (FFh = command not supported at this frequency)
23h
FFh
Read latency cycles
24h
00h
Read Fast mode cycles
25h
08h
Read Fast latency cycles
26h
00h
Read Dual Out mode cycles
27h
08h
Read Dual Out latency cycles
28h
00h
Read Quad Out mode cycles
29h
08h
Read Quad Out latency cycles
2Ah
04h
Dual I/O Read mode cycles
2Bh
00h
Dual I/O Read latency cycles
2Ch
02h
Quad I/O Read mode cycles
2Dh
04h
Quad I/O Read latency cycles
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Table 11.17 CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Sheet 2 of 2)
132
Parameter Relative
Byte Address
Offset
Data
2Eh
5Ah
Start of row 4, SCK frequency limit for this row (90 MHz)
2Fh
01h
Latency Code for this row (01b)
30h
FFh
Read mode cycles (FFh = command not supported at this frequency)
31h
FFh
Read latency cycles
32h
00h
Read Fast mode cycles
33h
08h
Read Fast latency cycles
34h
00h
Read Dual Out mode cycles
Description
35h
08h
Read Dual Out latency cycles
36h
00h
Read Quad Out mode cycles
37h
08h
Read Quad Out latency cycles
38h
04h
Dual I/O Read mode cycles
39h
01h
Dual I/O Read latency cycles
3Ah
02h
Quad I/O Read mode cycles
3Bh
04h
Quad I/O Read latency cycles
3Ch
68h
Start of row 5, SCK frequency limit for this row (104 MHz)
3Dh
02h
Latency Code for this row (10b)
3Eh
FFh
Read mode cycles (FFh = command not supported at this frequency)
3Fh
FFh
Read latency cycles
40h
00h
Read Fast mode cycles
41h
08h
Read Fast latency cycles
42h
00h
Read Dual Out mode cycles
43h
08h
Read Dual Out latency cycles
44h
00h
Read Quad Out mode cycles
45h
08h
Read Quad Out latency cycles
46h
04h
Dual I/O Read mode cycles
47h
02h
Dual I/O Read latency cycles
48h
02h
Quad I/O Read mode cycles
49h
05h
Quad I/O Read latency cycles
4Ah
85h
Start of row 6, SCK frequency limit for this row (133 MHz)
4Bh
02h
Latency Code for this row (10b)
4Ch
FFh
Read mode cycles (FFh = command not supported at this frequency)
4Dh
FFh
Read latency cycles
4Eh
00h
Read Fast mode cycles
4Fh
08h
Read Fast latency cycles
50h
FFh
Read Dual Out mode cycles
51h
FFh
Read Dual Out latency cycles
52h
FFh
Read Quad Out mode cycles
53h
FFh
Read Quad Out latency cycles
54h
FFh
Dual I/O Read mode cycles
55h
FFh
Dual I/O Read latency cycles
56h
FFh
Quad I/O Read mode cycles
57h
FFh
Quad I/O Read latency cycles
S25FL512S
S25FL512S_00_09 January 21, 2015
Data
She et
Table 11.18 CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR
Parameter Relative
Byte Address
Offset
Data
00h
9Ah
Parameter ID (Latency Code Table)
01h
2Ah
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
Description
02h
05h
Number of rows
03h
08h
Row length in bytes
04h
46h
Start of header (row 1), ASCII “F” for frequency column header
05h
43h
ASCII “C” for Code column header
06h
0Dh
Read Fast DDR 3-byte address instruction
07h
0Eh
Read Fast DDR 4-byte address instruction
08h
BDh
DDR Dual I/O Read 3-byte address instruction
09h
BEh
DDR Dual I/O Read 4-byte address instruction
0Ah
EDh
Read DDR Quad I/O 3-byte address instruction
0Bh
EEh
Read DDR Quad I/O 4-byte address instruction
0Ch
32h
Start of row 2, SCK frequency limit for this row (50 MHz)
0Dh
03h
Latency Code for this row (11b)
0Eh
04h
Read Fast DDR mode cycles
0Fh
01h
Read Fast DDR latency cycles
10h
02h
DDR Dual I/O Read mode cycles
11h
02h
DDR Dual I/O Read latency cycles
12h
01h
Read DDR Quad I/O mode cycles
13h
03h
Read DDR Quad I/O latency cycles
14h
42h
Start of row 3, SCK frequency limit for this row (66 MHz)
15h
00h
Latency Code for this row (00b)
16h
04h
Read Fast DDR mode cycles
17h
02h
Read Fast DDR latency cycles
18h
02h
DDR Dual I/O Read mode cycles
19h
04h
DDR Dual I/O Read latency cycles
1Ah
01h
Read DDR Quad I/O mode cycles
1Bh
06h
Read DDR Quad I/O latency cycles
1Ch
42h
Start of row 4, SCK frequency limit for this row (66 MHz)
1Dh
01h
Latency Code for this row (01b)
1Eh
04h
Read Fast DDR mode cycles
1Fh
04h
Read Fast DDR latency cycles
20h
02h
DDR Dual I/O Read mode cycles
21h
05h
DDR Dual I/O Read latency cycles
22h
01h
Read DDR Quad I/O mode cycles
23h
07h
Read DDR Quad I/O latency cycles
24h
42h
Start of row 5, SCK frequency limit for this row (66 MHz)
25h
02h
Latency Code for this row (10b)
26h
04h
Read Fast DDR mode cycles
27h
05h
Read Fast DDR latency cycles
28h
02h
DDR Dual I/O Read mode cycles
29h
06h
DDR Dual I/O Read latency cycles
2Ah
01h
Read DDR Quad I/O mode cycles
2Bh
08h
Read DDR Quad I/O latency cycles
January 21, 2015 S25FL512S_00_09
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Table 11.19 CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU
Parameter Relative
Byte Address
Offset
Data
00h
F0h
Parameter ID (RFU)
0Fh
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
01h
Description
02h
FFh
RFU
...
FFh
RFU
10h
FFh
RFU
Table 11.20 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B
(Sheet 1 of 5)
CFI
Parameter
Relative
Byte
Address
Offset
SFDP
Parameter
Relative
Byte
Address
Offset
SFDP Dword
Name
Data
00h
—
N/A
A5h
CFI Parameter ID (JEDEC SFDP)
01h
—
N/A
50h
CFI Parameter Length (The number of following bytes in this parameter.
Adding this value to the current location value +1 = the first byte of the next
parameter)
E7h
Start of SFDP JEDEC parameter, located at 1120h in the overall SFDP
address space. Bits 7:5 = unused = 111b Bit 4:3 = 06h is status register
write instruction & status register is default non-volatile= 00b Bit 2 =
Program Buffer > 64Bytes = 1 Bits 1:0 = Uniform 4KB erase unavailable =
11b
FFh
Bits 15:8 = Uniform 4KB erase opcode = not supported = FFh
02h
00h
03h
01h
04h
02h
F3h
(FLxxxSAG)
F7h
(FLxxxSDP)
05h
03h
FFh
06h
04h
07h
05h
08h
06h
09h
07h
0Ah
08h
0Bh
09h
0Ch
0Ah
0Dh
0Bh
0Eh
0Ch
0Fh
0Dh
10h
0Eh
11h
0Fh
12h
134
JEDEC Basic
Flash
Parameter
Dword-1
11h
14h
12h
15h
13h
Bit 23 = Unused = 1b Bit 22 = Supports Quad Out Read = Yes = 1b Bit 21
= Supports Quad I/O Read = Yes =1b Bit 20 = Supports Dual I/O Read =
Yes = 1b Bit19 = Supports DDR 0= No, 1 = Yes Bit 18:17 = Number of
Address Bytes, 3 or 4 = 01b Bit 16 = Supports Dual Out Read = Yes = 1b
Bits 31:24 = Unused = FFh
FFh
JEDEC Basic
Flash
Parameter
Dword-2
FFh
Density in bits, zero based, 512Mb = 1FFFFFFFh
FFh
1Fh
JEDEC Basic
Flash
Parameter
Dword-3
JEDEC Basic
Flash
Parameter
Dword-4
10h
13h
Description
JEDEC Basic
Flash
Parameter
Dword-5
44h
Bits 7:5 = number of Quad I/O Mode cycles = 010b Bits 4:0 = number of
Quad I/O Dummy cycles = 00100b for default latency code 00b
EBh
Quad I/O instruction code
08h
Bits 23:21 = number of Quad Out Mode cycles = 000b Bits 20:16 = number
of Quad Out Dummy cycles = 01000b
6Bh
Quad Out instruction code
08h
Bits 7:5 = number of Dual Out Mode cycles = 000b Bits 4:0 = number of
Dual Out Dummy cycles = 01000b for default latency code
3Bh
Dual Out instruction code
04h (HPLC)
80h
(EHPLC)
Bits 23:21 = number of Dual I/O Mode cycles = 100b for EHPLC or 000b
for HPLC Bits 20:16 = number of Dual I/O Dummy cycles = 00000b for
EHPLC or 00100b for HPLC Default Latency code = 00b
BBh
Dual I/O instruction code
EEh
Bits 7:5 RFU = 111b Bit 4 = Quad All supported = No = 0b Bits 3:1 RFU =
111b Bit 0 = Dual All not supported = 0b
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:16 = RFU = FFh
FFh
Bits 31:24 = RFU = FFh
S25FL512S
S25FL512S_00_09 January 21, 2015
Data
She et
Table 11.20 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B
(Sheet 2 of 5)
CFI
Parameter
Relative
Byte
Address
Offset
SFDP
Parameter
Relative
Byte
Address
Offset
16h
14h
17h
15h
18h
16h
SFDP Dword
Name
JEDEC Basic
Flash
Parameter
Dword-6
Data
Description
FFh
Bits 7:0 = RFU = FFh
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of Dual All Mode cycles = 111b Bits 20:16 = number
of Dual All Dummy cycles = 11111b
19h
17h
FFh
Dual All instruction code
1Ah
18h
FFh
Bits 7:0 = RFU = FFh
1Bh
19h
1Ch
1Ah
1Dh
1Bh
1Eh
1Ch
JEDEC Basic
Flash
Parameter
Dword-7
JEDEC Basic
Flash
Parameter
Dword-8
FFh
FFh
Bits 15:8 = RFU = FFh
EBh
Bits 23:21 = number of Quad All Mode cycles = 111b Bits 20:16 = number
of Quad All Dummy cycles = 11111b
00h
Quad All mode Quad I/O (4-4-4) instruction code
FFh
Erase type 1 instruction = not supported = FFh
00h
Erase type 2 size 2N Bytes = not supported = 00h
1Fh
1Dh
20h
1Eh
21h
1Fh
FFh
Erase type 2 instruction = not supported = FFh
22h
20h
12h
Erase type 3 size 2N Bytes = 256KB = 12h
23h
21h
D8h
Erase type 3 instruction
24h
22h
00h
Erase type 4 size 2N Bytes = not supported = 00h
25h
23h
FFh
Erase type 4 instruction = not supported = FFh
26h
24h
F2h
27h
25h
FFh
28h
26h
0Fh
Bits 31:30 = Erase type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms,
10b: 128 ms, 11b: 1 s) = RFU = 11b Bits 29:25 = Erase type 4 Erase,
Typical time count = RFU = 11111b ( typ erase time = count +1 * units =
RFU ) Bits 24:23 = Erase type 3 Erase, Typical time units (00b: 1 ms, 01b:
16 ms, 10b: 128 ms, 11b: 1 s) = 128mS = 10b Bits 22:18 = Erase type 3
Erase, Typical time count = 00011b ( typ erase time = count +1 * units =
4*128mS = 512mS) Bits 17:16 = Erase type 2 Erase, Typical time units
(00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = RFU = 11b Bits 15:11 =
Erase type 2 Erase, Typical time count = RFU = 11111b ( typ erase time =
count +1 * units = RFU ) Bits 10:9 = Erase type 1 Erase, Typical time units
(00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = RFU = 11b Bits 8:4 =
Erase type 1 Erase, Typical time count = RFU = 11111b ( typ erase time =
count +1 * units = RFU ) Bits 3:0 = Multiplier from typical erase time to
maximum erase time = 2*(N+1), N=2h = 6x multiplier Binary Fields: 1111111-10-00011-11-11111-11-11111-0010 Nibble Format:
1111_1111_0000_1111_1111_1111_1111_0010 Hex Format:
FF_0F_FF_F2
JEDEC Basic
Flash
Parameter
Dword-9
JEDEC Basic
Flash
Parameter
Dword-10
29h
27h
FFh
2Ah
28h
91h
2Bh
29h
25h
2Ch
2Ah
07h
JEDEC Basic
Flash
Parameter
Dword-11
2Dh
2Bh
January 21, 2015 S25FL512S_00_09
D9h
Bit 31 Reserved = 1b Bits 30:29 = Chip Erase, Typical time units (00b: 16
ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s = 10b Bits 28:24 = Chip Erase,
Typical time count, (count+1)*units, count = 11001b, ( typ Program time =
count +1 * units = 26*.4uS = 104S Bits 23 = Byte Program Typical time,
additional byte units (0b:1uS, 1b:8uS) = 1uS = 0b Bits 22:19 = Byte
Program Typical time, additional byte count, (count+1)*units, count =
0000b, ( typ Program time = count +1 * units = 1*1uS = 1uS Bits 18 = Byte
Program Typical time, first byte units (0b:1uS, 1b:8uS) = 8uS = 1b Bits
17:14 = Byte Program Typical time, first byte count, (count+1)*units, count
= 1100b, ( typ Program time = count +1 * units = 13*8uS = 104uS Bits 13 =
Page Program Typical time units (0b:8uS, 1b:64uS) = 64uS = 1b Bits 12:8
= Page Program Typical time count, (count+1)*units, count = 00101b, ( typ
Program time = count +1 * units =6*64uS = 384uS) Bits 7:4 = Page size 2N,
N=9h, = 512B page Bits 3:0 = Multiplier from typical time to maximum for
Page or Byte program = 2*(N+1), N=1h = 4x multiplier Binary Fields: 1-1011001-0-0000-1-1100-1-00101-1001-0001 Nibble Format:
1101_1001_0000_0111_0010_0101_1001_0001 Hex Format:
D9_07_25_91
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Table 11.20 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B
(Sheet 3 of 5)
CFI
Parameter
Relative
Byte
Address
Offset
SFDP
Parameter
Relative
Byte
Address
Offset
2Eh
2Fh
30h
SFDP Dword
Name
Data
Description
2Ch
ECh
2Dh
83h
2Eh
18h
Bit 31 = Suspend and Resume supported = 0b Bits 30:29 = Suspend inprogress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b:
64us) = 8us= 10b Bits 28:24 = Suspend in-progress erase max latency
count = 00101b, max erase suspend latency = count +1 * units = 6*8uS =
48uS Bits 23:20 = Erase resume to suspend interval count = 0001b,
interval = count +1 * 64us = 2 * 64us = 128us Bits 19:18 = Suspend inprogress program max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b:
64us) = 8us= 10b Bits 17:13 = Suspend in-progress program max latency
count = 00100b, max erase suspend latency = count +1 * units = 5*8uS =
40uS Bits 12:9 = Program resume to suspend interval count = 0001b,
interval = count +1 * 64us = 2 * 64us = 128us Bit 8 = RFU = 1b Bits 7:4 =
Prohibited operations during erase suspend = xxx0b: May not initiate a
new erase anywhere (erase nesting not permitted) + xx1xb: May not
initiate a page program in the erase suspended sector size + x1xxb: May
not initiate a read in the erase suspended sector size + 1xxxb: The erase
and program restrictions in bits 5:4 are sufficient = 1110b Bits 3:0 =
Prohibited Operations During Program Suspend = xxx0b: May not initiate a
new erase anywhere (erase nesting not permitted) + xx0xb: May not
initiate a new page program anywhere (program nesting not permitted) +
x1xxb: May not initiate a read in the program suspended page size +
1xxxb: The erase and program restrictions in bits 1:0 are sufficient = 1100b
Binary Fields: 0-10-00101-0001-10-00100-0001-1-1110-1100 Nibble
Format: 0100_0101_0001_1000_1000_0011_1110_1100 Hex Format:
45_18_83_EC
JEDEC Basic
Flash
Parameter
Dword-12
31h
2Fh
45h
32h
30h
33h
31h
34h
32h
35h
33h
75h
36h
34h
F7h
37h
35h
FFh
38h
36h
8Ah
JEDEC Basic
Flash
Parameter
Dword-13
85h
7Ah
FFh
JEDEC Basic
Flash
Parameter
Dword-14
39h
37h
FFh
3Ah
38h
00h
3Bh
39h
F6h
3Ch
3Ah
5Dh
JEDEC Basic
Flash
Parameter
Dword-15
3Dh
136
3Bh
FFh
Bits 31:24 = Erase Suspend Instruction = 75h Bits 23:16 = Erase Resume
Instruction = 7Ah Bits 15:8 = Program Suspend Instruction = 85h Bits 7:0 =
Program Resume Instruction = 8Ah
Bit 31 = Deep Power Down Supported = not supported = 1 Bits 30:23 =
Enter Deep Power Down Instruction = not supported = FFh Bits 22:15 =
Exit Deep Power Down Instruction = not supported = FFh Bits 14:13 = Exit
Deep Power Down to next operation delay units = (00b: 128ns, 01b: 1us,
10b: 8us, 11b: 64us) = 64us = 11b Bits 12:8 = Exit Deep Power Down to
next operation delay count = 11111b, Exit Deep Power Down to next
operation delay = (count+1)*units = not supported Bits 7:4 = RFU = Fh Bit
3:2 = Status Register Polling Device Busy = 01b: Legacy status polling
supported = Use legacy polling by reading the Status Register with 05h
instruction and checking WIP bit[0] (0=ready; 1=busy). Bits 1:0 = RFU =
11b Binary Fields: 1-11111111-11111111-11-11111-1111-01-11 Nibble
Format: 1111_1111_1111_1111_1111_1111_1111_0111 Hex Format:
FF_FF_FF_F7
Bits 31:24 = RFU = FFh Bit 23 = Hold and WP Disable = not supported =
0b Bits 22:20 = Quad Enable Requirements = 101b: QE is bit 1 of the
status register 2. Status register 1 is read using Read Status instruction
05h. Status register 2 is read using instruction 35h. QE is set via Write
Status instruction 01h with two data bytes where bit 1 of the second byte is
one. It is cleared via Write Status with two data bytes where bit 1 of the
second byte is zero. Bits 19:16 0-4-4 Mode Entry Method = xxx1b: Mode
Bits[7:0] = A5h Note: QE must be set prior to using this mode + x1xxb:
Mode Bits[7:0] = Axh + 1xxxb: RFU = 1101b Bits 15:10 0-4-4 Mode Exit
Method = xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the
end of the current read operation + xx_1xxxb: Input Fh (mode bit reset) on
DQ0-DQ3 for 8 clocks. This will terminate the mode prior to the next read
operation. + x1_xxxxb: Mode Bit[7:0] != Axh + 1x_x1xx: RFU
S25FL512S
S25FL512S_00_09 January 21, 2015
Data
She et
Table 11.20 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B
(Sheet 4 of 5)
CFI
Parameter
Relative
Byte
Address
Offset
SFDP
Parameter
Relative
Byte
Address
Offset
3Eh
3Fh
40h
SFDP Dword
Name
Data
Description
3Ch
F0h
3Dh
28h
3Eh
FAh
Bits 31:24 = Enter 4-Byte Addressing = xxxx_1xxxb: 8-bit volatile bank
register used to define A[30:A24] bits. MSB (bit[7]) is used to enable/
disable 4-byte address mode. When MSB is set to ‘1’, 4-byte address
mode is active and A[30:24] bits are don’t care. Read with instruction 16h.
Write instruction is 17h with 1 byte of data. When MSB is cleared to ‘0’,
select the active 128 Mbit segment by setting the appropriate A[30:24] bits
and use 3-Byte addressing. + xx1x_xxxxb: Supports dedicated 4-Byte
address instruction set. Consult vendor data sheet for the instruction set
definition or look for 4 Byte Address Parameter Table. + 1xxx_xxxxb:
Reserved = 10101000b Bits 23:14 = Exit 4-Byte Addressing =
xx_xxxx_1xxxb: 8-bit volatile bank register used to define A[30:A24] bits.
MSB (bit[7]) is used to enable/disable 4-byte address mode. When MSB is
cleared to ‘0’, 3-byte address mode is active and A30:A24 are used to
select the active 128 Mbit memory segment. Read with instruction 16h.
Write instruction is 17h, data length is 1 byte. + xx_xx1x_xxxxb: Hardware
reset + xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD) +
xx_1xxx_xxxxb: Power cycle + x1_xxxx_xxxxb: Reserved +
1x_xxxx_xxxxb: Reserved = 1111101000b Bits 13:8 = Soft Reset and
Rescue Sequence Support = x0_1xxxb: issue instruction F0h + 1x_xxxxb:
exit 0-4-4 mode is required prior to other reset sequences above if the
device may be operating in this mode. = 101000b Bit 7 = RFU = 1 Bits 6:0
= Volatile or Non-Volatile Register and Write Enable Instruction for Status
Register 1 = xx1_xxxxb: Status Register 1 contains a mix of volatile and
non-volatile bits. The 06h instruction is used to enable writing of the
register. + x1x_xxxxb: Reserved + 1xx_xxxxb: Reserved = 1110000b
Binary Fields: 10101000-1111101000-101000-1-1110000 Nibble Format:
1010_1000_1111_1010_0010_1000_1111_0000 Hex Format:
A8_FA_28_F0
JEDEC Basic
Flash
Parameter
Dword-16
41h
3Fh
A8h
42h
40h
43h
41h
44h
42h
45h
43h
46h
44h
F4h
47h
45h
FFh
48h
46h
49h
47h
JEDEC Sector
Map Parameter
Dword-1
Config-0
Header
JEDEC Sector
Map Parameter
Dword-2
Config-0
Region-0
FFh
00h
00h
FFh
FFh
3Fh
4Ah
48h
FFh
4Bh
49h
E8h
4Ch
4Ah
FFh
4Dh
4Bh
January 21, 2015 S25FL512S_00_09
JEDEC 4 Byte
Address
Instructions
Parameter
Dword-1
Bits 31:24 = RFU = FFh Bits 23:16 = Region count (Dwords -1) = 00h: One
region Bits 15:8 = Configuration ID = 00h: Uniform 256KB sectors Bits 7:2
= RFU = 111111b Bit 1 = Map Descriptor = 1 Bit 0 = The end descriptor = 1
FFh
Bits 31:8 = Region size = 00FFFFh: Region size as count-1 of 256 Byte
units = 64MB/256 = 256K Count = 262144, value = count -1 = 262144 -1 =
262143 = 3FFFFh Bits 4:7 = RFU = Fh Erase Type not supported = 0/
supported = 1 Bits 3 = Erase Type 4 support = 0b ---Erase Type 4 is not
defined Bits 2 = Erase Type 3 support = 1b ---Erase Type 3 is 256KB erase
and is supported in the 256KB sector region Bits 1 = Erase Type 2 support
= 0b ---Erase Type 2 is 64KB erase and is not supported in the 256KB
sector region Bits 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB
erase and is not supported in the 256KB sector region
Supported = 1, Not Supported = 0 Bits 31:20 = RFU = FFFh Bit 19 =
Support for non-volatile individual sector lock write command,
Instruction=E3h = 1 Bit 18 = Support for non-volatile individual sector lock
read command, Instruction=E2h = 1 Bit 17 = Support for volatile individual
sector lock Write command, Instruction=E1h = 1 Bit 16 = Support for
volatile individual sector lock Read command, Instruction=E0h = 1 Bit 15 =
Support for (1-4-4) DTR_Read Command, Instruction=EEh = 1 Bit 14 =
Support for (1-2-2) DTR_Read Command, Instruction=BEh = 1 Bit 13 =
Support for (1-1-1) DTR_Read Command, Instruction=0Eh = 1 Bit 12 =
Support for Erase Command – Type 4 = 0 Bit 11 = Support for Erase
Command – Type 3 = 1 Bit 10 = Support for Erase Command – Type 2 = 0
Bit 9 = Support for Erase Command – Type 1 = 0 Bit 8 = Support for (1-4-4)
Page Program Command, Instruction=3Eh =0 Bit 7 = Support for (1-1-4)
Page Program Command, Instruction=34h = 1 Bit 6 = Support for (1-1-1)
Page Program Command, Instruction=12h = 1 Bit 5 = Support for (1-4-4)
FAST_READ Command, Instruction=ECh = 1 Bit 4 = Support for (1-1-4)
FAST_READ Command, Instruction=6Ch = 1 Bit 3 = Support for (1-2-2)
FAST_READ Command, Instruction=BCh = 1 Bit 2 = Support for (1-1-2)
FAST_READ Command, Instruction=3Ch = 1 Bit 1 = Support for (1-1-1)
FAST_READ Command, Instruction=0Ch = 1 Bit 0 = Support for (1-1-1)
READ Command, Instruction=13h = 1
S25FL512S
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Table 11.20 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B
(Sheet 5 of 5)
CFI
Parameter
Relative
Byte
Address
Offset
SFDP
Parameter
Relative
Byte
Address
Offset
4Eh
4Ch
4Fh
4Dh
50h
4Eh
51h
4Fh
SFDP Dword
Name
Data
JEDEC 4 Byte
Address
Instructions
Parameter
Dword-2
Description
FFh
FFh
DCh
Bits 31:24 = FFh = Instruction for Erase Type 4: RFU Bits 23:16 = DCh =
Instruction for Erase Type 3 Bits 15:8 = FFh = Instruction for Erase Type 2:
RFU Bits 7:0 = FFh = Instruction for Erase Type 1: RFU
FFh
This parameter type (Parameter ID F0h) may appear multiple times and have a different length each time.
The parameter is used to reserve space in the ID-CFI map or to force space (pad) to align a following
parameter to a required boundary.
11.4
Registers
The register maps are copied in this section as a quick reference. See Registers on page 57 for the full
description of the register contents.
Table 11.21 Status Register-1 (SR1)
Bits
Field
Name
Function
Type
Default State
Description
7
SRWD
Status Register
Write Disable
Non-Volatile
0
1 = Locks state of SRWD, BP, and configuration register
bits when WP# is low by ignoring WRR command
0 = No protection, even when WP# is low
6
P_ERR
Programming
Error Occurred
Volatile, Read only
0
1 = Error occurred
0 = No Error
5
E_ERR
Erase Error
Occurred
Volatile, Read only
0
1= Error occurred
0 = No Error
Block
Protection
Volatile if CR1[3]=1,
Non-Volatile if
CR1[3]=0
4
BP2
3
BP1
2
BP0
1
0
138
WEL
Write Enable
Latch
WIP
Write in
Progress
Volatile
Volatile, Read only
S25FL512S
1 if CR1[3]=1,
0 when
shipped from
Spansion
Protects selected range of sectors (Block) from Program
or Erase
0
1 = Device accepts Write Registers (WRR), program or
erase commands
0 = Device ignores Write Registers (WRR), program or
erase commands
This bit is not affected by WRR, only WREN and WRDI
commands affect this bit.
0
1= Device Busy, a Write Registers (WRR), program,
erase or other operation is in progress
0 = Ready Device is in standby mode and can accept
commands
S25FL512S_00_09 January 21, 2015
Data
She et
Table 11.22 Configuration Register (CR1)
Bits
Field Name
7
LC1
Default
State
Function
Type
Latency Code
Non-Volatile
0
Selects number of initial read latency cycles
See Latency Code Tables
6
LC0
5
TBPROT
Configures Start of
Block Protection
OTP
0
1 = BP starts at bottom (Low address)
0 = BP starts at top (High address)
4
RFU
RFU
RFU
0
Reserved for Future Use
3
BPNV
Configures BP2-0 in
Status Register
OTP
0
1 = Volatile
0 = Non-Volatile
2
RFU
RFU
RFU
0
Reserved for Future Use
QUAD
Puts the device into
Quad I/O operation
Non-Volatile
0
1 = Quad
0 = Dual or Serial
FREEZE
Lock current state of
BP2-0 bits in Status
Register, TBPROT in
Configuration
Register, and OTP
regions
Volatile
0
1 = Block Protection and OTP locked
0 = Block Protection and OTP un-locked
1
0
0
Description
Table 11.23 Status Register-2 (SR2)
Bits
Field Name
Function
Type
Default State
Description
7
RFU
Reserved
0
6
RFU
Reserved
0
Reserved for Future Use
Reserved for Future Use
5
RFU
Reserved
0
Reserved for Future Use
4
RFU
Reserved
0
Reserved for Future Use
Reserved for Future Use
3
RFU
Reserved
0
2
RFU
Reserved
0
Reserved for Future Use
1
ES
Erase Suspend
Volatile, Read only
0
1 = In erase suspend mode.
0 = Not in erase suspend mode.
0
PS
Program
Suspend
Volatile, Read only
0
1 = In program suspend mode.
0 = Not in program suspend mode.
Table 11.24 Bank Address Register (BAR)
Bits
7
Field Name
EXTADD
Function
Extended Address
Enable
Type
Default State
Volatile
0b
Description
1 = 4-byte (32-bits) addressing required from command.
0 = 3-byte (24-bits) addressing from command + Bank
Address
6 to 2
RFU
Reserved
Volatile
00000b
1
BA25
Bank Address
Volatile
0
A25 for 512 Mb device
0
RFU
Bank Address
Volatile
0
RFU for lower density device
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Table 11.25 ASP Register (ASPR)
Function
Type
Default
State
Bits
Field Name
Description
15 to 9
RFU
Reserved
OTP
1
Reserved for Future Use
8
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
7
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
6
RFU
Reserved
OTP
1
Reserved for Future Use
5
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
4
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
3
RFU
Reserved
OTP
(Note 1)
Reserved for Future Use
2
PWDMLB
Password
Protection Mode
Lock Bit
OTP
1
0 = Password Protection Mode permanently enabled.
1 = Password Protection Mode not permanently enabled.
1
PSTMLB
Persistent
Protection Mode
Lock Bit
OTP
1
0 = Persistent Protection Mode permanently enabled.
1 = Persistent Protection Mode not permanently enabled.
0
RFU
Reserved
OTP
1
Reserved for Future Use
Note:
1. Default value depends on ordering part number, see Initial Delivery State on page 141.
Table 11.26 Password Register (PASS)
Bits
Field
Name
Function
Type
Default State
Description
63 to 0
PWD
Hidden
Password
OTP
FFFFFFFFFFFFFFFFh
Non-volatile OTP storage of 64-bit password. The password is
no longer readable after the password protection mode is
selected by programming ASP register bit 2 to zero.
Table 11.27 PPB Lock Register (PPBL)
Bits
Field Name
Function
Type
Default State
7 to 1
RFU
Reserved
Volatile
00h
Volatile
Persistent Protection Mode = 1
Password Protection Mode = 0
0
PPBLOCK
Protect PPB Array
Description
Reserved for Future Use
0 = PPB array protected until next power cycle
or hardware reset
1 = PPB array may be programmed or erased
Table 11.28 PPB Access Register (PPBAR)
Bits
7 to 0
Field Name
PPB
Function
Type
Read or Program per
sector PPB
Non-volatile
Default
State
FFh
Description
00h = PPB for the sector addressed by the PPBRD or
PPBP command is programmed to ‘0’, protecting that
sector from program or erase operations.
FFh = PPB for the sector addressed by the PPBRD or
PPBP command is erased to ‘1’, not protecting that
sector from program or erase operations.
Table 11.29 DYB Access Register (DYBAR)
Bits
7 to 0
140
Field Name
DYB
Function
Read or Write
per sector DYB
Type
Default State
Volatile
FFh
S25FL512S
Description
00h = DYB for the sector addressed by the DYBRD or DYBP
command is cleared to ‘0’, protecting that sector from program or
erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBP
command is set to ‘1’, not protecting that sector from program or
erase operations.
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Table 11.30 Non-Volatile Data Learning Register (NVDLR)
Bits
Field Name
Function
Type
Default State
7 to 0
NVDLP
Non-Volatile
Data Learning
Pattern
OTP
00h
Description
OTP value that may be transferred to the host during DDR read
command latency (dummy) cycles to provide a training pattern to
help the host more accurately center the data capture point in the
received data bits.
Table 11.31 Volatile Data Learning Register (NVDLR)
Bits
7 to 0
11.5
Field Name
Function
VDLP
Volatile Data
Learning
Pattern
Type
Default State
Volatile
Takes the
value of
NVDLR
during POR
or Reset
Description
Volatile copy of the NVDLP used to enable and deliver the Data
Learning Pattern (DLP) to the outputs. The VDLP may be changed
by the host during system operation.
Initial Delivery State
The device is shipped from Spansion with non-volatile bits set as follows:
 The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).
 The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased
to FFh.
 The SFDP address space contains the values as defined in the description of the SFDP address space.
 The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.
 The Status Register 1 contains 00h (all SR1 bits are cleared to 0’s).
 The Configuration Register 1 contains 00h.
 The Autoboot register contains 00h.
 The Password Register contains FFFFFFFF-FFFFFFFFh
 All PPB bits are 1.
 The ASP Register contents depend on the ordering options selected:
Table 11.32 ASP Register Content
Ordering Part Number Model
ASPR Default Value
01, 21, 31, R1, A1, B1, C1, D1,
91, Q1, 71, 61, 81
FE7Fh
K1, L1. S1, T1, Y1, Z1,
M1, N1, U1, V1, W1, X1
FE4Fh
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Ordering Information
12. Ordering Information FL512S
The ordering part number is formed by a valid combination of the following:
S25FL
512
S
AG
M
F
I
0
0
1
Packing Type
0
= Tray
1
= Tube
3
= 13” Tape and Reel
Model Number (Sector Type)
1
=
Uniform 256-kB sectors
Model Number (Latency Type, Package Details, RESET# and VIO Support)
0
=
EHPLC, SO footprint
2
=
EHPLC, 5 x 5 ball BGA footprint
3
=
EHPLC, 4 x 6 ball BGA footprint
G
=
EHPLC, SO footprint with RESET#
R
=
EHPLC, SO footprint with RESET# and VIO
A
=
EHPLC, 5 x 5 ball BGA footprint with RESET# and VIO
B
=
EHPLC, 4 x 6 ball BGA footprint with RESET# and VIO
C
=
EHPLC, 5 x 5 ball BGA footprint with RESET#
D
=
EHPLC, 4 x 6 ball BGA footprint with RESET#
9
=
HPLC, SO footprint
4
=
HPLC, 5 x 5 ball BGA footprint
8
= HPLC, 4 x 6 ball BGA footprint
H
=
HPLC, SO footprint with RESET#
Q
=
HPLC, SO footprint with RESET# and VIO
7
=
HPLC, 5 x 5 ball BGA footprint with RESET# and VIO
6
=
HPLC, 4 x 6 ball BGA footprint with RESET# and VIO
E
=
HPLC, 5 x 5 ball BGA footprint with RESET#
F
= HPLC, 4 x 6 ball BGA footprint with RESET#
Temperature Range
I
=
Industrial (–40°C to + 85°C)
V
=
Automotive In-Cabin (–40°C to + 105°C)
Package Materials
F
= Lead (Pb)-free
H
= Low-Halogen, Lead (Pb)-free
Package Type
M
= 16-pin SO package
B
= 24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
AG =
DP =
DS =
133 MHz
66 MHz DDR
80 MHz DDR
Device Technology
S
=
0.065 µm MirrorBit Process Technology
Density
512 =
512 Mbit
Device Family
S25FL
Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory
Notes:
1. EHPLC = Enhanced High Performance Latency Code table.
2. HPLC = High Performance Latency Code table.
3. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer.
142
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Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Valid Combinations
Base Ordering
Part Number
Speed
Option
Package and
Temperature
Model Number
AG
MFI, MFV
01, G1, R1
DP
MFI, MFV
01, G1
DS
MFV, MFI
01
AG
BHI, BHV
21, 31, A1, B1, C1, D1
DP
BHI, BHV
21, 31, C1, D1
MFV, MFI
01
0, 1, 3
FL512S + S + (Temp) + F + (Model
Number)
BHI, BHV
21
0, 3
FL512S + S + (Temp) + H + (Model
Number)
Packing Type
Package Marking (1)
FL512S + A + (Temp) + F + (Model
Number)
0, 1, 3
S25FL512S
FL512S + D + (Temp) + F + (Model
Number)
0, 1, 3
FL512S + S + (Temp) + F + (Model
Number)
FL512S + A + (Temp) + H + (Model
Number)
0, 3
FL512S + D + (Temp) + H + (Model
Number)
DS
Note:
1. Example, S25FL512SAGMFI000 package marking would be FL512SAIF00.
13. Contacting Spansion
Obtain the latest list of company locations and contact information at:
http://www.spansion.com/About/Pages/Locations.aspx
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14. Revision History
Section
Description
Revision 01 (December 20, 2011)
Initial release
Revision 02 (March 2, 2012)
General
Changed data sheet designation from Advance Information to Preliminary
Performance Summary
Current Consumption table: corrected Serial Read 50 MHz and Serial Read 133 MHz values
DC Characteristics
DC Characteristics table: corrected ICC1 values
SDR AC Characteristics
AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) table: corrected TCSH and TSU
Max values
AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V) table: corrected TCSH
and TSU Max values
Embedded Algorithm Performance
Tables
Program and Erase Performance table: corrected TW Typ and Max values
Device ID and Common Flash Interface
(ID-CFI) Address Map
Updated table: CFI Alternate Vendor-Specific Extended Query Parameter 0
Revision 03 (May 2, 2012)
Global
Added 105°C updates
Ordering Information
Updated Valid Combinations table
Embedded Algorithm Performance
Tables
Updated table: Program and Erase Performance
Revision 04 (June 13, 2012)
SDR AC Characteristics
Updated tHO value from 0 Min to 2 ns Min
Revision 05 (April 12, 2013)
Global
Data Sheet designation updated from Preliminary to Full Production
Revision 06 (December 20, 2013)
Global
Performance Summary
80 MHz DDR Read operation added
Updated Maximum Read Rates DDR (VIO = VCC = 3V to 3.6V) table
Current Consumption table: added Quad DDR Read 80 MHz
Migration Notes
FL Generations Comparison table: updated DDR values for FL-S
SDR AC Characteristics
Updated Clock Timing figure
DDR AC Characteristics
Updated AC Characteristics — DDR Operation table
DDR Output Timing
Updated SPI DDR Data Valid Window figure and Notes
Ordering Information
Added 80 MHz to Speed option
Valid Combinations table: added DS to Speed Option
Revision 07 (January 8, 2014)
DDR AC Characteristics
Removed AC Characteristics 80 MHz Operation table
Revision 08 (December 18, 2014)
AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) table: removed tV (Min) value
SDR AC Characteristics
Bank Address Register
AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V) table: removed
tV (Min) value
Bank Address Register (BAR) table: corrected Bit 0
Updated section
Serial Flash Discoverable Parameters
(SFDP) Address Map
SFDP Overview Map table: updated
Field Definitions: updated SFDP Header table
Field Definitions: added CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC
SFDP Rev B table
Device ID and Common Flash Interface
(ID-CFI) Address Map
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Section
Description
Revision 09 (January 21, 2015)
Capacitance Characteristics
Capacitance table: added TA = 25°C under Test Conditions
SDR AC Characteristics
AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) table: changed tSU (Min)
Configuration Register 1 (CR1)
Latency Codes for DDR Enhanced High Performance table: added 80 MHz
Command Set Summary
S25FL512S Command Set (sorted by function) table: updated Maximum Frequency (MHz) of DDR
Command Descriptions to 80 MHz
Read Memory Array Commands
Changed 66 MHz to 80 MHz throughout section
Software Interface Reference
S25FL512S Instruction Set (sorted by instruction) table: updated Maximum Frequency (MHz) of
DDR Command Descriptions to 80 MHz
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2011-2015 Spansion LLC. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
HyperBus™, HyperFlash™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other
countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
146
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