A Route to Chaos Using FPGAs Volume I

A Route to Chaos Using FPGAs Volume I
Bharathwaj Muthuswamy, Santo Banerjee
A Route To Chaos Using FPGAs
Volume I : Experimental Observations
January 27, 2015
Dedicated to the pursuers of knowledge...
Preface
If a picture is worth a thousand words, how much is a video worth? To answer this
question, please take a look at a video demonstrating the capabilities of a FieldProgrammable Gate Array (FPGA) for implementing chaotic systems: https://
www.youtube.com/watch?v=wwa7aylrLGo&index=1&list=PLr9kJR
BrySkf3P4yiWAxzCdzaWhTof-PW
Now that we have you convinced about the robustness of 21st century FPGAs, let
us talk about the book. In a single sentence, the purpose of this volume is to expose
the reader to the exciting world of chaos (science) using FPGAs (engineering). This
book differs from other texts on chaos because of a variety of reasons. First, our
experimental approach towards chaos theory attempts to provide the reader with
a ”physical-feel” for the mathematics involved. Second, the medium that we use
for physical realization and experiments is the FPGA. These devices are massively
parallel digital architectures that can be configured to realize a variety of logic functions. Hence unlike micro controllers that run sequential compiled code, FPGAs can
be configured to execute systems of discrete difference equations in parallel. Moreover, ever since the early 21st century, one could realize design specifications in a
mathematical simulation software such as Simulink directly onto an FPGA. Also,
21st century FPGA development boards have digital-to-analog converters, hence the
signals viewed on the oscilloscope are analog waveforms from our digital chaotic
realization!
Nevertheless maximizing the capabilities of an FPGA requires the user to deeply
understand the underlying hardware and also the software used to realize the differential equations. This is achieved by another feature in this book: a lab component (along with exercises) in each chapter. In the lab component, readers are asked
to investigate chaotic phenomena via MATLAB (or Simulink), design digital logic
systems on FPGAs and also implement a variety of chaotic systems. The specific
objective of the lab depends obviously on the particular chapter. Note that one could
use FPGAs and development platforms from other manufacturers to understand the
concepts in this book. But, for the sake of brevity, we use the Altera Cyclone IV
FPGA on a Terasic DE2-115 board which includes an on-board ADA (Analog-toDigital and Digital-to-Analog) from the audio codec (coder/decoder). Details on
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Preface
procuring hardware are in Chapter 2. However understand that FPGA technology is
changing rapidly and the hardware (software) used in this book will become quickly
outdated. Thus from this book, one has to learn the concepts used in implementing
nonlinear ordinary differential equations on FPGAs.
This text is intended for final-year undergraduate or graduate electrical engineering students who are interested in a scientific application of an engineered product.
Knowledge of digital logic system (combinational and sequential) realization on FPGAs and an integral calculus course is necessary. A first-year undergraduate course
in FPGA based digital logic and a first-year undergraduate calculus course is necessary and sufficient. However, the only pre-requisite for understanding this book
is a thirst for knowledge and the willingness to overcome failure. To quote Albert
Einstein, ”Anyone who has never made a mistake has never tried anything new”.
This book is organized as follows: Chapter 1 is an introduction to both chaos
theory and FPGAs. Some mathematical foundations for working with chaos are discussed. Chapter 2 gives an overview of the FPGA hardware platform and includes
tutorials on utilizing the DE2-115. Chapter 3 shows how to simulate and realize
some chaotic ODEs on FPGAs. This chapter combines the ideas in chapters 1 and
2 to show the reader how to implement chaotic systems on FPGAs. Chapters 4 and
5 are more mathematical in nature and serve as a precursor to Volume II (Theoretical Methods). Chapter 4 shows how to study bifurcation mechanisms in chaotic
systems using FPGAs. Chapter 5 covers time delayed systems. The FPGA is particularly suited for implementing time delayed systems because one can implement
the necessary delay using n flip-flops (n could be 4096!) by using only five lines in
a hardware description language!
There is also a companion website: http://www.harpgroup.org/muthu
swamy/ARouteToChaosUsingFPGAs/ARouteToChaosUsingFPGAs.ht
ml for the book that has recorded video solutions (maximum 20 minutes) to all book
exercises+labs, FPGA reference designs and corresponding videos (maximum 20
minutes), forums for discussing other hardware platforms etc. It would be prudent
to have access to the internet as you read through this book.
Note that this volume is an ”engineering cookbook” that is full of examples for
implementing nonlinear dynamical (chaotic) systems on FPGAs. The second volume (theoretical methods) is more rigorous and covers concepts for digital emulation of chaotic dynamics. However, either volumes can be used as standalone texts
for understanding FPGA -based chaotic system implementation.
This book was typeset using LATEX. Image processing software used were GIMP
2.8, Inkscape 0.48 and Xfig 3.2. An iPhone 5 camera was used for pictures. NCH
Debut Professional v1.64 was used for screen recordings. Oscilloscopes used were
the Agilent 54645D and the Tektronix 2205.
Happy chaos via FPGAs!
Bharathwaj Muthuswamy, Santo Banerjee
Ankara, Turkey, December 2012
About the book title : it is intended to be a pun on the mathematical concept of a route to chaos.
About the cover art: we show a chaotic attractor from the Ikeda DDE.
Acknowledgements
There are a plethora of folks that we have to thank. From Dr. Muthusamy’s perspective, first and
foremost, he would like to thank his MS and PhD advisor Dr. Leon O. Chua for all his support
and guidance. Ferenc Kovac and Carl Chun from the University of California, Berkeley (Cal)
have been both professional and personal mentors throughout the years. Dr. Pravin Varaiya was
also instrumental for Dr. Muthuswamy’s success at Cal. Dr. Muthuswamy’s exposure to cluster
computing in 2001 at the Los Alamos National Labs under the guidance of Ron Minnich was
invaluable.
This book was technically four years in the making. Dr. Fondjo, Dr. Kennedy and Ferenc Kovac were extremely helpful in reviewing the very first sample chapters from this book, back in
2010. Faculty colleagues at the Milwaukee School of Engineering, Dr. Jovan Jevtic and Dr. Gerald
Thomas, have also provided much needed feedback. Altera (Jeff Nigh, Greg Nash) and Stephen
Brown (University of Toronto) donated software and DE2-115 hardware respectively, along with
providing much needed feedback. Many thanks to anonymous peer-reviewers from Springer. Their
comments were extremely insightful and helpful in fixing errors from the very first version of this
book.
Most of the material in this book is based primarily off Dr. Muthuswamy’s and Dr. Banerjee’s
research into FPGA-based nonlinear dynamics. As a result, our research students throughout the
years, specifically Ms. Valli from the Vellore Institute of Technology (VIT); Chris Feilbach, Andrew Przybylski from MSOE and students (Andrew, Curt, Dan, Jonathan, Ryan and Scott) from
the very first nonlinear dynamics course offering at MSOE deserve special mention. In addition,
Cornell University’s ECE 5760 course served as an inspiration for this book. Dr. Muthuswamy
was also inspired by Dr. Kennedy et. al.’s work on Digital Signal Processor-based investigation of
Chua’s circuit family (in Chua’s Circuit : A Paradigm for Chaos, edited by N. Madan, World Scientific, 1993, pp.769 - 792). In many ways, Dr. Muthuswamy’s use of FPGAs is a “21st century”
extension of Dr. Kennedy et. al.’s work. Dr. Muthuswamy would also particularly like to thank
Ms. Valli, Dr. Ganesan, Dr. C. K. Subramaniam and others from VIT for providing much needed
support in the Summer of 2014 for completing this volume.
A round of applause to Dr. Muthuswamy’s spouse, Ms. Deepika Srinivasan, for her help in
producing many of the figures. Her ”architectural eye” was very helpful in formatting figures so
that the appropriate information is properly represented.
Finally, last but not the least, we would like to thank Springer for being very patient with us
despite the delay in delivering the final manuscript.
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Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 An Introduction to Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1
A Brief History of Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2
An Application of Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 An Introduction to Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . .
1.2.1
History of FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2
Why FPGAs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Some Basic Mathematical Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
Linear Versus Nonlinear Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
Linear Versus Nonlinear Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3
Fixed (Equilibrium) Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.4
System Behaviour Near Fixed Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lab 1 : Introduction to MATLAB and Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
1
6
8
8
9
10
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13
16
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21
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25
25
2
Designing Hardware for FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 The FPGA Development Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 The Architecture of an FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 An Overview of the Hardware and Software Development Platform . . . . . . . . . . .
2.3.1
An Overview of the Terasic DE2-115 Development Board . . . . . . . . . . .
2.3.2
VHDL Primer and Using the Quartus Toolset . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Audio Codec Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Timing Closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lab 2 : Introduction to Altera FPGA Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3
Chaotic ODEs : FPGA Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Euler’s Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Specifying Chaotic Systems for FPGAs Using DSP Builder . . . . . . . . . . . . . . . . .
3.2.1
The Lorenz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Introduction to Functional Simulation and In-System Debugging . . . . . . . . . . . . .
3.4 Functional Simulation of Chaotic Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Debugging Using SignalTap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents
3.5.1
General Concepts - An Illustration Using a Simple Example . . . . . . . . .
3.5.2
Debugging the Chen system Using SignalTap . . . . . . . . . . . . . . . . . . . . . .
3.6 Hardware Debugging Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Observing a Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2
Identifying the Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
Sources of Errors in VHDL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Another Example - A Highly Complex Attractor System . . . . . . . . . . . . . . . . . . . .
3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lab 3 : The Muthuswamy-Chua Chaotic System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4
Bifurcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 The Concept of Bifurcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Routes to Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
Period-Doubling Route To Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2
Period-Adding Route To Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3
Quasi-periodic Route To Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4
Intermittency Route to Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5
Chaotic Transients and Crisis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Bifurcation Experiments With an FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
Period-Doubling Route To Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2
Period-Adding Route To Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3
Quasi-periodic Route to Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4
Intermittency Route To Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5
Chaotic Transients and Crisis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lab 4 : Displaying Bifurcation Parameter(s) on the LCD . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5
Chaotic DDEs : FPGA Examples and Synchronization Applications . . . . . . . . . . . . .
5.1 An Introduction to Time Delay Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Simulating DDEs in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 FPGA Realization of DDEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Applications of (Time Delayed) Chaotic Systems - Synchronization . . . . . . . . . . .
5.4.1
Unidirectional Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2
Bidirectional Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lab 5 : The Lang-Kobayashi Chaotic Delay Differential Equation . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A
Introduction to MATLAB and Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 Simulating Nonlinear Differential Equations in MATLAB . . . . . . . . . . . . . . . . . . .
A.1.1 Starting MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.2 Simulating a One Dimensional System in MATLAB . . . . . . . . . . . . . . . .
A.2 Simulating Nonlinear Differential Equations in Simulink . . . . . . . . . . . . . . . . . . . .
A.2.1 Starting Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.2 Simulating a One Dimensional System in Simulink . . . . . . . . . . . . . . . . .
A.2.3 Simulating a Chaotic System in Simulink . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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B
Chapter 1 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
B.1 The Lorenz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
B.2 Linear Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
C
Chapter 2 VHDL and Simulink DSP Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.1 VHDL Generic Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2 VHDL Seven Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.3 Top-Level for Generic Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.4 Seconds Counter with Single Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.5 Abstracting the FPGA Development Flow in Simulink . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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D
Chapter 3 VHDL, MATLAB Code and ModelSim Scripts . . . . . . . . . . . . . . . . . . . . . .
D.1 VHDL Specification of the Lorenz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.2 VHDL Specification of the Lorenz System with Mathematical Labelling of
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.3 MATLAB Code for Plotting Lorenz System Trajectory Obtained from Euler’s
Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.4 Complete VHDL Specification of the Lorenz System . . . . . . . . . . . . . . . . . . . . . . .
D.5 Complete VHDL Specification of the Highly Complex Attractor System . . . . . . .
D.6 VHDL Testbench for Chen System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.7 ModelSim Script File for Chen System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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E
F
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Chapter 4 MATLAB Code, VHDL and ModelSim Scripts . . . . . . . . . . . . . . . . . . . . . .
E.1 R¨ossler System Specification in MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.2 Period-1 Limit Cycle for the R¨ossler System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.3 MATLAB Code for Period-Doubling Route to Chaos . . . . . . . . . . . . . . . . . . . . . . .
E.4 MATLAB Code for Chua Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.5 MATLAB Code for Period-Adding Route to Chaos . . . . . . . . . . . . . . . . . . . . . . . . .
E.6 MATLAB Code for Torus Breakdown System . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.7 MATLAB Code for Quasi-periodic Route To Chaos . . . . . . . . . . . . . . . . . . . . . . . .
E.8 MATLAB Code with Chua Oscillator Parameter Values for Intermittency
Route to Chaos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.9 MATLAB Code for Plotting Intermittency Route to Chaos . . . . . . . . . . . . . . . . . .
E.10 MATLAB Code for Resource-Consumer-Predator Model . . . . . . . . . . . . . . . . . . .
E.11 MATLAB Code for Chaotic Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.12 VHDL Specification for Single Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.13 ModelSim Testbench for Single Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.14 ModelSim Script File for Single Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.15 VHDL Specification of Period-Doubling Route to Chaos . . . . . . . . . . . . . . . . . . . .
E.16 VHDL Specification for Period-Adding Route to Chaos . . . . . . . . . . . . . . . . . . . . .
E.17 VHDL Specification for Quasi-Periodic Route to Chaos . . . . . . . . . . . . . . . . . . . . .
E.18 VHDL Specification for Chaotic Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171
171
171
172
173
174
175
176
Chapter 5 VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.1 Flip-flops in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.2 VHDL Tapped Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.3 VHDL Specification of Ikeda DDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.4 VHDL Specification of DDE with Sigmoidal Nonlinearity . . . . . . . . . . . . . . . . . . .
F.5 VHDL Specification of DDE with Signum Nonlinearity . . . . . . . . . . . . . . . . . . . . .
F.6 VHDL Specification for Chaotic DDE Synchronization . . . . . . . . . . . . . . . . . . . . .
F.7 DE2 Chaotic DDE Specification Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
207
207
207
208
212
215
219
223
177
178
180
181
183
184
185
186
191
196
200
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
xiv
Contents
Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Acronyms
ADC
DAC
DDE
DSP
FPGA
FSM
HDL
LAB
LE
LUT
ODE
PLL
ROM
RTL
SDC
SDRAM
SMA
VHDL
Analog to Digital Converter
Digital to Analog Converter
Delay Differential Equation
Digital Signal Processor/Processing
Field Programmable Gate Array
Finite State Machine
Hardware Description Language
Logic Array Block
Logic Element
Look Up Table
Ordinary Differential Equation
Phase Locked Loop
Read Only Memory
Register Transfer Level
Synopsys Design Constraints
Synchronous Dynamic Random-Access Memory
Subminiature Version A
Very High Speed Integrated Circuit Hardware Description Language
xv
Mathematical Notation
The mathematical notation used in this book is standard [12]; nevertheless, this section clarifies the
notation used throughout the book.
1. Lowercase letters from the Latin alphabet (a − z) are used to represent variables, with italic
script for scalars and bold invariably reserved for vectors. The letter t is of course√always
reserved for time. n is usually reserved for the dimension of the state. j is used for −1, in
accordance with the usual electrical engineering convention. Mathematical constants such as
π , e, h (Planck’s constant) have their usual meaning. Other constant scalars are usually drawn
from lower case Greek alphabet. SI units are used.
2. Independent variable in functions and differential equations is time (unless otherwise stated)
because physical processes change with time.
3. Differentiation is expressed as follows. Time derivatives use Leibniz’s ( dy
dx , for example) or
Newton’s notation: one, two or three dots over a variable corresponds to the number of derivatives and a parenthetical superscripted numeral for higher derivatives. Leibniz’s notation is used
explicitly for non-time derivatives.
4. Real-valued functions, whether scalar- or vector-valued, are usually taken (as conventionally)
from lowercase Latin letters f through h, r and s along with x through z.
5. Vector-valued functions and vector fields are bold-faced as well, the difference between the two
being indicated by the argument font; hence f(x) and f(x) respectively.
6. Constant matrices and vectors are represented with capital and lowercase letters respectively,
from the beginning of the Latin alphabet. Vectors are again bolded.
7. In the context of linear time-invariant systems the usual conventions are respected: A is the state
matrix B(b) is the input matrix (vector).
8. Subscripts denote elements of a matrix or vector: di is the ith column of D; x j is the jth element
of x. Plain numerical superscripts on the other hand may indicate exponentiation, a recursive
operation or simply a numbering depending on context. A superscripted T indicates matrix
transpose. I is reserved for the identity matrix. All vectors are assumed to be columns.
9. Σi is used for summations, sampling interval is symbolized by T and ∈ denotes set inclusions.
10. Calligraphic script (R etc.) is reserved for sets which use capital letters. Elements of sets are
then represented with the corresponding lowercase letter. Excepted are the well known number
sets which are rendered in doublestruck bold: N, Z, Q, R and C for the naturals, integers,
rationals, reals and complex numbers respectively. The natural numbers are taken to include
0. Restrictions to positive or negative subsets are indicated by a superscripted + or −. The
△
symbol = is used for definitions. ∀ and ∃ have the usual meaning of ”for all” and ”there exists”
respectively.
xvii
Conventions Used In The Book
Each chapter starts with an epigraph, the purpose is to evoke the intellectual curiosity of the reader.
Chapters are divided into sections and subsections for clarity. We also embed MATLAB code or
VHDL (when relevant) as shown below. We use line numbers for ease of code discussion.
1
MATLAB code or VHDL goes here
We have placed the most of the MATLAB code and VHDL in appendices to avoid disrupting
content flow.
MATLAB, FPGA Design Suite (Quartus, ModelSim etc.) menu actions along with respective
library block names and in-text elements of VHDL syntax are indicated by Boldface notation.
Note however that further details for utilizing the toolsets are incorporated in online videos on the
companion website.
We have used UPPERCASE to describe FPGA pins. The distinction between pins and acronyms
will be clear from the context.
Figures and equations are numbered consecutively. Mathematical notation has already been
clarified. The convention for a definition is shown below.
Definition 0.1. Definitions are typeset as shown.
The book has a variety of solved examples, in light gray shade.
Solved Examples
All references are placed at the end of each chapter for convenience. We use a number surrounded by square brackets for in-text references, example [5]. Occasionally, important terminology and concepts are highlighted using red font. Although references are hyperlinked, only online
URLs are colored midnight blue for clarity.
The chapter concludes with a comprehensive set of exercises and a lab.
On a concluding remark, when you find typos in the book please contact the authors with
constructive comments: [email protected], [email protected]
xix
Chapter 1
Introduction
Lorenz, E. N. Deterministic
Nonperiodic Flow [11]
Abstract This chapter will provide a historical overview of chaos and FPGAs. We will begin
with a history of how chaos was observed (but unidentified) in a problem related to astronomy
and made its way into electronics. On the flip side, the history of FPGAs is a part of the history
of Silicon Valley. Next we will look at some very important and fundamental concepts: linearity
versus nonlinearity, equilibrium points and Jacobi linearization.
As you read through the chapter and work through the exercises, you will realize that nonlinear
systems have ”rich behaviour” compared to linear systems. Yet you will also notice that relatively
simple nonlinear systems can give rise to this rich behaviour.
1.1 An Introduction to Chaos
In this section, we will first go through a very brief history of chaos. The purpose is to emphasize
that chaos is essentially a scientific phenomenon that has been studied by engineering for potential
applications. The application we will consider is synchronization, although chaos has been used in
robot locomotion [20].
1.1.1 A Brief History of Chaos
Chaos was first observed in the late 19th century [1] via a problem related to astronomy! Henri
Poincar´e, a professor at the University of Paris, observed chaos in the circular restricted three body
problem: three masses interacting with each other (think Sun-Earth-Moon). Poincar´e determined
that it was impossible to accurately predict long term motion of the masses. He discovered the
crucial ideas of stable and unstable manifolds which are special curves in the plane. However, even
after Poincar´e’s seminal work, chaos was largely forgotten till the 1920s.
Edwin H. Armstrong invented the regenerative circuit for high frequency oscillations in 1912
[9]. It is possible that he actually observed chaos [9]. In 1927, Dutch physicists Van Der Pol and
Van Der Mark proposed one of the first nonlinear oscillators [22], [23]. They observed that at
certain drive frequencies, an ”irregular noise” is present. These were one of the first discovered
instances of deterministic chaos in circuits.
In the late 1950s, a meteorologist at MIT named Edward Lorenz acquired a Royal-McBee LGP30 computer with 16 kilobyte (KB) of internal memory [1]. Although Lorenz initially started with
1
2
1 Introduction
a system of twelve ordinary differential equations, he eventually simplified the model to a system
of three ordinary coupled nonlinear differential equations now known as the Lorenz equations [11],
shown in Eqs.(1.1), (1.2), (1.3).
x˙ = −σ x + σ y
(1.1)
y˙ = −xz + ρ x − y
(1.2)
z˙ = xy − β z
(1.3)
Notice that since our notation implies that the independent variable in differential equations is time,
we have omitted t in the differential equations for clarity. The equations are said to be coupled
because the right-hand-side (RHS) of one equation involves a variable from another equation. For
example, the RHS of Eq.(1.1) involves y(t), which is the solution to Eq.(1.2). The exact definition
of nonlinearity will be clarified later in this chapter.
Fig. 1.1 shows the result of simulating Eqs.(1.1), (1.2), (1.3) in MATLAB. The code for simulation is shown in listing B.1. You should type the code and reproduce the plot, refer to Appendix A
at the end of the book for a short tutorial on MATLAB (and Simulink). The parameter values are
σ = 10, ρ = 28, β = 38 . Initial conditions are x(0) = 10, y(0) = 20, z(0) = 30.
45
40
35
z
30
25
20
15
10
5
−20
−15
−10
−5
0
x
5
10
15
20
Fig. 1.1: The Lorenz Butterfly as plotted in two dimensional phase space.
Fig. 1.1 is the phase plot obtained from our system. A phase plot is a parametric plot, in this
case the x-axis function is x(t) and the y-axis function is z(t). In other words, each point on the
plot of the object in Fig. 1.1 corresponds to a solution (x(t), z(t)). Fig. 1.2 shows a parametric three
dimensional plot. We have also plotted the time domain waveform x(t) in Fig. 1.3. The waveform
1.1 An Introduction to Chaos
3
is not visually appealing as Figs.1.1 and 1.2. For instance, the elegance of the phase plots is absent
in the time domain waveform.
The structure that we see in Fig. 1.2 is called a chaotic strange attractor (or attractor)1 . Using
computer simulations, Lorenz identified the presence of sensitive dependence on initial conditions,
aperiodicity and bounded trajectories, the hallmarks of chaos. Just like Lorenz, we also obtained
the solution using a numerical simulation. The exception might be that our computer probably does
not have 16KB of memory.
45
40
35
30
z
25
20
15
10
5
−20
−10
0
10
x
20
25
20
15
10
5
0
−5
−10
−15
y
Fig. 1.2: The Lorenz Butterfly as plotted in three dimensional phase space.
Comparing this picture to a true three dimensional object such as a sphere, you can
see that there is no ”inside” and ”outside” to the Lorenz Butterfly. This in turn
implies that the Lorenz Butterfly has a fractional dimension. In other words, the
Lorenz Butterfly is a fractal.
It turns out that we cannot determine an explicit chaotic solution (x(t), y(t), z(t)) for the Lorenz
system in Eqs.(1.1), (1.2), (1.3). This lack of an explicit chaotic solution lead to a natural question:
was the strange attractor an artifact of computer round-off errors? Although other chaotic sytems
1 There exist nonchaotic strange attractors and chaotic nonstrange attractors. We will primarily
discuss chaotic strange attractors in this book.
−20
−25
4
1 Introduction
20
15
10
x
5
0
−5
−10
−15
−20
0
5
10
t (seconds)
Fig. 1.3: x(t) time domain waveform for the Lorenz butterfly. We have plotted only
one waveform for clarity. Although the waveform looks periodic, a fast Fourier
transform will clearly show that there is no underlying period.
were proposed in the 1970s and early 1980s, they were also studied through computer simulations. Hence the question of the strange attractor being an artifact of computer simulation was still
unanswered and there was a need to demonstrate that chaos is a robust physical phenomenon.
Electronic circuits were a natural choice for realizing the Lorenz system because electronic
components such as operational amplifiers were becoming ubiquitous in the early 1970s. However
the difficulty in realizing Lorenz and other similar systems via electronic circuits was the fact
that the equations describing the chaotic system involved multiplying two functions. The analog
multiplier was not a reliable electronic component in the 1970s and early 1980s.
This unreliablity of the analog multiplier spurred the invention of the first electronic chaotic
circuit in 1983, almost 20 years after Lorenz’s paper. Leon O. Chua, a professor at the University
of California, Berkeley designed the first electronic chaotic circuit, Chua’s circuit [13]. The circuit
and oscilloscope pictures are shown in Fig. 1.4 and Fig. 1.5 respectively [2].
By rescaling the circuit variables vC1 , vC2 and iL from Fig. 1.4, we obtain the dimensionless2
Chua Equations shown in Eqs.(1.4), (1.5) and (1.6). α , m1 , m0 , β ∈ R are parameters of the system.
2
Dimensionless formulation will be covered in Sec. 4.2.4.
15
1.1 An Introduction to Chaos
5
Fig. 1.4: Chua’s circuit, the nonlinear resistor is realized using two operational
amplifiers.
Fig. 1.5: Phase plot recorded on an oscilloscope from experimental measurements
of Fig. 1.4. The inductor was realized using an op-amp operating as a gyrator [3].
6
1 Introduction
x˙ = α [y − x − m1 x −
1
(m0 − m1 ) (|x + 1| − |x − 1|)
2
y˙ = x − y + z
(1.4)
(1.5)
z˙ = −β y
(1.6)
Notice that the circuit in Fig. 1.4 is not an analog computer. That is, we do not have analog
integrators for solving the system of equations in (1.4), (1.5) and (1.6). Chua was able to construct
the circuit in Fig. 1.4 without analog integrators because he systematically derived the circuit for
producing chaos from basic concepts in nonlinear circuit theory. This approach was also instrumental in mathematically proving the existence of chaos [2] in Chua’s circuit. Thus Chua’s circuit
was the first system in which the existence of chaos was confirmed numerically via simulation,
experimentally via electronics and rigorously via Shilnikov’s theorem by 1984. Between the announcement of the circuit in late 1983 and the rigorous proof of chaos by 1984, the time span was
approximately one year. In comparison, Lorenz’s system was rigorously proved to be chaotic only
in 1999 by Warwick Tucker, a span of 36 years since Lorenz’s paper in 1963! Chua’s approach
illustrates the paradigm of using electronics to study chaos - we have at our disposal a physical interpretation of chaos. This physical interpretation of chaos is the motivation behind using FPGAs
to study the phenomenon.
Since Chua’s work, many other chaotic circuits have been proposed. A family of such circuits
involve jerky dynamics and were proposed by Julien Clinton Sprott from the University of Wisconsin, Madison [19]. One possible chaotic circuit based on jerky dynamics is shown in Fig. 1.6.
An oscilloscope phase plot is shown in Fig. 1.7. Notice that unlike Chua’s circuit, Fig. 1.6 is a
circuit based on analog integrators. These circuits are easy to build and analyze analytically. We
will realize the system equations on FPGAs later in the book.
...
x = J(x, x,
˙ x)
¨
(1.7)
Eq.(1.7) shows the general system equation for Sprott’s jerky dynamical systems. They are so
named because if x(t) is considered to be position then Eq.(1.7) implies that x¨ is the acceleration.
But Eq.(1.7) involves the derivative of acceleration or the jerk. Jerky dynamics is very useful in
rocket science, although we unfortunately will not be building rockets in this book.
After Sprott, a variety of other chaotic circuits (hysteresis based chaos generators, chaos from
synchronized oscillators etc.) have been developed. We will leave the history of chaos with Sprott
and turn our attention to one application of chaos that will be discussed later in the book - synchronization.
1.1.2 An Application of Chaos
One very interesting application of chaos is synchronization for secure communication : a transmitter and receiver chaotic system can synchronize with each other. But if we use the chaotic signal
as a much larger masking signal, then we can transmit a message using the chaotic mask. The concept of synchronization in chaotic systems was originally proposed by Pecora and Carroll [15]. An
application to secure communication was suggested by Cuomo and Oppenheim [10].
The key to this concept is that if a chaotic system (say the Lorenz system) can be decomposed
into subsystems, a drive subsystem and a stable response subsystem, then the original message can
be recovered at the receiver using only the transmitted signal. Consider again the Lorenz system of
equations.
1.1 An Introduction to Chaos
7
Fig. 1.6: A chaotic circuit realizing jerky dynamics. This circuit was implemented
by former MSOE students Chris Feilbach and Clara Backes.
Fig. 1.7: Phase plot from an oscilloscope screenshot for the circuit in Fig. 1.6. x¨ is
on the y-axis, x is plotted on the x-axis.
8
1 Introduction
x˙ = −σ x + σ y
y˙ = −xz + ρ x − y
z˙ = xy − β z
(1.8)
(1.9)
(1.10)
Pecora and Carroll [15] showed that Eqs.(1.8) through (1.10) can be decomposed into two
stable response subsystems.
x˙1 = −σ x1 + σ y
(1.11)
y˙2 = −xz2 + ρ x − y2
(1.13)
z˙1 = x1 y − β z1
z˙2 = xy2 − β z2
(1.12)
(1.14)
Eqs.(1.8) through (1.10) can be interpreted as the drive system since its dynamics are independent of the response subsystems. Nevertheless, the two response subsystems (Eqs.(1.11) through
(1.14)) can be used together to regenerate the full-dimensional dynamics which are evolving at the
drive system [10]. Specifically, if the input signal to the (y2 , z2 ) subsystem is x(t), then the output
y2 (t) can be used to drive the (x1 , z1 ) subsystem and subsequently generate a ”new” x(t) in addition
to having obtained, through synchronization, y(t) and z(t).
We will study such synchronization mechanisms in delay differential equations in Chapter 5.
1.2 An Introduction to Field Programmable Gate Arrays
We will now take a digression from science and give a brief overview of a very flexible integrated
circuit - the FPGA.
1.2.1 History of FPGAs
The FPGA industry originated from the programmable read-only memory and programmable logic
devices industry of the 1970s. Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first commercially viable field programmable gate array in 1985 [6] - the XC20643 .
Freeman and Vonderschmitt were both working as chip engineers at Zilog Corp. prior to joining
Xilinx. While working at Zilog, Freeman wanted to design a computer chip that effectively acted
as a blank tape, allowing the user to program the chip ”in hardware” rather than having to purchase
a preprogrammed chip (or ASIC - Application Specific Integrated Circuit) from the manufacturer.
Freeman approached his superiors at Zilog and suggested that such a programmable chip would be
a viable new avenue for the company. Nevertheless, he was unable to convince executives at Exxon
(Zilog’s parent company) to chase a totally unexplored market. As a result, Freeman left his post
at Zilog and along with Vonderschmitt founded Xilinx.
Xilinx’s FPGA was based on the company’s patented Logic Cell Array technology. The company’s system basically consisted of an off-the-shelf programmable chip and a software package
that could be used to program and tailor the chip for specific needs. The technology was based
on the arrangement of gates (the lowest level building block in a logic circuit) in complex forma3
Although Xilinx’s competitor, Altera, was founded in 1983.
1.2 An Introduction to Field Programmable Gate Arrays
9
tions called arrays; as the number of gates increased, the more complex were the functions that the
semiconductor could perform. Fig. 1.8 shows a very simple FPGA Logic Element or LE.
Fig. 1.8: The basic processing unit on an Altera FPGA, the Logic Element (LE).
Screenshot has been obtained using Altera’s Chip Planner tool in Quartus 12.0.
In this book, we will utilize FPGAs from Altera (and a development board from Terasic Inc.).
Altera’s history is as interesting as Xilinx. We will not discuss their history more except to note
that the name ”Altera” is from ”alterable” [5].
1.2.2 Why FPGAs?
Unlike processors, FPGAs use dedicated hardware for processing logic and hence are not constrained by the complexities of additional overhead, such as an operating system. In the early days
of FPGAs, they were usually constrained by high power requirements. Nevertheless with the latest FPGA families (such as Stratix from Altera) emphasizing low dynamic power performance,
FPGAs are being increasingly used for digital signal processing (DSP) applications [14].
Another interesting benefit of FPGA technology is that since it is truly a ”hard” implementation
of our design specification, FPGAs provide more reliability unlike software tools running in a
programming environment. This is because processor-based systems often involve several layers
of abstraction to help schedule tasks and share resources among multiple processes. All these
complexities are unnecessary in an FPGA based system.
From the standpoint of differential equations, one can recast a fixed step algorithm (such as
Euler’s method) in a simple block diagram form suitable for realization on an FPGA, refer to
Fig. 1.9.
However, before we can realize differential equations on FPGAs we need to learn some basic
mathematical concepts. That is the subject of the next section.
10
1 Introduction
reset
reset
reset
reset
xNNew
f(x(t), x(t − Ni ))
X
+
D
Q
xN
∆t
Global
clock
reset
reset
Global clock
Shift Register
x(t − Ni )
Clock
Divider
fEuler =
1
δt
Fig. 1.9: The block diagram that we will eventually implement in this book for
solving the nonlinear delay differential equation (DDE): x˙ = f(t, x(t), x(t − τi )) [4].
The blocks in yellow will be implemented in MATLAB using the DSP Builder
Advanced Blockset from Altera.
1.3 Some Basic Mathematical Concepts
We will start with the very basic concept of what is a linear system (and what is not). This will
eventually help us understand what kind of systems give rise to chaotic behaviour.
1.3.1 Linear Versus Nonlinear Equations
Consider Eqs.(1.15), (1.16), a system of linear equations:
x − 3y = 3
2x − 6y = 6
(1.15)
(1.16)
What are the solutions to Eqs.(1.15), (1.16)? To answer this question notice that Eq.(1.16) can be
simplified to x − 3y = 3. Thus we have only one equation in two unknowns, shown below.
y=
x
−1
3
(1.17)
Hence if we let x ∈ R, there are infinitely many real number solutions in the form (x, y). In other
words, we have two superimposed straight lines in our solution space. The MATLAB code in
listing B.2 plots one of the equations, the result is Fig. 1.10.
The beauty of linear equations is that we can have only two other kinds of solutions to a system
of linear equations: a unique solution or no solution. The detailed study of linear systems and their
application is the subject of linear algebra [21]. We will introduce concepts from linear algebra,
when required in this book.
Unlike linear equations, one cannot state beforehand (or a priori) how many solutions a non2
linear equation can have in general. Take the case
√ of a simple quadratic equation: y = x − 2. If
x ∈ R then the equation has two solutions: x = ± 2. The situation changes drastically if we have
non-polynomial functions involved.
1.3 Some Basic Mathematical Concepts
11
1
0.5
0
y
−0.5
−1
−1.5
−2
−2.5
−3
−5
−4
−3
−2
−1
0
x
1
2
3
4
5
Fig. 1.10: The function y = 3x − 1 as plotted in MATLAB.
However we can understand the difference between linearity and nonlinearity using the concept
of a system4 . Loosely speaking a system ”acts” on a function. For example consider the volume
knob on your car stereo. This volume knob adjusts the gain of your audio amplifier. In other words
the audio amplifier multiplies your input signal by a factor proportional to how much you turn the
volume knob. Mathematically, the audio amplifier transforms an input function into another output
function. Hence we have our first definition [8].
Definition 1.1. A system is a function whose domain and range are sets of signals called signal
spaces.
For example, let us say the audio amplifier has a gain K ∈ R that can be controlled by the volume
knob. Then we can say that the audio amplifier is a system S such that:
y = S(x)
(1.18)
x and y are functions in the function space of continuous-time systems: x, y : t → R. Thus the output
of the system at any time t is given by:
y(t) = S(x)(t)
= Kx(t)
4
(1.19)
(1.20)
Note that we are not talking about a system of equations. This difference should become clear
after we provide a mathematical definition of a system.
12
1 Introduction
Thus if the gain K is positive, then we hear loud (sometimes obnoxiously loud) music.
We need to emphasize that we should not write the mathematical description of the system as
S(x(t)). This is because a system’s domain is a function. x(t) is a number, not a function.
Now that we know the definition of a system, a linear system is defined below [8].
Definition 1.2. A system S is said to be linear iff: ∀u, v ∈ D, ∀α , β ∈ R, S(α u + β v) = α S(u) +
β S(v)
In Definition 1.2, set D is the domain of S. In other words, Definition 1.2 is the superposition
theorem: ”response of the sum is the sum of the responses”. Let us understand the definition via
examples.
Example 1.1. Consider the audio amplifier system: y(t) = S(x)(t) = Kx(t). Is this system
linear or nonlinear?
Solution: Applying Definition 1.2 to the audio amplifier system, we have:
S(α u + β v) = K(α u + β v)
(1.21)
= Kα u + Kβ v
(1.22)
= α Ku + β Kv
(1.23)
= α S(u) + β S(v)
(1.24)
Thus our audio amplifier system is linear.
Note that in reality you cannot expect to get infinite gain out of your audio amplifier. That is,
physically the audio amplifier is going to eventually saturate as you turn the volume knob. However
the linearity model is an excellent approximation when the audio amplifier does not saturate and
we listen to music in the linearity range of the audio amplifier.
Example 1.2. Consider a system that squares the input function: y(t) = S(x)(t) = x2 (t). Is
this system linear or nonlinear?
Solution: Applying Definition 1.2 to the square system, we have:
S(α u + β v)(t) = (α u + β v)2 (t)
= α 2 u2 (t) + β 2 v2 (t) + 2αβ u(t)v(t)
(1.25)
(1.26)
However,
S(α u + β v)(t) 6= α u2 (t) + β v2 (t)
= α S(u)(t) + β S(v)(t)
Thus our square system is nonlinear.
(1.27)
(1.28)
1.3 Some Basic Mathematical Concepts
13
1.3.2 Linear Versus Nonlinear Dynamics
The systems (scaling and squaring) we studied in Sec. 1.3.1 are examples of non dynamical systems. On the other hand, a dynamical system is governed by differential equations, and such systems are the topic of study in this book. We will be concerned with nth order ordinary nonlinear
differential equations (ODE), autonomous or non-autonomous, with or without delay.
Definition 1.3. The order of a differential equation is the order of the highest derivative in the
equation.
Example 1.3. What is the order of the differential equation: (x)
¨ 3 + sin(x) = 0?
Solution: Since the highest derivative appearing in the equation is the 2nd derivative, the
order of the differential equation is two.
Definition 1.4. A differential equation involving ordinary (non-partial) derivatives is an ODE
Definition 1.5. An autonomous ODE does not involve an explicit function of time.
Example 1.4. Is Eq.(1.29) below an autonomous ODE?
x¨ + x˙ + x = cos(t)
(1.29)
Solution: Eq.(1.29) involves only ordinary derivatives and hence is an ODE. But it does
not involve an explicit function of time so the equation is non-autonomous. In this book, we
will use the following change of variables to convert non-autonomous ODEs to autonomous
ODEs.
x1 = x
(1.30)
x2 = x˙
(1.31)
x3 = t
(1.32)
Using Eqs.(1.29), (1.30),(1.31) and (1.32), we get:
x˙1 = x2
(1.33)
x˙2 = −x1 − x2 + cos(x3 )
(1.34)
x˙3 = 1
(1.35)
The advantage of this change of variables is that it allows us to visualize a phase plot with
trajectories ”frozen” in it.
Linearity or nonlinearity of differential equations can be determined using superposition from
Definition 1.2, as the following example illustrates.
14
1 Introduction
Example 1.5. Consider the jerky dynamical system below.
x˙ = y
(1.36)
y˙ = z
(1.37)
z˙ = −x − y − sign(1 + 4y)
(1.38)
Prove the system above is nonlinear. sign is the signum function defined below.

 −1 when x < 0,
sign(x) = 0 when x = 0,

1 when x > 0
(1.39)
Proof. First, we will write the system above as one third order differential equation in x. To
...
...
do so, notice that Eq.(1.37) and Eq.(1.36) imply z˙ = y¨ = x . Thus substituting x for z˙ and x˙
for y in Eq.(1.38), we get:
...
x + x˙ + sign(1 + 4x)
˙ +x = 0
(1.40)
Suppose there exist three solutions to Eq.(1.40): x1 , x2 , x3 . That is:
...
x1 + x˙1 + sign(1 + 4x˙1 ) + x1 = 0
...
x2 + x˙2 + sign(1 + 4x˙2 ) + x2 = 0
...
x3 + x˙3 + sign(1 + 4x˙3 ) + x3 = 0
(1.41)
(1.42)
(1.43)
We will apply Definition 1.2 and check if a superposition of the solutions: α x1 + β x2 + δ x3 ,
α , β , δ ∈ R is also a solution. That is:
d3
d
(α x1 + β x2 + δ x3 ) + (α x1 + β x2 + δ x3 )+
dt 3
dt
d
?
sign 1 + 4 (α x1 + β x2 + δ x3 ) + (α x1 + β x2 + δ x3 ) = 0
dt
(1.44)
Simplifying the left-hand-side (LHS) of Eq.(1.44), we get:
...
...
...
LHS = α (x1 + x¨1 + x1 ) + β (x2 + x¨2 + x2 ) + δ (x3 + x¨3 + x3 )+
sign (1 + 4(α x˙1 ) + 4(β x˙2 ) + 4(δ x˙3 ))
(1.45)
sign(1 + 4α x˙1 ) + sign(1 + 4β x˙2 ) + sign(1 + 4δ x˙3 )
(1.46)
Note that if:
sign (1 + 4(α x˙1 ) + 4(β x˙2 ) + 4(δ x˙3 )) =
then Eq.(1.44) is zero by virtue of Eqs.(1.41), (1.42) and (1.43). However, the signum function is nonlinear. Eq.(1.39) shows that signum returns the sign of the input number x: −1 if
x is negative, 0 if x is zero and 1 if x is positive. Sketch the signum function or use a few
counter-examples to convince yourself that signum is nonlinear. Thus, Eq.(1.44) may not be
zero. Hence Definition 1.2 is not satisfied and this implies that our system is nonlinear. ⊓
⊔
The point to be noted from this example is that a rigorous proof of nonlinearity may involve
a bit of work. But a quick glance at Eqs.(1.36) through (1.38) reveals the signum function is the
1.3 Some Basic Mathematical Concepts
15
reason our system in nonlinear. In other words, if the RHS of our system of first-order ODEs has a
nonlinear function, our system is nonlinear.
There is an interesting subset of linear systems that have the same behaviour independent of
time shifts : linear time-invariant systems.
Definition 1.6. A system S is said to be linear time-invariant (or LTI) iff (S ◦ D)(x) = (D ◦ S)(x)
Definition 1.7 defines a time shift using a delay system.
Definition 1.7. Dτ (x)(t) = x(t − τ )
Now that we have studied the differences between linear and nonlinear systems, a logical next
step would be to try and find an explicit solution to the system under question. We already know
that this may not be possible, case in point being an explicit chaotic solution to the Lorenz system
does not exist. However, for some differential equations, it may be possible to find an explicit
solution.
Example 1.6. Consider the DDE in Eq.(1.47)
x˙ = D1 (x)(t) History(t) = 1,t ≤ 0.
(1.47)
Find x(t) for t ≥ 0.
Solution: In order to solve the DDE, we will solve the differential equation over mutually
exclusive intervals as shown below.
For 0 ≤ t < 1, the DDE can be written as:
x˙ = 1
(1.48)
Eq.(1.48) is valid since D1 (x)(t) = History(t) if 0 ≤ t < 1. Notice also that Eq.(1.48) justifies our choice of the label ”History”. We have an infinite set of initial conditions in the
form of a ”History” function. Solving Eq.(1.48),
x(t) = t + c0 , 0 ≤ t < 1
(1.49)
Now, c0 in Eq.(1.49) can be determined because we have defined the value of the history
function at t = 0: x(0) = History(0) = 1. Hence the solution to our DDE in the interval
0 ≤ t < 1 is:
x(t) = t + 1, 0 ≤ t < 1
(1.50)
Proceeding in this manner, we see that the solution to our differential equation are polynomials of increasing order:

0 ≤ t < 1,
t +1
2
x(t) = t2 + t + c1 1 ≤ t < 2,
(1.51)

···
···
In order to find c1 in Eq.(1.51), we will impose continuity constraints:
t + 1|t=1 =
t2
+ t + c1 |t=1
2
(1.52)
Thus c1 = 12 .
Now, contrast the solution to our DDE with the solution that corresponds to a differential
equation with no delay: x˙ = x. The solution to the differential equation with no delay is the
exponential function. Quite a contrast to the solution in this example!
16
1 Introduction
The example above shows that we need an infinite set of initial conditions to properly solve a
DDE. Thus even first order DDEs are infinite-dimensional and can exhibit chaos (and hyperchaos
etc.). In Chapter 5, we will simplement chaotic DDEs.
However most physical systems cannot be solved explicitly. But, interestingly, we can predict
the behavior of most physical systems without solving for an explicit closed form solution. An
introduction to this approach is the topic of Sec. 1.3.3.
1.3.3 Fixed (Equilibrium) Points
Consider the differential equation in Eq.(1.53), written explicitly using time t:
dx
= cos(x(t))
dt
(1.53)
Physically, points of interest are x† for which the derivative dx
dt † = 0. In other words, the system
x
does not ”move” from x† . Such points are called fixed points or equilibrium points.
We can extend the above description to nth order differential equations by rewriting an nth
order differential equation as n first-order differential equations. In other words, our definition of
equilibrium will involve a system of n first-order differential equations as shown below.
Definition 1.8. A system of differential equations x˙ = f(x) has equilibrium point(s) x† such x˙ † =
x
n
0. Here, x ∈ R
Hence given a system of differential equations, we need to solve a set of nonlinear equations for
finding the equilibrium points. Let us look at a couple of examples, starting with Eq.(1.53).
Example 1.7. Determine the equilibrium points for the system in Eq.(1.54).
x˙ = cos(x)
Solution: Applying Definition 1.8, we get:
x˙ † = 0
x
(1.54)
(1.55)
Thus:
cos(x† ) = 0
(1.56)
Hence the equilibrium points are the zeroes of the cosine function:
π
x† = (2k + 1) , k ∈ Z
2
(1.57)
Example 1.8. Determine the equilibrium points for the Lorenz system with the specific
value of parameters shown below.
1.3 Some Basic Mathematical Concepts
17
x˙ = −10x + 10y
y˙ = −xz + 28x − y
8
z˙ = xy − z
3
(1.58)
(1.59)
(1.60)
Solution: Applying Definition 1.8, we get:
−10x† + 10y† = 0
(1.61)
−x z + 28x − y = 0
8
x† y† − z† = 0
3
(1.62)
x † = y†
(1.64)
† †
†
†
(1.63)
Eq.(1.61) implies
Replacing x† with y† in Eqs.(1.62) and (1.63) and solving, we get y† and z† . Hence our
equilibrium points are:
√
√
√ √
(1.65)
(x† , y† , z† ) = (0, 0, 0), (6 2, 6 2, 27), (−6 2, −6 2, 27)
1.3.4 System Behaviour Near Fixed Points
Revisiting the Lorenz system from Sec. 1.3.3, if (x(0), y(0), z(0)) = (x† , y† , z† ) then ((x(t →
∞), y(t → ∞), z(t → ∞)) = (x† , y† , z† ). That is if our initial conditions are exactly equilibrium points,
we will continue to stay at the equilibrium point, courtesy of Definition 1.8.
However, physically speaking, there is always some inherent noise present in our initial conditions. So a practical question is: what happens when we start our system ”near” (or close to) a
fixed point? The answer to the question is given by the stability theory of dynamic systems, a topic
that is beyond the scope of this volume. The short answer is: if the equilibrium point is stable,
our system trajectories will move back towards the equilibrium point. If the equilibrium point is
unstable, the system trajectories will move away from the equilibrium point. The unstable case is
the interesting one since it may lead to the chaotic trajectories in phase space.
But we can determine what happens to the system behavior near the equilibrium point via
numerical simulation using MATLAB. Let us start with the Lorenz system.
Example 1.9. Simulate the Lorenz system starting with the initial conditions
(x(0), y(0), z(0)) = (8.5, 8.7, 3.0). Plot a two dimensional phase plot (x(t), z(t)).
Solution: We have already simulated the Lorenz system in the introduction section. For
this question, we are just going to change the initial condition. We leave it to you as an
exercise to generate Fig. 1.11.
If you recall our Lorenz example from the introduction section, the initial conditions were (x(0), y(0), z(0)) = (10, 20, 30). In this example, we start quite a distance away
(10, 20, 30). Yet our system still manages to get into a chaotic state. In other words, the
Lorenz attractor is robust. Refer to Problem 1.11 for quantifying “robustness”.
18
1 Introduction
50
45
40
35
z
30
25
20
15
10
5
0
−20
−15
−10
−5
0
x
5
10
15
Fig. 1.11: We obtain the Lorenz butterfly with a different initial condition.
For two dimensional systems, you can of course write a MATLAB program for simulating the
system. However, a very nice tool is pplane75 , available from Rice University [17]. Download
pplane7 from [17].
Next, start MATLAB and navigate to the directory where you downloaded type pplane7. Type
pplane7 at the prompt and press enter. The window in Fig. 1.12 should appear.
Choose the vibrating spring as the system to simulate: Gallery → vibrating spring. Leave the
default parameter value for d as 0 and left-click ”Proceed”. The window in Fig. 1.13 should appear.
In addition to the phase plot, pplane plots the vector field of two dimensional systems. As
the name implies, a vector field associates a vector to every point in phase space. How do we
know the direction of the vector? The answer is we can obtain the direction of the vector from the
differential equation. Consider the following system of two dimensional nonlinear ODEs. These
are representative of systems in pplane.
5
An alternative to pplane is the MATLAB command quiver. We will explore the use of quiver in
the lab component of this chapter. Nevertheless, pplane is excellent MATLAB code and is opensource. One is encouraged to explore coding styles used in pplane7.
20
1.3 Some Basic Mathematical Concepts
Fig. 1.12: pplane7 startup.
Fig. 1.13: pplane7 vector field for a simple mass-spring system (no damping).
19
20
1 Introduction
x˙ = f1 (x, y)
(1.66)
y˙ = f2 (x, y)
(1.67)
The slope of the solution trajectory at any point in the plane is given by:
dy
=
dx
dy
dt
dx
dt
=
f2 (x, y)
f1 (x, y)
(1.68)
In other words, the vector field is described by a tangent to the solution trajectory. Fig. 1.14 show
a few solution trajectories in pplane. To obtain these trajectories, left-click anywhere in the vector
field. Refering to Fig. 1.14, we see that y(t) is v(t) or velocity. Thus to obtain an analytic expression
Fig. 1.14: Some typical mass-spring system trajectories, no damping. Notice the
system oscillates forever. This system is an ideal case in the sense that most
practical (except superconducting) physical systems will have some damping.
of the vibrating spring vector field, we use Eq.(1.68).
−kx
dv
−3x
dy
=
= m =
dx
dx
v
v
(1.69)
A mechanical schematic of our system is shown in Fig. 1.15. We have a system that is governed
by Newton’s law and Hooke’s law.
mx¨ = −kx
(1.70)
1.4 Conclusions
21
Fig. 1.15: A mass spring system with the positive direction of displacement
labelled.
In our case, m = 1 kg and k = 3 Nm . Using Fig. 1.15 as the physical model for Fig. 1.14, we can
further understand the vector field. If we give an initial position and velocity to the mass, then the
system oscillates forever since there is no damping. Eq.(1.70) is also called the simple harmonic
oscillator.
1.4 Conclusions
Below is a summary of how we could apply the concepts and techniques from this chapter.
1. Given a system of differential equations, determine if they are linear or nonlinear.
2. Compute the equilibrium points6 of the system using Definition 1.8.
3. Numerically simulate the system using MATLAB and display phase plots. Start with initial
conditions near the equilibrium points.
4. The phase plot will qualitatively describe system behavior. Use the phase plot as a starting point
for rigorous analysis.
6 If the system has no equilibrium points, you need to rely on intuition to select initial conditions.
As a specific example, refer to problem 1.8 in the exercises.
22
1 Introduction
The beauty of the equilibrium point method lies in the fact that we do not find an explicit
analytic solution. Rather, we determine any equilibrium points and determine system behavior by
starting close to those equilibrium points. An example application of the equilibrium point method
was the Lorenz system. We first found the equilibrium point(s). Then, using MATLAB, we found
that starting close to one of the equilibrium points the solution will move into a strange attractor.
Looking at the differential equation for the Lorenz system, it is not obvious at all that the solution
could be chaotic.
In the next chapter, we will discuss the engineering part of the book - the FPGA.
1.4 Conclusions
23
Problems
Note that an excellent book on problem solving is ”How to Solve It” by Polya [16]. You should
obtain a copy of this book and read it thoroughly, it is time well spent!
1.1. Google Scholar http://scholar.google.com is a great tool to find research papers.
Using Google Scholar, find Lorenz’s original paper from 1963 [11]. Lorenz’s paper is very well
written, read the paper and determine the physical meaning of the variables x, y and z in Eqs.(1.1),
(1.2) and (1.3). Note that Google Scholar is not yet universally accepted as a scientific database.
Hence the reader should be familiar with other tools such as Web of Science and Scopus.
1.2. Consider three dimensional space R3 . Draw all possibilities for a linear system of three equations (in three unknowns x, y, z) such that the system has no solution, unique solution and infinitely
many solutions.
1.3. Consider the amplifier system and the system that squares the input function.
y1 (t) = S(x)(t) = Kx(t)
2
y2 (t) = S(x)(t) = x (t)
(1.71)
(1.72)
What is the output of the amplifier if the input is x(t) = sin(ω t)? What is the frequency of the
output? Now, what is the output frequency of the square system when the input is x(t) = sin(ω t)?
Based on the results of this problem, what can you conclude about the output of a nonlinear system to a sinusoidal input of a specific frequency? Can your conclusion be extended to nonlinear
dynamical systems?
1.4. Recall the Sprott system from the text with the signum nonlinearity. We wrote the three firstorder differential equations as one third order differential equation. Can we, in general, write any n
first-order differential equations as one nth order differential equation? Prove your answer or give
a counter-example. HINT: Before you look for a proof, try to write the Lorenz system as one third
order differential equation.
1.5. Analogous to the Prob. 1.4, can we write any nth order differential equation as n first-order
differential equations of the form x˙ = f(x)? Prove your answer or give a counter-example.
1.6. Consider the simple harmonic oscillator from the text:
mx¨ + kx = 0
(1.73)
Can you realize this system physically (on a breadboard, for instance)?
1.7. For each of the following system, determine equilibrium points analytically. Simulate each
system near the equilibrium point to determine dynamics. For two dimensional systems, use
pplane.
1. Van Der Pol oscillator
x3
x˙ = µ x − − y
3
x
y˙ =
µ
(1.74)
(1.75)
µ ∈ R, µ 6= 0 is a parameter indicating the strength of nonlinear damping. Use µ = 1.5 for
simulation. What do you observe for µ << 1?
24
1 Introduction
2. R¨ossler System
x˙ = −y − z
(1.76)
y˙ = x + α y
(1.77)
z˙ = β + z(x − γ )
(1.78)
α , β , γ ∈ R are parameters of the system. Use α = 0.1, β = 0.1, γ = 14 for simulation.
3. Sprott System
x˙ = −2y
(1.79)
y˙ = x + z2
(1.80)
z˙ = 1 + y − 2z
(1.81)
4. Chua System
x˙ = α [y − x − m1 x −
1
(m0 − m1 ) (|x + 1| − |x − 1|)]
2
(1.82)
y˙ = x − y + z
(1.83)
z˙ = −β y
(1.84)
m0 , m1 , α , β ∈ R are parameters of the system. Use m0 =
for simulation.
−8
7 , m1
=
−5
7 ,α
= 15.6, β = 25.58
1.8. What are the fixed points for the system below?
x˙ = y
(1.85)
y˙ = −x + yz
(1.86)
z˙ = 1 − y
(1.87)
2
Construct a three dimensional phase plot in MATLAB.
1.9. What is the phase plot for the one dimensional nonlinear differential equation:
x˙ = sin(x)
(1.88)
1.10. In the text, we considered three dimensional systems. Now consider the following four dimensional system proposed by R¨ossler [18].
x˙ = −y − z
y˙ = x + α y + w
(1.89)
(1.90)
z˙ = β + xz
(1.91)
w˙ = −γ z + δ w
(1.92)
α , β , γ , δ ∈ R are parameters. What are the equilibrium points for this system? Simulate the system
in MATLAB, try to pick values for α , β , γ , δ for chaos. Contrast the behavior of this system with
the R¨ossler system in Eqs.(1.76), (1.77) and (1.78). The system above is the first example of a
hyperchaotic system.
1.11. In the text, we discussed “robustness” of the Lorenz attractor. A mathematical approach to
quantifying “robustness” is to compute the divergence of a vector field f defined by the the RHS of
the Lorenz system:
△
f = (−σ x + σ y)xˆ + (−xz + ρ x − y)yˆ + (xy − β z)ˆz
(1.93)
References
25
x,
ˆ yˆ and zˆ are the unit vectors in the x, y and z directions respectively. Compute ∇ · f. What can you
conclude?
Lab 1 : Introduction to MATLAB and Simulink
Objective: To compute equilibrium points and numerically investigate behaviour of dynamical
systems.
Theory: Refer to the Appendix for a tutorial on MATLAB and Simulink.
Lab Exercises:
1. After working through the Appendix, simulate all systems from exercise 1.7.
2. Consider the Lotka-Volterra system in Eq.(1.94).
x˙ = x(α − β y)
y˙ = −y(γ − δ x)
(1.94)
a. Determine the equilibrium points of this system.
b. Using pplane, determine all possible qualitatively different phase portraits for this system,
as α , β , γ , δ are changed. Note that the Lotka-Volterra system is available in pplane.
3. pplane7 can be used to plot two dimensional phase plots. MATLAB has an equivalent command
called quiver. Moreover, in order to plot vector fields for three dimensional systems, investigate
the MATLAB command quiver3. Use quiver or quiver3 to plot vector fields for all systems in
Exercise 1.7.
References
1. Alligood, K. T., Sauer, T. D. and Yorke, J. A. (1996) Chaos : An Introduction to Dynamical
Systems. Springer-Verlag, New York
2. Chua, L. O. (2011) Chua’s Circuit. In: Scholarpedia, Available via DIALOG.
http://www.scholarpedia.org/article/Chua_circuit Cited 25 December
2012
3. Muthuswamy, B. et. al. (2009) A Synthetic Inductor Implemenation of Chua’s Circuit. In:
University of California, Berkeley, EECS Technical Reports, Available via DIALOG.
http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-20.
html Cited 22 November 2014
4. Cornell University Digital Differential Analyzer. In : ECE5760 Homepage, Available via
DIALOG.
http://people.ece.cornell.edu/land/courses/ece5760/DDA/index.
htm Cited 26 December 2012
5. A History of Altera. In : Funding Universe, Available via DIALOG.
http://www.fundinguniverse.com/company-histories/altera-corpo
ration-history/ Cited 26 December 2012
6. A History of Xilinx. In: Funding Universe, Available via DIALOG.
http://www.fundinguniverse.com/company-histories/xilinx-inc-h
istory/ Cited 26 December 2012
7. A simple FPGA logic cell. In : Wikipedia, Available via DIALOG.
http://en.wikipedia.org/wiki/File:FPGA_cell_example.png Cited 26
December 2012
26
1 Introduction
8. Lee, E. A. and Varaiya, P. P. (2011) Structure and Interpretation of Signals and Systems. 2nd
Edition, LeeVaraiya.org
9. Chen, G. and Ueta, T. (2002) Chaos in Circuits and Systems. World Scientific, Singapore
10. Cuomo, K. M. and Oppenheim A. V. (1993) Circuit Implementation of Synchronized Chaos
with Applications to Communications. Physical Review Letters (71):65-68
11. Lorenz, E. N. (1963) Deterministic Nonperiodic Flow. Journal of Atmospheric Sciences, 130–
141.
12. Makin, J. G. (2008) A Computational Model of Human Blood Clotting: Simulation, Analysis, Control and Validation. Tech. Rep. UCB/EECS-2008-165. Electrical Engineering and
Computer Sciences Department, University of California, Berkeley
13. Matsumoto, T. (1984) A Chaotic Attractor from Chua’s Circuit. IEEE Transactions on Circuits and Systems CAS-31(12):1055–1058
14. Top 5 benefits of FPGAs. In : National Instruments Whitepaper, Available via DIALOG.
http://www.ni.com/white-paper/6984/en Cited 26 December 2012
15. Pecora, L. M. and Carroll, T. L. (1990) Synchronization in Chaotic Systems. Physical Review
Letters 64:821–824
16. Polya, G. (1957) How to Solve It. Gardent City, NY
17. Polking, J. C (2011) pplane homepage. Available via DIALOG.
http://www.math.rice.edu/˜dfield/ Cited 25 December 2012.
18. R¨ossler, O. E. (1979) An Equation for Hyperchaos. Physics Letters A (71):155–157
19. Sprott, J.C. (2010) Elegant Chaos. Algebraically Simple Chaotic Flows. World Scientific,
Singapore
20. Steingrube, S., Timme M., Worgotter, F. and Manoonpong, P. (2010) Self-organized Adaptation of a Simple Neural Circuit Enables Complex Robot Behaviour. Nature Physics 6:224–
230.
21. Strang, G. (2009) Introduction to Linear Algebra. Wellesley-Cambridge Press, Massachusetts
22. Van der Pol, B. (1927) On relaxation-oscillations, The London, Edinburgh and Dublin Phil.
Mag. & J. of Sci., 2(7):978–992
23. Van der Pol, B. and Van der Mark, J. (1927) Frequency demultiplication, Nature, 120:363–
364
Chapter 2
Designing Hardware for FPGAs
FPGA realization of the Lorenz
butterfly
Abstract In this chapter we will cover many of the basic concepts behind FPGA design. We start
with an overview of our hardware platform, go through a quick introduction to the Quartus toolset
and then review combinational along with sequential logic. We will conclude with the all important
concept of timing closure. Although we cover a particular hardware platform, the material in this
chapter can be adopted to understand other FPGA hardware platforms. This chapter, along with
chapter 1, lay the groundwork for the rest of the book. Nevertheless, please understand that majority
of this chapter is meant primarily as a review. However, the conceptual material on abstracting the
FPGA development flow via Simulink should not be skipped.
2.1 The FPGA Development Flow
In order to design for an FPGA, one needs to intimately understand the design process shown
in Fig. 2.1 [1]. The first step in the process is design entry. In other words, you specify design
Fig. 2.1: A high-level view of FPGA design flow.
functionality (differential equations) using tools such as Hardware Description Languages (HDLs),
schematic entry or using a high level block diagram approach like Simulink. Next we compile the
design to identify any syntax errors and then simulate the design to verify functionality. If design
specifications are not met, we debug the design entry as necessary in order to meet functional
specifications. Once the functional specifications have been met, we should run a timing-intensive
27
28
2 Designing Hardware for FPGAs
simulation, but this topic is beyond the scope of this volume1 . Once we have confirmed that the
design is both functional and satisfies timing, we can download the bitstream onto the FPGA.
The first step in maximizing the capabilities of an FPGA is understanding the underlying architecture, the topic of Sec. 2.2.
2.2 The Architecture of an FPGA
Although the specifics of FPGA architecture vary between each device family (even within the
same manufacturer), an FPGA is simply a massively parallel lookup table. Fig. 2.2 shows a screen
shot from the Quartus chip planner of the FPGA that we will be using in this book, the Cyclone IV.
Note how the device architecture is very repetitive in terms of fundamental structure, i.e..,
the FPGA has a two dimensional row and column-based architecture to implement custom logic.
Figs. 2.3 and 2.4 show just how uniform this structure is.
Let us examine the LE in Fig. 2.4 in some detail [2], since a LE is the basic design unit on an
FPGA. Each LE features:
•
•
•
•
•
•
•
A four-input look-up table (LUT), which is a function generator that can implement any combinational logic function of four variables
A programmable register
A carry chain connection
A register chain connection
The ability to drive all types of interconnects : local, row, column, register chain and direct link
interconnects
Support for register packing
Support for register feedback
An LE can also operate in normal mode or arithmetic mode. Normal mode is suitable for general
logic applications and combinational functions. The arithmetic mode is ideal for implementing
adders, counters, accumulators and comparators. LEs in arithmetic mode can drive out registered
and unregistered versions of the LUT output. Register feedback and register packing are supported
when LEs are used in arithmetic mode.
In addition to LEs, Cyclone IV provide Phase Locked Loops (PLLs) for general-purpose clocking [2], as well as support for features such as clock multiplication (division) and phase shifting.
These PLLs are easily configurable via FPGA software tools, this feature will be discussed in the
book as necessary. Cyclone IVs also incorporate embedded memory consisting of columns of M9K
memory blocks [2]. Each M9K block can implement various types of memory, with our without
parity. The M9K blocks are also easy to configure via FPGA software.
We have covered a brief overview of FPGA architecture. Going back to Fig. 2.1, a natural
question is: how do we utilize software to realize a design onto an FPGA? The answer is: FPGA
manufacturers provide advanced software tools for FPGA hardware design. The toolset that Altera
provides is the Quartus suite. However since we are implementing differential equations, we will
primarily utilize MATLAB and Simulink. Nevertheless, we first need to choose the appropriate
development board.
1
We will however discuss the important concept of timing closure.
2.2 The Architecture of an FPGA
29
Fig. 2.2: A view of the Cyclone IV from the Chip planner in Quartus. The darker
blue indicates filled FPGA regions.
30
2 Designing Hardware for FPGAs
Fig. 2.3: A zoomed in view of the Logic Array Block (LAB) that highlight the 16
Logic Elements (LEs). LABs are the primary design features on the Cyclone
FPGA that are grouped into rows and columns across the device [2].
Fig. 2.4: LEs are the smallest units of logic in the Cyclone IV device architecture
[2].
2.3 An Overview of the Hardware and Software Development
Platform
In order to physically realize our differential equations, we will use the DE2-115 board2 [9] shown
in Fig. 2.5 from Terasic Technologies that utilizes a Cyclone IV (EP4CE115F29C7N) FPGA.
2
These are not the only possible development platforms that can be used to realize chaotic dynamics. Please utilize the companion website to obtain information on other development platforms
and software tools.
2.3 An Overview of the Hardware and Software Development Platform
31
Fig. 2.5: The DE2-115 board [9].
One also requires the Quartus toolset from Altera and the MATLAB (along with Simulink)
package from Mathworks Corporation. Please contact the respective companies for the appropriate licenses. Note also that you need miscellaneous hardware such as interface cables and oscilloscopes.
FPGA hardware and software platforms evolve rapidly. A decision had to be made on the particular choice of hardware and software. We first chose the DE2-115 because it offered a large
functionality-to-cost ratio for our research project(s) and, consequently, we chose the Quartus
toolset. This platform was also available at the time when the volume was first published. However,
the concepts covered in this volume should be applicable to any appropriate FPGA development
platform and toolset(s).
We will now go over the salient features of our development platform, starting with the DE2115 board.
2.3.1 An Overview of the Terasic DE2-115 Development Board
Since we have already discussed the FPGA in sec. 2.2, we will discuss board peripherals.
32
2 Designing Hardware for FPGAs
2.3.1.1 FPGA Clocks
Probably the most important component on the FPGA board is the crystal oscillator for the clock
circuitry [10]. The DE2-115 board includes one oscillator that produces 50 MHz clock signal. A
clock buffer is used to distribute 50 MHz clock signal with low jitter to the FPGA. The board also
includes two Subminiature Version A (SMA) connectors which can be used to connect an external
clock source to the board or to drive a clock signal out through the SMA connector. In addition,
all these clock inputs are connected to the PLL clock input pins of the FPGA to allow users to use
these clocks as a source clock for the PLL circuit [10].
Fig. 2.6: Block Diagram of Clock Distribution on the DE2-115 [10].
Since clocks are fundamental to FPGA functionality, pin assignments for clock inputs to FPGA
input/output (I/O) pins are listed in Table 2.1.
Table 2.1: Pin Assignments for Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
CLOCK 50
PIN Y2
50 MHz clock input
3.3V
CLOCK2 50
PIN AG14
50 MHz clock input
3.3V
CLOCK3 50
PIN AG15
50 MHz clock input
Depending on JP6
SMA CLKOUT PIN AE23 External (SMA) clock output Depending on JP6
SMA CLKIN
PIN AH14 External (SMA) clock input
3.3V
2.3.1.2 Switches and Light Emitting Diodes (LEDs)
The DE2-115 board provides four push-button switches as shown in Fig. 2.7 [10]. Each of these
switches is debounced using a Schmitt Trigger circuit, as indicated in Fig. 2.8 . The four outputs
called KEY0, KEY1, KEY2, and KEY3 of the Schmitt Trigger devices are connected directly to the
Cyclone IV E FPGA. Each push-button switch provides a high logic level when it is not pressed,
2.3 An Overview of the Hardware and Software Development Platform
33
and provides a low logic level when depressed. Since the push-button switches are debounced, they
are appropriate for using as clock or reset inputs in a circuit.
Fig. 2.7: Connections between the push-button and Cyclone IV FPGA [10].
There are also 18 slide switches on the DE2-115 board (See Fig. 2.9) [10]. These switches are
not debounced, and are assumed for use as level-sensitive data inputs to a circuit. Each switch is
connected directly to a pin on the Cyclone IV FPGA. When the switch is in the down position
(closest to the edge of the board), it provides a low logic level to the FPGA, and when the switch
is in the up position it provides a high logic level.
There are 27 user-controllable LEDs on the DE2-115 board [10]. Eighteen red LEDs are situated above the 18 Slide switches, and eight green LEDs are found above the push-button switches
(the 9th green LED is in the middle of the 7-segment displays). Each LED is driven directly by a
pin on the Cyclone IV FPGA; driving its associated pin to a high logic level turns the LED on, and
driving the pin low turns it off. Fig. 2.10 shows the connections between LEDs and Cyclone IV
FPGA.
2.3.1.3 7-Segment Displays
The DE2-115 board has eight 7-segment displays. These displays are arranged in two pairs and a
group of four. As indicated in the schematic in Fig. 2.11, the seven segments (common anode) are
connected to pins on the Cyclone IV. The 7-segment displays are actve low.
34
2 Designing Hardware for FPGAs
Fig. 2.8: Push button debouncing [10].
Fig. 2.9: Connections between the slide switches and Cyclone IV FPGA [10].
2.3 An Overview of the Hardware and Software Development Platform
35
Fig. 2.10: Connections between the LEDs and Cyclone IV FPGA [10].
Fig. 2.11: Connections between the 7-segment display HEX0 and the Cyclone IV
FPGA [10].
2.3.1.4 I/O Standards
The I/O voltage levels (standards) for the High Speed Mezzanine Card (HSMC) and the expansion
header on the DE2-115 can be set by using JP7 and JP6 respectively [10]. Nevertheless, these
jumpers also set the I/O standards for peripherals, for example the clock input in Table 2.1. Hence
we list the JP7 and JP6 settings in Tables 2.2 and 2.3.
Table 2.2: JP7 Settings for Different I/O standards
JP7 Jumper Settings Supplied Voltage to VCCIO5 and VCCIO6 IO Voltage of HSMC Connector (JP8)
Short Pins 1 and 2
1.5V
1.5V
Short Pins 3 and 4
1.8V
1.8V
Short Pins 5 and 6
2.5V
2.5V (Default)
Short Pins 7 and 8
3.3V
3.3V
36
2 Designing Hardware for FPGAs
Table 2.3: JP6 Settings for Different I/O standards
JP6 Jumper Settings Supplied Voltage to VCCIO4 IO Voltage of Expansion Header (JP5)
Short Pins 1 and 2
1.5V
1.5V
Short Pins 3 and 4
1.8V
1.8V
Short Pins 5 and 6
2.5V
2.5V
Short Pins 7 and 8
3.3V
3.3V (Default)
2.3.2 VHDL Primer and Using the Quartus Toolset
Although we will be primarily utilizing Simulink for a high level functional specification of our
chaotic systems, it is important to have an idea of the underlying hardware to which our design
synthesizes to. There are many abstraction levels for understanding synthesized hardware. In this
book, we will utilize the HDL approach. Specifically, we will use VHDL - one of the two HDLs
that have an IEEE standard associated with them [14]. The other IEEE standard HDL is Verilog.
We use VHDL in this book because it has better support for parameterized design [13].
Discussing every nuance of VHDL is beyond the scope of this book. Fortunately, many details
are abstracted away because of our functional approach to specifying chaotic systems. However,
we will still discuss some of the most important ideas behind VHDL in this section. For further
study, two very good references on VHDL are Brown and Vranesic that deals with basic VHDL
concepts [12] and Chu’s book on VHDL for efficient synthesis [13].
Before we begin, an important note: as the name indicates, HDL describes hardware [13]. We
are not writing a software program and hence it is essential to approach HDL from the hardware’s
perspective. The synthesis software should also be treated as a tool to perform transformation and
local optimization. It cannot alter the original architecture or convert a poor design into a good one
[13]. A rule of thumb: if we as humans cannot understand the underlying hardware functionality
via the HDL, the synthesizer will not translate the design into a correct functional specification.
2.3.2.1 VHDL modules: entity, ports and architecture
Listing 2.1 below is a sample VHDL hardware specification.
Listing 2.1: Combinational logic in VHDL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-- Lines starting with -- are comments in VHDL.
library ieee; -- include ieee library for the use statements
below
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity simpleLogicGates is port (
x1,x2,x3 : in std_logic;
x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(4 downto 0));
end simpleLogicGates;
architecture combinational of simpleLogicGates is
begin
y(0) <= (x1 and x2) or x3;
2.3 An Overview of the Hardware and Software Development Platform
15
16
17
37
y(2 downto 1) <= (x1&x(0)) AND (x2&x(1));
y(4 downto 3) <= x(3 downto 2);
end combinational;
The first three statements are IEEE standardized libraries to facilitate synthesis [13]. Line
1 invokes the IEEE library and line 2 allows us to use the predefined datatypes, std logic and
std logic vector. The numeric std package enables us to utilize other datatypes such as signed and
unsigned.
The entity declaration in line 6 describes the external interface of our circuit [13]. Our design
communicates with the outside world via ports. These ports can be input, output or inout (bidirectional). In our example, we have three 1-bit wide input ports (x1, x2, x3) and two multi-bit wide
(bus) ports. Note that the std logic (and std logic vector) types support more than ’1’ and ’0’. We
will additionally only utilize the high impedance (’Z’) support in std logic, as this is the only other
type defined for proper synthesis. A potential issue of utilizing ’Z’ is support for tri-state devices
in the underlying hardware but the Cyclone IV on the DE2-115 does support these devices. Also
note that for interfacing to external physical components, we should not use VHDL types such as
integers3 .
The architecture body specifies the internal operation or organization of the digital logic system
[13]. The architecture body consists of concurrent statements that describe combinational logic
and process statements that describe sequential logic. We will first give examples of combinational
logic design.
2.3.2.2 VHDL Combinational Logic Design and Using Quartus
Going back to our design specification in Sec. 2.3.2.1, we have three concurrent statements that
synthesize to the RTL description in Fig. 2.12.
Fig. 2.12: Screen shot of our hardware specification, generated using the Quartus
RTL viewer. The thicker lines imply multi-bits or a bus.
We will now summarize the main steps for using Quartus.
3 Of course, we are free to choose any type for internal communication between modules. Such
flexibility is the purpose of abstraction.
38
2 Designing Hardware for FPGAs
1. The first step in using Quartus is to obtain the software. Although the Quartus web-edition
[3] will suffice for this section, we will need the Quartus Subscription Edition [4], ModelSimAltera [5] and DSP Builder [6] for synthesis, simulation and mathematical functionality specification respectively. Please contact Altera corporation for details on obtaining academic licenses
or purchasing software. In this book, we will utilize the 12.0 versions of the toolset, although
any version after 12.0 is acceptable. Note that some of the screens and menu actions may be
different in newer versions of Quartus.
2. Next we need to download the system CD for our board, the DE2-115, from the board manufacturer (Terasic) website [9]. Although a system CD is part of the board kit, the latest version
is available online. The CD has a plethora of useful documentation and reference designs.
3. Now that we have Quartus installed and the system CD, we can start our design by creating a
new folder 4 for the combinational logic project.
Please refer to the online video and reference design on the companion website: http://www
.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/ReferenceDesigns
/volumeI-ExperimentalObservations/chapter2/combinationalLogicDesig
n/ for completing the simple combinational logic design.
Let us examine a frequently used VHDL construct for combinational logic design, the selected
signal assignment, shown in listing 2.2. The selected signal assignment synthesizes to a multiplexer
at the RTL level.
Listing 2.2: VHDL selected signal assignment
1
2
3
4
5
with selectBits select
output0 <= input0 when "00",
input1 when "01",
input2 when "10",
input3 when others;
The careful reader should have noticed that the type of input (and consequently output) cannot
be inferred from the VHDL snippet above. The type could be std logic, std logic vector or integers. In fact, now would be a good time to look at the online video for a reference design that
realizes an arithmetic logic unit using a mux at the output for selecting between different operations: http://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/R
eferenceDesigns/volumeI-ExperimentalObservations/chapter2/alu/
The video should help the reader complete the simple combinational logic design. An RTL
view of the ALU is shown in Fig. 2.13.
2.3.2.3 VHDL Parameterization
In this section, we will utilize parameterization functionality of VHDL. We will let the synthesizer
infer and connect multiple instances of the same module. Although we will be using a for loop for
synthesis, please remember that we are designing hardware, not programming. The Quartus RTL
view of the top level from our design is shown in Fig. 2.14.
The design primarily contains three components :
1. oneBitFullAdder : The oneBitFullAdder simply implements a structural one bit adder. The
boolean equations for the sum input and the carry outputs for the ith one bit full adder are
shown in Eqs.(2.1) and (2.2) respectively.
si = xi ⊕ yi ⊕ ci
ci+1 = xi yi + ci (xi + yi )
4
It is not a good idea to include spaces in the project path
(2.1)
(2.2)
2.3 An Overview of the Hardware and Software Development Platform
39
Fig. 2.13: RTL view for the ALU design.
Fig. 2.14: RTL view for the ripple carry adder. Extraction of digits in the sum is
done at the top level.
2. genericNBitFullAdder : In order to realize the genericNBitFullAdder, we will connect n one
bit full adders in a ripple carry structure, as shown in listing C.1.
3. sevenSegmentDecoder : The seven segment decoder is a standard decimal to hex decoder module. The VHDL description is shown in listing C.2.
The top level realization of the generic ripply carry adder is shown in listing C.3. In order
to completely understand the design, please look at the online video for the genericNBitFullAdder: http://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/Re
ferenceDesigns/volumeI-ExperimentalObservations/chapter2/rippleCar
ryAdder/
40
2 Designing Hardware for FPGAs
2.3.2.4 VHDL Sequential Logic Design
So far we have seen designs whose output only dependent on the current input, not on the past
history of inputs. Digital circuits where the input depends on both the present and past history of
inputs (or the entire sequence of input values) are called sequential logic circuits [13]. We need
sequential logic circuits to implement memory via registers (flip-flops). We store the system’s state
or state variables in memory and hence sequential logic circuits can also be specified using finite
state machines (or state machines). Fig. 2.15 shows a block diagram of a Moore (Mealy) state
machine. We will examine a 24-hour clock design in order to understand the concepts behind state
machines.
Inputs
Next State Logic
State
Memory
Output
Logic
Outputs
Clock
Reset
Fig. 2.15: Generic block diagram for a finite state machine. State machines are
composed of next state logic (a combinational function of inputs and synchronous
current state). The output function combinational logic function can be a function
of current state only (Moore machine) or current state and input (Mealy). There is a
single clock to ensure the design is fully synchronous. All finite state machines
must have a well defined global reset.
The synthesized Quartus project and a 20-minute video on the design can be obtained from: ht
tp://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/Referenc
eDesigns/volumeI-ExperimentalObservations/chapter2/twentyFourHourC
lock/
Considering Fig. 2.15, one can infer that we should be able to specify each of the blocks via
VHDL. However before we discuss the VHDL realization, we need to understand the concept of a
globally synchronous design [13].
A large digital system should consist of subsystems that operate at different rates or different
clock frequencies. In our 24-hour clock, the seconds counter should be updated at 1 Hz, the minutes
1
1
counter at 60
Hz and the hours counter at 3600
Hz. There are primarily two approaches for clocking,
shown in Figs. 2.16 and Fig. 2.17 .
There are two main problems with the approach in Fig. 2.16. First, the system is no longer
synchronous because if the subsystems interact, then the timing analysis becomes very involved.
Second problem is the placement and routing of multiple clock signals. Since a clock signal needs
a special driver and distribution network, having derived clock signals makes this process more
difficult.
In contrast, the low rate single-clock enable pulse design shown in Fig. 2.17 is the preferred
approach since the different subsystems are driven with the same clock frequency.
2.3 An Overview of the Hardware and Software Development Platform
Step Down
Counter
41
Seconds
Counter
Minutes
Counter
Hours
Counter
Fig. 2.16: System with multiple clock frequencies.
The specification of the seconds counter, along with a single pulse generator is in listingC.4
(obtained from the online Quartus project). The single pulse generator is a state machine that helps
us implement the scheme shown in Fig. 2.17. The state machine generates a pulse that is exactly
one clock cycle long, everytime the seconds counter overflows.
One way to visualize an FSM is using State Machine Diagrams. The state transition diagram
for the single pulse generator is shown in Fig. 2.18
Once you download the online design to the DE2-115 board, you will notice that the base design
clock is counting much faster than the usual 1 Hz frequency for a seconds counter. Exercise 2.1
asks you to modify the design so we have the 1 Hz frequency for the seconds counter.
42
2 Designing Hardware for FPGAs
Seconds
Counter
Minutes
Counter
Hours
Counter
Fig. 2.17: System with a single synchronous clock.
You should also understand that the design has a well defined reset state. Since the DE2-115
keys are debounced in hardware, we can utilize them as reset inputs without a debounce circuit.
Exercise 2.4 considers debouncer design.
Going back to the issue of multiple clock frequencies in a design, a natural question is: can
we always use a single clock frequency for every design? The answer is: no. This situation is
very common when interfacing to external devices. For example, if our design were to interface
with external memory (like SDRAM) then we will most likely have our FPGA design running
at one frequency while the external SDRAM’s clock is at a different frequency. Nevertheless we
should clearly separate the different clock domains in our design. If we do, then we can utilize
powerful timing closure tools provided by FPGA manufacturers to ensure that our design meets
2.3 An Overview of the Hardware and Software Development Platform
43
1/1
0/0
Input0
Input1
0/0
Fig. 2.18: A state transition diagram for the Mealy FSM realization of the single
pulse generator. The circles represent states and the arcs represent transitions
between states. Input(s)/Output(s) are specified on the arcs. It is assumed that
transitions take place only on clock edges and hence synchronous behaviour is
implied. Hence, the output is logic 1 only when we transition from the Input0 to
Input1 state, in other words, the output is high only for one clock pulse. A Moore
FSM is specified in a similar manner, except the outputs are given in the states.
How would you specify the single pulse generator as a Moore FSM? Hint: you
need at least one more state.
timing requirements. We will discuss timing closure in Sec. 2.4. In fact the next section shows an
example design where we do interface to external hardware on the DE1 board.
2.3.3 Audio Codec Interfacing
We need ADC and DAC converters to interface external signals to/from the FPGA respectively. On
the DE2 board, there is a Wolfson WM8731 [11] audio coder/decoder (codec) that has on-board
ADC and DAC. This section shows how we can interface to these peripherals.
Fig. 2.19 shows a top-level block diagram of our design. A discussion of each block follows
[15].
The clock buffer uses two PLL modules: one to buffer the 50 MHz global clock and the other
to provide a 18.42105 MHz clock (from the 27 MHz clock) for sending data to/from the codec.
The i2 c interface initializes the audio codec by sending a series of 10 data packets. In accordance with the i2 c protocol, each data packet is 24 bits long, consisting of: the codec address, the
control register and the control register settings. The 10 packets were retrieved from ROM, and
sent over the two-wire interface via an FSM.
The i2 c clock signal was a 50 KHz clock signal, generated from the 50 MHz PLL buffered
FPGA clock using a counter. Functionally, the i2 c clock lagged the FSM clock by a half-clock
cycle. This allowed the FSM to update each bit on the rising edge of the clock but the bit was still
correctly interpreted by the codec.
Hence this design utilizes different clock frequencies between modules and this cannot be
avoided due to the fact that we are interfacing to an external device. Also, the i2 c protocol lim-
1/0
44
2 Designing Hardware for FPGAs
Fig. 2.19: A screenshot from the Quartus RTL view of our i2 c interface.
its the maximum frequency of the clock to be 3.4 MHz, depending on the mode [8]. Therefore,
there is no possibility of clocking the i2 c initialization module at the global clock frequency of 50
MHz.
The ADC DAC controller module’s primary function is to place data into and read data from
the A/D and D/A registers respectively. First, this controller generates two clock signals:
1. A bit clock with a frequency of 3.07 MHz to clock I/O bits from the codec.
2. A frame clock with a frequency of 192 KHz to signify either the left or right channel.
The synthesized Quartus project for our design can be found online:
http://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/Ref
erenceDesigns/volumeI-ExperimentalObservations/chapter2/DE2i2cInte
rface/
The State Machine Viewer in Quartus can be used to examine the state transition diagram
of our FSM. We can access the state machine viewer using Analysis and Synthesis→Netlist
Viewers→State Machine Viewer.
An important point that we need to remember is the voltage range of the ADA are ±2 V . Hence
any digital design’s I/O must confirm to this range of voltage. Also, the I/O range assumes there is
no loading of the codec input and output.
Fig. 2.20 shows the setup that we used throughout the book. We have a stereo-to-banana cable
that is used for interfacing to scope probes. Fig 2.21 shows the results of the classic loop-back
test: the input from the ADC is directly to DAC output (the online i2 c reference design utilizes
loopback).
Nevertheless, only the phase delay is apparent in fig. 2.21. Effects of sampling are not readily
apparent with a sine wave. Fig 2.22 shows the result of the loop-back rest with a square wave.
Although we could implement the nonlinear functions and the numerical integration method
in VHDL5 , it is much easier to utilize Simulink for an abstract specification of the mathematics.
Sec. C.5 highlights the conceptual steps in using DSP Builder, the Simulink library developed by
Altera. You should go through that section before continuing on with the rest of the this chapter.
5 That is, one could use the MegaWizard in Quartus and avoid DSP Builder. However, the DSP
builder approach is more visual and this is the approach that we will use in this book. If you don’t
have access to DSP Builder, then you can utilize the approach using the MegaWizard. You can
discuss questions related to this approach in the online forums available on the book’s companion
website. Note however that we will use the MegaWizard for implementing some of the functionality, such as bifurcations in Chapter 4.
2.5 Conclusions
45
Fig. 2.20: The experimental setup used in this book. We are not using the
left-channel in this experiment.
2.4 Timing Closure
2.5 Conclusions
Below is a summary of the main concepts in this chapter:
1. The FPGA is an ideal platform for implementing discrete specifications of nonlinear differential
equations because of the massively parallel architecture and variable (user-specified) data and
address bus widths. Nevertheless, properly utilizing an FPGA requires the user to have a sound
knowledge of basic digital logic principles.
2. In the case of sequential logic, one must aim for a globally synchronous design.
3. For implementing abstract mathematical concepts, we will use DSP Builder Advanced Blockset
from Altera.
This chapter involved a lot of ideas and hopefully most of them were review of digital logic
design concepts. In Chapter 3, we will combine digital logic design concepts and the ideas of DSP
builder from this chapter to realize some classic chaotic systems on FPGAs via Simulink.
46
2 Designing Hardware for FPGAs
Fig. 2.21: Sine wave loopback, input frequency is 500 Hz. Notice the large phase
delay at the output.
Fig. 2.22: Square wave loopback at 700 Hz. Compare with Fig. 2.21.
Problems
2.1. Modify the 24-hour clock design from Sec. 2.3.2.4 to accurately count seconds, minutes and
hours.
2.5 Conclusions
47
2.2. Instantiate the D flip-flops for synchronous reset from the 24-hour clock design in VHDL as
opposed to a component-based specification.
2.3. Design a finite state machine whose output is a 1 iff there are two consecutive 1s in the input
stream.
1. Design a Moore FSM for this problem.
2. Design a Mealy FSM for this problem.
2.4. In this problem, we will consider debouncer design [7]. The goal is to design a circuit that
would compensate for the mechanical bounces in switch contacts. This circuit is necessary because
consider our 50 MHz system clock with 20 ns period. Say a mechanical bounce lasts for 1 ms.
1. How many system clock cycles is one mechanical bounce?
2. Let us say we decide to have a timing-based solution: we declare an input change after signal
has been stable for at least 5 ms. Design a system that incorporates a finite state machine and
timer to accomplish this task.
Test your realization by using the mechanical switches on the DE2 board.
2.5. Design a finite state state machine that returns the remainder when an arbitrary size integer is
divided by 5. One way to test your design on the DE2 board is: use two keys as 0 and 1 inputs. You
can use an other key to send a ”display remainder” signal to your design. Obviously, the fourth key
is global reset.
2.6. The concept of recursion is central to computer programming. Consider listing 2.3 that recursively defines the factorial function:
Listing 2.3: Recursive specification of factorial function in MATLAB
1
2
3
4
5
6
7
8
9
function y = myfact(number)
%myfact Recursive realization of factorial function:
%
n! = n*(n-1)*(n-2)...1
if number == 0
y=1;
else
y=number*myfact(number-1);
end
end
A natural question to ask would be: are there recursive structures in hardware? The answer is
yes and a classic example is specifying an m-bit 2n -to-1 mux (m-bits is the input/output bus width
with n-select bits) using 2-1 muxes. Using Fig. 2.23 as an example, design and realize on the DE2
board a recursive multiplexer specification.
The elegant solution in Fig. 2.23 was proposed by Jake Nagel in the EE2900 (Combinational
Logic Design) course at the Milwaukee School of Engineering in the Winter 2012-2013 quarter.
Lab 2 : Introduction to Altera FPGA Tools
Objective: DE2 LCD interface.
Theory: We first need to thoroughly understand the LCD communication protocol. The DE2-115
user’s manual [10] should be our starting point. The display controller is the HD44780 and a data
sheet is available on the system CD that accompanies the DE2 board. Nevertheless, you can simply
48
2 Designing Hardware for FPGAs
Fig. 2.23: Recursively specifying a 3-bit 2-to-1 mux, technology map viewer from
Quartus.
search online and get the latest version of the data sheet.
Lab Exercise:
After going through the LCD documentation, design an FSM to display the words ”Hello” on the
first line and ”World” on the second line of the LCD display. This lab should be a very good review
of digital logic concepts, so please take your time to complete the design before looking at the
online solution video.
References
1. Altera Corporation (2008) My First FPGA Design Tutorial. In: Altera Corporation Online
Tutorials, Available via DIALOG.
http://www.altera.com/literature/tt/tt_my_first_fpga.pdf Cited
22 March 2013
2. Altera Corporation (2013) Cyclone IV Handbook. In: Altera Corporation Online Datasheets,
Available via DIALOG.
http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handb
ook.pdf Cited 19 April 2013
3. Altera Corporation (2013) Quartus Web Edition, Available via DIALOG.
http://www.altera.com/products/software/quartus-ii/web-editio
n/qts-we-index.html Cited 7 May 2013
4. Altera Corporation (2013) Quartus Subscription Edition, Available via DIALOG.
http://www.altera.com/products/software/quartus-ii/subscripti
on-edition/qts-se-index.html Cited 7 May 2013
References
49
5. Altera Corporation (2013) ModelSim-Altera Edition, Available via DIALOG.
http://www.altera.com/products/software/quartus-ii/modelsim/q
ts-modelsim-index.html Cited 7 May 2013
6. Altera Corporation (2013) DSP Builder, Available via DIALOG.
http://www.altera.com/products/software/products/dsp/dsp-buil
der.html Cited 7 May 2013
7. Brigham-Young University ECEn 224 Debouncing a Switch - A Design Example, Available
via DIALOG.
http://ece224web.groups.et.byu.net/lectures/20%20DEBOUNCE.pdf
Cited 12 October 2013
8. NXP Semiconductors (2012) UM10204 i2 C-bus specification and user manual. Available via
DIALOG.
http://www.nxp.com/documents/user_manual/UM10204.pdf Cited 30
September 2013
9. Terasic (2013) Altera DE2-115 Development and Education Board. In: Terasic Corporation
Online Cyclone Main Boards, Available via DIALOG.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=En
glish&No=502 Cited 21 April 2013
10. Terasic (2013) Altera DE2-115 Board User’s Manual on the System CD. In: Terasic
Corporation Online Cyclone Main Boards, Available via DIALOG.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=En
glish&No=502 Cited 21 April 2013
11. Wolfson WM8731 datasheet, Available via DIALOG.
http://www.wolfsonmicro.com/products/audio_hubs/WM8731/ Cited 4
October 2013
12. Brown, S. and Vranesic, Z. (2008) Fundamentals of Digital Logic Design with VHDL. 3rd
edition. McGraw-Hill, New York.
13. Chu, P. P. (2006) RTL Hardware Design using VHDL - Coding for efficiency, portability and
scalability. Wiley-Interscience, New Jersey.
14. Simpson, P. (2010) FPGA design - Best Practices for Team-based Design. Springer, New
York.
15. Stapleton, C. (2011) Neuron Project EE2902 Spring 2011 Final Project Report.
Chapter 3
Chaotic ODEs : FPGA Examples
FPGA realization of the chaotic
attractor from the Highly Complex
Attractor system [9]
Abstract In this chapter, we will focus on realizing chaotic systems on an FPGA. We will first
show a simple numerical method for specifying chaotic systems on the FPGA and then realize the
Lorenz system. We will then illustrate the complete FPGA design process of functional simulation,
in-system debugging and physical implementation. In order to illustrate the robustness of FPGAs,
we will conclude this chapter by realizing a chaotic system with a hyperbolic tangent nonlinearity.
3.1 Euler’s Method
Recall from chapter 1 that we studied chaos in continuous-time differential equations. We also
learned that an FPGA can be used to realize a sampled and discretized version of the differential
equation (recall Fig. 1.9). In this section, we will understand that the block diagram in Fig. 1.9 is
how we realize the forward-Euler’s method [11] on an FPGA.
Consider Eqs.(3.1) through (3.2).
x˙1 = f1 (x1 , . . . , xn )
(3.1)
..
.
x˙n = fn (x1 , . . . , xn )
(3.2)
We can use first principles [11] and rewrite Eqs.(3.1) through (3.2) as Eqs.(3.3) through (3.4).
x1 (t + δ t) = x1 (t) + f1 (x1 (t), . . . , xn (t))∆ t
(3.3)
..
.
xn (t + δ t) = xn (t) + fn (x1 (t), . . . , xn (t))∆ t
(3.4)
When implementing Eqs.(3.3) through (3.4) on an FPGA, we can define:
△
(3.5)
△
(3.6)
xNNew = xn (t) + fn (x1 (t), . . . , xn (t))∆ t
xN = xn (t + δ t)
51
52
3 Chaotic ODEs : FPGA Examples
In Eqs.(3.5) and (3.6), xNNew and xN are VHDL signals with N = 1, 2, · · · , n. δ t is the clock
period for the D flip-flop that results in a synchronous xN. ∆ t is the step-size in Euler’s method.
Listing D.1 shows one possible VHDL specification of Euler’s method for the Lorenz system.
However for consistency (with material from chapter 1) and clarity (the Lorenz system is three
dimensional), we can simply use x, y, z instead of x1, x2, x3. Thus the VHDL design that we will
use is shown in listing D.2.
In order to complete listing D.2, we have to specify the various nonlinearities and scale the nonlinearities by ∆ t. For these purposes, we will utilize DSP builder, along with a VHDL specification
of Euler’s method. This topic is the subject of Sec. 3.2. But a detailed mathematical discussion of
the numerical methods for approximating continuous-time dynamical systems is beyond the course
of this book. This will be discussed in more detail in volume II. Simply put a ”large enough” step
size in Euler’s (or any other numerical method) [4] could introduce anomalies in the numerical
simulation.
3.2 Specifying Chaotic Systems for FPGAs Using DSP Builder
3.2.1 The Lorenz System
Let us first simulate the Lorenz system in Simulink but using the discrete-time integrator block.
Fig. 3.1 shows the discrete Euler’s method specification of the Lorenz system. We have scaled the
state variable outputs to match the output voltage range of the audio codec. x(t) from the simulation
plotted via MATLAB is shown in Fig. 3.2. Code for plotting the result is in listing D.3.
Now that we have verified the functionality of a discrete implementation of the Lorenz system,
we need to implement the nonlinearities using DSP builder. The procedure incorporates the ideas
from Sec. C.5 and an online-video of the implementation can be found on the companion website:
http://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/Ref
erenceDesigns/volumeI-ExperimentalObservations/chapter3/lorenzSyst
em/
We can now complete the VHDL in listing D.2, as shown in listing D.4. An online video that
shows how to incorporate this design with the i2 c interface from Sec. 2.3.3 is on the companion
website:
http://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/Ref
erenceDesigns/volumeI-ExperimentalObservations/chapter3/lorenzSyst
em/
Fig. 3.3 shows x(t) and also the FFT of the signal. If you have headphones, you should plug
them into the line out port and listen to the sounds of the stereo Lorenz chaotic attractor!
3.2 Specifying Chaotic Systems for FPGAs Using DSP Builder
53
Fig. 3.1: Simulink Euler’s method realization of the Lorenz system. We use K=1,
1
) for each discrete time integrator block and use a sampling time
Ts=-1 (∆ t = 1000
of 1e-3 to conserve memory. The physical implementation uses ∆ t = 2−10 and a
sampling time of 1.28 µ s. The discrete-time integrator block can be found in the
Simulink libraries, under Discrete. You can download Simulink design from the
companion website: http://www.harpgroup.org/muthuswamy/ARout
eToChaosUsingFPGAs/ReferenceDesigns/volumeI-Experimenta
lObservations/chapter3/lorenzSystem/
54
3 Chaotic ODEs : FPGA Examples
Fig. 3.2: x(t) from the Lorenz system. Notice the plot indicates that our sampling
time and range of x(t) values should be compatible with the DE2 Wolfson audio
codec parameters.
3.2 Specifying Chaotic Systems for FPGAs Using DSP Builder
55
Fig. 3.3: x(t) from the Lorenz attractor realization on the FPGA, along with an FFT
of the signal.
56
3 Chaotic ODEs : FPGA Examples
One potential issue with the discrete realization is that we have not really discussed how the our
sampling frequency affects the chaotic signal frequency content. We may need to adjust either the
sampling frequency or the fixed-point representation. In the case of the Lorenz system, consider
Fig. 3.4.
Fig. 3.4: x(t) from the Lorenz attractor realization on the FPGA, compared to z(t).
Notice the large variations in z(t) values are not being adequately captured by our
digital system.
In order to refine1 z(t) in Fig. 3.4, we changed the fixed-point representation and this is actually
reflected in the online reference design.
Fig. 3.5 shows the result. Figs. 3.6, 3.7 and 3.8 show the various phase plots.
1
One way to predict the effect on z(t) in Fig. 3.4 is to use functional simulation, the subject of
Sec. 3.3.
3.2 Specifying Chaotic Systems for FPGAs Using DSP Builder
Fig. 3.5: We changed the fixed-point representation to refine z(t).
Fig. 3.6: y(t) vs. x(t) Phase plot of the Lorenz attractor, the left (right) audio
channel is on input X or channel 1 (input Y or channel 2) of the scope. Screen
intensity has been set to 50%.
57
58
3 Chaotic ODEs : FPGA Examples
Fig. 3.7: z(t) vs. x(t) - the classic Lorenz butterfly.
Fig. 3.8: z(t) vs. y(t)
3.3 Introduction to Functional Simulation and In-System Debugging
59
3.3 Introduction to Functional Simulation and In-System
Debugging
After we complete our design in Simulink, it would be prudent to check if the design is functionally
correct. That is, does the hardware perform as it is supposed to? In the case of chaotic systems, a
functional simulation will also tell us if our design functionally reproduces chaotic behavior. One
could also perform a timing-intensive simulation that will also account for delays in the physical
FPGA [6]. Nevertheless, a functional simulation is more than enough for us to check the effects
of sampling rate. Moreover, timing simulations take a lot longer time to run and we will not be
pursuing them further in this book.
There is another important difference between a functional simulation and checking our system
behaviour in Simulink. Functional simulation can tell us how the signals propagate within our
hardware system. Hence a functional simulation will test the fundamental correctness of our digital
circuit. We will use the industry standard ModelSim simulator for functional simulation.
As a natural followup to functional simulation, we can utilize a tool called SignalTap, to debug
the design as it executes on the FPGA. The ”SignalTap Core” is a logic analyzer provided by Altera
that is compiled with your design. A block diagram view of a system that incorporates SignalTap
is shown in Fig. 3.9. In-system debugging using SignalTap is discussion in Sec. 3.5.
Fig. 3.9: Block diagram of a design that has SignalTap compiled as a separate
design partition [2].
In the next section, we will simulate Chen’s system. We will discuss general concepts behind
simulation and then highlight the main steps as to how we can perform the simulation in ModelSim
via the online video. The discussion of ModelSim will be followed by the SignalTap section.
60
3 Chaotic ODEs : FPGA Examples
3.4 Functional Simulation of Chaotic Systems
Eqs.(3.7) through (3.9) are the system equations for Chen’s system [10].
x˙ = a(y − x)
(3.7)
z˙ = xy − bz
(3.9)
y˙ = (c − a)x − xz + cy
(3.8)
Parameters are a = 35, b = 3, c = 28. Initial conditions are (10, 20, 30).
First, we will perform a discrete Euler simulation and realize this system in DSP Builder. The
reference design is placed online: http://www.harpgroup.org/muthuswamy/ARouteT
oChaosUsingFPGAs/ReferenceDesigns/volumeI-ExperimentalObservations
/chapter3/ We have not prepared a video since obviously the steps are the same as in Sec. 3.2.1.
Also note that we have not included ModelSim simulation results since the amount of data can be
hundreds of megabytes (depends on simulation time length, number of waveforms etc.).
In order to perform functional simulation, we first need to design a VHDL file called as a ”test
bench”, that mimics a physical lab bench [6]. The test bench for the Chen system is shown in
listing D.6.
An online video that illustrates how to perform ModelSim simulation is available on the companion website: http://www.harpgroup.org/muthuswamy/ARouteToChaosUsing
FPGAs/ReferenceDesigns/volumeI-ExperimentalObservations/chapter3/c
henSystem Once we know the script window commands appropriate to our design, they can be
placed in a batch file with a .do extension. This file is also available online and is also shown in
listing D.7. In order to use this file, you can simply type: ”do FILENAME.do” in the transcript window command line as soon as you start ModelSim (assuming you have already created a default
work library with the vlib command).
Fig. 3.10 show the result of the ModelSim simulation. Figs. 3.11 through 3.13 show the phase
plots from the physical realization.
Fig. 3.10: 1 ms functional simulation of the Chen system, performed in Modelsim.
Notice how ModelSim can interpret the x, y, z state variables from our Chen system
as an analog waveform.
3.5 Debugging Using SignalTap
61
Fig. 3.11: y(t) vs. x(t) for Chen’s system. 0.5 V/div for both scales on the digital
scope.
3.5 Debugging Using SignalTap
Before we debug the Chen system in SignalTap, let us go over some general ideas, using a simple
design.
3.5.1 General Concepts - An Illustration Using a Simple Example
The design to be analyzed configures a Cyclone II PLL via the MegaIPWizard to step up the 50
MHz board clock to 100 MHz. We use a counter to step down the 50 MHz clock to 1 Hz and output
the slow clock to a green LED on the DE2. We use a different instance of the 1 Hz counter, with
an input clock of 100 MHz. We output this clock to a red LED on the board. Visually, the red LED
will appear to flash twice as fast as the green LED. A top-level FSM waits for the user to press
KEY(0) on the DE2 board before running the design. Fig. 3.14shows a top-level RTL view of the
project. To avoid confusion, we have not included the SignalTap core in Fig. 3.14.
62
3 Chaotic ODEs : FPGA Examples
Fig. 3.12: z(t) vs. y(t) for Chen’s system. X-axis scale is 0.5 V/div, Y-axis scale is
0.2 V/div.
Fig. 3.13: x(t) vs. z(t) for Chen’s system. X-axis scale is 0.2 V/div, Y-axis scale is
0.5 V/div.
There are many ways to start2 SignalTap. The simplest is to add a SignalTap (.stp) file to our
project. We can then configure SignalTap, compile SignalTap with our design and download the
2 Before using SignalTap, you may need to enable the TalkBack feature in Quartus under
Tools→Options→Internet Connectivity.
3.5 Debugging Using SignalTap
63
Fig. 3.14: The top level RTL view of the simple SignalTap project.
resulting .sof file to the DE2. Note that every time we change settings in SignalTap, we will have
to recompile the entire project, if we do not have Incremental Compilation enabled in Quartus.
Incremental Compilation is beyond the scope of this book.
To add the SignalTap file to the project, use File→New and select the SignalTap II Logic
Analyzer File (under Verification/Debugging Files). The SignalTap window in Fig. 3.15 should
appear, the different ”sub-windows” have been labeled. We will use the ”sub-windows” to understand the three primary concepts behind SignalTap: the clock signal, trigger and buffer. Please refer
to Fig. 3.15 as you read the three ideas below.
1. The Clock Signal provides the sampling clock source for the design, we cannot display this
clock in SignalTap. It is implied that SignalTap is always sampling at this clock frequency, data
is captured when one or more trigger conditions are met. According to the Nyquist-Shannon
sampling theorem [12], to avoid aliasing, the sampling clock frequency needs to be at least
twice the highest clock frequency3 in the system. In our project, the fastest clock has a frequency of 100 MHz. Hence we need a sampling clock with a frequency of at least 200 MHz,
we will use a 300 MHz clock.
2. The Trigger source starts capturing data, based on trigger condition(s). In the case of our simple
project, we will trigger on the start button.
3. The Buffer specifies the size of on-chip FPGA memory for data storage. We will use a buffer
size of 4K. The sampling frequency, buffer size and number of signals that we monitor determine the amount of time for which data can be stored.
Please refer to the online video on the companion website: http://www.harpgroup.org
/muthuswamy/ARouteToChaosUsingFPGAs/ReferenceDesigns/volumeI-Exper
imentalObservations/chapter3/SignalTapDemo/. However the result that we should
obtain via SignalTap is shown in Fig. 3.16.
3
Although chaotic systems are mathematically not band-limited, ”most” of the chaos is practically
band-limited due to the underlying sampling period of the numerical method. Hence a good rule
of thumb is to choose the sampling clock frequency to be twice the frequency underlying the
numerical method.
64
3 Chaotic ODEs : FPGA Examples
Fig. 3.15: SignalTap main window.
Fig. 3.16: Results from the SignalTap session. Notice how the 100 MHz clock has
twice the frequency of the 50 MHz clock. Since we are not using a global reset, the
signals are not synchronized.
3.5.2 Debugging the Chen system Using SignalTap
For understanding how to use SignalTap to debug the Chen system, please refer to the online video
and reference design on the companion website: http://www.harpgroup.org/muthuswa
my/ARouteToChaosUsingFPGAs/ReferenceDesigns/volumeI-ExperimentalOb
servations/chapter3/chenSystem/ to understand how to debug the Chen system using
SignalTap.
3.6 Hardware Debugging Concepts
65
3.6 Hardware Debugging Concepts
Before we conclude this chapter, it would be instructive to discuss some general hardware debugging ideas [1] since the designs that we are going to specify using VHDL are quite complex.
We have also discussed debugging via simulation and an in-system logic analyzer in this chapter, so this would be an appropriate place in the book to summarize some engineering debugging
ideas. Most of this section has been paraphrased from Altera’s online documentation for debugging hardware. If you are using an FPGA from a different manufacturer, you should consult the
manufacturer’s debugging documentation for additional tips. However this section is quite general
and should apply to debugging hardware, irrespective of the FPGA manufacturer.
Debugging of complex logic circuits can be difficult. The task is made easier if one uses an
organized approach with the aid of debugging tools. The debugging task involves:
1.
2.
3.
4.
5.
Observing that there is a problem
Identifying the source of the problem
Determining the design changes that have to be made
Changing and re-implementing the design
Testing the corrected design
3.6.1 Observing a Problem
Often it is easy to see that there is a problem because hardware functionality does not match the
designer’s expectations in an obvious way. For example, the graphical image displayed by the RTL
Viewer may indicate that there are missing logic blocks and/or connections. It is usually a good
idea to check at least the top-level of our design. Consider the RTL view in Fig. 3.17.
Fig. 3.17: The erroneous circuit displayed by the RTL Viewer.
66
3 Chaotic ODEs : FPGA Examples
Notice that there is no output from the block hundredth sec. The probable reason is that the
outputs of this module are not being used as inputs anywhere else in the design. Hence the Compiler
decided to omit all output signals from this module. Making this observation via the RTL view
would solve the problem.
As another example, suppose the designer assumes erroneously the labeling of the elements of
a VHDL std logic vector. Consider for instance the labeling of the segments for a seven segment
display. Compiling, synthesizing and programming the FPGA would result in a circuit that seems
to respond properly to pressing of input keys, but generates a strange looking output on the seven
segment displays. Observing this behavior, the designer may suspect that there is something wrong
with the decoder itself. A simple test is to use ModelSim or the SignalTap logic analyzer to ensure
that the outputs of the decoder are in the correct order.
A complex design may be difficult to debug. The implementation may appear to contain all
necessary components, it may appear to function properly, but the results it produces do not exhibit
the expected behavior. In such cases, the first task is to correctly identify the source of the problem.
3.6.2 Identifying the Problem
Designer’s intuition (which improves greatly with experience) may suggest some tests that could
be tried. Otherwise, it is necessary to adopt an organized procedure. A golden rule is to first test
small portions of the circuit, which should be easy to do if the circuit is designed in a modular
fashion. This is referred to as the divide-and-conquer approach.
In this book, you should have noticed that we do emphasize the modular approach. Specifically, the top-level of our design in the RTL Viewer should show only blocks and tri-state buffers.
For instance, consider the DE2 Chaos Engine that implements a variety of chaotic systems,
found online:http://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFP
GAs/ReferenceDesigns/volumeI-ExperimentalObservations/DE2ChaosEngi
ne.zip.
The Compilation Report for the design in Fig. 3.18 is shown in Fig. 3.19.
Notice how the modular top-level has abstracted away a quite complicated design. Moreover,
the modular approach allows a designer to compile, simulate and test each module on its own.
We have also been emphasizing this approach when we simulated the discrete Euler method in
MATLAB before FPGA specification.
3.6.3 Sources of Errors in VHDL Designs
The Quartus II Compiler can detect many errors in VHDL files that specify a given circuit. Typical
errors include incorrect syntax, undeclared inputs or outputs, improper use of signals and incorrect
sizes of vectors. The compiler stops compilation and displays an error message. Such errors are
usually easy to find and correct. It is much more difficult to find errors in a design that appears to
be correctly specified but the specification does not result in hardware that the designer hoped to
achieve. In this subsection, we will consider some typical errors of this type:
1.
2.
3.
4.
5.
6.
Inadvertent creation of latches
Omission of signals
Not assigning a value to a wire
Assigning a value to a wire more than once
Incorrect specification of port map signals
Incorrect definition of signal vector
3.6 Hardware Debugging Concepts
67
Fig. 3.18: Top-level RTL view of the DE2 chaos engine that implements seven
chaotic systems: Lorenz, R¨ossler, Highly Complex Attractor, Chen, Ikeda Delay
Differential Equation, Chua oscillator and Torus Breakdown.
Fig. 3.19: Compilation report for the DE2 chaos engine. It took 45 minutes to
assemble a programmable file on Dr. Muthuswamy’s Windows 7 emulator under
Parallels Desktop.
7. Incorrectly specified FSM (e.g. wrong or invalid next state)
8. Incorrect timing where the output signal of a given subsystem is off by one clock cycle
9. Careless use of clocks
68
3 Chaotic ODEs : FPGA Examples
Inadvertent latches are created by the Compiler if the designer fails to specify the action needed
for all cases in constructs. Latches can also be inferred by the Compiler if the designer forgets to
register input(s) on clock edges.
If the designer fails to use some signals in a VHDL file, the Compiler will ignore these signals
completely and may even omit circuitry associated with these signals. Failure to include the begin
and end delimiters in a multi-statement process block will cause only one statement to be considered valid. Careful use of blocking and nonblocking assignments is essential. It is dangerous, and
not advisable, to use both types of assignments in the same process block. To describe a combinational circuit in a process construct, it is best to use blocking assignments. For sequential circuits,
it is best to use nonblocking assignments.
Errors in the specification of an FSM may lead to a variety of undesirable consequences. They
can cause wrong functional behavior by reaching wrong states, as well as wrong timing behavior
by producing incorrect output signals. A common error results in an output signal that is off by one
clock cycle.
It is particularly important to use clocks carefully. We already discussed in Sec. 2.3.2.4 the
implications of having a single synchronous clock. If we have to utilize different clock frequencies
for interfacing to external components, it is best to use PLL(s).
Inadequate understanding of the board can lead to design errors. Typical examples include:
1. Wrong pin assignment
2. Wrong interpretation of the polarity of pushbutton keys and toggle switches
3. Timing issues when accessing various chips on the board, such as SDRAM memory
If pins are not assigned correctly, the design will not exhibit desired behavior. The Quartus II
compiler causes all unused pins to be driven to ground by default. The easiest way of ensuring
that the pins are correctly assigned for the board is to import the (usual) manufacturer provided
pin assignment file. If the design involves access to external peripherals (particularly memory like
SDRAM), it is necessary to adhere to strict timing requirements by utilizing the peripheral’s data
sheet.
3.6.4 Design Procedure
It is prudent to follow a systematic design procedure that tends to minimize the number of design
errors and simplifies the debugging tasks. Here are final suggestions that are likely to help:
1.
2.
3.
4.
5.
Design the system in a modular, hierarchical manner.
Use well-understood and commonly-used constructs to define circuits.
Test each module, by simulating it, before it is incorporated into a larger system.
Define and test portions of the final design by connecting two or more modules.
If possible, simulate the full design.
It is vital that we write VHDL in a style that allows one to easily visualize the hardware specified by the code. It is also useful to make the resulting VHDL easily understandable for others.
3.7 Another Example - A Highly Complex Attractor System
In Sec. 3.2.1, we realized the classic Lorenz system. In this section, we will realize a system that
will show the robustness of using DSP builder. Consider the Eqs. (3.10), (3.11) and (3.12) [9].
3.7 Another Example - A Highly Complex Attractor System
69
x˙ = y − x
(3.10)
z˙ = −R + xy + |y|
(3.12)
y˙ = − tanh(x)z
(3.11)
R = 60 in Eq.(3.12) and initial conditions are (1, 1, 1). The robustness of DSP builder will be
evident when we are able to realize the hyperbolic tangent function in Eq.(3.11). What makes this
system interesting is the fact that as of 2013, this system has the largest Lyapunov dimension of
2.3 (for a dissipative chaotic system) [9]. In this section, we will first simulate and then realize this
system on the FPGA.
Figs. 3.20 and 3.21 show a portion of the Simulink block diagram and x(t) from the simulation
result respectively.
Fig. 3.20: A screenshot of the Simulink discrete Euler realization of the highly
complex attractor system. You can download Simulink design from the companion
website: http://www.harpgroup.org/muthuswamy/ARouteToChaos
UsingFPGAs/ReferenceDesigns/volumeI-ExperimentalObserva
tions/chapter3/highlyComplexAttractor/
70
3 Chaotic ODEs : FPGA Examples
Fig. 3.21: x(t) from the highly complex attractor system. Notice how the large
Lyapunov dimension affects our simulation in the sense we need a large simulation
time step to save memory.
Notice that due to the large Lyapunov dimension, our simulation parameters need to closely
match our implementation sampling frequency and dt. The step size used in simulation implies
large amounts of memory (we generate 40000001 x, y, z values). One solution to overcome the
memory issue is to run a hardware functional simulation4
Example 3.1. Implement tanh(x) in DSP Builder Advanced blockset
Solution: Upon examining the ModelPrim blocks, we will notice that we do not have a
hyperbolic tangent function. Nevertheless, using first principles, we get:
4
We could also reduce simulation step size and K in the Simulink simulation but you will notice
our results will not match with the physical realization (when compared with the Lorenz system)
because of the large Lyapunov dimension. Turns out our choices for sampling frequency and dt
are sufficient to simulate the system accurately. But before we look at the physical realization, we
need to address the issue of specifying the hyperbolic tangent function in DSP builder.
3.7 Another Example - A Highly Complex Attractor System
71
sinh(x)
cosh(x)
(3.13)
=
0.5(ex − e−x )
0.5(ex + e−x )
(3.14)
=
e2x − 1
e2x + 1
(3.15)
tanh(x) =
In the ModelPrim blocks, we do have exponential functions. Hence, we will implement
Eq.(3.15) in DSP Builder.
Figs. 3.22 through 3.26 show physical realization results. The VHDL specification is in listing D.5. We have however not recorded videos since the concepts are analogous to the Lorenz system. You can however download the Quartus project that incorporates the Lorenz system and the
highly complex attractor system5 from the companion website: http://www.harpgroup.or
g/muthuswamy/ARouteToChaosUsingFPGAs/ReferenceDesigns/volumeI-Expe
rimentalObservations/chapter3/. We have not synthesized the Quartus project since
the fully synthesized project size is approximately 90 MB.
Fig. 3.22: Time domain waveform from the highly complex attractor system.
5 There are other chaotic systems in the zipped Quartus project that we will utilize later in the
book.
72
3 Chaotic ODEs : FPGA Examples
Fig. 3.23: The two other state variables from the highly complex attractor system
plotted in the time-domain.
3.8 Conclusions
Below is a summary of the main concepts and steps used in this chapter:
1. We have made a design choice of specifying synchronous Euler’s method in VHDL instead of
in DSP Builder, please refer to listing D.4.
2. We should first run a discrete-time simulation of our chaotic differential equation to identify
ideal sampling frequencies and to get an idea of the maximum (minimum) state variable values
so we can appropriately scale the output to match the DAC range of our audio codec.
3. We need to add both the nonlinear subsystem and nonlinear synthesizable subsystem from our
DSP builder design to our Quartus project. We also need to add the following DSP builder
libraries (from the appropriate Quartus installation directory):
altera/12.0/quartus/dspba/Libraries/vhdl/fpc/math_package.vhd
altera/12.0/quartus/dspba/Libraries/vhdl/fpc/math_implementation.vhd
altera/12.0/quartus/dspba/Libraries/vhdl/fpc/hcc_package.vhd
altera/12.0/quartus/dspba/Libraries/vhdl/fpc/hcc_implementation.vhd
altera/12.0/quartus/dspba/Libraries/vhdl/fpc/fpc_library_package.vhd
altera/12.0/quartus/dspba/Libraries/vhdl/fpc/fpc_library.vhd
4. We need to add fixed point wrapper functions [3] around our DSP builder synthesized subsystem so that we can use the audio codec controller, please refer to listing D.4. Note that the
number of bits for the fixed point integer and decimal part will vary with the chaotic system.
5. A ModelSim simulation of our chaotic system is used to confirm the functionality of our digital
design. Since the discrete Euler’s method in Simulink cannot take into account our entire digital
system (including the i2 c protocol for the audio codec), a ModelSim simulation is a must.
3.8 Conclusions
73
Fig. 3.24: y(t) vs. x(t), 0.5 V/div scale for y and 0.2 V/div scale for x. We used the
analog Tektronix 2205 scope to capture XY waveforms because, due to the large
Lyapunov dimension, the features of the attractor in phase space were better
resolved in an analog scope.
6. A test bench should be utilized to test the different sub-components of our design. Test benches
are not synthesizable, so any VHDL constructs can be used.
7. In-system debugging provides an alternative to timing intensive simulation. Moreover, we are
debugging the design as it is executing on the FPGA.
8. Debugging is both an art and a science. But remember this quote from Einsten while debugging:
”Insanity: doing the same thing over and over again but expecting different results”.
We now have the necessary FPGA knowledge to study a very important concept that is central
to the formation of a chaotic attractor - bifurcations. This is the subject of chapter 4.
Problems
3.1. Experiment with the sampling frequency and fixed point representation for the highly complex
attractor system.
3.2. Reconsider the Chua system (Eqs.(1.82), (1.83) and (1.84)), repeated below for convenience.
x˙ = α [y − x − m1 x −
y˙ = x − y + z
z˙ = −β y
1
(m0 − m1 ) (|x + 1| − |x − 1|)]
2
(3.16)
(3.17)
(3.18)
74
3 Chaotic ODEs : FPGA Examples
Fig. 3.25: z(t) vs. x(t), 0.5 V/div scale for z and 0.2 V/div scale for x.
Fig. 3.26: z(t) vs. y(t), 0.5 V/div scale for both axes.
−5
m0 , m1 , α , β ∈ R are parameters of the system. Use m0 = −8
7 , m1 = 7 , α = 15.6, β = 25.58 to
perform a discrete simulation and then realize the system on the FPGA.
3.8 Conclusions
75
3.3. Simulate and implement Sprott’s jerky chaotic system shown in Eqs.(3.19), (3.20) and (3.21).
x˙ = −2y
(3.19)
y˙ = x + z2
(3.20)
z˙ = 1 + y − 2z
(3.21)
3.4. Simulate and implement the R¨ossler system in Eqs.(3.22), (3.23) and (3.24).
x˙ = −y − z
(3.22)
y˙ = x + α y
(3.23)
z˙ = β + z(x − γ )
(3.24)
α , β , γ ∈ R are parameters of the system. Use α = 0.1, β = 0.1, γ = 14.
3.5. Simulate and implement the hyperchaotic L¨u system [5] in Eqs.(3.25), (3.26), (3.27) and
(3.28).
x˙ = a(y − x) + u
(3.25)
z˙ = xy − bz
(3.27)
y˙ = −xz + cy
(3.26)
u˙ = xz + du
(3.28)
Parameter values are: a = 36, b = 3, c = 20, d = 1.3. Initial conditions are (1, 2, 3, 4). Note
that since we have a four-dimensional system and for the parameters chosen we have a value of
hyperchaos. When we realize this system on the FPGA, we have to make sure that we output all
four state variables via the DAC on the audio codec.
3.6. We could make a refinement on the simple forward-Euler numerical method for solving
chaotic differential equations by considering the fourth-order RK method shown in Eqs.(3.29)
through (3.33) [11].
k1 = F(xt )δ t
k1
δt
k2 = F xt +
2
k2
k3 = F xt +
δt
2
k4 = F (xt + k3 ) δ t
k1 k2 k3 k4
+
+
+
xt+δ t = xt +
6
3
3
6
(3.29)
(3.30)
(3.31)
(3.32)
(3.33)
Implement Eqs. (3.29) through (3.33) on the FPGA. A maximum step size of δ t = 0.1 is more than
adequate for most cases because the natural period of oscillation is typically less than 1 radian per
second when the parameters are of order unity, and thus there is the order of 2δπt ≈ 63 iterations
per cycle [11]. Using this idea, determine an appropriate step size (∆ t) and sampling count for the
FPGA realization. Test your algorithm by implementing the circulant chaotic system [11] on the
FPGA.
x˙ = −ax + by − y3
y˙ = −ay + bz − z3
z˙ = −az + bx − x3
(3.34)
(3.35)
(3.36)
76
3 Chaotic ODEs : FPGA Examples
Parameters are: a = 1, b = 4. Initial conditions are (0.4, 0, 0). Note that the online reference design
for this chapter has an Euler’s method realization of the circulant chaotic system. Compare your
RK realization to the Euler realization.
3.7. Perform a functional simulation of the simple combinational logic design from Sec. 2.3.2.1
(listing 2.1). Note that although a functional simulation is ”overkill” for this design, this problem should help you understand the nuances of ModelSim by using a very simple example for
simulation.
3.8. Perform a functional simulation of the generic n-bit ripple carry adder from Sec. 2.3.2.3.
3.9. Perform a functional simulation of the i2 c design from Sec. 2.3.3.
3.10. Design and verify the SignalTap waveforms for the PLL based design in Sec. 3.5.1. Also add
a global asynchronous reset.
Lab 3 : ModelSim Simulation, In-System Debugging and
Physical Realization of the Muthuswamy-Chua System
Objective: Simulate and physically realize the Muthuswamy-Chua [13] [7] [8] system.
Theory: The Muthuswamy-Chua system models a linear inductor, linear capacitor and memristor
in series (or parallel). In this book, we will use the original series version whose system equations
are Eqs.(3.37) through (3.39) [8].
iL
C
−1
(vC + R(z)iL )
i˙L =
L
z˙ = f (z, iL )
v˙C =
(3.37)
(3.38)
(3.39)
(3.40)
Lab Exercise:
Simulate, verify using SignalTap and hence implement Eqs. (3.37) through (3.39) for the following
parameters and functions: C = 1, L = 3, R(z) = β (z2 − 1), f (z, iL ) = −iL − α z + ziL , β = 1.5, α =
0.6. Initial conditions are: (0.1, 0, 0.1). For the simulation, please check the output from the audio
codec controller as well. This will help you determine if the left-channel and right-channel DAC
registers use the entire range of values reserved for 16-bit 2’s complement.
References
1. Altera Corporation Debugging of VHDL Hardware Designs on Altera’s DE-Series Boards,
Available via DIALOG.
ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/VH
DL/Debugging_Hardware.pdf Cited 23 March 2014
2. Altera Corporation Quartus II 10.0 handbook - Design Debugging Using the SignalTap II
Logic Analyzer, Available via DIALOG.
http://www.altera.com/literature/hb/qts/qts_qii53009.pdf Cited
23 March 2014
References
77
3. Cornell University Digital Differential Analyzer. In : ECE5760 Homepage, Available via
DIALOG.
http://people.ece.cornell.edu/land/courses/ece5760/DDA/index.
htm Cited 13 October 2013
4. Numerical Simulation of Chaotic ODEs . In : Chaos from Euler Solution of ODEs, Available
via DIALOG.
http://sprott.physics.wisc.edu/chaos/eulermap.htm Cited 24 August
2014
5. Chen, A. et. al. (2006) Generating Hyperchaotic L¨u attractor via state feedback control, Physica A, 364, pp. 103 - 110.
6. Chu, P. P. (2011) Embedded SOPC Design with NIOS II Processor and VHDL Examples.
John-Wiley.
7. Llibre, J. and Valls, C. (2012) On the Integrability of a Muthuswamy-Chua system, Journal
of Nonlinear Mathematical Physics, Vol. 19, No. 4, pp. 1250029-1250041.
8. Muthuswamy, B. and Chua, L. O. (2010) Simplest Chaotic Circuit, International Journal of
Bifurcation and Chaos, Vol. 10, No. 5, pp. 1567-1580.
9. San-Um W. and Srisuchinwong, B. (2012) Highly Complex Chaotic System with Piecewise
Linear Nonlinearity and Compound Structures, Journal of Computers, Vol. 7, No. 4, pp. 10411047.
10. Lu, J. et. al. (2002) Local Bifurcations of the Chen System, International Journal of Bifurcation and Chaos, Vol. 12, No. 10, pp. 2257-2270.
11. Sprott, J. C. (2010) Elegant Chaos. World Scientific.
12. Varaiya, P. P. and Lee, E. A. (2002) Structure and Interpretation of Signals and Systems,
Addison-Wesley.
13. Zhang, Y. and Zhang, X. (2013) Dynamics of the Muthuswamy-Chua system, International
Journal of Bifurcation and Chaos, Vol. 23, No. 8, pp. 1350136 - pp. 1350143.
Chapter 4
Bifurcations
FPGA realization of the R¨ossler
chaotic system
Abstract This chapter will explore a variety of routes that lead to chaos in dynamical systems,
through simulation and FPGA experiments. The goal of this chapter is simply for the reader to
understand that a system is chaotic for a certain range of parameters and there are interesting
mechanisms that lead to the chaotic behavior.
4.1 The Concept of Bifurcations
Simply put, bifurcations are sudden qualitative changes in system dynamics at critical parameter
values [2]. For example, consider the R¨ossler system in problem 2 from Chapter 1.
x˙ = −y − z
(4.1)
y˙ = x + α y
(4.2)
z˙ = β + z(x − γ )
(4.3)
We will first specify the system from Eqs.(4.1) through (4.3) in MATLAB. In listing E.1, we
have utilized parameterized functions so that we can pass in ODE simulation settings and parameters. On the MATLAB command line, we can type listing E.2 to obtain a phase plot, with parameter
values α = 0.1, β = 0.1 and γ = 4. In listing E.2, we only plot a subset of our state variables to
account for transient behavior. Fig. 4.1 shows the result.
We will now investigate the behavior of our system as we change one of the parameters while
keeping the other parameters fixed. We will use phase space to visualize the change in system
behavior, leading to chaos. This ”birth” of chaos is technically called as ”route to chaos”.
Note that the question regarding the most common route to chaos is, in any but a very select
set of specific examples, still an open and poorly defined question [3]. Even analytically piecing
together the types of bifurcations that can exist en route to chaos is usually difficult.
79
80
4 Bifurcations
6
4
2
x
0
−2
−4
−6
−8
−8
−6
−4
y
−2
0
Fig. 4.1: y vs. x phase plot for the R¨ossler system from listings E.1 and E.2.
4.2 Routes to Chaos
There are a variety of routes to chaos, in this section we will discuss some of the more ”common”
types and investigate bifurcation behaviour using MATLAB. FPGA investigation of bifurcations is
covered in Sec. 4.3.
4.2.1 Period-Doubling Route To Chaos
In this route to chaos, an equilibrium point looses stability and a stable limit cycle emerges through
an Andronov-Hopf bifurcation [6]. As we continue changing the value of a parameter, a stable limit
cycle at approximately twice the period emerges, which we will refer to as a period-2 limit cycle.
As the parameter value is further changed, the period-2 limit cycle in turn loses stability and a
stable period-4 limit cycle appears. This bifurcation occurs many times at ever decreasing intervals
of the parameter range which converges at a geometric rate to a limit when chaos is observed.
Let us use the R¨ossler system to illustrate period-doubling. Listing E.3 gives MATLAB code,
results are shown in Fig. 4.2.
Notice that it becomes quite difficult to visually spot the period (Fig. 4.2d) as the system tends
towards chaotic behaviour.
4.2 Routes to Chaos
Period-3
20
15
15
10
10
5
5
0
0
−5
−5
−10
−10
−15
−15
−20
−20
−15
−10
−5
x
−20
−20
0
−15
−10
x
−5
0
5
0
5
Higher Period
Chaos
20
Period-6
20
y
y
81
20
15
15
10
10
5
5
y
0
y
0
−5
−5
−10
−10
−15
−15
−20
−25
−20
−20
−15
−10
x
−5
0
5
−25
−20
−15
−10
x
−5
Fig. 4.2: Period-doubling route to chaos in the R¨ossler system. α = 0.1, β = 0.1 for
all the plots above. Bifurcation parameter value of γ (starting clockwise from
top-left): Period-3 - γ = 12; Period-6 - γ = 12.6; Higher Period - γ = 13.3; Chaos γ = 14.
4.2.2 Period-Adding Route To Chaos
In this route to chaos, we will have windows of consecutive periods separated by regions of chaos
[6]. In other words as the parameter is varied, we obtain a stable period-n orbit, n = 1, 2, · · · followed by a region of chaos, then a stable period-(n + 1) orbit, followed by chaos and then a period(n + 2) orbit and so on.
Consider Chua’s oscillator equations [4] in Eqs.(4.4) through (4.6), a generalization of the Chua
system from problem 1.7.
x˙ = α (y − g(x))
(4.4)
z˙ = −β y − γ z
(4.6)
y˙ = x − y + z
The nonlinear function g is given in Eq.(4.7).
(4.5)
82
4 Bifurcations
g(x) = ax3 + cx
(4.7)
The difference between Chua’s oscillator and Chua’s circuit is the γ z term in Eq.(4.6). In the
physical circuit realization, this term is obtained by using a resistor in series with the inductor [4].
In order to observe period-adding route to chaos, we will fix parameters α = 3.708, γ =
0.076, a = 1, c = −0.276. β will be varied. Listings E.4 and E.5 show MATLAB code, results
are in Fig. 4.3.
Chaos after 3:3 Limit Cycle
0.2
0.15
0.15
0.1
0.1
0.05
0.05
x
x
3:3 Limit Cycle
0.2
0
−0.05
0
−0.05
−0.1
−0.1
−0.15
−0.15
−0.2
−0.8
−0.6
−0.4
y
−0.2
−0.2
−0.8
0
0.2
0.15
0.15
0.1
0.1
0.05
0.05
0
−0.05
y
−0.2
0
0
−0.05
−0.1
−0.1
−0.15
−0.15
−0.2
−0.8
−0.4
Chaos after 4:4 Limit Cycle
0.2
x
x
4:4 Limit Cycle
−0.6
−0.6
−0.4
y
−0.2
0
−0.2
−0.8
−0.6
−0.4
y
−0.2
0
Fig. 4.3: Period-adding route to chaos, obtained using Chua’s oscillator. For 3 : 3
limit cycle β = 3.499, for chaos after 3:3 limit cycle β = 3.708, for 4 : 4 limit
cycle β = 3.574 and for chaos after 4:4 limit cycle β = 3.6.
4.2 Routes to Chaos
83
4.2.3 Quasi-periodic Route To Chaos
In this route to chaos, we will have a toroidal attractor bifurcating into a chaotic attractor [6]. The
toroidal attractor is initially formed due to two incommensurate frequencies1 . Consider the system
of equations in Eqs.(4.8) through (4.10) [9].
x˙ = −α f (y − x)
(4.8)
y˙ = − f (y − x) − z
(4.9)
z˙ = β y
(4.10)
The nonlinear function f is given in Eq.(4.11).
1
f = −ax + (a + b) (|x + 1| − |x − 1|)
2
(4.11)
The bifurcation sequence is shown in Fig. 4.4, the relevant code is in listings E.6 and E.7. Here,
we have a two-torus, namely a quasi-periodic solution and as we increase α further we observe that
the two-torus and the periodic attractor (phase-locking) alternatively appear and disappear many
times [9]. As we continue to increase α , the two-torus will fail to appear and we can obtain chaos
through the period-doubling, period-adding (discussed earlier) or torus-breakdown. This section
discussed torus-breakdown, the other two scenarios are left as exercises.
4.2.4 Intermittency Route to Chaos
Intermittency is the phenomenon where the signal is virtually periodic except for some irregular
(unpredictable) bursts [6]. In other words, we have intermittently periodic behaviour and irregular
aperiodic behaviour.
In this section, we will start with the physical Chua’s oscillator [6], to illustrate the idea of
dimensionless scaling2 . We will then choose a set of parameter values such that the intermittency
route to chaos is observed.
Example 4.1. Consider the circuit equations of Chua’s oscillator shown in Eqs.(4.12)
through (4.14). Scale the circuit equations into a dimensionless form suitable for implementation on an FPGA [10].
1 (v2 − v1 )
− f (v1 )
(4.12)
v˙1 =
C1
R
1 (v1 − v2 )
v˙2 =
+ i3
(4.13)
C2
R
1
di3
= − (v2 + R0 i3 )
(4.14)
dt
L
1
2
Incommensurate frequencies ω1 and ω2 imply that the ratio
ω1
ω2
∈ R\Q.
Although dimensionless scaling could have been covered in Chapter 1, we delayed introducing
this concept so the reader can appreciate the idea better, once they have been well-exposed to chaos.
84
4 Bifurcations
Two-torus
2.5
Period-8
3.5
3
2
2.5
2
x
x
1.5
1
1.5
1
0.5
0.5
0
0
−2.5
−2
−1.5
−1
y
−0.5
0
−0.5
−2.5
0.5
Chaos
4
−2
−1.5
−1
y
−0.5
0
0.5
0
0.5
Period-15
3.5
3
3
2.5
2
x
x
2
1
1.5
1
0
0.5
0
−1
−0.5
−2
−3
−2
−1
0
y
1
2
3
−1
−2.5
−2
−1.5
−1
y
−0.5
Fig. 4.4: Torus breakdown route to chaos. β = 1, a = 0.07, b = 0.1 for all the plots
above. Bifurcation parameter value of α (starting clockwise from top-left):
Two-torus - α = 2.0; Period-8 - α = 8.0; Period-15 - α = 8.8; Chaos - α = 15.0
The piecewise-linear function f in Eq.(4.12) is given in Eq.(4.15):
1
f (v1 ) = Gb v1 + (Ga − Gb )(|v1 + E| − |v1 − E|)
2
(4.15)
Solution: Notice we know have a piecewise linear function for the nonlinearity, as opposed
to Eq.(4.7) in Sec. 4.2.2. In order to perform dimensionless scaling, we need to cast voltage,
current and time into dimensionless form. To do so consider the following definitions:
RR0C2
L
△
R2C2
,
L
γ=
y=
△
C2
,
C1
β=
△
△
z = i3
v1
,
E
a = RGa ,
R
,
E
v2
,
E
△
α=
△
△
x=
△
b = RGb ,
k = 1, if RC2 > 0,
△
τ=
t
|RC2 |
(4.16)
(4.17)
k = −1, if RC2 < 0
(4.18)
Utilizing the definitions in Eqs.(4.16) through (4.18), we get Eqs.(4.19) through (4.22).
4.2 Routes to Chaos
85
dx
= kα (y − x − f (x))
dτ
dy
= k (x − y + z)
dτ
dz
= k (−β y − γ z)
dτ
1
f (x) = bx + (a − b) (|x + 1| − |x − 1|)
2
(4.19)
(4.20)
(4.21)
(4.22)
Parameter values for the intermittency route to chaos are α = −75.018755, a = −0.98, b =
−2.4, k = 1. In this case, we will have two bifurcation parameters: β and γ . However the intermittency route to chaos is nevertheless a co-dimension one bifurcation in the sense that the
corresponding route in the parameter space is a 1-D curve [8].
Simulation code is shown in listings. E.8 and E.9. Simulation result is shown in Fig 4.5. FPGA
implementation will be discussed in Sec. 4.3.4.
4.2.5 Chaotic Transients and Crisis
Transient chaos is the mechanism by which a trajectory typically behaves chaotically for a finite
amount of time before settling into a final (usually nonchaotic state) [7]. The dynamical origin of
transient chaos is known : it is due to nonattracting chaotic saddles in phase space [7]. What is interesting about transient chaos is that we have chaotic saddles, unlike say the Lorenz system where
we have chaotic attractors. A chaotic attractor is a bounded set that exhibits a fractal structure only
in the stable direction whereas a chaotic saddle is a bounded set that exhibits a fractal structure
in both stable and unstable directions3 . Due to the fractal structure in the unstable direction, an
infinite number of gaps of all sizes exists along the unstable manifold of the chaotic saddle. An
initial condition is typically attracted toward the chaotic saddle along the stable direction, stays in
its vicinity for a finite amount of time, and then leaves the chaotic saddle through one of the gaps
int he unstable direction. It is known that chaotic saddles and transient chaos are responsible for
important physical phenomena such as chaotic scattering and particle transport in open hydrodynamical flows [7]. We will now consider an example of chaotic transients in a physical model, that
will lead to species extinction!
Extinction of species has been one of the biggest mysteries in nature [7]. A common belief
about local extinction is that it is typically caused by external environmental factors such as sudden changes in climate. For a species of very small population size, small random changes in
population (known as ”demographic stochasticity”) can also lead to its extinction. Clearly, the
question of how species extinction occurs is extremely complex, as each species typically lives in
an environment that involves interaction with many other species (e.g., through competition for
common food sources, predator-prey interactions, etc.) as well as physical factors such as weather
and disturbances. From a mathematical point of view, a dynamical model for the population size
of a species is complex, involving both spatial and temporal variations. Thus such a system in general should be modeled by nonlinear partial differential equations. An obvious difficulty associated
with this approach is that the analysis and numerical solution of such nonlinear partial differential
equations present an extremely challenging problem in mathematics.
3
Detailed theoretical methods to understand chaotic systems as pertaining to FPGA realizations
will be covered in Volume II.
86
4 Bifurcations
Limit Cycle(s)
Limit Cycle(s) (time-domain)
3
1.5
1
2
0.5
z
x
1
0
0
−0.5
−1
−2
−0.3
−1
−0.2
−0.1
y
0
0.1
−1.5
740
0.2
750
760
t
770
780
790
Intermittency Chaos (time-domain)
Intermittency
0.4
1.5
0.3
1
0.2
0.1
y
x
0.5
0
0
−0.1
−0.5
−0.2
−1
−1.5
−3
−0.3
−2
−1
0
z
1
2
−0.4
740
3
750
760
t
770
780
790
Intermittency Chaos (time-domain)
Intermittency
0.4
1.5
0.3
1
0.2
0.1
y
x
0.5
0
0
−0.1
−0.5
−0.2
−1
−1.5
−2.5
−0.3
−2
−1.5
−1
z
−0.5
0
−0.4
740
0.5
750
760
t
770
780
790
Intermittency Chaos (time-domain)
Intermittency
0.5
1.5
0.4
1
0.3
0.5
y
x
0.2
0
0.1
−0.5
0
−1
−1.5
−0.5
−0.1
0
0.5
1
z
1.5
2
2.5
−0.2
740
750
760
t
770
780
790
Fig. 4.5: The intermittency route to chaos. Bifurcation parameter value for β , γ
(starting from top): Periodic - β = 44.803, γ = −4.480; First chaotic intermittency
- β = 43.994721, γ = −4.3994721; Second chaotic intermittency β = 31.746032, γ = −3.1746032; Third chaotic intermittency β = 31.25, γ = −3.125
Nonetheless, in certain situations, the problem of species extinction may become simpler.
Specifically, in this section, we will use the much simpler three dimensional nonlinear ODEs suggested by McCann and Yodzis [7]: a resource species, a prey (consumer) and a predator. The population densities of these three species denoted by R, C and P for resource, consumer and predator,
respectively, are governed by Eqs.(4.23) through (4.25).
4.3 Bifurcation Experiments With an FPGA
R
xC yCCR
dR
= R 1−
−
dt
K
R + R0
yC R
xP yP PC
dC
−1 −
= xCC
dt
R + R0
C +C0
dP
yP C
= xP P −1 +
dt
C +C0
87
(4.23)
(4.24)
(4.25)
K is the resource carrying capacity and xC , yC , xP , yP , R0 and C0 are parameters that are positive.
The model carries the following biological assumptions [7]:
1. The life histories of each species involve continuous growth and overlapping generations, with
no age structure (this permits the use of differential equations)
2. The resource population (R) grows logistically
3. Each consumer species (immediate consumer C, top consumer P) without food dies of exponentially
C yC R
4. Each consumer’s feeding rate (example, xR+R
) saturates at high food levels
0
Realistic values for parameters can be derived from bioenergetics. Following [7], we fix xC =
0.4, yC = 2.009, xP = 0.08, yP = 2.876, R0 = 0.16129,C0 = 0.5. The resource carrying capacity, K,
can be different in different environments and hence is our bifurcation parameter.
Figure 4.6 show a chaotic attractor and a limit cycle for K < Kc ≈ 0.99976. There is a perioddoubling cascade to chaos and a crisis at K = Kc . Note that none of the populations will become
extinct for K < Kc because the chaotic attractor is located in a phase-space region away from the
origin. Initial conditions do tend to a trajectory along the second co-existing attractor, the limit
cycle. This correspond to the situation where the top predator population becomes extinct. As the
carrying capacity increases beyond the critical value Kc , the predator population becomes extinct
for almost all initial conditions. This can be understood from dynamical systems theory because
at K = Kc a crisis occurs since the tip of the chaotic attractor touches the basin boundary [7], after
which there is transient chaos shown in Fig 4.6. It can be seen that P(t) remains finite initially
but decreases rapidly to zero. Thus we see that species extinction can indeed occur as a result of
transient chaos.
Simulation code is in listings E.10 and E.11. FPGA realization is in Sec. 4.3.5.
4.3 Bifurcation Experiments With an FPGA
The next step is to physically study bifurcation mechanisms in chaotic systems using FPGAs. Most
development boards (including the DE2) have hardware debounced push-buttons. These pushbuttons can be used to increment or decrement parameters. As we discussed in Chapter 2, we have
four push-buttons on the DE2 board. Since we have used KEY(0) as global reset, we can utilize
the rest of the keys for bifurcation experiments. There are two steps involved:
1. Implement a pulse generator that accounts for latency (propagation delay)
2. Implement parameter change(s) (increment, decrement etc.) using the appropriate floating point
modules (adder, subtractor etc.).
We will illustrate both steps above using the bifurcation scenarios from Sec. 4.2. We will also
illustrate the concept of hierarchical design by using subsystems in Simulink for implementing the
various nonlinearities.
88
4 Bifurcations
Limit Cycle
0.9
Chaos
1.2
0.8
1.1
0.7
1
0.6
0.9
P
C
0.5
0.4
0.8
0.3
0.7
0.2
0.6
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.1
0.5
0.15
0.2
R
0.3
0.35
P population decays
P time series
1.4
0.25
R
0.14
1
0.1
0.8
0.08
P
0.12
P
1.2
0.6
0.06
0.4
0.04
0.2
0.02
0
0
100
200
t
300
400
500
0
0
100
200
t
300
400
500
Fig. 4.6: Chaotic Transients and Crisis. Starting from top, clockwise: The limit
cycle co-exists with the chaotic attractor. Notice that before the onset of crisis, P
time series decays. The limit cycle and chaotic attractor were obtained by using
different sets of initial conditions (for limit cycle: (0.1, 0.2, 0.1), for chaos:
(0.55, 0.35, 0.8)), but the same parameter values. After the onset of crisis, even
though P oscillates chaotically initially, the predator population eventually decays
to 0.
Example 4.2. Discuss why we need a pulse generator and utilize the single pulse generator
from listing C.4 as a reference design, but implement the pulse generator as a Moore FSM.
Solution: The sampling clock period is 20 ns. But pressing and releasing any push button
has a minimum human reaction time of 1 ms. Therefore in order to ensure that a single key
press is not misinterpreted as multiple key presses, we need a pulse generator. We will also
need to account for latency associated with floating point computation. Implementation of
a pulse generator Moore FSM that incorporates latency is shown in listing E.12.
We use a pulse that is eight clock cycles long because the latency associated with the
floating point addition or subtraction is seven clock cycles. We wait one more clock cycle
to make sure data has been correctly updated on the rising edge of the clock for the floating
point module.
4.3 Bifurcation Experiments With an FPGA
89
Before we move on to the next example of realizing parameter increment, it is a good idea
to check our FSM functionality using ModelSim. Listing E.13 shows the test bench, listing E.14
shows the ModelSim script file and Fig. 4.7 shows the result.
Fig. 4.7: Pulse FSM simulation in ModelSim that shows the eight clock cycle long
pulse.
4.3.1 Period-Doubling Route To Chaos
Example 4.3. Implement the R¨ossler period-doubling bifurcation from Sec. 4.2.1 on the
FPGA.
Solution: Listing E.15 shows the VHDL specification. We have included the entire design
specification instead of a snippet since we want the reader to understand the different steps
involved in implementing bifurcations on the FPGA.
The DSP builder Advanced Blockset design that uses subsystems (hierarchical design)
is shown in Figs 4.8 through 4.11.
90
4 Bifurcations
Fig. 4.8: Period-Doubling system top level.
Fig. 4.9: Period-Doubling nonlinear subsystem.
4.3 Bifurcation Experiments With an FPGA
Fig. 4.10: Period-Doubling synthesizable subsystem.
91
92
4 Bifurcations
Fig. 4.11: R¨ossler nonlinearity.
Fig 4.12 shows the result. Compare to Fig. 4.2. Note that the bifurcation parameter value(s) are
approximately (since we are using 32-bit floating point) equal to those in Fig. 4.2.
4.3 Bifurcation Experiments With an FPGA
93
Fig. 4.12: Period-doubling route to chaos in the R¨ossler system, as realized on the
FPGA. For the period-3 limit cycle and chaotic attractor, X and Y-axes scales are
0.5 V/div; for the period-6 limit cycle, the X-axis scale is 0.2 V/div and the Y-axis
scale is 0.5 V/div.
4.3.2 Period-Adding Route To Chaos
Example 4.4. Implement the Chua oscillator from Sec. 4.2.2 on the FPGA.
Solution: Listing E.16 shows the VHDL specification. We have again specified the full
design because there are subtle differences between VHDL specifications of the different
chaotic systems. It would be instructive to understand the reason for the differences. Nevertheless, we have not implemented the bifurcation mechanism in this example. This is left
as an exercise for the reader.
The DSP builder Advanced Blockset design that uses subsystems (hierarchical design)
is shown in Figs 4.13 through 4.16.
94
4 Bifurcations
Fig. 4.13: Period-Adding system top level.
Fig. 4.14: Period-Adding nonlinear subsystem.
4.3 Bifurcation Experiments With an FPGA
Fig. 4.15: Period-Adding synthesizable subsystem.
Fig 4.17 shows the result.
95
96
4 Bifurcations
Fig. 4.16: Period-Adding nonlinearity.
4.3.3 Quasi-periodic Route to Chaos
Example 4.5. Implement the quasi-periodic route to chaos (via torus-breakdown) from
Sec. 4.2.3 on the FPGA.
Solution: Listing E.17 shows the VHDL specification for the quasi-periodic route to chaos.
We have again left the bifurcation implementation as an exercise for the reader.
The DSP builder Advanced Blockset design that uses subsystems (hierarchical design) is shown in
Figs 4.18 through 4.21.
4.3 Bifurcation Experiments With an FPGA
97
4:4 Limit Cycle
0.2
0.15
0.15
0.1
0.1
0.05
0.05
x
x
3:3 Limit Cycle
0.2
0
−0.05
0
−0.05
−0.1
−0.1
−0.15
−0.15
−0.2
−0.8
−0.6
−0.4
y
−0.2
−0.2
−0.8
0
0.2
0.15
0.15
0.1
0.1
0.05
0.05
0
−0.05
y
−0.2
0
0
−0.05
−0.1
−0.1
−0.15
−0.15
−0.2
−0.8
−0.4
Chaos after 4:4 Limit Cycle
0.2
x
x
Chaos after 3:3 Limit Cycle
−0.6
−0.6
−0.4
y
−0.2
0
−0.2
−0.8
−0.6
−0.4
y
−0.2
0
Fig. 4.17: Period-adding route to chaos in the Chua oscillator, as realized on the
FPGA.
98
4 Bifurcations
Fig. 4.18: Torus-breakdown system top level.
Fig. 4.19: Torus-breakdown nonlinear subsystem.
4.3 Bifurcation Experiments With an FPGA
Fig. 4.20: Torus-breakdown synthesizable subsystem.
Fig 4.22 shows the result.
99
100
4 Bifurcations
Fig. 4.21: Torus-breakdown nonlinearity.
4.3.4 Intermittency Route To Chaos
Example 4.6. Implement the Intermittency route to chaos from Sec. 4.2.4 on the FPGA.
Solution: We have not shown the VHDL design since we are utilizing Chua’s oscillator.
The DSP builder Advanced Blockset design that uses subsystems (hierarchical design) is
shown in Figs 4.23 through 4.26.
4.3 Bifurcation Experiments With an FPGA
101
Two-torus
2.5
Period-8
3.5
3
2
2.5
2
x
x
1.5
1.5
1
1
0.5
0.5
0
0
−2.5
−2
−1.5
−1
−0.5
y
0
0.5
−0.5
−2.5
Period-15
3.5
−2
−1.5
−1
y
−0.5
0
0.5
Chaos
4
3
3
2.5
2
x
x
2
1.5
1
1
0.5
0
0
−1
−0.5
−1
−2.5
−2
−1.5
−1
y
−0.5
0
0.5
−2
−3
−2
−1
0
y
1
2
Fig. 4.22: Torus-breakdown route to chaos, as realized on the FPGA.
3
102
4 Bifurcations
Fig. 4.23: Intermittency system top level.
Fig. 4.24: Intermittency nonlinear subsystem.
4.3 Bifurcation Experiments With an FPGA
Fig. 4.25: Intermittency synthesizable subsystem.
Fig 4.27 shows the result.
103
104
4 Bifurcations
Fig. 4.26: Intermittency nonlinearity.
4.3.5 Chaotic Transients and Crisis
Example 4.7. Implement the chaotic transient behaviour from Sec. 4.2.5 on the FPGA.
Solution: Listing E.18 shows the VHDL specification (bifurcation subsystem left as an exercise) for implementing chaotic transient behaviour. The DSP builder Advanced Blockset
design that uses subsystems (hierarchical design) is shown in Figs 4.28 through 4.31.
4.3 Bifurcation Experiments With an FPGA
105
Limit Cycle(s)
Limit Cycle(s) (time-domain)
3
1.5
1
2
0.5
z
x
1
0
0
−0.5
−1
−2
−0.3
−1
−0.2
−0.1
y
0
0.1
−1.5
740
0.2
750
760
t
770
780
790
Intermittency Chaos (time-domain)
Intermittency
0.4
1.5
0.3
1
0.2
0.1
y
x
0.5
0
0
−0.1
−0.5
−0.2
−1
−1.5
−3
−0.3
−2
−1
0
z
1
2
−0.4
740
3
750
760
t
770
780
790
Intermittency Chaos (time-domain)
Intermittency
0.4
1.5
0.3
1
0.2
0.1
y
x
0.5
0
0
−0.1
−0.5
−0.2
−1
−1.5
−2.5
−0.3
−2
−1.5
−1
z
−0.5
0
−0.4
740
0.5
750
760
t
770
780
790
Intermittency Chaos (time-domain)
Intermittency
0.5
1.5
0.4
1
0.3
0.5
y
x
0.2
0
0.1
−0.5
0
−1
−1.5
−0.5
−0.1
0
0.5
1
z
1.5
2
2.5
−0.2
740
750
760
t
770
780
790
Fig. 4.27: Intermittency route to chaos, as realized on the FPGA.
106
4 Bifurcations
Fig. 4.28: DSP builder top level for investigating chaotic transients.
Fig. 4.29: DSP builder nonlinear subsystem for investigating chaotic transients.
4.3 Bifurcation Experiments With an FPGA
107
Fig. 4.30: DSP builder synthesizable subsystem for investigating chaotic transients.
Fig 4.32 shows the result.
108
4 Bifurcations
Fig. 4.31: DSP builder nonlinear for implementing chaotic transients.
4.4 Conclusions
In this chapter, we studied bifurcations. In particular:
1. We understood bifurcations as a change in system behaviour when a parameter is varied.
2. We used the concept of bifurcations to study a variety of routes to chaos including perioddoubling, period-adding, torus-breakdown, intermittency and chaotic transients.
3. We utilized single pulse generator to implement bifurcation mechanism on the FPGA.
This chapter has only scratched the surface of bifurcation phenomenon. Entire books have been
written on this subject. The interested reader should pursue this topic further.
So far in this book, we have learned how to implement chaotic ODEs on an FPGA. In the
concluding chapter to this volume, we will exercise the robustness of an FPGA by realizing chaotic
DDEs. FPGA realization of DDEs is possible nowadays because of the copious amounts of on-chip
memory.
Problems
4.1. Consider the Langford System, shown in Eqs.(4.26) through (4.28). These equations can be
used to describe the motion of turbulent flow in a fluid [1].
x˙ = xz − ω y
(4.26)
y˙ = ω x + xy
(4.27)
1
z˙ = p + z − z3 − (x2 + y2 )(1 + qx + ε x)
3
(4.28)
4.4 Conclusions
109
Limit Cycle
0.9
Chaos
1.2
0.8
1.1
0.7
1
0.6
0.9
P
C
0.5
0.4
0.8
0.3
0.7
0.2
0.6
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.1
0.5
0.15
0.2
R
0.3
0.35
P population decays
P time series
1.4
0.25
R
0.14
1
0.1
0.8
0.08
P
0.12
P
1.2
0.6
0.06
0.4
0.04
0.2
0.02
0
0
100
200
t
300
400
500
0
0
100
200
t
300
400
500
Fig. 4.32: Chaotic transients for ecology model, as realized on the FPGA.
First, compute the equilibrium points for the system. Now consider the following typical system
parameters: p = 1.1, q = 0.7 and ε = 0.5. Investigate the route to chaos in this system as a function
of parameter ω . In other words, obtain a bifurcation diagram. Implement your design on the FPGA.
4.2. Investigate the route(s) to chaos in the Lorenz system.
4.3. Read [9] and obtain the period-doubling route to chaos in Eqs.(4.8), (4.9) and (4.10)
4.4. Repeat problem 4.3 but for the period-adding route.
4.5. Parameterize the pulseFSM in listing E.12 using generics. This will allow us to utilize the
pulseFSM for other modules that require different delays.
4.6. We can also examine limit cycles with high periods (such as period-16) on the FPGA as
opposed to an analog realization, due to noise immunity on the FPGA. Try to obtain high period
limit cycles in any of the system(s) (say R¨ossler system) from this chapter.
4.7. Perform an In-system verification using SignalTap, of the period-doubling route to chaos for
the R¨ossler system.
4.8. Investigate the route to chaos as a function of parameterκ , in the optically injected laser system
in Eqs.(4.29) through (4.31) [5]. Use α = 2.5, β = 0.015, Γ = 0.05, ω = 2.
110
4 Bifurcations
x1 x3 α
− x2 x3 + ω x2
2
2
α
x2 x3
x˙2 = −ω x1 + x1 x3 +
2
2
x˙3 = −2Γ x3 − (1 + 2β x3 )(x12 + x22 − 1)
x˙1 = κ +
(4.29)
(4.30)
(4.31)
Lab 4 : Displaying Bifurcation Parameter(s) on the LCD
Objective: Implement a display module for bifurcation parameter(s).
Lab Exercise:
You should have realized from the design(s) in this chapter that simply pressing the key and mentally keeping track of the increment or decrement of the bifurcation parameter is cumbersome.
Hence, utilize the solution from Lab 2.5 to display the current value of the bifurcation parameter
on the LCD display. You can of course display any additional information or even interface to an
external monitor using VGA.
References
1. Buscarino, A. et. al. (2014) A Concise Guide to Chaotic Electronic Circuits. Springer-Verlag,
Berlin
2. Lakshmanan, M. and Rajasekar, S. (2003) Nonlinear Dynamics - Integrability, Chaos and
Patterns. Springer-Verlag, Berlin
3. Albers, D. J. and Sprott, J. C. (2006) Routes to chaos in high-dimensional dynamical systems:
A qualitative numerical study. Physica D, 223, pp. 194-207
4. Ambelang, S. (2011) Four Routes to Chaos: Chua’s Oscillator with a Cubic Nonlinearity.
Final Project Report, EE4060 Spring 2011. Electrical Engineering and Computer Sciences
Department, Milwaukee School of Engineering
5. Banerjee, S., Saha, P. and Chowdhury, A. R. (2004) Optically Injected Laser System: Characterization of Chaos, Bifurcation and Control. Chaos, 14(2), pp. 347-357
6. Chua, L. O., Wah, C. W., Huang, A. and Zhong, G. (1993) A Universal Circuit for Studying
and Generating Chaos - Part I : Routes to Chaos. IEEE Transactions on Circuits and Systems,
40(10), pp. 732-744
7. Dhamala, M. and Lai, Y-C. (1999) Controlling transient chaos in deterministic flows with
applications to electrical power systems and ecology. Physical Review E, Vol. 59(2), pp. 16461655
8. Kevorkian, P. (1993) Snapshots of Dynamical Evolution of Attractors from Chua’s Oscillator. IEEE Transactions on Circuits and Systems - I : Fundamental Theory and Applications,
40(10), pp. 762-780
9. Matsumoto, T., Chua, L. O. and Tokunaga, R. (1987) Chaos via Torus Breakdown. IEEE
Transactions on Circuits and Systems, CAS-34(3), pp. 240-253
10. . Pivka, L., Wu, C. W. and Huang, A. (1994) Chua’s Oscillator : A Compendium of Chaotic
Phenomena. Journal of the Franklin Institute, 331(6), pp. 705-741
Chapter 5
Chaotic DDEs : FPGA Examples and
Synchronization Applications
Valli et. al. Synchronization in Coupled
Ikeda Delay Systems : Experimental
Observations using FPGAs [7]
Abstract This chapter explores particular advantage(s) of FPGAs for investigating nonlinear dynamics - realization of time delayed chaotic systems. These advantages are the availability of onchip memory and the fact that generate statements in VHDL can be used to elegantly implement
arbitrary (limited by on-chip memory and the number of FPGA logic elements) length delay chains.
We will also explore synchronization applications in chaotic DDEs using the FPGA.
5.1 An Introduction to Time Delay Systems
Time delay is inherent in many physical systems and could be caused by (for example) lag between
the sensing of disturbance and the triggering of an appropriate response [7]. Differential equations
can be used to model time-delay systems and the general model that we will use in this chapter [5]
is given in Eq.(5.1).
x˙ = f(t, x(t), x(t − τi ))
(5.1)
△
In Eq.(5.1), x = (x1 (t), x2 (t), · · · , xn (t))T and τi > 0, i = 1, 2, · · · , n are lag times or delay times.
f is a vector valued continuous function.
We will utilize the forward-Euler’s method (recall Sec. 3.1) for specifying the DDE, refer to
Eq.(5.2).
x(t + δ t) = x(t) + f(x(t), x(t − Ni ))∆ t
(5.2)
In Eq.(5.2), we have slightly abused our notation and have used continuous time t whereas the
equation is actually discrete. Nevertheless, the advantage of an FPGA becomes apparent when
realizing the delay(s) Ni . But let us first simulate DDEs in Simulink.
5.2 Simulating DDEs in Simulink
A general simulation block diagram is shown in Fig. 5.1. Example 1 shows how to adapt the block
diagram in Fig. 5.1 to a particular chaotic DDE.
111
112
5 Chaotic DDEs : FPGA Examples and Synchronization Applications
x˙
f (x, x(t − Ni ))
x
KTs
z−1
z −Ni
Fig. 5.1: Simulating a DDE in Simulink, block diagram adopted from [7]. We
utilize the discrete-time integrator but inherit the sample time from the fixed-point
simulation period.
Example 5.1. Simulate the Ikeda DDE [4] in Simulink.
x˙ = µ sin(x(t − τ )) − α x(t)
(5.3)
µ = 6, τ = 1, α = 1.
Solution: Fig. 5.2 shows the Ikeda DDE simulation block diagram. Phase plot is shown in
Fig. 5.3.
Fig. 5.2: Simulink block diagram for simulating the Ikeda DDE. Fixed-step Euler’s
method was used with a step size 0.001.
5.3 FPGA Realization of DDEs
113
Fig. 5.3: Ikeda DDE simulation result. y-axis is x(t − 1), x-axis is x(t).
Fig. 5.1 implies that DDEs can be realized on an FPGA quite easily, once the delay has been
specified. The subject of FPGA realization is the topic of the next section.
5.3 FPGA Realization of DDEs
In order to implement the delay on an FPGA, we will need the definition in Eq.(5.4) [5].
△
∆t =
τi
Ni − 1
(5.4)
Based on Eq.(5.4), we can utilize the for statement (refer to listing C.1) to let the synthesizer
infer the number of flip-flops required for the delay.
Line 22 in listing F.2 declares the internal delay lines to be 32 bits wide. However, we need
an array of these internal delay lines and hence we have declared it as ”memory”. Thus, we are
specifying a tapped delay line in VHDL.
Fig. 5.4 is the block diagram for FPGA realization of DDEs.
We can infer from Fig. 5.4 that the only modification to our already existing FPGA realization
of chaotic systems (starting from Chapter 3) is the delay realization using VHDL from listing F.1
and F.2. In Fig. 5.4, the clock divider block is configured to divide the global clock (usually obtained from the FPGA board clock) so propagation delays associated with the various sub-modules
(such as the shift register) can be accommodated. Hence the clock divider output clock (with frequency fEuler = δ1t ) is used as clock input for the shift register and the D flip-flop synchronizer.
Since the overall design is synchronous, all sequential logic components have a well-defined reset
state. xN (x(t + δ t)) and x(t − Ni ) also serve as inputs to the audio codec DAC.
We will now discuss examples of FPGA realization of DDEs.
Example 5.2. Implement the Ikeda DDE from Example 5.2 on the DE2.
Solution: In order to implement the Ikeda DDE, we will simply utilize the D flip-flop (with
async reset) and the addressable shift register from listings F.1 and F.2 resp. Listing F.3
shows the complete VHDL Ikeda module.
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5 Chaotic DDEs : FPGA Examples and Synchronization Applications
reset
reset
reset
reset
xNNew
f(x(t), x(t − Ni ))
X
+
D
Q
xN
∆t
Global
clock
reset
reset
Global clock
Shift Register
x(t − Ni )
Clock
Divider
fEuler =
1
δt
Fig. 5.4: Hardware block diagram for specifying DDEs, using forward-Euler
method [7]. Note that one could specify more advanced integration methods such
as Runge-Kutta. The block diagram utilizes a combination of DSP Builder
Advanced Block Set (blocks highlighted in yellow ) and VHDL. The shift register
is obviously unnecessary for non-delay systems and thus the block diagram
specifies how we can implement nonlinear ODEs on FPGAs.
Please refer to the online video and reference design on the companion website: http://www
.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/ReferenceDesigns
/volumeI-ExperimentalObservations/chapter5/ikedaDDE/ for further details
on the Ikeda DDE. Nevertheless, we have shown all the DSP builder subsystems (similar to Chapter 4) in Figs. 5.5 through 5.8.
5.3 FPGA Realization of DDEs
Fig. 5.5: Ikeda system top level.
Fig. 5.6: Ikeda nonlinear subsystem.
115
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5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Fig. 5.7: Ikeda synthesizable subsystem.
Fig 5.9 shows the result.
5.3 FPGA Realization of DDEs
117
Fig. 5.8: Ikeda nonlinearity.
Example 5.3. Implement the Sigmoidal DDE in Eq.(5.5) on the FPGA.
x˙ = 2tanh(x(t − τ )) − x(t − τ )
(5.5)
Use τ = 3.
Solution: Although DSP builder advanced blockset does not have a hyperbolic tangent
function, recall from Sec. 3.7 that the hyperbolic tangent can be written in terms of exponential functions, refer to Eq.(5.6).
tanh(x) =
ex − e−x
ex + e−x
(5.6)
We can thus implement the sigmoidal DDE since the exponential function is available in
DSP builder advanced blockset. Listing F.4 shows the complete VHDL specification for the
sigmoidal DDE.
Figs. 5.10 through 5.13 show the DSP builder design.
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5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Fig. 5.9: x(t − τ ) vs. x(t) for the Ikeda DDE, implemented on the DE2.
Oscilloscope scales are 0.5 V/div for both axis.
5.3 FPGA Realization of DDEs
Fig. 5.10: Sigmoid DDE DSP builder system top level.
Fig. 5.11: Sigmoid DDE DSP builder nonlinear subsystem.
119
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5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Fig. 5.12: Sigmoid DDE DSP builder synthesizable subsystem.
Fig 5.14 shows the result.
5.4 Applications of (Time Delayed) Chaotic Systems - Synchronization
121
Fig. 5.13: Sigmoid DSP builder nonlinearity.
Example 5.4. Implement the Signum DDE in Eq.(5.7) on the FPGA.
x˙ = sgn(x(t − τ )) − x(t − τ )
(5.7)
Use τ = 2.
Solution: Listing F.5 shows the complete VHDL specification for the signum DDE. Note
that we do not use DSP builder advanced block set for the nonlinearity, since it is so trivial
to implement.
Fig 5.15 shows the result.
5.4 Applications of (Time Delayed) Chaotic Systems Synchronization
In Sec. 1.1.2, we briefly touched upon the topic of synchronization. In this section, we will expand
upon this topic further. We will briefly discuss the concept of synchronization first and then show
examples of synchronization in chaotic DDEs. One of the reasons why we focus on DDEs is
because they are infinite dimensional [5]. Hence they are more attractive to applications such as
secure communications, compared to chaotic systems without delay [5].
A surprising property of chaotic attractors is their susceptibility to synchronization [2]. This
refers to the tendency of two or more systems that are coupled together to undergo closely related motions, even if the motions are chaotic. This property is surprising because it was believed
122
5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Fig. 5.14: x(t − τ ) vs. x(t) for the Sigmoid DDE, implemented on the DE2.
Oscilloscope scales are 0.1 V/div for X-axis and 1 V/div for Y-axis.
that chaotic synchronization was not feasible because of the hallmark property of chaos: sensitive dependence on initial conditions [5]. Hence chaotic systems intrinsically defy synchronization
because even two identical systems starting from very slightly different initial conditions would
evolve in time in an unsynchronized manner (the differences in state would grow exponentially).
Nevertheless it has been shown that it is possible to synchronize chaotic systems [2] [5], to make
them evolve on the same trajectory, by introducing appropriate coupling between them due to the
works of Pecora and Carroll and the earlier works of Fujisaka and Yamada [5].
Chaos synchronization has been receiving a great deal of interest for more than two decades in
view of its potential applications in various fields of science and engineering [5]. There are a variety
of synchronization mechanisms that have been proposed: complete or identical synchronization,
phase synchronization, almost synchronization, episodic synchronization - are a few [5]. A detailed
discussion of synchronization mechanisms is obviously beyond the scope of this chapter or this
book. We will however give an example of chaotic DDE synchronization on FPGAs using the
Ikeda DDE [7].
Complete synchronization is the simplest type of synchronization that is characterized by perfect follow-up of two chaotic trajectories. Synchronization is achieved by means of a coupling
factor. We consider linearly coupled Ikeda systems as the drive and response systems, described
by Eq.(5.8) and Eq.(5.9) respectively.
x˙ = −α x + µ sin x(t − τ )
(5.8)
5.4 Applications of (Time Delayed) Chaotic Systems - Synchronization
123
Fig. 5.15: x(t − τ ) vs. x(t) for the Signum DDE, implemented on the DE2.
Oscilloscope scales are 0.1 V/div for X-axis and 1 V/div for Y-axis.
y˙ = −α y + µ sin y(t − τ ) + k(t)(x − y)
(5.9)
k(t) is the coupling factor between drive and response system. In the following subsections, we
illustrate complete synchronization using unidirectional and bidirectional coupling via the FPGA.
The parameters are taken as µ = 20, α = 5, τ = 1. Figure 5.16 shows the analog output from
Eq.(5.3), with the parameters for synchronization.
5.4.1 Unidirectional Coupling
In unidirectional coupling, the drive system is free to evolve and the response system is influenced
by the coupling factor k(t). Due to this, the dynamical evolution of the response system is to follow
the dynamics of the drive system in the course of time. We investigated chaos synchronization in
unidirectionally coupled Ikeda systems with two types of coupling factors. In the first type, k(t) is
a square wave coupling represented by
(t0 , k1 ), (t1 , k2 ), (t2 , k1 ), (t3 , k2 ).......
(5.10)
where t j = t0 + ( j − 1)τ , j ≥ 1 with k1 6= k2 . It is observed that the amplitude of the control
parameter k(t) is the key factor to achieve synchronization between drive and response, larger the
amplitude quicker the convergence into synchronization, provided that the conditional Lyapunov
exponents of the response systems are all negative. The threshold value is chosen as k1 = 0 and
k2 = 50 for square wave coupling. We also used the second type of coupling factor defined in
Eq.(5.11).
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5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Fig. 5.16: x(t − τ ) (Y-input) vs. x(t) (X-input) displayed on an oscilloscope for the
Ikeda attractor with parameters for synchronization experiments. Scales for both
channels are 0.2 V/div.
k(t) = −α + 2µ | cos(y(t − τ ))|
(5.11)
5.4.2 Bidirectional Coupling
In bidirectional coupling, both drive and response systems are coupled with each other by a coupling factor k(t) that induces mutual synchronization. For this bidirectional coupling, the drive
(Eq.(5.12)) and response (Eq.(5.13)) systems are considered as
x˙ = −α x + µ sin x(t − τ ) + k(t)(y − x)
(5.12)
y˙ = −α y + µ sin y(t − τ ) + k(t)(x − y)
(5.13)
The synchronization error is computed by e(t) = x(t) − y(t), which is the measure for convergence of two chaotic trajectories. Figures 5.17 through 5.20 show results from the analog output
synchronization experiment. In order to generate the analog output, we simply passed x(t) − y(t)
into a DAC channel. It is observed that the synchronization is quicker in bidirectional coupling
compared to the unidirectional coupling for the same parameters.
In order to shed more light on synchronization, we have used the analog oscilloscope to obtain
X-Y plots where X is x(t) (drive) and Y is y(t) (response). Figure 5.21 first shows the X-Y plot
when the drive and response systems are not synchronized. The X-Y plots as a result of synchronization are shown in figures 5.22 through 5.25.
5.5 Conclusions
125
Fig. 5.17: Synchronization error for unidirectional square wave coupling. Vertical
scale is 200 mV/div., horizontal scale is 200 µ s/div.
Fig. 5.18: Synchronization error for unidirectional cosine function based coupling.
Vertical scale is 200 mV/div., horizontal scale is 100 µ s/div.
Listing F.6 shows one possible approach for implementing synchronization schemes on an
FPGA. The top level is shown in listing F.7 so that we may fully understand the design.
5.5 Conclusions
In this chapter, we understood that chaotic DDEs can be realized on FPGAs using tapped delay
lines. We also studied an application of chaotic systems (on FPGAs) to synchronization. DDEs
are particularly suited for synchronization and secure communication applications because of their
infinite dimensionality.
Applications aside, we hope you had fun understanding that FPGAs are robust physical platforms for realizing nonlinear (chaotic) ODEs. In a followup volume, we will examine theoretical
126
5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Fig. 5.19: Synchronization error for bidirectional square wave coupling. Vertical
scale is 200 mV/div., horizontal scale is 2.00 µ s/div.
Fig. 5.20: Synchronization error for bidirectional cosine function based coupling.
Vertical scale is 200 mV/div., horizontal scale is 100 µ s/div.
methods to rigorously understand the implications of sampling and quantization on the underlying
system behaviour.
Acknowledgements Many thanks to our colleagues at the Vellore Institute of Technology, Vellore, India for working with us on the synchronization experiments. Specifically, Ph.D. candidate
Ms. Valli, Professors Ganesan and Subramanian have been extremely helpful.
Problems
5.1. Consider the Ikeda DDE:
x˙ = µ sin(x(t − τ )) − α x(t)
(5.14)
5.5 Conclusions
127
Fig. 5.21: The fact that the drive and response systems are not synchronized and
the outputs are analog waveforms is an experimental evidence of ”sensitive
dependence on initial conditions”, one of the hallmarks of chaotic systems.
Although the FPGA Ikeda DDE drive and response systems are both digital
specifications, the output waveform is analog. Thus any noise on the analog line is
going to ensure that the drive and response systems do not have the same initial
conditions and this leads to the X-Y plot shown.
Fig. 5.22: XY plot for unidirectional square wave coupling. Vertical and horizontal
scales are 200 mV/div.
µ = 6, τ = 1, α = 1.
Perform a ModelSim simulation of the system above.
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5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Fig. 5.23: XY plot for unidirectional cosine function based coupling. Vertical and
horizontal scales are 200 mV/div.
Fig. 5.24: XY plot for bidirectional square wave coupling. Vertical and horizontal
scales are 200 mV/div.
5.2. One approach to speed up the synthesis procedure is to minimize the number of delays by
increasing the sampling frequency of the system. Explore this approach by increasing the sampling
frequency for, say, the Ikeda system.
5.3. One of the earliest and most widely studied DDE is the Mackey-Glass equation [6], shown in
Eq.(5.15).
x˙ =
ax(t − τ )
− bx(t)
1 + x(t − τ )c
Parameters for chaos: a = 3, b = 1, c = 7, τ = 3 [6]. Implement the equation on the FPGA.
(5.15)
5.5 Conclusions
129
Fig. 5.25: XY plot for bidirectional cosine function based coupling. Vertical and
horizontal scales are 200 mV/div.
5.4. Implement the antisymmetric piecewise-linear DDE [6], shown in Eq.(5.16) on the FPGA.
Use τ = 3.
x˙ = |x(t − τ ) + 1| − |x(t − τ ) − 1| − x(t − τ )
(5.16)
5.5. Implement the asymmetric piecewise-linear DDE [6], shown in Eq.(5.17) on the FPGA. Use
τ = 1.8.
x˙ = x(t − τ ) − 2|x(t − τ )| + 1
(5.17)
5.6. Explore the synchronization schemes discussed in Sec. 5.4 using the DDEs from problems 5.3
through 5.5.
5.7. Consider Eq.(5.18 [6].
x˙ =
1
τ
Z τ
0
x(t − s)(4 − |x(t − s)|)ds
(5.18)
In Eq.(5.18), the time derivative depends on the average value of a function for time lags of xs from
s = 0 to τ . Implement the equation on an FPGA, using τ = 3.
5.8. Investigate bifurcation mechanisms in any of the DDEs from this chapter.
Lab 5 : The Lang-Kobayashi Chaotic Delay Differential
Equation
Objective: Simulate and physically realize the Lang-Kobayashi (L-K) chaotic DDE [3]
dE
= −(1 + iα )|E|2 E + η1 E(t − τ1 ) + η2 E(t − τ2 )
dt
(5.19)
130
5 Chaotic DDEs : FPGA Examples and Synchronization Applications
Theory:
Notice that Eq.(5.19) is in the complex domain. However we can separate the real and imaginary
parts by writing E(t) = ρ (t)eiθ (t) in Eq.(5.19) to obtain Eqs.(5.20) and (5.21).
dρ
= −ρ 3 + η1 ρ (t − τ1 ) cos(θ (t) − θ (t − τ1 )) + η2 ρ (t − τ2 ) cos(θ (t) − θ (t − τ2 ))
dt
dθ
= −αρ 3 + η1 ρ (t − τ1 ) sin(θ (t) − θ (t − τ1 )) + η2 ρ (t − τ2 ) sin(θ (t) − θ (t − τ2 ))
ρ
dt
(5.20)
(5.21)
Verify that one can indeed obtain Eqs.(5.20) and (5.21) from Eq.(5.19).
Lab Exercise:
1. Simulate (using Simulink and Modelsim), verify using SignalTap and hence implement Eqs.
(5.20) and (5.21) for the following parameters α = 4, η1 = 3.5, η2 = 3, τ1 = 2.5, τ2 = 0.1.
2. Study synchronization mechanisms in the L-K DDE using the ideas from Sec. 5.4.
References
1. Wolfson WM8731 datasheet, Available via DIALOG.
http://www.wolfsonmicro.com/products/audio_hubs/WM8731/ Cited 4
October 2013
2. Alligood, K. T., Sauer, T. D. and Yorke, J. A. (2010) Chaos : An Introduction to Dynamical
Systems. Springer, corrected edition, New York
3. Banerjee, S. and Ariffin, M. R. K. (2013) Noise Induced Synchronization of Time-Delayed
Semiconductor Lasers and Authentication Based Asymmetric Encryption. Optics and Laser
Technology. Vol. 45, pp. 435-442
4. Ikeda, K., Daido, H.and Akimoto, O. (1980) Optical Turbulence: Chaotic Behavior of Transmitted Light from a Ring Cavity. Phys. Rev. Lett. (45): 709
5. Lakshmanan, M. and Senthilkumar, D. V. (2011) Dynamics of Nonlinear Time-Delay Systems. Springer Series in Synergetics, New York
6. Sprott, J. C. (2010) Elegant Chaos. World Scientific
7. Valli, D. et. al. (2014) Synchronization in Coupled Ikeda Delay Differential Equations : Experimental Observations using Field Programmable Gate Arrays. Eur Phys. J. Special Topics,
pp. 1-15, DOI: 10.1140/epjst/e2014-02144-8
Appendix A
Introduction to MATLAB and Simulink
In this appendix, we will discuss MATLAB and Simulink. Note that we will only cover aspects of
MATLAB and Simulink that are useful for simulating nonlinear differential equations. MATLAB is
an acronym for MATrix LABoratory and is a product of the MathWorks corporation [1]. Simulink
is a graphical front end to MATLAB. This appendix assumes you have MATLAB version 7.1
(R14) installed (with default options). Note that any version of MATLAB later than 7.1 should
work although there may be slight differences between your version of MATLAB and the version
used in this appendix.
Note our approach is not the only procedure for simulating differential equations. The reader is
encouraged to independently explore other methods on their own.
A.1 Simulating Nonlinear Differential Equations in MATLAB
A.1.1 Starting MATLAB
First, start MATLAB by left-clicking on the MATLAB icon . Fig. A.1.1 should appear. Some
of the windows maybe disabled by default. Make sure that Window → Command History and
Window → Workspace are enabled. These windows enable you to quickly retype a previous command and check MATLAB’s memory usage respectively.
The online help system in MATLAB is extensive. If you are unfamiliar with MATLAB, you
should understand the basics of MATLAB before proceeding further. Press ”F1” on your keyboard
to bring up the MATLAB help window, a portion of which is shown in Fig. A.1.2. You should go
through the ”Getting Started” section and as many sections as necessary to understand MATLAB.
A.1.2 Simulating a One Dimensional System in MATLAB
Consider the following one dimensional dynamical system
x˙ = sin x, x(0) =
π
2
(A.1)
131
132
A Introduction to MATLAB and Simulink
Fig. A.1.1: The startup screen in MATLAB, the command prompt is indicated by
”>>”.
Fig. A.1.2: The MATLAB help window.
The code required to simulate the system is shown below. The MATLAB comments should make
the code self-explanatory. Note that you should liberally comment your code to improve readability. While labeling the plot of our solution, we have used MATLAB’s ability to interpret
LATEXcommands for improved readability. For more information, type ”help latex” at the MATLAB command prompt.
1
% Lines starting with a % are comment.
A.1 Simulating Nonlinear Differential Equations in MATLAB
2
3
4
5
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133
% MATLAB code for simulating a one dimensional nonlinear
% dynamical system
% Muthuswamy, Bharathwaj
% The lines below instruct MATLAB to clear all workspace variables
% (or memory). It is a good idea to start your simulation from a
% clean MATLAB state in order to eliminate the side-effects caused
% by unused variables. The semicolon at the end of a line
% supresses echo to the MATLAB command line.
clear all;
close all;
% The line below defines our system via the "inline" MATLAB
% command. The first argument is our system. The second
% argument defines the independent variable (time) and the
% third argument defines the array "y" for our dependent
% variable. Thus y(1) = x(t).
sinusoidalSystem = inline('[sin(y(1))]','t','y');
% We setup tolerance options for the Ordinary Differential
% Equation (ODE) solver.
% The values below suffice for our systems.
options = odeset('RelTol',1e-7,'AbsTol',1e-7);
% The line below invokes the medium order ode45 solver,
% we will use this solver for our systems. The first argument
% is the system to be solved.
% The second argument is a matrix with start and stop times.
% The third argument specifies the initial conditions and
% the fourth argument uses the options specified previously.
[t,ya] = ode45(sinusoidalSystem,[0,100],[pi/2],options);
% plot the solution. The first argument to the plot
% command is the x-axis variable and the second argument
% is the y-axis variable.
plot(t,ya(:,1));
% Label axis with units. Then title the plot.
% Note that we use a Latex interpreter.
xlabel('$t$ (seconds)','FontSize',14,'Interpreter','Latex');
ylabel('$x(t)$','FontSize',14,'Interpreter','Latex');
title('Solution of $\dot{x} = \sin(x),x(0)=\frac{\pi}{2}$','Interpreter','Latex');
The reader is encouraged to use script files (or M-files in MATLAB terminology) to enter your
commands so you can save them for reuse in a later MATLAB session. To create an M-file and
enter the commands above, go to File → New → M − File. Enter the commands above and save
the file as ”oneDimensionalSimulation.m”. The result is shown in Fig. A.1.3. You can run the file
by typing the filename in the MATLAB command prompt and pressing enter.
We have already seen how to simulate a chaotic system in MATLAB (the Lorenz system in
Chapter 1). Let us now understand how to use Simulink, the graphical front-end to MATLAB.
134
A Introduction to MATLAB and Simulink
Fig. A.1.3: The result of simulating our one dimensional system.
A.2 Simulating Nonlinear Differential Equations in Simulink
In this section, we will show you how to simulate nonlinear differential equations using Simulink.
This tool offers a more visual approach to the differential equation setup.
A.2.1 Starting Simulink
in the
First, start Simulink by left-clicking on the Simulink icon
MATLAB tool bar. Fig. A.2.1 should pop up.
The Simulink library browser contains a plethora of components. We will restrict ourselves to
the Integrator block (highlighted in Fig. A.2.1) under the Continuous Library and various blocks
in the Math Operations, User − Defined Functions, Sinks and Sources library.
A.2 Simulating Nonlinear Differential Equations in Simulink
135
Fig. A.2.1: Simulink Library Browser.
A.2.2 Simulating a One Dimensional System in Simulink
We will simulate the system shown below.
x˙ = e−x − cos(x), x(0) = 0.1
(A.2)
First open a new model in Simulink by left-clicking File → New → Model
Fig. A.2.2 shows the system represented in Simulink. In order to construct this system, follow
the steps below.
1. Place an Integrator block from the Continuous Library by left-clicking the block and dragging
it into your model. Double-click the block and set the initial condition to 0.1
2. Next place a Fcn block from the User − Defined Functions library.
3. Double-click the Fcn block and enter ”exp(-u)-cos(u)”. Notice that ”u” is the input variable.
4. Drag and place a Scope block from the Sinks library.
5. Connect all the components as shown inFig. A.2.2 by left-clicking and dragging a wire connection.
6. Double-click anywhere in the model to add comments. Make sure you add a comment indicating the system you are simulating and also label wires, as shown in Fig. A.2.2.
136
A Introduction to MATLAB and Simulink
Fig. A.2.2: The one dimensional system x˙ = e−x − cos(x), x(0) = 0.1 in Simulink.
in the Simulink toolbar. The
To simulate the system, left-click the Play button
default options are sufficient for the models in this book. You can increase the simulation time
appropriately, for this differential equation, 10 seconds is sufficient.
The result should be Fig. A.2.3. Note that you cannot unfortunately name the axes and title the
plot. The colors have been inverted for printing purposes.
Fig. A.2.3: Result of simulating our system.
A.3 Conclusion
137
A.2.3 Simulating a Chaotic System in Simulink
Now we will simulate the Sprott system shown below.
...
x + x¨ + x + f (x)
˙ =0
(A.3)
f (x)
˙ = sign(1 + 4x)
˙
(A.4)
The nonlinear function is given by:
Here sign(x) is the signum function given by:

 −1 when x < 0,
sign(x) = 0 when x = 0,

1 when x > 0.
The Simulink model of our system is shown in Fig. A.2.4. Simulating our system for 100
seconds, the result should be Fig. A.2.5.
Fig. A.2.4: Simulating the Sprott System in Simulink.
The Sum block can be found in Math Operations library. The Sprott Nonlinear System is an
XY Scope from the Sinks library. The initial conditions are x(0) = −0.5, y(0) = z(0) = 0. sgn is
used with the Fcn block under the User − Defined Functions library.
A.3 Conclusion
In this appendix we showed you how to simulate nonlinear differential equations in MATLAB and
Simulink.
138
A Introduction to MATLAB and Simulink
Fig. A.2.5: Results of Simulating the Sprott System.
The reader may have noticed that we are simulating a sensitive system on a finite state machine
(computer). How can we be even confident that our simulation is correct? It turns out that the
concept of ”shadowing” can be used to justify numerical simulation of chaotic systems1 . For more
information, please refer to the upcoming volume II on theoretical methods.
References
1. The Mathworks Corporation. Available via DIALOG.
http://www.mathworks.com Cited 25 December 2012
1
We cannot invoke the Nyquist-Shannon sampling theorem to determine a sampling frequency
since our system is not bandlimited.
Appendix B
Chapter 1 MATLAB Code
B.1 The Lorenz System
Listing B.1: MATLAB code for Lorenz equations
1
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3
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% Lines starting with % are comments in MATLAB.
% Extensively comment your code!
% Purpose of this code: Obtaining phase plots and time-domain
% waveforms for Lorenz system.
%
% The lines below instruct MATLAB to clear all workspace
% variables (or memory). It is a good idea to start your
% simulation from a clean MATLAB state in order to eliminate
% the side-effects caused by unused variables. The semicolon
% at the end of a line will supress echo to the MATLAB command
% line.
clear all;
close all;
% The line below defines our system via the "inline" MATLAB
% command. The first argument is our system. Since our system
% is three dimensional, we have a 3 x 1 matrix for our system.
% The second argument defines the independent variable (time)
% and the third argument defines the array "y" for our dependent
% variable. Thus y(1) = x(t),y(2) = y(t) and y(3) = z(t).
lorenz = inline('[-10*y(1)+10*y(2);-y(1)*y(3)+28*y(1)-y(2);y(1)*y
(2)-(8/3)*y(3)]','t','y');
% We setup tolerance options for the Ordinary Differential
% Equation (ODE) solver. The values below suffice for our
% systems.
options = odeset('RelTol',1e-7,'AbsTol',1e-7);
% The line below invokes the medium order ode45 solver, we will
% use this solver for our systems. The first argument is the
% system to be solved. The second argument is a matrix with
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% start and stop times. The third argument specifies the initial
% conditions and the fourth argument uses the options specified
% in the line above.
% You should use initial conditions very close to the equilibrium
% points.
h1=figure;
[t,ya] = ode45(lorenz,[0,100],[10,20,30],options);
% classic view of lorenz butterfly
% the first argument is the x-value to be plotted
% the second argument is the y-value
plot(ya(:,1),ya(:,3));
% clearly label your axes!
xlabel('$x$','Interpreter','LaTeX','FontSize',32);
ylabel('$z$','Interpreter','LaTeX','FontSize',32);
% uncomment line belwo for EPS output
% print(h1,'-depsc','-r600','chap1Figure-LorenzAttractor2D.eps');
% new figure for three dimensional plot
h2 = figure;
% plot3 is very similar to plot
plot3(ya(:,1),ya(:,2),ya(:,3));
% the view point setting below was experimentally determined to
% see the best possible view of the attractor, in order to
% understand the sheet-like nature of the fractal. You should
% rotate and zoom the view in the 3D MATLAB figure to better
% understand the structure.
azimuth = -76; % degrees
elevation = -40; % degrees
view(azimuth,elevation);
xlabel('$x$','Interpreter','LaTeX','FontSize',24);
ylabel('$y$','Interpreter','LaTeX','FontSize',24);
zlabel('$z$','Interpreter','LaTeX','FontSize',24);
% uncomment line belwo for EPS output
% print(h2,'-depsc','-r600','chap1Figure-LorenzAttractor3D.eps');
% time domain plot, not visually appealing :)
h3 = figure;
% we plot only 5000 points so we can see some features of
% the waveform clearly
% remember: MATLAB array indices start at 1.
plot(t(1:5000),ya([1:5000],1));
xlabel('$t$ (seconds)','Interpreter','LaTeX','FontSize',24);
ylabel('$x$','Interpreter','LaTeX','FontSize',24);
% uncomment line belwo for EPS output
% print(h3,'-depsc','-r600','chap1FigureLorenzAttractorTimeDomain.eps');
B.2 Linear Equation
Listing B.2: MATLAB code for plotting the graph of a straight line
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% Purpose: plot simple linear system
% define range of x values (-5 to 5) and spacing (0.1) between
B.2 Linear Equation
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% values.
close all;
clear all;
x = [-5:0.1:5];
% define function and plot the resulting straight line.
y=(x/3)-1;
h1=figure;
plot(x,y)
xlabel('$x$','Interpreter','LaTeX','FontSize',24);
ylabel('$y$','Interpreter','LaTeX','FontSize',24);
% uncomment line below for EPS output
% print(h1,'-depsc','-r600','chap1Figure-MATLABStraightLinePlot.
eps');
Appendix C
Chapter 2 VHDL and Simulink DSP Builder
C.1 VHDL Generic Full Adder
Listing C.1: VHDL full adder with generics
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericNBitFullAdder is
generic (bitLength : integer := 0);
port (
xInBits,yInBits : in std_logic_vector(bitLength
downto 0);
cIn : in std_logic;
cOut : out std_logic;
sumBits : out std_logic_vector(bitLength downto 0));
end genericNBitFullAdder;
architecture structuralRippleCarryAdder of genericNBitFullAdder
is
component oneBitFullAdder is port (
xIn,yIn,cIn : in std_logic;
sum,cOut : out std_logic);
end component;
signal carryInternal : std_logic_vector(bitLength+1 downto 0)
;
begin
-- map cIn and cOut to carryInternal!
carryInternal(0) <= cIn;
cOut <= carryInternal(bitLength+1);
-- Generate statement for instantiating repeated structures
-- p. 799 (Appendix A) in your book (Fundamentals of Digital
-- Logic Design with VHDL)
generateAdders : -- generate label
for i IN 0 to bitLength generate
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nFullAdders : oneBitFullAdder
port map (xInBits(i),yInBits(i),carryInternal(i),sumBits(
i),
carryInternal(i+1));
end generate;
end structuralRippleCarryAdder;
Points to note from the VHDL description are:
1. In line 6 we have utilized the generic keyword to emphasize that, the size of the full adder
can be resolved only at synthesis time.
2. Line 19 declares internal carry signals that will be utilized to interconnect the carry inputs and
outputs of the one bit adders.
3. Lines 22 and 23 map the input carry to the least significant bit of the internal carry signal and
the output carry to the most significant bit of the internal carry signal.
4. Lines 27 through 31 implement parameterization in VHDL via the for loop construct. Note that
you need to make sure the VHDL syntax is correct, we have added carriage returns for code
clarity.
C.2 VHDL Seven Segment Decoder
Listing C.2: VHDL behavioural seven segment decoder
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sevenSegmentDecoder is port (
integerIn : in integer range 0 to 9;
hexOut : out std_logic_vector(7 downto 0));
end sevenSegmentDecoder;
architecture behavioral of sevenSegmentDecoder is
begin
with integerIn select
hexOut <= X"40" when 0,
X"79" when 1,
X"24" when 2,
X"30" when 3,
X"19" when 4,
X"12" when 5,
X"02" when 6,
X"78" when 7,
X"00" when 8,
X"10" when others;
end behavioral;
C.3 Top-Level for Generic Full Adder
C.3 Top-Level for Generic Full Adder
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Listing C.3: VHDL top level for generic adder
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rippleCarryAdder is port (
SW : in std_logic_vector(9 downto 0);
HEX3,HEX2,HEX1,HEX0 : out std_logic_vector(6 downto 0);
-- LEDs are going to indicate carry out
LEDG : out std_logic_vector(7 downto 0));
end rippleCarryAdder;
architecture topLevel of rippleCarryAdder is
component genericNBitFullAdder is
generic (bitLength : integer := 0);
port (
xInBits,yInBits : in std_logic_vector(bitLength
downto 0);
cIn : in std_logic;
cOut : out std_logic;
sumBits : out std_logic_vector(bitLength downto 0));
end component;
component sevenSegmentDecoder is port (
integerIn : in integer range 0 to 9;
hexOut : out std_logic_vector(7 downto 0));
end component;
signal
signal
signal
signal
signal
carry0 : std_logic;
sumInternal : std_logic_vector(3 downto 0);
sumInteger : integer;
unitsDigit,tensDigit : integer;
hex0Out,hex1Out : std_logic_vector(7 downto 0);
begin
carry0 <= '0';
oneBitFullAdder : genericNBitFullAdder generic map (bitLength
=> 0)
port map ( xInBits => SW(0 downto 0),
yInBits => SW(1 downto 1),
cIn => carry0,
cOut => LEDG(0),
sumBits => LEDG(1 downto 1));
fourBitFullAdder : genericNBitFullAdder generic map (
bitLength => 3)
port map ( xInBits => SW(5 downto 2),
yInBits => SW(9 downto 6),
cIn => carry0,
cOut => LEDG(2),
sumBits => sumInternal(3 downto 0));
sumInteger <= to_integer(unsigned(sumInternal));
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unitsDigit <= sumInteger rem 10;
tensDigit <= sumInteger / 10;
unitsDisplay : sevenSegmentDecoder port map (unitsDigit,
hex0Out);
tensDisplay : sevenSegmentDecoder port map (tensDigit,hex1Out
);
HEX0 <= hex0Out(6 downto 0);
HEX1 <= hex1Out(6 downto 0);
end topLevel;
1. Lines 36 through 47 show that we are going to realize two adders : an one bit full adder and
a four bit full adder. The important VHDL syntax nuance is: since the genericNBitFullAdder module expects a std logic vector, we need to make sure our one bit inputs and outputs
are of type std logic vector, not of type std logic. Hence, instead of using SW(0) we use
SW(0 down to 0).
2. Lines 49 through 51 convert the output from the four bit full adder into an unsigned integer and
the digits from the integer are extracted for use with the sevenSegmentDecoder module. The
online reference design video for the ALU realization in Sec. 2.3.2.2 has details on extracting
digits from unsigned integers.
C.4 Seconds Counter with Single Pulse Generator
Listing C.4: VHDL seconds counter
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity secondsCounter is port (
areset,clockIn : in std_logic;
minuteCounterEnablePulse : out std_logic;
secondsOut : out integer range 0 to 59);
end entity;
architecture behavioralSecondsCounter of secondsCounter is
type state is (reset,generatePulse,stop);
signal currentState,nextState : state;
signal secondsCountRegister : integer range 0 to 49999999;
signal internalSecondsCount : integer range 0 to 59;
signal enablePulseGenerator : std_logic;
-begin
secondsCountProcess : process(areset,clockIn)
begin
if areset='1' then
C.4 Seconds Counter with Single Pulse Generator
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secondsCountRegister <= 0;
internalSecondsCount <= 0;
enablePulseGenerator <= '0';
else
if rising_edge(clockIn) then
if secondsCountRegister >= 49999 then
secondsCountRegister <= 0;
if internalSecondsCount >= 59 then
internalSecondsCount <= 0;
enablePulseGenerator <= '1';
else
internalSecondsCount <=
internalSecondsCount + 1;
enablePulseGenerator <= '0';
end if;
else
secondsCountRegister <= secondsCountRegister
+ 1;
end if;
end if;
end if;
end process;
-- single pulse generator state machine
stateMemory : process(areset,clockIn)
begin
if areset='1' then
currentState <= reset;
else
if rising_edge(clockIn) then
currentState <= nextState;
end if;
end if;
end process;
stateTransitionLogic : process(enablePulseGenerator,
currentState)
begin
case currentState is
when reset =>
if enablePulseGenerator='1' then
nextState <= generatePulse;
else
nextState <= reset;
end if;
when generatePulse =>
nextState <= stop;
when others =>
if enablePulseGenerator='0' then
nextState <= reset;
else
nextState <= stop;
end if;
end case;
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end process;
-- output logic (could put this inside state transition logic
process)
with currentState select
minuteCounterEnablePulse <= '1' when generatePulse,
'0' when others;
-- end single pulse generator FSM
--output seconds count register content for display
secondsOut <= internalSecondsCount;
end behavioralSecondsCounter;
The main ideas in the snippet that correspond to each of the blocks in Fig. 2.15 are:
1. Lines 13 and 14 illustrate how to use the type specification in VHDL to specify user-defined
states. This will help the synthesizer (and simulator) infer a state machine from your design.
2. Lines 48 through 57 will infer the state memory block in Fig. 2.15.
3. Lines 58 through 76 will infer the next state logic block in Fig. 2.15.
4. Line 78 will infer the output logic block in Fig. 2.15.
C.5 Abstracting the FPGA Development Flow in Simulink
Simulink should be the tool of choice in realizing abstract mathematical concepts. For realizing
chaotic system nonlinearities, we will utilize DSP builder blockset for Simulink from Altera. The
reference for this section is Altera’s DSP Builder Advanced Blockset reference manual that can be
found on Altera’s DSP Builder website [1].
1. The concept behind DSP builder is to create a synthesizable subsystem that incorporates our
mathematical abstraction. To do so, we first access the Altera DSP Builder Advanced Blockset1 library from Simulink, as shown in Fig. C.5.1.
Fig. C.5.1: The Base blocks library in the DSP Builder Advanced Blockset.
1
Altera recommends the use of Advanced Blockset instead of Standard Blockset for newer designs.
C.5 Abstracting the FPGA Development Flow in Simulink
149
2. We create a new Simulink model and then place the Control and Signals block from the Base
Blocks library in Fig. C.5.1. Fig. C.5.2 and Fig. C.5.3 show the configuration parameters for
these blocks that will be used in a majority of the designs in this book.
Fig. C.5.2: In the Control block, make sure Generate Hardware is checked and use
an absolute path for the hardware destination directory. Turn off automatic test
benches. Set both address and data width to 16-bits.
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Fig. C.5.3: In the Signals block configuration, set the clock frequency to 50 MHz.
There is no need to use a separate bus clock. Make sure the reset is active high.
3. We next set the solver configurations as shown in Fig. C.5.4. The completed top level is shown
in Fig. C.5.5. We have created a subsystem at the top level. Within this subsystem, we will
realize the nonlinear synthesizable subsystem.
4. Within the nonlinear subsystem, we place a Device block from the Base Blocks library and
configure the Device block as shown in Fig. C.5.6. Fig. C.5.7 shows the subsystem from the
top level that incorporates the Device Block.
5. Inside the nonlinear synthesizable subsystem from Fig. C.5.7, we specify our design mathematically. In order to do this, we will use blocks from the ModelPrim library, shown in Fig. C.5.8.
C.5 Abstracting the FPGA Development Flow in Simulink
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Fig. C.5.4: The solver should be configured as fixed-step and with no discrete
states.
Fig. C.5.5: The top level of our design. According to DSP Builder syntax, the
synthesizable portion of our design must be specified as a subsystem within the top
level.
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Fig. C.5.6: Device block configuration. We don’t have to explicitly set the Cyclone
IV E part number since we are only going to be synthesizing a subsystem, not a
stand-alone Quartus project from DSP Builder.
Fig. C.5.7: The Device block must be placed within a subsystem, not at the top
level that has the Control and Signals blocks.
C.5 Abstracting the FPGA Development Flow in Simulink
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Fig. C.5.8: The ModelPrim library from the DSP Builder Advanced Blockset.
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6. There are two main blocks that should be part of any nonlinear synthesizable subsystem: the
Convert block shown in Fig. C.5.9 and the SynthesisInfo block shown in Fig. C.5.10.
Fig. C.5.9: This block is used to convert inputs and outputs to single precision
(32-bit) floating point.
Fig. C.5.10: We need a SynthesisInfo block for controlling synthesis flow. By using
the default option of Scheduled, we let DSP builder use a pipelining and delay
distribution algorithm that create fast hardware implementations from an easily
described untimed block diagram.
References
155
7. We finally enable port data types as shown in Fig. C.5.11 as a visual debugging tool, in case of
errors.
Fig. C.5.11: Enable port data types helps us debug the design more easily. In our
experience, the most common error is incorrect data types. In the case of incorrect
data types, functionally speaking, we have domain and range errors.
Once we run our top level in Simulink, DSP builder should generate the appropriate hardware
in the directory specified via the Control block (Fig. C.5.2). Make sure the constant input(s) from
the Source library at the top level have single as the output data type. The default is double and
will generate 64-bit bus widths.
References
1. Altera Corporation (2013) DSP Builder, Available via DIALOG.
http://www.altera.com/products/software/products/dsp/dsp-buil
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der.html Cited 7 May 2013
Appendix D
Chapter 3 VHDL, MATLAB Code and
ModelSim Scripts
D.1 VHDL Specification of the Lorenz System
Listing D.1: VHDL specification of the Lorenz system. We have split comments
over multiple lines so be careful when copying and pasting the HDL! Note that the
specification is incomplete, we use it to understand the ideas behind Euler’s
method.
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entity lorenzSystem is port (
resetn, clockIn : in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end lorenzSystem;
architecture behavioral of lorenzSystem is
signal reset : std_logic;
...
-- state variables
signal x1,x2,x3,x1New,x2New,x3New : std_logic_vector(31 downto 0)
;
...
begin
reset <= not resetn;
-- Euler's method
...
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
...
if resetn = '0' then
-- initial state
-- the constants below are in single-precision
32-bit floating point format
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-- You can use an online floating point converter
such as :
-- http://babbage.cs.qc.cuny.edu/IEEE-754.old/
Decimal.html
-- to determine the appropriate 32-bit
hexadecimal values for the corresponding
reals.
x1 <=
X"41200000";-- 10
x2 <=
X"41A00000";-- 20
x3 <=
X"41F00000";-- 30
...
else
if rising_edge(clockIn) then
... -- appropriate state update computations
go here (will be discussed later)
x1 <= x1New;
x2 <= x2New;
x3 <= x3New;
end if;
end if;
end process;
...
...
end behavioral;
D.2 VHDL Specification of the Lorenz System with
Mathematical Labelling of Signals
Listing D.2: VHDL specification of the Lorenz system with consistent
mathematical labels for the various signals. This specification is also incomplete.
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entity lorenzSystem is port (
resetn, clockIn : in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end lorenzSystem;
architecture behavioral of lorenzSystem is
signal reset : std_logic;
...
-- state variables
signal x,y,z,xNew,yNew,zNew : std_logic_vector(31 downto 0);
...
begin
reset <= not resetn;
-- Euler's method
...
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
D.4 Complete VHDL Specification of the Lorenz System
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...
if resetn = '0' then
-- initial state
-- the constants below are in single-precision
32-bit floating point format
-- You can use an online floating point converter
such as :
-- http://babbage.cs.qc.cuny.edu/IEEE-754.old/
Decimal.html
-- to determine the appropriate 32-bit
hexadecimal values for the corresponding
reals.
x <=
X"41200000";-- 10
y <=
X"41A00000";-- 20
z <=
X"41F00000";-- 30
...
else
if rising_edge(clockIn) then
... -- appropriate state update computations
go here (will be discussed later)
x <= xNew;
y <= yNew;
z <= zNew;
end if;
end if;
end process;
...
...
end behavioral;
D.3 MATLAB Code for Plotting Lorenz System Trajectory
Obtained from Euler’s Method
Listing D.3: MATLAB code for plotting output from Simulink.
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>>
>>
>>
>>
>>
>>
x=xSimOut.signals.values; % extract x data from structure
t=linspace(0,1,1001);
plot(t,x')
xlabel('t');
ylabel('x(t)');
title('x(t) plot for Lorenz System');
D.4 Complete VHDL Specification of the Lorenz System
Listing D.4: Complete VHDL specification of the Lorenz system, incorporating
both DSP builder synthesized subsystem and Euler’s method.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
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entity lorenzSystem is port (
resetn, clockIn : in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end lorenzSystem;
architecture behavioral of lorenzSystem is
signal reset : std_logic;
-- constants
signal dt,output1Over10Scale,output1Over20Scale,
output1Over30Scale : std_logic_vector(31 downto 0);
-- state variables
signal x,y,z,xNew,yNew,zNew,xScaled,yScaled,zScaled,xFixed,yFixed
,zFixed : std_logic_vector(31 downto 0);
-- prescalar
signal count : integer range 0 to 64;
-- DSP builder top level.
-- Note: Open lorenzSystem_NonlinearSubsystem.vhd and create
component.
-- NOTE : SAME STEPS FOR OTHER CHAOTIC SYSTEMS!
component lorenzSystem_NonlinearSubsystem is
port (
In_dt : in std_logic_vector(31 downto 0);
In_x : in std_logic_vector(31 downto 0);
In_y : in std_logic_vector(31 downto 0);
In_z : in std_logic_vector(31 downto 0);
Out_x : out std_logic_vector(31 downto 0);
Out_y : out std_logic_vector(31 downto 0);
Out_z : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
-- END DSP builder top level.
-- latency : 5 clock cycles (scale for DAC range)
component floatingPointMultiplyDedicated IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
-- latency : 6 clock cycles
component floatingPointToFixedLorenz IS
PORT
D.4 Complete VHDL Specification of the Lorenz System
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(
aclr
clock
dataa
result
:
:
:
:
IN STD_LOGIC ;
IN STD_LOGIC ;
IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component floatingPointToFixedZLorenz IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 781.250
KHz (64 counts of 50 MHz clock)
-- Since dt = 1/1024, time scale is actually (780.250e3/1024)
= 762 Hz (approximately)
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A800000"; -- 1/1024
output1Over10Scale <= X"3DCCCCCC"; --0.1
output1Over20Scale <= X"3D4CCCCC"; -- 0.05
output1Over30Scale <= X"3D888888"; -- 0.06666
approx.
if resetn = '0' then
-- initial state
x <=
X"41200000";-- 10
y <=
X"41A00000";-- 20
z <=
X"41F00000";-- 30
count <= 0;
else
if rising_edge(clockIn) then
if count = 64 then
count <= 0;
else
count <= count + 1;
end if;
if count = 63 then
x <= xNew;
y <= yNew;
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z <= zNew;
end if;
end if;
end if;
end process;
staticNonlinearitiesAndDeltaT :
lorenzSystem_NonlinearSubsystem port map (
In_dt => dt,
In_x => x,
In_y => y,
In_z => z,
Out_x => xNew,
Out_y => yNew,
Out_z => zNew,
clk => clockIn,
areset => reset,
h_areset => reset);
-- END Euler's method
-- scale outputs
scaleX : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => x,
datab
=> output1Over10Scale,
result => xScaled);
scaleY : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => y,
datab
=> output1Over20Scale,
result => yScaled);
scaleZ : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => z,
datab
=> output1Over30Scale,
result => zScaled);
--state outputs : convert scaled floating point x,y variables
to 2.30 fixed point for DAC
xOutFinal : floatingPointToFixedLorenz port map (
aclr => reset,
clock => clockIn,
dataa
=> xScaled,
result
=> xFixed);
yOutFinal : floatingPointToFixedLorenz port map (
aclr => reset,
clock => clockIn,
dataa
=> yScaled,
result
=> yFixed);
-- convert scaled z variable to 3.29 fixed point since z(t)
for Lorenz requires larger resolution for the
D.5 Complete VHDL Specification of the Highly Complex Attractor System
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-- magnitude component (this should be evident from the
MATLAB and/or ModelSim simulation.
zOutFinal : floatingPointToFixedZLorenz port map (
aclr => reset,
clock => clockIn,
dataa
=> zScaled,
result
=> zFixed);
xOut <= xFixed(31 downto 16);
yOut <= yFixed(31 downto 16);
zOut <= zFixed(31 downto 16);
end behavioral;
D.5 Complete VHDL Specification of the Highly Complex
Attractor System
Listing D.5: Highly Complex Attractor System in VHDL
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--04/10/13
--Single precision (32-bit) floating point realization
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity highlyComplexAttractorSystem is port (
resetn, clockIn : in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end highlyComplexAttractorSystem;
architecture behavioral of highlyComplexAttractorSystem is
signal reset : std_logic;
-- constants
signal dt,outputHalfScale,output1Over8Scale : std_logic_vector
(31 downto 0);
-- state variables
signal x,y,z,xNew,yNew,zNew,xScaled,yScaled,zScaled,xFixed,yFixed
,zFixed : std_logic_vector(31 downto 0);
-- prescalar
signal count : integer range 0 to 64;
-- DSP builder top level.
Steps to add:
-- 1. source ./dspba_rtl/highlyComplexAttractor/
NonlinearSubsystem/NonlinearSubsystem.add.tcl via TCL window
(View -> Utility Windows -> TCL Console)
-- 2. source ./dspba_rtl/highlyComplexAttractor/
NonlinearSubsystem/
highlyComplexAttractor_NonlinearSubsystem_fpc.add.tcl via TCL
window (View -> Utility Windows -> TCL Console)
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-- 2. Open highlyComplexAttractor_NonlinearSubsystem.vhd from
the path above and create component.
-- NOTE : SAME STEPS FOR OTHER CHAOTIC SYSTEMS!
component highlyComplexAttractor_NonlinearSubsystem is
port (
In_dt : in std_logic_vector(31 downto 0);
In_x : in std_logic_vector(31 downto 0);
In_y : in std_logic_vector(31 downto 0);
In_z : in std_logic_vector(31 downto 0);
Out_x : out std_logic_vector(31 downto 0);
Out_y : out std_logic_vector(31 downto 0);
Out_z : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic);
end component;
-- END DSP builder top level.
-- latency : 5 clock cycles (scale for DAC range)
component floatingPointMultiplyDedicated IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 781.250
KHz (64 counts of 50 MHz clock)
-- Since dt = 1/1024, time scale is actually (780.250e3/1024)
= 762 Hz (approximately)
-- state memory
process(clockIn, resetn)
begin
D.5 Complete VHDL Specification of the Highly Complex Attractor System
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-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A800000"; -- 1/1024
outputHalfScale <= X"3F000000"; --0.5
output1Over8Scale <= X"3E000000"; -- 0.125
if resetn = '0' then
-- initial state
x <=
X"3F800000";-- 1
y <=
X"3F800000";
z <=
X"3F800000";
count <= 0;
else
if rising_edge(clockIn) then
if count = 64 then
count <= 0;
else
count <= count + 1;
end if;
if count
x <=
y <=
z <=
end if;
end if;
= 63 then
xNew;
yNew;
zNew;
end if;
end process;
staticNonlinearities :
highlyComplexAttractor_NonlinearSubsystem port map (
In_dt => dt,
In_x => x,
In_y => y,
In_z => z,
Out_x => xNew,
Out_y => yNew,
Out_z => zNew,
clk => clockIn,
areset => reset,
h_areset => reset);
-- END Euler's method
-- scale outputs
scaleX : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => x,
datab
=> outputHalfScale,
result => xScaled);
scaleY : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => y,
datab
=> outputHalfScale,
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D Chapter 3 VHDL, MATLAB Code and ModelSim Scripts
result => yScaled);
scaleZ : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => z,
datab
=> output1Over8Scale,
result => zScaled);
--state outputs : convert scaled floating point variables to
5.27 fixed point format DAC (no latency)
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xScaled,
result
=> xFixed);
yOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> yScaled,
result
=> yFixed);
zOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> zScaled,
result
=> zFixed);
xOut <= xFixed(31 downto 16);
yOut <= yFixed(31 downto 16);
zOut <= zFixed(31 downto 16);
end behavioral;
D.6 VHDL Testbench for Chen System
Listing D.6: A test bench. Note that test benches are not synthesizable.
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-- testbench for Chen system
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity chenSystemtb is
end chenSystemtb;
architecture testbench of chenSystemtb is
signal clock,reset,resetn,trigger,increment,pulseOut :
std_logic := '0';
signal xOut,yOut,zOut : std_logic_vector(15 downto 0);
component chenSystem is port (
resetn, clockIn : in std_logic;
D.7 ModelSim Script File for Chen System
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xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end component;
begin
chenSystemInstance : chenSystem port map (
resetn => resetn,
clockIn => clock,
xOut => xOut,
yOut => yOut,
zOut => zOut);
clock50MHzProcess : process
begin
clock <= not clock;
wait for 10 ns;
end process clock50MHzProcess;
stimulus : process
begin
resetn <= '0';
wait for 55 ns;
resetn <= '1'; -- unreset after 55 ns
wait; -- prevent process from being executed again
end process stimulus;
end testbench;
The salient features of the test bench are:
1. The entity statement has no input and/or output ports. This makes sense since the test bench is
a virtual environment that cannot be synthesized.
2. We have to generate a 50 MHz clock. This is done using the process statement shown.
3. We then provide stimulus inputs to our module under test. Notice that since VHDL processes
execute concurrently, our stimulus process has a wait as the last statement to prevent repeated
process execution.
D.7 ModelSim Script File for Chen System
Listing D.7: Script file for Chen system that lists ModelSim commands for
performing functional simulation
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# do vlib work only once!
# vlib work
vmap work work
# compile DSP builder advanced blockset source
vcom D:/altera/12.0/quartus/dspba/Libraries/vhdl/fpc/math_package
.vhd
vcom D:/altera/12.0/quartus/dspba/Libraries/vhdl/fpc/
math_implementation.vhd
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D Chapter 3 VHDL, MATLAB Code and ModelSim Scripts
vcom D:/altera/12.0/quartus/dspba/Libraries/vhdl/fpc/hcc_package.
vhd
vcom D:/altera/12.0/quartus/dspba/Libraries/vhdl/fpc/
hcc_implementation.vhd
vcom D:/altera/12.0/quartus/dspba/Libraries/vhdl/fpc/
fpc_library_package.vhd
vcom D:/altera/12.0/quartus/dspba/Libraries/vhdl/fpc/fpc_library.
vhd
# compile DSP builder advanced blockset nonlinearities
vcom ../dspBuilder/chenSystem/dspba_rtl/chenSystem/
NonlinearSubsystem/chenSystem_NonlinearSubsystem.vhd
vcom ../dspBuilder/chenSystem/dspba_rtl/chenSystem/
NonlinearSubsystem/NonlinearSynthesizableSubsystem/
chenSystem_NonlinearSubsystem_NonlinearSynthesizableSubsystem
.vhd
# compile source
vcom ../floatingPointMultiplyDedicated.vhd
vcom ../floatingPointToFixed.vhd
vcom ../chenSystem.vhd
vcom chenSystemtb.vhd
vsim chenSystemtb
# configure wave window to have a white background color
# http://www.utdallas.edu/˜zhoud/EE%203120/
Xilinx_tutorial_Spartan3_home_PC.pdf and ModelSim Reference
Manual - configure command
configure wave -background white -foreground red -textcolor blue
-timecolor blue -vectorcolor red -wavebackground white cursorcolor black
add wave -divider "Clock and Reset"
add wave clock
add wave resetn
add wave -divider "Outputs from Chen System model"
# obtained switch information below by using analog
formatting in ModelSim
add wave -format analog-step -min -13380 -max 11972
xOut
add wave -format analog-step -min -26982 -max 24076
yOut
add wave -format analog-step -min -11033 -max 20597
zOut
(automatic)
-height 74
-height 74
-height 74
add wave -divider "Chen System Module Internal Signals"
add wave -label dt -hex sim:/chenSystemtb/chenSystemInstance/dt
add wave -label count -hex sim:/chenSystemtb/chenSystemInstance/
count
add wave -label xPlus_f1 -hex sim:/chenSystemtb/
chenSystemInstance/xNew
D.7 ModelSim Script File for Chen System
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add wave -label yPlus_f2 -hex sim:/chenSystemtb/
chenSystemInstance/yNew
add wave -label zPlus_f3 -hex sim:/chenSystemtb/
chenSystemInstance/zNew
add wave -label x -hex sim:/chenSystemtb/chenSystemInstance/x
add wave -label y -hex sim:/chenSystemtb/chenSystemInstance/y
add wave -label z -hex sim:/chenSystemtb/chenSystemInstance/z
add wave -label xFixed -hex sim:/chenSystemtb/chenSystemInstance/
xFixed
add wave -label yFixed -hex sim:/chenSystemtb/chenSystemInstance/
yFixed
add wave -label zFixed -hex sim:/chenSystemtb/chenSystemInstance/
zFixed
# run 1ms
Appendix E
Chapter 4 MATLAB Code, VHDL and
ModelSim Scripts
E.1 R¨ossler System Specification in MATLAB
Listing E.1: MATLAB code for the R¨ossler system
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function [t,y] = rossler(tspan,reltol,abstol,x0,alpha,beta,gamma)
%
%
%
%
%
Simulates the Rossler system:
x'=-y-z
y'=x+alpha*y
z'=beta+z*(x-gamma)
Function uses ode45. The arguments to be passed into the
function
% are tspan, reltol,abstol,x0,alpha,beta,gamma. For classic
Rossler
% attractor, try:
% [t,rosslerOut]=rossler([0:0.01:100],1e-5,1e-5,[14.5 0
0.1],0.1,0.1,14);
options = odeset('RelTol',reltol,'AbsTol',abstol);
[t,y] = ode45(@rosslerFunction,tspan,x0,options);
function dy = rosslerFunction(t,y)
dy = zeros(3,1);
% a column vector
dy(1) = -y(2)-y(3);
dy(2) = y(1) + alpha*y(2);
dy(3) = beta+y(3)*(y(1)-gamma);
end
end
E.2 Period-1 Limit Cycle for the R¨ossler System
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Listing E.2: MATLAB code for obtaining a limit cycle (period 1) the R¨ossler
system
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% type one line at a time or use a script file after defining the
rossler function
h1=figure;
[t,y1]=rossler([0:0.01:100],1e-5,1e-5,[14.5 0 0.1],0.1,0.1,4);
plot(y1([5000:10001],1),y1([5000:10001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h1,'-depsc','-r600','chap4FigureRosslerSystemPeriodOneLimitCycle.eps');
E.3 MATLAB Code for Period-Doubling Route to Chaos
Listing E.3: MATLAB code for obtaining period-doubling bifurcation in the
R¨ossler system
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% rossler period-doubling script
% make sure rossler.m is in the same folder
[t,rosslerPeriod3]=rossler([0:0.01:10000],1e-5,1e-5,[14.5 0
0.1],0.1,0.1,12);
[t,rosslerPeriod6]=rossler([0:0.01:10000],1e-5,1e-5,[14.5 0
0.1],0.1,0.1,12.6);
[t,rosslerPeriodHigh]=rossler([0:0.01:10000],1e-5,1e-5,[14.5 0
0.1],0.1,0.1,13.3);
[t,rosslerChaos]=rossler([0:0.01:10000],1e-5,1e-5,[14.5 0
0.1],0.1,0.1,14);
h1 = figure;
plot(rosslerPeriod3([75000:100001],1),rosslerPeriod3
([75000:100001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$x$','Interpreter','Latex','Fontsize',32)
ylabel('$y$','Interpreter','Latex','Fontsize',32)
title('Period=3','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h1,'-depsc','-r600','chap4Figure-rosslerP3.eps');
h2=figure;
plot(rosslerPeriod6([75000:100001],1),rosslerPeriod6
([75000:100001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$x$','Interpreter','Latex','Fontsize',32)
ylabel('$y$','Interpreter','Latex','Fontsize',32)
title('Period=6','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
E.4 MATLAB Code for Chua Oscillator
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% print(h2,'-depsc','-r600','chap4Figure-rosslerP6.eps');
h3=figure;
plot(rosslerPeriodHigh([75000:100001],1),rosslerPeriodHigh
([75000:100001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$x$','Interpreter','Latex','Fontsize',32)
ylabel('$y$','Interpreter','Latex','Fontsize',32)
title('Higher Period','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h3,'-depsc','-r600','chap4Figure-rosslerHighPeriod.eps');
h4=figure;
plot(rosslerChaos([75000:100001],1),rosslerChaos
([75000:100001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$x$','Interpreter','Latex','Fontsize',32)
ylabel('$y$','Interpreter','Latex','Fontsize',32)
title('Chaos','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h4,'-depsc','-r600','chap4Figure-rosslerChaos.eps');
E.4 MATLAB Code for Chua Oscillator
Listing E.4: MATLAB code for simulating Chua oscillator
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function [t,y] = chuaOscillator(tspan,reltol,abstol,x0,alpha,beta
,gamma,a,c)
% Simulates Chua's oscillator with a smooth nonlinearity
% from Ambelang's EE4060 project report (Spring 2011 Nonlinear
Dynamics
% Course at MSOE)
% x'=alpha*(y-g(x))
% y'=x-y+z
% z'=-beta*y-gamma*z
% Function uses ode45. The arguments to be passed into the
function
% are tspan, reltol,abstol,x0,alpha,beta,,gamma,a and c. a and c
are
% parameters for the nonlinear function:
% f(x)=-a*x+0.5(a+b)(|x+1|-|x-1|)
% For a double-scroll chaotic attractor, try:
% [t,doubleScroll]=chuaOscillator([0:0.1:1000],1e-5,1e-5,[0.1 0
0.1],10,16,0,1,-0.143);
% For period-adding route,
% [t,period3]=chuaOscillator([0:0.1:1000],1e-5,1e-5,[0.1 0
0.1],3.708,3.499,0.076,1,-0.276);
% [t,chaosAfterPeriod3]=chuaOscillator([0:0.1:1000],1e-5,1e
-5,[0.1 0 0.1],3.708,3.549,0.076,1,-0.276);
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% [t,period4]=chuaOscillator([0:0.1:1000],1e-5,1e-5,[0.1 0
0.1],3.708,3.574,0.076,1,-0.276);
% [t,chaosAfterPeriod4]=chuaOscillator([0:0.1:1000],1e-5,1e
-5,[0.1 0 0.1],3.708,3.6,0.076,1,-0.276);
options = odeset('RelTol',reltol,'AbsTol',abstol);
[t,y] = ode45(@chuaOscillatorFunction,tspan,x0,options);
function dy = chuaOscillatorFunction(t,y)
dy = zeros(3,1);
% a column vector
dy(1) = alpha*(y(2)-g(y(1),a,c));
dy(2) = y(1)-y(2)+y(3);
dy(3) = -beta*y(2)-gamma*y(3);
end
function y=g(x,a,c)
y=a*xˆ3+c*x;
end
end
E.5 MATLAB Code for Period-Adding Route to Chaos
Listing E.5: MATLAB code for obtaining the period-adding route to chaos in
Fig. 4.3
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% period-adding, using Chua's oscillator
% Make sure chuaOscillator.m is in the same folder
[t,period3]=chuaOscillator([0:0.1:1000],1e-5,1e-5,[0.1 0
0.1],3.708,3.499,0.076,1,-0.276);
[t,chaosAfterPeriod3]=chuaOscillator([0:0.1:1000],1e-5,1e-5,[0.1
0 0.1],3.708,3.549,0.076,1,-0.276);
[t,period4]=chuaOscillator([0:0.1:1000],1e-5,1e-5,[0.1 0
0.1],3.708,3.574,0.076,1,-0.276);
[t,chaosAfterPeriod4]=chuaOscillator([0:0.1:1000],1e-5,1e-5,[0.1
0 0.1],3.708,3.6,0.076,1,-0.276);
h1 = figure;
plot(period3([5000:10001],1),period3([5000:10001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('3:3 Limit Cycle','Fontsize',32)
% enable line below for EPS output
% print(h1,'-depsc','-r600','chap4Figure-chuaOscillatorP3.eps');
h2 = figure;
plot(chaosAfterPeriod3([5000:10001],1),chaosAfterPeriod3
([5000:10001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
E.6 MATLAB Code for Torus Breakdown System
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xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Chaos after 3:3 Limit Cycle ','Fontsize',32)
% enable line below for EPS output
% print(h2,'-depsc','-r600','chap4FigurechuaOscillatorChaosAfterP3.eps');
h3 = figure;
plot(period4([5000:10001],1),period4([5000:10001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('4:4 Limit Cycle ','Fontsize',32)
% enable line below for EPS output
% print(h3,'-depsc','-r600','chap4Figure-chuaOscillatorP4.eps');
h4 = figure;
plot(chaosAfterPeriod4([5000:10001],1),chaosAfterPeriod4
([5000:10001],2))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Chaos after 4:4 Limit Cycle ','Fontsize',32)
% enable line below for EPS output
% print(h4,'-depsc','-r600','chap4FigurechuaOscillatorChaosAfterP4.eps');
E.6 MATLAB Code for Torus Breakdown System
Listing E.6: MATLAB code implementing Eqs.(4.8) through (4.10)
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function [t,y] = torusBreakdown(tspan,reltol,abstol,x0,alpha,beta
,a,b)
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%
%
%
%
%
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%
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%
%
%
%
%
Simulates the torus breakdown system from Matsumoto et. al.:
x'=-alpha*f(y-x)
y'=-f(y-x)-z
z'=beta*y
Function uses ode45. The arguments to be passed into the
function
are tspan, reltol,abstol,x0,alpha,beta,a and b. a and b are
parameters
for the piecewise-linear function:
f(x)=-a*x+0.5(a+b)(|x+1|-|x-1|)
For a folded torus chaotic attractor, try:
[t,torusBreakdownOut]=torusBreakdown([0:0.1:1000],1e-5,1e-5,
[0.1 0 0.1],15,1,0.07,0.1);
options = odeset('RelTol',reltol,'AbsTol',abstol);
[t,y] = ode45(@torusBreakdownFunction,tspan,x0,options);
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E Chapter 4 MATLAB Code, VHDL and ModelSim Scripts
function dy = torusBreakdownFunction(t,y)
dy = zeros(3,1);
% a column vector
dy(1) = -alpha*f(y(2)-y(1),a,b);
dy(2) = -f(y(2)-y(1),a,b)-y(3);
dy(3) = beta*y(2);
end
function y=f(x,a,b)
y=-a*x+0.5*(a+b)*(abs(x+ones(length(x),1))-abs(x-ones(
length(x),1)));
end
end
E.7 MATLAB Code for Quasi-periodic Route To Chaos
Listing E.7: MATLAB code for obtaining torus-breakdown route to chaos in
Fig. 4.4
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% torus breakdown script
% make sure torusBreakdown.m is in the same folder
[t,torusAttractorTwoTorus]=torusBreakdown([0:0.1:1000],1e-5,1e
-5,[0.1 0 0.1],2.0,1,0.07,0.1);
[t,torusAttractorPeriod8]=torusBreakdown([0:0.1:1000],1e-5,1e
-5,[0.1 0 0.1],8.0,1,0.07,0.1);
[t,torusAttractorPeriod15]=torusBreakdown([0:0.1:1000],1e-5,1e
-5,[0.1 0 0.1],8.8,1,0.07,0.1);
[t,torusAttractorTorusBreakdown]=torusBreakdown([0:0.1:1000],1e
-5,1e-5,[0.1 0 0.1],15.0,1,0.07,0.1);
h1 = figure;
plot(torusAttractorTwoTorus([7500:10001],2),
torusAttractorTwoTorus([7500:10001],1))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Two-torus','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
%print(h1,'-depsc','-r600','chap4Figure-torusBreakDownTwoTorus.
eps');
h2=figure;
plot(torusAttractorPeriod8([7500:10001],2),torusAttractorPeriod8
([7500:10001],1))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
E.8 MATLAB Code with Chua Oscillator Parameter Values for Intermittency Route to Chaos177
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title('Period-8','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
%print(h2,'-depsc','-r600','chap4Figure-torusBreakDownPeriod8.eps
');
h3=figure;
plot(torusAttractorPeriod15([7500:10001],2),
torusAttractorPeriod15([7500:10001],1))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Period-15','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
%print(h3,'-depsc','-r600','chap4Figure-torusBreakDownPeriod15.
eps');
h4=figure;
plot(torusAttractorTorusBreakdown([7500:10001],2),
torusAttractorTorusBreakdown([7500:10001],1))
a = get(gca,'XTickLabel');
set(gca,'XTickLabel',a,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Chaos','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
%print(h4,'-depsc','-r600','chap4FiguretorusAttractorTorusBreakdown.eps');
E.8 MATLAB Code with Chua Oscillator Parameter Values for
Intermittency Route to Chaos
Listing E.8: MATLAB code implementing Eqs.(4.19) through (4.22)
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function [t,y] = chuaOscillatorIntermittency(tspan,reltol,abstol,
x0,alpha,beta,gamma,a,b)
% Simulates Chua's oscillator with a piecewise-linear
nonlinearity
% x'=alpha*(y-x-f(x))
% y'=x-y+z
% z'=-beta*y-gamma*z
% f(x) = bx + 0.5*(a-b)*(|x+1|-|x-1|)
% Function uses ode45. The arguments to be passed into the
function
% are tspan, reltol,abstol,x0,alpha,beta,,gamma,a and b.
options = odeset('RelTol',reltol,'AbsTol',abstol);
[t,y] = ode45(@chuaOscillatorFunction,tspan,x0,options);
function dy = chuaOscillatorFunction(t,y)
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E Chapter 4 MATLAB Code, VHDL and ModelSim Scripts
dy = zeros(3,1);
% a column vector
dy(1) = alpha*(y(2)-y(1)-f(y(1),a,b));
dy(2) = y(1)-y(2)+y(3);
dy(3) = -beta*y(2)-gamma*y(3);
end
function y=f(x,a,b)
y=b*x+0.5*(a-b)*(abs(x+ones(length(x),1))-abs(x-ones(
length(x),1)));
end
end
E.9 MATLAB Code for Plotting Intermittency Route to Chaos
Listing E.9: MATLAB code for obtaining intermittency route to chaos in Fig. 4.5
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% Intermittency script
% make sure chuaOscillatorIntermittency.m is in the same folder
alpha=-75.018755;
a=-0.98;
b=-2.4;
% Periodic
beta=44.803;
gamma=-4.480;
[t,intermittencyPeriodic]=chuaOscillatorIntermittency
([0:0.01:1000],1e-4,1e-4,[0.1 0 0.1],alpha,beta,gamma,a,b);
h1a = figure;
plot(intermittencyPeriodic(:,2),intermittencyPeriodic(:,3))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$y$','Interpreter','Latex','Fontsize',32)
ylabel('$z$','Interpreter','Latex','Fontsize',32)
title('Limit Cycle(s)','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h1a,'-depsc','-r600','chap4Figure-intermittencyPeriodic.
eps');
h1b = figure;
plot(t([75000:83000],1),intermittencyPeriodic([75000:83000],1));
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$t$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Limit Cycle(s) (time-domain)','Interpreter','Latex','
Fontsize',32)
%enable line below for EPS output
E.9 MATLAB Code for Plotting Intermittency Route to Chaos
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% print(h1b,'-depsc','-r600','chap4Figure-intermittencyPeriodicTimeDomain.eps');
% Chaos, one instance
beta=43.994721;
gamma=-4.3994721;
[t,intermittencyChaosOne]=chuaOscillatorIntermittency
([0:0.01:1000],1e-6,1e-6,[0.1,0,0.1],alpha,beta,gamma,a,b);
h2a = figure;
plot(intermittencyChaosOne([75000:100001],3),
intermittencyChaosOne([75000:100001],1))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$z$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Intermittency','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h2a,'-depsc','-r600','chap4Figure-intermittencyChaosOne.
eps');
h2b = figure;
plot(t([75000:83000],1),intermittencyChaosOne([75000:83000],2))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$t$','Interpreter','Latex','Fontsize',32)
ylabel('$y$','Interpreter','Latex','Fontsize',32)
title('Intermittency Chaos (time-domain)','Interpreter','Latex','
Fontsize',32)
% enable line below for EPS output
% print(h2b,'-depsc','-r600','chap4Figure-intermittencyChaosOneTimeDomain.eps');
% Chaos, second instance
beta=31.746032;
gamma=-3.1746032;
[t,intermittencyChaosTwo]=chuaOscillatorIntermittency
([0:0.01:1000],1e-6,1e-6,[0.1,0,0.1],alpha,beta,gamma,a,b);
h3a = figure;
plot(intermittencyChaosTwo([75000:100001],3),
intermittencyChaosTwo([75000:100001],1))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$z$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Intermittency','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h3a,'-depsc','-r600','chap4Figure-intermittencyChaosTwo.
eps');
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h3b = figure;
plot(t([75000:83000],1),intermittencyChaosTwo([75000:83000],2))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$t$','Interpreter','Latex','Fontsize',32)
ylabel('$y$','Interpreter','Latex','Fontsize',32)
title('Intermittency Chaos (time-domain)','Interpreter','Latex','
Fontsize',32)
% enable line below for EPS output
% print(h3b,'-depsc','-r600','chap4Figure-intermittencyChaosTwoTimeDomain.eps');
% Chaos, third instance
beta=31.25;
gamma=-3.125;
[t,intermittencyChaosThree]=chuaOscillatorIntermittency
([0:0.01:1000],1e-6,1e-6,[0.1,0,0.1],alpha,beta,gamma,a,b);
h4a = figure;
plot(intermittencyChaosThree([75000:100001],3),
intermittencyChaosThree([75000:100001],1))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$z$','Interpreter','Latex','Fontsize',32)
ylabel('$x$','Interpreter','Latex','Fontsize',32)
title('Intermittency','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h4a,'-depsc','-r600','chap4Figure-intermittencyChaosThree
.eps');
h4b = figure;
plot(t([75000:83000],1),intermittencyChaosThree([75000:83000],2))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$t$','Interpreter','Latex','Fontsize',32)
ylabel('$y$','Interpreter','Latex','Fontsize',32)
title('Intermittency Chaos (time-domain)','Interpreter','Latex','
Fontsize',32)
% enable line below for EPS output
% print(h4b,'-depsc','-r600','chap4Figure-intermittencyChaosThree
-TimeDomain.eps');
E.10 MATLAB Code for Resource-Consumer-Predator Model
Listing E.10: MATLAB code implementing Eqs.(4.23) through (4.25)
E.11 MATLAB Code for Chaotic Transients
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function [t,y] = resourcePredatorPrey(tspan,reltol,abstol,x0,xC,
yC,xP,yP,R0,C0,K)
% Simulates the resource predator prey model from
% "Controlling transient chaos in deterministic flows with
applications
% to electrical power systems and ecology". Physical Review E,
59(2),
% 1646 - 1655, 1999.
% Function uses ode45. The arguments to be passed into the
function
% are tspan, reltol,abstol,x0,alpha,beta,,gamma,a and b.
options = odeset('RelTol',reltol,'AbsTol',abstol);
[t,y] = ode45(@resourcePredatorPreyFunction,tspan,x0,options);
function dy = resourcePredatorPreyFunction(t,y)
dy = zeros(3,1);
% a column vector
dy(1) = y(1)*(1-y(1)/K)-(xC*yC*y(2)*y(1))/(y(1)+R0);
dy(2) = xC*y(2)*((yC*y(1))/(y(1)+R0)-1)-(xP*yP*y(3)*y(2))
/(y(2)+C0);
dy(3) = xP*y(3)*(-1+(yP*y(2))/(y(2)+C0));
end
end
E.11 MATLAB Code for Chaotic Transients
Listing E.11: MATLAB code for simulating chaotic transients and crisis
phenomenon in Fig. 4.6
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% chaotic transients script
% make sure resourcePredatorPrey.m is in the same folder
xC=0.4;
yC=2.009;
xP=0.08;
yP=2.876;
R0=0.16129;
C0=0.5;
% Periodic attractor and chaotic attractor co-exist
K=0.99;
[t,chaoticTransientPeriodic]=resourcePredatorPrey([0:0.1:1000],1e
-4,1e-4,[0.1 0.2 0.1],xC,yC,xP,yP,R0,C0,K);
h1 = figure;
plot(chaoticTransientPeriodic(:,1),chaoticTransientPeriodic(:,2))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
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xlabel('$R$','Interpreter','Latex','Fontsize',32)
ylabel('$C$','Interpreter','Latex','Fontsize',32)
title('Limit Cycle','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h1,'-depsc','-r600','chap4FigurechaoticTransientsPeriodic.eps');
h2 = figure;
plot(t(:,1),chaoticTransientPeriodic(:,3))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$t$','Interpreter','Latex','Fontsize',32)
ylabel('$P$','Interpreter','Latex','Fontsize',32)
title('$P$ population decays','Interpreter','Latex','Fontsize'
,32)
%enable line below for EPS output
% print(h2,'-depsc','-r600','chap4FigurechaoticTransientsPeriodic-TimeDomain.eps');
h3 = figure;
[t,chaoticTransientChaos]=resourcePredatorPrey([0:0.1:1000],1e
-4,1e-4,[0.55 0.35 0.8],xC,yC,xP,yP,R0,C0,K);
plot(chaoticTransientChaos(:,2),chaoticTransientChaos(:,3))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$R$','Interpreter','Latex','Fontsize',32)
ylabel('$P$','Interpreter','Latex','Fontsize',32)
title('Chaos','Interpreter','Latex','Fontsize',32)
%enable line below for EPS output
% print(h3,'-depsc','-r600','chap4Figure-chaoticTransientsChaos.
eps');
% Crisis past critical carrying capacity.
K=1.02;
[t,chaoticTransientCrisis]=resourcePredatorPrey([0:0.1:1000],1e
-4,1e-4,[0.55 0.35 0.8],xC,yC,xP,yP,R0,C0,K);
h4 = figure;
plot(t(:,1),chaoticTransientCrisis(:,3))
% http://www.mathworks.com/matlabcentral/newsreader/view_thread
/288159
figureProperties = get(gca,'XTickLabel');
set(gca,'XTickLabel',figureProperties,'fontsize',18)
xlabel('$t$','Interpreter','Latex','Fontsize',32)
ylabel('$P$','Interpreter','Latex','Fontsize',32)
title('$P$ time series','Interpreter','Latex','Fontsize',32)
% enable line below for EPS output
% print(h4,'-depsc','-r600','chap4Figure-chaoticTransientsCrisis.
eps');
E.12 VHDL Specification for Single Pulse Generator
E.12 VHDL Specification for Single Pulse Generator
Listing E.12: VHDL pulse FSM
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulseFSM is port (
reset,clock,trigger : in std_logic;
pulseOut,pulseOutSingleClockCycle : out std_logic);
end pulseFSM;
architecture mooreFSM of pulseFSM is
type state is (resetState,generatePulseCycle1,
generatePulseCycle2,generatePulseCycle3,
generatePulseCycle4,generatePulseCycle5,
generatePulseCycle6,generatePulseCycle7,
generatePulseCycle8,stopPulse,waitForTriggerRelease);
signal currentState,nextState : state;
begin
-- state memory
stateMemory : process(reset,clock)
begin
if reset='1' then
currentState <= resetState;
else
if rising_edge(clock) then
currentState <= nextState;
end if;
end if;
end process;
-- next state logic
stateTransitionLogic : process (currentState,trigger)
begin
case currentState is
when resetState =>
if trigger='0' then
nextState <= resetState;
else
nextState <= generatePulseCycle1;
end if;
when generatePulseCycle1 =>
nextState <= generatePulseCycle2;
when generatePulseCycle2 =>
nextState <= generatePulseCycle3;
when generatePulseCycle3 =>
nextState <= generatePulseCycle4;
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when generatePulseCycle4 =>
nextState <= generatePulseCycle5;
when generatePulseCycle5 =>
nextState <= generatePulseCycle6;
when generatePulseCycle6 =>
nextState <= generatePulseCycle7;
when generatePulseCycle7 =>
nextState <= generatePulseCycle8;
when generatePulseCycle8 =>
nextState <= stopPulse;
when stopPulse =>
nextState <= waitForTriggerRelease;
when waitForTriggerRelease =>
if trigger='1' then
nextState <= waitForTriggerRelease;
else
nextState <= resetState;
end if;
end case;
end process;
-- output logic
with currentState select
pulseOut <= '0' when resetState,
'0' when waitForTriggerRelease,
'0' when stopPulse,
'1' when others;
-- we enable single clock cycle pulse only after latency of
floating point design has been
-- accounted for.
with currentState select
pulseOutSingleClockCycle <= '1' when stopPulse,
'0' when others;
end mooreFSM;
E.13 ModelSim Testbench for Single Pulse Generator
Listing E.13: VHDL pulse FSM test bench
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-- testbench for pulse FSM (bifurcations)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulseFSMtb is
end pulseFSMtb;
architecture testbench of pulseFSMtb is
signal clock,reset,trigger,pulseOut : std_logic := '0';
E.14 ModelSim Script File for Single Pulse Generator
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component pulseFSM is port (
reset,clock,trigger : in std_logic;
pulseOut : out std_logic);
end component;
begin
pulseFSMInstance : pulseFSM port map (
reset => reset,
clock => clock,
trigger => trigger,
pulseOut => pulseOut);
clock50MHzProcess : process
begin
clock <= not clock;
wait for 10 ns;
end process clock50MHzProcess;
stimulus : process
begin
reset <= '1';
trigger <= '0';
wait for 55 ns;
reset <= '0';
-- unreset after 55 ns
wait for 100 ns;
trigger <= '1';
wait for 150 ns;
trigger <= '0';
wait; -- prevent process from being executed again
end process stimulus;
end testbench;
E.14 ModelSim Script File for Single Pulse Generator
Listing E.14: ModelSim script file for pulse FSM
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# do vlib work only once!
# vlib work
vmap work work
# compile source
vcom ../../pulseFSM.vhd
# compile testbench
vcom pulseFSMtb.vhd
vsim pulseFSMtb
# configure wave window to have a white background color
# http://www.utdallas.edu/˜zhoud/EE%203120/
Xilinx_tutorial_Spartan3_home_PC.pdf and ModelSim Reference
Manual - configure command
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configure wave -background white -foreground red -textcolor blue
-timecolor blue -vectorcolor red -wavebackground white cursorcolor black
add wave -divider "Clock and Reset"
add wave clock
add wave reset
add
add
add
add
add
add
wave -divider "Input"
wave trigger
wave -divider "Output"
wave pulseOut
wave -divider "FSM states"
wave -label "Synchronous current state" sim:/pulsefsmtb/
pulseFSMInstance/currentState
# run 500ns
E.15 VHDL Specification of Period-Doubling Route to Chaos
Listing E.15: VHDL specification of period-doubling bifurcation in the R¨ossler
system
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--Single precision (32-bit) floating point realization
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity rosslerSystem is port (
resetn, clockIn, incrementCountClockN,
incrementGammaClockN,incrementCount,incrementGamma :
in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end rosslerSystem;
architecture behavioral of rosslerSystem is
signal reset,incrementGammaClock,incrementDecrementGammaPulse,
dFlipFlopClock : std_logic;
-- constants
signal dt,output1Over2Scale,output1Over5Scale,alpha,beta,gamma,
gammaSignal : std_logic_vector(31 downto 0);
-- state variables
signal x,y,z,xNew,yNew,zNew,xScaled,yScaled,zScaled,xFixed,yFixed
,zFixed : std_logic_vector(31 downto 0);
-- prescalar
signal count,countIncrement : integer range 0 to 128;
-- DSP builder top level.
-- Note: Open rosslerSystem_NonlinearSubsystem.vhd and create
component.
-- NOTE : SAME STEPS FOR OTHER CHAOTIC SYSTEMS!
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component rosslerSystem_NonlinearSubsystem is
port (
In_a : in std_logic_vector(31 downto 0);
In_b : in std_logic_vector(31 downto 0);
In_dt : in std_logic_vector(31 downto 0);
In_g : in std_logic_vector(31 downto 0);
In_x : in std_logic_vector(31 downto 0);
In_y : in std_logic_vector(31 downto 0);
In_z : in std_logic_vector(31 downto 0);
Out_x : out std_logic_vector(31 downto 0);
Out_y : out std_logic_vector(31 downto 0);
Out_z : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
-- END DSP builder top level.
-- latency : 5 clock cycles (scale for DAC range)
component floatingPointMultiplyDedicated IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component floatingPointAddSubtract IS
PORT
(
aclr
: IN STD_LOGIC ;
add_sub
: IN STD_LOGIC ;
clk_en
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
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component pulseFSM is port (
reset,clock,trigger : in std_logic;
pulseOut,pulseOutSingleClockCycle : out std_logic);
end component;
component dFlipFlopWithAsyncReset is port (
clock,reset : in std_logic;
d,resetVal : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 781.250
KHz (64 counts of 50 MHz clock)
-- Since dt = 1/1024, time scale is actually (780.250e3/1024)
= 762 Hz (approximately)
-- since synchronous update count is integer, simply use a
process statement
process(incrementCountClockN,resetn)
begin
if resetn = '0' then
countIncrement <= 64;
else
if falling_edge(incrementCountClockN) then
if incrementCount = '1' then
countIncrement <= countIncrement+1;
else
countIncrement <= countIncrement-1;
end if;
end if;
end if;
end process;
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A800000"; -- 1/1024
output1Over5Scale <= X"3E4CCCCC";
output1Over2Scale <= X"3F000000";
-- default values for parameters and synchronous
count
alpha <= X"3DCCCCCC"; --0.1
beta <= X"3DCCCCCC"; --0.1
if resetn = '0' then
-- initial state
x <=
X"41680000"; -- 14.5
y <=
X"00000000"; -- 0
z <=
X"3DCCCCCC"; -- 0.1
count <= 0;
E.15 VHDL Specification of Period-Doubling Route to Chaos
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else
if rising_edge(clockIn) then
if count = countIncrement then
count <= 0;
else
count <= count + 1;
end if;
if count
x <=
y <=
z <=
end if;
end if;
= countIncrement-1 then
xNew;
yNew;
zNew;
end if;
end process;
incrementGammaClock <= not incrementGammaClockN;
pulseFSMForGamma : pulseFSM port map (
reset => reset,
clock => clockIn,
trigger => incrementGammaClock,
pulseOut => incrementDecrementGammaPulse,
pulseOutSingleClockCycle => dFlipFlopClock);
gammaParameterBifurcation : floatingPointAddSubtract port map
(
aclr => reset,
add_sub
=> incrementGamma, -- '1' = add, '0' =
subtract
clk_en => incrementDecrementGammaPulse,
clock
=> clockIn,
dataa
=> gamma, -- start at 12 = X"41400000". Memory
implemented using D flip-flop
datab
=> X"3DCCCCCC", -- increment/decrement by 0.1 =
X"3DCCCCCC"
result => gammaSignal);
-- we will need the flip-flop below to provide a proper initial
state.
gammaFlipFlop : dFlipFlopWithAsyncReset port map (
clock => dFlipFlopClock,
reset => reset,
d => gammaSignal,
resetVal => X"41400000", -- start at 12
q => gamma);
staticNonlinearitiesAndDeltaT :
rosslerSystem_NonlinearSubsystem port map (
In_a => alpha,
In_b => beta,
In_dt => dt,
In_g => gamma,
In_x => x,
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In_y => y,
In_z => z,
Out_x => xNew,
Out_y => yNew,
Out_z => zNew,
clk => clockIn,
areset => reset,
h_areset => reset);
-- END Euler's method
-- scale outputs
scaleX : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => x,
datab
=> output1Over2Scale,
result => xScaled);
scaleY : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => y,
datab
=> output1Over2Scale,
result => yScaled);
scaleZ : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => z,
datab
=> output1Over5Scale,
result => zScaled);
--state outputs : convert scaled floating point x,y variables
to 2.30 fixed point for DAC
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xScaled,
result
=> xFixed);
yOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> yScaled,
result
=> yFixed);
zOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> zScaled,
result
=> zFixed);
xOut <= xFixed(31 downto 16);
yOut <= yFixed(31 downto 16);
zOut <= zFixed(31 downto 16);
end behavioral;
E.16 VHDL Specification for Period-Adding Route to Chaos
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1. Lines 67 through 89 show how we have decided to implement the bifurcation scenario. Instead
of using DSP builder to increment (decrement) a parameter, we have utilized the MegaWizard.
The primary reason is that the increment or decrement of the bifurcation parameter simply
requires only one module : floating point addition and subtraction.
2. Lines 145 through 168 show how we implement the bifurcation. We generate two single-cycle
20 ns wide clock pulses using the pulse FSM. The first clock pulse is used as a clock enable signal for the appropriate floating point module that implements the bifurcation sequence. In this
example, we use the floating-point addsub module (lines 153 through 160) to specify gamma
as the bifurcation parameter. The second clock pulse is delayed by the appropriate number of
clock cycles (depending on the floating point module) and used to clock the bifurcation parameter register. In this design, we have a delay of nine clock cycles due to the eight clock cycle
latency associated with the floating-point addsub module.
E.16 VHDL Specification for Period-Adding Route to Chaos
Listing E.16: VHDL specification of period-adding bifurcation in the Chua system
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--Single precision (32-bit) floating point realization
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity chuaOscillator is port (
resetn, clockIn, incrementCountPulseN,incrementBetaPulseN
,incrementCount,incrementBeta : in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end chuaOscillator;
architecture behavioral of chuaOscillator is
signal reset,incrementBetaPulse,incrementDecrementBetaPulse,
dFlipFlopClock : std_logic;
-- constants
signal dt,outputScaledBy8,alpha,beta,betaSignal,gamma,a,c :
std_logic_vector(31 downto 0);
-- state variables
signal x,y,z,xNew,yNew,zNew,xScaled,yScaled,zScaled,xFixed,yFixed
,zFixed : std_logic_vector(31 downto 0);
-- prescalar
signal count,countIncrement : integer range 0 to 128;
-- DSP builder top level.
component chuaOscillator_NonlinearSubsystem is
port (
In_a : in std_logic_vector(31 downto 0);
In_alpha : in std_logic_vector(31 downto 0);
In_beta : in std_logic_vector(31 downto 0);
In_c : in std_logic_vector(31 downto 0);
In_dt : in std_logic_vector(31 downto 0);
In_gamma : in std_logic_vector(31 downto 0);
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E Chapter 4 MATLAB Code, VHDL and ModelSim Scripts
In_x : in std_logic_vector(31 downto 0);
In_y : in std_logic_vector(31 downto 0);
In_z : in std_logic_vector(31 downto 0);
Out_x : out std_logic_vector(31 downto 0);
Out_y : out std_logic_vector(31 downto 0);
Out_z : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic);
end component;
-- END DSP builder top level.
-- latency : 5 clock cycles (scale for DAC range)
component floatingPointMultiplyDedicated IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component floatingPointAddSubtract IS
PORT
(
aclr
: IN STD_LOGIC ;
add_sub
: IN STD_LOGIC ;
clk_en
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component pulseFSM is port (
reset,clock,trigger : in std_logic;
pulseOut,pulseOutSingleClockCycle : out std_logic);
end component;
component dFlipFlopWithAsyncReset is port (
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clock,reset : in std_logic;
d,resetVal : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 781.250
KHz (64 counts of 50 MHz clock)
-- Since dt = 1/1024, time scale is actually (780.250e3/1024)
= 762 Hz (approximately)
-- since synchronous update count is integer, simply use a
process statement
process(incrementCountPulseN,resetn)
begin
if resetn = '0' then
countIncrement <= 64;
else
if falling_edge(incrementCountPulseN) then
if incrementCount = '1' then
countIncrement <= countIncrement+1;
else
countIncrement <= countIncrement-1;
end if;
end if;
end if;
end process;
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A800000"; -- 1/1024
outputScaledBy8 <= X"41000000";
-- default values for parameters and synchronous
count
alpha <= X"406D4FDF"; -- 3.708, approximately
3.70799999
beta <= X"40666666"; -- 3.6, approximately
3.5999999
gamma <= X"3D9BA5E3"; -- 0.076, approximately
0.0759999
a <= X"3F800000"; -- 1
c <= X"BE8D4FDF"; -- -0.276, approximately
-0.27599999
if resetn = '0' then
-- initial state
x <=
X"3DCCCCCC"; -- 0.1
y <=
X"00000000"; -- 0
z <=
X"3DCCCCCC"; -- 0.1
count <= 0;
else
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----------
154
155
---
156
157
158
----
159
--
160
161
162
------ we will need the flip-flop below to provide a proper initial
state.
-- betaFlipFlop : dFlipFlopWithAsyncReset port map (
-clock => dFlipFlopClock,
-reset => reset,
-d => betaSignal,
-resetVal => X"", -- start at ??????????
-q => beta);
-staticNonlinearitiesAndDeltaT :
chuaOscillator_NonlinearSubsystem port map (
In_a => a,
In_alpha => alpha,
In_beta => beta,
In_c => c,
In_dt => dt,
In_gamma => gamma,
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if rising_edge(clockIn) then
if count = countIncrement then
count <= 0;
else
count <= count + 1;
end if;
if count
x <=
y <=
z <=
end if;
end if;
= countIncrement-1 then
xNew;
yNew;
zNew;
end if;
end process;
incrementBetaPulse <= not incrementBetaPulseN;
pulseFSMForBeta : pulseFSM port map (
reset => reset,
clock => clockIn,
trigger => incrementBetaPulse,
pulseOut => incrementDecrementBetaPulse,
pulseOutSingleClockCycle => dFlipFlopClock);
betaParameterBifurcation : floatingPointAddSubtract port map
(
aclr => reset,
add_sub
=> incrementBeta, -- '1' = add, '0' =
subtract
clk_en => incrementDecrementBetaPulse,
clock
=> clockIn,
dataa
=> beta, -- start at ????????. Memory
implemented using D flip-flop
datab
=> X"", -- increment/decrement by ???? = X
"??????????"
result => betaSignal);
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In_x => x,
In_y => y,
In_z => z,
Out_x => xNew,
Out_y => yNew,
Out_z => zNew,
clk => clockIn,
areset => reset,
h_areset => reset);
-- END Euler's method
-- scale outputs
scaleX : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => x,
datab
=> outputScaledBy8,
result => xScaled);
scaleY : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => y,
datab
=> outputScaledBy8,
result => yScaled);
scaleZ : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => z,
datab
=> outputScaledBy8,
result => zScaled);
--state outputs : convert scaled floating point x,y variables
to 2.30 fixed point for DAC
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xScaled,
result
=> xFixed);
yOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> yScaled,
result
=> yFixed);
zOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> zScaled,
result
=> zFixed);
xOut <= xFixed(31 downto 16);
yOut <= yFixed(31 downto 16);
zOut <= zFixed(31 downto 16);
end behavioral;
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E.17 VHDL Specification for Quasi-Periodic Route to Chaos
Listing E.17: VHDL specification of quasi-periodic route to chaos via
torus-breakdown
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--Single precision (32-bit) floating point realization
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity torusBreakdown is port (
resetn, clockIn, incrementCountPulseN,
incrementAlphaPulseN,incrementCount,incrementAlpha :
in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end torusBreakdown;
architecture behavioral of torusBreakdown is
signal reset,incrementAlphaPulse,incrementDecrementAlphaPulse,
dFlipFlopClock : std_logic;
-- constants
signal dt,outputScaledBy4,alpha,beta,alphaSignal,a,b :
std_logic_vector(31 downto 0);
-- state variables
signal x,y,z,xNew,yNew,zNew,xScaled,yScaled,zScaled,xFixed,yFixed
,zFixed : std_logic_vector(31 downto 0);
-- prescalar
signal count,countIncrement : integer range 0 to 128;
-- DSP builder top level.
component torusBreakdown_NonlinearSubsystem is
port (
In_a : in std_logic_vector(31 downto 0);
In_alpha : in std_logic_vector(31 downto 0);
In_b : in std_logic_vector(31 downto 0);
In_beta : in std_logic_vector(31 downto 0);
In_dt : in std_logic_vector(31 downto 0);
In_x : in std_logic_vector(31 downto 0);
In_y : in std_logic_vector(31 downto 0);
In_z : in std_logic_vector(31 downto 0);
Out_x : out std_logic_vector(31 downto 0);
Out_y : out std_logic_vector(31 downto 0);
Out_z : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic);
end component;
-- END DSP builder top level.
-- latency : 5 clock cycles (scale for DAC range)
component floatingPointMultiplyDedicated IS
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PORT
(
aclr
clock
dataa
datab
result
);
END component;
:
:
:
:
:
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IN STD_LOGIC ;
IN STD_LOGIC ;
IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component floatingPointAddSubtract IS
PORT
(
aclr
: IN STD_LOGIC ;
add_sub
: IN STD_LOGIC ;
clk_en
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component pulseFSM is port (
reset,clock,trigger : in std_logic;
pulseOut,pulseOutSingleClockCycle : out std_logic);
end component;
component dFlipFlopWithAsyncReset is port (
clock,reset : in std_logic;
d,resetVal : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 781.250
KHz (64 counts of 50 MHz clock)
-- Since dt = 1/1024, time scale is actually (780.250e3/1024)
= 762 Hz (approximately)
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-- since synchronous update count is integer, simply use a
process statement
process(incrementCountPulseN,resetn)
begin
if resetn = '0' then
countIncrement <= 64;
else
if falling_edge(incrementCountPulseN) then
if incrementCount = '1' then
countIncrement <= countIncrement+1;
else
countIncrement <= countIncrement-1;
end if;
end if;
end if;
end process;
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A800000"; -- 1/1024
-- default values for parameters and synchronous
count
beta <= X"3F800000"; -- 1
outputScaledBy4 <= X"40800000";
a <= X"3D8F5C28"; -- 0.07, approximately 0.069999
b <= X"3DCCCCCC"; -- 0.1, approximately 0.099999
if resetn = '0' then
-- initial state
x <=
X"3DCCCCCC"; -- 0.1
y <=
X"00000000"; -- 0
z <=
X"3DCCCCCC"; -- 0.1
count <= 0;
else
if rising_edge(clockIn) then
if count = countIncrement then
count <= 0;
else
count <= count + 1;
end if;
if count
x <=
y <=
z <=
end if;
end if;
= countIncrement-1 then
xNew;
yNew;
zNew;
end if;
end process;
incrementAlphaPulse <= not incrementAlphaPulseN;
pulseFSMForAlpha : pulseFSM port map (
reset => reset,
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clock => clockIn,
trigger => incrementAlphaPulse,
pulseOut => incrementDecrementAlphaPulse,
pulseOutSingleClockCycle => dFlipFlopClock);
alphaParameterBifurcation : floatingPointAddSubtract port map
(
aclr => reset,
add_sub
=> incrementAlpha, -- '1' = add, '0' =
subtract
clk_en => incrementDecrementAlphaPulse,
clock
=> clockIn,
dataa
=> alpha, -- start at 15. Memory implemented
using D flip-flop
datab
=> X"3DCCCCCC", -- increment/decrement by 0.1 =
X"3DCCCCCC"
result => alphaSignal);
-- we will need the flip-flop below to provide a proper initial
state.
alphaFlipFlop : dFlipFlopWithAsyncReset port map (
clock => dFlipFlopClock,
reset => reset,
d => alphaSignal,
resetVal => X"41700000", -- start at 15
q => alpha);
-staticNonlinearitiesAndDeltaT :
torusBreakdown_NonlinearSubsystem port map (
In_a => a,
In_alpha => alpha,
In_b => b,
In_beta => beta,
In_dt => dt,
In_x => x,
In_y => y,
In_z => z,
Out_x => xNew,
Out_y => yNew,
Out_z => zNew,
clk => clockIn,
areset => reset,
h_areset => reset);
-- END Euler's method
-- scale outputs
scaleX : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => x,
datab
=> outputScaledBy4,
result => xScaled);
scaleY : floatingPointMultiplyDedicated port map (
aclr => reset,
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clock
=> clockIn,
dataa => y,
datab
=> outputScaledBy4,
result => yScaled);
scaleZ : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => z,
datab
=> outputScaledBy4,
result => zScaled);
--state outputs : convert scaled floating point x,y variables
to 2.30 fixed point for DAC
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xScaled,
result
=> xFixed);
yOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> yScaled,
result
=> yFixed);
zOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> zScaled,
result
=> zFixed);
xOut <= xFixed(31 downto 16);
yOut <= yFixed(31 downto 16);
zOut <= zFixed(31 downto 16);
end behavioral;
E.18 VHDL Specification for Chaotic Transients
Listing E.18: VHDL specification of chaotic transients
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--Single precision (32-bit) floating point realization
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity torusBreakdown is port (
resetn, clockIn, incrementCountPulseN,
incrementAlphaPulseN,incrementCount,incrementAlpha :
in std_logic;
xOut,yOut,zOut : out std_logic_vector(15 downto 0));
end torusBreakdown;
architecture behavioral of torusBreakdown is
E.18 VHDL Specification for Chaotic Transients
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signal reset,incrementAlphaPulse,incrementDecrementAlphaPulse,
dFlipFlopClock : std_logic;
-- constants
signal dt,outputScaledBy4,alpha,beta,alphaSignal,a,b :
std_logic_vector(31 downto 0);
-- state variables
signal x,y,z,xNew,yNew,zNew,xScaled,yScaled,zScaled,xFixed,yFixed
,zFixed : std_logic_vector(31 downto 0);
-- prescalar
signal count,countIncrement : integer range 0 to 128;
-- DSP builder top level.
component torusBreakdown_NonlinearSubsystem is
port (
In_a : in std_logic_vector(31 downto 0);
In_alpha : in std_logic_vector(31 downto 0);
In_b : in std_logic_vector(31 downto 0);
In_beta : in std_logic_vector(31 downto 0);
In_dt : in std_logic_vector(31 downto 0);
In_x : in std_logic_vector(31 downto 0);
In_y : in std_logic_vector(31 downto 0);
In_z : in std_logic_vector(31 downto 0);
Out_x : out std_logic_vector(31 downto 0);
Out_y : out std_logic_vector(31 downto 0);
Out_z : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic);
end component;
-- END DSP builder top level.
-- latency : 5 clock cycles (scale for DAC range)
component floatingPointMultiplyDedicated IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
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E Chapter 4 MATLAB Code, VHDL and ModelSim Scripts
component floatingPointAddSubtract IS
PORT
(
aclr
: IN STD_LOGIC ;
add_sub
: IN STD_LOGIC ;
clk_en
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component pulseFSM is port (
reset,clock,trigger : in std_logic;
pulseOut,pulseOutSingleClockCycle : out std_logic);
end component;
component dFlipFlopWithAsyncReset is port (
clock,reset : in std_logic;
d,resetVal : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 781.250
KHz (64 counts of 50 MHz clock)
-- Since dt = 1/1024, time scale is actually (780.250e3/1024)
= 762 Hz (approximately)
-- since synchronous update count is integer, simply use a
process statement
process(incrementCountPulseN,resetn)
begin
if resetn = '0' then
countIncrement <= 64;
else
if falling_edge(incrementCountPulseN) then
if incrementCount = '1' then
countIncrement <= countIncrement+1;
else
countIncrement <= countIncrement-1;
end if;
end if;
end if;
end process;
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
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dt <= X"3A800000"; -- 1/1024
-- default values for parameters and synchronous
count
beta <= X"3F800000"; -- 1
outputScaledBy4 <= X"40800000";
a <= X"3D8F5C28"; -- 0.07, approximately 0.069999
b <= X"3DCCCCCC"; -- 0.1, approximately 0.099999
if resetn = '0' then
-- initial state
x <=
X"3DCCCCCC"; -- 0.1
y <=
X"00000000"; -- 0
z <=
X"3DCCCCCC"; -- 0.1
count <= 0;
else
if rising_edge(clockIn) then
if count = countIncrement then
count <= 0;
else
count <= count + 1;
end if;
if count
x <=
y <=
z <=
end if;
end if;
= countIncrement-1 then
xNew;
yNew;
zNew;
end if;
end process;
incrementAlphaPulse <= not incrementAlphaPulseN;
pulseFSMForAlpha : pulseFSM port map (
reset => reset,
clock => clockIn,
trigger => incrementAlphaPulse,
pulseOut => incrementDecrementAlphaPulse,
pulseOutSingleClockCycle => dFlipFlopClock);
alphaParameterBifurcation : floatingPointAddSubtract port map
(
aclr => reset,
add_sub
=> incrementAlpha, -- '1' = add, '0' =
subtract
clk_en => incrementDecrementAlphaPulse,
clock
=> clockIn,
dataa
=> alpha, -- start at 15. Memory implemented
using D flip-flop
datab
=> X"3DCCCCCC", -- increment/decrement by 0.1 =
X"3DCCCCCC"
result => alphaSignal);
-- we will need the flip-flop below to provide a proper initial
state.
alphaFlipFlop : dFlipFlopWithAsyncReset port map (
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E Chapter 4 MATLAB Code, VHDL and ModelSim Scripts
clock => dFlipFlopClock,
reset => reset,
d => alphaSignal,
resetVal => X"41700000", -- start at 15
q => alpha);
-staticNonlinearitiesAndDeltaT :
torusBreakdown_NonlinearSubsystem port map (
In_a => a,
In_alpha => alpha,
In_b => b,
In_beta => beta,
In_dt => dt,
In_x => x,
In_y => y,
In_z => z,
Out_x => xNew,
Out_y => yNew,
Out_z => zNew,
clk => clockIn,
areset => reset,
h_areset => reset);
-- END Euler's method
-- scale outputs
scaleX : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => x,
datab
=> outputScaledBy4,
result => xScaled);
scaleY : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => y,
datab
=> outputScaledBy4,
result => yScaled);
scaleZ : floatingPointMultiplyDedicated port map (
aclr => reset,
clock
=> clockIn,
dataa => z,
datab
=> outputScaledBy4,
result => zScaled);
--state outputs : convert scaled floating point x,y variables
to 2.30 fixed point for DAC
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xScaled,
result
=> xFixed);
yOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
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dataa
=> yScaled,
result
=> yFixed);
zOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> zScaled,
result
=> zFixed);
xOut <= xFixed(31 downto 16);
yOut <= yFixed(31 downto 16);
zOut <= zFixed(31 downto 16);
end behavioral;
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Appendix F
Chapter 5 VHDL
F.1 Flip-flops in VHDL
Listing F.1: VHDL specification of D flip-flop with asynchronous reset
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library ieee;
use ieee.std_logic_1164.all;
entity dFlipFlopWithAsyncReset is port (
clock,reset : in std_logic;
d : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end dFlipFlopWithAsyncReset;
architecture structuralDFlipFlop of dFlipFlopWithAsyncReset is
begin
process (clock,reset)
begin
if reset = '1' then
q <= X"00000000";
else
if rising_edge(clock) then
q <= d;
end if;
end if;
end process;
end structuralDFlipFlop;
F.2 VHDL Tapped Delay Line
Listing F.2: Realization of VHDL delay
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F Chapter 5 VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity addressableShiftRegister is
generic (numberOfFlipFlops : integer := 0;
delay : integer := 0);
port (
clk,areset : in std_logic;
In_x : in std_logic_vector(31 downto 0);
Out_xDelayed : out std_logic_vector(31 downto 0));
end addressableShiftRegister;
architecture behavioral of addressableShiftRegister is
component dFlipFlopWithAsyncRChap9eset is port (
clock,reset : in std_logic;
d : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;
type memory is array(0 to numberOfFlipFlops) of
std_logic_vector(31 downto 0);
signal internalDataArray : memory;
begin
internalDataArray(0) <= In_x;
generateFlipFlops:
for i IN 0 to numberOfFlipFlops-1 generate
nFlipFlops : dFlipFlopWithAsyncReset port map (
clock => clk,
reset => areset,
d => internalDataArray(i),
q => internalDataArray(i+1));
end generate;
Out_xDelayed <= internalDataArray(delay-1);
end behavioral;
F.3 VHDL Specification of Ikeda DDE
Listing F.3: Realization of Ikeda DDE
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-- In order to implement a DDE, we need to implement two modules:
-- 1. An addressable shift register that implements the delay (
refer to addressableShiftRegister subsystem)
-- 2. An appropriate clock for the addressable shift register,
based on the global clock divider. The
addressableShiftRegisterClock has 2x the count of the clock
F.3 VHDL Specification of Ikeda DDE
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-- divider. Hence, the rising edge for the addressable shift
register clock occurs whenever the 50 MHz clock divider count
overflows.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity ikedaDDESystem is port (
resetn, clockIn : in std_logic;
xFloatOut,xDelayedFloatOut : out std_logic_vector(31
downto 0);
xOut,xDelayedOut : out std_logic_vector(15 downto 0);
syncIn : in std_logic_vector(31 downto 0);
syncClock : out std_logic);
end ikedaDDESystem;
architecture behavioral of ikedaDDESystem is
signal reset : std_logic;
-- constants
signal dt : std_logic_vector(31 downto 0);
-- state variables
signal x,xDelayed,xNew,xFixed,xDelayedFixed : std_logic_vector(31
downto 0);
-- prescalar
signal count: integer range 0 to 64;
signal addressableShiftRegisterCount : integer range 0 to 128;
signal addressableShiftRegisterClock : std_logic;
signal internalSyncClockCount : integer range 0 to 2048;
signal internalSyncClock : std_logic;
-- DSP builder top level.
Add both the nonlinear subsystem and
nonlinear synthesizable
-- subsystem VHDL files to project.
component ikedaDDE_NonlinearSubsystem is
port (
In_dt : in std_logic_vector(31 downto 0);
In_sync : in std_logic_vector(31 downto 0);
In_x : in std_logic_vector(31 downto 0);
In_xDelayed : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic);
end component;
-- END DSP builder top level.
component addressableShiftRegister is
generic (numberOfFlipFlops : integer := 0;
delay : integer := 0);
port (
clk,areset : in std_logic;
In_x : in std_logic_vector(31 downto 0);
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F Chapter 5 VHDL
Out_xDelayed : out std_logic_vector(31 downto 0));
end component;
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 781.250
KHz (64 counts of 50 MHz clock)
-- Since dt = 1/1024, time scale is actually (781.250e3/1024)
= 762 Hz (approximately)
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A800000"; -- 1/1024
if resetn = '0' then
-- initial state
x <=
X"3DCCCCCC";-- 0.1
count <= 0;
addressableShiftRegisterCount <= 0;
addressableShiftRegisterClock <= '0';
else
if rising_edge(clockIn) then
if count = 64 then
count <= 0;
else
count <= count + 1;
end if;
if count = 63 then
x <= xNew;
end if;
if addressableShiftRegisterCount = 128 then
addressableShiftRegisterCount <= 0;
else
addressableShiftRegisterCount <=
addressableShiftRegisterCount + 1;
end if;
F.3 VHDL Specification of Ikeda DDE
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if addressableShiftRegisterCount >= 63 then
addressableShiftRegisterClock <= '1';
else
addressableShiftRegisterClock <= '0';
end if;
-- for synchronizer period
if internalSyncClockCount = 2048 then
internalSyncClockCount <= 0;
else
internalSyncClockCount <=
internalSyncClockCount + 1;
end if;
if internalSyncClockCount >= 1023 then
internalSyncClock <= '1';
else
internalSyncClock <= '0';
end if;
end if;
end if;
end process;
-- this design also includes synchronization
-- since y(t+dt)=y(t)+(-alpha*y+mu*sin(y(t-tau))+k(t)(x(t)-y(
t)))*dt,
-- we also send in the sync signal into the DSP builder
nonlinear subsystem.
staticNonlinearities : ikedaDDE_NonlinearSubsystem port map (
In_dt => dt,
In_sync => syncIn,
In_x => x,
In_xDelayed => xDelayed,
y => xNew,
clk => clockIn,
areset => reset,
h_areset => reset);
delay : addressableShiftRegister generic map (
numberOfFlipFlops => 2048,delay => 1024)
port map (
In_x => x,
Out_xDelayed => xDelayed,
clk => addressableShiftRegisterClock,
areset => reset);
-- END Euler's method
--state outputs : convert scaled floating point variables to
5.27 fixed point format DAC (no latency)
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
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F Chapter 5 VHDL
dataa
=> x,
result
=> xFixed);
xDelayedOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xDelayed,
result
=> xDelayedFixed);
xOut <= xFixed(31 downto 16);
xDelayedOut <= xDelayedFixed(31 downto 16);
xFloatOut <= x;
xDelayedFloatOut <= xDelayed;
syncClock <= internalSyncClock;
end behavioral;
F.4 VHDL Specification of DDE with Sigmoidal Nonlinearity
Listing F.4: Realization of Sigmoidal DDE
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity sigmoidDDESystem is port (
resetn, clockIn : in std_logic;
xFloatOut,xDelayedFloatOut : out std_logic_vector(31
downto 0);
xOut,xDelayedOut : out std_logic_vector(15 downto 0);
syncIn : in std_logic_vector(31 downto 0);
syncClock : out std_logic);
end sigmoidDDESystem;
architecture behavioral of sigmoidDDESystem is
signal reset : std_logic;
-- constants
signal dt : std_logic_vector(31 downto 0);
-- state variables
signal x,xDelayed,xNew,xFixed,xDelayedFixed : std_logic_vector(31
downto 0);
-- prescalar
signal count: integer range 0 to 64;
signal addressableShiftRegisterCount : integer range 0 to 128;
signal addressableShiftRegisterClock : std_logic;
signal internalSyncClockCount : integer range 0 to 2048;
signal internalSyncClock : std_logic;
-- DSP builder top level.
Add both the nonlinear subsystem and
nonlinear synthesizable
-- subsystem VHDL files to project.
component sigmoidalDDE_NonlinearSubsystem is
F.4 VHDL Specification of DDE with Sigmoidal Nonlinearity
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port (
In_dt : in std_logic_vector(31 downto 0);
In_sync : in std_logic_vector(31 downto 0);
In_x : in std_logic_vector(31 downto 0);
In_xDelayed : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
-- END DSP builder top level.
component addressableShiftRegister is
generic (numberOfFlipFlops : integer := 0;
delay : integer := 0);
port (
clk,areset : in std_logic;
In_x : in std_logic_vector(31 downto 0);
Out_xDelayed : out std_logic_vector(31 downto 0));
end component;
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 3.125 MHz
(16 counts of 50 MHz clock)
-- Since dt = 1/1000, time scale is actually (3.125e6/1000) =
3.125 kHz (approximately)
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A83126E"; -- 1/1000
if resetn = '0' then
-- initial state
x <=
X"3DCCCCCC";-- 0.1
count <= 0;
addressableShiftRegisterCount <= 0;
addressableShiftRegisterClock <= '0';
else
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if rising_edge(clockIn) then
if count = 16 then
count <= 0;
else
count <= count + 1;
end if;
if count = 15 then
x <= xNew;
end if;
if addressableShiftRegisterCount = 16 then
addressableShiftRegisterCount <= 0;
else
addressableShiftRegisterCount <=
addressableShiftRegisterCount + 1;
end if;
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if addressableShiftRegisterCount >= 7 then
addressableShiftRegisterClock <= '1';
else
addressableShiftRegisterClock <= '0';
end if;
-- for synchronizer period
if internalSyncClockCount = 2048 then
internalSyncClockCount <= 0;
else
internalSyncClockCount <=
internalSyncClockCount + 1;
end if;
if internalSyncClockCount >= 1023 then
internalSyncClock <= '1';
else
internalSyncClock <= '0';
end if;
end if;
end if;
end process;
-- this design also includes synchronization, so we also send
in the sync signal into the DSP builder nonlinear
subsystem.
staticNonlinearities : sigmoidalDDE_NonlinearSubsystem port
map (
In_dt => dt,
In_sync => syncIn,
In_x => x,
In_xDelayed => xDelayed,
y => xNew,
clk => clockIn,
F.5 VHDL Specification of DDE with Signum Nonlinearity
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areset => reset,
h_areset => reset);
delay : addressableShiftRegister generic map (
numberOfFlipFlops => 4096,delay => 3000)
port map (
In_x => x,
Out_xDelayed => xDelayed,
clk => addressableShiftRegisterClock,
areset => reset);
-- END Euler's method
--state outputs : convert scaled floating point variables to
5.27 fixed point format DAC (no latency)
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> x,
result
=> xFixed);
xDelayedOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xDelayed,
result
=> xDelayedFixed);
xOut <= xFixed(31 downto 16);
xDelayedOut <= xDelayedFixed(31 downto 16);
xFloatOut <= x;
xDelayedFloatOut <= xDelayed;
syncClock <= internalSyncClock;
end behavioral;
F.5 VHDL Specification of DDE with Signum Nonlinearity
Listing F.5: Realization of Signum DDE
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity signumDDESystem is port (
resetn, clockIn : in std_logic;
xFloatOut,xDelayedFloatOut : out std_logic_vector(31
downto 0);
xOut,xDelayedOut : out std_logic_vector(15 downto 0);
syncIn : in std_logic_vector(31 downto 0);
syncClock : out std_logic);
end signumDDESystem;
architecture behavioral of signumDDESystem is
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F Chapter 5 VHDL
signal reset : std_logic;
-- constants
signal dt : std_logic_vector(31 downto 0);
-- state variables
signal x,xDelayed,xNew,xFixed,xDelayedFixed,f1,f2,f :
std_logic_vector(31 downto 0);
-- prescalar
signal count: integer range 0 to 64;
signal addressableShiftRegisterCount : integer range 0 to 128;
signal addressableShiftRegisterClock : std_logic;
signal internalSyncClockCount : integer range 0 to 2048;
signal internalSyncClock : std_logic;
-- We do not use DSP builder for the signum system since the
signum function is very easy to implement:
-- from http://en.wikipedia.org/wiki/Single-precision_floatingpoint_format
-- sign bit is MSb, +0 = 0x00000000, -0 = 0x80000000
-- System: x'=sgn(x(t-2))-x(t-2), x(t <= 0) = 0.1
signal isZero,signbit : std_logic;
signal signbitOut : std_logic_vector(31 downto 0);
component addressableShiftRegister is
generic (numberOfFlipFlops : integer := 0;
delay : integer := 0);
port (
clk,areset : in std_logic;
In_x : in std_logic_vector(31 downto 0);
Out_xDelayed : out std_logic_vector(31 downto 0));
end component;
-- latency : 6 clock cycles
component floatingPointToFixed IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
-- add_sub = '1' for addition, else subtraction
component floatingPointAddSubtract IS
PORT
(
aclr
: IN STD_LOGIC ;
add_sub
: IN STD_LOGIC ;
clk_en
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
F.5 VHDL Specification of DDE with Signum Nonlinearity
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);
END component;
component floatingPointMultiplyDedicated IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
begin
reset <= not resetn;
-- Euler's method
-- We first synchronously update state variables at 3.125 MHz
(16 counts of 50 MHz clock)
-- Since dt = 1/1000, time scale is actually (3.125e6/1000) =
3.125 kHz (approximately)
-- state memory
process(clockIn, resetn)
begin
-- constants (place outside reset and clock to
avoid latches)
dt <= X"3A83126E"; -- 1/1000
if resetn = '0' then
-- initial state
x <=
X"3DCCCCCC";-- 0.1
count <= 0;
addressableShiftRegisterCount <= 0;
addressableShiftRegisterClock <= '0';
else
if rising_edge(clockIn) then
if count = 16 then
count <= 0;
else
count <= count + 1;
end if;
if count = 15 then
x <= xNew;
end if;
if addressableShiftRegisterCount = 16 then
addressableShiftRegisterCount <= 0;
else
addressableShiftRegisterCount <=
addressableShiftRegisterCount + 1;
end if;
if addressableShiftRegisterCount >= 7 then
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addressableShiftRegisterClock <= '1';
else
addressableShiftRegisterClock <= '0';
end if;
-- for synchronizer period
if internalSyncClockCount = 2048 then
internalSyncClockCount <= 0;
else
internalSyncClockCount <=
internalSyncClockCount + 1;
end if;
if internalSyncClockCount >= 1023 then
internalSyncClock <= '1';
else
internalSyncClock <= '0';
end if;
end if;
end if;
end process;
-- this design could include synchronization
delay : addressableShiftRegister generic map (
numberOfFlipFlops => 4096,delay => 2000)
port map (
In_x => x,
Out_xDelayed => xDelayed,
clk => addressableShiftRegisterClock,
areset => reset);
-- compute f1=sgn(x(t-2))
with xDelayed select
isZero <= '1' when X"00000000",
'1' when X"80000000",
'0' when others;
signBit <= xDelayed(31);
with signBit select
signBitOut <= X"3F800000" when '0', -- +1
X"BF800000" when others; -- -1
with isZero select
f1 <= signBitOut when '0',
X"00000000" when others;
-- compute f2=sgn(x(t-2))-x(t-2)=f1-xDelayed
f2Out : floatingPointAddSubtract port map (
aclr => reset,
add_sub => '0',
clk_en => '1',
clock
=> clockIn,
dataa
=> f1,
datab
=> xDelayed,
result => f2);
F.6 VHDL Specification for Chaotic DDE Synchronization
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-- compute f=f2*dt
fOut : floatingPointMultiplyDedicated port map (
aclr => reset,
clock => clockIn,
dataa => f2,
datab
=> dt,
result => f);
-- compute xNew = x+f
xNewOut : floatingPointAddSubtract port map (
aclr => reset,
add_sub => '1',
clk_en => '1',
clock
=> clockIn,
dataa
=> x,
datab
=> f,
result => xNew);
-- END Euler's method
--state outputs : convert scaled floating point variables to
5.27 fixed point format DAC (no latency)
xOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> x,
result
=> xFixed);
xDelayedOutFinal : floatingPointToFixed port map (
aclr => reset,
clock => clockIn,
dataa
=> xDelayed,
result
=> xDelayedFixed);
xOut <= xFixed(31 downto 16);
xDelayedOut <= xDelayedFixed(31 downto 16);
xFloatOut <= x;
xDelayedFloatOut <= xDelayed;
syncClock <= internalSyncClock;
end behavioral;
F.6 VHDL Specification for Chaotic DDE Synchronization
Listing F.6: VHDL module for implementing synchronization schemes
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity
synchronizer is port (
resetn,clockIn,syncMode,xMinusYIn : in std_logic;
syncClock : in std_logic;
xIn,yIn,yDelayedIn : in std_logic_vector(31 downto 0);
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F Chapter 5 VHDL
syncOut : out std_logic_vector(31 downto 0));
end synchronizer;
architecture synchronizationSystem of synchronizer is
-- add_sub = '1' for addition, else subtraction
component floatingPointAddSubtract IS
PORT
(
aclr
: IN STD_LOGIC ;
add_sub
: IN STD_LOGIC ;
clk_en
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component floatingPointMultiplyDedicated IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
dataa
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component floatingPointCos IS
PORT
(
aclr
: IN STD_LOGIC ;
clock
: IN STD_LOGIC ;
data
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
component floatingPointAbs IS
PORT
(
aclr
: IN STD_LOGIC ;
data
: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result
: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END component;
signal reset : std_logic;
signal xMinusY,yMinusX,kTimesXMinusY,kTimesYMinusX,
kSquareWaveTimesXMinusY,kSquareWaveTimesYMinusX,
kCosineTimesXMinusY,kCosineTimesYMinusX :
std_logic_vector(31 downto 0);
F.6 VHDL Specification for Chaotic DDE Synchronization
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signal cosineOut,absOut,k1,cosCoupling : std_logic_vector(31
downto 0);
signal k,alpha,twoTimesMu : std_logic_vector(31 downto 0);
begin
reset <= not resetn;
alpha <= X"40A00000"; -- alpha = 5
twoTimesMu <= X"42200000"; -- two*mu = 2*20 = 40
-- generate x-y and y-x using megaWizard. We chose to use
the megaWizard because DSP builder is too much effort for
something as simple as floating point subtraction
xMinusYInstance : floatingPointAddSubtract port map (
aclr => reset,
add_sub => '0', -- dataa - datab
clk_en => '1',
clock => clockIn,
dataa => xIn,
datab => yIn,
result => XMinusY);
yMinusXInstance : floatingPointAddSubtract port map (
aclr => reset,
add_sub => '0', -- dataa - datab
clk_en => '1',
clock => clockIn,
dataa => yIn,
datab => xIn,
result => YMinusX);
-- generate square wave based on delayed clock
with syncClock select
k <= X"00000000" when '0',
X"42480000" when others; -- square wave
amplitude is 50
-- generate k(t) = -alpha+2*mu*|cos(y(t-tau))|
-- compute cosine
cosineYDelay : floatingPointCos port map (
aclr
=> reset,
clock
=> clockIn,
data
=> yDelayedIn,
result => cosineOut);
-- compute abs
absOfCos : floatingPointAbs port map (
aclr
=> reset,
data => cosineOut,
result => absOut);
-- compute product: 2*mu*|cos(y(t-tau))|
cosCouplingProductTerm : floatingPointMultiplyDedicated port
map (
aclr => reset,
clock => clockIn,
dataa
=> twoTimesMu,
datab
=> absOut,
result => k1);
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-- subtract from alpha
cosineCouplingOut : floatingPointAddSubtract port map (
aclr => reset,
add_sub => '0', -- dataa - datab
clk_en => '1',
clock => clockIn,
dataa => k1,
datab => alpha,
result => cosCoupling);
-- generate k*(x-y), k*(y-x) (k is square wave)
kSquareWaveTimesXMinusYInstance :
floatingPointMultiplyDedicated port map (
aclr => reset,
clock => clockIn,
dataa => k,
datab => XMinusY,
result => kSquareWaveTimesXMinusY);
kSquareWaveTimesYMinusXInstance :
floatingPointMultiplyDedicated port map (
aclr => reset,
clock => clockIn,
dataa => k,
datab => YMinusX,
result => kSquareWaveTimesYMinusX);
-- generate k*(x-y), k*(y-x) (k is cosine coupling)
kCosineTimesXMinusYInstance : floatingPointMultiplyDedicated
port map (
aclr => reset,
clock => clockIn,
dataa => k,
datab => XMinusY,
result => kCosineTimesXMinusY);
kCosineTimesYMinusXInstance : floatingPointMultiplyDedicated
port map (
aclr => reset,
clock => clockIn,
dataa => k,
datab => YMinusX,
result => kCosineTimesYMinusX);
-- syncMode: '0' - square wave coupling, '1' - cosine
coupling
with syncMode select
kTimesXMinusY <= kSquareWaveTimesXMinusY when '0',
kCosineTimesXMinusY
when others;
with syncMode select
kTimesYMinusX <= kSquareWaveTimesYMinusX when '0',
F.7 DE2 Chaotic DDE Specification Top Level
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kCosineTimesYMinusX
when others;
with xMinusYIn select
syncOut <= kTimesXMinusY when '1',
kTimesYMinusX when others;
end synchronizationSystem;
F.7 DE2 Chaotic DDE Specification Top Level
Listing F.7: VHDL top level for implementing synchronization scheme for DDEs
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-- DE2-115 Audio codec interface for analog chaotic signals
output from chaotic DDEs
-- Reference design for EPJ-ST paper - "Synchronization in
Coupled Ikeda Delay Differential Equations : Experimental
Observations using Field
-- Programmable Gate Arrays", Valli, D. et. al.
-- i2c Audio codec interface courtesy of Stapleton, Colin, EE2902
Spring 2011, Milwaukee School of Engineering, 4/15/11
-- adc_dac interface courtesy of Chu, Embedded SOPC Design with
VHDL, pp. 545-546, 4/8/13
-- Based on chaos engine created by Dr. Muthuswamy (AY 2013-2014)
, primarily for the book:
-- "A Route to Chaos Using FPGAs - Volumes I and II"
-- DSP builder based design
-- IMPORTANT : NEED TO SET nCEO as regular I/O via Device and Pin
Options
-- KEY(0): global reset
-- KEY(1): bifurcation parameter control (see SW(2) below), but
this is not used in this design.
-- SW(0) : loopback (switch down or SW(0)='0') or chaotic
dynamics (switch up or SW(0)='1' (default))
-- SW(1) : select between drive (switch down or SW(0)='0') and
sync error signal (switch up or SW(0)='1', e(t) for square
wave is on left-channel. e(t) for cosine on right channel)
-- SW(2) : bifurcation parameter decrement (switch down or SW(2)
= '0') or increment (switch up or SW(2) = '1' (default)).
This is not used in this design.
-- left channel data is controlled by SW(4 downto 3)
-- right channel data is controlled by SW(6 downto 5)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all; -- need to subtract
std_logic_vectors for synchronization result
entity DE2ChaoticDDEs is
port(
KEY: in std_logic_vector(3 downto 0);
CLOCK_50: in std_logic;
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F Chapter 5 VHDL
--I2C ports
I2C_SCLK: out std_logic;
I2C_SDAT: inout std_logic;
--audio codec ports
AUD_ADCDAT: in std_logic;
AUD_ADCLRCK: out std_logic;
AUD_DACLRCK: out std_logic;
AUD_DACDAT: out std_logic;
AUD_XCK: out std_logic;
AUD_BCLK: out std_logic;
--select loopback test or neuron model output
SW: in std_logic_vector(17 downto 0);
--output for logic analyzer
GPIO: inout std_logic_vector (35 downto 0);
HEX3,HEX2,HEX1,HEX0: out std_logic_vector(6 downto 0);
LEDG: out std_logic_vector (8 downto 0)
);
end DE2ChaoticDDEs;
architecture toplevel of DE2ChaoticDDEs is
--PLL from MegaWizard in Quartus.
--both input and output are 50MHz
component clockBuffer IS
PORT
(
areset
: IN STD_LOGIC
inclk0
: IN STD_LOGIC
c0
: OUT STD_LOGIC
);
END component;
:= '0';
:= '0';
--I2C controller to drive the Wolfson codec
component audioCodecController is
port(
clock50MHz,reset: in std_logic;
I2C_SCLK_Internal: out std_logic;
--must be inout to allow FPGA to read the ack bit
I2C_SDAT_Internal: out std_logic;
SDAT_Control: out std_logic;
--for testing
clock50KHz_Out: out std_logic
);
end component;
--generates digital audio interface clock signals
component adc_dac is
port (
clk, reset: in std_logic; -- reset signal starts '0' then
goes to '1' after 40 ms => active low. Hence we will
complement the delayed reset signal
dac_data_in: in std_logic_vector(31 downto 0);
adc_data_out: out std_logic_vector(31 downto 0);
m_clk, b_clk, dac_lr_clk, adc_lr_clk: out std_logic;
F.7 DE2 Chaotic DDE Specification Top Level
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dacdat: out std_logic;
adcdat: in std_logic;
load_done_tick: out std_logic
);
end component;
component topLevelMux is port (
loopbackN,chaosSystemSelect : in std_logic;
selectLeftChannelBits,selectRightChannelBits : in
std_logic_vector(1 downto 0);
leftChannelLoopBackIn,rightChannelLoopBackIn: in
std_logic_vector(15 downto 0);
chaosX1,chaosY1,chaosZ1,chaosX2,chaosY2,chaosZ2 : in
std_logic_vector(15 downto 0);
leftChannelDACRegister,rightChannelDACRegister : out
std_logic_vector(15 downto 0));
end component;
component pulseFSM is port (
reset,clock,trigger : in std_logic;
pulseOut : out std_logic);
end component;
-- Chaotic system. DSP builder static nonlinearity interface
is inside the module.
-- The ikeda DDE subsystem can also implement synchronization
component ikedaDDESystem is port (
resetn, clockIn : in std_logic;
xFloatOut,xDelayedFloatOut : out std_logic_vector(31
downto 0);
xOut,xDelayedOut : out std_logic_vector(15 downto 0);
syncIn : in std_logic_vector(31 downto 0);
syncClock : out std_logic);
end component;
component sigmoidDDESystem is port (
resetn, clockIn : in std_logic;
xFloatOut,xDelayedFloatOut : out std_logic_vector(31
downto 0);
xOut,xDelayedOut : out std_logic_vector(15 downto 0);
syncIn : in std_logic_vector(31 downto 0);
syncClock : out std_logic);
end component;
component signumDDESystem is port (
resetn, clockIn : in std_logic;
xFloatOut,xDelayedFloatOut : out std_logic_vector(31
downto 0);
xOut,xDelayedOut : out std_logic_vector(15 downto 0);
syncIn : in std_logic_vector(31 downto 0);
syncClock : out std_logic);
end component;
component
synchronizer is port (
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F Chapter 5 VHDL
resetn,clockIn,syncMode,xMinusYIn,syncClock : in
std_logic;
xIn,yIn,yDelayedIn : in std_logic_vector(31 downto 0);
syncOut : out std_logic_vector(31 downto 0));
end component;
-- end dsp builder top level
--clock signal from the PLL clockBuffer
signal clock50MHz : std_logic;
--asynchronous reset for the whole project
signal reset: std_logic;
--I2C data and clock lines
signal i2cData, i2cClock: std_logic;
--tri-state buffer control
signal i2cDataControl: std_logic;
signal i2cDataTriState: std_logic;
--assert signal from delay counter
signal codecReset,codecResetn: std_logic;
--audio codec signals
signal clock18MHz : std_logic;
signal adcDat_sig: std_logic;
signal adcLRCK_sig: std_logic;
signal dacLRCK_sig: std_logic;
signal dacDat_sig: std_logic;
signal bck_sig: std_logic;
signal dac_data_in,adc_data_out : std_logic_vector(31 downto
0);
--nonlinear dynamics model signals
signal leftChannelDataRegister,leftChannelADCRegister,
leftChannelDACRegister : std_logic_vector(15 downto 0);
signal rightChannelDataRegister,rightChannelADCRegister,
rightChannelDACRegister : std_logic_vector(15 downto 0);
signal leftChannelChaos,rightChannelChaos : std_logic_vector
(15 downto 0);
signal chaosXOut,chaosYOut,chaosZOut : std_logic_vector(15
downto 0);
signal chaosX1,chaosY1,chaosZ1 : std_logic_vector(15 downto
0);
signal chaosX2,chaosX2Temp,chaosY2,chaosZ2 : std_logic_vector
(15 downto 0);
-- 32-bit single-precision floating point data for
synchronization
signal chaosXFloatOut,chaosYFloatOut,chaosXDelayedFloatOut,
chaosYDelayedFloatOut,syncSignalXMinusY,syncSignalYMinusX
: std_logic_vector(31 downto 0);
signal syncClock,syncClockTemp : std_logic;
F.7 DE2 Chaotic DDE Specification Top Level
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signal trigger,pulseOut : std_logic;
-- testing
signal clock50KHz : std_logic;
-- select signals
signal selectBitsX,selectBitsY : std_logic_vector(1 downto 0)
;
begin
--keys are active low
reset <= not KEY(0);
--PLL
clockBufferInstance: clockBuffer port map(reset,CLOCK_50,
clock50MHz);
--I2C
I2CControllerInstance: audioCodecController port map(
clock50MHz, reset, i2cClock, i2cData,i2cDataControl,
clock50KHz);
--Codec Controller
dac_data_in <= leftChannelDACRegister&rightChannelDACRegister
;
leftChannelADCRegister <= adc_data_out(31 downto 16);
rightChannelADCRegister <= adc_data_out(15 downto 0);
adcDacInterface : adc_dac port map (
clk => clock50MHz,
reset => reset,
dac_data_in => dac_data_in,
adc_data_out => adc_data_out,
m_clk=>clock18MHz,
b_clk => bck_sig,
dac_lr_clk => dacLRCK_sig,
adc_lr_clk => adcLRCK_sig,
dacdat => dacDat_sig,
adcdat => adcDat_sig,
load_done_tick => open);
mulitplexers : topLevelMux port map (
loopbackN => SW(0),
chaosSystemSelect => SW(1),
selectLeftChannelBits => SW(4 downto 3), -- SW(2) is used to
increment or decrement bifurcation parameter
selectRightChannelBits => SW(6 downto 5),
leftChannelLoopBackIn => leftChannelADCRegister,
rightChannelLoopBackIn => rightChannelADCRegister,
chaosX1 => chaosX1,
chaosY1 => chaosY1,
chaosZ1 => chaosZ1,
chaosX2 => chaosX2,
chaosY2 => chaosY2,
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F Chapter 5 VHDL
chaosZ2 => chaosZ2,
leftChannelDACRegister => leftChannelDACRegister,
rightChannelDACRegister => rightChannelDACRegister);
-----------------------------------------------
------------------------ BEGIN DSP BUILDER BASED CHAOTIC
DYNAMICS
IKEDA DDE SYNCHRONIZATION CURRENTLY DISABLED
ikedaDDESystemInstance_drive : ikedaDDESystem port map (
resetn => KEY(0),
clockIn => clock50MHz,
xFloatOut => chaosXFloatOut,
xDelayedFloatOut => chaosXDelayedFloatOut,
xOut => chaosX1,
xDelayedOut => chaosY1,
syncIn => X"00000000", -- k(t)*(y-x)
syncClock => syncClock);
chaosZ1 <= X"0000";
ikedaDDESystemInstance_Response : ikedaDDESystem port map (
resetn => KEY(0),
clockIn => clock50MHz,
xFloatOut => chaosYFloatOut,
xDelayedFloatOut => chaosYDelayedFloatOut,
xOut => chaosX2,
xDelayedOut => chaosY2,
syncIn => syncSignalXMinusY, -- k(t)*(x-y)
syncClock => syncClockTemp);
--chaosX2 <= chaosX1 - chaosX2Temp; -- synchronization error
chaosZ2 <= X"0000";
syncInstanceSquareXMinusY : synchronizer port map (
resetn => KEY(0),
clockIn => clock50MHz,
syncMode => '0',
xMinusYIn => '1',
syncClock => syncClock,
xIn => chaosXFloatOut,
yIn => chaosYFloatOut,
yDelayedIn => chaosYDelayedFloatOut,
syncOut => syncSignalXMinusY);
syncInstanceSquareYMinusX : synchronizer port map (
resetn => KEY(0),
clockIn => clock50MHz,
syncMode => '0',
xMinusYIn => '0',
syncClock => syncClock,
xIn => chaosXFloatOut,
yIn => chaosYFloatOut,
yDelayedIn => chaosYDelayedFloatOut,
syncOut => syncSignalYMinusX);
F.7 DE2 Chaotic DDE Specification Top Level
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sigmoidalDDE : sigmoidDDESystem port map (
resetn => KEY(0),
clockIn => clock50MHz,
xFloatOut => chaosXFloatOut, -- unused
xDelayedFloatOut => chaosXDelayedFloatOut,
xOut => chaosX1,
xDelayedOut => chaosY1,
syncIn => X"00000000",
syncClock => syncClock);
chaosZ1 <= X"0000";
signumDDE : signumDDESystem port map (
resetn => KEY(0),
clockIn => clock50MHz,
xFloatOut => chaosYFloatOut, -- unused
xDelayedFloatOut => chaosYDelayedFloatOut,
xOut => chaosX2,
xDelayedOut => chaosY2,
syncIn => X"00000000",
syncClock => syncClockTemp);
chaosZ2 <= X"0000";
------------------------ END DSP BUILDER CHAOTIC DYNAMICS
--tri-state data output
i2cDataTriState <= i2cData when i2cDataControl = '1' else 'Z
';
--I2C output ports
I2C_SCLK <= i2cClock;
I2C_SDAT <= i2cDataTriState;
--audio codec input port
adcDat_sig <= AUD_ADCDAT;
--audio codec ouput ports
AUD_ADCLRCK <= adcLRCK_sig;
AUD_DACLRCK <= dacLRCK_sig;
AUD_DACDAT <= dacDat_sig;
AUD_XCK <= clock18MHz;
AUD_BCLK <= bck_sig;
--for testing
GPIO(5) <= adcLRCK_sig;
GPIO(4) <= dacLRCK_sig;
GPIO(3) <= bck_sig;
GPIO(2) <= adcDat_sig;
GPIO(1) <= dacDat_sig;
GPIO(0) <= clock18MHz;
LEDG(0) <= reset;
LEDG(1) <= clock50KHz;
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F Chapter 5 VHDL
HEX1 <= "1111111";
HEX0 <= "1111111";
HEX2 <= "1111111";
HEX3 <= "1111111";
end toplevel;
The synchronizer functionality for the Ikeda DDE is implemented in Lines 222 through 267
in listing F.7. We have commented out the functionality so that the reader can experiment with
synchronization.
1. Lines 222 through 244 define the Ikeda drive and response system.
2. Lines 247 through 267 implement two synchronizer modules : one for square wave coupling
and the other for cosine coupling. Depenging on the syncMode input, either square wave or
cosine coupling is selected (refer to listing F.6).
Within each DDE DSP builder specification, we have included a ”syncIn” input that can be tied
to ground for non-synchronous designs.
Glossary
1. ADC : Hardware component for interfacing external analog signals to digital platforms.
2. DAC : Hardware component for converting digital into analog signals. They are usually at the
output-end of digital systems and can be used, for example, to drive actuators.
3. DDE : Differential equations that incorporate time delays. They usually need a continuum of
initial conditions.
4. DSP : These are digital integrated circuits that are designed for computation-intensive signal
processing applications.
5. FPGA : A massively parallel semiconductor device that can be ”programmed” after manufacturing. The word programmed is in quotes since one should not think of designing for an FPGA
as programming. Rather, one should think about what hardware one wants to specify for time
critical execution on an FPGA. FPGAs are so named because they can be ”programmed” in the
field.
6. FSM : Concept from automata theory that is used to describe sequential logic.
7. HDL : Computer languages for specifying physical hardware. VHDL and Verilog are very popular; there are HDLs such as SystemC that is a set of C++ classes for event-driven simulation.
8. PLL : These are nonlinear control systems that generate an output whose phase is locked with
the input. We primarily use these in this book to buffer clock signals and as clock frequency
multipliers.
9. ROM : The data on these integrated circuits cannot be modified by the user, unlike random
access memories.
10. RTL : A design abstraction that models a synchronous digital circuit in terms of data flow
between hardware registers and logic operations.
11. SDC : A language for specifying timing constraints.
12. VHDL : Hardware description language that can also be used for mixed-signal system specification and a general purpose parallel programming language.
231
Solutions
For step-by-step solutions to all problems, please visit the book’s website:
http://www.harpgroup.org/muthuswamy/ARouteToChaosUsingFPGAs/ARo
uteToChaosUsingFPGAs.html
233
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