CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10

CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10
CFP2 LR4 Optical Transceiver with 100 Gigabit
Ethernet for up to 10 km Reach
JC2 Series
The JDSU 100 G CFP2 LR4 optical transceiver is a full duplex, photonicintegrated optical transceiver that provides a high-speed link at a 103.125
or 111.81 Gbps aggregated data rate over up to 10 km of SMF-28. The
module complies with the CFP MSA CFP2 Hardware Specification Rev. 1.0,
IEEE 802.3-2012 Clause 88, and ITU-T G.959.1-2012-02.
The JDSU 100 G CFP2 LR4 optical transceiver integrates the transmit and receive path onto
one module. On the transmit side, four lanes of serial data streams are recovered, retimed,
and passed on to four laser drivers, which control four electric-absorption modulated
lasers (EMLs) with 1296, 1300, 1305, and 1309 nm center wavelengths. The optical signals
are then multiplexed into a single-mode fiber through an industry-standard LC connector.
On the receive side, four lanes of optical data streams are optically demultiplexed by an
integrated optical demultiplexer. Each data steam is recovered by a PIN photodetector and
transimpedance amplifier, retimed, and passed on to an output driver. This module features a
hot-pluggable electrical interface, low power consumption, and MDIO management interface.
Key Features
• Compliant with 100GBase-LR4 and OTU4
• Supports 103.125 to 111.81 Gbps line rates
• Integrated LAN WDM TOSA/ROSA for up to 10 km
reach over SMF-28
• Duplex LC optical receptacle
• Operating temperature range of up to –5 to 70°C
• Low power dissipation < 9 W (< 8 W typical)
• RoHS 6/6 compliant
• Single 3.3 V power supply
• No external reference clock
• Fast Tx_DIS deassert time (< 5 ms) for service
disruption recovery
• Compliant with CEI-28G-VSR electrical interface
• Real-time digital diagnostic monitoring (DDM)
support
Applications
• Local and wide area networks (LAN and WAN)
• Ethernet switches and router applications
• ITU-T OTU4 OTL4.4 applications
Compliance
• IEEE 802.3-2012 Clause 88 standard
• MDIO IEEE 802.3-2012 Clause 45 standard
• ITU-T G.959.1-2012-02 OTL4.4 standard
• OIF2010.404.08 CEI-28G-VSR standard
• MSA CFP2 Hardware Specification Rev. 1.0
• CFP MSA Management Interface Specification
V2.2 (R06a)
• Class 1 laser safety
• Tested in accordance with Telcordia GR-468
www.jdsu.com
Data Sheet
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
Section 1 Functional Description
Receiver
The JDSU 100 G CFP2 LR4 Optical Transceiver is a full duplex parallel
optical, parallel electric device containing both transmit and receive
functions in a single module. The optical signals are multiplexed to a
single-mode fiber through an industry-standard LC connector.
The receiver takes incoming combined four lanes of DC-balanced
LAN-WDM NRZ optical data from 25.78 to 27.95 Gbps line rates through
an industry-standard LC optical connector. The four incoming wavelengths are separated by an optical demultiplexer into four separated
channels. Each output is coupled to a PIN photodetector. The electrical
currents from each PIN photodetector are converted to a voltage in a
high-gain transimpedance amplifier. The electrical output is recovered
and retimed by the CDR chip. The four lanes of reshaped electrical signals
are output on the RDxp and RDxn pins as a 100 Ω differential CEI signal.
The module provides a high-speed link at an aggregated 103.125 to
111.81 Gbps signaling rate. It complies with IEEE 802.3-2012 Clause
88, 100GBase-LR4, and ITU-T G.959.1-2012-02 OTL4.4 (OTU4 striped
across four physical lanes) 4I1-9D1F for up to 10 km reach over SMF-28
fiber, and OIF2010.404.08 CEI-28G-VSR electrical specifications. The
MDIO management interface complies with IEEE 802.3-2012 Clause
45 standard. The transceiver complies with CFP MSA CFP2 Hardware
Specification Rev. 1.0, CFP MSA Management Interface Specification
Rev. 2.2, and OIF CEI-28G-VSR standards. Figure 1 shows block diagram.
Optical
Demulti plexer
CDR /
Limiting
Amplifier
TIA
TIA
LDD
CDR /
Equalizer
TOSA
Optical
Multiplexer
104-pin Connect or
TIA
LC Connector
ROSA
TIA
LDD
LDD
LDD
Low-Speed Signaling
Low-speed signaling is based on low-voltage CMOS (LVCMOS)
operating at a nominal voltage of 3.3 V for the control and alarm signals,
and at a nominal voltage of 1.2 V for MDIO address, clock, and data
signals. All low-speed inputs and outputs are based on CFP MSA CFP2
Hardware Specification Rev. 1.0 and CFP MSA Management Interface
Specification Rev. 2.2 R06a requirements.
Low-Speed Interface
Connections
Definition
MDC/MDIO
Management interface clock and data lines.
PRTADR0, 1, 2
Input pins. MDIO physical port addresses.
GLB_ALRMn
Output pin. When asserted low, indicates that the
module has detected an alarm condition in any
MDIO alarm register.
PRG_CNTL1, 2, 3
Input pins. Programmable control lines defined in
the CFP MSA Management Interface Specification.
Pulled up with 4.7 to 10 kΩ resistors to 3.3 V inside
the CFP2 module.
TX_Disable
Input pin. When asserted high or left open, the
transmitter output is turned off. When Tx_Dsiable
is asserted low or grounded, the module
transmitter is operating normally. Pulled up with
4.7 to 10 kΩ resistors to 3.3 V inside the CFP2
module.
MOD_LOPWR
Input pin. When asserted high or left open, the
CFP2 module is in low-power mode. When
asserted low or grounded, the module is operating
normally. Pulled up with 4.7 to 10 kΩ resistors to
3.3 V inside the CFP2 module.
MOD_RSTn
Input pin. When asserted low or grounded, the
module is in reset mode. When asserted high or
left open, the CFP2 module is operating normally
after an initialization process. Pulled down with
4.7 to 10 kΩ resistors to ground inside the CFP2
module.
PRG_ALRM1, 2, 3
Output pins. Programmable alarm lines defined in
the CFP MSA Management Interface Specification.
MOD_ABS
Output pin. Asserted high when the CFP2 module
is absent and is pulled low when the CFP2 module
is inserted.
RX_LOS
Output pin. Asserted high when receiving
insufficient optical power for reliable signal
reception.
MDIO, MDC, PRTADR0,1,2
PRG_CNTL1,2,3, TX_DIS, MOD_LOPWR, MOD_RSTn
PRG_ALRM1,2,3, RX_LOS, MOD_ABS, GLB_ALRM
Control &
Monitoring
REFCLK +
REFCLK –
Figure 1. JDSU CFP2 LR4 Optical Transceiver functional block diagram
Transmitter
The transmitter path converts four lanes of serial NRZ electrical data
from 25.78 to 27.95 Gbps line rates to a standard compliant optical
signal. Each signal path, or CEI lane, accepts a 100 Ω differential 100 mV
peak-to-peak to 900 mV peak-to-peak 25 Gbps CEI electrical signal on
TDxn and TDxp pins.
Inside the module, each differential pair of electric signals is input to a
CDR (clock-data recovery) chip. The recovered and retimed signals are
then passed to a laser driver which transforms the small swing voltage
to an output modulation that drives a cooled EML laser. The laser
drivers control four EMLs with 1296, 1300, 1305, and 1309 nm center
wavelengths, respectively. Closed-loop control of the transmitted laser
power and modulation swing over temperature and voltage variations
is provided on each laser. The optical signals from the four lasers are
multiplexed together optically. The combined optical signals are
coupled to single-mode optical fiber through an industry-standard LC
optical connector. The optical signals are engineered to meet the
100 Gigabit Ethernet or OTU4 specifications.
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2
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
Section 2 Application Schematics
Section 3 Technical Specifications
Figure 2 shows an example of an application schematic showing
connections from a host IC and host power supply to the JDSU 100G
CFP2 LR4 Optical Transceiver.
Section 3.1 Pin Function Definitions
Section 3.2 CFP2 Lane Assignment
Section 3.3 Absolute Maximum Ratings
CFP2 modules are hot-pluggable and active connections are powered
by individual power connection at 3.3 V nominal voltage. Multiple
modules can share a single 3.3 V power supply with individual filtering.
A possible example of a power-supply filtering circuit that might be
used on the host system is a proportional integral (PI) C-L-C filter. To
limit wideband noise power, the host system and module shall each
meet a maximum of 2% peak-to-peak noise when measured with a
1 MHz low-pass filter. In addition, the host system and the module shall
each meet a maximum of 3% peak-to-peak noise when measured with
a filter from 1 to 10 MHz.
Section 3.4 Low-Speed Electrical Characteristics
Section 3.5 High-Speed Electrical Characteristics
Section 3.6 Timing Requirement of Control and Status I/O
Section 3.7 MDIO Management Interface
Section 3.8 Optical Transmitter Characteristics
Section 3.9 Optical Receiver Characteristics
Section 3.10 Module Startup Setup for Program Control
(PRG_CNTLx) Pins
Section 3.11 Regulatory Compliance
Section 3.12 Module Outline
Section 3.13 Connectors
A module will meet all electrical requirements and remain fully
operational in the presence of noise on the 3.3 V power supply. Power
supply filtering components should be placed as close to the VCC pins of
the host connector as possible for optimal performance.
1.2V
3.1 Preliminary Datasheet
Pin Function Definitions
3.3V
CFP2 Module
MDIO
MDC
MOD_ABS
GLB_ALRMn
PRTADR0,1,2
PRG_ALRM1,2,3
RX_LOS
PRG_CNTL1,2,3
TX_DIS
MOD_LOWPR
MOD_RSTn
Communication,
Control and
Monitor IC
RX Data Bus
RX CDR
TX Data Bus
TX CDR
Host Vcc_3.3V
GND
3.3V_GND
Figure 2. Application schematics for the JDSU CFP2 optical transceiver
Figure 3. CFP2 optical transceiver pin assignments
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3
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
Table 1. Pin descriptions
Pin No. Type
1
Name
Description
GND
Module ground
Pin No. Type
Name
Description
34
1.2V CMOS
PRTADR1
MDIO physical port address bit 1
1.2V CMOS
PRTADR2
MDIO physical port address bit 2
2
CML
(TX_MCLKn) No connect
35
3
CML
(TX_MCLKp) No connect
36
VND_IO_C
Module vendor IO C; do not connect
GND
37
VND_IO_D
Module vendor IO D; do not connect
4
Module ground
5
N.C.
No connect
38
VND_IO_E
Module vendor IO E; do not connect
6
N.C.
No connect
39
3.3V_GND
3.3 V ground; tied with module ground
7
3.3V_GND
3.3 V ground; tied with module ground
40
3.3V_GND
3.3 V ground; tied with module ground
8
3.3V_GND
3.3 V ground; tied with module ground
41
3.3V
3.3 V module supply voltage
9
3.3V
3.3 V module supply voltage
42
3.3V
3.3 V module supply voltage
3.3 V module supply voltage
10
3.3V
3.3 V module supply voltage
43
3.3V
11
3.3V
3.3 V module supply voltage
44
3.3V
3.3 V module supply voltage
12
3.3V
3.3 V module supply voltage
45
3.3V_GND
3.3 V ground; tied with module ground
13
3.3V_GND
3.3 V ground; tied with module ground
46
3.3V_GND
3.3 V ground; tied with module ground
14
3.3V_GND
3.3 V ground; tied with module ground
47
N.C.
No connect
15
VND_IO_A
Module vendor IO A; do not connect
48
N.C.
No connect
16
VND_IO_B
Module vendor IO B; do not connect
49
GND
Module ground
17
LVCMOS1
18
LVCMOS1
19
LVCMOS
20
21
22
1
LVCMOS
LVCMOS
LVCMOS
23
24
LVCMOS1
PRG_CNTL1 Programmable control 1; MSA default:
TRXIC_RSTn; “0”: reset; “1”: enable
PRG_CNTL2 Programmable control 2; MSA default:
Hardware interlock LSB; Default “0”:
≤9W
PRG_CNTL3 Programmable control 3: MSA default:
Hardware interlock MSB; Default “1”:
≤9W
PRG_ALRM1 Programmable alarm 1; MSA default:
HIPWR_ON; “1”: module power up
completed, “0”: module not high
powered up
PRG_ALRM2 Programmable alarm 2; MSA default:
MOD_READY, “1”: Ready, “0”: not Ready
52
GND
Module ground
53
GND
Module ground
54
N.C.
No connect
55
N.C.
No connect
56
GND
Module ground
57
RX0P
25 Gbps receiver data; Lane 0
58
RX0n
25 Gbps receiver data bar; Lane 0
59
GND
Module ground
60
RX1p
25 Gbps receiver data; Lane 1
61
RX1n
25 Gbps receiver data bar; Lane 1
GND
Module ground
63
N.C.
No connect
GND
Module ground
64
N.C.
No connect
TX_DIS
Transmitter disable for all lanes;
“1” or NC: transmitter disabled; “0”:
transmitter enabled
65
GND
Module ground
66
N.C.
No connect
67
N.C.
No connect
RX_LOS
26
LVCMOS1
MOD_LOPWR Module low power mode; “1” or NC:
module in low power mode, “0”: power
on enabled
MOD_ABS
Receiver loss of optical signal; “1”: low
optical signal, “0”: normal condition
27
GND
28
LVCMOS
MOD_RSTn
29
LVCMOS
GLB_ALRMn Global alarm; “0”: alarm in any MDIO
alarm register; “1”: no alarm condition.
Pull up resistor on host.
68
GND
Module ground
69
RX2p
25 Gbps receiver data; Lane 2
70
RX2n
25 Gbps receiver data bar; Lane 2
71
GND
Module ground
25 Gbps receiver data; Lane 3
Module absent; “1” or NC: module
absent; “0”: module present. Pull up
resistor on host.
72
RX3p
73
RX3n
25 Gbps receiver data bar; Lane 3
Module reset; “0”: reset the module;
“1” or NC: module enabled
74
GND
Module ground
75
N.C.
No connect
76
N.C.
No connect
77
GND
Module ground
GND
Module ground
31
1.2V CMOS
MDC
Management interface clock input
32
1.2V CMOS
MDIO
Management interface bidirectional
data
33
1.2V CMOS
PRTADR0
MDIO physical port address bit 0
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(RX_MCLKn) No connect
(RX_MCLKp) No connect
62
LVCMOS
30
CML
CML
PRG_ALRM3 Programmable alarm 3; MSA default:
MOD_FAULT, “1”: Fault, “0”: no Fault
25
2
50
51
78
CML
(REFCLKp)
Module reference clock. No connect.
79
CML
(REFCLKn)
Module reference clock. No connect.
80
GND
Module ground
81
N.C.
No connect
82
N.C.
No connect
4
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
3.2 Table 1. Pin descriptions (Cont'd.)
Pin No. Type
Name
Description
83
GND
Module ground
84
TX0p
25 Gbps transmitter data; Lane 0
85
TX0n
25 Gbps transmitter data bar; Lane 0
86
GND
Module ground
87
TX1p
25 Gbps transmitter data; Lane 1
88
TX1n
25 Gbps transmitter data bar; Lane 1
Lane
CFP2 Lane Assignment
Center Frequency Center Wavelength Wavelength Range
L0
231.4 THz
1295.56 nm
1294.53 to 1296.59 nm
L1
230.6 THz
1300.05 nm
1299.02 to 1301.09 nm
L2
229.8 THz
1304.58 nm
1303.54 to 1305.63 nm
L3
229.0 THz
1309.14 nm
1308.09 to 1310.19 nm
89
GND
Module ground
3.3 90
N.C.
No connect
91
N.C.
No connect
Absolute maximum ratings represent the device’s damage threshold.
Damage may occur if the device is operated outside the limits stated
here. Performance is not guaranteed and reliability is not implied for
operation at any condition outside the recommended operating limits.
92
GND
Module ground
93
N.C.
No connect
94
N.C.
No connect
95
GND
Module ground
96
TX2p
25 Gbps transmitter data; Lane 2
97
TX2n
25 Gbps transmitter data bar; Lane 2
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Storage temperature
TST
−40 to +85
ºC
Operating case
temperature
TOP
−5 to +70
ºC
Relative humidity
RH
5 to 85 (noncondensing)
%
ESD
500
V
98
GND
Module ground
99
TX3p
25 Gbps transmitter data; Lane 3
100
TX3n
25 Gbps transmitter data bar; Lane 3
Static electrical discharge
(human body model)
101
GND
Module ground
Power supply voltages
N.C.
No connect
VCC, max
−0.3 to 3.6
102
N.C.
No connect
Pdmg
+ 5.5
103
Receive input optical
power (damage threshold)
104
GND
Module ground
Unit
V
dBm
1. Pulled up with 4.7 to 10 kΩ to 3.3 V inside the module.
2. Pulled down with 4.7 to 10 kΩ to GND inside the module.
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5
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
3.4 Low-Speed Electrical Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Voltage
VCC
3.135
3.3
3.465
V
With respect to GND
Supply current
ICC
3.75
A
Power dissipation
Pwr
9.0
W
Per MSA MSA CFP2 Hardware Specification
Rev. 1.0 Table 4-1 Class 3
Supply Currents and Voltages
Power dissipation (low power mode)
Plp
2.0
W
Inrush current
I_inrush
100
mA/µs
Turn-off current
I_turnoff
–100
mA/µs
Low-Speed Control and Sense Signals, 3.3 V LVCMOS
Outputs low voltage
VOL
Output high voltage
VOH
VCC –0.2
Input low voltage
VIL
–0.3
0.8
Input high voltage
VIH
2
VCC+ 0.3
V
Input leakage current
IIN
–10
10
µA
V
0.2
V
IOH = 100 µA
V
IOH = –100 µA
V
Low-Speed Control and Sense Signals, 3.3 V LVCMOS
Outputs low voltage
VOL
–0.3
0.2
Output high voltage
VOH
1.0
1.5
Output low current
IOL
4
V
mA
Output high current
IOH
Input low voltage
VIL
Input high voltage
VIH
0.84
1.5
V
Input leakage current
IIN
–100
100
µA
Input capacitance
C
MDC clock rate
3.5 –0.3
0.1
–4
mA
0.36
V
10
pF
4
MHz
High-Speed Electrical Specifications
Parameter
Symbol
Min.
Max.
Unit
Notes
Transmitter Electrical Input from Host at TP1a (detailed specification in CEI-28G-VSR)
Differential voltage pk-pk
900
mV
Common mode noise (rms)
17.5
mV
10
%
Differential termination mismatch
Transition time
10
Common mode voltage
–0.3
ps
2.8
20/80%
V
Eye width
EW15
0.46
UI
At 10−15 probability
Eye height
EH15
100
mV
At 10−15 probability
Receiver Electrical Output to Host at TP4 (detailed specification in CEI-28G-VSR)
Differential voltage pk-pk
900
mV
Common mode noise (rms)
17.5
mV
Differential termination mismatch
10
Transition time
Vertical eye closure
9.5
VEC
%
ps
5.5
20/80%
dB
Eye width
EW15
0.57
UI
At 10−15 probability
Eye height
EH15
228
mV
At 10−15 probability
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CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
3.6 Timing Requirement of Control and Status I/O
Parameter
Symbol
Min.
Minimum pulse width of control pin signal
t_CNTL
100
Max.
Unit
Notes
Hardware MOD_LOPWR assert
t_MOD_LOPWR_assert
1
Hardware MOD_LOPWR deassert
t_MOD_LOPWR_deassert
60
s
Stored in NVR register 8072h
RX_LOS assert time
t_loss_assert
100
µs
From occurrence of loss of signal to assertion
of RX_LOS
RX_LOS deassert time
t_loss_deassert
100
µs
From occurrence of return of signal to deassert
of RX_LOS
GLB_ALRM assert time
GLB_ALRMn_assert
150
ms
A logic “OR” of associated MDIO alarm and
status registers
GLB_ALRM deassert time
GLB_ALRMn_deassert
150
ms
A logic “OR” of associated MDIO alarm and
status registers
MDC is 4 MHz rate or less
µs
ms
Management interface clock period
t_prd
250
ns
Host MDIO setup time
t_setup
10
ns
Host MDIO hold time
t_hold
10
CFP2 MDIO delay time
t_delay
0
ns
175
ns
Initialization time from reset
t_initialize
2.5
s
TX_Disable assert time
t_deassert
100
µs
Transmitter disable, application specific
TX_Disable deassert time1
t_assert
5
ms
Time from Tx Disable pin deasserted until CFP2
module enters the Tx-turn-on state
Stored in NVR register 8073h
1. The transceiver is stabilized prior to TX_Disable deassert event.
3.7 MDIO Management Interface
The JDSU 100G CFP2 optical transceiver incorporates an MDIO management interface which is used for serial ID, digital diagnostics, and certain
control and status report functions. The CFP2 transceiver supports MDIO pages 8000h NVR 1 Based ID registers, NVR 2 Alarm/Warning threshold
registers, and NVR 4 tables, and pages A000h VR 1, and VR 3 tables .
Details of the protocol and interface are explicitly described in IEEE 802.3-2012 Clause 45 and CFP MSA Management Interface Specification V2p2_r01b.
Please refer to the specifications for design reference.
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7
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
3.8 Optical Transmitter Characteristics
Parameter
Symbol
Min.
Signaling rate, each lane
Typ.
Max.
25.78125 ±100 ppm
Unit
GBd
27.9525 ±20 ppm
Notes
100GBase-LR4
OTU4
The following specifications are applicable within the operating case temperature range
Side-mode suppression ratio
SMSR
30
dB
Total launch power
10.5
10.0
Average launch power, each lane
1
Extinction ratio
Pavg
ER
Optical modulation amplitude, each lane (OMA)2
OMA
–4.3
4.5
–0.6
4.0
4
TDP
OMA minus TDP, each lane
OMA-TDP
dBm
dB
100GBase-LR4
OTU4
100GBase-LR4
OTU4
100GBase-LR4
4
6.5
–1.3
4.5
dBm
5
dB
100GBase-LR4, OTU4
2.2
dB
100GBase-LR4
Difference in launch power between any two lanes (OMA)
Transmitter and dispersion penalty, each lane
dBm
100GBase-LR4
dBm
100GBase-LR4
Average launch power of OFF transmitter, each lane
–30
dBm
100GBase-LR4
Optical return loss tolerance
20
dB
–130
dB/Hz
–12
dB
Relative intensity noise
–2.3
OTU4
RIN20OMA
Transmitter reflectance3
Transmitter eye mask {X1, X2, X3, Y1, Y2, Y3}
3.9 {0.25, 0.4, 0.45, 0.25, 0.28, 0.4}
100GBase-LR4
100GBase-LR4
Optical Receiver Characteristics
Parameter
Symbol
Min.
Signaling rate, each lane
Typ.
Max.
25.78125 ±100 ppm
Unit
GBd
27.9525 ±20 ppm
Notes
100GBase-LR4
OTU4
The following specifications are applicable within the operating case temperature range
Average receive power, each lane4
Pavg
–10.6
4.5
Average receive power, each lane5
Pavg
–6.9
4
–8.8
2.9
dBm
dBm
Receive power, each lane (OMA)
4.5
dBm
Difference in launch power between any two lanes (OMA)
5.5
dB
–8.6
dBm
Receiver Sensitivity (OMA), each lane4 at BER= 1x10–12
Rsen
Equivalent receiver sensitivity5 at BER=1.8x10–4
–8.4
–10.3
Optical path penalty
Stressed receiver sensitivity (OMA), each lane
SRS
dBm
1.5
dB
–6.8
dBm
100GBase-LR4
OTU4 with Tx ER of 4 to 6.5 dB
OTU4 with Tx ER > 7 dB
100GBase-LR4
100GBase-LR4, OTU4
100GBase-LR4
OTU4 with Tx ER of 4 to 6.5 dB
OTU4 with Tx ER > 7 dB
OTU4
100GBase-LR4, at TP3 for BER= 1x10–12
Stressed receiver sensitivity test conditions
Vertical eye closure penalty, each lane6
VECP
6
Stressed sys J2 jitter, each lane
Stressed sys J9 jitter, each lane6
1.8
dB
100GBase-LR4
J2
0.3
UI
100GBase-LR4
J9
0.47
UI
100GBase-LR4
–26
dB
100GBase-LR4, OTU4
–15
dBm
4
dB
Receiver reflectance
LOS assert7
LOS hysteresis7
Plos_on
0.5
1. Average launch power, each lane (min) is informative for 100GBase-LR4, not the principal indicator of signal strength.
2. Even if the TDP < 1 dB, the OMA (min) must exceed this value.
3. Transmitter reflectance is defined looking into the transmitter.
4. Minimum average receive power and maximum receiver sensitivity (OMA), each lane, is informative for 100GBase-LR4,
5. For OTU4, 4I1-9D1F defines two sets of specification based on two options of transmitter ER. The minimum average receive power represents an Rx_sensitivity (OMA) of –7.5 dBm at worst case ER over all condition with
10 km fiber link at post GFEC of BER 1x10−12. The maximum receiver sensitivity is informative and representing Rx_sensitivity (OMA) of –9.05 dBm at worst case ER over all condition at pre-GFEC of BER 1.8 x 10−4.
6. Vertical eye closure penalty, stressed eye J2 jitter, and stressed eye J9 jitter are test conditions for measuring stressed receiver sensitivity. They are not characteristics of the receiver.
7. LOS function is implemented per modulated input signal.
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8
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
3.10 Module Startup Setup for Program Control (PRG_CNTLx) Pins
MSA default setting of PRG_CNTL1 is TRxIC_RSTn to reset Tx and Rx ICs.
CFP2 operation and PRG_CNTL1 Pin State dependencies on hardware
pin settings and Soft PRG_CNTL1 shall be as follows.
PRG_CNTL1
Pin State
PRG_CNTL1
(Register
(Hardware pin) A010h.1)
HW_Interlock = 0 if HW_IL_MSB and HW_IL_LSB = 11b, or
HW_Interlock = 0 if module power ≤ Host cooling capacity, or else
HW_Interlock = 1 if module power > Host cooling capacity.
SoftPRG_CNTL1
(Register
CFP2
A010h.10)
Operation
A
1=high
(Normal)
1
0 (Normal)
Normal
B
1=high
(Normal)
1
1 (Reset)
Reset
C
0=low (Reset)
0
0 (Normal)
Reset
D
0=low (Reset)
0
1 (Reset)
Reset
In operation, the module samples the status of the HW_IL_MSB and
HW_IL_LSB input pins once during the initialize state. To ensure a
reliable sampling, the host shall hold HW_IL_MSB and HW_IL_LSB
signal valid until the module exits initialize state. The module stores
these values in a variable HW_IL_inputs.
Hardware pins PRG_CTRL2 and PRG_CTRL3 are used for the hardware
interlock function during Initialization State. It is a logic signal CFP
module generates internally based upon the comparisons between the
module’s power class and the host cooling capacity.
Pin No. Symbol
17
PRG_CNTL1
Description
Programmable Control 1
MSA Default :TRXIC_RSTn,
Tx and Rx ICs reset
"0": reset, "1" :enabled
18
PRG_CNTL2
Programmable Control 2
MSA default : Hardware
interlock LSB
0
1
0
1
19
PRG_CNTL3
Programmable Control 3
MSA default : Hardware
interlock MSB
0
0
1
1
Power class
Module power
dissipation (W)
Its purpose is to prevent an otherwise-dangerous high-power
condition that may harm either the host or the module itself, due to
potential power requirements which the host cannot support. The
status of HW_Interlock (CFP2 Module VR1, Address A01D, bit13) is defined
as follows:
1
2
3*
4
≤3
≤6
≤ 9*
≥9
When both the MOD_LOPWR input pin and the soft module low power
register bit are deasserted, the module then compares the variable
HW_IL_inputs to the power class for which it is designed (defined in
the Power Class field of register 8001h). The result of this comparison
updates the HW_Interlock status. The module remains in the low-power
state if HW_Interlock evaluates to '1' (this does not result in a transition
to the fault state). Conversely, if HW_Interlock evaluates to '0', the
module may transition to the high-power-up state.
Host capable to manage CFP2 module with power class > 3 are
recommended upon MOD_ABS pin deassertion to keep MOD_LOPWR
input pin asserted. When MOD_LOPWR state is reached, the host shall
interrogate the module via MDIO bus and check whether CFP2 exact
power class derived from 807Eh register is matching the host cooling
capacity. Only after a positive response from previous check the MOD_
LOPWR input pin can be deasserted from the host.
After initialization, the Host is free to reprogram the usage of the
PRG_CNTLn input pins and change their values at any time. The pin
functions follow PRG_CNTL1, 2, and 3 Function Select settings (A005h,
A006h, and A007h).
*JDSU CFP2 module power class/dissipation level
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9
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
3.11 Regulatory Compliance
3.12 Module Outline
The JDSU 100G CFP2 optical transceiver is lead-free and RoHS 6/6
compliant.
The JDSU 100G CFP2 optical transceiver complies with international
electromagnetic compatibility (EMC) and international safety
requirements and standards. EMC performance is dependent on the
overall system design.
Table 2. Regulatory Compliance
Feature
Test Method
Performance
UL 60950-1
CSA C22.2 No. 60950-1
UL recognized component for US
and CAN
EN 60950-1
TUV certificate
IEC 60950-1
CB certificate
Flame Class V-0
Passes Needle Flame Test for
component flammability verification
Low Voltage Directive
2006/95/EC
Certified to harmonized standards
listed; Declaration of Conformity issued
EN 60825-1, EN 60825-2
TUV certificate
IEC 60825-1
CB certificate
U.S. 21 CFR 1040.10
FDA/CDRH certified with accession
number
Safety
Product
Laser
Electromagnetic Compatibility
Radiated
emissions
EMC Directive 2004/108/EC Class B digital device with a
minimum –6 dB margin to the limit.
FCC rules 47 CFR Part 15
Final margin may vary depending
CISPR 22
on system implementation.
AS/NZS CISPR22
Tested frequency range: 30 MHz to
EN 55022
40 GHz or 5th harmonic (5 times the
highest frequency), whichever is less.
ICES-003, Issue 5
VCCI regulations
Immunity
ESD
Radiated
immunity
Requires good system EMI design
practice to achieve Class B margins
at the system level.
EMC Directive 2004/108/EC Certified to harmonized standards
listed; Declaration of Conformity
CISPR 24
issued
EN 55024
IEC/EN 61000-4-2
IEC/EN 61000-4-3
Exceeds requirements. Withstands
discharges of ± 8 k V contact,
±15 k V air.
Exceeds requirements. Field
strength of 10 V/m from 80 MHz
to 6 GHz. No effect on transmitter/
receiver performance is detectable
between these limits.
3.13 Connectors
Fiber
The CFP2 module has a duplex LC receptacle connector.
Electrical
The electrical connector is the 104-way, two-row PCB edge connector.
Customer connector is Yamaichi CN121P-104-0001 connector or
equivalent.
Restriction of Hazardous Substances (RoHS)
RoHS
EU Directive 2011/65/EU
Compliant per the Directive 2011/65/EU
of the European Parliament and
of the 8 June 2011 Council on the
restriction of the use of certain
hazardous substances in electrical
and electronic equipment (recast).
A RoHS Certificate of Compliance
(C of C) is available upon request.
The product may use certain RoHS
exemptions.
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10
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
Section 4
Other Related Information
4.3 Section 4.1 Packing and Handling Instructions
Section 4.2 Electrostatic Discharge
Section 4.3 Laser Safety
The transceiver is certified as a Class 1 laser product per international
standard IEC 60825-1:2007 2nd edition and is considered nonhazardous when operated within the limits of this specification.
Section 4.4 Electromagnetic Compliance (EMC)
4.1 Laser Safety
The transceiver complies with 21 CFR 1040.10 except for deviations
pursuant to Laser Notice No. 50 dated June 24, 2007.
Package and Handling Instructions
Connector Covers
The JDSU 100G CFP2 optical transceiver is supplied with an LC duplex
receptacle. The connector plug supplied protects the connector
during standard manufacturing processes and handling by preventing
contamination from dust, aqueous solutions, body oils, or airborne
particles.
Note: It is recommended that the connector plug remain on whenever
the transceiver optical fiber connector is not inserted.the transceiver
optical fiber connector is not inserted.
Recommended Cleaning and Degreasing Chemicals
Caution
Operating this product in a manner inconsistent with intended usage
and specifications may result in hazardous radiation exposure.
Use of controls or adjustments or performance of procedures other
than these specified in this product data sheet may result in hazardous
radiation exposure.
JDSU recommends the use of methyl, isopropyl, and isobutyl alcohols
for cleaning.
Tampering with this laser product or operating this product outside the
limits of this specification may be considered an ‘act of manufacturing’
and may require recertification of the modified product.
Do not use halogenated hydrocarbons, such as trichloroethane,
ketones such as acetone, chloroform, ethyl acetate, MEK, methylene
chloride, methylene dichloride, phenol, N-methylpyrolldone).
Viewing the laser output with certain optical instruments, such as eye
loupes, magnifiers, microscopes, within a distance of 100 mm may pose
an eye hazard.
This product is not designed for aqueous wash.
Housing
4.4 The JDSU CFP2 optical transceiver housing is made from zinc.
The transceiver has been tested and found compliant with
international electromagnetic compatibility (EMC) standards and
regulations and is declared EMC compliant as stated below.
4.2 Electrostatic Discharge
Handling
Normal electrostatic discharge (ESD) precautions are required
during the handling of this module. This transceiver is shipped in ESD
protective packaging. It should be removed from the packaging and
otherwise handled in an ESD protected environment utilizing standard
grounded benches, floor mats, and wrist straps.
Test and Operation
In most applications, the optical connector will protrude through the
system chassis and be subjected to the same ESD environment as the
system. Once properly installed in the system, this transceiver should
meet and exceed common ESD testing practices and fulfill system ESD
requirements.
EMC (Electromagnetic) Compliance
Note: EMC performance depends on the overall system design.
US
CAN
EU
AU/NZ
Japan
CAN
ICES-3 (B)
NMB-3 (B)
United States
This device complies with Part 15 of the FCC Rules. Operation is subject
to the following two conditions:
1. This device may not cause harmful interference
2. This device must accept any interference received, including
interference that may cause undesired operation.
Typical of optical transceivers, this module’s receiver contains a highly
sensitive optical detector and amplifier which may become temporarily
saturated during an ESD strike, resulting in a short burst of bit errors. Such
an event might require that the application reacquire synchronization
at the higher layers (for example, serializer/deserializer chip).
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11
CFP2 LR4 Optical Transceiver with 100 Gigabit Ethernet for up to 10 km Reach—JC2 Series
This equipment has been tested and found to comply with the limits
for a Class B digital device, pursuant to Part 15 of the FCC Rules. These
limits are designed to provide reasonable protection against harmful
interference in a residential installation. This equipment generates, uses,
and can radiate radio frequency energy and, if not installed and used
in accordance with the instructions, may cause harmful interference to
radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment causes harmful
interference to radio or television reception, which can be determined
by turning the equipment off and on, the user is encouraged to try to
correct the interference by one or more of the following measures:
European Union
This product complies with the European Union’s Low Voltage Directive
2006/95/EC and EMC Directive 2004/108/EC and is properly CE
marked. This declaration is made by JDS Uniphase Corp. who is solely
responsible for the declared compliance.
Japan
• Reorient or relocate the receiving antenna
• Increase the separation between the equipment and receiver
• Connect the equipment into an outlet on a circuit different from
that to which the receiver is connected
• Consult the dealer or an experienced radio/TV technician for help
Caution: Any changes or modifications to the product not expressly
approved by JDS Uniphase Corp. could void the user's authority to
operate this equipment.
Canada
ICES-3 (B) / NMB-3 (B)
This Class B digital apparatus complies with Canadian ICES-003.
Cet appareil numérique de la classe B est conforme à la norme
NMB-003 du Canada.
North America Worldwide
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Translation: This is a Class B product based on the standard of
the Voluntary Control Council for Interference from Information
Technology Equipment (VCCI). If this is used near a radio or television
receiver in a domestic environment, it may cause radio interference.
Install and use the equipment according to the instruction manual.
Ordering Information
For more information on this or other products and their availability,
please contact your local JDSU account manager or JDSU directly
at 1-800-498-JDSU (5378) in North America and +800-5378-JDSU
worldwide or via e-mail at [email protected]
Description
Product Code
100 GE, 10 km reach, LR4, commercial temperature
range, CFP2 optical transceiver
JC2-10LR4AA1
100 GE and OTU4, 10 km reach, LR4, commercial
temperature range, CFP2 optical transceiver
JC2-10LM4AA1
Toll Free: 800 498-JDSU (5378)
Tel: +800 5378-JDSU
© 2014 JDS Uniphase Corporation Product specifications and descriptions in this document are subject to change without notice.
30175969 000 0814 JC2-10LX4AA1.DS.OC.AE August 2014
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