CENTIPEDE-PCI Manual, Mach3 Firmware

CENTIPEDE-PCI Manual, Mach3 Firmware
CENTIPEDE-PCI CNC Interface Board
Mach3 Version
Firmware V3.0.1
KSI Labs, LLC
2013
COPYRIGHT
© 2013 KSI Labs, LLC. All rights reserved.
The trademarks mentioned in this manual are legally registered to
their respective owners.
Disclaimer
Information in this manual is protected by copyright laws and is the property of
KSI Labs, LLC. Changes to specication and features in this manual may be
made by KSI Labs, LLC at any time without prior notice. All information in
this manual including schematics is for sole use by KSI Labs, LLC end users
ONLY. Any commercial use of information contained in this document requires
a written permission from
KSI Labs, LLC. All violators will be prosecuted to
the fullest extent of the law. For product-related information and latest versions
check our web site:
http://www.ksilabs.com
1
Contents
1 HARDWARE
1.1 Connectors . . . . . . . . . .
1.1.1 JTAG . . . . . . . . .
1.1.2 External Connector .
1.1.3 Extension Connector
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2 FIRMWARE
2.1 PCI Device Registers . . . . . . . . . . . . . . . .
2.2 Registers Description . . . . . . . . . . . . . . . .
2.2.1 DATA_OUT, Oset 0x00 . . . . . . . . .
2.2.2 DATA_IN, Oset 0x04 . . . . . . . . . .
2.2.3 DAC, Oset 0x08 . . . . . . . . . . . . . .
2.2.4 ADC, Oset 0x0c . . . . . . . . . . . . . .
2.2.5 IRQ_RAW, Oset 0x10 . . . . . . . . . .
2.2.6 IRQ_MASK, Oset 0x14 . . . . . . . . .
2.2.7 IRQ_STAT, Oset 0x18 . . . . . . . . . .
2.2.8 MACH_IDX_[XYZABC], Osets 0x1c,
0x24, 0x28, 0x2c, 0x30 . . . . . . . . . . .
2.2.9 MACH_CONFIG, Oset 0x34 . . . . . .
2.2.10 MACH_CONFIG2, Oset 0x38 . . . . .
2.2.11 MACH_CTL, Oset 0x3c . . . . . . . . .
2.2.12 MACH_STAT, Oset 0x40 . . . . . . . .
2.2.13 MACH_FIFO, Oset 0x44 . . . . . . . .
2.2.14 MACH_ENC, Oset 0x48 . . . . . . . .
2.2.15 MACH_SPCNT, Oset 0x4c . . . . . . .
2.2.16 MACH_SPCTL, Oset 0x50 . . . . . . .
2.2.17 MACH_CONFIG3, Oset 0x54 . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
....
....
....
....
....
....
....
....
....
0x20,
....
....
....
....
....
....
....
....
....
....
3
4
4
4
6
8
9
11
11
12
14
15
15
17
17
18
18
20
21
22
24
24
25
25
26
3 Appendix A - Hardware dierences between rev.1.0 and rev.1.1 28
4 Appendix B - CENTIPEDE-PCI rev.1.0 Schematics
30
5 Appendix C - CENTIPEDE-PCI rev.1.1 Schematics
33
2
Chapter 1
HARDWARE
CENTIPEDE-PCI is a PCI-2.2 compatible interface card for CNC control applications. It may be used for other purposes as well but it was designed to control
a CNC machine when used with optional breakout board, CENTIPEDE-BRK.
It is universal PCI Add-In card i.e. it will work in both 3.3V and 5V PCI/PCI-X
slot.
CENTIPEDE-PCI (simply PCI from now on) board is designed in the way
that allows for maximum exibility and extensibility.
Entire functionality is
implemented in innitely reprogrammable Altera MaxII
© CPLD so all board's
hardware is actually an HDL code. That code can be changed and programmed
into the CPLD thus allowing for easy bug xes, new functionality addition, and
ultimately for making it into something totally diererent.
All CPLD source
code (in VHDL) is available for free from KSI Labs, LLC web site. New releases,
extensions, user-contibuted add-ons etc. will be also available from our web site
as well as precompiled CPLD images (*.pof les) that can be directly written
into the CPLD.
All external connections are made through a single 100-pin connector. There
are 32 galvanically isolated dedicated inputs, 32 Open Drain dedicated outputs,
2 LVDS inputs and 10 LVDS outputs (all galvanically isolated.) LVDS I/O is
supposed to implement SPI-like interfaces to external devices with up to 1MHz
clock rate. Some of them used for communication with DAC/ADC peripherals
on the breakout board (BRK from now on,) some are free for future use with
add-on extension boards.
ALL external I/O is designed as galvanically isolated; there is no provision
for a direct galvanic connection to the PCI board.
Open Drain outputs are
supposed to drive optocouplers so no ground connection is provided. There is
+5V power from the external connector and external devices' optocouplers are
connected between that +5V power and OD outputs.
In the similar fashion
all input optocouplers' LED anodes are connected together and routed to the
external connector for connection to external +5V power and their cathodes are
supposed to be connected to that external 5V ground to pass a signal to the
PC.
3
LVDS I/O is also galvanically isolated with ISO72xx digital isolators. Those
have 2 separate power supplies; the PCI board side is powered from the PC and
connected to CPLD pins while the external side is powered from external 5V
power. There is no galvanic connection between those two sides.
8 of 32 digital inputs use high speed FOD053L optocouplers with 1
agation time for time-critical signals.
devices with 3
1.1
μS
μS prop-
Remaining 24 use regular MOCD207M
propagation time.
Connectors
1.1.1 JTAG
Connector J2 in the center of the board is a standard Altera JTAG connector
for programming the CPLD. It is fully compatible with standard Altera programming tools (ByteBlasterII, USB-Blaster etc.) This connector is keyed to
prevent from inserting the programming tool plug a wrong way.
Other than
that there is nothing more to say about it. CPLD programming is fully documented in QuartusII Web Edition software available for free from Altera web
site. There is a brief programming procedure description in Setting up CEN-
TIPEDE board set for Mach3 document. Here is the schematics fragment with
JTAG connector:
+3.3V
10
8
6
4
2
9
7
5
3
1
R2 10K
R1 10K
J2 JTAG
TDI
TMS
TDO
TCK
R3 10K
Figure 1.1: JTAG Connector
1.1.2 External Connector
External connector is high quality 100-pin N102A0-52E2PC connector from 3M.
All I/O signals come from this connector. Special cable is used for connecting
PCI to BRK board.
It is 1:1 cable and it is made to order when ordering
PCI/BRK boards from
KSI Labs, LLC.
Cable length can be up to 20 ft.
according to the customer's specication.
Here is the external connector pinout and signals description:
4
+5V
J3
V+IN0..7
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
V+IN8..15
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
V+IN16..23
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
V+IN24..31
IN24
IN25
IN26
IN27
IN28
IN29
IN30
IN31
IVCC
MISO1+
MISO1−
MOSI1+
MOSI1−
SPCK1+
SPCK1−
NSS11+
NSS11−
NSS12+
NSS12−
NSS13+
NSS13−
IGND
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
OUT28
OUT29
OUT30
OUT31
IVCC
MISO2+
MISO2−
MOSI2+
MOSI2−
SPCK2+
SPCK2−
NSS21+
NSS21−
NSS22+
NSS22−
NSS23+
NSS23−
IGND
Figure 1.2: External Connector
IN0..31
Input optocouplers cathodes. Connect them to external power nega-
tive (or ground) rail to set input to '1' level. IN0 is bit 0 of DATA_IN
register.
V+IN0..7-V+IN24..32
Input optocouplers anodes in groups of 8.
They
should be connected to the positive rail of an external power supply. There
are series 330
Ω resistors installed for each optocoupler so there is no need
for additional resistors if 5V external power is used.
Those are usually
powered from BRK board 5V power supply. 4 separate pins are used to
spread the load between 4 wires.
OUT0..31
Open Drain outputs for driving external optocouplers. There is
NO
common ground connection on the external connector from PCI board
5
version 1.1 and up.
These outputs
MUST
drive external optocouplers
only to provide galvanical isolation. They should be connected to external
optocouplers LED cathode. Anodes of those LEDs should be connected to
+5V outputs (pins 51,60,69,78.) Series resistors are required for external
optocouplers. They should be designed for 5V operation. OUT0 is bit 0
of DATA_OUT register.
+5V
Power for external optocouplers on OUT0..31 lines. This is taken directly
from PCI bus and should
NOT
be used for anything else (there is no
ground connection anyway.) There is 4 pins for this power to spread the
load between 4 wires. OUT0..31 OD outputs make ground connection for
this power rail when corresponding DATA_OUT register bits set to '1.'
MISO1+/-
SPI1 data input dierential pair.
Not accessible directly from
application software.
MOSI1+/-
SPI1 data output dierential pair.
Not accessible directly from
application software.
SPCK1+/-
SPI1 clock dierential pair. Not accessible directly from applica-
tion software.
NSS1[1..3]+/-
SPI1 chip select dierential pairs. Not accessible directly from
application software.
MISO2+/-
SPI2 data input dierential pair.
Not accessible directly from
application software.
MOSI2+/-
SPI2 data output dierential pair.
Not accessible directly from
application software.
SPCK2+/-
SPI2 clock dierential pair. Not accessible directly from applica-
tion software.
NSS2[1..3]+/-
SPI2 chip select dierential pairs. Not accessible directly from
application software.
IVCC
External +5V power for machine side SPI interface. Usually connected
to BRK board 5V power supply.
IGND
External 5V power supply ground for machine side SPI interface. Usu-
ally connected to BRK board ground.
1.1.3 Extension Connector
Extension connector is used for connecting add-on boards. It is
NOT
isolated
from PC so add-on boards implementing external interface to a machine must
provide their own galvanic isolation.
There is no particular add-on interface implemented for this connector as
of right now (rmware v3.0.1) but it is going to change in near future when
6
add-on boards are out. There is at least one such board in early design stage
as of v3.0.1 rmware time. This interface is NOT software accessible right now
and should have some VHDL code added to use it.
Here is the connector pinout and signals description:
J1
+5V
EX40
EX38
EX36
EX34
EX32
EX30
EX28
EX26
EX24
EX22
EX20
EX18
EX16
EX14
EX12
EX10
EX8
EX6
EX4
EX2
EX0
+3.3V
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
+5V
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
EX41
EX39
EX37
EX35
EX33
EX31
EX29
EX27
EX25
EX23
EX21
EX19
EX17
EX15
EX13
EX11
EX9
EX7
EX5
EX3
EX1
+3.3V
Figure 1.3: Extension Connector
EX0..41
CPLD signals. EX0..41 lines are connected to CPLD pins so they can
be used for any purpose with custom VHDL additions.
Power
Power rails are self-explanatory. They are supposed to power add-on
boards. +5V, +3.3V, and ground all come directly from PCI bus.
7
Chapter 2
FIRMWARE
CENTIPEDE-PCI board is a set of dierent buers/optocouplers/isolators and
one big CPLD. The entire functionality is implemented in the CPLD; all other
components are just simple interface components not implementing any logical
functions.
That means that functionality may by radically changed by pro-
gramming CPLD with dierent rmware. Such design allows for easy hardware
bugxes, almost unlimited exibility, new functionality addition by simply reprogramming the CPLD etc.
It is necessary to understand that CPLD code implements
HARDWARE
unlike some code for an embedded microcontroller that implements FIRMWARE.
The principal dierence is that CPLD code is actually a table of interconnects
between dierent basic hardware blocks that CPLD is made of. In other words
it is a bunch of wires and instructions where each wire is connected.
Micro-
controller rmware, on the other hand, is a PROGRAM i.e a set of instructions that microcomtroller fetches from memory and executes one-by-one. That
means that rmware is always slower because every action is usually a sequence
of instructions. Another rmware disadvantage is that MCU (MicroController
Unit) can only execute a single instruction at a time (actually there are MCUs
that are able of executing several instructions at a single step but that is not
a regular case and there are other limitations) so it can not act fast enough on
several dierent tasks, it can get into an innite loop in one execution branch
and all other tasks will get suspended indenitely and there are other issues
with such approach.
In CPLD, on the other hand we can implement several
dierent units that are working in parallel totally independent of each other.
There is another fundamental dierence between CPLD and MCUthere is
no program running in CPLD. The interconnection table is loaded from internal FLASH-like memory only once (usually on powerup) and then it is pure
hardware operation. It is not bootup like it is in MCU where the initial program is loaded and then that program executes for the entire time the MCU is
operating; it is a one-time
CONFIGURATION
that only executes once.
That does not mean that CPLD can not execute some action sequences but
those sequences are purely hardware ones.
8
Machine gun also performs some
sequence of actions when trigger is pulled but there is no software program in
it. MCU counts pulses by incrementing some variable while CPLD implements
it as a string of triggers changing their states.
Yet another dierence is that unlike MCU CPLD does not have its pin
functions preassigned to particular pin (except a few such as power/ground pins
or JTAG pins for initial programming.) Almost any signal can be connected to
almost any CPLD pin upon initial conguration that makes PCB design much
easier because one can reassign signals to dierent pins if it makes PCB layout
easier. There are some limitations of course but they are not all that strict.
There are dierent ways to make that CPLD (Complex Programmable Logic
Device) conguration table. One can use a pure schematic approach by drawing
schematics with special CAD software and then it is translated to the particular
CPLD device conguration image by special compiler. This is the most precise
way but it is cumbersome and not actually suitable for bigger and more complex designs. Another way is using some kind of HDL (Hardware Description
Language) that describes how the hardware is supposed to operate. Then such
a description is processed by a set of CAD tools that synthesize a schematic implementation of the described behavior. This way is easier to work with, better
suited for big complex designs, more maintainable and more portable between
dierent devices. Here in KSI Labs, LLC we use one of HDL languages, VHDL
for CPLD design. The entire VHDL source for CENTIPEDE-PCI board CPLD
is available for free from our web site so everybody can customize our board as
he sees t and/or change/extend its functionality.
So strictly speaking FIRMWARE is not a right word to call the CPLD
conguration but we will be using it for the lack of better one.
This chapter does NOT describe how to congure the CENTIPEDE set of
boards for use with particular software (e.g. Mach 3;) it is the description what
the board looks like from a programmer's standpoint so he can write his own
software for it.
Please note that rmware may change at every moment so
please visit our web site,
http://www.ksilabs.com
for the latest information.
The included information describes Mach3-specic rmware version 3.0.1 that
is programmed in CENTIPEDE-PCI boards as they shipped. There is also a
Generic GPIO rmware available for this board from our web site that does not
have any particular use as of time of writing but can be used for any task by
writing an appropriate software for it. There is no particular purpose of writing
that rmware but it is released in full binary and source form as a service for
the public. It can be used for any type of control applications and much more.
2.1
PCI Device Registers
CENTIPEDE-PCI is a regular PCI board fully conforming to PCI 2.2 standard.
It has one 4Kbyte PCI Memory BAR that is initialized for proper system mem-
(That might be changed
to KSI Labs, LLC VendorID when it is obtained.) DeviceID is 0x0002,
ory mapping by PC BIOS. VendorID is 0xFEFF
ClassCode 0x078000.
All register osets are from BAR0 base.
9
Registers are
32-bit and
MUST be accessed with 32-bit instructions. Write operations other
that 32-bit will have unpredictable results and probably will lead to faulty operation and computer crash.
Here is the register map:
Register
Oset
Description
DATA_OUT
0x00
Output Data Register, R/W
DATA_IN
0x04
Input Data Register, R/O
DAC
0x08
DAC Data Register, W/O
ADC
0x0c
ADC Data Register, R/W
IRQ_RAW
0x10
Raw IRQ Status Register, R/C
IRQ_MASK
0x14
IRQ Mask Register, R/W
IRQ_STAT
0x18
Masked IRQ Status Register, R/O
MACH_IDX_X
0x1c
Mach3 Axis X Index, R/W
MACH_IDX_Y
0x20
Mach3 Axis Y Index, R/W
MACH_IDX_Z
0x24
Mach3 Axis Z Index, R/W
MACH_IDX_A
0x28
Mach3 Axis A Index, R/W
MACH_IDX_B
0x2c
Mach3 Axis B Index, R/W
MACH_IDX_C
0x30
Mach3 Axis C Index, R/W
MACH_CONFIG
0x34
Mach3 Conguration Register, R/W
MACH_CONFIG2
0x38
Mach3 Second Conguration Register, R/W
MACH_CTL
0x3c
Mach3 Control Register, R/W
MACH_STAT
0x40
Mach3 Status Register, R/C
MACH_FIFO
0x44
Mach3 FIFO Register, W/O
Mach3 Encoders Count Register, R/C
MACH_ENC
0x48
MACH_SPCNT
0x4c
Mach3 Spindle Count, R/O
MACH_SPCTL
0x50
Mach3 Spindle Control, R/W
MACH_CONFIG3
0x54
Mach3 Third Conguration Register, R/W
Table 2.1: CENTIPEDE-PCI/Mach3 Register Map
10
2.2
Registers Description
2.2.1 DATA_OUT, Oset 0x00
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14/CPUMP
D13/SPSTEP
D12/SPDIR
D11/CSTEP
D10/CDIR
D9/BSTEP
D8/BDIR
D7/ASTEP
D6/ADIR
D5/ZSTEP
D4/ZDIR
D3/YSTEP
D2/YDIR
D1/XSTEP
D0/XDIR
Table 2.2: DATA_OUT Register
D0..31
Output Data, R/W. All data written to this register is immediately
reected on External Connector OUT0..31 pins. '1' will make the output
FET to open i.e. the output will go
LOW . In other words writing '1' to a
particular bit will turn the corresponding external optocoupler LED ON.
Read operation will give the current actual output register state. D0..D11
outputs are physically disconnected from output pins when corresponding
Axis (XYZABC) is enabled in MACH_CONFIG register. In this case you
can still read/write the corresponding bits but the actual output pins are
controlled by FIFO outputs so such R/W operations will not have any
eect on the actual physical outputs. Defaults to all '0' on powerup.
xDIR
Direction outputs for x Axis (XYZABC) when that Axis is enabled in
MACH_CONFIG register. In this case the corresponding DATA_OUT
register outputs are not connected to anything. You can write to those
bits and you will read back what you wrote but they are physically dis-
Generates dierent step sequence
(along with corresponding xSTEP output) when put in Boss II
step mode by setting a corresponding bit in MACH_CONFIG3
register.
connected from the output pins.
xSTEP
Step outputs for x Axis (XYZABC) when that Axis is enabled in
MACH_CONFIG register. In this case the corresponding DATA_OUT
register outputs are not connected to anything. You can write to those
bits and you will read back what you wrote but they are physically dis-
Generates dierent step sequence
(along with corresponding xDIR output) when put in Boss II
step mode by setting a corresponding bit in MACH_CONFIG3
register.
connected from the output pins.
11
SPDIR/SPSTEP
Direction and Step outputs for Spindle drive when Dir/Step
Spindle is enabled in MACH_CONFIG2 register. In this case the corresponding DATA_OUT register outputs are not connected to anything.
You can write to those bits and you will read back what you wrote but
they are physically disconnected from the output pins.
CPUMP
Charge Pump output when Charge Pump is enabled in MACH_CONFIG3
register.
In this case the corresponding DATA_OUT register output is
not connected to anything. You can write to this bit and you will read
back what you wrote but it is physically disconnected from the output
pin.
2.2.2 DATA_IN, Oset 0x04
D31/ENC4_B
D30*/ENC4_A
D29/ENC3_B
D28*/ENC3_A
D27/ENC2_B
D26*/ENC2_A
D25/ENC1_B
D24*/ENC1_A
D23*/SP_IDX
D22/SP_TIMING
D21*
D20
D19*/ESTOP_SW
D18/PROBE_SW
D17*/CHome
D16/CMinus
D15/CPlus
D14/BHome
D13/BMinus
D12/BPlus
D11/AHome
D10/AMinus
D9/APlus
D8/ZHome
D7/ZMinus
D6/ZPlus
D5/YHome
D4/YMinus
D3/YPlus
D2/XHome
D1/XMinus
D0/XPlus
Table 2.3: DATA_IN Register
D0..D31
Input Data, R/O. IN0..31 External Connector data state directly
from connector pin latched on every PCI clock (through an optocoupler.)
The same rule as for DATA_OUT register applies'1' means there is current through the input optocoupler LED (switch connected to the corresponding BRK board terminal is CLOSED,) '0' means optocoupler LED
is OFF. Bits marked with '*' have fast optocouplers on inputs on rev.1.0
CENTIPEDE-PCI board. Starting from rev.1.1 fast optocouplers are on
bits 24..31.
Input changes are reected immediately.
Raw state for all
optional signals (xHome etc.) can be read from corresponding Dxx bits if
needed. Raw means it is ELECTRICAL, not LOGICAL state i.e. it only
tells if there is current through an optocoupler or not. That can be interpreted by the user software (Driver) and hardware as either activated or
not depending on Negated setting in appropriate conguration registers
or in software conguration.
xPlus/xMinus
Plus and minus side Limit Switch inputs for x Axis (XYZ-
ABC) when the corresponding Axis is enabled in MACH_CONFIG register. Those perform a specic Hardware action when the corresponding
12
axis is enabled. They stop all motion and activate EStop hardware state.
IRQ is also generated when one of these is activated (if enabled.)
xHome
Home Switch inputs for x Axis (XYZABC) when the corresponding
Axis is enabled in MACH_CONFIG register.
MACH_IDX register for
corresponding axis is frozen when this signal is activated so exact hit position can be read. Actual Index Counters are NOT aected so the current
position information is not lost.
MACH_IDX registers are transparent
latches that mirror Index Counters all the time but latch the last reading when Probe or Home Switch is hit thus giving the exact hit position.
Once read they resume their normal operation if the corresponding switch
is not active or not enabled any more. Home Switch freezes only the corresponding axis Index while Probe Switch freezes ALL Indexes.
IRQ is
generated when one of these switches is activated so the Driver software
can take appropriate action immediately.
PROBE_SW
Digital Probe Switch input for probing. Its state can be read
from a corresponding bit but it also performs some hardware actions when
ALL MACH_IDX registers are frozen when this signal is acti-
activated.
vated so exact hit position can be read. Actual Index Counters are NOT
aected so the current position information is not lost. MACH_IDX registers are transparent latches that mirror Index Counters all the time but
latch the last reading when Probe or Home Switch is hit thus giving the
exact hit position. Once read they resume their normal operation if the
corresponding switch is not active or not enabled any more. Home Switch
freezes only the corresponding axis Index while Probe Switch freezes ALL
Indexes.
IRQ is generated when this switch is activated so the Driver
software can take appropriate action immediately.
ESTOP_SW
Emergency Stop Switch input.
That can
NOT be disabled
MUST be a
or recongured to other polarity (not Negated) and it
normally closed switch. If it is OPEN i.e. there is no current through its
optocoupler hardware will be in EStop hardware mode and there is
NO
way to get it out of this state until this switch is closed. In other words this
switch is
ABSOLUTELY
required and it
MUST be a Push-To-Break
type.
SP_TIMING
Multiple pulse per revolution Spindle rotation sensor input.
This is used for reporting Spindle RPM and for Z Axis motion control
when lathe threading or rigid tapping.
On every transition on this in-
put (rising or faling depending on conguration bit in MACH_CONFIG2
register) the internal counter contents is transferred to MACH_SPCNT
register, counter is reset, and then incremented on each and every PCI
clock pulse. IRQ is generated on SP_TIMING transition so software can
read MACH_SPCNT register and act appropriately by calculating actual
Spindle RPM and displaying it or adjusting Z Axis speed thus gearing it
to the Spindle. There is also a debouncing counter that is loaded with a
13
value set in MACH_CONFIG2 register and started decrementing every
15
μS on a transition at this input.
Input state is ignored until this counter
counted down to zero. This cycle repeats on all consecutive transitions,
both low-to-high and high-to-low.
SP_INDEX
Single pulse per revolution Spindle Index sensor.
This is used
in lathe threading to start Z Axis motion at exactly the same spot on
each consecutive threading pass.
This is done in hardware by holding
step output until SP_INDEX pulse detected. To do this software should
write '1' in MACH_CTL register WAIT4PULSE bit.
This will put all
step output (except Spindle) on hold and will restart it when SP_INDEX
is detected. FIFO will be still taking step data while this hold is in effect until it is full.
Then, when Index pulse comes the very rst FIFO
entry will be output immediately. This input also performs all the functions of SP_TIMING if that is not enabled.
There is a separate de-
bouncing counter for SP_INDEX working in exactly the same fashion as
SP_TIMING. IRQ is also generated on each SP_INDEX pulse.
2.2.3 DAC, Oset 0x08
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 2.4: DAC Register
D0..15
SPI Transmit Holding Register (THR.) Once written data is transferred
bit-by-bit to TLV5617A 2-channel 0-10V output DAC on the BRK board.
Each write to DAC register clears corresponding bit in IRQ_RAW register
and that bit goes back to '1' once that written data is transferred to
the DAC. This register is Write-Only. Please read TLV5617A datasheet
and Mach3 Driver source to learn how to use this register.
that despite only 16 bits are used all writes
instructions.
X
Don't care.
14
MUST
Please note
be done as 32-bit
2.2.4 ADC, Oset 0x0c
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 2.5: ADC Register
D0..9
SPI Transmit Holding Register (THR) on write, Receive Holding Regis-
ter (RHR) on read. This is a second SPI controller, separate from DAC
SPI. Once written data is transferred bit-by-bit to TLV1544 4-channel
0-10V input ADC on the BRK board.
At the same time ADC data is
received into RHR. Each write to ADC register clears corresponding bit
in IRQ_RAW register and that bit goes back to '1' once that written data
is transferred to the ADC (and ADC data is received into RHR.) Reading
ADC register (RHR) does not have any eect on SPI controller and IRQ
state, only write starts a new SPI cycle. Please read TLV1544 datasheet
and Mach3 Driver source to nd out how to use this register. Please note
that despite only 10 bits are used all reads and writes
MUST be done as
32-bit instructions.
X
Don't care on write, '0' on read.
2.2.5 IRQ_RAW, Oset 0x10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MACH_SP_TIM
MACH_SP_IDX
MACH_HomeC
MACH_HomeB
MACH_HomeA
MACH_HomeZ
MACH_HomeY
MACH_HomeX
MACH_PROBE
MACH_FOVF
MACH_FAULT
MACH_DONE
MACH_TMR
ADC
DAC
Table 2.6: IRQ_RAW Register
DAC
DAC SPI Controller is Idle and ready to take new data to be sent to
TLV5617A DAC on the BRK board.
This bit is always set when DAC
SPI Controller is Idle. Write data to its THR and write '1' to this bit to
reset it. It will get set again when transfer is complete.
15
ADC
ADC SPI Controller is Idle and ready to take new data to be sent to
TLV1544 ADC on the BRK board. This bit is always set when ADC SPI
Controller is Idle. Write data to its THR and write '1' to this bit to reset
it. It will get set again when transfer is complete.
MACH_TMR
Mach3 timer interrupt.
Periodic interrupt every 5th cycle
when the board in is RUN condition.
Cycle period is determined by
CYCLE setting in MACH_CTL register. Write '1' to this bit to clear.
MACH_DONE
All data in FIFO were sent out and last cycle has ended so
board got idle. Write '1' to this bit to clear.
MACH_FAULT
Fault interrupt. Raised when any of Limit Switches hit, or
Emergency Stop (EStop from now on) button is activated.
Cleared by
writing '1' in this bit if the condition that caused it is cleared. Will not
reset if condition is still present. FIFO is purged on this event, periodic
It can be also activated by Watchdog overow
if it is enabled by setting a bit in MACH_CONFIG3 register.
timer stays ticking.
MACH_FOVF
FIFO overow.
Theoretically should not happen because
hardware ignores all FIFO writes when it is full but anyways...
Write
'1' to clear.
MACH_PROBE
Probe Switch hit. Write '1' to clear. Will not reset if the
switch is still activated.
All axes indexes are frozen on this event until
they are read, PROBE_HIT bit in MACH_STAT register is written with
'1,' and this IRQ is acknowledged by writing '1' to its bit. The freeze is
done by stopping transparent latches between actual index counters and
IDX registers so they keep the last data while index counters continue
counting so the running position is not lost.
MACH_HOMEx
Home Switch for x Axis (XYZABC) is hit.
Write '1' to
clear. Will not reset if the switch is still activated. The corresponding axis
index is frozen on this event until it is read, corresponding HOME_HIT bit
in MACH_STAT register is written with '1,' and this IRQ is acknowledged
by writing '1' to its bit. The freeze is done by stopping transparent latches
between actual index counters and IDX registers so they keep the last data
while index counters continue counting so the running position is not lost.
MACH_SP_IDX
Spindle Index Pulse detected.
This is single pulse per
revolution Index sensor that is used for starting lathe threading pass. It
doubles at Spindle Timing if no Timing sensor installed. Write '1' to this
bit to clear.
MACH_SP_TIM
Spindle Timing Pulse detected.
This is multiple pulse
per revolution Timing sensor that is used for measuring Spindle RPM for
Mach DRO and gearing Z Axis to the Spindle while threading or rigid
tapping. See DATA_IN register for Spindle Index and Timing operation
description. Write '1' to clear.
16
2.2.6 IRQ_MASK, Oset 0x14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MACH_SP_TIM
MACH_SP_IDX
MACH_HomeC
MACH_HomeB
MACH_HomeA
MACH_HomeZ
MACH_HomeY
MACH_HomeX
MACH_PROBE
MACH_FOVF
MACH_FAULT
MACH_DONE
MACH_TMR
ADC
DAC
Table 2.7: IRQ_MASK Register
X
Don't care. Those bits can be written to and read back but they don't have
any eect for now.
They might be used in the future when additional
functionality is implemented and add-on boards are out.
Rest
Remaining bits are used to mask corresponding IRQ_RAW interrupt bits.
Default to all '0' on powerup so no IRQs to PCI bus is generated.
2.2.7 IRQ_STAT, Oset 0x18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MACH_SP_TIM
MACH_SP_IDX
MACH_HomeC
MACH_HomeB
MACH_HomeA
MACH_HomeZ
MACH_HomeY
MACH_HomeX
MACH_PROBE
MACH_FOVF
MACH_FAULT
MACH_DONE
MACH_TMR
ADC
DAC
Table 2.8: IRQ_STAT Register
0 Unused, read as '0.'
Rest Remaining bits are a result of bitwise AND on IRQ_RAW and IRQ_MASK
registers. PCI IRQ signal is an OR on all bits of this register. That means
that it is only raised when the corresponding bit is set in both IRQ_RAW
and IRQ_MASK. All bits are read-only. To reset (acknowledge) a particular IRQ '1' should be written to a bit in IRQ_RAW register.
17
2.2.8 MACH_IDX_[XYZABC], Osets 0x1c, 0x20, 0x24,
0x28, 0x2c, 0x30
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 2.9: MACH_IDX_[XYZABC] Registers
D0..31
Current Axis position, R/W. Incremented/Decremented on each and
every step output to the Axis depending on step direction.
Signed (2-
complement) 32-bit INT. Actual counters are connected to these registers
through transparent latches.
Those latches are open most of the time
so registers show the current positions. They are frozen when Home or
Probe Switch event occurs so the exact hit position can be read.
unfreeze them the Switch Hit event should be cleared.
To
This is done by
writing '1' to a corresponding bit in MACH_STAT register. To prevent
this condition from reoccuring if a switch is still activated one can rst
disable that switch in MACH_CONFIG register and then write '1' to
MACH_STAT bit.
2.2.9 MACH_CONFIG, Oset 0x34
PROBE_EN
PROBE_NO
C_HOME_EN
C_HOME_NO
C_LIMS_NO
C_DIR_REV
C_EN
B_HOME_EN
B_HOME_NO
B_LIMS_NO
B_DIR_REV
B_EN
A_HOME_EN
A_HOME_NO
A_LIMS_NO
A_DIR_REV
A_EN
Z_HOME_EN
Z_HOME_NO
Z_LIMS_NO
Z_DIR_REV
Z_EN
Y_HOME_EN
Y_HOME_NO
Y_LIMS_NO
Y_DIR_REV
Y_EN
X_HOME_EN
X_HOME_NO
X_LIMS_NO
X_DIR_REV
X_EN
Table 2.10: MACH_CONFIG Register
x_EN
Axis x (XYZABC) enable. Enables corresponding axis hardware. Axis
x(Plus,Minus,Home) signals are connected to the corresponding DATA_IN
bits, x(DIR/STEP) outputs switched from DATA_OUT bits to corresponding FIFO outputs, Limit Switches logic is enabled so MACH_FAULT
IRQ will be generated.
18
x_DIR_REV
Axis x (XYZABC) Direction Signal will be inverted. In Mach3
'0' means move to PLUS side. That is what is stued in FIFO for each
and every Axis.
Actual drives might treat direction signals dierently.
To accomodate all of them DIR output is inverted if these bits are set to
'1.' It is only the actual physical output line that is inverted, all internal
signals are still the same and MACH_IDX registers are Incremented on
every step when corresponding DIR bit is '0.'
x_LIMS_NO
Axis x (XYZABC) Limit Switch is Normally Open (NO.) Usu-
ally it is recommended that Limit/Home/Probe/EStop switches
BREAK
the connection when activated, i.e. they are Normally Closed (NC) until
activated. That ensures the machine will be saved from damage even if
the switch cable is cut or otherwise disconnected. If the switch is NO its
activation will not be detected if it is disconnected and the machine can
be damaged. If it is necessary to use NC switches this bit should be set
to invert the default logic. It can also be used to make the switch signal
always inactive if there is no particular switch on the machine instead
of shorting that pin (all axes signals are xed in hardware and there is
no way to disable a Limit Switch or use its pin for something else if an
Axis is enabled.) There is only ONE LIMS_NO bit per axis so BOTH of
switches must be either NO or NC, mix is not allowed.
x_HOME_NO
Axis x (XYZABC) Home Switch is Normally Open. Every-
thing from x_LIMS_NO applies here.
x_HOME_EN
Axis x (XYZABC) Home Switch Enable. To avoid unneces-
sary interrupts and to provide for resetting HOME_HIT conditions Home
Switches are only enabled briey during Homing cycles. These are per-axis
Enable bits.
PROBE_NO
Probe Switch is Normally Open.
Everything written about
NO/NC switches above applies.
PROBE_EN
Probe Switch Enable. It is only enabled when probing, disabled
all other time to provide for PROBE_HIT condition reset and eliminame
unnecessary interrupts.
19
2.2.10 MACH_CONFIG2, Oset 0x38
SP_TIM_INV
SP_TIM_EN
TIM_DB[8..7]
TIM_DB[6..3]
TIM_DB[2..0]
IDX_DB[9]
IDX_DB[8..5]
IDX_DB[4..1]
IDX_DB[0]
SP_DIR_INV
SP_STEP_INV
SP_DIRSTEP
SP_IDX_INV
SP_IDX_EN
C_STEP_INV
B_STEP_INV
A_STEP_INV
Z_STEP_INV
Y_STEP_INV
X_STEP_INV
Table 2.11: MACH_CONFIG2 Register
x_STEP_INV
Axis x Step signal Inverted.
Usually Step Signal is output
as a pulse that turns the drive Step input optocoupler ON. Some drives
may require inverted signal.
These bits invert STEP outputs when set,
per axis.
SP_IDX_EN Spindle Index signal Enable.
SP_IDX_INV Spindle Index signal is Inverted i.e.
turns CENTIPEDE op-
tocoupler OFF to indicate Index pulse.
SP_DIRSTEP Enables Dir/Step Spindle when set.
SP_STEP_INV Spindle Step signal Inverted i.e. drive Step input optocoupler ON to OFF transition is used to make a step.
SP_DIR_INV
Spindle Dir signal Inverted. Set this if your Spindle rotates
in the wrong direction.
IDX_DB[0..9]
Spindle Index signal debounce time in 15
signal state is ignored for this number of 15
μS
μS
units.
Index
intervals after initial tran-
sition. Write '0' to disable debouncing.
TIM_DB[0..8]
Spindle Timing signal debounce time in 15
signal state is ignored for this number of 15
μS
μS
units.
Index
intervals after initial tran-
sition. Write '0' to disable debouncing.
SP_TIM_EN Spindle Timing signal Enable.
SP_TIM_INV Spindle Timing signal is Inverted
optocoupler OFF to indicate Timing pulse.
20
i.e.
turns CENTIPEDE
2.2.11 MACH_CTL, Oset 0x3c
WAIT4PULSE
FIFO_PURGE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MACH_CYCLE[10..7]
MACH_CYCLE[6..3]
RUN
MACH_CYCLE[2..0]
RESET
NO_LIMITS
SIMULATE
ESTOP_REQ
Table 2.12: MACH_CTL Register
SIMULATE
When set to '1' motor control outputs are kept at '0' state, no
Steps output. Everything else works as usual so this is the most precise
Dry Run simulation possible.
ESTOP_REQ
Programmatic Emergency Stop (EStop.)
Stops the CEN-
TIPEDE FSM, purges FIFO. Board goes in EStop state; only periodic
timer IRQs are generated.
NO_LIMITS
Makes the board to ignore any of Limit Switches.
Normally,
when this bit is not set CENTIPEDE immediately goes into EStop state,
FIFO purged, FSM stopped, FAULT IRQ generated, only periodic timer
is ticking. Board will NOT go out of EStop until the condition is removed
i.e.
machine is moved out of Limit Switches.
Setting this bit overrides
this behaviour thus allowing to jog o the switch.
RUN
Setting this bits allows the Finite State Machine (FSM) to run so the
actual Mach3 work can be done.
RESET
Setting this bit generates board RESET signal most registers are
set to all zero, FSM stopped, FIFO purged, periodic timer is also stopped
so no IRQs.
This is self-clearing bit because reset sets all the registers
to their initial state (almost always all zeroes) thus resetting this very bit
among others.
MACH_CYCLE[0..10]
Mach3 Cycle Period, 11 bit. This eld determines
kernel frequency or Engine frequency as it is called in Mach3. Every Mach3
cycle will be this number of PCI clocks long. PCI Clock is roughly 30 nS
that corresponds to standard 33.333 MHz PCI Frequency (the exact value
is measured by the Mach Driver.) For 100 KHz, e.g. the value is 333 (33.3
MHz / 333 = 100 KHz.)
FIFO_PURGE
Writing '1' to this bit will purge the FIFO FIFO pointer
(internal) will be set to the rst element, i.e. FIFO will become empty.
21
This bit is not sticky i.e. action is only taken once on the write operation
and its value is not saved. That means there is no need to write '0' there
after writing '1.'
WAIT4PULSE
Writing '1' to this bit will make CENTIPEDE put all step
data on hold until Spindle Index Pulse. This is used for lathe threading
to start each consecutive thread pass at exactly the same spot. This bit
is not sticky i.e. action is only taken once on the write operation and its
value is not saved. That means there is no need to write '0' there after
writing '1.'
X
Don't care.
Please note that there is no Step Pulse settings any more. It did not make sence
to have them at all because ALL stepper/servo drives we are aware of only state
MINIMUM pulse width.
They all make step on Step input TRANSITION,
either low-to-high or high-to-low.
That is why CENTIPEDE step generation
has changed.
Now we generate step pulses as transitions from inactive to active state
exactly in the middle of each Mach Cycle period and resetting it back to inactive at the very end of that cycle. The exact meaning of active depends on
x_STEP_INV bits in MACH_CONFIG2 register. All Step signals are exactly
one Mach Cycle wide with actual Step transition happening at the middle of it.
In Mach terms (Motor Tuning dialog) that means that both Dir and Step Pulse
are
ALWAYS half of Mach Cycle period i.e. half of Kernel Frequency period.
For 100KHz Kernel Frequency they are both 5
μS.
Mach3 settings are ignored
by the driver.
That allowed to simplify our hardware implementation a little bit thus freeing CPLD resources for other purposes and gave us some additional benets.
One of those is that step is ALWAYS taken at the middle of Mach Cycle that
reduces step jitter when lathe threading or rigid tapping.
2.2.12 MACH_STAT, Oset 0x40
RUNNING
ESTOP
BUSY
SP_STOPPED
WD_OVF
X
FIFO_FULL
FIFO_EMPTY
FIFO_ROOM[0]
ProbeHit
CHomeHit
CMinusHit
CPlusHit
BHomeHit
BMinusHit
BPlusHit
FIFO_ROOM[4..1]
AHomeHit
AMinusHit
APlusHit
ZHomeHit
ZMinusHit
ZPlusHit
YHomeHit
YMinusHit
YPlusHit
XHomeHit
XMinusHit
XPlusHit
Table 2.13: MACH_STAT Register
22
xPlusHit
Axis x (XYZABC) Plus side Limit Switch hit. This is NOT a switch
state but the indicator it's been hit. This event generates FAULT interrupt and forces board into EStop. Writing '1' to these bits will clear the
condition if the Limit Switch is no longer activated. If the switch is still
active it will have no eect unless NO_LIMITS bit is set in MACH_CTL
register.
xMinusHit Same as above for Minus side Limit switch.
xHomeHit Axis x (XYZABC) Home Switch hit. Freezes the IDX register for
the aected axis, stays set until cleared with writing '1' to a particular
bit.
Such a write will have no eect if condition still exists.
Recom-
mended action is read the frozen value (hit point,) disable the switch
in MACH_CONFIG, reset with writing '1.' Usually Home Switches are
only enabled briey on Homing forward pass and disabled right after the
switch is hit. Resetting a particular bit unfreezes the corresponding axis
IDX register so it starts giving the actual position.
FIFO_ROOM[0..4]
Current free space left in FIFO. Used by the driver to
make a decision on how many steps it can push in FIFO.
FIFO_EMPTY
Set when FIFO is empty. Indicator bit, R/O. Resets auto-
matically if there is at least one entry in FIFO and its cycle is not nished.
FIFO_FULL
No more room in FIFO. R/O, self-resets when the rst entry is
popped.
WD_OVF
Watchdog timer overow. MACH_FAULT interrupt is generated
on this event and system goes in EStop.
This bit allows to check if
MACH_FAULT has been caused by Watchdog event.
Watchdog oper-
ation is detailed in MACH_CONFIG3 register desctription.
Will not
self-reset until Watchdog is reset.
SP_STOPPED
Spindle stopped. Either Dir/Step Spindle is stopped (if en-
abled) or no Spindle Index/Timing pulses detected for more than 8 seconds.
BUSY
CENTIPEDE is busy i.e. FIFO is not empty and there are still cycles
to do. R/O, self-clearing.
ESTOP
Board is in EStop state Limit Switch hit, EStop button activated,
connection to BRK board lost, or ESTOP_REQ bit set in MACH_CTL
register. Writing '1' to this bit will clear EStop if the condition that forced
CENTIPEDE in that state is no longer active. Write will have no eect
if condition persists. Will not go away by itself when condition removed;
writing '1' to reset is required.
RUNNING
Indicator bit, R/O meaning the board is up and running. Run-
ning means board was congured properly and RUN bit set in MACH_CTL.
23
EStop does NOT aect this bit board can be running but in EStop condition. '0' in this bit means FSM is stopped and board is not active, even
the periodic timer is stopped.
X
Don't care.
2.2.13 MACH_FIFO, Oset 0x44
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CStep
CDir
BStep
BDir
AStep
ADir
ZStep
ZDir
YStep
YDir
XStep
XDir
Table 2.14: MACH_FIFO Register
xDir
Axis x (XYZABC) Direction for current step. '0' means move to the Plus
direction. FIFO is 20 entries deep. That number is chosen because Mach3
outputs Planned Motion points in sets of 5 so FIFO is made a multiple
of 5. The rst entry written to FIFO will be automatically output to the
motors by CENTIPEDE hardware on the next cycle. Then it will remove
it automatically and pop the next one from FIFO until no more entries
left. It pops one entry each CENTIPEDE cycle. Periodic timer interrupt
is generated every 5th cycle so the driver ISR can load another set of 5
steps to FIFO.
xStep
Axis x (XYZABC) Step signal. Step pulse will be generated if it is '1'.
Everything from xDir also applies here. As usual only 32-bit writes should
be used. This is a W/O register, reads are not guaranteed to return any
particular value.
2.2.14 MACH_ENC, Oset 0x48
ENC4_CNTR[7..0]
ENC3_CNTR[7..0]
ENC2_CNTR[7..0]
ENC1_CNTR[7..0]
Table 2.15: MACH_ENC Register
ENCx_CNTR[7..0]
8-bit counter for Encoder x (1..4.) Signed (2-complement)
CHAR. Increments/Decrements on Quadrature Encoder rotation depending on direction. Registers are R/O and they are reset to zero after each
read. That is done to save on CPLD resources the main 32-bit counter
24
is in the software driver and these 8-bit counters are used as Change from
last read.
Every periodic timer tick driver reads all these counters and
adds them to the main 32-bit counters. Decoder logic for quadrature encoders is all-hardware, x4 multiplying i.e. every transition is detected so
the actual resolution is 4 times of encoder stated one. That means that
e.g. 2500 CPR encoder will give 10000 steps per revolution.
2.2.15 MACH_SPCNT, Oset 0x4c
X
X
X
X
SP_CNT[27..24]
SP_CNT[23..16]
SP_CNT[15..8]
SP_CNT[7..0]
Table 2.16: MACH_SPCNT Register
SP_CNT[0..27]
Spindle Count. Number of PCI Clock pulses between last 2
Spindle Timing (or Spindle Index if Timing is not enabled) pulses. ReadOnly.
X
Don't care.
2.2.16 MACH_SPCTL, Oset 0x50
X
X
X
X
FAKE_PULSE
SP_RUN
SP_DIR
SP_DIV[24]
SP_DIV[23..16]
SP_DIV[15..8]
SP_DIV[7..0]
Table 2.17: MACH_SPCTL Register
SP_DIV[0..24]
Dir/Step Pulse Frequency Divisor. Steps are generated by di-
viding PCI clock. This is a value that determines resulting step frequency
e.g.
Dir/Step Spindle RPM. Every time internal counter decrements to
zero Step output is inverted and counter is reloaded with SP_DIV value
(this is all done by the hardware; SP_DIV is stored in a register when
written so it only needs to be written once for particular RPM.) For a full
step pulse 2 such transitions needed so this value must be calculated to get
a frequency twice the desired RPM multiplied by steps per rotation. E.g.
if we want to get 300 RPM from a motor with 1000 steps per revolution
we should feed it with 300(RPM)
/
60(sec/min)
*
1000(steps/rev) = 5
KHz pulse rate. We need 2 transitions per step so we should program our
25
divisor for 5 KHz
* 2 = 10 KHz frequency.
PCI clock is usually 33.333MHz
so to get 10 KHz we should use 33.333(MHz)
/
10(KHz) = 3333 divisor
value.
SP_DIR Dir signal for Dir/Step Spindle.
SP_RUN Go signal. Set this to '1' to actually start the Spindle, set to '0' to
stop it.
FAKE_PULSE
This bit imitates Spindle Timing pulse.
It is only used on
Driver startup to measure actual PCI clock frequency. This is Write-Only
bit.
X
Don't care. No eect on write, read back as '0.'
Please note that there is no Step Pulse settings. It did not make sence to have
them at all because ALL stepper/servo drives we are aware of only state MIN-
IMUM pulse width. They all make step on Step input TRANSITION, either
low-to-high or high-to-low. Our Step Pulses are actually a constant 50% Duty
Cycle square wave.
This is generated in hardware without any need for sot-
ware intervention once SP_DIV is programmed and SP_RUN is set. Software
only has to intervene when Spindle RPM or some other state (e.g. Direction or
Run/Stop) needs to be changed.
2.2.17 MACH_CONFIG3, Oset 0x54
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
WD_ENABLE
CPUMP_INV
CPUMP_5KHZ
CPUMP_ALWAYS
CPUMP_ENABLE
SEQ_ENABLE
Table 2.18: MACH_CONFIG3 Register
SEQ_ENABLE
Setting this bit to '1' inserts a step sequencer between inter-
nal Step/Dir signals and Step/Dir outputs for all axes. That means there
will be steady
state on Step/Dir pairs changing with each step taken and
pulses . This sequencer is made
kept until the next step instead of Step
for particular machines - Bridgeport Series II BOSS 6 Mill. It allows to
make a quick retrot by keeping its existing motors and drives, just by disconnecting its ZDI board from Axis Drives and connecting CENTIPEDE
outputs to those drives.
Step sequence consists of 4 states.
26
Changing
state to the next one makes existing Drives/Motors make a step in one
direction; for opposite direction state should be changed to a previous one.
State table wraps around after the rst step (if going backwards) to the
last one and vice versa for forward direction. Here is the state table:
CPUMP_ENABLE
Pin13
Pin19
L
L
H
L
H
H
L
H
Enable ChargePump.
Setting this bit to '1' enables
50% duty cycle signal output on Out14 output. It is used as indication
that Mach3 itself, the driver, and hardware is alive and well. Usually used
with cheap Parallel Port breakout boards but it is also here if somebody
really needs it.
Unlike those cheap boards this signal is generated and
controlled by CENTIPEDE rmware, no Mach3 cooperation required. If
not congured to output constantly (see below) it will be only output if
Mach3 is running and CENTIPEDE is not in EStop state.
CPUMP_ALWAYS
ever it
ChargePump output will not stop in EStop state. How-
WILL stop if Mach3 is not running.
CPUMP_5KHZ
If this bit is set to '1' ChargePump will output signal of
about 5kHz frequency. Otherwise it is about 12.5kHz.
CPUMP_INV
Invert ChargePump signal if set to '1.' It doesn't make any
dierence when signal is running but aects the ChargePump output pin
(Out14) state when signal is stopped. It will stop at
LOW
pin is not set otherwise that pin will be kept
when ChargePump
HIGH
state if this
signal is stopped.
WD_ENABLE
Write '1' to enable watchdog timer. Watchdog is 4-bit binary
counter incremented on every timer interrupt request (doesn't matter if
timer IRQ is enabled or not) and reset on every timer interrupt acknowledgement. When it overows MACH_FAULT interrupt is generated, all
Mach3 activity stops (except timer interrupts) and watchdog timer gets
frozen in overown state. There is only one way to get out of this state
- disable and reenable watchdog.
X
Don't care.
27
Chapter 3
Appendix A - Hardware
dierences between rev.1.0
and rev.1.1
There are some dierences between rev.1.0 and rev.1.1 CENTIPEDE-PCI boards.
They are not all that signicant but there some caveats.
ˆ
First of all, there were 4 unpopulated footprints for optional oscillator on
rev.1.0 board (elements R4, C15, U2, and R5) close to the boards center.
Those were removed completely from rev.1.1 PCB. There is absolutely no
impact because those elements were never used.
ˆ
Rev.1.0 board has 4 out of 8 fast optocouplers on dierent input lines
(see section 2.2.2.) It is not very likely somebody would use that feature
but if he would one should take care to assign data lines properly with
application software (e.g. conguration editor or whatever it's called) for
his particular board revision.
ˆ
As a result of the above CPLD project le diers between those 2 revisions. VHDL code is absolutely identical between the two but there are
some changes in pin assignments in centipede_pci.qsf le and resulting
centipede_pci.pof le is dierent.
careful anyway.
Changes are minimal but please be
All future CPLD rmware will be released in versions
for both rev.1.0 and rev.1.1 PCI boards. There is no dierences between
those revisions from software point of view.
ˆ
IMPORTANT!
Rev.1.0.
PCI board had PCI bus
GROUND
con-
nected to pins 69 and 78 of the External Connector, NOT +5V power. It
had 2 +5V power pins (51 and 60) and 2 GROUND pins (69 and 78.) On
rev.1.0 CENTIPEDE-BRK board pins 69 and 78 of the mating connectors are
NOT CONNECTED to anything so it works OK with rev.1.0
28
CENTIPEDE-PCI board. Rev.1.1 PCI board will also work just ne with
rev.1.1 BRK board though 2 +5V conductors in the cable will not be
But rev.1.0 PCI board can NOT be used with rev.1.1 BRK
board because the latter has pins 51, 60, 69, and 78 all connected together that will make a short circuit between PC +5V
and ground.
used.
ˆ
Other than that those boards absolutely identical and fully compatible
with each other.
29
Chapter 4
Appendix B CENTIPEDE-PCI rev.1.0
Schematics
30
+3.3V
C13
PCIEN# B16
EX32
C12
EX40
A15
D12
EX41
B14
EX28
C11
EX38
B13
EX30
D11
EX39
A13
E11
EX36
B12
EX24
C10
EX37
A12
U1
IO2_1
IO2_2
IO2_3
IO2_4
IO2_5
IO2_6
IO2_7
IO2_8
IO2_9
IO2_10
IO2_11
IO2_12
IO2_13
IO2_14
EX41
EX39
EX37
EX35
EX33
EX31
EX29
EX27
EX25
EX23
EX21
EX19
EX17
EX15
EX13
EX11
EX9
EX7
EX5
EX3
EX1
9
7
5
3
1
R3 10K
+3.3V
10
8
6
4
2
J2 JTAG
+3.3V
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
+3.3V
+5V
10nF
0.1uF
10nF
0.1uF
10nF
0.1uF
10nF
0.1uF
C1
C2
C3
C4
C5
C6
C7
C8
VCCIO2 I/O POWER
BANK 2
EPM2210 FBGA256
IO2_15
IO2_16
IO2_17
IO2_18
EX26 D10
EX34 B11
E10
EX35 A11
J1 50
48
EX4046
EX3844
EX3642
EX3440
EX3238
EX3036
EX2834
EX2632
EX2430
EX2228
EX2026
EX1824
EX1622
EX1420
EX1218
EX1016
EX8 14
EX6 12
EX4 10
EX2 8
EX0 6
4
2
D4 EX0
B1 EX1
D5 EX4
A2 EX3
C5 EX6
B3 EX5
C6 EX10
C4 EX2
D6 EX8
B4 EX7
E6
IO2_53
IO2_52
IO2_51
IO2_50
IO2_49
IO2_48
IO2_47
IO2_46
IO2_45
IO2_44
IO2_43
+5V
1 ENA
U2
66MHz
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
VCCIO1
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
OUT
+3.3V
IO2_34
IO2_33
IO2_32
IO2_31
IO2_30
IO2_29
IO2_42
IO2_41
IO2_40
IO2_39
IO2_38
IO2_37
IO2_36
3
A6
C8
B7
D8
A7
E8
A4
C7
B5
D7
A5
E7
B6
H7
H9
J8
J10
F7
G6
K11
L10
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
R5 33
EX17
EX18
EX19
EX16
EX21
EX15
EX9
EX14
EX11
EX12
EX13
EXPANSION
H8
H10
J7
J9
F10
G11
K6
L7
L8
L9
T3
T14
C16
H11
J11
P16
A3
A14
F8
F9
C1
H6
J6
P1
U1
EX33 B10
EX20 C9
EX31 A10
EX22 D9
EX29 B9
E9
EX27 A9
EX25 A8
EX23 B8
IO2_20
IO2_21
IO2_22
IO2_23
IO2_24
IO2_25
IO2_26
IO2_27
IO2_28
4
VCC
66MHZ
TMS
TDO
TCK
TDI
LSS12
LOSI1
LSS13
LPCK1
I18
LSS11
LSS22
LOSI2
LSS21
LPCK2
U1
P4
R1
P5
T2
N5
R3
P6
R4
N6
T4
M6
R5
P7
T5
U1
P14
N13
P15
M14
N14
M13
N15
L14
N16
L13
M15
L12
M16
L11
O24 D3
C2
O23 E3
C3
O25 E4
D2
E5
D1
O22 F3
O16 E2
O26 F4
O8 E1
F5
O15 F2
LCLK
LREQ#
LGNT#
LAD27
LAD31
LAD29
LAD30
LC/BE3#
LAD28
LAD25
LAD26
LINTA#
LAD24
LRST#
U1
IO3_1
IO3_2
IO3_3
IO3_4
IO3_5
IO3_6
IO3_7
IO3_8
IO3_9
IO3_10
IO3_11
IO3_12
IO3_13
IO3_14
IO4_1
IO4_2
IO4_3
IO4_4
IO4_5
IO4_6
IO4_7
IO4_8
IO4_9
IO4_10
IO4_11
IO4_12
IO4_13
IO4_14
M9
M8
IO_DEV_CLRn
IO_DEV_OE
VCCIO3 I/O POWER
BANK 3
EPM2210 FBGA256
VCCIO4 I/O POWER
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
IO1_8
IO1_9
IO1_10
IO1_11
IO1_12
IO1_13
IO1_14
BANK 4
EPM2210 FBGA256
IO4_15
IO4_16
IO4_17
IO4_18
LISO1 N7
I30 R6
I22M7
I32 T6
M5 TDO
P3 TCK
L6 TDI
N4 TMS
VCCIO1 I/O POWER
BANK 1
EPM2210 FBGA256
LAD9
LAD14
LAD11
LAD12
LAD13
LAD15
LPERR#
LPAR
LSERR#
LSTOP#
G15
G12
G16
H14
H15
LC/BE0#
I8
I6
T10
P9
IO1_32
IO1_31
IO1_30
IO1_29
K2
J3
K1
J4
M3
L5
M2
K3
M1
K4
L2
K5
L1
O3
O32
O11
O19
O10
O1
O30
O9
O31
O2
I15
I21
I16
I25
I14
I28
I19
I26
I17
I24
I20
T13
N11
R12
M11
T12
P10
R11
N10
T11
M10
R10
OUT
IO1_42
IO1_41
IO1_40
IO1_39
IO1_38
IO1_37
IO1_36
IO1_35
IO1_34
IO4_30
IO4_29
IO4_42
IO4_41
IO4_40
IO4_39
IO4_38
IO4_37
IO4_36
IO4_35
IO4_34
IO4_33
IO4_32
IN, SPI
IO3_33
IO3_32
IO3_31
IO3_30
IO3_29
IO3_42
IO3_41
IO3_40
IO3_39
IO3_38
IO3_37
IO3_36
IO3_35
F12
E15
F11
E16
G14
F15
G13
F16
PCI
14
17
18
21
22
LCLK
LREQ#
LAD31
LAD29
LAD27
14
17
18
21
22
LAD25
LC/BE3#
LAD23
LAD21
LAD19
14
17
18
21
22
LAD17
LC/BE2#
LIRDY#
LDEVSEL#
LPERR#
14
17
18
21
22
LSERR#
LC/BE1#
LAD14
LAD12
LAD10
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
24
15
16
19
20
23
2
5
6
9
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
P_AD25
P_C/BE3#
P_AD23
P_AD21
P_AD19
P_AD20
P_AD22
P_IDSEL#
P_AD24
P_AD26
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
24
P_AD17
15
16 P_C/BE2#
19 P_IRDY#
20 P_DEVSEL#
23 P_PERR#
P_STOP#
2
P_TRDY#
5
6 P_FRAME#
P_AD16
9
P_AD18
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
24
15
16
19
20
23
2
5
6
9
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
P_SERR#
P_C/BE1#
P_AD14
P_AD12
P_AD10
P_AD9
P_AD11
P_AD13
P_AD15
P_PAR
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
R4 10K
C15 10nF
C14
33uF10V
1
C13
1
2
33uF10V
2
PAGE
FILE:
1
P_AD8
P_AD7
P_AD5
P_AD3
P_AD1
P_AD0
P_AD2
P_AD4
P_AD6
P_C/BE0#
OF
2
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
P_AD1
P_AD5
P_AD3
P_AD8
P_AD7
+5V
DRAWN BY:
P_AD2
P_AD0
P_AD6
P_AD4
P_C/BE0#
P_AD9
P_AD13
P_AD11
P_PAR
P_AD15
P_STOP#
P_TRDY#
P_FRAME#
P_AD18
P_AD16
P_AD22
P_AD20
P_AD24
P_IDSEL#
P_AD28
P_AD26
P_AD30
P_GNT#
P_RST#
P_INTA#
+5V
+5V
Sergey Kubushyn <[email protected]>
1.0
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
+3.3V
C/BE0
+3.3V
AD6
AD4
GND
AD2
AD0
+V_IO
REQ64
+5V
+5V
5V Key
5V Key
AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+V_IO
ACK64
+5V
+5V
3.3V_AUX
RST
+V_IO
GNT
GND
PME
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME
GND
TRDY
GND
STOP
+3.3V
SDONE
SBO
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9
3.3V Key
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
RSVD1
+V_IO
RSVD3
RSVD4
GND
CLK
GND
REQ
+V_IO
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND
IRDY
+3.3V
DEVSEL
PCIXCAP
LOCK
PERR
+3.3V
SERR
+3.3V
C/BE1
AD14
GND
AD12
AD10
M66EN
3.3V Key
−12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
RSVD2
PRSNT2
P1 PCI Edge Connector
REVISION:
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B14
B15
B16
B17
P_REQ#
B18
B19
P_AD31
B20
P_AD29
B21
B22
P_AD27
B23
P_AD25
B24
B25
P_C/BE3# B26
P_AD23
B27
B28
P_AD21
B29
P_AD19
B30
B31
P_AD17
B32
P_C/BE2# B33
B34
P_IRDY#
B35
B36
P_DEVSEL# B37
B38
B39
P_PERR# B40
B41
P_SERR# B42
B43
P_C/BE1# B44
P_AD14
B45
B46
P_AD12
B47
P_AD10
B48
B49
P_CLK
+5V
PCI CNC Interface Board
CENTIPEDE−PCI
24
15
16
19
20
23
2
5
6
9
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
TITLE
1
13
14
17
18
21
22
3
4
7
8
11
U7 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
LAD9
LAD11
LAD13
LAD15
LPAR
PCIEN#
P_CLK
P_REQ#
P_AD31
P_AD29
P_AD27
P_AD28
P_AD30
P_GNT#
P_RST#
P_INTA#
U6 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
LSTOP#
LTRDY#
LFRAME#
LAD16
LAD18
LAD8
LAD7
LAD5
LAD3
LAD1
24
15
16
19
20
23
2
5
6
9
10
U5 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
LAD20
LAD22
LIDSEL#
LAD24
LAD26
LAD0
LAD2
LAD4
LAD6
LC/BE0#
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
U4 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
U3 SN74CBTD3384CDBQ
LAD28
LAD30
LGNT#
LRST#
LINTA#
COMPONENT
H12LDEVSEL#
J12 LIRDY#
IO_GCLK3
IO_GCLK2
IO3_15
IO3_16
IO3_17
IO3_18
IO3_19
IO3_20
IO3_21
L15
K14
L16
K13
K15
K12
K16
LIDSEL#
LAD21
LAD22
LAD23
LAD20
LC/BE2#
LAD18
TDO
TCK
TDI
TMS
IO1_15
IO1_16
IO1_17
IO1_18
IO1_19
IO1_20
IO1_21
IO1_22
R1 10K
2 GND
R2 10K
F6
O7 F1
O21G3
O14G2
O27G4
O6 G1
G5
O13H2
SOLDER
D13 LAD1
E14 LAD7
C14 LAD0
E13 LAD5
C15 LAD2
E12
D14 LAD3
F14 LAD10
D15 LAD4
F13 LAD8
D16 LAD6
IO3_53
IO3_52
IO3_51
IO3_50
IO3_49
IO3_48
IO3_47
IO3_46
IO3_45
IO3_44
IO3_43
IO3_23
IO3_24
IO3_25
IO3_26
IO3_27
IO3_28
J15
J14
J16
J13
H16
H13
LAD16
LAD17
LFRAME#
LAD19
LTRDY#
LC/BE1#
P13 I7
R16 I5
P12I12
T15 I3
N12I10
R14 I1
M12
R13 I2
P11I23
IO4_51
IO4_50
IO4_49
IO4_48
IO4_47
IO4_46
IO4_45
IO4_44
IO4_43
IO4_20
IO4_21
IO4_22
IO4_23
IO4_24
IO4_25
IO4_26
IO4_27
IO4_28
31
I29 R7
J5
LISO2 P8
H566MHZ
I31 T7
P2
LSS23N8
N3
I27 R8
M4
I4 N9
N2 O17
I13 T8
L3 O29
I11T9
N1 O18
I9 R9
L4
C9 10nF
IO_GCLK1
IO_GCLK0
IO1_49
IO1_48
IO1_47
IO1_46
IO1_45
IO1_44
IO1_43
C10 10nF
IO1_24
IO1_25
IO1_26
IO1_27
IO1_28
C11 0.1uF
O5 H1
O20H3
O12 J1
O28H4
O4 J2
C12 0.1uF
+3.3V
R6 10K
1
G
G
C17
33uF10V
2
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
IGND
2 NSS13+
3 NSS13−
6 NSS12+
5 NSS12−
10NSS22+
11NSS22−
14NSS23+
13NSS23−
R7 10K
51
52 OUT1
53 OUT2
54 OUT3
55 OUT4
56 OUT5
57 OUT6
58 OUT7
59 OUT8
60
61 OUT9
62 OUT10
63 OUT11
64 OUT12
65 OUT13
66 OUT14
67 OUT15
68 OUT16
69
70 OUT17
71 OUT18
72 OUT19
73 OUT20
74 OUT21
75 OUT22
76 OUT23
77 OUT24
78
79 OUT25
80 OUT26
81 OUT27
82 OUT28
83 OUT29
84 OUT30
85 OUT31
86 OUT32
IVCC
87
88 MISO2+
89 MISO2−
90 MOSI2+
91 MOSI2−
92 SPCK2+
93 SPCK2−
94 NSS21+
95 NSS21−
96 NSS22+
97 NSS22−
98 NSS23+
99 NSS23−
100 IGND
+5V
V+IN1
SN75ALS192D
1A
2A
3A
4A
RP1
330
32
RP2
330
U23 MOCD207M
1
8
2
7
3
6
4
5
IN8
IN4
5
R39
C_OUT[1:32], p.1
2
R10 10K
2
O7
R40
R38
4.7K
RP8
DRAWN BY:
REVISION:
R44
OF
PCI CNC Interface Board
O6
Q31
OUT6
O15
1.0
Q24
O16
Q32
OUT7
O8
IGND
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
OUT8
OUT16
OUT24
OUT25
IGND
0.1uF
2 NSS11+
3 NSS11−
6SPCK1+
5SPCK1−
10MOSI1+
11MOSI1−
14
13
Q1−Q32
FDV301N
Sergey Kubushyn <[email protected]>
R45
PAGE
O5
CENTIPEDE−PCI
O4
Q30
OUT5
R43
FILE:
TITLE
O3
R41
C_IN[1:32], p.1
I18
100
O2
100
6
100
O1
100
FOD053L
I20
R42
4
3
7
Q29
OUT4
100
IN18
8
I22
I24
Q28
OUT3
100
1
2
U31
5
6
7
Q27
OUT2
O14
100
I2
IN20
IN22
FOD053L
Q26
O13
Q23
O24
OUT15
100
IN2
I4
I6
I8
4
3
1
2
R30
IN6
U22 MOCD207M
1
8
2
7
3
6
4
5
IN24
R31
OUT1
R32
I9
Q25
R33
8
5
R34
U30
O12
R35
IN9
I11
O11
R36
MOCD207M
1
8
2
7
3
6 U21
4
5
O10
Q22
O23
OUT14
Q16
G
G
1A
2A
3A
4A
C27
U15
SN75ALS192D
4
12
1
7
9
15
O25
OUT23
R37
IN11
100
O9
100
I25
I27
100
6
7
100
IN13
FOD053L
Q21
100
4
3
8
Q20
100
IN25
1
2
U29
I29
Q19
O22
OUT13
Q15
100
I13
IN27
6
Q18
O21
OUT12
Q14
O26
OUT22
100
IN15
4.7K
RP4
I15
5
FOD053L
R22
U20
MOCD207M
1
8
2
7
3
6
4
5
+3.3V
4
3
RP6
330
IN29
R23
I1
4.7K
RP7
Q17
R24
IN1
I31
O20
R26
V+IN2
7
R25
OUT11
R27
1
2
O19
100
OUT10
O27
OUT21
R28
IN31
100
O18
100
OUT9
Q13
100
I3
100
O17
Q12
O28
OUT20
100
U28 8
+3.3V
Q11
O32
OUT19
100
IN3
V+IN4
Q10
O30
OUT18
R29
U19 MOCD207M
1
8
2
7
3
6
4
5
I5
I7
I17
O31
OUT17
100
IN5
U18 MOCD207M
1
8
2
7
3
6
4
5
IN17
I19
R14
IN7
I10
U27 MOCD207M
1
8
2
7
3
6
4
5
Q8
Q7
Q6
Q5
R15
IN19
OUT26
OUT27
OUT28
OUT32
R16
IN10
U17
4.7K
RP3
Q9
IGND
Q4
16
15
14
13
12
11
10
9
OUT30
Vcc2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
Q3
Vcc1
GND1
INA
INB
INC
NC
NC
GND1
IVcc
IGND
0.1uF
OUT31
1
2
LSS11 3
LPCK1 4
LOSI1 5
6
7
8
C26
Q2
R17
I12
100
O29
IGND
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
SN75ALS192D
G
G
1A
2A
3A
4A
0.1uF
OUT29
100
I21
Q1
IGND
4
12
1
7
9
15
C25
U14 ISO7230A
+3.3V
SPI[1:2], p.1
R18
IN21
16
15
14
13
12
11
10
9
2 NSS21+
3 NSS21−
6SPCK2+
5SPCK2−
10 MOSI2+
11 MOSI2−
14
13
IGND
0.1uF
R19
I14
I23
I26
I28
I30
I32
Vcc2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
U13
C24
100
U26 MOCD207M
1
8
2
7
3
6
4
5
U25 MOCD207M
1
8
2
7
3
6
4
5
U24
MOCD207M
1
8
2
7
3
6
4
5
Vcc1
GND1
INA
INB
INC
NC
NC
GND1
IVcc
IGND
0.1uF
100
IN23
IN26
IN28
IN30
IN32
MISO2−
+3.3V
120
MISO2+
1
2
LSS21 3
LPCK2 4
LOSI2 5
6
7
8
C23
100
I16
MISO1−
V+IN3
120
0.1uF
100
MOCD207M
1
8
2
7
3
6
4
5
IGND
IVCC
MISO1+
R47
IGND
C22
U12 ISO7230A
+3.3V
R20
IN12
16
8
13
11
5 IS2
3 IS1
R46
IVcc
16
15
14 SS13
13 SS12
12
IS1
11
10
9
100
IN14
+3.3V
VCC
GND
4Y
3Y
2Y
1Y
U16
MOCD207M
1
8
2
7
3
6
4
5
1A
1B
2A
2B
3A
3B
4A
4B
G
G
Vcc2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
ISO7231 U11
Vcc1
GND1
INA
INB
OUTC
NC
EN1
GND1
IVcc
+3.3V
1
2
LSS13 3
LSS12 4
LISO1 5
6
7
8
U10 SN75ALS193D
IGND
R9
10K
0.1uF
R21
IN16
C18
IGND
MISO1+ 2
MISO1− 1
MISO2+ 6
MISO2− 7
10
9
14
15
4
12
IVcc
16
15
14 SS22
13 SS23
12
IS2
11
10
9
C20 0.1uF
IGND
4
12
SS13 1
SS12 7
SS22 9
SS2315
U9
Vcc2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
C28 0.1uF
IVcc
ISO7231
Vcc1
GND1
INA
INB
OUTC
NC
EN1
GND1
RP5
330
V+IN1 1
IN1
2
IN2
3
IN3
4
IN4
5
IN5
6
IN6
7
IN7
8
IN8
9
V+IN2 10
IN9
11
IN10 12
IN11 13
IN12 14
IN13 15
IN14 16
IN15 17
IN16 18
V+IN3 19
IN17 20
IN18 21
IN19 22
IN20 23
IN21 24
IN22 25
IN23 26
IN24 27
V+IN4 28
IN25 29
IN26 30
IN27 31
IN28 32
IN29 33
IN30 34
IN31 35
IN32 36
IVCC 37
MISO1+ 38
MISO1− 39
MOSI1+ 40
MOSI1− 41
SPCK1+42
SPCK1−43
NSS11+44
NSS11−45
NSS12+46
NSS12−47
NSS13+48
NSS13−49
IGND 50
J3
IVcc
1
2
LSS22 3
LSS23 4
LISO2 5
6
7
8
U8
16
R8 10K
VCC
16
VCC
16
VCC
GND
C16 0.1uF
GND
C19 0.1uF
8
R11 10K
8
C21 0.1uF
GND
R12 10K
8
R13 10K
100
Chapter 5
Appendix C CENTIPEDE-PCI rev.1.1
Schematics
33
EX41
EX39
EX37
EX35
EX33
EX31
EX29
EX27
EX25
EX23
EX21
EX19
EX17
EX15
EX13
EX11
EX9
EX7
EX5
EX3
EX1
IO2_1
IO2_2
IO2_3
IO2_4
IO2_5
IO2_6
IO2_7
IO2_8
IO2_9
IO2_10
IO2_11
IO2_12
IO2_13
IO2_14
+3.3V
C13
PCIEN# B16
EX32
C12
EX40
A15
D12
EX41
B14
EX28
C11
EX38
B13
EX30
D11
EX39
A13
E11
EX36
B12
EX24
C10
EX37
A12
U1
+3.3V
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
+3.3V
+5V
10nF
0.1uF
10nF
0.1uF
10nF
0.1uF
10nF
0.1uF
C1
C2
C3
C4
C5
C6
C7
C8
VCCIO2 I/O POWER
+5V
BANK 2
EPM2210 FBGA256
IO2_15
IO2_16
IO2_17
IO2_18
EX26 D10
EX34 B11
E10
EX35 A11
J1 50
48
EX4046
EX3844
EX3642
EX3440
EX3238
EX3036
EX2834
EX2632
EX2430
EX2228
EX2026
EX1824
EX1622
EX1420
EX1218
EX1016
EX8 14
EX6 12
EX4 10
EX2 8
EX0 6
4
2
D4 EX0
B1 EX1
D5 EX4
A2 EX3
C5 EX6
B3 EX5
C6 EX10
C4 EX2
D6 EX8
B4 EX7
E6
+3.3V
C13
1
2
33uF10V
2
R3 10K
9
7
5
3
1
IO2_34
IO2_33
IO2_32
IO2_31
IO2_30
IO2_29
IO2_42
IO2_41
IO2_40
IO2_39
IO2_38
IO2_37
IO2_36
J2 JTAG
10
8
6
4
2
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
VCCIO1
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
A6
C8
B7
D8
A7
E8
A4
C7
B5
D7
A5
E7
B6
EX17
EX18
EX19
EX16
EX21
EX15
EX9
EX14
EX11
EX12
EX13
EXPANSION
H8
H10
J7
J9
F10
G11
K6
L7
L8
L9
T3
T14
C16
H11
J11
P16
A3
A14
F8
F9
C1
H6
J6
P1
U1
IO2_20
IO2_21
IO2_22
IO2_23
IO2_24
IO2_25
IO2_26
IO2_27
IO2_28
EX33 B10
EX20 C9
EX31 A10
EX22 D9
EX29 B9
E9
EX27 A9
EX25 A8
EX23 B8
H7
H9
J8
J10
F7
G6
K11
L10
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
TMS
TDO
TCK
TDI
LSS12
LOSI1
LSS13
LPCK1
I26
LSS11
LSS22
LOSI2
LSS21
LPCK2
U1
P4
R1
P5
T2
N5
R3
P6
R4
N6
T4
M6
R5
P7
T5
U1
P14
N13
P15
M14
N14
M13
N15
L14
N16
L13
M15
L12
M16
L11
O24 D3
C2
O23 E3
C3
O25 E4
D2
E5
D1
O22 F3
O16 E2
O26 F4
O8 E1
F5
O15 F2
LCLK
LREQ#
LGNT#
LAD27
LAD31
LAD29
LAD30
LC/BE3#
LAD28
LAD25
LAD26
LINTA#
LAD24
LRST#
U1
IO3_1
IO3_2
IO3_3
IO3_4
IO3_5
IO3_6
IO3_7
IO3_8
IO3_9
IO3_10
IO3_11
IO3_12
IO3_13
IO3_14
IO4_1
IO4_2
IO4_3
IO4_4
IO4_5
IO4_6
IO4_7
IO4_8
IO4_9
IO4_10
IO4_11
IO4_12
IO4_13
IO4_14
M9
M8
IO_DEV_CLRn
IO_DEV_OE
VCCIO3 I/O POWER
BANK 3
EPM2210 FBGA256
VCCIO4 I/O POWER
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
IO1_8
IO1_9
IO1_10
IO1_11
IO1_12
IO1_13
IO1_14
BANK 4
EPM2210 FBGA256
IO4_15
IO4_16
IO4_17
IO4_18
LISO1 N7
I23 R6
I27M7
I24 T6
M5 TDO
P3 TCK
L6 TDI
N4 TMS
VCCIO1 I/O POWER
BANK 1
EPM2210 FBGA256
LAD9
LAD14
LAD11
LAD12
LAD13
LAD15
LPERR#
LPAR
LSERR#
LSTOP#
G15
G12
G16
H14
H15
LC/BE0#
I8
I6
T10
P9
IO1_32
IO1_31
IO1_30
IO1_29
O10
O3
O32
O11
O19
M3
L5
M2
K3
M1
K4
L2
K5
L1
K2
J3
K1
J4
O1
O30
O9
O31
O2
I15
I18
I16
I29
I14
I22
I19
I21
I17
I28
I25
T13
N11
R12
M11
T12
P10
R11
N10
T11
M10
R10
OUT
IO1_42
IO1_41
IO1_40
IO1_39
IO1_38
IO1_37
IO1_36
IO1_35
IO1_34
IO4_30
IO4_29
IO4_42
IO4_41
IO4_40
IO4_39
IO4_38
IO4_37
IO4_36
IO4_35
IO4_34
IO4_33
IO4_32
IN, SPI
IO3_33
IO3_32
IO3_31
IO3_30
IO3_29
IO3_42
IO3_41
IO3_40
IO3_39
IO3_38
IO3_37
IO3_36
IO3_35
F12
E15
F11
E16
G14
F15
G13
F16
PCI
14
17
18
21
22
LCLK
LREQ#
LAD31
LAD29
LAD27
14
17
18
21
22
LAD25
LC/BE3#
LAD23
LAD21
LAD19
14
17
18
21
22
LAD17
LC/BE2#
LIRDY#
LDEVSEL#
LPERR#
14
17
18
21
22
LSERR#
LC/BE1#
LAD14
LAD12
LAD10
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
24
15
16
19
20
23
2
5
6
9
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
P_AD25
P_C/BE3#
P_AD23
P_AD21
P_AD19
P_AD20
P_AD22
P_IDSEL#
P_AD24
P_AD26
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
24
P_AD17
15
16 P_C/BE2#
19 P_IRDY#
20 P_DEVSEL#
23 P_PERR#
P_STOP#
2
P_TRDY#
5
6 P_FRAME#
P_AD16
9
P_AD18
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
24
15
16
19
20
23
2
5
6
9
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
P_SERR#
P_C/BE1#
P_AD14
P_AD12
P_AD10
P_AD9
P_AD11
P_AD13
P_AD15
P_PAR
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
PAGE
FILE:
1
P_AD8
P_AD7
P_AD5
P_AD3
P_AD1
P_AD0
P_AD2
P_AD4
P_AD6
P_C/BE0#
OF
2
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
P_AD1
P_AD5
P_AD3
P_AD8
P_AD7
+5V
DRAWN BY:
P_AD2
P_AD0
P_AD6
P_AD4
P_C/BE0#
P_AD9
P_AD13
P_AD11
P_PAR
P_AD15
P_STOP#
P_TRDY#
P_FRAME#
P_AD18
P_AD16
P_AD22
P_AD20
P_AD24
P_IDSEL#
P_AD28
P_AD26
P_AD30
P_GNT#
P_RST#
P_INTA#
+5V
+5V
Sergey Kubushyn <[email protected]>
1.1
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
+3.3V
C/BE0
+3.3V
AD6
AD4
GND
AD2
AD0
+V_IO
REQ64
+5V
+5V
5V Key
5V Key
AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+V_IO
ACK64
+5V
+5V
3.3V_AUX
RST
+V_IO
GNT
GND
PME
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME
GND
TRDY
GND
STOP
+3.3V
SDONE
SBO
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9
3.3V Key
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
RSVD1
+V_IO
RSVD3
RSVD4
GND
CLK
GND
REQ
+V_IO
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND
IRDY
+3.3V
DEVSEL
PCIXCAP
LOCK
PERR
+3.3V
SERR
+3.3V
C/BE1
AD14
GND
AD12
AD10
M66EN
3.3V Key
−12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
RSVD2
PRSNT2
P1 PCI Edge Connector
REVISION:
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B14
B15
B16
B17
P_REQ#
B18
B19
P_AD31
B20
P_AD29
B21
B22
P_AD27
B23
P_AD25
B24
B25
P_C/BE3# B26
P_AD23
B27
B28
P_AD21
B29
P_AD19
B30
B31
P_AD17
B32
P_C/BE2# B33
B34
P_IRDY#
B35
B36
P_DEVSEL# B37
B38
B39
P_PERR# B40
B41
P_SERR# B42
B43
P_C/BE1# B44
P_AD14
B45
B46
P_AD12
B47
P_AD10
B48
B49
P_CLK
+5V
PCI CNC Interface Board
CENTIPEDE−PCI
24
15
16
19
20
23
2
5
6
9
10
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
TITLE
1
13
14
17
18
21
22
3
4
7
8
11
U7 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
LAD9
LAD11
LAD13
LAD15
LPAR
PCIEN#
P_CLK
P_REQ#
P_AD31
P_AD29
P_AD27
P_AD28
P_AD30
P_GNT#
P_RST#
P_INTA#
U6 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
LSTOP#
LTRDY#
LFRAME#
LAD16
LAD18
LAD8
LAD7
LAD5
LAD3
LAD1
24
15
16
19
20
23
2
5
6
9
10
U5 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
LAD20
LAD22
LIDSEL#
LAD24
LAD26
LAD0
LAD2
LAD4
LAD6
LC/BE0#
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
1OE VCC
12
2OE GND
2A1
2A2
2A3
2A4
2A5
1A1
1A2
1A3
1A4
1A5
U4 SN74CBTD3384CDBQ
1
13
3
4
7
8
11
U3 SN74CBTD3384CDBQ
LAD28
LAD30
LGNT#
LRST#
LINTA#
COMPONENT
H12LDEVSEL#
J12 LIRDY#
IO_GCLK3
IO_GCLK2
IO3_15
IO3_16
IO3_17
IO3_18
IO3_19
IO3_20
IO3_21
L15
K14
L16
K13
K15
K12
K16
LIDSEL#
LAD21
LAD22
LAD23
LAD20
LC/BE2#
LAD18
TDO
TCK
TDI
TMS
IO2_53
IO2_52
IO2_51
IO2_50
IO2_49
IO2_48
IO2_47
IO2_46
IO2_45
IO2_44
IO2_43
1
IO1_15
IO1_16
IO1_17
IO1_18
IO1_19
IO1_20
IO1_21
IO1_22
C14
33uF10V
F6
O7 F1
O21G3
O14G2
O27G4
O6 G1
G5
O13H2
SOLDER
D13 LAD1
E14 LAD7
C14 LAD0
E13 LAD5
C15 LAD2
E12
D14 LAD3
F14 LAD10
D15 LAD4
F13 LAD8
D16 LAD6
IO3_53
IO3_52
IO3_51
IO3_50
IO3_49
IO3_48
IO3_47
IO3_46
IO3_45
IO3_44
IO3_43
IO3_23
IO3_24
IO3_25
IO3_26
IO3_27
IO3_28
J15
J14
J16
J13
H16
H13
LAD16
LAD17
LFRAME#
LAD19
LTRDY#
LC/BE1#
P13 I7
R16 I5
P12I12
T15 I3
N12I10
R14 I1
M12
R13 I2
P11I20
IO4_51
IO4_50
IO4_49
IO4_48
IO4_47
IO4_46
IO4_45
IO4_44
IO4_43
IO4_20
IO4_21
IO4_22
IO4_23
IO4_24
IO4_25
IO4_26
IO4_27
IO4_28
34
I31 R7
J5
LISO2 P8
H5
I32 T7
P2
LSS23N8
N3
I30 R8
M4
I4 N9
N2 O17
I13 T8
L3 O29
I11T9
N1 O18
I9 R9
L4
C9 10nF
IO_GCLK1
IO_GCLK0
IO1_49
IO1_48
IO1_47
IO1_46
IO1_45
IO1_44
IO1_43
C11 0.1uF
IO1_24
IO1_25
IO1_26
IO1_27
IO1_28
C10 10nF
R1 10K
O5 H1
O20H3
O12 J1
O28H4
O4 J2
C12 0.1uF
R2 10K
+3.3V
R6 10K
1
G
G
C17
33uF10V
2
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
IGND
2 NSS13+
3 NSS13−
6 NSS12+
5 NSS12−
10NSS22+
11NSS22−
14NSS23+
13NSS23−
R7 10K
51
52 OUT1
53 OUT2
54 OUT3
55 OUT4
56 OUT5
57 OUT6
58 OUT7
59 OUT8
60
61 OUT9
62 OUT10
63 OUT11
64 OUT12
65 OUT13
66 OUT14
67 OUT15
68 OUT16
69
70 OUT17
71 OUT18
72 OUT19
73 OUT20
74 OUT21
75 OUT22
76 OUT23
77 OUT24
78
79 OUT25
80 OUT26
81 OUT27
82 OUT28
83 OUT29
84 OUT30
85 OUT31
86 OUT32
IVCC
87
88 MISO2+
89 MISO2−
90 MOSI2+
91 MOSI2−
92 SPCK2+
93 SPCK2−
94 NSS21+
95 NSS21−
96 NSS22+
97 NSS22−
98 NSS23+
99 NSS23−
100 IGND
+5V
V+IN1
SN75ALS192D
1A
2A
3A
4A
RP1
330
35
RP2
330
U23 MOCD207M
1
8
2
7
3
6
4
5
IN8
IN4
5
R39
C_OUT[1:32], p.1
2
R10 10K
2
O7
R40
R38
2.2K
RP8
DRAWN BY:
REVISION:
R44
OF
PCI CNC Interface Board
O6
Q31
OUT6
O15
1.1
Q24
O16
Q32
OUT7
O8
IGND
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
OUT8
OUT16
OUT24
OUT25
IGND
0.1uF
2 NSS11+
3 NSS11−
6SPCK1+
5SPCK1−
10MOSI1+
11MOSI1−
14
13
Q1−Q32
FDV301N
Sergey Kubushyn <[email protected]>
R45
PAGE
O5
CENTIPEDE−PCI
O4
Q30
OUT5
R43
FILE:
TITLE
O3
R41
C_IN[1:32], p.1
I26
100
O2
100
6
100
O1
100
FOD053L
I25
R42
4
3
7
Q29
OUT4
100
IN26
8
I27
I28
Q28
OUT3
100
1
2
U31
5
6
7
Q27
OUT2
O14
100
I2
IN25
IN27
FOD053L
Q26
O13
Q23
O24
OUT15
100
IN2
I4
I6
I8
4
3
1
2
R30
IN6
U22 MOCD207M
1
8
2
7
3
6
4
5
IN28
R31
OUT1
R32
I9
Q25
R33
8
5
R34
U30
O12
R35
IN9
I11
O11
R36
MOCD207M
1
8
2
7
3
6 U21
4
5
O10
Q22
O23
OUT14
Q16
G
G
1A
2A
3A
4A
C27
U15
SN75ALS192D
4
12
1
7
9
15
O25
OUT23
R37
IN11
100
O9
100
I29
I30
100
6
7
100
IN13
FOD053L
Q21
100
4
3
8
Q20
100
IN29
1
2
U29
I31
Q19
O22
OUT13
Q15
100
I13
IN30
6
Q18
O21
OUT12
Q14
O26
OUT22
100
IN15
2.2K
RP4
I15
5
FOD053L
R22
U20
MOCD207M
1
8
2
7
3
6
4
5
+3.3V
4
3
RP6
330
IN31
R23
I1
2.2K
RP7
Q17
R24
IN1
I32
O20
R26
V+IN2
7
R25
OUT11
R27
1
2
O19
100
OUT10
O27
OUT21
R28
IN32
100
O18
100
OUT9
Q13
100
I3
100
O17
Q12
O28
OUT20
100
U28 8
+3.3V
Q11
O32
OUT19
100
IN3
V+IN4
Q10
O30
OUT18
R29
U19 MOCD207M
1
8
2
7
3
6
4
5
I5
I7
I17
O31
OUT17
100
IN5
U18 MOCD207M
1
8
2
7
3
6
4
5
IN17
I19
R14
IN7
I10
U27 MOCD207M
1
8
2
7
3
6
4
5
Q8
Q7
Q6
Q5
R15
IN19
OUT26
OUT27
OUT28
OUT32
R16
IN10
U17
2.2K
RP3
Q9
IGND
Q4
16
15
14
13
12
11
10
9
OUT30
Vcc2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
Q3
Vcc1
GND1
INA
INB
INC
NC
NC
GND1
IVcc
IGND
0.1uF
OUT31
1
2
LSS11 3
LPCK1 4
LOSI1 5
6
7
8
C26
Q2
R17
I12
100
O29
IGND
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
SN75ALS192D
G
G
1A
2A
3A
4A
0.1uF
OUT29
100
I18
Q1
IGND
4
12
1
7
9
15
C25
U14 ISO7230A
+3.3V
SPI[1:2], p.1
R18
IN18
16
15
14
13
12
11
10
9
2 NSS21+
3 NSS21−
6SPCK2+
5SPCK2−
10 MOSI2+
11 MOSI2−
14
13
IGND
0.1uF
R19
I14
I20
I21
I22
I23
I24
Vcc2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
U13
C24
100
U26 MOCD207M
1
8
2
7
3
6
4
5
U25 MOCD207M
1
8
2
7
3
6
4
5
U24
MOCD207M
1
8
2
7
3
6
4
5
Vcc1
GND1
INA
INB
INC
NC
NC
GND1
IVcc
IGND
0.1uF
100
IN20
IN21
IN22
IN23
IN24
MISO2−
+3.3V
120
MISO2+
1
2
LSS21 3
LPCK2 4
LOSI2 5
6
7
8
C23
100
I16
MISO1−
V+IN3
120
0.1uF
100
MOCD207M
1
8
2
7
3
6
4
5
IGND
IVCC
MISO1+
R47
IGND
C22
U12 ISO7230A
+3.3V
R20
IN12
16
8
13
11
5 IS2
3 IS1
R46
IVcc
16
15
14 SS13
13 SS12
12
IS1
11
10
9
100
IN14
+3.3V
VCC
GND
4Y
3Y
2Y
1Y
U16
MOCD207M
1
8
2
7
3
6
4
5
1A
1B
2A
2B
3A
3B
4A
4B
G
G
Vcc2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
ISO7231 U11
Vcc1
GND1
INA
INB
OUTC
NC
EN1
GND1
IVcc
+3.3V
1
2
LSS13 3
LSS12 4
LISO1 5
6
7
8
U10 SN75ALS193D
IGND
R9
10K
0.1uF
R21
IN16
C18
IGND
MISO1+ 2
MISO1− 1
MISO2+ 6
MISO2− 7
10
9
14
15
4
12
IVcc
16
15
14 SS22
13 SS23
12
IS2
11
10
9
C20 0.1uF
IGND
4
12
SS13 1
SS12 7
SS22 9
SS2315
U9
Vcc2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
C28 0.1uF
IVcc
ISO7231
Vcc1
GND1
INA
INB
OUTC
NC
EN1
GND1
RP5
330
V+IN1 1
IN1
2
IN2
3
IN3
4
IN4
5
IN5
6
IN6
7
IN7
8
IN8
9
V+IN2 10
IN9
11
IN10 12
IN11 13
IN12 14
IN13 15
IN14 16
IN15 17
IN16 18
V+IN3 19
IN17 20
IN18 21
IN19 22
IN20 23
IN21 24
IN22 25
IN23 26
IN24 27
V+IN4 28
IN25 29
IN26 30
IN27 31
IN28 32
IN29 33
IN30 34
IN31 35
IN32 36
IVCC 37
MISO1+ 38
MISO1− 39
MOSI1+ 40
MOSI1− 41
SPCK1+42
SPCK1−43
NSS11+44
NSS11−45
NSS12+46
NSS12−47
NSS13+48
NSS13−49
IGND 50
J3
IVcc
1
2
LSS22 3
LSS23 4
LISO2 5
6
7
8
U8
16
R8 10K
VCC
16
VCC
16
VCC
GND
C16 0.1uF
GND
C19 0.1uF
8
R11 10K
8
C21 0.1uF
GND
R12 10K
8
R13 10K
100
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement