AN133 VTOS DDR i.MX6 Addendum
AN133 – VTOS DDR: i.MX6 Processor Addendum
Application Note 133
VTOS DDR: i.MX6 Processor Addendum
April 17, 2015
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Table of Contents
Overview ....................................................................................................................................................................3
Supported Processors..............................................................................................................................................3
Loading the VTOS DDR image onto your board .......................................................................................................3
VTOS DDR Firmware Files ...................................................................................................................................3
Using Serial Downloader to load VTOS DDR Firmware ......................................................................................4
Requirements for using the Serial Downloader ..................................................................................................4
Installing the i.MX6 Manufacturing Tool ..........................................................................................................4
Loading the VTOS DDR Firmware image .........................................................................................................5
Using a JTAG debugger to load ELF and SREC images .......................................................................................8
Using a JTAG debugger to load binary images ......................................................................................................9
DDR Board Files ........................................................................................................................................................9
Timing Based Files .................................................................................................................................................9
Register Based Files .............................................................................................................................................12
DDR3 PHY Calibration............................................................................................................................................16
Empirical Software Calibration ............................................................................................................................16
Running the Empirical Software Calibration ...................................................................................................16
Command Summary .........................................................................................................................................19
Automatic Hardware Calibration..........................................................................................................................20
Manually Starting Hardware Calibration .........................................................................................................21
Additional Contact Information ...............................................................................................................................22
About Kozio, Inc. .....................................................................................................................................................22
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Overview
This addendum describes the VTOS DDR features specific to the i.MX6 processor family, manufactured by
Freescale.
Supported Processors
The VTOS DDR package for the i.MX6 processor family supports the following processor types:
●
i.MX6Dual (i.MX6D)
●
i.MX6Quad (i.MX6Q)
The following processor types are not supported at this time:
●
i.MX6 Solo (i.MX6S)
●
i.MX6 SoloLite (i.MX6SL)
●
i.MX6 DualLite (i.MX6DL)
Loading the VTOS DDR image onto your board
The VTOS DDR image is configured to run directly from the on-chip memory of the i.MX6. The default interface
used for communication is through UART1 on the i.MX6.
VTOS DDR Image Information: i.MX6
Load Address
Entry Point (ARM mode)
Entry Point (THUMB mode)
0x00907000
0x00907000
Specified by the ELF image file
VTOS DDR Firmware Files
The VTOS DDR installer provides the following files under %KOZIO_VTOS_DDR_HOME% directory for the i.MX6
processor family. You can quickly traverse to this folder by using the Windows File Explorer and entering
%KOZIO_VTOS_DDR_HOME% as the new location.
Select the appropriate VTOS DDR firmware image based on the pins used for the UART1 connection on you
board. The pins below apply to the i.MX6Dual and i.MX6Quad processor only.
Filename
UART1 pins E13 and F13
vtos.imx6_ddr.uart1_e13_f13.bin
vtos.imx6_ddr.uart1_e13_f13.elf
vtos.imx6_ddr.uart1_e13_f13.srec
UART1 pins M3 and M1
vtos.imx6_ddr.uart1_m3_m1.bin
vtos.imx6_ddr.uart1_m3_m1.elf
vtos.imx6_ddr.uart1_m3_m1.srec
© Copyright Kozio, Inc. 2014
Description
VTOS DDR Firmware image for boards using pin E13 for
UART1_RXD and pin F13 for UART1_TXD, raw binary format.
VTOS DDR Firmware image for boards using pin E13 for
UART1_RXD and pin F13 for UART1_TXD, ELF object file format.
VTOS DDR Firmware image for boards using pin E13 for
UART1_RXD and pin F13 for UART1_TXD, SREC file format.
VTOS DDR Firmware image for boards using pin M3 for
UART1_RXD and pin M1 for UART1_TXD, raw binary format.
VTOS DDR Firmware image for boards using pin M3 for
UART1_RXD and pin M1 for UART1_TXD, ELF object file format.
VTOS DDR Firmware image for boards using pin M3 for
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Common Files
vtos.imx6_ddr.elf
UART2 pins R5 and E24
vtos.imx6_ddr.uart2_r5_e24.bin
vtos.imx6_ddr. uart2_r5_e24.elf
vtos.imx6_ddr. uart2_r5_e24.srec
UART4 pins V6 and W5
vtos.imx6_ddr.uart4_v6_w5.bin
vtos.imx6_ddr. uart4_v6_w5.elf
vtos.imx6_ddr. uart4_v6_w5.srec
Common Files
vtos.imx6_ddr.elf
UART1_RXD and pin M1 for UART1_TXD, SREC file format.
VTOS DDR Firmware image loaded by the VTOS DDR application.
The VTOS DDR application always uses this file, regardless of the
UART pin configuration used on your board.
VTOS DDR Firmware image for boards using pin R5 for
UART2_RXD and pin E24 for UART2_TXD, raw binary format.
VTOS DDR Firmware image for boards using pin R5 for
UART2_RXD and pin E24 for UART2_TXD, ELF object file format.
VTOS DDR Firmware image for boards using pin R5 for
UART2_RXD and pin E24 for UART2_TXD, SREC file format.
VTOS DDR Firmware image for boards using pin V6 for
UART4_RXD and pin W5 for UART2_TXD, raw binary format.
VTOS DDR Firmware image for boards using pin V6 for
UART4_RXD and pin W5 for UART2_TXD, ELF object file format.
VTOS DDR Firmware image for boards using pin V6 for
UART4_RXD and pin W5 for UART2_TXD, SREC file format.
VTOS DDR Firmware image loaded by the VTOS DDR application.
The VTOS DDR application always uses this file, regardless of the
UART pin configuration used on your board.
Using Serial Downloader to load VTOS DDR Firmware
The ROM code for the i.MX6 includes a Serial Downloader which provides a mechanism for downloading a
firmware image directly into the on-chip RAM over a USB connection.
Requirements for using the Serial Downloader
●
●
●
USB OTG1 port is connected on your platform.
BOOT_MODE[1:0] pins are set to 01b on your platform: enabling the Serial Downloader.
Windows host PC to run the i.MX6 manufacturing tool
Installing the i.MX6 Manufacturing Tool
1. Download the i.MX6 Dual/Quad manufacturing tool from the Freescale website: IMX_6DQ_MFG_TOOL.
At the time of writing, the latest version of this tool is 4.1.0: Mfgtools-Rel4.1.0_130816_MX6Q_UPDATER.gz
2. Unpack the i.MX6 Manufacturing Tool. The open source utility 7-zip (http://www.7-zip.org/) is a good
option for unpacking the manufacturing tool.
3. You can unpack the iMX6 Manufacturing Tool anywhere that is convenient on your system. In this
document, the tool was installed to C:\Users\<username>\Mfgtools-Rel-4.1.0_130816_MX6Q_UPDATER
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Loading the VTOS DDR Firmware image
1. Open up the Windows Device Manager. Expand the Human Interface Devices section and note the
number of “USB Input Device” listed. In the example below, there are two (2) USB Input Devices.
2. Connect a USB cable between your Windows host and the USB OTG1 connection on your board.
3. Power up your board (ensure that that the BOOT_MODE[1:0] pins are set to 01b. If the board is
configured correctly and the USB OTG1 port is functional, then a new “USB Input Device” is displayed in
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
the Windows Device Manager. In the example below, there are now three (3) USB Input Devices.
4. Connect a serial cable between UART1 on your board and the Windows host. Launch the VTOS DDR
application and configure the COM port connected to your board.
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
5. Open the Windows command shell and execute these commands:
cd Mfgtools-Rel-4.1.0_130816_MX6Q_UPDATER
cd Utils\sb_loader
6. Use the utility sb_loader to transfer VTOS DDR firmware binary and start it executing. Note that you
must select the VTOS DDR firmware binary that matches the UART1 pin configuration of your board.
sb_loader -trans 0x907000 -f %KOZIO_VTOS_DDR_HOME%\vtos.imx6_ddr.uart1_e13_f13.bin
sb_loader –exec 0x907000
7. The output from the “sb_loader” utility confirms that transfer and execution of the VTOS DDR firmware
binary was successful.
8. Check the VTOS DDR application window, if the COM port settings are correct, then the VTOS DDR
application window will display “DUT Ready” as shown below.
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Using a JTAG debugger to load ELF and SREC images
The instruction below assume that you are starting with a board that does not have any boot media
programmed (such as NOR Flash, NAND flash, SD Card, eMMC, etc).
1.
2.
3.
4.
Connect the JTAG debugger to your board
Power up the JTAG debugger
Power up your board
Using the JTAG vendor supplied interface, issue a CPU reset to the i.MX6 core and allow the i.MX6 ROM
code to execute.
5. Halt the i.MX6 processor.
a. Confirm that the processor program counter register (labelled as PC, or R15) points to the I.MX6
ROM code area: 0x00000 – 0x17FFF.
b. Confirm that the processor execution state is THUMB mode. THUMB mode operation is
indicated by CPSR (Current Processor State Register) bit number 5. If bit 5 is set, the execution
state is THUMB mode. If bit 5 is clear, the execution state is ARM mode.
6. Load the VTOS DDR ELF or SREC file using the JTAG vendor supplied interface. ELF and SREC files contain
both the load address information, and the entry point location. Note that you must select the
ELF/SREC file that matches the pin configuration of UART1 for your board.
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
a. After loading the ELF/SREC file, confirm that the processor program counter has been changed
to the THUMB mode entry point. This must be an address in the range 0x00907000 –
0x00937FFF.
7. Resume operation of the i.MX6 processor. The VTOS DDR application will display “DUT Ready” when
the VTOS DDR firmware image boots.
Using a JTAG debugger to load binary images
1.
2.
3.
4.
Connect the JTAG debugger to your board
Power up the JTAG debugger
Power up your board
Using the JTAG vendor supplied interface, issue a CPU reset to the i.MX6 core and allow the i.MX6 ROM
code to execute.
5. Halt the i.MX6 processor.
a. Confirm that the processor program counter register (labelled as PC, or R15) points to the i.MX6
ROM code area: 0x00000 – 0x17FFF.
6. Load the VTOS DDR binary file using the JTAG vendor supplied interface. The load address for the file is
0x00907000.
a. After loading the file, modify the processor state to set ARM execution mode. Set the CPSR
register to the value 0x00000193.
b. Modify the program counter to point to the ARM execution mode entry point. Set the PC
register to the value 0x00907000.
8. Resume operation of the i.MX6 processor. The VTOS DDR application will display “DUT Ready” when
the VTOS DDR firmware image boots.
DDR Board Files
Please see the VTOS DDR User manual for a detailed description on how to create and use board files. This
document details the parameters that are specific to the i.MX6 processor family.
Timing Based Files
Use a Timing Based DDR board file to have VTOS DDR automatically calculate the register settings for the MMDC
(Multi Mode DDR Controller). Register settings are based on the memory part file selected and the desired
speed of the DDR clock.
In your Timing Mode board file, you must provide the following items:
●
Select a memory part script file
●
Specify the DDR clock frequency
●
Specify the number of chip selects used
●
Specify the number of memory chips connected to each chip select
●
Specify the on-die termination value
●
Specify additional read and write latency
●
Specify the PHY calibration information. The PHY calibration information can be entered manually, or
you can have the VTOS DDR run the automatic hardware calibration to determine optimum calibration
values for you.
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Parameter
Description
$ddr.frequency
Specifies the frequency of the DDR clock, in Hertz. For
i.MX6 designs, this value should be typically set to 528
MHz. Note that the data transfer rate of the interface
is twice this frequency because data is clocked on both
edges of the DDR clock. For example DDR3-800
memories, run the DDR clock at 400 MHz.
$ddr.chips_per_chip_select
Specifies the number of memory chips connected to
each chip select. Set to 1 when using 16-bit wide
memory chips. Set to 2 when using 8-bit wide
memory chips.
$ddr.num_chip_selects
Specifies the number of DDR memory controller chip
selects used on the board. The i.MX6 processor
supports 1 or 2 chip selects. This parameter is also
referred to as the number of physical ranks of
memory.
$ddr.memctrl.odt
Specifies the desired on-die termination value, in
ohms. For DDR3 memories, valid settings are 20, 30,
40, 60, and 120.
$ddr.memctrl.trpa
Specifies the setting for the MDCFG1[tRPA] field. Valid
settings are 0 and 1. The recommended value of 1
forces the memory controller to delay one additional
cycle after issuing a precharge-all command.
$ddr.memctrl.walat
This parameter specifies the additional delay, in cycles,
for writes. This setting is applied to the
MMDCx_MDMISC[WALAT] field. Valid settings are 0 to
3 cycles. Recommended default value is 0 cycles.
$ddr.memctrl.ralat
This parameter specifies the additional delay, in cycles,
for reads. This setting is applied to the
MMDCx_MDMISC[RALAT] field. Valid settings are 0 to
7 cycles. Recommended default value is 4 cycles.
$ddr.memctrl.fixed_calibration
Specifies whether the PHY is configured using
fixed/hardcoded settings or if automatic hardware
calibration is performed.
Set to FALSE to use automatic hardware calibration.
Set to TRUE to used fixed calibration values.
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
It is recommended to set this to FALSE when first
testing DDR on a new platform. Once stable PHY
calibration settings are known, set to TRUE.
$mmdc_mpwldectrl0
Specifies the value written to the
MMDC1_MPWLDECTRL0 register. This value is only
used if fixed PHY calibration is enabled.
$mmdc_mpwldectrl1
Specifies the value written to the
MMDC1_MPWLDECTRL1 register. This value is only
used if fixed PHY calibration is enabled.
$mmdc_mpdgctrl0
Specifies the value written to the
MMDC1_MPDGCTRL0 register. This value is only used
if fixed PHY calibration is enabled.
$mmdc_mpdgctrl1
Specifies the value written to the
MMDC1_MPDGCTRL1 register. This value is only used
if fixed PHY calibration is enabled.
$mmdc_mprddlctl
Specifies the value written to the
MMDC1_MPRDDLHWCTL register. This value is only
used if fixed PHY calibration is enabled.
$mmdc_mpwrdlctl
Specifies the value written to the
MMDC1_MPWRDLHWCTL register. This value is only
used if fixed PHY calibration is enabled.
$mmdc2_mpwldectrl0
Specifies the value written to the
MMDC2_MPWLDECTRL0 register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mpwldectrl1
Specifies the value written to the
MMDC2_MPWLDECTRL1 register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mpdgctrl0
Specifies the value written to the
MMDC2_MPDGCTRL0 register. This value is only used
for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mpdgctrl1
Specifies the value written to the
MMDC2_MPDGCTRL1 register. This value is only used
for designs with a 64-bit data bus and if fixed PHY
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
calibration is enabled.
$mmdc2_mprddlctl
Specifies the value written to the
MMDC2_MPRDDLHWCTL register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mpwrdlctl
Specifies the value written to the
MMDC2_MPWRDLHWCTL register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
Example i.MX6 board timing based parameters are shown below.
// filetype=ddr-board_timing-based version=1 architecture=imx6_ddr
include scripts/Kozio/imx6_ddr.ksc
include memory_parts/micron/micron_ddr3_MT41J128M16-15E.ksc
528 MHz -> $ddr.frequency // DDR Frequency
1 -> $ddr.num_chip_selects // Number of chip selects
4 -> $ddr.chips_per_chip_select // DDR chips per chip select
60 -> $ddr.memctrl.odt // On-Die Termination
1 -> $ddr.memctrl.trpa // Precharge-all extra cycle
0 -> $ddr.memctrl.walat // Write Additional Latency
4 -> $ddr.memctrl.ralat // Read Additional Latency
TRUE -> $ddr.memctrl.fixed_calibration
0x000B0009 -> $mmdc_mpwldectrl0
0x00170012 -> $mmdc_mpwldectrl1
0x4309031B -> $mmdc_mpdgctrl0
0x030B0301 -> $mmdc_mpdgctrl1
0x473C3B3E -> $mmdc_mprddlctl
0x39444741 -> $mmdc_mpwrdlctl
0x0007001B -> $mmdc2_mpwldectrl0
0x00040018 -> $mmdc2_mpwldectrl1
0x03070321 -> $mmdc2_mpdgctrl0
0x030F025A -> $mmdc2_mpdgctrl1
0x3D3B3648 -> $mmdc2_mprddlctl
0x493D4D3C -> $mmdc2_mpwrdlctl
ddr.timing.convert
Note that the DDR clock frequency can be specified in a number of formats. The following lines all set the DDR
clock frequency to 400 MHz.
400 MHz -> $ddr.frequency
400000 KHz -> $ddr.frequency
400000000 -> $ddr.frequency
Register Based Files
Use a Register Based DDR board file if you want to explicitly specify all register values programmed into the
MMDC (Multi Mode DDR Controller).
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
The table below lists all parameters required on the Freescale i.MX6 processor.
Parameter
Description
$ddr.memctrl.fixed_calibration
Specifies whether the PHY is configured using
fixed/hardcoded settings or if automatic hardware
calibration is performed.
Set to FALSE to use automatic hardware calibration
(recommended setting).
Set to TRUE to used fixed calibration values.
$mmdc_mdctl
Specifies the value written to the MMDCx_MDCTL
register.
$mmdc_mdpdc
Specifies the value written to the MMDC1_MDPDC
register.
$mmdc_mdotc
Specifies the value written to the MMDC1_MDOTC
register.
$mmdc_mdcfg0
Specifies the value written to the MMDC1_CFG0
register.
$mmdc_mdcfg1
Specifies the value written to the MMDC1_CFG1
register.
$mmdc_mdcfg2
Specifies the value written to the MMDC1_CFG2
register.
$mmdc_mdmisc
Specifies the value written to the MMDC1_MDMISC
register.
$mmdc_mdscr
Specifies the value written to the MMDC1_MDSCR
register.
$mmdc_mdref
Specifies the value written to the MMDC1_MDREF
register.
$mmdc_mdor
Specifies the value written to the MMDC1_MDOR
register.
$mmdc_mapsr
Specifies the value written to the MMDC1_MAPSR
register.
$mmdc_mpzqhwctrl
Specifies the value written to the
MMDC1_MPZQHWCTRL register.
$mmdc_mpwldectrl0
© Copyright Kozio, Inc. 2014
Specifies the value written to the
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AN133 – VTOS DDR: i.MX6 Processor Addendum
MMDC1_MPWLDECTRL0 register. This value is only
used if fixed PHY calibration is enabled.
$mmdc_mpwldectrl1
Specifies the value written to the
MMDC1_MPWLDECTRL1 register. This value is only
used if fixed PHY calibration is enabled.
$mmdc_mpdgctrl0
Specifies the value written to the
MMDC1_MPDGCTRL0 register. This value is only used
if fixed PHY calibration is enabled.
$mmdc_mpdgctrl1
Specifies the value written to the
MMDC1_MPDGCTRL1 register. This value is only used
if fixed PHY calibration is enabled.
$mmdc_mprddlctl
Specifies the value written to the
MMDC1_MPRDDLHWCTL register. This value is only
used if fixed PHY calibration is enabled.
$mmdc_mpwrdlctl
Specifies the value written to the
MMDC1_MPWRDLHWCTL register. This value is only
used if fixed PHY calibration is enabled.
$mmdc2_mpwldectrl0
Specifies the value written to the
MMDC2_MPWLDECTRL0 register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mpwldectrl1
Specifies the value written to the
MMDC2_MPWLDECTRL1 register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mpdgctrl0
Specifies the value written to the
MMDC2_MPDGCTRL0 register. This value is only used
for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mpdgctrl1
Specifies the value written to the
MMDC2_MPDGCTRL1 register. This value is only used
for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
$mmdc2_mprddlctl
Specifies the value written to the
MMDC2_MPRDDLHWCTL register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
calibration is enabled.
$mmdc2_mpwrdlctl
Specifies the value written to the
MMDC2_MPWRDLHWCTL register. This value is only
used for designs with a 64-bit data bus and if fixed PHY
calibration is enabled.
Example i.MX6 board register based settings are shown below.
// filetype=ddr-board_timing-based version=1 architecture=imx6_ddr
include scripts/kozio/imx6_ddr.ksc
TRUE -> $ddr.memctrl.fixed_calibration
0x831A0000
0x00020036
0x09444040
0x545978F4
0xFF538F64
0x01FF00DB
0x40001700
0x00000000
0x10168000
0x00591023
0x00000067
0xA13839C3
0x000B0009
0x00170012
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x4309031B
0x030B0301
0x473C3B3E
0x39444741
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
$mmdc_mdctl
$mmdc_mdpdc
$mmdc_mdotc
$mmdc_mdcfg0
$mmdc_mdcfg1
$mmdc_mdcfg2
$mmdc_mdmisc
$mmdc_mdscr
$mmdc_mdref
$mmdc_mdor
$mmdc_mapsr
$mmdc_mpzqhwctrl
$mmdc_mpwldectrl0
$mmdc_mpwldectrl1
$mmdc_mpodtctrl
$mmdc_mprddqby0dl
$mmdc_mprddqby1dl
$mmdc_mprddqby2dl
$mmdc_mprddqby3dl
$mmdc_mpwrdqby0dl
$mmdc_mpwrdqby1dl
$mmdc_mpwrdqby2dl
$mmdc_mpwrdqby3dl
$mmdc_mpdgctrl0
$mmdc_mpdgctrl1
$mmdc_mprddlctl
$mmdc_mpwrdlctl
0x0007001B
0x00040018
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x03070321
0x030F025A
0x3D3B3648
0x493D4D3C
->
->
->
->
->
->
->
->
->
->
->
->
->
->
$mmdc2_mpwldectrl0
$mmdc2_mpwldectrl1
$mmdc2_mprddqby0dl
$mmdc2_mprddqby1dl
$mmdc2_mprddqby2dl
$mmdc2_mprddqby3dl
$mmdc2_mpwrdqby0dl
$mmdc2_mpwrdqby1dl
$mmdc2_mpwrdqby2dl
$mmdc2_mpwrdqby3dl
$mmdc2_mpdgctrl0
$mmdc2_mpdgctrl1
$mmdc2_mprddlctl
$mmdc2_mpwrdlctl
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
DDR3 PHY Calibration
The DDR PHY on the i.MX6 requires calibration. The calibration process fine tunes various parameters including:
● ZQ calibration
● Write leveling calibration
● DQS gating calibration
● Read data DQS delay calibration
● Write data DQS delay calibration
VTOS DDR supports two modes for calibrating the DDR3 PHY.
1. Empirical software calibration
2. Automatic hardware calibration (no longer recommended by Freescale)
Empirical Software Calibration
VTOS DDR provides an empirical software calibration procedure for the DDR3 PHY on the i.MX6 processor
family. This procedure calibrates the DDR3 PHY by executing the following steps:
1. Set the write leveling delay for one byte lane to a fixed value.
2. Calibrate of the DQS gating
3. Calibrate the read data DQS delay
4. Calibrate the write data DQS delay
5. Run a memory cell test
6. Run a memory bus noise test
7. Increment the write leveling delay value and repeat at step 2.
The procedure is repeated for all valid byte lanes for the design. For example, if your board uses a 64-bit wide
data bus to the DDR memory, the procedure is repeated a total of 8 times.
Unlike hardware based calibration, the empirical software calibration procedure does not use DQ prime bits to
obtain the leveling feedback. Instead, the results of the memory tests determine whether a specific write
leveling setting is valid. At the successfully completion of the procedure, VTOS DDR reports the window of valid
write leveling delay values for all byte lanes and sets the calibrated result to the middle of the window.
Running the Empirical Software Calibration
The empirical software calibration procedure can take significant time to run, as much as 20 minutes or more to
complete. The procedure is typically run on new board designs, when changing to a new memory part, or
changing the DDR interface speed.
Follow this procedure when running the empirical software calibration procedure:
1. In you board file, set the following parameters:
a. Set Write Additional Latency to the maximum value of 3.
b. Set Read Additional Latency to the maximum value of 7.
c. Enable Fixed PHY calibration
d. Set the initial value of all PHY calibration registers to zero.
Example board file settings are shown below.
3 -> $ddr.memctrl.walat // Write Additional Latency
7 -> $ddr.memctrl.ralat // Read Additional Latency
TRUE -> $ddr.memctrl.fixed_calibration
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AN133 – VTOS DDR: i.MX6 Processor Addendum
0
0
0
0
0
0
0
0
0
0
0
0
->
->
->
->
->
->
->
->
->
->
->
->
$mmdc_mpwldectrl0
$mmdc_mpwldectrl1
$mmdc_mpdgctrl0
$mmdc_mpdgctrl1
$mmdc_mprddlctl
$mmdc_mpwrdlctl
$mmdc2_mpwldectrl0
$mmdc2_mpwldectrl1
$mmdc2_mpdgctrl0
$mmdc2_mpdgctrl1
$mmdc2_mprddlctl
$mmdc2_mpwrdlctl
2. Configure the DDR controller using the Configure->Configure DDR controller menu option, or by running
the command ddr.configure. Note that at this point, the DDR3 PHY is programmed with reset values
and the DDR memory tests are not expected to pass.
3. Run the empirical software calibration. Run the command ddr.tune.phy. Note that for designs using
64-bit wide memory, this procedure can take 20 minutes or more to complete.
4. At the completion of the empirical software calibration, update your board file with the fixed PHY
calibration settings displayed.
Example output from the empirical software calibration executed on a Sabre-Lite reference design is shown
below.
kozio> ddr.tune.phy
Searching for write level window on byte lane 0
------------------------------------------------MPWLDECTRL = 0x00000000
Starting calibration of DQS gating, read delay, and write delay
Warning: PHY0 reported errors during read DQS gating
Warning: PHY1 reported errors during read DQS gating
Warning: PHY0 reported errors during read delay line calibration
Warning: PHY1 reported errors during read delay line calibration
Warning: PHY0 reported errors during write delay line calibration
Warning: PHY1 reported errors during write delay line calibration
Calibration of DQS gating, read delay, and write delay completed
SDRAM: Full burst (64 bit) [00000000_10000000 - 00000000_100fffff]
Warning: only comparing data bus mask bits 0x00000000_000000ff
................Bad value at address 0x00000000_10000008
expected 0x00000000_10000008, actual 0xffdfefff_ffffffff
//
// output truncated
//
Write level window (1/256 cycles) for byte 0
lower = 0x00000001
upper = 0x00000077
middle = 0x0000003C
Searching for write level window on byte lane 1
------------------------------------------------MPWLDECTRL = 0x0000003C
Starting calibration of DQS gating, read delay, and write delay
Calibration of DQS gating, read delay, and write delay completed
SDRAM: Full burst (64 bit) [00000000_10000000 - 00000000_100fffff]
Warning: only comparing data bus mask bits 0x00000000_0000ff00
.................................................................
Passed!
SDRAM: Memory bus noise (burst) [00000000_10000000 - 00000000_100fffff]
Warning: only comparing data bus mask bits 0x00000000_0000ff00
.................................................................
Passed!
//
// output truncated
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AN133 – VTOS DDR: i.MX6 Processor Addendum
//
Final Write Leveling results (1/256 cycles):
lower
upper
middle MPWLDECTRL setting
Byte 0 : 0x0001 0x0077 0x003C
0x003C
Byte 1 : 0x0000 0x006C 0x0036
0x0036
Byte 2 : 0x0000 0x005E 0x002F
0x002F
Byte 3 : 0x0000 0x0074 0x003A
0x003A
Byte 4 : 0x0000 0x0067 0x0033
0x0033
Byte 5 : 0x0000 0x0076 0x003B
0x003B
Byte 6 : 0x0000 0x005F 0x002F
0x002F
Byte 7 : 0x0000 0x0062 0x0031
0x0031
Calibration completed.
following settings.
Update your board file with the
TRUE -> $ddr.memctrl.fixed_calibration
0x0036003C -> $mmdc_mpwldectrl0
0x003A002F -> $mmdc_mpwldectrl1
0x4302031C -> $mmdc_mpdgctrl0
0x027D026E -> $mmdc_mpdgctrl1
0x40303436 -> $mmdc_mprddlctl
0x34474A44 -> $mmdc_mpwrdlctl
0x003B0033 -> $mmdc2_mpwldectrl0
0x0031002F -> $mmdc2_mpwldectrl1
0x03070321 -> $mmdc2_mpdgctrl0
0x03010255 -> $mmdc2_mpdgctrl1
0x37363047 -> $mmdc2_mprddlctl
0x493A4D3D -> $mmdc2_mpwrdlctl
Tip: The empirical software calibration may generate warnings regarding PHY errors during the calibration
process. These warnings are expected, especially during the first phases of the empirical software calibration.
If you see the message “Final Write Leveling results”, then the empirical software calibration completed
successfully.
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Command Summary
VTOS DDR provides the following commands related to empirical software calibration on the i.MX6 processor.
Command
Description
ddr.tune.phy
Searches for valid write leveling values and calibrates all required DDR3
parameters. The process is automatically repeated for all available byte lanes on
the design.
The current write leveling value on each byte lane is used as a seed value to begin
the search. If the search fails for any byte lane, set the corresponding
MPWLDECTRL register to zero and retry.
Usage
Parameters
Command
Description
Usage
Parameters
Note that you must run the command ddr.configure before running this
command.
ddr.tune.phy
None
tune.wrlvl
Searches for valid write leveling values and calibrates all required DDR3
parameters on a single byte lane only. While this command runs, any data errors
on other byte lanes are ignored.
Note that you must run the command ddr.configure before running this
command.
<byte_lane> tune.wrlvl
None
<byte_lane>
<ddr_dqsx_length>
Command
Description
Usage
Parameters
© Copyright Kozio, Inc. 2014
The byte lane to run calibration against. Valid values are
0 – 7.
Average trace length of the DDR_DQSx signals, specified
in thousandths of an inch.
ddr.calibration.report
Display the results of the last ddr.tune.phy calibration performed.
ddr.calibration.report
None
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Automatic Hardware Calibration
VTOS DDR executes the automatic hardware calibration for all the required PHY parameters. Note that using
automatic hardware calibration is no longer recommended by Freescale. However, the automatic hardware
calibration runs very quickly compared to the empirical software calibration. It can be useful to initially run the
automatic hardware calibration to find stable, but not necessarily optimal DDR PHY settings.
Automatic hardware calibration is enabled by including the following line in your Timing Based or Register Based
board file:
FALSE -> $ddr.memctrl.fixed_calibration
When automatic hardware calibration is enabled, the command ddr.configure displays the calibration results.
The output from the hardware calibration executed on a Sabre-Lite reference design from Freescale is shown
below.
kozio> ddr.configure
Configuring MMDC channel 1 for DDR3
Resetting MMDC channel 1
DDR total size = 1 GiB
Performing HW based calibration for DDR3
Starting ZQ calibration
ZQ calibration complete
Starting write leveling calibration
Write leveling complete
Preparing DQS gating and delay line calibration
Starting DQS gating calibration
DQS gating calibration completed.
Starting read delay line calibration.
Read calibration completed.
Starting write delay line calibration.
Write calibration completed.
HW based calibration completed successfully
Calibration completed.
following settings.
Update your board file with the
TRUE -> $ddr.memctrl.fixed_calibration
0x001B0016 -> $mmdc_mpwldectrl0
0x001D001B -> $mmdc_mpwldectrl1
0x4313032C -> $mmdc_mpdgctrl0
0x0310027E -> $mmdc_mpdgctrl1
0x473B3E40 -> $mmdc_mprddlctl
0x36444741 -> $mmdc_mpwrdlctl
0x000C001D -> $mmdc2_mpwldectrl0
0x00070018 -> $mmdc2_mpwldectrl1
0x0307031D -> $mmdc2_mpdgctrl0
0x03060252 -> $mmdc2_mpdgctrl1
0x41383848 -> $mmdc2_mprddlctl
0x45344C3E -> $mmdc2_mpwrdlctl
Enabling MMDC 1 controller for DDR3 operation
At this point you should run all the DDR tests to confirm the DDR settings and PHY calibration values are good.
After confirming calibration values on several boards, you can use fixed calibration values by copying and
pasting the calibration results back into your board file.
© Copyright Kozio, Inc. 2014
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AN133 – VTOS DDR: i.MX6 Processor Addendum
The example below shows the output from the ddr.configure command when fixed calibration is used.
kozio> ddr.configure
Configuring MMDC channel 1 for DDR3
Resetting MMDC channel 1
DDR total size = 1 GiB
Enabling MMDC 1 controller for DDR3 operation
Manually Starting Hardware Calibration
You can execute the DDR PHY calibration manually with command imx6.ddr3.calib.hw. You may run this
command even if your board file has enabled fixed calibration values. Repeatedly execute the DDR PHY
calibration to verify that the calibration results are stable.
kozio> imx6.ddr3.calib.hw
Performing HW based calibration for DDR3
Starting ZQ calibration
ZQ calibration complete
Starting write leveling calibration
Write leveling complete
Preparing DQS gating and delay line calibration
Starting DQS gating calibration
DQS gating calibration completed.
Starting read delay line calibration.
Read calibration completed.
Starting write delay line calibration.
Write calibration completed.
HW based calibration completed successfully
To skip hardware driven calibration, copy and paste the following
lines into your board file.
TRUE -> $ddr.memctrl.fixed_calibration
0x001B0016 -> $mmdc_mpwldectrl0
0x001E001B -> $mmdc_mpwldectrl1
0x4313032C -> $mmdc_mpdgctrl0
0x03120300 -> $mmdc_mpdgctrl1
0x473A3C40 -> $mmdc_mprddlctl
0x36444741 -> $mmdc_mpwrdlctl
0x000D001D -> $mmdc2_mpwldectrl0
0x00070018 -> $mmdc2_mpwldectrl1
0x0309031D -> $mmdc2_mpdgctrl0
0x0301024D -> $mmdc2_mpdgctrl1
0x3F363848 -> $mmdc2_mprddlctl
0x45344B3D -> $mmdc2_mpwrdlctl
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AN133 – VTOS DDR: i.MX6 Processor Addendum
Additional Contact Information
Kozio, Inc., +1 (303) 776-1356 x1, [email protected], www.kozio.comhttp://www.kozio.com/
http://www.kozio.com/
About Kozio, Inc.
Kozio, Inc. is a software technology company focused on providing superior embedded tools solving a variety of
challenges during the design, production, and support of embedded devices. With its wide range of embedded
tools, Kozio offers solutions to aerospace, automotive, consumer, industrial, military, medical, networking, and
wireless markets. Kozio has been crafting embedded software since 2003 and has served the needs of thousands
of engineers working for hundreds of companies, from the smallest to the largest.
Kozio’s line of embedded tools include everything you need to configure, test, and tune DDR memory; identify
interconnect faults and component placement problems on your printed circuit board; program on-board
devices such as NAND Flash, NOR Flash, eMMC, FPGAs, and other programmable devices; and control, monitor,
and calibrate power settings and usage. Kozio’s tools are reusable across a family of SoC-based designs and
reusable across teams.
© 2014 Kozio, Inc. All rights reserved worldwide. Kozio and the Kozio logo are registered trademarks of Kozio,
Inc. VTOS, VTOS DDR, VTOS Scan, VTOS Program, and vAccess are trademarks of Kozio, Inc. All other trademarks
are the property of their respective owners.
© Copyright Kozio, Inc. 2014
22
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