MB39A302 5ch System Power Management IC for LCD Panel with

MB39A302 5ch System Power Management IC for LCD Panel with
MB39A302
5ch System Power Management IC
for LCD Panel with VCOM Regulator
MB39A302 is a 5ch system power supply management IC. It consists of 1ch Buck converter, 1ch Boost converter, 2ch charge pump,
1ch LDO, an operational amplifier for VCOM calibration and a gate voltage shaping circuit. The Buck converter is a voltage mode
asynchronous converter with integrated switching FET. The Boost converter equips integrated switching FET with voltage mode
control. It is most suitable for large size LCD panel power supply.
Features
 Power supply voltage range (VIN=VINVL=VIN2)
: 8 V to14 V
 Boost Converter included SW FET (Vs)
: output 20 V Max 1.5 A Max
 Buck Converter included SW FET (Vlogic)
: output 1.8 V to 3.3 V 1.1 A Max
 Negative charge pump with output voltage feedback (VGL)
: output current 250 mA Max
 Positive charge pump with output voltage feedback (VGH)
: output current 250 mA Max
 Low dropout regulator (Vref_o)
: output current 60 mA Max
 High performance operational amplifier (VCOM)
: output current ±75 mA Max, 20 MHz Gain bandwidth
 Feedback threshold voltage
: 1.25 V ±1% (Vs)
: 1.25 V ±1% (Vlogic)
: 0.25 V ±40 mV (VGL)
: 1.25 V ±2% (VGH)
: 1.25 V ±0.5% (Vref_o)
 Built-in soft-start circuit independent of loading (Vs - programmable, Vlogic, VGL, VGH)
 Excellent line regulation by the feed-forward method (Vs, Vlogic)
 Built-in output over voltage protection (Vs, Vlogic)
 Built-in output under voltage and short circuit protection (Vs, Vlogic, VGL, VGH)
 Built-in current limit protection (Vs - programmable, Vlogic, Vref_o, OPO)
 Built-in external p-channel gate control for Vs sequencing
 Integrated gate voltage shaping circuitry with adjustable turn on delay
 Built-in under voltage lock out protection function
 Built-in over temperature protection
 Selectable 500 kHz/750 kHz switching frequency
 Package: QFN-48 Exposed PAD
Applications
 Power supply of LCD panel for TV and monitor
Cypress Semiconductor Corporation
Document Number: 002-08356 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 19, 2016
MB39A302
Contents
1. Pin Assignment ................................................................................................................................................................. 3
2. Pin Descriptions ................................................................................................................................................................ 4
3. I/O Pin Equivalent Circuit Diagram .................................................................................................................................. 5
4. Block Diagram ................................................................................................................................................................... 7
5. Functional Descriptions ................................................................................................................................................... 8
6. Absolute Maximum Ratings ........................................................................................................................................... 13
7. Recommended Operating Conditions ........................................................................................................................... 14
8. Electrical Characteristics ............................................................................................................................................... 16
9. Typical Characteristics ................................................................................................................................................... 21
10. Setup ................................................................................................................................................................................ 28
10.1 Setting Control Pin....................................................................................................................................................... 28
10.2 Setting Switching Frequency ....................................................................................................................................... 28
10.3 Protection Circuitry ...................................................................................................................................................... 28
11. Application Note.............................................................................................................................................................. 29
12. Circuit Diagram ............................................................................................................................................................... 39
13. Land Pattern .................................................................................................................................................................... 43
14. Usage Precaution ............................................................................................................................................................ 44
15. Ordering Information ...................................................................................................................................................... 45
16. EV Board Ordering Information ..................................................................................................................................... 45
17. RoHS Compliance Information of Lead (Pb) Free Version .......................................................................................... 45
18. Marking Format (Lead Free Version) ............................................................................................................................. 45
19. Labeling Sample (Lead Free Version) ........................................................................................................................... 46
20. MB39A302 Recommended Conditions of Moisture Sensitivity Level ........................................................................ 47
21. Package Dimensions ...................................................................................................................................................... 49
22. Major Changes ................................................................................................................................................................ 50
Document History ................................................................................................................................................................. 51
Document Number: 002-08356 Rev. *A
Page 2 of 52
MB39A302
1. Pin Assignment
DLY1
FBP
VGH
VGHM
DRN
SUPN
DRVN
GND
FBN
REF
VREF_FB
VREF_O
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
VREF_I 1
36 DRVP
VOP 2
35 CPGND
OGND 3
34 SUPP
OPP 4
33 THR
OPN 5
32 COMP
OPO 6
31 FB1
XAO 7
30 GD
GVOFF 8
29 GD_I
EN 9
28 PGND
FB2 10
27 PGND
OUT 11
26 LX1
GND 12
25 LX1
SS
CLIM
FSEL
VL
INVL
VDET
GND
IN2
IN2
BST
LX2
LX2
13 14 15 16 17 18 19 20 21 22 23 24
(LCC-48P-M11)
Document Number: 002-08356 Rev. *A
Page 3 of 52
MB39A302
2. Pin Descriptions
Block
Vs
(Boost
DC/DC)
Vlogic
(Buck
DC/DC)
VGL
(Negative
Charge
Pump)
VGH
(Positive
Charge
Pump)
Gate Voltage
Shaping
Vref_o (LDO)
VCOM
(OPAMP)
Misc.
Control Pin
Power
Pin No.
Pin Name
I/O
Description
23
24
25
26
29
30
31
32
10
11
13
14
15
42
43
45
46
36
34
CLIM
SS
LX1
LX1
GD_I
GD
FB1
COMP
FB2
OUT
LX2
LX2
BST
SUPN
DRVN
FBN
REF
DRVP
SUPP
I
I
Boost converter current limit setting pin
Boost converter soft start timing control pin
O
Boost converter inductor connection pin
I
O
I
O
I
I
External isolation PMOS source terminal connection and VGH supply pin
External isolation PMOS gate terminal connection pin
Boost converter Error Amp input pin
Boost converter frequency compensation pin
Buck converter Error Amp input pin
Buck converter regulated output sense pin
O
Buck converter inductor connection pin
I/O
O
O
I
O
O
O
Buck converter gate drive boot pin
VGL power supply decoupling capacitor connection pin
VGL external pumping capacitor connection pin
VGL Error Amp input pin
Reference voltage output pin
VGH external pumping capacitor connection pin
VGH power supply decoupling capacitor connection pin
38
FBP
I
VGH Error Amp input pin
39
40
41
8
33
37
47
48
4
5
6
21
7
9
19
22
1
2
16
17
20
27
28
35
44
3
12
18
VGH
VGHM
DRN
GVOFF
THR
DLY1
VREF_FB
VREF_O
OPP
OPN
OPO
VL
XAO
EN
VDET
FSEL
VREF_I
VOP
IN2
IN2
INVL
PGND
PGND
CPGND
GND
OGND
GND
GND
I
I/O
I/O
I
I
I
I
O
I
I
O
O
O
I
I
I
I
I
I
I
I
-
Gate shaping circuit high voltage input pin
Gate voltage shaping circuit output pin
Gate voltage shaping discharge slope adjustment pin
Gate voltage shaping circuit control pin
Gate voltage shaping circuit output lower limit control pin (10xTHR)
Time delay control pin for gate voltage shaping circuit
LDO feedback input pin
LDO output pin
VCOMP OPAMP non-inverting input pin
VCOMP OPAMP inverting input pin
VCOMP OPAMP output pin
Internal 5.2 V regulator output pin
Open drain output of power supply detection circuit
5.2 V rated Boost converter enable pin
Power supply detection input pin
Switching frequency select pin
VREF LDO supply pin
VCOMP OPAMP supply pin
Buck converter and VGL power supply pin
Buck converter and VGL power supply pin
Common and Internal 5.2 V regulator supply pin
Document Number: 002-08356 Rev. *A
-
High Current Boost Ground pin
VGH Ground pin
Analog ground pin
VCOM OPAMP ground pin
Analog ground pin
Analog ground pin
Page 4 of 52
MB39A302
3. I/O Pin Equivalent Circuit Diagram
Document Number: 002-08356 Rev. *A
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MB39A302
Document Number: 002-08356 Rev. *A
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MB39A302
4. Block Diagram
Document Number: 002-08356 Rev. *A
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MB39A302
5. Functional Descriptions
CH1 (Vs): Boost Converter
The Boost converter features fixed frequency pulse width modulated (PWM) control with integrated NMOS power switch. The
switching frequency can be set to either 500 kHz or 750 kHz via the FSEL pin. The converter operates as an asynchronous Boost
converter with external Schottky diode. The use of voltage mode control with input feed forward improves line regulation
performance. In addition, the converter is designed with external frequency compensation that allows flexibility on selecting external
component values. A PMOS switch with on resistance of 18 Ω connects between LX1 and GD_I pin so that it operates in parallel
with the external Schottky diode. At high loading current, most of the inductor current flows through the external Schottky diode. At
light load, the PMOS switch provides a conduction path that allows the inductor current flow in reverse direction. As a result, the
converter stays in continuous conduction mode for most of the load current range and allows the use of simple frequency
compensation scheme.
Soft Start (Boost Converter)
The build in soft start circuit limits the inrush current at start up. The soft start cycle starts after EN is asserted and the duration can
be set by user through the capacitor connected to SS pin.
1. When SS pin capacitor value > 220 pF, soft start time is set externally. Charging current is 5 μA and
trigger threshold is 1.25 V.
2. When SS pin capacitor value < 220 pF or SS pin is open, soft start time is fixed internally at 10 ms.
Protection (Boost Converter)
The Boost converter has built in over voltage protection to prevent MB39A302 from being damaged due to excessive voltage stress
under fault conditions such as FB1 pin is left floating or short to ground. The protection circuitry monitors the Boost converter output
via GD_I pin and shut down the NMOS power FET that connects to LX1 pin when the voltage on GD_I pin is higher than 21.5 V. As
a result, the inductor current starts to fall and the output of the Boost converter follows. The Boost converter resumes normal
operation when the voltage at GD_I pin falls below the protection threshold.
The Boost converter has built in under voltage protection and short circuit protection to prevent MB39A302 from damage due to low
voltage stress under fault conditions. The protection circuitry monitors the Boost converter output via FB1 pin and the Under Voltage
Protection activates when the voltage on FB1 pin is lower than 1 V and the NMOS power FET will be shut down after 50 ms. The
Short Circuit Protection will activate when the voltage of FB1 pin is lower than 0.5 V and the NMOS power FET will be shut down
immediately.
In addition, Boost converter has programmable over current protection that turns off the power FET to prevent excessive output
current from damaging internal IC and external components.
Gate Drive Pin (GD)
GD pin voltage is pulled down by 10 µA (Typ) internal current source after EN pin is asserted. The external PMOS turns on and
connects the cathode of the Boost converter Schottky catch diode to the Boost converter load capacitors when GD falls below the
turn-on threshold of the external PMOS. When VGD reaches VGD_I-6V, the Boost converter regulator is enabled and initiates a
soft-start routine. Startup SCP protection is included to protect external PMOS from permanent damage in the event that Boost
output is initially shorted to GND upon power up. When not using this feature, leave GD high impedance and connect GD_I to the
output of the Boost converter.
CH2 (Vlogic): Buck Converter
The Buck converter is a fixed frequency PWM control asynchronous converter with integrated NMOS power switch. It features
voltage mode control with input feed forward to improve line regulation performance. The main switch of the converter is a 3.2 A
rated power NMOS with gate drive circuit reference to LX2 pin (source terminal of the NMOS power FET). The gate drive circuit is
powered from an internal 5V regulator and is bootstrapped from LX2 pin via an external capacitor to achieve driving capability
beyond the supply rail.
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MB39A302
Soft Start (Buck Converter)
The build in soft start circuit limits the inrush current at start up. The soft start cycle start after power supply is asserted and the
duration is internally set to 3 ms.
Protection (Buck Converter)
The Buck converter has built in over voltage protection to prevent MB39A302 from being damaged due to excessive voltage stress
under fault conditions such as FB2 pin is left floating or short to ground. The protection circuitry monitors the Buck converter output
voltage via OUT pin and shut down the NMOS power FET that connects to LX2 pin when the voltage on OUT pin is higher than
3.7 V. As a result, the inductor current starts to fall and the output of the Buck converter follows. The Buck converter resumes normal
operation when the voltage at OUT pin falls below the protection threshold.
The Buck converter has built in under voltage protection and short circuit protection to prevent MB39A302 from damage due to low
voltage stress under fault conditions. The protection circuitry monitors the Buck converter output voltage via FB2 pin and the Under
Voltage Protection activates when the voltage on FB2 pin is lower than 1 V and the NMOS power FET will be shut down after 50 ms.
The Short Circuit Protection will activate when the voltage of FB2 pin is lower than 0.5 V and the NMOS power FET will be shut
down immediately.
In addition, Buck converter has over current protection that turns off the power FET to prevent excessive output current from
damaging internal IC and external components.
CH3 (VGL): Negative Charge Pump
The negative charge pump uses fixed switching frequency controlled architecture. The output voltage is set externally by a resistor
divider. Regulation is done by controlling the pump current in the driver. The charge pump uses external diodes, pumping capacitor
and output filter capacitor. Since the input of the charge pump and the driver is connected to the supply pin (VIN), the maximum
negative output voltage is -VIN +Vloss. Vloss includes voltage drop in external diodes and gate driver. Additional charge pump stage
can be added to generate larger negative voltage.
Protection (Negative Charge Pump)
The negative charge pump has built in under voltage protection and short circuit protection. The protection circuitry monitors the
charge pump output voltage via FBN pin and the Under Voltage Protection activates when the voltage on REF-FBN pin is lower than
0.8 V and the power FETs will be shut down after 50 ms. The Short Circuit Protection will activate when the voltage of REF-FBN pin
is lower than 0.4 V and the power FETs will be shut down immediately.
CH4 (VGH): Positive Charge Pump
The positive charge pump uses fixed switching frequency controlled architecture. The output voltage is set externally by a resistor
divider. Regulation is done by controlling the pump current in the driver. The charge pump uses external diodes, pumping
capacitor and output filter capacitor. The input of the charge pump is connected to the VS (Boost converter output) and the pump
capacitor is charged to VS during charging phase. As the supply to the driver (SUPP pin) can be either the VS (Boost converter
output) or the VIN (Power supply) of MB39A302, the maximum output voltage is VSUPP + VS - Vloss. Vloss includes voltage drop in
external diodes and gate driver. Additional charge pump stage can be added to increase the maximum output voltage.
Protection (Positive Charge Pump)
The positive charge pump has built in under voltage protection and short circuit protection. The protection circuitry monitors the
charge pump output voltage via FBP pin and the Under Voltage Protection activates when the voltage on FBP pin is lower than 1 V
and the power FETs will be shut down after 50 ms. The Short Circuit Protection will activate when the voltage of FBP pin is lower
than 0.5 V and the power FETs will be shut down immediately.
Document Number: 002-08356 Rev. *A
Page 9 of 52
MB39A302
CH5 (Vref_o): Low Dropout regulator (LDO)
The integrated low noise low drop out regulator (LDO) is available with 60mA current capability. It has built in over current protection
circuit to prevent the LDO from being damaged under fault conditions. This LDO can be stable with 1 μF to 10 μF output ceramic
capacitor.
CH6 (OPO): VCOM Operational Amplifier
The integrated low input offset voltage operational amplifier (OP Amp) is available with ±75 mA current capability. It can be stable
with 3 Ω to 10 Ω load resistor in series with 1 μF to 150 μF output capacitor. There is also built in over current protection to prevent
this amplifier from being damaged under fault conditions.
Gate Voltage Shaping
The ability to control the falling edge of the gate drive signal is essential for reduction of flicking on LCD display. The gate voltage
shaping circuit provides timing and slew rate control for the gate drive signal and an isolation switch to protect circuit powered from
VGH.
Upon initial startup, VGHM output stays low until after XAO is released (pulled low), VGH reached power good and the capacitor on
DLY1 pin past 1.25 V. Then, VGHM would be dictated by the logic level on GVOFF and the cut threshold dictated by THR pin
voltage. After this, if XAO is pulled low, then VGH and VGHM are shorted together as long as there is enough supply voltage to
maintain the circuit operation.
XAO
XAO is an open-drain output that externally connects through a resistor to Vlogic. Upon startup, XAO follow VLOGIC output. When
VLOGIC and VGL reaches 90% of its final output, XAO control is passed to VDET pin. When VDET sense that VIN is below desired
voltage (defined by external resistor divider), XAO is pulled low immediately.
Common Block
Under Voltage Lockout Protection
MB39A302 will shutdown when the supply voltage below 6 V to prevent improper operation of the device.
Over Temperature Protection
When the junction temperature rises above +150°C, most of the active circuitries are shutdown to prevent damage from excessive
power dissipation beyond safety limits.
Document Number: 002-08356 Rev. *A
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MB39A302
Power Up Sequencing
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Page 11 of 52
MB39A302
Power Down Sequencing
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Page 12 of 52
MB39A302
6. Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
VDD
VBOOT
AVDD
VLV_IN
Input/Output voltage
SW voltage
SW peak current
Power dissipation
Storage temperature
VLV_OUT
VHV_IN
VGL_OUT
VGH_OUT
VGH
VGS
VREFO
VOPP
VOPN
VOPO
SUPN
VGD
VLX
VLX
ILX
ILX
PD
TSTG
Rating
Condition
IN2, INVL
BST
SUPP, VREF_I, VOP
CLIM, SS, FB1, FB2, FBN, FBP,
GVOFF, THR, DLY1, VREF_FB, EN,
VDET, OUT
COMP, REF, XAO, VL
FSEL
DRVN
DRVP
VGH
VGHM, DRN
VREF_O
OPP
OPN
OPO
SUPN
GD, GD_I
LX1
LX2
LX1 AC
LX2 AC
Ta ≤ +85°C
-
Min
Unit
Max
-0.3
-0.3
-0.3
+20
+25
+25
V
V
V
-0.3
+5.5
V
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-1
-1
-0.3
-0.3
-0.3
-2
-55
+5.5
+20
+20
+25
+40
+40
+20
+25
+25
+25
+20
+25
+25
+20
4.2
3.9
1.51
+125
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
W
°C
[1]: When mounted on a 100mm ×100 mm: 4 layer (2S2P JEDEC).
-1
-1
θja: 26.5°CW , θjc: 0.5°CW
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-08356 Rev. *A
Page 13 of 52
MB39A302
7. Recommended Operating Conditions
Parameter
Power supply voltage
Symbol
VIN
VBOOT
VSUP
VSS
VTHR
VILIM
VFB
Input voltage
Output voltage
VGD
VEN
VFSEL
VGH
VCOM
VXAO
VO1
VO2
VO3
VO4
VO5
VO6
Output current
REF pin output current
SW inductor
BOOT pin capacitor
SUPP pin capacitor
GD pin capacitor
DRP, DRN pins capacitor
SUPN pin capacitor
REF pin capacitor
VL pin capacitor
INVL pin capacitor
VREFI pin capacitor
VOP pin capacitor
Document Number: 002-08356 Rev. *A
VOX
IO1
IO2
IO3
IO4
IO4
IO5
IO6
IO6
IGD
IGDI
IDRVN
IDRVP
IREF
LX1
LX2
CBOOT
CSUPP
CGD1,
CGD2
CDRV
CSUPN
CREF
CVL
CINVL
CVREFI
CVOP
Condition
Value
Typ
Min
Max
Unit
IN2, INVL, SUPN
BST
SUPP, VREF_I, VOP
SS, DLY1
THR
CLIM
FB1, FB2, FBN, FBP,
VREF_FB, OUT
GD, GD_I
EN, GVOFF
FSEL
VGH
OPP, OPN
VDET
VS: Boost DC/DC
VLOGIC: Buck DC/DC
VGL
VGH, VGHM
VREF_O: LDO
(Io = 1 mA to 60 mA)
OPO: Opamp
(Io = 1 mA to 25 mA)
XAO
VS: BOOST DC
VLOGIC: BUCK DC
VGL DC
DRN pin Peak
VGH DC
Vref DC: VREF_O
VCOMP DC: OPO
VCOMP AC: OPO
GD
GD_I (light load)
DRVN
DRVP
REF
LX1
LX2
BST
SUPP
8
8
0
0
0
12[1]
-
14
19
20
5
5
5
V
V
V
V
V
V
0
-
5
V
0
0
0
0
0
0
-
17.7
3.3
-5.5
30
20
5
20
37
20
3.7
-
V
V
V
V
V
V
V
V
V
V
-
17
-
V
-
7.5
-
V
0
0
0
-0.25
0.5
-75
-200
-100
-500
-500
-50
0.01
-
0.1
0.1
10
6.8
10
0.10
1
GD
-
10
-
µF
DRVP, DRVN
SUPN
REF
VL
INVL
VREFI
VOP
-
0.47
1
1
1
1
1
1
-
µF
µF
µF
µF
μF
μF
μF
5
1.5[2]
1.1
0.25[3]
0.25[4], [5]
60
75
200
100
500
500
0
1.00
-
V
A
A
A
A
A
mA
mA
mA
µA
mA
mA
mA
µA
µH
µH
µF
µF
Page 14 of 52
MB39A302
Parameter
Symbol
Condition
Min
Value
Typ
Max
Unit
IN2 pin capacitor
CLIM pin resistor
VS output filter capacitor
CIN2
RCLIM
Cout1
IN2
CLIM
VS: Boost DC/DC
10
60
-
40
60
70
-
µF
kΩ
µF
VLOGIC output filter capacitor
Cout2
VLOGIC: Buck DC/DC
-
µF
Cout3
Cout4
Cscan
Cout5
Cout6
Rscan
Rdrn
Rout6
Fscan
Tdscan
Ta
NCP
PCP
In series with Rscan
VREF_O: LDO
In series with Rout
VGHM
DRN
In series with Cout
-
1
0.47
1
1
1
200
3
40
1
-30
2×10
4.7
10
1.61
+25
-
VGL output filter capacitor
VGH output filter capacitor
VGHM output capacitor
LDO output filter capacitor
VCOMP output filter capacitor
VGHM output resistance
VGHM output resistance
VCOMP output filter resistance
Charge/Discharge cycle frequency
Discharge duration
Operating ambient temperature
20
10.00
1000
10
150
3000
10
70
10
+85
µF
µF
nF
µF
µF
kΩ
Ω
Ω
kHz
µs
°C
[1]: Performance is guaranteed for 12 V ± 10%
[2]: Maximum current is only guaranteed if OCP is not triggered. ILIM > Vo1 × Io1max/VIN + VIN × (Vo1-VIN) /L/fosc/Vo1/2
For: VIN = 8 V, Iomax = 1 A, VIN=10 V, Iomax = 1.2 A, VIN ≥ 12 V, Iomax = 1.5 A
[3]: Maximum current is only guaranteed if VIN-|Vo3| > Rdsonmax (Hiside + Loside) × 2 × Imax + 2 × Vdiode +
Imax / (fosc × Cpump) (for doubler).
For Vo3 = -5.5 V: VIN > 12 V, Iomax = 250 mA, VIN = 10 V, Iomax = 150 mA, VIN = 8 V, Iomax = 80 mA
[4]: Maximum current is only guaranteed if 2 × Vo1 - Vo4 > Rdsonmax (Hiside + Loside) × 2 × Imax + 2 × Vdiode +
Imax/(fosc × Cpump) (for doubler).
For Vo1 = 17.7 V: Iomax = 150 mA
[5]: Maximum current is only guaranteed if VIN+2 × Vo1 - Vo4 > Rdsonmax (Hiside + Loside) × 4 × Imax + 4 × Vdiode + 3 ×
Imax/(fosc × Cpump) (for Tripler)
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-08356 Rev. *A
Page 15 of 52
MB39A302
8. Electrical Characteristics
(Ta = 0°C to + 85°C, VIN = IN2 = INVL = 12 V, SUPP = VREF_I = VOP = 17.7 V.
Typical values are at Ta = +25°C unless noted otherwise)
Parameter
REF Block
[REF]
Under Voltage
Lockout
Protection
Circuit Block
[UVLO]
Over
Temperature
Protection Block
[OTP]
Control Block
[CTL]
Symbol
Pin
VL Regulator
[VL]
Min
Typ
Max
Unit
REF output voltage
REF
46
IREF = 0 mA
-2%
1.25
+2%
V
REF load regulation
REF
46
0 < IREF < 50 µA
-
-
15
mV
UVLOIN
16, 17
INVL =
5.3
6
6.7
V
INHYS
16, 17
-
-
0.5
-
V
INVL UVLO
threshold
INVL hysteresis
width
VL UVLO threshold
UVLOVL
21
VL =
3
3.4
3.8
V
VL hysteresis width
VLHYS
21
-
-
0.5
-
V
[1]
Stop temperature
TOTPH
-
T junction
-
150
-
°C
Hysteresis width
TOTPHYS
-
-
-
20[1]
-
°C
Input voltage
threshold
VIH
8, 9, 22
EN, GVOFF, FSEL ON
2
-
-
V
VIL
8, 9, 22
EN, GVOFF, FSEL OFF
-
-
0.9
V
EN pulldown
resistance
REN
9
EN
-
800
-
kΩ
FSEL pullup current
IFSEL
22
FSEL
1.4
2.4
4.0
µA
-
5
-
mA
-
4
-
mA
FB1 = FBP = 1.5V, FBN = 0,
EN = VL, FSEL = H
(Only LX2 switching)
FB1 = FB2 =
FBP = 1.5V,
FBN = 0,
EN = VL,
FSEL = H
(No switching)
INVL + IN2 quiescent
current
IQ
16, 17,
20
INVL + IN2 standby
current
ISB
16, 17,
20
630
750
870
kHz
fosc
13, 14
25, 26
36, 43
FSEL = "H"
Output frequency
FSEL = "L"
420
500
580
kHz
General
Oscillator Block
[OSC]
Value
Condition
VL output voltage
VL
21
IL = 0 mA
4.9
5.2
5.5
V
VL load regulation
VL
21
0 < IVL < 30 mA
-
-
300
mV
Document Number: 002-08356 Rev. *A
Page 16 of 52
MB39A302
(Ta = 0°C to + 85°C, VIN = IN2 = INVL = 12 V, SUPP = VREF_I = VOP = 17.7 V.
Typical values are at Ta = +25°C unless noted otherwise)
Parameter
Pin
Value
Condition
Min
Typ
Max
Unit
Line regulation
Vline1
29, 34
VIN = 10.8 V to 13.2 V
-
-
0.15
%/V
Load regulation
Vload1
29, 34
Io1 = 150 mA to 1.5 A
-1
-
+1
%/A
Threshold voltage
VTH1
31
FB1
-1%
1.25
+1%
V
Input bias current
IB1
31
FB1 = 0 V
-100
0
100
nA
25, 26
27, 28
25, 26,
29
LX1 = 500 mA
VGS = 5 V
GD_I = -200 mA
VGS = 5 V
EN = 0 V
GD_I = 15 V
LX1 = 0 V
EN = 0 V
LX1 = 15 V
-
120
185
mΩ
-
18
36
Ω
-
-
10
µA
-
-
10
µA
SW NMOS-Tr
On resistance
SW PMOS-Tr
On resistance
VS
[Boost DC/DC]
Symbol
RON1
RON1
SW PMOS-Tr Leak
current
ILEAK1
29
SW NMOS-Tr Leak
current
ILEAK1
25, 26
Output OCP
threshold
ILIM1
25, 26
LX1,
RCLIM > 60 kΩ
2.83.54.260.5 kΩ/ 60.5 kΩ/ 60.5 kΩ/
RCLIM RCLIM
RCLIM
A
Vuvp1
31
FB1
0.96
1
1.04
V
Td,uvp1
-
-
42
50
58
ms
Vovp1
34
SUPP
21
21.5
22
V
Vscp1
31
FB1
0.4
0.5
0.6
V
3.8
5
6
µA
24
SS: CSS > 220 pF
SS charge current
SS: CSS < 220 pF
V(GD) - V(GD_I) >
4 V to 95% VO1
-
10
-
ms
Output UVP
threshold
Output UVP delay
time
Output OVP
threshold
Output SCP
threshold
Soft-start time
Tss1
GD clamp voltage
VGD1
29, 30
V(GD) - V(GD_I)
-7
-6
-5
V
GD discharge current
IGD1
30
GD
4
10
16
µA
Document Number: 002-08356 Rev. *A
Page 17 of 52
MB39A302
(Ta = 0°C to + 85°C, VIN = IN2 = INVL = 12 V, SUPP = VREF_I = VOP = 17.7 V.
Typical values are at Ta = +25°C unless noted otherwise)
Parameter
Vlogic
[Buck DC/DC]
VGL [Negative
Charge Pump]
Symbol
Pin
Value
Condition
Min
Typ
Max
Unit
Bootstrap output
VBST
15
FB2 = 5 V
-
4.5
-
V
Threshold voltage
VTH2
10
FB2
-1%
1.25
+1%
V
Input Bias current
IB2
10
FB2 = 0 V
-100
0
+100
nA
RON2
13, 14,
16, 17
LX2 = 0.2 A
VGS = 5 V
-
200
300
mΩ
ILEAK2
13, 14,
16, 17
LX2 = 0 V
-10
-
-
µA
ROUT
11
OUT
70
125
210
kΩ
Vovp2
11
OUT DC
3.5
3.7
3.9
V
Vuvp2
10
FB2
0.96
1.00
1.04
V
Td, uvp2
-
-
42
50
58
ms
ILIM2
13, 14
LX2
2.2
3.2
3.9
A
Vscp2
10
FB2
0.4
0.5
0.6
V
Load regulation
Vload2
11
Io2 = 150 mA to 1.1 A
-
-
0.5
%/A
Line regulation
Vline2
11
VIN: 10.8 to 13.2 V
-
-
0.1
%/V
Soft-start time
Tss2
10
0 to 99% VO2
-
3
-
ms
Threshold voltage
VTH3
45
FBN
210
250
290
mV
Input bias current
IB3
45
FBN = 0 V
-100
0
+100
nA
RON3
43, 44
Iout = 100 mA
-
1.5
3
Ω
RON3
42, 43
Iout = 100 mA
-
3.5
7
Ω
Vuvp3
45, 46
REF-FBN
0.768
0.800
0.832
V
Td, uvp3
-
-
42
50
58
ms
Vscp3
45, 46
REF-FBN
0.3
0.4
0.5
V
Tss3
45
0% to 95% VO3
-
3
-
ms
SW NMOS-Tr
(upper)
On resistance
SW NMOS-Tr
(upper)
Leak current
OUT to GND switch
on resistance
Output OVP
threshold
Output UVP
threshold
Output UVP delay
time
Output OCP
threshold
Output SCP
threshold
SW NMOS-Tr
On resistance
SW PMOS-Tr
On resistance
Output UVP
threshold
Output UVP delay
time
Output SCP
threshold
Soft start up time
Document Number: 002-08356 Rev. *A
Page 18 of 52
MB39A302
(Ta = 0°C to + 85°C, VIN = IN2 = INVL = 12 V, SUPP = VREF_I = VOP = 17.7 V.
Typical values are at Ta = +25°C unless noted otherwise)
Parameter
Threshold voltage
VGH
[Positive Charge
Pump]
GD_I input supply
current
Input bias current
SW NMOS-Tr
On resistance
SW PMOS-Tr
On resistance
Output UVP
threshold
Output UVP delay
time
Output SCP
threshold
VTH4
Pin
Value
Condition
Min
Typ
Max
Unit
38
FBP
-2%
1.25
+2%
V
IGDI
29
FBP = 1.5 V
(not switching)
-
0.4
-
mA
IB4
38
FBP = 0 V
-100
0
+100
nA
Iout = 100 mA
-
1.5
3
Ω
Iout = 100 mA
-
3.5
7
Ω
RON4
RON4
25, 26
27, 28
25, 26
27, 28
Vuvp4
38
FBP
0.96
1
1.04
V
Td,uvp4
-
-
42
50
58
ms
Vscp4
45, 46
FBP
0.4
0.5
0.6
V
Soft start up time
Tss4
38
90% VO1 to 95% VO4
-
3
-
ms
VGH supply current
IVGH
39
GVOFF = 0 V
-
0.1
-
mA
Rdson charge
Rchg5
39, 40
Ichg = 100 mA
-
5
10
Ω
Rdson discharge
Rdis5
40, 41
Idischg = 100 mA
-
20
50
Ω
Rvghm
40
DLY1 = GND, VGHM = 1 V
10
14
20
kΩ
Trise
8, 40
-
60
120
ns
GVOFF to VGHM fall
propagation delay
Tfall
8, 40
-
280
500
ns
DLY1 charge current
Idly1
37
-
6
8
10
µA
DLY1 voltage
threshold
Vdly1
37
-
1.19
1.25
1.31
V
Slider Stop Voltage
Vslide5
33
RDRN = 1 kΩ, Rscan = 1.6 kΩ,
Cscan = 1.3 nF
9.4
10
10.6
V/V
VDET threshold
voltage
VDET
19
VDET
1.275
1.300
1.325
V
VDEThyst
19
VDET
-
50
-
mV
VDET output voltage
VXAO5
7
VDET = GND,
IXAO = 1 mA
-
-
0.4
V
VDET output current
IXAO
7
VDET = 1.5 V, VXAO = 3.3 V
-
-
100
nA
VGHM to ground
discharge resistance
GVOFF to VGHM
rise propagation
delay
VGHM
[Gate Voltage
Shaping]
Symbol
VDET hysteresis
Document Number: 002-08356 Rev. *A
RDRN = 1 k,
VGHM no load, GVOFF
rising edge to VGHM × 0.2
RDRN = 1 k,
VGHM noload, GVOFF
falling edge to VGHM × 0.8
Page 19 of 52
MB39A302
(Ta = 0°C to + 85°C, VIN = IN2 = INVL = 12 V, SUPP = VREF_I = VOP = 17.7 V.
Typical values are at Ta = +25°C unless noted otherwise)
Parameter
VREF
[LDO]
Pin
Value
Condition
Min
Typ
Max
Unit
VREF_I
supply current
IREFI
1
No load,
open loop, VFB = 1.5 V
-
0.15
-
mA
Line regulation
Vline5
48
VREF_I = 13.5 V to 20 V
-
0.02
-
%
Load regulation
Vload5
48
Io = 1 mA to 30 mA
-
0.3
-
%
Threshold voltage
VTH5
47
VREF_FB
- 0.5%
1.25
+ 0.5%
V
Drop out voltage
Vload5
48
IO = 60 mA
VREF_I = VREF_O
-
-
500
mV
-
40
(50 kHz)
50
(500/
750 kHz)
dB
60
100
150
mA
-
3
-
mA
-
0.02
-
%/V
-0.4
-
+0.4
%
PSRR
PSRR5
48
F = 50 KHz/
500 KHz/750 kHz,
Io = 10mA, 30 mA,
VREF_I = Vo5 + 0.7 V,
Reference to VREF_I
Output SCP
protection current
Iscp5
48
VREF_O = 0 V
VOP supply current
IVOP
2
Line regulation
Vline6
6
Load regulation
Vload6
6
Vdrop6
6
IOP = -10 mA
40
90
180
mV
Vdrop6
6
IOP = +10 mA
40
90
180
mV
Unit gain bandwidth
(sourcing)
fu66
6
10
-
MHz
Unit gain bandwidth
(sinking)
fu66
6
20
-
MHz
PSRR
PSRR6
6
60
-
dB
Input offset voltage
Vos6
4, 5
OPO = 6 to 9 V
-15
-
+15
mV
-
40
-
V/µs
-
±200
-
mA
Dropout voltage
(sinking)
Dropout voltage
(sourcing)
VCOM [VCOMP
OPAMP]
Symbol
Buffer configuration,
OPP = OPN = VOP/2,
no load
VOP
13.5 V to 20 V, OPP = 7.5 V
IOP
1 mA to 75 mA, OPP = 7.5 V
Unit gain configuration
Ro = 10 Ω, Co = 0.1 µF,
Io = 75 mA, OPP = 6 V
Unit gain configuration
Ro = 10 Ω, Co = 0.1 µF,
Io = -75 mA, OPP = 6 V
F = 50 KHz/
500 KHz/750 kHz,
Io6 = 10 mA,100 mA dynamic
or Io6 = 30 mA static,
VOP = 8 V,
reference to VOP
Slew rate
Vslew6
-
Ro = 10 Ω, Co = 0.1 µF,
OPP from 6 V ↔ 8 V
Output short circuit
current
Iscp6
6
OPO
[1]: Standard design value
Document Number: 002-08356 Rev. *A
Page 20 of 52
MB39A302
9. Typical Characteristics
Boost Converter (Vs)
Efficiency vs. Load Current
Output Voltage vs. Load Current
100
18.3
500 kHz
95
Output Voltage (V)
Efficiency (%)
90
750 kHz
85
80
75
70
65
18.0
750 kHz
17.7
17.4
500 kHz
60
55
17.1
0
50
0
0.5
1
Load Current (A)
1
1.5
2
Load Current (A)
Load Transient Response
(Switching Load Current = 0.1 A to 1.1 A)
L = 6.8 µH, Freq = 750 kHz
0.5
1.5
Load Transient Response
(Pulsed Load Current = 0.1 A to 1.9 A)
L = 6.8 µH, Freq = 750 kHz
Heavy Load Soft-start
(Load Current = 0.5 A)
L = 6.8 µH, CSS = 22 nF
ILIM1 (ILpeak) vs. RCLIM
ILIM1 (ILpeak) (A)
4.0
3.5
750 kHz
3.0
500 kHz
2.5
2.0
OPEN
200
100
50
RCLIM (kΩ)
Document Number: 002-08356 Rev. *A
Page 21 of 52
MB39A302
Buck Converter (Vlogic)
Efficiency vs. Load Current
Output Voltage vs. Load Current
90
3.45
Efficiency (%)
80
Output Voltage (V)
500 kHz
85
750 kHz
75
70
65
60
3.39
500 kHz
3.33
3.27
750 kHz
3.21
55
3.15
50
0
0
0.5
1
1.5
0.5
1
1.5
Load Current (A)
Load Current (A)
Load Transient Response
(Switching Load Current = 0.3 A to 1.8 A)
L = 10 µH, Freq = 750 kHz
Document Number: 002-08356 Rev. *A
Heavy-load Soft-start
(Load Current = 1 A)
L = 10 µH, Freq = 750 kHz
Page 22 of 52
MB39A302
Negative Charge-pump (VGL)
Normalized Line Regulation
Output Voltage vs. Load Current (VIN = 12 V)
0.10%
2.0
1.5
Output Voltage Erorr (%)
VGL Error (%)
0.05%
IVGL=0mA
0.00%
IVGL=25mA
-0.05%
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-0.10%
8
10
12
14
0
16
50
100
150
200
250
Load Current (A)
SUPN Voltage (V)
Load Transient Response
Positive Charge-pump (VGH)
(Switching Load Current = 10 mA to 60 mA)
Normalized Line Regulation
2
VGH Error (%)
1
Io=0A
0
Io=25mA
-1
-2
12
13
14
15
16
17
SUPP Voltage (V)
18
Positive Charge-pump (VGH)
Load Transient Response
Output Voltage vs. Load Current
(Switching Load Current = 10 mA to 60 mA)
Output Voltage Error (%)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
50
100
150
Load Current (mA)
Document Number: 002-08356 Rev. *A
Page 23 of 52
MB39A302
Low Dropout regulator (LDO)
Line Regulation (Load Current = 20 mA)
Output Voltage vs. Load Current
17.4
16
17.2
14
Output Voltage (V)
Output Voltage (V)
18
17.0
16.8
12
10
8
6
4
2
16.6
17
0
18
17.5
0
50
100
150
VREF_I Voltage (V)
Load Current (mA)
Op-amp (VCOM)
Output Voltage vs. Load Current (Source)
Output Voltage vs. Load Current (Sink)
19
Output Voltage (V)
8
Output Voltage (V)
6
4
2
17
15
13
11
9
7
0
0
50
100
150
200
Load Current (mA)
Rail-to-rail Input / Output Waveforms
Document Number: 002-08356 Rev. *A
250
0
-50
-100 -150 -200
Load Current (mA)
-250
Load Transient Response
Page 24 of 52
MB39A302
Large-signal Step Response
Small-signal Step Response
Switching Frequency vs. Input Voltage
Power-up Sequence of All Supply Outputs
800
Frequency (kHz)
775
750
725
700
8
10
12
14
Input Voltage Vin (V)
16
Gate Voltage Shaping (VGHM)
(VGHM with 470 pF Load)
Document Number: 002-08356 Rev. *A
Page 25 of 52
MB39A302
Switching Frequency vs. Input Voltage
VIN Supply Current vs. VIN Voltage
7
INVL Current (mA)
Frequency (kHz)
800
775
750
725
700
8
10
12
14
16
Input Voltage Vin (V)
All Output Swicthing
6
5
4
Buck Output Swicthing
3
2
No Output Swicthing
1
0
8
10
12
14
16
Input Voltage (V)
Reference Voltage Load Regulation
1.270
Reference Voltage (V)
1.265
1.260
1.255
1.250
No Switching
1.245
1.240
1.235
Switching
1.230
0
50
100
150
Load Current (uA)
Document Number: 002-08356 Rev. *A
200
Page 26 of 52
MB39A302
Power Dissipation PD (W)
Power Dissipation vs. Operating Ambient Temperature
Operating Ambient Temperature Ta (°C)
Document Number: 002-08356 Rev. *A
Page 27 of 52
MB39A302
10. Setup
10.1 Setting Control Pin
Pin
Channels
Vlogic: Buck Converter
VGL: Negative Charge Pump
VS: Boost Converter
VGH: Positive Charge Pump
VREF_O: LDO
OPO: VCOMP OP
IN2, INVL
EN
Standby
operating
L
>6V
L
H
10.2 Setting Switching Frequency
Pin
FSEL
Setting
H/Float
L
Internal oscillator frequency
750kHz
500kHz
10.3 Protection Circuitry
1. IC
Under voltage lock out protection: VIN ≤ 6 V, all circuits shut down.
Over temperature protection: Junction Temp > +150°C, all circuits shut down.
2. VS: Boost converter
Over voltage protection: GD_I pin ≥ 21.5 V, protection circuit active
Over current protection: threshold value is set by user
Short circuit protection: FB1 pin voltage < 1 V for 50 ms or FB1 pin voltage < 0.5 V, protection circuit active. Boost, VGH,
VGL are turned off (stop switching) immediately. External GDFET open.
Startup short circuit protection: If VS short to ground before power on, IC would trigger protection as VIN is pulled low and
disable all channels immediately.
3. VLOGIC: Buck converter
Over voltage protection: OUT > 3.7 V, protection circuit active
Over current protection: ILX2 > 3.2 A, protection circuit active
Short circuit protection: FB2 pin voltage < 1 V for 50 ms or FB2 pin voltage < 0.5 V, protection circuit active. Buck, Boost,
VGH, VGL are turned off (stop switching) immediately. External GDFET open.
4. VGL: Negative Charge Pump
Short circuit protection: REF-FBN voltage < 0.8 V for 50 ms or REF-FBN voltage < 0.4 V, protection circuit active. Boost,
VGH, VGL are turned off (stop switching) immediately. External GDFET open.
5. VGH: Positive Charge Pump
Short circuit protection: FBP pin voltage < 1 V for 50 ms or FBP pin voltage < 0.5 V, protection circuit active. Boost, VGH,
VGL are turned off (stop switching) immediately. External GDFET open.
Power down: When XAO is pulled low, VGHM is shorted to VGH internally.
6. VREF_O: LDO
Short current protection: Io > 100 mA, protection circuit active.
7. VCOM: VCOMP OP
Over current protection: Io > 200 mA, protection circuit active.
Document Number: 002-08356 Rev. *A
Page 28 of 52
MB39A302
11. Application Note
Boost Converter Design
Boost Converter Block Diagram
Output voltage selection
The Boost converter output voltage VS can be set by external resistor divider as below:
VS = 1.25 × (1+
R3
R4
)
Feedback resistor
Resistor values R3 and R4 do not have direct impact on compensation. However, to minimize noise pickup on FB1 without
degrading light load efficiency, it is recommended that the equivalent values be set around 100 kΩ.
Compensation (COMP) Capacitor Selection
The regulator compensation is adjusted by an external component connected to the COMP-pin. This pin is the output of internal
trans-conductance error amplifier. By adding a resistor in series will change the internal zero to achieve a stable mid-frequency gain.
The formula below give the frequency (Fz) at which the resistor increases the high-frequency gain.
FZ =
1
2 × π × CC × (RC+115 k)
For 6.8 μH inductor & 60 μF output capacitor, we recommend using Cc = 680 pF and Rc = 30 kΩ, resulting in fz = 1.5 kHz.
Document Number: 002-08356 Rev. *A
Page 29 of 52
MB39A302
Over current protection selection
The Over current protection for the Boost converter limits the maximum switching current I SWMAX. The current limit value can be
programmed by an external resistor RCLIM.
ILIM1 = 3.5 -
60.5 k
RCLIM
When RCLIM is open, the OCP will set to ILIM1 = 3.5 A. It is recommended that RCLIM be > 60 kΩ.
Peak inductor current
It is necessary to verify the maximum output current of this converter whether it meets the application requirements. The efficiency
of the Boost converter can be read from the graph or employ a worst-case assumption of 80%.
Duty cycle: D = 1 -
Vin × η
Vs
Maximum output current: ISmax = (1-D) × (ISWLIM =
Vin
Vs
× (ISWLIM -
Peak switching/inductor current: ISWMAX =
Vin × D
2 ×fosc × L
Vin × D
)
2 ×fosc × L
Vin × D
2 × fosc × L
+
)
ISmax
1-D
Where:
D = Duty cycle
fosc = Switching frequency [Hz] (500 kHz or 750 kHz)
L = Inductor value [H]
η = Estimated Boost converter efficiency (typically 80% minimum)
ISWLIM = Minimum switch current limit of LX1-pin [A] (= 2.8 A)
ISmax = Maximum output current possible under minimum switch current limit of LX1-pin [A]
The selected components, including the embedded switch, the inductor and external Schottky Diode must be able to handle the
peak switching current. The estimation should be based on the minimum input voltage, since the switching current will be the
highest in this case.
Inductor Selection
Typical inductor value is 6.8 μH. When selects the inductor, chooses an inductor that has saturation current higher than the peak
switch current (ISWMAX) as calculated below. Extra margin is required to cope with high current transients. A more conservative
design is to use the maximum SW current limit of 4.2 A as saturation current rating of inductor. Another parameter for choosing
inductor is the DC resistance. Usually, lower the DC resistance can result in higher converter efficiency.
Document Number: 002-08356 Rev. *A
Page 30 of 52
MB39A302
Rectifier Diode Selection
Schottky diode should be used to attain high efficiency. The reverse voltage rating of the diode must be higher than the maximum
output voltage of the converter. The required averaged rectified forward current of the Schottky diode is the product of off-time of
Boost converter and the maximum switch current at LX1 pin. The peak rectifier forward current is the same as inductor peak current,
Iswmax, determined above.
Off-time of Boost converter: D’=1-D =
Vin
Vs
Average rectifier forward current: IDmax = Ismax × D’
The rectifier diode selected must have average current rating exceeding I Dmax and repetitive peak current rating exceeding Iswmax.
A Schottky diode with maximum rectified forward-current of 2 A should be sufficient for most applications. Another requirement for
Schottky diode is the power dissipation. The power dissipation can be calculated from the formula below:
PD = IDMAX × VF = (1-D) × (ISWLIM -
Vin × D
2 × fosc × L
) ×VF
Where:
PD = Power dissipation of the diode [W]
VF = Diode forward voltage [V]
ISWLIM = Minimum over current protection of LX1-pin [A] (3A)
Output Capacitor Selection
Capacitors with low ESR are recommended. Ceramic capacitor which has low ESR is particularly suitable for this purpose. Typically,
six 10 µF ceramic capacitors connected in parallel are placed at the converter output. More capacitance can be added so as to
reduce voltage drop during heavy load transients.
Soft Start Capacitor Selection
SS pin capacitor is used for defining the soft start time of Boost converter. The Boost converter soft start time, Tss, is determined by
the user when SS pin capacitor value, Css, is higher than 220 pF. And the Boost converter soft start time is determined internally
when SS pin capacitor value is lower than 220 pF or SS pin is open and fixed at 10ms.
CSS ≤ 220 pF
CSS > 220 pF
TSS = 10 ms
TSS = CSS × 1.25/5u
Document Number: 002-08356 Rev. *A
Page 31 of 52
MB39A302
Buck Converter Design
Buck Converter Block Diagram
Output voltage selection
The Buck converter output voltage Vlogic can be set by external resistor divider as below:
Vlogic = 1.25× (1+
R1
R2
)
Softstart
Internal preset.
The soft start starts after internal POR and UVLO checks are completed and the duration is set to 3 ms.
Rectifier Diode Selection
Schottky diode should be used to attain high efficiency. The reverse voltage rating of the diode must be higher then the maximum
output voltage of the converter. The required averaged rectified forward current of diode is the product of off-time of Buck converter
and the maximum switch current at SWB pin.
Off-time of Buck converter: D' = 1-
Vout
Vin
= 1-D
Maximum output current: Iavg = (1-D) × ISWLIM = (1-
Document Number: 002-08356 Rev. *A
Vin
Vout
) × ISWLIM
Page 32 of 52
MB39A302
A Schottky diode with maximum rectified forward-current of 1.5 A to 2 A should be sufficient for most of applications. The diode
forward voltage should be less than 0.7 V in order to prevent damage to IC. Another requirement for Schottky diode is the power
dissipation. The power dissipation can be calculated from the formula below:
PD = Iavg × VF = (1 - D) × ISWLIM × VF
Where:
PD = Power dissipation of the diode [W]
VF = Diode forward voltage [V]
ISWLIM = Minimum over current protection of SWB-pin [A] (2.5 A)
Feedforward capacitor selection
A feed forward capacitor (Cff1) is added parallel to the upper resistor (R1). The Cff1 sets a zero in the transfer function. This will
improve the load transient response and stabilize the converter loop. The value of Cff1 is depending on the value of output inductor
and capacitor used.
For 10 µH inductor & 20 µF output capacitor, a double pole, fLC, is formed at 11 kHz. For stability, a zero, fz, is recommended to be
placed at approximately 70% of fLC = 8 kHz;
Cff =
1
2 × π × R1 × fZ
=
1
2 × π × 2 kΩ × 8 kHz
= 9.9 nF ≈ 10 nF
A capacitor value close to the calculated value is chosen.
A small capacitor to ground, Cfb2, can be added to FB2 node to filter out high frequency noise on the FB2 node. Ensure the low
pass filtering pole formed by this R2 and Cfb2 is >> 200 kHz to not impact system stability.
Inductor Selection
Typical inductor value is 10 μH. The current flow through the inductor must be below the saturation current rating of the inductor.
The maximum current flowing through the inductor can be found from the following formula:
ILMAX ≥ IOMAX +
ΔIL =
Vin - Vout
L
ΔIL
2
×
Vout
Vin × fosc
Where:
ILMAX = Maximum current through inductor [A]
IOMAX = Maximum load current [A]
ΔIL = Inductor ripple current peak-to-peak value [A]
Vin = Input voltage [V]
Vout = Output voltage [V]
fosc = Switching frequency [Hz] (500 kHz or 750 kHz)
Document Number: 002-08356 Rev. *A
Page 33 of 52
MB39A302
Bootstrap Capacitor Selection
Bootstrap capacitor connected to BST pin is charged by integrated synchronous diode with 4.5 V internal supply. Ceramic capacitor
is recommended for less leakage current.
0.1 µF bootstrap capacitor is recommended for Buck converter in MB39A302. The bootstrap capacitor voltage rating is suggested to
be higher than input voltage.
Output Capacitor Selection
This IC is designed to work best with ceramic output capacitor. Two 10 μF ceramic output capacitors are recommended for most
application. More capacitance can be added so as to reduce voltage drop during load transients.
Negative Charge Pump Design
Negative Charge Pump Block Diagram
Output Voltage Selection
Recall from functional description, the maximum negative output voltage is - VDRN + 2Vdiode ideally, which is -12V + 0.8V = -11.2V.
Similar to Positive Charge Pump, the regulated output voltage can be set by equation below:
VGL= 0.25 -
R5
R6
Pumping Capacitor and Output Capacitor Selection
Selection of pumping capacitor and output capacitor are similar to Positive Charge Pump design.
For -5V output, ΔVDRN = |-VGL|-Vdiode = 5 V - 0.4 V = 4.6 V. The pumping capacitor and output filtering capacitor can be estimated for
required application.
The minimum pumping capacitor is determined by following equation.
C≥
Iout
f × ΔVDRN
,
Where:
Iout = The output current
f = Switching frequency (750 kHz/500 kHz)
ΔVDRN = Pumping clock voltage
Document Number: 002-08356 Rev. *A
Page 34 of 52
MB39A302
The charge stored on pumping capacitor is transferred to output capacitor cycle-by-cycle. Output capacitor determines output ripple
voltage of charge pump. The ripple voltage is estimated by:
Vripple =
Iout
+ Iout × ESRCout
2f × Cout
Where:
Cout=Output filtering capacitance
ESRCout = Equivalent series resistance of output filtering capacitor
A small capacitor, Cfbl, can be added between FBN and REF node to filter out high frequency noise on the FBN node. A 22 pF
capacitor is suitable for most applications.
Positive Charge Pump Design
Positive Charge Pump Block Diagram
D
29
<< CH4 (Positive Charge Pump) >>
Cfbp
R7 FBP
38
R8
L priority
Error
Amp4
1.25V
enb4
Current
Control
Logic
Vth
(1.25V±2%)
Ron=(4Ω
at
VGS=5V)
DRV
SUPP
34
B
DRVP
36
Ron=(1Ω
at VGS=5V)
CPGND
35
D
VGH
(30.2V/250mA)
timer
ppg
Clk
1V
0.5V
1.1V
Output Voltage Selection
Theoretically, the maximum output voltage is the sum of input voltage and pumping clock voltage of a charge pump. In MB39A302,
the maximum output voltage is VS (Boost converter output voltage) + VSUP – 2 Vdiode which is 17.7 V + 17.7 V – 2 (0.4 V) = 34.6 V
with typical setting. Due to the regulated voltage control, the output voltage can be configured by equation below:
VGH = Vref × (1+
R7
R8
) = 1.25 × (1+
Document Number: 002-08356 Rev. *A
R7
R8
)
Page 35 of 52
MB39A302
Pumping Capacitor and Output Capacitor Selection
Ceramic capacitor is recommended for its non-polarized, more stable over temperature, low leakage and small ESR. Choosing a
pumping capacitor should consider the required voltage rating and output current loading. For 30.2 V output voltage setting, the
pumping clock voltage is calculated below.
ΔVDRP = VGH - VS + Vdiode = 30.2 V - 17.7 V + 0.4 V = 12.9 V
The minimum pumping capacitor is determined by following equation.
C≥
Iout
f × ΔVDRP
,
Where:
Iout = The output current
f = Switching frequency (750 kHz/500 kHz)
ΔVDRP = Pumping clock voltage
The charge stored on pumping capacitor is transferred to output capacitor cycle-by-cycle. Output capacitor determines output ripple
voltage of charge pump. The ripple voltage is estimated by:
Vripple =
Iout
+ Iout × ESRCout
2f × Cout
Where:
Cout = Output filtering capacitance
ESRCout = Equivalent series resistance of output filtering capacitor
A small capacitor, Cfbp, can be added between FBP and GND node to filter out high frequency noise on the FBP node. A 22pF
capacitor is suitable for most applications.
Low Dropout Regulator Design (LDO)
Low Dropout Regulator Block Diagram
<<CH5 (LDO)>>
E
R9
Current
sense
Vth
1.25V±0.5%
Error
Amp5
VREF_FB
47
B
VREF_I (Vs)
1
Drive r
R10
E
1.25V
VREF_O
48
VREF
(17V/60mA)
MB39A302 includes a voltage regulator (Low Dropout Regulator, LDO) to supply the Gamma Buffer with a very stable voltage. The
LDO is designed to operate typically with a 4.7 μF ceramic output capacitor (any value between 1 μF and 10 μF works properly) and
a ceramic bypass capacitor of minimum 1 μF on its input VREF_I connected to ground. The output of the Boost converter VS is
usually connected to the input VREF_I. The LDO has an internal soft-start feature to limit the inrush current.
Output voltage selection
The Boost converter output voltage can be set by external resistor divider as below:
Vref_o = 1.25 × (1+
R9
R10
)
Document Number: 002-08356 Rev. *A
Page 36 of 52
MB39A302
VCOM Operational Amplifier
VCOM Operational Amplifier Block Diagram
The operational amplifier use Vs for power supply, to get better performance and smaller output noise, a 1 μF filter ceramic
capacitor should be placed between VOP and GND. The input pin OPP can either feed by a resistor divider from VREFO or an
external voltage reference. This operational amplifier is optimized to drive the LCD backplane (VCOM), so it is not stable to drive a
pure capacitor load, but series a 3 to 10 Ω small resistor with the load capacitor will provide the stable operation.
VGHM: Gate Voltage Shaping
Gate Voltage Shaping Block Diagram
XAO
7
Rdt
VDET
<< Gate Voltage Shaping >>
19
VGH
Rdb
GVOFF
VGH
39
1.25V
8
CH4pg
DLY1
37
Control
Logic
VGHM
VGHM
40
1k
1.25V
DRN
41
THR
33
Clamp
DLY1 Capacitor Selection
Refer to "Power Up Sequence" section, Gate Shape block power up sequence timing is set by capacitor at DLY1 pin. The delay
capacitor can be estimated by following equation.
Cdelay =
8 μA × tdelay
Vref
Where:
tdelay = Delay time
Cdelay = Capacitor connected to DLY1-pin
Vref = 1.25 V
Document Number: 002-08356 Rev. *A
Page 37 of 52
MB39A302
XAO
The XAO threshold, VINpg, can be set via a VIN resistive divider connecting to on the VDET pin.
If we select Rdb in the 10 kΩ to 50 kΩ range, then Rdt can be determined as:
Rdt
Rdb
=
VINpg
1.25V
-1
Where VINpg is the desired XAO threshold level. Note that Rdt and Rdb should be placed close to the IC.
XAO pin is open drain. Please ensure it is pull up to 3.3 V or 5.2 V supply.
VDET pin threshold voltage is 1.25 V typically. When using Gate voltage shaping and XAO output, please set 1.25 V < VDET < 3.7 V.
When not using Gate voltage shaping and XAO output, please set VDET pin to ground.
Others
Input capacitor Selection
It is recommended to use low ESR capacitor like ceramic capacitor for the input filtering. For INVL terminal, a 1 µF capacitance
connected from INVL to ground is needed. For the Buck converter, use typically four 10 µF and one 0.1 µF ceramic capacitors
connected from IN2 pin to ground.
Output capacitor Selection
Similarly, ceramic capacitors are recommended. For VL pin, a 1 µF capacitance connected from VL to ground is recommended. For
REF pin, a 1 µF capacitance connected from VL to ground is recommended.
PCB Layout Recommendation
PCB layout is significant for power supply design. Poor layout would result in generating unwanted voltage and current spikes. This
will not only affect DC output voltage, but also radiate EMI to adjacent equipment. Sufficient grounding and minimize parasitic
inductance can reduce DC/DC converter switching spike noise.
Document Number: 002-08356 Rev. *A
Page 38 of 52
TP16
GND
TP6
VCOM
TP21
OPO
RP61
EVM3ESX50BE3
TP10
GVOFF
C60 0.1uF/25V/10%
R21
5
R60 0R/0603/1% OP_IN-
C62 1uF-150uF/20V/10%
C24 10uF/25V/10%
TP18
GND
C23 10uF/25V/10%
R4
0R/0805/1%
R5 62K/0603/1%
VIN
VIN
VIN
R11 200K/0603/1%
TP8
VIN
GND
R26 NC C26 NC
MB39A302
TP12
GND
TP2
VO2(Vlogic)
VLOGIC
L2 10uH
R24 0R/0603/1%
JP1
12
OUT
FB2
EN
GVOFF
XAO
OPO
OPN
OPP
OGND
D2
C21
10nF/50V/10%
0R/0603/1%
R20
NC
11
10
9
8
7
OP_OUT 6
4
OP_IN+
OP_GND 3
VOP
VREF
C32
22pF/50V/5%
C71
R8
3
2
1
JP2
LX1_1
LX1_2
PGND_1
PGND_2
GD_I
GD
FB1
COMP
THR
SUPP
CPGND
DRVP
25
26
27
28
29
30
31
32
33
34
35
36
VGH
TP7
VGHM
TP17
GND
TP4
VO4(VGH)
LX1
TP14
GND
D1
MBRA340T3
C17
NC
C16
10nF/50V/10%
680 pF /50V/10%
L1 6.8uH
R7 0R/0603/1%
AVDD_FB
C40
1uF/50V/10%
C7 NC
R17 30.9K/0603/1%
C15
C41
0.47uF/25V/10%
AVDD_THR
C70
10nF/50V/10%
1.5nF/50V/5% 1.61K/0603/1%
VGH_FB R78 0R/0603/1%
C11
C22
68pF/50V/10%
R3
1
U1
27.4R/0603/1%
R53 0R/0603/1% OP_VCC 2
VLOGIC R2 0R/0603/1%
VL
VO1(Vs)
R54 0R/0603/1% LDO_IN
R1 1K/0603/1%
R63 10K/0603/1%
TP22
XAO
VLOGIC
R62 10R/1206/1%
C53 NC
10.5K/0603/1% 806R/0603/1%
MBR0540T1
D31
C80 10uF/25V/10%
R22
0R/0603/1%
TP20
REF
R55
MBR0540T1
D30
C81 10uF/25V/10%
19.6R/0603/1% 1.2K/0603/1% 2K/0603/1%
R23
TP9
OPP_IN
VREF R65 0R/0603/1%
TP15
GND
TP5
LDO(VREF)
R51
49
PGND
R50
LX2_1
R56
VREF_O
48
0R/0603/1% 604K/0603/1%
LX2_2
47
VREF_FB
VREF
1
2
3
R61
15.8K/0603/1%
13
C61 1uF/50V/10%
14
C50
10uF/25V/10%
15
TP13
GND
BST
46
REF
42
R32
IN2_1
45
FBN
41
R31
IN2_2
44
GND2
43
AGND
Document Number: 002-08356 Rev. *A
C55
0.1uF/25V/10%
16
C54
1uF/50V/10%
17
LDO_OUT
18
R64
19.6K/0603/1%
DRVN
C51 NC
VDET
10uF/25V/10%
40
10uF/25V/10%
39
C34
38
47K/0603/1%
VGHM
C35
C33 1uF/50V/10%
FSEL
R34
R35
0R/0603/1%
37
C31 0.47uF/25V/10%
19
D41 MBR0540T1
22
C30 1uF/50V/10%
FBP
1.5K/1206/1%
SUPN
R73
INVL
1.5K/1206/1%
R72
VGH
R33
105K/0603/1%
C46
0.47uF/25V/10%
LDO_+5V_VCC 20
R74 NC
DRN
R75 NC
VL
R76 NC
4
3
2
1
R12
0R/0805/1%
5
G
D1 6
S3 D2 7
S2 D3 8
S1 D4
AM4835P
TP19
VBST
Q1
Default X2
X2
D42
MBR0540T1
VIN
JP3
Q2
AO3403/NC
D40
MBR0540T1
X3
VO1(Vs)
D43
MBR0540T1
VLOGIC
20.5K/0603/1%
R42
0R/0603/1%
R45
VGH_FB C44 22pF/50V/5%
VO1(Vs)
R71
R79
340K/0603/1% 9.76K/0603/1% 120R/0603/1%
AVDD_THR
0R/0603/1%
R13
TP1
VO1(Vs)
TP11
GND
LX1
C47 0.47uF/25V/10%
R41
475K/0603/1%
R44 NC
3
2
1
R40
0R/0603/1%
R43 0R/0603/1%
C45
0.47uF/25V/10%
VLLDO_+5V 21
R77 NC
DLY1
R46
47K/0603/1%
CLIM
C43 NC
SS
C42
1uF/50V/10%
R70
Current Limit 23
AVDD_FB
C18 NC
24
VGH
TP3
VO3(VGL)
MB39A302
12. Circuit Diagram
MB39A302 EVB-01 Rev2.0
R14
R15
R16
392K/0603/1% 29.4K/0603/1% 383R/0603/1%
R19 47K/0603/1%
C86 10uF/25V/10%
C85 10uF/25V/10%
C84 10uF/25V/10%
C83 10uF/25V/10%
C82 NC
C14 10uF/25V/10%
C13 10uF/25V/10%
C12 10uF/25V/10%
R18 NC C19 NC
22nF/50V/10%
C52 1uF/50V/10%
C2 1uF/16V/10%
R52 0R/0603/1%
R6 10K/0603/1%
C20 0.1uF/25V/10%
MBRA340T3
C1 0.1uF/25V/10%
C6 10uF/25V/10%
R25 47K/0603/1%
C5 10uF/25V/10%
C25 NC
C4 10uF/25V/10%
C3 10uF/25V/10%
Page 39 of 52
MB39A302
Part List
Count
Designator
1
U1
4
C1, C20,
C55, C60
1
C2
18
1
1
2
1
7
5
2
1
1
1
2
6
3
Item Specification
C3, C4, C5, C6,
C12, C13, C14,
C23, C24, C34, 3216, 10%, X5R, 25 V,
C35, C50, C80, 10 µF
C81, C83, C84,
C85, C86
1608, 10%, X7R, 50 V,
C11
22 nF
1608, 5%, NPO, 50 V,
C15
680 pF
1608, 10%, X7R, 50 V,
C16, C21
10 nF
1608, 5%, NPO, 50 V,
C22
68 pF
C30, C33,
3216, 10%, X7R, 50 V,
C40, C42, C52,
1 µF
C54, C61
C31, C41, C45, 3216, 10%, X7R, 50 V,
C46, C47
470 nF
1608, 5%, NPO, 50 V,
C32, C44
22 pF
3216, 10%, X7R, 50 V,
C62
1 µF
1608, 10%, X7R, 50 V,
C70
10 nF
1608, 10%, X7R, 50 V,
C71
1.5 nF
Diode, Schottky
D1, D2
Rectifier, 3 A, 40 V
D30, D31, D40, Diode, Schottky,
D41, D42, D43 500 mA, 40 V
JP1, JP2, JP3
Part Value
IC, Power supply of
MB39A302
LCD panel
1608, 10%, X7R, 50 V,
0.1 µF
100 nF
1608, 20%, X5R, 16 V,
1 µF
1 µF
Jumper
Inductor, SMT, 4.4 A,
35 mΩ
Inductor, SMT, 4.4 A,
35 mΩ
Package
Part number
Vendor
Description
QFN-48
MB39A302
Cypress
Power IC
0603
CC0603KRX7R9BB104
Yageo
Capacitor
0603
CC0603KRX5R7BB105
Yageo
Capacitor
10 µF
1206
CC1206KKX5R8BB106
Yageo
Capacitor
22 nF
0603
CC0603KKX7R9BB223
Yageo
Capacitor
680 pF
0603
CC0603JRNPO9BN681
Yageo
Capacitor
10 nF
0603
CC0603KRX7R9BB103
Yageo
Capacitor
68 pF
0603
CC0603JRNPO9BN680
Yageo
Capacitor
1 µF
1206
CC1206KKX7R9BB105
Yageo
Capacitor
0.47 µF
1206
CC1206KKX7R9BB474
Yageo
Capacitor
22 pF
0603
CC0603JRNPO9BN220
Yageo
Capacitor
1 µF
1206
CC1206KKX7R9BB105
AVX
TanCapacitor
10 nF
0603
CC0603KRX7R9BB103
Yageo
Capacitor
1.5 nF
0603
CC0603KRX7R9BB152
Yageo
Capacitor
MBRA340T3G
SMA-403D MBRA340T3
OnSemi
Diode
MBR0540T1G
SOD-123
MBR0540T1G
OnSemi
MBR0540T1G
-
HDR1X3
Standard
-
HEADER1X3
6.8 µH
10.3×10.5
SDCS104R-6R8
Chilisin
Inductor
10 µH
10.3×10.5
SDCS104R-100
Chilisin
Inductor
1
L1
1
L2
1
Q1
MOSFET P-ch
AM4835P
SO-8
AM4835P
Analog
Power
MOSFET P-ch
1
RP61
Potentiometer,chip,
1%
EVM3ESX50BE3
Standard
EVM3ESX50BE3
Panasonic
Potentiometer
1
R1
Resistor, Chip, 1%
1K
0603
RC0603FR_1KL
Yageo
Resistor
8
R2, R35, R43,
R53, R54, R60,
R65, R78
Resistor, Chip, 1%
0R
0603
RC0603FR_0RL
Yageo
Resistor
1
R5
Resistor, Chip, 1%
62 K
0603
RC0603FR_62KL
Yageo
Resistor
2
R6, R63
Resistor, Chip, 1%
10 K
0603
RC0603FR_10KL
Yageo
Resistor
1
R8
Resistor, Chip, 1%
1.61 K
0603
RC0603FR_1K61L
Yageo
Resistor
1
R11
Resistor, Chip, 1%
200 K
0603
RC0603FR_200KL
Yageo
Resistor
1
R14
Resistor, Chip, 1%
392 K
0603
RC0603FR_392KL
Yageo
Resistor
1
R15
Resistor, Chip, 1%
29.4 K
0603
RC0603FR_29K4L
Yageo
Resistor
Document Number: 002-08356 Rev. *A
Page 40 of 52
MB39A302
Count
Designator
Item Specification
Part Value
Package
Part number
Vendor
Description
1
R16
Resistor, Chip, 1%
383R
0603
RC0603FR_383RL
Yageo
Resistor
1
R17
Resistor, Chip, 1%
30.9 K
0603
RC0603FR_30K9L
Yageo
Resistor
4
R19, R25,
R34, R46
Resistor, Chip, 1%
47 K
0603
RC0603FR_47KL
Yageo
Resistor
1
R21
Resistor, Chip, 1%
2K
0603
RC0603FR_2KL
Yageo
Resistor
1
R22
Resistor, Chip, 1%
1.2 K
0603
RC0603FR_1K2L
Yageo
Resistor
1
R23
Resistor, Chip, 1%
19.6 R
0603
RC0603FR_19R6L
Yageo
Resistor
1
R32
Resistor, Chip, 1%
604 K
0603
RC0603FR_604KL
Yageo
Resistor
1
R33
Resistor, Chip, 1%
105 K
0603
RC0603FR_105KL
Yageo
Resistor
1
R41
Resistor, Chip, 1%
475 K
0603
RC0603FR_475KL
Yageo
Resistor
1
R42
Resistor, Chip, 1%
20.5 K
0603
RC0603FR_20K5L
Yageo
Resistor
1
R45
Resistor, Chip, 1%
0R
0603
RC0603FR_0RL
Yageo
Resistor
1
R50
Resistor, Chip, 1%
10.5 K
0603
RC0603FR_10K5L
Yageo
Resistor
1
R51
Resistor, Chip, 1%
806R
0603
RC0603FR_806RL
Yageo
Resistor
1
R55
Resistor, Chip, 1%
27.4R
0603
RC0603FR_27R4L
Yageo
Resistor
1
R61
Resistor, Chip, 1%
15.8 K
0603
RC0603FR_15K8L
Yageo
Resistor
1
R62
Resistor, Chip, 1%
10R
1206
RC1206FR_10RL
Yageo
Resistor
1
R64
Resistor, Chip, 1%
19.6 K
0603
RC0603FR_19K6L
Yageo
Resistor
1
R70
Resistor, Chip, 1%
340 K
0603
RC0603FR_340KL
Yageo
Resistor
1
R71
Resistor, Chip, 1%
9.76 K
0603
RC0603FR_9K76L
Yageo
Resistor
2
R72, R73
Resistor, Chip, 1%,
1/4 W
1.5 K
1206
RC1206FR_1K5L
Yageo
Resistor
1
R79
Resistor, Chip, 1%
120R
0603
RC0603FR_120RL
Yageo
Resistor
Connecting pins
-
-
-
-
Pins
Connecting pins
-
-
-
-
Test Pad
-
-
-
-
-
Capacitor
1206
CC1206KKX5R8BB106
Yageo
Capacitor
1206
CC1206KKX7R9BB105
Yageo
Capacitor
TP1, TP2, TP3,
TP4, TP5, TP6,
TP7, TP8, TP9,
TP10, TP11,
19
TP12, TP13,
TP14, TP15,
TP16, TP17,
TP18, TP19
TP20, TP21,
3
TP22
Not
C7, C17, C18,
Mounted C19, C26, C53
Not
C25, C51, C82
Mounted
Not
C43
Mounted
Not
R3, R44
Mounted
Not
R18, R26
Mounted
Not
R74, R75, R76,
Mounted R77
Not
Q2
Mounted
Pattern
R4, R12
Short
R7, R13, R20,
Pattern
R24, R31, R40,
Short
R52, R56
3216, 10%, X5R, 25 V,
10 µF
10 µF
3216, 10%, X7R, 50 V,
1 µF
1 µF
Resistor, Chip, 1%
0R
0603
RC0603FR_0RL
Yageo
Resistor
-
-
-
-
-
Resistor
Resistor, Chip, 1%
1.5 K
1206
RC1206FR_1K5L
Yageo
Resistor
MOSFET P-ch
AO3403
sot23
AO3403
Alpha &
Omega
MOSFET P-ch
-
-
-
-
-
-
-
-
-
-
-
-
Document Number: 002-08356 Rev. *A
Page 41 of 52
MB39A302
Yageo
: YAGEO Corporation
AVX
: AVX Corporation
OnSemi
: ON Semiconductor
Chilisin
: Chilisin Electronics Corp.
AnalogPower
: Analog Power
Panasonic
: Panasonic Corporation
Alpha & Omega : Alpha & Omega Semiconductor
Document Number: 002-08356 Rev. *A
Page 42 of 52
MB39A302
13. Land Pattern
The MB30A302 has an exposed thermal pad zone on the bottom side of the IC. This area has to be soldered onto the PCB board to
enhance heat dissipation.
The via should be placed in the thermal pad. These via assist heat dissipation towards the bottom layer of the PCB. Via and copper
pad size may be adjusted according to PCB constraints.
Document Number: 002-08356 Rev. *A
Page 43 of 52
MB39A302
14. Usage Precaution
Never use setting exceeding maximum rated conditions.
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Use the devices within recommended conditions
It is recommended that devices be operated within recommended conditions.
Exceeding the recommended operating condition may adversely affect devices reliability.
Nominal electrical characteristics are warranted within the range of recommended operating conditions otherwise specified on each
parameter in the section of electrical characteristics.
Design the ground line on printed circuit boards with consideration of common impedance.
Take appropriate static electricity measures.
Containers for semiconductor materials should have anti-static protection or be made of conductive material.
After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
Work platforms, tools, and instruments should be properly grounded.
Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
Do not apply negative voltages.
The use of negative voltages below -0.3 V may activate parasitic transistors on the device, which can cause abnormal operation.
Document Number: 002-08356 Rev. *A
Page 44 of 52
MB39A302
15. Ordering Information
Part number
MB39A302WQN
Packege
Remarks
48-pin plastic QFN
(LCC-48P-M11)
16. EV Board Ordering Information
EV board number
MB39A302-EVB-01
EV board version No.
Remarks
MB39A302 EVB-01 Rev1.2
QFN-48 Exposed PAD
17. RoHS Compliance Information of Lead (Pb) Free Version
The LSI products of Cypress with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium,
mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). A product whose
part number has trailing characters “E1” is RoHS compliant.
18. Marking Format (Lead Free Version)
Lead-free version
INDEX
Document Number: 002-08356 Rev. *A
Page 45 of 52
MB39A302
19. Labeling Sample (Lead Free Version)
Lead-free mark
JEITA logo
The part number of a lead-free product has the
trailing characters "E1".
Document Number: 002-08356 Rev. *A
JEDEC logo
"ASSEMBLED IN CHINA" is printed on
the label of a product assembled in China.
Page 46 of 52
MB39A302
20. MB39A302 Recommended Conditions of Moisture Sensitivity Level
[Cypress Recommended Mounting Conditions]
Item
Condition
Mounting Method
Mounting times
IR (infrared reflow), warm air reflow
2 times
Before opening
From opening to the 2nd reflow
Please use it within two years after manufacture.
Less than 8 days
Please process within 8 days after baking
When the storage period after opening was
(125°C ± 3°C, 24hrs + 2H/-0H)
exceeded
Baking can be performed up to two times.[1]
5°C to 30°C, 70% RH or less (the lowest possible humidity)
Storage period
Storage conditions
[1]: When taping is used as the shipping form, baking should be performed individually.
[Parameters for Each Mounting Method]
1. IR (infrared reflow)
260 °C
255 °C
170 °C
to
190 °C
(b)
RT
(a)
H rank: 260°C Max
(a) Temperature Increase gradient
(b) Preliminary heating
(c) Temperature Increase gradient
(d) Actual heating
(d’)
(e) Cooling
(c)
(d)
(e)
(d')
: Average 1°C/s to 4°C/s
: Temperature 170°C to 190°C, 60s to 180s
: Average 1°C/s to 4°C/s
: Temperature 260°C Max; 255°C or more, 10s or less
: Temperature 230°C or more, 40 s or less
or
Temperature 225°C or more, 60 s or less
or
Temperature 220°C or more, 80 s or less
: Natural cooling or forced cooling
Note : Temperature : the top of the package body
2. JEDEC standard: Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020D)
Document Number: 002-08356 Rev. *A
Page 47 of 52
MB39A302
3. Recommended manual soldering (partial heating method)
Item
Before opening
Storage period
Storage
conditions
Mounting
conditions
Between opening and mounting
Condition
Within two years after manufacture.
Within two years after manufacture.
(No need to control moisture during the storage period because of
the partial heating method.)
5°C to 30°C, 70% RH or less (the lowest possible humidity)
Temperature at the tip of a soldering iron: 400°C max
Time: Five seconds or below per pin[1]
[1]: Make sure that the tip of a soldering iron does not come in contact with the package body.
Document Number: 002-08356 Rev. *A
Page 48 of 52
MB39A302
21. Package Dimensions
Document Number: 002-08356 Rev. *A
Page 49 of 52
MB39A302
22. Major Changes
Spansion Publication Number: MB39A302_DS405-00005
Page
Section
Revision 1.0
Revision 1.1
-
Change Results
Initial release
Company name and layout design change
Note: Please see “Document History” about later revised information.
Document Number: 002-08356 Rev. *A
Page 50 of 52
MB39A302
Document History
Document Title: MB39A302 5ch System Power Management IC for LCD Panel with VCOM Regulator
Document Number: 002-08356
Revision
ECN
Orig. of
Change
Submission
Date
**
–
TAOA
01/31/2014
Migrated to Cypress and assigned document number 002-08356.
No change to document contents or format.
*A
5221925
TAOA
04/19/2016
Updated to Cypress format.
Document Number: 002-08356 Rev. *A
Description of Change
Page 51 of 52
MB39A302
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
®
Products
®
PSoC Solutions
®
ARM Cortex Microcontrollers
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/touch
cypress.com/usb
cypress.com/wireless
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
© Cypress Semiconductor Corporation, 2012-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then
Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code
form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to
end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the
Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation,
or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be
reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from
any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages,
and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the
United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-08356 Rev. *A
April 19, 2016
Page 52 of 52
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