OPTi 82C931
OPTi
®
82C931
Plug and Play
Integrated Audio Controller
Data Book
912-3000-035
Revision: 2.1
August 1, 1997
Copyright
Copyright © 1996, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any
means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Incorporated, 888 Tasman Drive, Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described
and especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further,
OPTi Inc. reserves the right to revise the design and associated documentation and to make changes from time to
time in the content without obligation of OPTi Inc. to notify any person of such revisions or changes.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Incorporated.
All other trademarks and copyrights are the property of their respective holders.
OPTi Inc.
888 Tasman Drive
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
WWW: http://www.opti.com/
82C931
Table of Contents
1.0
Features ............................................................................................................................ 1
2.0
Overview ........................................................................................................................... 3
3.0
Signal Definitions ............................................................................................................. 5
3.1
Mode Selection ................................................................................................................................... 5
3.2
931-MB Mode....................................................................................................................................... 6
3.2.1
3.3
931-AD Mode .....................................................................................................................................12
3.3.1
4.0
931-MB Mode Signal Descriptions ......................................................................................... 8
3.2.1.1 ISA Bus Interface Signals ....................................................................................... 8
3.2.1.2 MIDI Interface Signals............................................................................................. 8
3.2.1.3 Configuration and External PnP EEPROM Interface Signals ................................. 9
3.2.1.4 Game Port and Serial Audio Interface Signals ....................................................... 9
3.2.1.5 Codec/Mixer Interface Signals ..............................................................................10
3.2.1.6 Power and Ground Pins ........................................................................................11
931-AD Mode Signal Descriptions........................................................................................14
3.3.1.1 ISA Bus Signals ....................................................................................................14
3.3.1.2 MIDI Interface Signals...........................................................................................14
3.3.1.3 Configuration, External PnP EEPROM, and IDE CD-ROM Interface Signals.......15
3.3.1.4 Game Port and Modem Interface Signals .............................................................16
3.3.1.5 Codec/Mixer Interface Signals ..............................................................................16
3.3.1.6 Serial Audio Interface Signals ...............................................................................17
3.3.1.7 Power and Ground Pins ........................................................................................17
Functional Description .................................................................................................. 19
4.1
Plug and Play ....................................................................................................................................19
4.2
16-Bit Codec/Mixer ...........................................................................................................................20
4.2.1
Codec ...................................................................................................................................20
4.2.2
Mixer.....................................................................................................................................21
4.3
Frequency Synthesizer ....................................................................................................................22
4.4
16-Bit Type F DMA Playback ...........................................................................................................23
4.5
Modem Interface ...............................................................................................................................23
4.6
Push Button Volume Control...........................................................................................................23
4.7
External Serial EEPROM ..................................................................................................................23
4.8
Serial Audio Interface .......................................................................................................................23
4.8.1
I2S-justified format and its variations....................................................................................23
4.8.2
Sony format ..........................................................................................................................24
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Page iii
82C931
Table of Contents (cont.)
5.0
6.0
AT&T PCM codec T7525 compatible 16-bit mono format ....................................................24
4.8.4
Testing I2S format (ZV port) with Audio Precision machine .................................................24
4.8.5
Relevant MC register settings ..............................................................................................24
4.8.6
ZV-Port I2S...........................................................................................................................25
4.8.6.1 LRCLK ..................................................................................................................25
4.8.6.2 SDATA ..................................................................................................................25
4.8.6.3 SCLK.....................................................................................................................26
4.8.6.4 MCLK ....................................................................................................................26
4.8.7
Advanced Precision General Purpose Serial Port................................................................26
4.8.8
TDA1311 Stereo Continuous Calibration .............................................................................27
Register Descriptions .................................................................................................... 29
5.1
I/O Base Addresses ..........................................................................................................................29
5.2
MCBase Register .............................................................................................................................29
5.3
SBBase Register...............................................................................................................................36
5.4
WSBase Register ..............................................................................................................................37
Electrical Specifications................................................................................................ 45
6.1
Absolute Maximum Ratings.............................................................................................................45
6.2
DC Characteristics: 5.0 Volt (VCC = 5.0V ±5%, TA = 0°C to +70°C)..............................................45
6.3
General Specifications: 5.0 Volt (VCC = 5.0V ±5%, TA = 0°C to +70°C) .......................................46
6.4
Pin Specifications - Analog (VCC = 5.0V, 25×C) ............................................................................47
6.5
Volume Setting..................................................................................................................................47
6.6
Analog Characteristics.....................................................................................................................47
6.7
7.0
4.8.3
6.6.1
Analog Inputs........................................................................................................................48
6.6.2
Analog Outputs (10kW, 25pF) ..............................................................................................48
6.6.3
Volume Settings ...................................................................................................................48
6.6.4
Analog-to-Digital Converters ................................................................................................49
6.6.5
Digital-to-Analog Converters ................................................................................................49
AC Timings ........................................................................................................................................49
Mechanical Packages .................................................................................................... 53
OPTi
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Revision: 2.1
82C931
List of Figures
Figure 1-1
Figure 2-1
Figure 2-2
Figure 3-1
Figure 3-2
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 7-1
Figure 7-2
System Block Diagram .................................................................................................................... 1
Functional Block Diagram................................................................................................................ 3
Data Flow Block Diagram ................................................................................................................ 4
931-MB Mode PQFP Pin Diagram.................................................................................................. 6
931-AD Mode PQFP Pin Diagram .................................................................................................12
Functional Block Diagram..............................................................................................................20
Mixer Block Diagram .....................................................................................................................21
I2S Format .....................................................................................................................................25
General Purpose Serial Port, Timing Relationships ......................................................................26
Format of Input Signals .................................................................................................................27
RESET and CLK Timing Waveform...............................................................................................50
CD-ROM I/O Read Cycle...............................................................................................................51
CD-ROM I/O Write Cycle...............................................................................................................51
DMA Write/Playback Cycle............................................................................................................52
DMA Read/Capture Cycle .............................................................................................................52
100-pin PQFP, Plastic Quad Flat Pack .........................................................................................53
100-pin TQFP, Thin Quad Flat Package .......................................................................................54
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82C931
OPTi
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Revision: 2.1
82C931
List of Tables
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 4-1
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 5-7
Table 5-8
Table 5-9
Table 5-10
Table 5-11
Mode Selection ................................................................................................................................ 5
Mode Features ................................................................................................................................ 5
Signal Definitions Legend ................................................................................................................ 5
931-MB Mode Numerical Pin Cross-Reference List ........................................................................ 7
931-MB Mode Alphabetical Pin Cross-Reference List..................................................................... 7
931-AD Mode Numerical Pin Cross-Reference List ......................................................................13
931-AD Mode Alphabetical Pin Cross-Reference List ...................................................................13
FS Output Frequencies .................................................................................................................22
82C931 I/O Base Addresses .........................................................................................................29
82C931 Register Map....................................................................................................................29
MCBase, Direct MC Register.........................................................................................................30
McBase, Index (MCIndx) and Data (MCData) Ports Address Range............................................30
MCIdx and MCData Registers .......................................................................................................30
MC Indirect Registers ....................................................................................................................31
SBBase Registers for FM and DAP Applications ..........................................................................36
WSBase Registers for Windows Sound System Applications .......................................................37
WSBase Register for Codec/Mixer Applications............................................................................38
Codec Indirect Registers ...............................................................................................................40
Expanded Mode CIR .....................................................................................................................43
OPTi
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912-3000-035
Revision: 2.1
Page vii
OPTi Confidential
82C931
OPTi
®
Page viii
912-3000-035
Revision: 2.1
OPTi
82C931
®
Plug and Play Integrated Audio Controller
1.0
Features
• Integrated sound controller compatible with:
- Sound Blaster Pro™
- Ad Lib™
- Microsoft® Windows™ Sound System™
• Full duplex operation: record and playback simultaneously
using two 8- or 16-bit DMA channels
• Supports IMA ADPCM, µ-law, A-law decompression
• 8- or 16-bit stereo sound data up to 48KHz stereo
• Microsoft® PC-97 compliant
• Built-in high-quality 22 voice, 52 operator, OPTiFM™
music synthesizer with enhanced bass
• Built-in 7-channel mixer: five stereo, two mono
• Built-in 16-bit sigma-delta stereo codec
• ISA Plug and Play Specification 1.0a compatible, supports
a maximum of six logical devices:
- Sound Blaster Pro, Windows Sound System,
FM synthesis
- MPU-401 MIDI interface
- CD-ROM interface
- Joystick/game port
- Modem interface
- 82C931 control
• Supports external serial EEPROM (optional)
• Supports 16-bit Type F DMA playback, accelerates telephony-audio applications
• Digital joystick interface support, improves responsiveness
(Microsoft SideWinder™)
• I2S serial interface supports Zoom Video Port, wavetable
controller and modem chipset
• DirectSound™ interface support
• Power-down modes
• Silence mode to turn-off all audio functions
• Hardware and software volume control via push-button
interface
• 100-pin PQFP (Plastic Quad Flat Pack)
• 100-pin TQFP (Thin Quad Flat Pack)
• External modem chipset interface
Figure 1-1
System Block Diagram
OPTi
82C931
Analog Interface
ISA Bus
Speaker
Line-Out
Line-In
CD Audio
Microphone
IDE CD-ROM Interface
Modem Interface
Joystick Port, MIDI Port
I2S Serial Audio Port
912-3000-035
Revision: 2.1
Page 1
82C931
OPTi
®
Page 2
912-3000-035
Revision: 2.1
82C931
2.0
Overview
The OPTi 82C931 is a single-chip Plug-and-Play audio system controller and codec that provides compatibility with
Sound Blaster Pro™, Microsoft Windows Sound System™,
OPL3, and MPU-401 interfaces. The 82C931 integrates a 16bit stereo sigma-delta codec and PC-97 compliant internal
resource structure. This provides an effective audio solution
for Windows 95 operating systems, DirectSound™, and
advanced audio applications.
MIDI interface, Windows Sound System interface, FM synthesizer interface, 16-bit codec/mixer, game port timer, and
IDE CD-ROM interface. The device also includes dual DMA
channels that support full duplex operation for simultaneous
record and playback, a silence mode, power-down modes,
and software programmable interrupts. (Figure 2-1 shows a
functional block diagram of the 82C931. Figure 2-2 shows the
82C931 data flow block diagram.)
The 82C931 provides front panel push-button volume control,
external modem chip interface, serial EEPROM for further
customizing, support for 16-bit Type F DMA playback and an
The 82C931 Integrated Audio Controller provides all of the
functions and interfaces for Sound Blaster Pro-compatible
and Microsoft Windows Sound System-compatible cards.
The 82C931 is intended to provide an integrated audio solution for business audio, educational/entertainment sound,
and multimedia applications.
I2S serial interface to a Zoom Video Port, wavetable controller, or modem chipset.
The 82C931 includes the following functions: ISA bus interface, Sound Blaster Pro-compatible Digital Audio Processor,
Figure 2-1
Functional Block Diagram
IOW#
IOR#
AEN
RESET
OSCI
SA[15:0]
SD[15:0] or SD[7:0]
SDHOE+GPIO0
DACK0#/1#/3#
DACK5#/6#
DRQ0/1/3
IRQ3/4/5/7/9/10/11/15
GD[7:0]
ISA
Control
WSS
REGS
CLK
GEN
CONF
REGS
8/16-bit Type
DMA Logic
Digital
Audio
Processor
FIFO
MIDI
Interrupt
RXD
UART
FIFO
TXD
Game Port Timer
OPTiFM
OSCI
OSCO
MICL/R
AUXL/R
CDL/R
LINEL/R
OUTL/R
MIXOUTL/R
16-bit Sigma-Delta
Codec/Mixer
VOLUP
VOLDWN
Volume Control
SADI
SADO
SCLK
FSYNC
CD-ROM
Interface
I2S Serial Audio Port
CA[2:0]
IDECS1#
IDECS3#
CDOE#
CDHOE#
XIOR#
XIOW#
RESET#
IDEIRQ
MODEMINT
Modem Interface
MODEMCS#
OPTi
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912-3000-035
Revision: 2.1
Page 3
82C931
Figure 2-2
Note:
Data Flow Block Diagram
There are four signals which are referenced by acronyms to make connections within the block diagram.
HCO = Host Capture Output
HPO = Host Playback Output
FMO = FM Output
SI = Serial In
SO = Serial Out
OPTi
®
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912-3000-035
Revision: 2.1
82C931
3.0
Signal Definitions
3.1
Mode Selection
The 82C931 can be configured into two different modes:
• 931-MB Mode
- Single-chip motherboard application with 16-bit DMA
support to enhance telephony-audio application performance.
• 931-AD Mode
- Single chip adaptor card with support for IDE CD-ROM
and modem interfaces.
Pins 11 is used to select the desired mode of the 82C931 (as
shown in Table 3-1). Table 3-2 details the features in both of
these modes.
Table 3-1
Mode Selection
Pin 11
Table 3-2
Mode
1
931-MB
0
931-AD
Mode Features
Some pins of the 82C931 take on different functions depending upon its configured mode. The following subsections give
the pin assignment and definitions for both the 931-MB and
931-AD modes, respectively.
In addition to mode defined pins, the 82C931 has multiplexed
pins. These pins are denoted with a plus (+) sign between
signal names. Their definitions can also be found in the signal
description tables.
Table 3-3 defines abbreviated terms that are used throughout
this section.
Table 3-3
Signal Definitions Legend
Mnemonic
Description
Analog
Analog-level compatible
CMOS
CMOS-level compatible
Ext
External
G
Ground
I
Input
Int
Internal
I/O
Input/Output
Mux
Multiplexer
931-MB
931-AD(4)
IDE CD Interface
No
Yes
O
Output
IDE Interrupt Redirect
No
Yes
OD
Open drain
Modem Interface
No
Yes(1)
P
Power
PD
Pull-down resistor
Feature
Volume Control
Yes(2)
Yes(2)
Serial Audio Port
Yes(3)
Yes
Internal OPTiFM
Yes
16-Bit DMA
Yes
PU
Pull-up resistor
Smt
Schmitt-trigger
Yes
TS
Tristate
No
TTL
TTL-level compatible
1.
Pins are shared between second Game Port and Modem
interface.
2.
Volume Control can be used when second Game Port is
not used by others.
3.
Pins are shared between second Game Port and Serial
Audio port.
4.
The IDE and modem resources are programmable in
931-AD mode (available in 931 silicon revision 1.1 only).
OPTi
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912-3000-035
Revision: 2.1
Page 5
82C931
3.2
931-MB Mode
931-MB Mode PQFP Pin Diagram*
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CDR
LINER
MICR
MICL
LINEL
CDL
AUXL
OUTR
OUTL
MIXOUTL
CINL
MIXOUTR
CINR
AVCC
VREF2
AGND
RESET
SA11
SA10
SA9
Figure 3-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
82C931
931-MB Mode
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD7
SD6
SD5
SD4
VCC
GND
SD3
SD2
SD1
SD0
DRQ3
DRQ1
DRQ0
VCC
GND
IRQ9
IRQ7
IRQ5
IRQ10
IRQ11
AEN
GD7+SADI+VOLUP
DRQ5
DRQ6
RESET#
GPIO2+ROMCLK
GPIO3+ROMDOUT
ROMDIN
SA15
SA14
GND
SA13
SA12
GPIO0+SDHOE+EXTROM#
DACK5#
DACK6#
DACK0#
DACK1#
DACK3#
IOW#
IOR#
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AUXR
VREF1
AVCC
AGND
AGND
AVCC
OSCI
OSCO
RXD
TXD
GPIO1+MODE0
ROMCS+PNPEN
SD15
SD14
SD13
SD12
GND
VCC
SD11
SD10
SD9
SD8
GD0
GD1
GD2+FSYNC
GD3+SCLK
GND
GD4+VOLDN
GD5+VOLUP
GD6+SADO+VOLDWN
* Pinout for TQFP Package is identical to pinout for PQFP Package.
OPTi
®
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Revision: 2.1
82C931
Table 3-4
931-MB Mode Numerical Pin Cross-Reference List
Pin
No. Pin Name
Pin
Type
Pin
No. Pin Name
Pin
Type
Pin
Type
I
26 GD3+SCLK
76 SA4
I
VREF1
AVCC
AGND
AGND
AVCC
OSCI
OSCO
RXD
O
P
G
G
P
I
O
I
27
28
29
30
31
32
33
34
GND
G
GD4+VOLDN
I/O
GD5+VOLUP
I/O
GD6+SADO+VOLDWN I/O
GD7+SADI+VOLUP
I/O
DRQ5
O-TS
DRQ6
O-TS
RESET#
O
52
53
54
55
56
57
58
59
IRQ11
IRQ10
IRQ5
IRQ7
IRQ9
GND
VCC
DRQ0
I/O
I/O
I/O
I/O
I/O
G
P
O-TS
77
78
79
80
81
82
83
84
SA5
SA6
SA7
SA8
SA9
SA10
SA11
RESET
I
I
I
I
I
I
I
I
10
11
12
13
14
15
16
17
TXD
GPIO1+MODE0
ROMCS+PNPEN
SD15
SD14
SD13
SD12
GND
O
I/O
I/O
I/O
I/O
I/O
I/O
G
35
36
37
38
39
40
41
42
GPIO2+ROMCLK
GPIO3+ROMDOUT
ROMDIN
SA15
SA14
GND
SA13
SA12
I/O
I/O
I/O
I
I
G
I
I
60
61
62
63
64
65
66
67
DRQ1
DRQ3
SD0
SD1
SD2
SD3
GND
VCC
O-TS
O-TS
I/O
I/O
I/O
I/O
G
P
85
86
87
88
89
90
91
92
AGND
VREF2
AVCC
CINR
MIXOUTR
CINL
MIXOUTL
OUTL
G
O
P
I
O
I
O
O
18
19
20
21
22
23
24
25
VCC
SD11
SD10
SD9
SD8
GD0
GD1
GD2+FSYNC
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
43 GPIO0+SDHOE
+EXTROM#
44 DACK5#
45 DACK6#
46 DACK0#
47 DACK1#
I/O
68
69
70
71
72
73
74
75
SD4
SD5
SD6
SD7
SA0
SA1
SA2
SA3
I/O
I/O
I/O
I/O
I
I
I
I
93
94
95
96
97
98
99
100
OUTR
AUXL
CDL
LINEL
MICL
MICR
LINER
CDR
O
I
I
I
I
I
I
I
Pin Name
48 DACK3#
49 IOW#
50 IOR#
I
I
I
I
Pin
Type
2
3
4
5
6
7
8
9
I
I
I
I
51 AEN
Pin
No. Pin Name
1 AUXR
Table 3-5
I/O
Pin
No. Pin Name
931-MB Mode Alphabetical Pin Cross-Reference List
Pin
No.
Pin
Type
Pin Name
Pin
No.
Pin
Type
Pin Name
Pin
No.
Pin
Type
Pin Name
Pin
No.
Pin
Type
AEN
AGND
AGND
AGND
AUXL
51
4
5
85
94
I
G
G
G
I
GD2+FSYNC
GD3+SCLK
GD4+VOLDN
GD5+VOLUP
GD6+SADO+VOLDWN
25
26
28
29
30
I/O
I/O
I/O
I/O
I/O
MICR
MIXOUTL
MIXOUTR
OSCI
OSCO
98
91
89
7
8
I
O
O
I
O
SA13
SA14
SA15
SD0
SD1
41
39
38
62
63
I
I
I
I/O
I/O
AUXR
AVCC
AVCC
AVCC
CDL
CDR
CINL
CINR
1
3
6
87
95
100
90
88
I
P
P
P
I
I
I
I
GD7+SADI+VOLUP
GND
GND
GND
GND
GND
GPIO0+SDHOE
+EXTROM#
GPIO1+MODE0
GPIO2+ROMCLK
GPIO3+ROMDOUT
IOW#
IOR#
IRQ5
31
17
27
40
57
66
43
I/O
G
G
G
G
G
I/O
OUTL
OUTR
RESET
RESET#
ROMCS+PNPEN
ROMDIN
RXD
SA0
92
93
84
34
12
37
9
72
O
O
I
O
I/O
I/O
I
I
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
64
65
68
69
70
71
22
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11
35
36
49
50
54
I/O
I/O
I/O
I
I
I/O
IRQ7
IRQ9
IRQ10
IRQ11
LINEL
LINER
MICL
55
56
53
52
96
99
97
I/O
I/O
I/O
I/O
I
I
I
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
73
74
75
76
77
78
79
80
I
I
I
I
I
I
I
I
SD10
SD11
SD12
SD13
SD14
SD15
TXD
VCC
20
19
16
15
14
13
10
18
I/O
I/O
I/O
I/O
I/O
I/O
O
P
SA9
SA10
SA11
SA12
81
82
83
42
I
I
I
I
VCC
VCC
VREF1
VREF2
58
67
2
86
P
P
O
O
DACK0#
DACK1#
DACK3#
DACK5#
DACK6#
DRQ0
DRQ1
DRQ3
46
I
47
I
48
I
44
I
45
I
59 O-TS
60 O-TS
61 O-TS
DRQ5
DRQ6
GD0
GD1
32 O-TS
33 O-TS
23 I/O
24 I/O
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Revision: 2.1
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82C931
3.2.1
931-MB Mode Signal Descriptions
3.2.1.1
ISA Bus Interface Signals
Signal Name
Pin No.
Signal/Pin
Type (Drive)
Signal Description
IOW#
49
I-TTL-Smt,
50KΩ PU
I/O Write Command
IOR#
50
I-TTL-Smt,
50KΩ PU
I/O Read Command
AEN
51
I-TTL-Smt
DMA Address Enable
RESET
84
I-TTL-Smt,
50KΩ PD
System Reset Input
SA[15:0]
38, 39, 41, 42,
83:72
I-TTL
SD[15:8]
13:16,
19:22
I/O-TTL
(12mA)
System Data Bus Lines 15 through 8
SD[7:0]
71:68, 65:62
I/O-TTL
(16mA)
System Data Bus Lines 7 through 0
DACK0#
DACK1#
DACK3#
46
47
48
I-TTL,
50KΩ PU
DRQ0
DRQ1
DRQ3
59
60
61
O-TS (12mA),
50KΩ PD
DACK5#
DACK6#
44
45
I-TTL
DRQ5
DRQ6
32
33
O-TS
(12mA)
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
54
55
56
53
52
OD-I/O-TTL
(12mA)
Interrupt Request Bits 5, 7, and 9 through 11: IRQ7 and IRQ9-11
are bidirectional for WSS auto interrupt determination.
Pin No.
Signal/Pin
Type (Drive)
Signal Description
RXD
9
I-TTL-Smt
Receive Data from 32KBaud MIDI UART Port
TXD
10
O (20mA)
Transmit Data to 32KBaud MIDI UART Port
3.2.1.2
System Address Bus Lines 15 through 0
8-Bit DMA Acknowledge Bits 0, 1, and 3
8-Bit DMA Request Bits 0, 1, and 3
16-Bit DMA Acknowledge Bits 5 and 6
16-Bit DMA Request Bits 5 and 6
MIDI Interface Signals
Signal Name
OPTi
®
Page 8
912-3000-035
Revision: 2.1
82C931
931-MB Mode Signal Descriptions (cont.)
3.2.1.3
Configuration and External PnP EEPROM Interface Signals
Signal Name
ROMCS
Pin No.
12
PNPEN
GPIO1
11
MODE0
GPIO2
35
ROMCLK
GPIO3
36
ROMDOUT
Signal/Pin
Type (Drive)
Signal Description
I/O-TTL, PU
(8mA)
External Serial EEPROM Chip Select
I/O-TTL, PU
(8mA)
General Purpose Input/Output
PNP Mode Enable Jumper Input: Jumper setting is latched at reset
power-on reset. This pin has an internal pull-up. Jumper pull-up:
enable (default), pull-down: disable
931 Mode Configuration Bit 0: This pin is used to configure the
82C931 in either the 931-MB or 931-AD mode (refer to Table 3-1).
These settings are latched into the 82C931 at reset.
I/O-TTL, PD
(12mA)
General Purpose Input/Output
I/O-TTL, PU
(12mA)
General Purpose Input/Output
External Serial EEPROM Data In
EEPROM enable jumper input function is removed
External Serial EEPROM Clock
External Serial EEPROM Data Out
ROMDIN
37
I/O-TTL, PD
(12mA)
RESET#
34
O
(12mA)
Buffered Reset (active low)
GPIO0
43
I/O-TTL, PU
(8mA)
General Purpose I/O Bit 0
SDHOE
External EEPROM enable jumper input: jumper setting is latched at
power-on reset. This pin has internal pull-up. Jumper pull-up: disable
(default), pull-down: enable
EXTROM
3.2.1.4
SD[15:8] Buffer Output Enable: Set MCIR19[7] = 1 to enable
SDHOE function on this pin.
Game Port and Serial Audio Interface Signals
Signal Name
GD7
Pin No.
31
SADI
Signal/Pin
Type (Drive)
I/O-CMOS-Smt
(8mA)
30
SADO
I/O-CMOS-Smt
(16mA)
VOLUP
Serial Audio Data Input
Game Port 2 Data Line 6
Serial Audio Data Output
Volume Down: Interface for push-button volume control. Used to
decrease volume. An external pull-up is required on this pin.
VOLDWN
GD5
Game Port 2 Data Line 7
Volume Up: Interface for push-button volume control. Used to
increase volume. An external pull-up is required on this pin.
VOLUP
GD6
Signal Description
29
I/O-CMOS
(8mA)
Game Port 1 Data Line 5
An External pull-up is required on this pin.
Volume Up: Interface for push-button volume control. Used to
increase volume. VOLUP on pin 29 is only available in rev. 1.1 silicon.
OPTi
®
912-3000-035
Revision: 2.1
Page 9
82C931
931-MB Mode Signal Descriptions (cont.)
3.2.1.4
Game Port and Serial Audio Interface Signals
Signal Name
Pin No.
GD4
28
Signal/Pin
Type (Drive)
I/O-CMOS
(8mA)
Signal Description
Game Port 1 Data Line 4
An External pull-up is required on this pin.
Volume Down: Interface for push-button volume control. Used to
decrease volume. VOLDN on pin 28 is only available in rev. 1.1 silicon.
VOLDN
GD3
26
SCLK
GD2
25
FSYNC
I/O-CMOS
(8mA)
Game Port 2 Data Line 3
I/O-CMOS
(8mA)
Game Port 2 Data Line 2
Serial Audio Clock
Serial Audio Synchronization
GD1
24
I/O-CMOS
(8mA)
Game Port 1 Data Line 1
GD0
23
I/O-CMOS
(8mA)
Game Port 1 Data Line 0
3.2.1.5
Codec/Mixer Interface Signals
Pin No.
Signal/Pin
Type (Drive)
MICL
97
I-Analog
Microphone Input Left
MICR
98
I-Analog
Microphone Input Right
LINEL
96
I-Analog
Line Input Left
LINER
99
I-Analog
Line Input Right
CDL
95
I-Analog
CD Input Left
CDR
100
I-Analog
CD Input Right
AUXL
94
I-Analog
Auxiliary Input Left
AUXR
1
I-Analog
Auxiliary Input Right
OUTL
92
O-Analog
Output Left
OUTR
93
O-Analog
Output Right
MIXOUTL
91
O-Analog
Mixer Output Left
MIXOUTR
89
O-Analog
Mixer Output Right
CINL
90
I-Analog
ADC Filter Pin Left
CINR
88
I-Analog
ADC Filter Pin Right
VREF1
2
O-Analog
Analog Common: Normally connected to AGND with a 0.1µF ceramic
capacitor in parallel with a 10µF electrolytic capacitor.
VREF2
86
O-Analog
Voltage Reference: Nominal 1.85V reference available externally. Not
meant for current sourcing or sinking. Normally connected to AGND
with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic
capacitor.
Signal Name
Signal Description
OPTi
®
Page 10
912-3000-035
Revision: 2.1
82C931
931-MB Mode Signal Descriptions (cont.)
3.2.1.5
Codec/Mixer Interface Signals
Pin No.
Signal/Pin
Type (Drive)
OSCI
7
I-Analog
Oscillator Input: A 14.318MHz crystal oscillator is to be connected
across this pin and the OSCO pin.
OSCO
8
O-Analog
Oscillator Output: See OSCI.
Signal Name
3.2.1.6
Signal Description
Power and Ground Pins
Pin No.
Signal/Pin
Type (Drive)
Signal Description
VCC
18, 58, 67
P
Power Connection
GND
17, 27, 40, 57,
66
G
Ground Connection
AVCC
3, 6, 87
P
Analog Power Connection
AGND
4, 5, 85
G
Analog Ground Connection
Signal Name
OPTi
®
912-3000-035
Revision: 2.1
Page 11
82C931
3.3
931-AD Mode
931-AD Mode PQFP Pin Diagram*
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CDR
LINER
MICR
MICL
LINEL
CDL
AUXL
OUTR
OUTL
MIXOUTL
CINL
MIXOUTR
CINR
AVCC
VREF2
AGND
RESET
SA11
SA10
SA9
Figure 3-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
82C931
931-AD Mode
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD7
SD6
SD5
SD4
VCC
GND
SD3
SD2
SD1
SD0
DRQ3
DRQ1
DRQ0
VCC
GND
IRQ9
IRQ7
IRQ5
IRQ10
IRQ11
AEN
GD7+MODEMCS#+
MODEM#+VOLUP
XIOR#
XIOW#
RESET#
CA2+ROMCLK+IDEDIS#
CA1+ROMDOUT
CA0+ROMDIN
IDECS1#
IDECS3#
GND
IDEIRQ+GPIO2
IRQ15+GPIO3
GPIO0+EXTROM#
CDOE#
CDHOE#
DACK0#
DACK1#
DACK3#
IOW#
IOR#
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AUXR
VREF1
AVCC
AGND
AGND
AVCC
OSCI
OSCO
RXD
TXD
GPIO1+MODE0
ROMCS+PNPEN
SA15
SA14
SA13
SA12
GND
VCC
SADI
SADO
SCLK
FSYNC
GD0
GD1
GD2+IRQ3
GD3+IRQ4
GND
GD4+VOLDN
GD5+VOLUP
GD6+MODEMINT+VOLDWN
* Pinout for TQFP Package is identical to pinout for PQFP Package.
OPTi
®
Page 12
912-3000-035
Revision: 2.1
82C931
Table 3-6
Pin
No.
931-AD Mode Numerical Pin Cross-Reference List
Pin
Type
Pin Name
1 AUXR
2 VREF1
3 AVCC
Pin Name
Pin
Type
I
O
P
27 GND
28 GD4+VOLDN
29 GD5+VOLUP
G
I/O
I/O
50 IOR#
51 AEN
52 IRQ11
30 GD6+MODEMINT+
VOLDWN
31 GD7+MODEMCS#+
+MODEM#+VOLUP
32 XIOR#
I/O
33 XIOW#
34 RESET#
35 CA2+ROMCLK+
IDEDIS#
36 CA1+ROMDOUT
37 CA0+ROMDIN
O
O
I/O
53
54
55
56
57
58
59
60
IRQ10
IRQ5
IRQ7
IRQ9
GND
VCC
DRQ0
DRQ1
I/O
I/O
38
39
40
41
42
43
44
45
IDECS1#
IDECS3#
GND
IDEIRQ+GPIO2
IRQ15+GPIO3
GPIO0+EXTROM#
CDOE#
CDHOE#
O
O
G
I/O
I/O
I/O
O
O
61
62
63
64
65
66
67
68
DRQ3
SD0
SD1
SD2
SD3
GND
VCC
SD4
46
47
48
49
DACK0#
DACK1#
DACK3#
IOW#
69
70
71
72
73
74
75
SD5
SD6
SD7
SA0
SA1
SA2
SA3
4
5
6
7
8
9
10
11
AGND
AGND
AVCC
OSCI
OSCO
RXD
TXD
GPIO1+MODE0
G
G
P
I
O
I
O
I/O
12
13
14
15
16
17
18
19
ROMCS+PNPEN
SA15
SA14
SA13
SA12
GND
VCC
SADI
I/O
I/O
I/O
I/O
I/O
G
P
I
20
21
22
23
24
25
26
SADO
SCLK
FSYNC
GD0
GD1
GD2+IRQ3
GD3+IRQ4
O
I/O
I/O
I/O
I/O
I/O
I/O
Table 3-7
Pin Name
Pin
No.
I/O
O
I
I
I
I
Pin
No.
Pin
Type
Pin Name
I
I
I/O
Pin
No.
Pin
Type
Pin Name
76 SA4
77 SA5
78 SA6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
P
O-TS
O-TS
79
80
81
82
83
84
85
86
SA7
SA8
SA9
SA10
SA11
RESET
AGND
VREF2
I/O
I/O
I/O
I/O
I/O
I
G
O
O-TS
I/O
I/O
I/O
I/O
G
P
I/O
87
88
89
90
91
92
93
94
AVCC
CINR
MIXOUTR
CINL
MIXOUTL
OUTL
OUTR
AUXL
P
I
O
I
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
95
96
97
98
99
100
CDL
LINEL
MICL
MICR
LINER
CDR
I
I
I
I
I
I
931-AD Mode Alphabetical Pin Cross-Reference List
Pin
No.
Pin
Type
Pin Name
Pin
No.
Pin
Type
Pin Name
Pin
No.
Pin
Type
Pin Name
Pin
No.
Pin
Type
AEN
AGND
AGND
51
4
5
I
G
G
GD0
GD1
GD2+IRQ3
23
24
25
I/O
I/O
I/O
IOR#
IOW#
LINEL
50
49
96
I
I
I
SA10
SA11
SA12
82
83
16
I/O
I/O
I/O
AGND
AUXL
AUXR
AVCC
AVCC
AVCC
CA0+ROMDIN
CA1+ROMDOUT
85
94
1
3
6
87
37
36
G
I
I
P
P
P
I/O
I/O
26
28
29
30
I/O
I/O
I/O
I/O
31
I/O
I
I
I
O
O
I
O
O
SA13
SA14
SA15
SADI
SADO
SCLK
SD0
SD1
15
14
13
19
20
21
62
63
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
45
95
44
100
O
I
O
I
G
G
G
G
G
99
97
98
91
89
7
8
92
35
17
27
40
57
66
LINER
MICL
MICR
MIXOUTL
MIXOUTR
OSCI
OSCO
OUTL
CA2+ROMCLK+
IDEDIS#
CDHOE#
CDL
CDOE#
CDR
GD3+IRQ4
GD4+VOLDN
GD5+VOLUP
GD6+MODEMINT
+VOLDWN
GD7+MODEMCS#+
+MODEM#+VOLUP
GND
GND
GND
GND
GND
GPIO0+EXTROM#
GPIO1+MODE0
IDECS1#
IDECS3#
IDEIRQ+GPIO2
IRQ5
IRQ7
IRQ9
43
11
38
39
41
54
55
56
I/O
I/O
O
O
I/O
I/O
I/O
I/O
OUTR
RESET
RESET#
ROMCS+PNPEN
RXD
SA0
SA1
SA2
93
84
34
12
9
72
73
74
O
I
O
I/O
I
I/O
I/O
I/O
SD2
SD3
SD4
SD5
SD6
SD7
TXD
VCC
64
65
68
69
70
71
10
58
I/O
I/O
I/O
I/O
I/O
I/O
O
P
IRQ10
IRQ11
IRQ15+GPIO3
53
52
42
I/O
I/O
I/O
SA3
SA4
SA5
SA6
SA7
SA8
SA9
75
76
77
78
79
80
81
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
VREF1
VREF2
XIOR#
XIOW#
18
67
2
86
32
33
P
P
O
O
O
O
CINL
CINR
DACK0#
DACK1#
DACK3#
DRQ0
DRQ1
DRQ3
90
I
88
I
46
I
47
I
48
I
59 O-TS
60 O-TS
61 O-TS
FSYNC
22
I/O
OPTi
®
912-3000-035
Revision: 2.1
Page 13
82C931
3.3.1
931-AD Mode Signal Descriptions
3.3.1.1
ISA Bus Signals
Signal Name
Pin No.
Signal/Pin
Type (Drive)
Signal Description
IOW#
49
I-TTL-Smt
50KΩ PU
I/O Write Command
IOR#
50
I-TTL-Smt
50KΩ PU
I/O Read Command
AEN
51
I-TTL-Smt
DMA Address Enable
RESET
84
I-TTL-Smt
50KΩ PD
System Reset Input
SA[15:0]
13:16,
83:72
I/O-TTL
(12mA)
System Address Bus Lines 15 through 0
SD[7:0]
71:68,
65:62
I/O-TTL
(16mA)
System Data Bus Lines 7 through 0
DACK0#
DACK1#
DACK3#
46,
47,
48
I-TTL
50KΩ PU
DMA Acknowledge Bits 0, 1, and 3
DRQ0
DRQ1
DRQ3
59
60
61
GPIO0
43
EXTROM#
O-TS, 50KΩ PD DMA Request Bits 0, 1, and 3
(12mA)
I/O-TTL, PU
(8mA)
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
54
55
56
53
52
OD, I/O-TTL
(12mA)
IRQ15
42
I/O-TTL
(12mA)
GPIO3
3.3.1.2
General Purpose I/O Bit 0
External EEPROM Enable Jumper Input: Jumper setting is latched
at reset time. (If pin 43 is pulled up, external EEPROM is enabled.)
Interrupt Request Bits 5, 7, and 9 through 11: IRQ7 and IRQ[9:11]
are bidirectional for WSS auto interrupt determination
Interrupt Request Bit 15
General Purpose I/O Bit 1
MIDI Interface Signals
Pin No.
Signal/Pin
Type (Drive)
RXD
9
I-TTL-Smt
TXD
10
O
(20mA)
Signal Name
Signal Description
Receive Data from 32KBaud MIDI UART Port
Transmit Data to 32KBaud MIDI UART Port
OPTi
®
Page 14
912-3000-035
Revision: 2.1
82C931
931-AD Mode Signal Descriptions (cont.)
3.3.1.3
Configuration, External PnP EEPROM, and IDE CD-ROM Interface Signals
Signal Name
ROMCS
Pin No.
12
PNPEN
GPIO1
11
MODE0
CA2
35
ROMCLK
Signal/Pin
Type (Drive)
I/O-TTL, PU
(8mA)
I/O-TTL, PU
(8mA)
I/O-TTL, PD
(12mA)
36
ROMDOUT
CA0
External Serial EEPROM Chip Select
PNP Mode Enable Jumper Input: Jumper setting is latched at poweron reset. This pin has an internal pull-up. Jumper pull-up: enable
(default), pull-down: disable.
General Purpose I/O Bit 1
931 Mode Configuration Bit 0: This pin is used to configure the
82C931 in either the 931-MB or 931-AD mode (refer to Table 3-1).
These settings are latched into the 82C931 at reset.
IDE CA2: Buffered SA2 for CD-ROM
External Serial EEPROM Clock
IDE Disable: Jumper selection to disable IDE resource. No connect
equals IDE enabled. Pull down equals IDE disabled. (Available in revision 1.1 silicon only.)
IDEDIS#
CA1
Signal Description
37
ROMDIN
I/O-TTL, PD
(12mA)
IDE CA1: Buffered SA1 for CD-ROM.
I/O-TTL, PD
(12mA)
IDE CA0: Buffered SA0 for CD-ROM.
External Serial EEPROM Data Out
External Serial EEPROM Data In
IDECS1#
38
O-TTL
(12mA)
IDE CD-ROM Chip Select Bit 1: CD-ROM chip select for address
decode range 0170h through 0177h.
IDECS3#
39
O-TTL
(12mA)
IDE CD-ROM Chip Select Bit 3: CD-ROM chip select for ISA address
decode range 0376h through 0377h.
IDEIRQ
41
I/O-TTL
(12mA)
IDE CD-ROM Interrupt: Interrupt input from IDE CD-ROM which redirect to IRQ5, 7, 9, 10, 11, 15 according to PNP logic.
General Purpose I/O Bit 2
GPIO2
RESET#
34
O
(12mA)
Buffered Reset (active low)
CDOE#
44
O-TTL
(8mA)
CD Output Enable: Enables low-order [7:0] of the CD data buffer.
CDHOE#
45
O-TTL
(8mA)
CD High Output Enable: Enables high-order [15:8] of CD data buffer.
XIOR#
32
O-TTL
(12mA)
IDE Buffered IOR#
XIOW#
33
O-TTL
(12mA)
IDE Buffered IOW#
OPTi
®
912-3000-035
Revision: 2.1
Page 15
82C931
931-AD Mode Signal Descriptions (cont.)
3.3.1.4
Game Port and Modem Interface Signals
Signal Name
Pin No.
GD7
31
MODEMCS#
Signal Type
(Drive)
I/O-CMOS-Smt
(8mA)
Signal Description
Game Port 2 Data Line 7
Modem Chip Select: Output to external modem chip select pin.
MODEM#
Modem Interface Enable Jumper Input: Jumper setting is latched at
power-on reset. Jumper pull-up: disable (default), pull-down: enable.
An external pull-up is required on this pin.
VOLUP
Volume Up: Interface for push-button volume control. Used to
increase volume.
GD6
30
MODEMINT
I/O-CMOS-Smt
(8mA)
Game Port 2 Data Line 6
Modem Interrupt: Interrupt signal from external modem.
Volume Down: Interface for push-button volume control. Used to
decrease volume. An external pull-up is required on this pin.
VOLDWN
GD5
29
I/O-CMOS
(8mA)
Game Port 1 Data Line 5
An external pull-up is required on this pin.
Volume Up: Interface for push-button volume control. Used to
increase volume. VOLUP on pin 29 is only available in rev. 1.1 silicon.
VOLUP
GD4
28
I/O-CMOS
(8mA)
Game Port 1 Data Line 4
An external pull-up is required on this pin.
Volume Down: Interface for push-button volume control. Used to
decrease volume. VOLDN on pin 28 is only available in rev. 1.1 silicon.
VOLDN
GD3
26
IRQ4
GD2
25
IRQ3
I/O-CMOS
(8mA)
Game Port 2 Data Line 3
I/O-CMOS
(8mA)
Game Port 2 Data Line 2
Interrupt Request Bit 4
Interrupt Request Bit 3
GD1
24
I/O-CMOS
(8mA)
Game Port 1 Data Line 1
GD0
23
I/O-CMOS
(8mA)
Game Port 1 Data Line 0
3.3.1.5
Codec/Mixer Interface Signals
Pin No.
Signal/Pin
Type (Drive)
MICL
97
I-Analog
Microphone Input Left
MICR
98
I-Analog
Microphone Input Right
LINEL
96
I-Analog
Line Input Left
LINER
99
I-Analog
Line Input Right
CDL
95
I-Analog
CD Input Left
CDR
100
I-Analog
CD Input Right
Signal Name
Signal Description
OPTi
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Revision: 2.1
82C931
931-AD Mode Signal Descriptions (cont.)
3.3.1.5
Codec/Mixer Interface Signals (cont.)
Pin No.
Signal/Pin
Type (Drive)
Signal Description
AUXL
94
I-Analog
Auxiliary Input Left
AUXR
1
I-Analog
Auxiliary Input Right
OUTL
92
O-Analog
Output Left
OUTR
93
O-Analog
Output Right
MIXOUTL
91
O-Analog
Mixer Output Left
MIXOUTR
89
O-Analog
Mixer Output Right
CINL
90
I-Analog
ADC Filter Pin Left
CINR
88
I-Analog
ADC Filter Pin Right
VREF1
2
O-Analog
Analog Common: Normally connected to AGND with a 0.1µF ceramic
capacitor in parallel with a 10µF electrolytic capacitor.
VREF2
86
O-Analog
Voltage Reference: Nominal 1.85V reference available externally. Not
meant for current sourcing or sinking. Normally connected to AVS with
a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic capacitor.
OSCI
7
I-Analog
Oscillator Input: A 14.318MHz crystal oscillator is to be connected
across this pin and the OSCO pin.
OSCO
8
O-Analog
Oscillator Output: See OSCI.
Signal Name
3.3.1.6
Serial Audio Interface Signals
Pin No.
Signal/Pin
Type (Drive)
SADI
19
I-TTL
Serial Audio Data Input
SADO
20
O-TTL
Serial Audio Data Output
SCLK
21
I/O-TTL
Serial Audio Clock
FSYNC
22
I/O-TTL
Serial Audio Synchronization
Signal Name
3.3.1.7
Signal Description
Power and Ground Pins
Pin No.
Signal/Pin
Type (Drive)
Signal Description
VCC
18, 58, 67
P
Power Connection
GND
17, 27, 40, 57,
66
G
Ground Connection
AVCC
3, 6, 87
P
Analog Power Connection
AGND
4, 5, 85
G
Analog Ground Connection
Signal Name
OPTi
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Revision: 2.1
Page 17
82C931
OPTi
®
Page 18
912-3000-035
Revision: 2.1
82C931
4.0
Functional Description
The 82C931 is an optimized single chip solution with built-in
Plug-and-Play functions, built-in FM synthesizer and 16-bit
Sigma-Delta Codec to provide all of the features needed to
create the following sound characteristics and applications:
• 16-bit sound quality Sound Blaster Pro and Windows
Sound System compatible card
• 22 voice FM synthesis
• 16-bit CD-quality digital wave audio up to 44.1KHz stereo
A PnP configuration sequence is carried out by either the
system BIOS supporting PnP or Configuration Manager software of the operating system. It is used to map the various
functional blocks (logical devices) within the 82C931 into the
host system address space as well as to configure the DMA
and IRQ channels. The configuration sequence occurs as follows:
1.
The 82C931 is isolated from the system.
2.
A unique indentifier (handle) is programmed into the
82C931 and the resource data is read.
3.
After the resource requirement and capabilities are
determined, the handle is used to assign conflict-free
resources by programming the appropriate information
into the 82C931 configuration registers a logical device
at a time
4.
After the configuration registers are programmed, the
82C931 leaves the configuration mode and each logical
device is activated individually. The bus interface of each
logical device is then enabled.
• Game port
• MPU-401 MIDI interface
• Wavetable synthesis upgrade
The following sub-sections will discuss these built-in functions in detail.
4.1
Plug and Play
The OPTi 82C931 supports the ISA Plug and Play (PnP)
Specification 1.0a. After power-up, the 82C931 is isolated
from other PnP cards in the host system by the system software. With this mechanism, the I/O address, IRQ and DMA
usage of the 82C931 can be configured by the system
according to the free resources available. As a result, the
chance of getting a resource conflict is minimized.
The PnP function is disabled by pulling pin 12 (PNPEN) of
the 82C931 low at power-up; otherwise the 82C931 will operate in PnP mode.
The 82C931 supports the following logical devices:
• IDE CD-ROM interface
• Windows Sound System
• FM synthesis
• Sound Blaster Pro
• Game Port
• MPU-401 MIDI interface
• Modem interface
• 82C931 Master Control
OPTi
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912-3000-035
Revision: 2.1
Page 19
82C931
4.2
16-Bit Codec/Mixer
4.2.1
Codec
• L/R - to select between the left and right channels for both
the ADC and DAC data.
Features of the built-in 16-bit stereo sigma-delta codec
include:
• MCLK - This internal master clock signal is synthesized by
the frequency synthesizer from the crystal reference of
14.318MHz. One of 236 frequencies may be selected
through the 8-bit FSEL line. MCLK is not active when the
frequency synthesizer is powered down. The frequency of
MCLK is 256 times the sampling frequency.
• Sigma-delta stereo ADC with 128X over-sampling
• Sigma-delta stereo DAC with 128X over-sampling
• On-chip 8X Interpolation Filter
• On-chip analog post filter
The DAC left/right 16-bit input data are multiplexed onto
DAC[15:0] and fed into the codec. The L/R signal qualifies
the data. The period of L/R is equal to that of the codec sampling frequency. One set of left/right 16-bit input data to the
DAC is sent every L/R cycle. When L/R is low, the data on
DAC[15:0] is meant for the left channel; when L/R is high, the
data is meant for the right channel. This means that the DAC
treats data packets L1 and R1 as belonging to the same sampling instance; while L2 and R2 are data for the next sampling instance.
• Single-ended input and output
• Sampling rate of 5KHz to 48KHz
The codec serial interface provides a means to read and
write 16-bit stereo data from the ADC or to the DAC respectively. The interface (as shown in Figure 4-1) consists of the
following lines:
• DAC[15:0] - to write to the DAC 16-bit input
• ADC[15:0] - to read the ADC 16-bit output
Figure 4-1
The ADC left/right 16-bit output data are similarly multiplexed
onto the ADC[15:0] bus.
Functional Block Diagram
AVCC
Stereo 16-Bit Sigma-Delta ADC
AGND
CINL
Analog
Sigma-Delta
Modulator
1
128fs
Analog
Sigma-Delta
Modulator
1
128fs
128:1
Decimation
Filter
16
128:1
Decimation
Filter
16
fs
fs
Stereo 16-Bit Sigma-Delta DAC
DACL
DACR
Analog
Low-Pass
Filter
Digital
Sigma-Delta
Modulator
Analog
Low-Pass
Filter
Digital
Sigma-Delta
Modulator
VREF
Voltage Reference
MCLK
Clock Generation
16
8fs
Serial Interface
CINR
8X
Interpolator
16
8fs
8X
Interpolator
Power Supply
VCC VCC
PD
OPTi
®
Page 20
912-3000-035
Revision: 2.1
82C931
4.2.2
Mixer
The built-in mixer mixes two mono microphone level inputs
(MICL/R) and five stereo analog line level input sources
(LINEL/R, CDL/R, AUXL/R, FML/R, and DACL/R) with individual mixer programmable gain and mute control. The
DACL/R stereo analog inputs are routed to a programmable
circuit with 1.5dB steps (total of 32 levels). Internal amplifiers
with a programmable 20dB gain block are provided for the
MIC input (only). The remaining stereo analog inputs are
routed to a programmable gain circuit which can be programmed in 3dB steps (total of 16 levels). Also, internal
amplifiers with a programmable 20dB gain block are provided. Level changes only take effect on zero crossings to
minimize audible artifacts. AC coupling is mandatory for
Figure 4-2
these inputs since any DC offset on the input will be amplified.
MIXOUTL (mixer record output left) must be connected to
CINL (codec analog input left) with a ceramic capacitor. MIXOUTR (mixer record output right) must be connected to CINR
(codec analog input right) with a ceramic capacitor. MIXOUT/R are routed via gain control (1.5dB steps: total of 16
levels). Analog output OUTL/R are routed via a master volume control which provides 0db to 94.5db of attenuation,
adjustable in 3dB steps. The Codec Indirect Registers used
for programming the various functions/gain levels for the
mixer. For details regarding these registers, refer to Table 510 and Table 5-11 in the Register Section. Figure 4-2 shows
a functional block diagram of the mixer.
Mixer Block Diagram
2
2
2
Mux
2
+20dB
2
Gain
(16 Levels)
MIXOUTL/R
0 to 22.5dB
(1.5dB step)
16 Levels
–33 to 12dB
(3dB steps)
2
2
2
MICL/R
2
LINEL/R
2
CDL/R
2
AUXL/R
ATTEN
+
MUTE
2
2
ATTEN
+
MUTE
2
ATTEN
+
MUTE
2
2
ATTEN
+
MUTE
2
2
ATTEN
+
MUTE
2
FML/R
DACL/R
ATTEN
+
MUTE
2
∑
Master Volume
ATTEN/MUTE
(32 Levels)
2
OUTL/R
0 to -93dB
(3dB steps)
Zero
Cross
Detect
Mixer Latch Control
32 Levels
0 to –46.5dB
(1.5dB step)
OPTi
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Revision: 2.1
Page 21
82C931
4.3
Frequency Synthesizer
The Frequency Synthesizer (FS) block generates the codec
sampling clock from a reference crystal oscillator of
14.318MHz. The output frequency of the FA is equal to 256
times fs (where fs = codec sampling frequency).
One of the 236 frequencies may be generated by the FS. The
selection of the FS output frequency is done via programming
eight register bits in the Digital Audio Processor Write Command/Data (40h/FSEL[7:0]).
Table 4-1
Table 4-1 gives the Frequency Selection, where the
FSEL[7:0] address is given in decimal equivalent. FOUTactual is the FS output frequency for a given FSEL code and
%error gives the difference between the FOUT-actual and
the target FOUT-spec.
Shaded table entries refer to the 14 critical sampling frequencies. The error for these frequencies fall within ±0.15%.
FS Output Frequencies
FSEL
FOUT-actual
(Hz)
FSEL
FOUT-actual
(Hz)
FSEL
FOUT-actual
(Hz)
FSEL
FOUT-actual
(Hz)
FSEL
FOUT-actual
(Hz)
FSEL
FOUT-actual
(Hz)
0
1
2
3
4
5
3909.064
3924.890
3938.710
3947.978
3951.554
3957.289
43
44
45
46
47
48
4713.176
4716.962
4739.804
4759.973
4783.460
4806.457
86
87
88
89
90
91
5887.335
5915.640
5949.967
5992.466
6023.197
6059.049
129
130
131
132
133
134
7877.421
7935.969
7989.955
8066.782
8129.315
8196.592
172
173
174
175
176
177
11910.952
12046.394
12189.804
12356.559
12494.931
12663.325
215
216
217
218
219
220
24394.863
24989.860
25634.440
26303.566
27446.976
27703.490
6
7
8
9
10
11
12
13
3994.978
4030.968
4033.391
4047.543
4067.614
4084.752
4092.416
4112.477
49
50
51
52
53
54
55
56
4833.430
4847.240
4877.589
4906.113
4934.972
4955.795
4971.528
4993.722
92
93
94
95
96
97
98
99
6101.420
6138.624
6168.715
6214.410
6260.786
6292.090
6331.663
6377.947
135
136
137
138
139
140
141
142
8262.340
8329.953
8389.453
8474.195
8544.813
8636.202
8691.776
8773.284
178
179
180
181
182
183
184
185
12817.220
12983.677
13159.926
13332.077
13511.104
13697.066
13866.865
14099.921
221
222
223
224
225
226
227
228
28566.238
29417.563
30295.247
31254.825
32007.953
33080.364
34502.080
35691.971
14
15
16
17
18
19
20
21
4131.170
4142.940
4164.977
4178.655
4209.761
4221.108
4237.097
4255.520
57
58
59
60
61
62
63
64
5019.331
5049.208
5084.517
5115.520
5126.888
5151.419
5178.675
5202.762
100
101
102
103
104
105
106
107
6408.610
6453.425
6491.839
6544.963
6579.963
6615.339
6670.513
6711.562
143
144
145
146
147
148
149
150
8849.634
8924.950
9005.628
9088.574
9175.964
9219.179
9321.614
9433.923
186
187
188
189
190
191
192
193
14286.387
14487.810
14703.165
14914.583
15147.624
15380.664
15627.413
15871.938
229
230
231
232
233
234
235
37053.418
38003.505
40005.262
41693.039
44098.407
45495.044
48006.315
22
23
24
25
26
27
28
29
4276.976
4302.284
4302.284
4327.892
4350.087
4369.507
4386.642
4415.502
65
66
67
68
69
70
71
72
5243.408
5268.739
5290.646
5326.637
5346.220
5377.855
5412.550
5437.608
108
109
110
111
112
113
114
115
6750.135
6802.259
6848.533
6895.441
6935.281
6991.211
7049.961
7089.679
151
152
153
154
155
156
157
158
9519.947
9599.872
9710.015
9805.854
9904.215
10025.133
10098.416
10209.387
194
195
196
197
198
199
200
201
16018.697
16379.408
16665.917
16948.390
17244.987
17537.275
17839.642
18177.148
30
31
32
33
34
35
36
37
4433.451
4448.952
4462.475
4488.185
4500.090
4523.725
4544.287
4565.689
73
74
75
76
77
78
79
80
5456.555
5493.094
5514.194
5519.377
5523.920
5592.969
5668.549
5680.359
116
117
118
119
120
121
122
123
7139.960
7190.960
7250.145
7295.177
7359.169
7402.459
7457.292
7512.943
159
160
161
162
163
164
165
166
10302.837
10418.275
10532.214
10634.518
10755.709
10875.217
10986.188
11028.389
202
203
204
205
206
207
208
209
18511.939
18905.810
19225.830
19617.129
20034.515
20418.775
20836.550
21286.672
38
39
40
41
42
4584.401
4601.810
4605.974
4609.590
4660.807
81
82
83
84
85
5720.082
5746.201
5785.830
5804.024
5843.400
124
125
126
127
128
7573.812
7626.775
7690.332
7752.630
7813.706
167
168
169
170
171
11263.617
11360.718
11485.561
11616.166
11774.671
210
211
212
213
214
21750.434
22049.203
22721.435
23238.391
23821.904
OPTi
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Revision: 2.1
82C931
4.4
16-Bit Type F DMA Playback
The 82C931 supports the Type F DMA playback.
4.5
Modem Interface
The 82C931 includes the modem as a PnP logical device, as
well as interface pins to connect to a modem chipset. When
PnP is activated (931-AD Mode), the 82C931 provides the
resource configuration for the modem chipset, such as the
I/O address range and interrupt level.
The modem interface pins include pin 31 (MODEMCS#), pin
30 (MODEMINT), pin 25 (IRQ3), and pin 26 (IRQ4). To use
the modem interface, pin 31 (MODEM#) must be pulled
low. If a modem is connected with the 82C931, the joystick
port will provide support for one joystick only.
4.6
The 82C931 provides a serial EEPROM interface that is compatible with devices from a number of vendors. A 512- byte
EEPROM is sufficient for information required by PnP. Pin 35
of the 82C931 provides the data clock for the EEPROM. Pin
36 provides data to the EEPROM, while pin 37 gets input
from the EEPROM.
4.8
When the volume control feature is enabled, only one joystick
will be supported by the joystick port.
In silicon revision 1.1, the volume pins are additionally available in pins 28 and 29, as shown:
Serial Audio Interface
When the 82C931 is implemented in MB mode, the SAIO
connector is coming from pins 25, 26, 30 and 31.
Push Button Volume Control
In silicon revision 1.0, two pins of the joystick interface can be
used as volume control push-buttons (pin 30 as volume
down, and pin 31 as volume up) so that the speaker volume
can be controlled through front panel buttons in desktop or
notebook PCs. Appropriate software drivers are needed to
enable this feature.
931-MB mode
(no pull-down at pin#11)
931-AD mode
(pull-down at pin#11)
SCLK
pin#26
pin#21
FSYNC
(LRCLK)
pin#25
pin#22
SADI
pin#31
pin#19
SADO
pin#30
pin#20
The 82C931's serial audio interface supports the following
formats:
pin#31 & 29
Volume up
• I2S-justified format (ZV port) and its variations.
pin#30 & 28
Volume down
• Sony format (short right-justified format, used by OPTi's
wavetable chip and the Philips TDA1311AT DAC).
These two pins are active-low, edge-triggering and pulled up
internally. When the button is pressed and the corresponding
pin is activated, the register bits MCIR16[5:4] are set accordingly. The software drivers poll these two bits periodically.
The scheme is as follows:
MCIR[5:4]
(BUTUP:BUTDN)
Action required for the
driver
Press UP button
10
increase the volume by
one step
Press Down button
01
decrease the volume by
one step
Press both Up &
Down button
11
mute
Buttons
The register bits MCIR[5:4] will be cleared automatically after
they are read by the driver.
4.7
customer wants to use a different resource data and serial
identifier to customize their application, an external EEPROM
can be used. To use an external EEPROM, pin 43
(EXTROM#) must be pulled low. This enables the resource
data and serial identifier to be read from the external
EEPROM instead of the 82C931’s internal storage.
External Serial EEPROM
• AT&T PCM codec T7525 compatible16-bit mono format.
Please refer to sections 4.8.6, ZV-Port I2S, 4.8.7, Advanced
Precision General Purpose Serial Port, 4.8.8, TDA1311 Stereo Continuous Calibration, for the respective timing diagrams.
4.8.1
I2S-justified format and its variations
In the I2S-justified format (ZV-port), LRCLK is low for the left
channel, and high for the right channel. The left-channel MSB
is left-justified to the high-to-low LRCLK transition with a single SCLK delay. SDATA could be SADI when the 931 is in
receive mode, and SADO when the 931 is in transmit mode.
The LRCLK period is programmable with a minimum of 32
SCLKs (MC22[4]). The following example assumes LRCLK
period is greater than 32 SCLKs. Please note that in ZV port,
there is one more signal MCLK defined but this is not needed
for the 931.
The 82C931 has the resource data and serial identifier
required by the PnP specification stored internally. If an OEM
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Page 23
82C931
To program the 931 in the I2S-justified mode, the MC22 and
MC21 registers need to be set. The relevant MC22 and
MC21 bit definitions are shown below for reference.
I2S-justified mode (ZV-port):
MC22[7:0] = "00110001" (31H).
MC21[7:0] = "10000010" (82H).
could be used to save a T7525 as the voice codec in
modem/audio combo solution. To program the 931 in T7525
mode:
MC22[7:0] = "00110010" (32H)
MC21[7:0] = "10000010" (82H)
In short summary:
There are other I2S variations: left-justified and right-justified.
For the left-justified, LRCLK is high for the left channel, and
low for the right channel. The MSB is left-justified to an
LRCLK transition, with zero SCLK delay.
MC22[7:0] = "00110100" (34H).
MC21[7:0] = "10000010" (82H).
For the right-justified, LRCLK is high for the left channel, and
low for the right channel. The MSB is delayed from an LRCLK
transition, the LSB will be right-justified to the next LRCLK
transition.
MC22[7:0] = "00010100" (14H).
MC21[7:0] = "10000010" (82H).
Sony format1
4.8.2
This data format is essentially the same as the I2S right-justified format. Normally there are only 32 SCLKs in a LRCLK
period. The LRCLK is high for the left channel, and low for the
right channel. The MSB comes in first. To set up the 931 in
Sony format:
MC22[7:0] = "00000100" (04H).
MC21[7:0] = "10000010" (82H).
4.8.3
AT&T PCM codec T7525 compatible 16-bit
mono format
The 931 supports the T7525 receive timing - word format with
positive FSYNC. The benefit is that the 931's secondary DAC
4.8.5
MC22[7:0]
I2Sjustified
leftjustified
rightjustified
Sony
format
T7525
format
31H*
34H*
14H*
04H*
32H
82H
MC22[7:0]
* The MC22[4] bit setting may vary, depending on the LRCLK
period (32 SCLK or more).
4.8.4
Testing I2S format (ZV port) with Audio Precision machine
The Audio Precision machine system two 2322 has a serial
audio data port that can generate a test tone in the I2S format
with programmable FSYNC, ranging from 24KHz to 48KHz.
The 931 was tested with AP machine in various test tones:
256Hz, 1KHz and 3KHz in both sine wave and square wave
with FSYNC = 48KHz.
To test out the feature, the AP machine is hooked up with the
931 with appropriate connections (AP's pin#6, 12, 14 are
SDATA, SCLK and FSYNC, respectively). The next step is to
setup the MC22 to “31H” and MC21 to “82H”. Then the test
tone could be heard from the speaker connected to the 931.
Please note that there might be some noise in the speaker.
This is due to unshielded cable used to connect the serial
audio interface. Shielding the cable would help improve the
audio quality.
Relevant MC register settings
MC22 Serial Audio format control register (R/W)
Default: 00h
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset ASIO
ASIO test
enable
First16-bit
CLK32
SCLK
Polarity
FSYNC
Polarity
Pulse Mode
I2S Mode
Bit 5
First16-bit: Specifies where the data is located in the LRCLK period
0:
data located at the last 16 bits of the left/right channel in an LRCLK period
1:
data located at the first 16 (or 17) bit of the left/right channel in an LRCLK period
Bit 4
CLK32: Specifies the number of SCLKs per LRCLK period, used only in delay-mode or pulse-mode ASIO
0:
32 SCLK per LRCLK period
1:
more than 32 SCLK per LRCLK period
1.
Short right-justified format, used by OPTi's wavetable chip and the Philips TDA1311AT DAC.
OPTi
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Page 24
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Revision: 2.1
82C931
Bit 3
SCLK polarity:
0:
SDATA and LRCLK change at the rising edge of SCLK
1:
SDATA and LRCLK change at the falling edge of SCLK
Bit 2
FSYNC (LRCLK) polarity:
0:
LRCLK is LOW for the left channel, HIGH for the right channel
1:
LRCLK is HIGH for the left channel, LOW for the right channel
Bit 1
Pulse mode: Used for AT&T T7525 codec or CS8412 DSP data format
0:
Pulse mode disabled
1:
Pulse mode enabled, used for AT&T T7525 or CS8412 data format
Bit 0
I2S mode: MSB delay mode
0:
Zero SCLK delay from an LRCLK transition to MSB data
1:
One SCLK delay from an LRCLK transition to MSB data
MC21 Serial Audio selection control register (R/W)
bit 7
bit 6
CTL_SEL[1:0]
bit 5
Default: 00h
bit 4
P2S_SEL[1:0]
bit 3
bit 2
bit 1
bit 0
SPCDSEL
ADCSEL
FDACSEL
DACSEL
bit [7:6] CTL_SEL[1:0]: ASIO shift clock selection
00/11: Use the shift clock from internal FS
01:
Use FM timing
10:
Use external SCLK
bit 1
FDACSEL: selects the data source to the FDAC
0:
FDAC takes FM data
1:
FDAC takes SADI (if SPCDSEL=0) or second DMA playback data (if SPCDSEL=1)
4.8.6
ZV-Port I2S
4.8.6.1
LRCLK
This signal determines which audio channel (left/right) is currently being input on the audio Serial Data input line. LRCLK
is low to indicate the left channel and high to indicate the right
channel. Typical frequency values for this signal are 48KHz,
44.1KHz, 32KHz, and 22KHz.
4.8.6.2
SDATA
This signal is the digital PCM signal that carries the audio
information. Digital audio data is transferred using the I2S format.
I2S Format
The I2S format is shown below. The digital audio data is left
channel-MSB justified to the high-to-low going edge of the
LRCLK plus one SCLK delay.
Figure 4-3
LRCLK
I2S Format
Left Channel
Right Channel
SCLK
SDATA
15 14 13 12 1110 9 8
7 6 5 4 3
2 1 0 15 14 13 12 1110 9 8
7 6 5 4 3
2 1 0
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82C931
4.8.6.3
SCLK
This signal is the serial digital audio PCM clock.
4.8.7
The 15-pin "D-sub" connector on the rear panel provides all
input and output signals for a general purpose serial
input.output port, plus DSP-program specific input and output
pins which may be used in certain DSP (.AZ2) programs. The
pinout of the connector is detailed below. All inputs are TTL
level compatible CMOS. All outputs are CMOS isolated by
50Ω series resistors and rise time limiting networks.
4.8.6.4
MCLK
This signal is the Master clock for the digital audio. MCLK is
asynchronous to LRCLK, SDATA and SCLK.
The MCLK must be either 256x or 384x the desired Input
Word Rate (IWR). IWR is the frequency at which words for
each channel are input to the DAC and is equal to the LRCLK
frequency. The following table illustrates several standard
audio word rates and the required MCLK and LRCLK frequencies. Typically, most devices operate with 384fx master
clock.
Pin
The ZV Port audio DAC should support an MCLK frequency
of 384fs. This results in the frequencies shown below.
LRCLK (KHz)
Sample Frequency
SCLK (MHz)
32xfs
MCLK (MHz)
384x
22
0.704
8.448
32
1.0240
12.2880
44.1
1.4112
16.9344
48
1.5360
18.4320
Figure 4-4
Advanced Precision General Purpose
Serial Port
Function
Pin
9
Function
1
Ground
Serial Input Master
Clock (input)
2
+5V (tied to unused
inputs high)
10
Serial Input Bit Clock
(input)
3
Auxiliary Input (DSP
program specific)
11
Auxiliary Output (DSP
program specific)
4
Ground
12
Serial Output Bit
Clock (output)
5
Ground
13
Serial Input Data
(input)
6
Serial Output Data
(output)
14
Serial Output Frame
Sync (output)
7
Ground
15
Serial Input Frame
Sync (input)
8
Ground
General Purpose Serial Port, Timing Relationships
MSB
LSB
MSB
Bit Clock In
MSB
LSB
MSB
LSB
MSB
Data In
Frame Sync In
CHAN
A
Channel A
Detail
CLK
63
CLK
0
CLK
1
CHAN
A
Channel B
Detail
CLK
32
CLK
31
CLK
2
CLK
33
CLK
34
Bit Clock In
CH A
MSB
3
CH B
MSB
Data In
3
4
4
Frame Sync In
1
1.
2.
3.
4.
2
1
2
FRAME SYNC INPUT SETUP TIME (from falling edge, las bit clock previous subframe) 30nS minimum
FRAME SYNC INPUT SETUP TIME (to falling edge, first bit clock of present subframe) 30nS minimum
DATA INPUT SETUP TIME (to bit clock falling edge) 30nS minimum
DATA INPUT HOLD TIME (from bit clock falling edge) 45nS minimum
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82C931
4.8.8
TDA1311 Stereo Continuous Calibration
Figure 4-5
DATA
Format of Input Signals
LSB
MSB
MSB
LSB
BCK
LEFT
WS
SAMPLE OUT
RIGHT
MKA488
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82C931
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Revision: 2.1
82C931
5.0
Register Descriptions
5.1
I/O Base Addresses
Table 5-1 lists the I/O base address registers of the 82C931.
These base addresses are programmable, which assists in
avoiding possible I/O port conflicts among different devices.
The configuration registers, called MC Indirect Registers,
located via MCBase control most functions of the 82C931. An
indirect addressing scheme is used to access the MC Indirect
Registers.
The MC address (0E0Eh-0EFEh) and data (0E0Fh-0FFFh)
I/O port addresses are fully programmable. The only fixed I/O
port used by the 82C931 is at 0F8Dh.
The remaining I/O base address registers are accessed by
the same type of indexing scheme as MCBase (CPU Direct
I/O R/W).
Table 5-2 gives the register map of the 82C931.
5.2
MCBase Register
MCBase is the Direct MC base address register which controls access to the MC Indirect Registers (MCIR1-23).
MCIR1-23 control most of the basic functions of the 82C931
(i.e., CD-ROM select, base decode address select, etc.).
To avoid possible conflict of I/O ports with different devices,
the 82C931 uses a unique indirect addressing scheme with
the base addresses being programmable. Under this design
scheme, the only fixed I/O port used by 82C931 is at 0F8Dh.
The MC address and data I/O port addresses are fully programmable, from 0E0Eh-0EFEh (address port) and 0E0Fh0FFFh (data port). To access the MC registers:
(1) All MC registers in 82C931 are password protected. To
read or write into the MC registers, the password E4h
must be written into I/O Port 0F8Dh before accessing the
address or data port.
(2) The address and data access port address can be fully
programmable by writing the desired base address
selection into I/O port 0F8Dh bit 4 to bit 0, [b4..b0]. The
port address can be read as ‘111b4, b3..b0, 1110’ for the
address port and ‘111b4, b3..b0, 1111’ for the data port.
Therefore, the possible address and data access ports
can be any one from 0E0Eh-0FFEh (address port) and
0E0Fh-0FFFh (data port).
Table 5-1
82C931 I/O Base Addresses
Base Register
Function
Address Selections
MCBase
Configuration
0F8D; 0E0[E..F] to
0FF[E..F]
SBBase
Digital Audio Processor
220/240
WSBase
Windows Sound System
530/640/E80/F40
IDEBase
IDE CD ROM
170/370
ALBase
AdLib
388
OPL4Base
OPL4
380
MIDIBase
MPU-401
300/310/320/330
Table 5-2
82C931 Register Map
I/O Address
Register Name (Type)
SBBase+00h (or
ALBase+00h)
Left FM Status Port (RO)
SBBase+00h (or
ALBase+00h)
Left FM Register Address Port (WO)
SBBase+01h (or
ALBase+01h)
Left FM Data Port (WO)
SBBase+02h (or
ALBase+02h)
Right FM Register Address Port (WO)
SBBase+03h (or
ALBase+03h)
Right FM Data Port (WO)
SBBase+04h
Mixer Address Port (WO)
SBBase+05h
Mixer Data Port (R/W)
SBBase+06h
DAP Reset (WO)
SBBase+08h
FM Status Port (RO)
SBBase+08h
FM Register Address Port (WO)
SBBase+09h
FM Data Port (WO)
SBBase+0Ah
DAP Read Data (RO)
SBBase+0Ch
DAP Write Data/Cmd (WO)
SBBase+0Ch
DAP Write Buffer Status (RO)
SBBase+0Eh
DAP Output Buffer Status (RO)
WSBase+00h-03h
Configuration (WO)
WSBase+00h-03h
Version (RO)
WSBase+04h
Codec Index Reg (R/W, exists in Codec and shadowed in 82C931)
WSBase+05h
Codec Indexed Data Reg (R/W, exists in Codec only)
WSBase+06h
Codec Status Reg (R/W, exists in Codec only)
WSBase+07h
Codec Direct Data (R/W, exists in Codec only)
200h-201h
Game Port (R/W)
0F8Dh
MCBase/Password Register - Specifies:
MC Index Port Address (R/W)
MC Data Port Address (R/W)
380-383/388-38B
OPL4 (R/W)
388-38F
OPL5 (R/W)
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(3) To access MCIR1-23, write the corresponding register
index into the address access port and read (or write) the
data from (or to) the data access port. This read or write
is only possible if the correct password (E4h) has been
written into Port 0F8Dh, or is disabled (0F8Dh[7] = 1).
Table 5-3
Tables 5-3 through 5-5 illustrate the necessary steps to
access MCIR1-23. Table 5-6 gives the bit formats for the
MCIR1-23.
MCBase, Direct MC Register
7
6
5
4
Port 0F8Dh
3
2
1
0
MCBase Register (WO)
Pass word protection for
access to
address or data
port:
Reserved
These bits specify the address for
MCIdx[8:4] and MCData[8:4]: (Refer to Table 5-4.)
Address range = 00000 through 11111
0 = Enable
1 = Disable
Table 5-4
15
McBase, Index (MCIndx) and Data (MCData) Ports Address Range
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
1
1
1
1
Index Port Address [15:0]
0
0
0
0
1
1
1
Specified by MCBase[4:0]
(Refer to Table 5-3)
Data Port Address [15:0]
0
0
0
Table 5-5
0
1
1
1
Specified by MCBase[4:0]
(Refer to Table 5-3)
MCIdx and MCData Registers
7
6
5
0
0
0
4
3
2
1
0
MCIdx
Specifies which MCIR register is to be accessed.
00000 = Disable
00001 = MCIR1:Base/Type Configuration
00010 = MCIR2: Reserved
00011 = MCIR3: SB/WSS Configuration
00100 = MCIR4: User Programmable GP
00101 = MCIR5: Option
00110 = MCIR6: MIDI Interface
00111 = MCIR7: Semaphore Software
01000 = MCIR8: Reserved
01001 = MCIR9: Test Control
01010 = MCIR10: Test Control
01011 = MCIR11: Status
01100 = MCIR12: Test
01101 = MCIR13: PNP Status
01110 = MCIR14: PNP CSN
01111 = MCIR15: PNP READ_DATA
10000 = MCIR16: Volume Control
10001 = MCIR17: Serial EEPROM
10010 = MCIR18: CONFIG Status
10011 = MCIR19: FM Control
10100 = MCIR20: GPIO Control
10101 = MCIR21: Serial Audio Control
10110 = MCIR22: Serial Audio Control
10111 = MCIR23: Reserved
Remaining combinations = Reserved
MCData (refer to Table 5-6)
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82C931
Table 5-6
MC Indirect Registers
7
6
5
4
MCIR1
3
2
1
0
Base/Type Configuration Register
Sound Blaster
I/O base
address
(SBBase):
Reserved
Windows Sound System I/O base
address (WSBase):
00 = 530
01 = E80
10 = F40
11 = 640
CD-ROM interface:
Game port:
The sense of these bits is reversed during writes.
To disable CD, write b’011’.
0 = Disable
1 = Enable
000 = Disabled
100 = Secondary IDE
All others = Reserved
0 = 220
1 = 240
MCIR2
Default = 06h
BAUD 96 register
Reserved
Default = 00h
BAUD96:
This bit could
be used by PDA
devices to communicate with
other devices
Set to 0.
Reserved
Set to 0.
0 = Disabled,
normal MIDI
UART in RXD
pin.
1 = Enabled,
9600 baud rate
UART in RXD
pin
MCIR3
Sound Blaster/Windows Sound System Configuration Register
Reserved:
Must be set to
0.
Reserved:
Must be set to 0
for normal operation in WSS.
DAP IRQ select:
000 = Disable
001 = IRQ7
010 = IRQ9
011 = IRQ10
Default = 00h
DAP DMA select:
100 = IRQ11
101 = IRQ5
110 = Reserved
111 = Reserved
000 = Disabled
001 = DRQ0
010 = DRQ1
011 = DRQ3
100 = Disable
101 = DRQ0
110 = DRQ1
111 = DRQ3
DRQ1(1)
DRQ1(1)
DRQ0(1)
DRQ0(1)
(1) If CIR9[2] = 0 (Codec Indirect Register 9, bit 2), then DAP DMA[4:7] can be selected
MCIR4
User Programmable General Purpose Register
Playback FIFO flow control:
00 = Empty
01 = Full-2
10 = Full-4
11 = Not full
OPL select:
00 = OPL2
01 = OPL3
10 = OPL4
11 = OPL5
Digital-Analog
controller zero:
0 = Hold
1 = Clear
Audio:(1)
0 = Disable
1 = Enable
Default = 10h
Sound Blaster version:
00 = 2.1
01 = 1.5
10 = 3.2
11 = 4.4
(1) Bit 2 can also accessed through the MC register or through PNP logic.
MCIR5
Option Register
Reserved
Codec
Expanded
Mode:(1)
0 = Disable
1 = Enable
Sound Blaster
ADPCM:
0 = Disable
1 = Enable
Command FIFO
in Sound
Blaster mode:
0 = Disable
1 = Enable
Default = 00h
Volume effect
for Sound
Blaster Pro
mixer voice volume emulation:
0 = Disable
1 = Enable
DMA watch
dog timer:
0 = Disable
1 = Enable
Reserved
When enabled,
the 82C931 will
generate internal DACK after
the DRQ pending time-up.
(1) Bit 5 must be set in order to access the CIR16-31, the Expanded Mode of the Codec Indirect Registers. Refer to Table 5-9 and Table 5-11.
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82C931
Table 5-6
MC Indirect Registers (cont.)
7
6
5
4
MCIR6
3
2
1
MIDI Interface Register (WO)
MPU-401 base address select:
MPU-401:
00 = 330
01 = 320
0 = Disable
1 = Enable
10 = 310
11 = 300
MPU-401 interrupt select:
00 = IRQ9
01 = IRQ10
Default = 00h
Reserved
10 = IRQ5
11 = IRQ7
Windows
sound system
mode:
0 = Disable
1 = Enable
MCIR7
Semaphore Software Register (Software use only)
D7
D6
D5
D4
D3
0
D2
Sound Blaster
mode:
0 = Disable
1 = Enable
Default = 00h
D1
D0
MCIR8
Reserved Register
Default = 00h
MCIR9
Test Control Register
Default = 00h
Digital
power-down:
Analog
power-down:
0 = Normal
1 = Powerdown
0 = Normal
1 = Powerdown
Reserved
Software
reset:
0 = Disable
1 = Enable
MCIR10
Test Control Register
Playback reset:
0 = Normal
Capture reset:
0 = Normal
PNP test mode:
Default = 00h
Reserved
0 = Normal
1 = Reset (play- 1 = Reset (cap- 1 =
back data
ture data
path clear,
path clear,
active high)
active high)
Test (PNP
logic is set
to Sleep
mode)
MCIR11
Status Register (RO)
Default = 00h
Playback DMA
pending?
Capture DMA
pending?
MPU interrupt
pending?
CD interrupt
pending?
Capture interrupt pending?
Playback interrupt pending?
Playback FIFO
empty?
Capture FIFO
empty?
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
MCIR12
Test Register
Reserved
Digital test
mode output
high/low byte
select (WO)
MCIR13
Default = 00h
Digital test mode output select (WO)
PNP Status Register (RO)
CSN not zero active high:
1 = PNP configuration manager assigned
a CSN to
82C931.(1)
Modem interface logical
device:
0 = Disable
1 = Enable
IDE logic
device:
MC logical
device:
0 = Disable
1 = Enable
0 = Disable
1 = Enable
CONFIG mode:
1 = 82C931’s
PNP logic is in
the CONFIG
mode
Default = 01h
ISOLATE
mode:
1 = 82C931’s
PNP logic is in
the ISOLATE
mode
SLEEP mode:
1 = 82C931’s
PNP logic is in
the SLEEP
mode
WAIT4KEY
mode:
1 = 82C931’s
PNP logic is in
the WAIT4KEY
mode
(1) When a CSN is assigned to the 82C931, it switches to the PNP mode and the resource configuration is controlled through the PNP registers.
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82C931
Table 5-6
MC Indirect Registers (cont.)
7
6
5
4
MCIR14
3
2
1
PNP CSN Register (RO)
0
Default = 00h
PNP card select number: This registers shows the CSN assigned to the 82C931 by the PNP configuration manager.
MCIR15
PNP Read Port Address Register (RO)
Default = 00h
PNP READ_DATA port: This registers shows the READ_DATA port assigned by the PNP configuration manager.
MCIR16
Reserved
Volume Control Register
Push-bottom
volume control
interrupt enable
UP bottom is
pushed?
DOWN bottom
is pushed?
0 = No
0 = No
1 = Yes
1 = Yes
This bit is
cleared after a
read.
This bit is
cleared after a
read.
MCIR17
Master volume
mute control
(active high)
External serial
EEPROM
clock:
External serial
EEPROM
data out:
External serial
EEPROM
data out:
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
Connected to
DIN of external
EEPROM
Connected to
DIN of external
EEPROM
MCIR18
0 = Disable
1 = Enable
When write to
change:
Volume control interrupt select:
00 = Disable
01 = IRQ5
10 = IRQ10
11 = IRQ11
Serial EEPROM Control Register
External serial
EEPROM chip
select:
When read for
status:
Push-bottom
volume control
interrupt status
(RO)
This bit is
cleared after a
read.
Write to external serial
EEPROM:
Modem interface capability
(R/W):
Default = 00h
Default = 00h
External serial
PNP setting
EEPROM
(R/W):
capability (R/W) Read:
When read for
0 = enabled
status:
1 = disabled
0 = Disable
Write:
1 = Enable
0 = disabled
When write to
1 = enabled
change:
Note:the polar0 = Enable
ity of the read
1 = Disable
is the opposite
Note: read
of the write.
polarity is the
opposite of
write’s.
CONFIG Status Register
ASIO function:
Reserved
0 = Disable
1 = Enable
0 = Default
Mode 0 status
(RO): reflects
931 pin#11 setting.
Reserved
Default = xxh
Chip Revision ID (RO)
Silicon rev. 0.1 = 0x8
Silicon rev. 1.1 = 0x9
0 = 931-AD for
adapter
1 = 931-MD for
motherboard
0 = Enable
1 = Disable
Note: read
polarity is the
opposite of
write’s
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82C931
Table 5-6
MC Indirect Registers (cont.)
7
6
5
4
MCIR19
3
2
1
FM Control Register
IDE IRQ input
routed to IRQ
output:
SDHOE
function on pin
43 when configured for MB
Mode:
0 = Disable
1 = Enable
Reserved
IRQ3, IRQ4:
Default = xxh
MEGA bass:
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0
OPTi mode for
enhanced FM
features:
0 = Disable
1 = Enable
External FM
select:
0 = Disable
1 = Enable
0 = Disable
1 = Enable
MCIR20
GPIO Control Register 0
GPIO3
mapping:
0 = Pin 42
931-AD
GPIO2
mapping:
GPIO2
pin type:
GPIO1
mapping:
GPIO1
pin type:
GPIO0
mapping:
GPIO0
pin type:
0 = Input
1 = Output
0 = Pin 41
931-AD
0 = Input
1 = Output
Pin 11 for
931-AD and
931-MB
0 = Input
1 = Output
Pin 43 for
931-AD and
931-MB
0 = Input
1 = Output
1 = Pin 35
931-MB
1 = Pin 36
931-MB
Note:
Default = 00h
GPIO3
pin type:
GPIO function is available only when the specified pin is not being used for another function.
MCIR21
Serial Audio Control Register 0
Default = 00h
CTL_SEL[1:0]
P2S_SEL[1:0]
SPCDSEL
ADCSEL
FDACSEL
DACSEL
ASIO shift clock selection
SAO data source selection
00/11 = Use the shift clock from
internal FS
00/11 = From DMA Playback
Enables dual
playback
Selects DMA
data capture
source
Selects FDAC
data source
Selects DAC
data souce
01 = Use FM timing
10 = From ADC, captured from
analog section
0 = FDAC
takes FM data
0 = DMA playback
1 = FDAC
takes SADI (if
SPCDSEL=0),
2nd DMA playback data (if
SPCDSEL=1)
1 = SAI
10 = Use external SCLK
01 = From FM
0 = 2nd DMA
channel is used
for DMA capture
1 = 2nd DMA is
used with 1st
DMA channel
for DMA playback
MCIR22
0 = ADC data
(from analog
section)
1 = SAI data
Serial Audio Control Register 1
Reset
ASIO:
ASIO test
mode:
0 = Normal
1 = Reset
0 = Normal
1 = Test
F16
CLK32
Specify ASIO
sample period
data location:
Number of
SLCKs in a
sample period
(delay-mode or
pulse-mode
ASIO only)
0 = Last 16 bits
of the L/R half
sample period
1 = First 16/17
bits of L/R half
sample period
0 = 32
1 = >32
SCLK
polarity:
Default = 00h
FSYNC
polarity:
0 = Reverse
0 = Reverse
1 = No changed 1 = No changed
PULSE
Pulse mode
type of serial
data
(AT&T7525
comp or
CS8412 DSP)
0 = Not activated
1 = Activated
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82C931
Table 5-6
7
MC Indirect Registers (cont.)
6
5
4
MCIR23
3
2
1
0
Serial Audio Clock/Output Control Register
Default = 00h
ASDOOE
SCLKOE
FSYNCOE
MCLKEN
MCLKSEL[1:0]
CLKSEL[1:0]
ADO direction
control
SCLK direction
control
FSYNC direction control
Master clock divider selection
00 = asdo_clk/8
Selects shift clock for serial audio
data output (sclk_out)
0 = Input
0 = Input
0 = Input
External MCLK
enable (fed
through ASDO)
01 = asdo_clk/4
00 = mclk/8
1 = Output
1 = Output
1 = Output
0 = Disabled
10 = asdo_clk/2
01 = mclk/4
11 = asdo_clk/1
10 = mclk/2
1 = Enabled
11 = mclk/1
MCIR24
JRDY/Game
Port IRQ
Readback of ’1’
indicates the
game port
counters are
stopped and the
interrups is generated. The IRQ
is cleared by
writing a ’1’ to
this location.
Game Port Counter Setup and Status Register
Default = 00h
SOUNDIRQ
GPIRQEN
GPWPEN
ACTBY
ACTBX
ACTAY
ACTAX
Shows the status of the audio
IRQ, a ’1’ indicates there is a
soundIRQ
IRQ generation
when the game
port counter is
finish counting
Auto game port
trigger (20x
write)
By axis counter
enable
Bx axis counter
enable
Ay axis counter
enable
Ax axis counter
enable
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
0 = Disabled
1 = Enabled
1 = Enabled
MCIR25
Game Port Counter Values Register
Default = xxh
GPCOUNT[7:0]
Hardware counter values in H-byte L-byte fashion (16-bit). The sequence will be:
Joystick A-X axis
Joystick A-Y axis
Joystick B-X axis
Joystick B-Y axix
The count value will be changed automatically upon each read of this register. If that particular joystick axis is maksed (disabled), the count
will skip accordingly.
MCIR26
JPTSTEN
Game port
counter test
mode, counter
toggled by
14.318MHz
(default=1MHz)
0 = Disabled
1 = Enabled
FDAC Data Control Register
Reserved
VCPIN
ASWTST
Special volume
FDAC data
control pins
auto-switching
move the pins timer test mode,
to
TxD timer togup/down=GD5/
gled by
4 (normal:
14.318MHz
up/down =
(default =
GD7/6
31KHz)
Default = 00h
FDACMUL
FMMUL
FMDIV
AUTOSW
Multiply FDAC
data by 2
Multiply FM
data by 2
Divide FM data
by 2
0 = Disabled
0 = Disabled
0 = Disabled
1 = Enabled
1 = Enabled
1 = Enabled
0 = Disabled
0 = Disabled
Auto-detect of
TxD activity to
switch the
FDAC data
between FM
and serial
audio (which
comes from
TxD
1 = Enabled
1 = Enabled
0 = Disabled
1 = Enabled
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5.3
SBBase Register
SBBase is mainly used to access the Digital Audio Processor
(DAP) registers, however, as shown in Table 5-7 other types
of registers are also accessible through SBBase. The indexing scheme is the same as when accessing MCBase regis-
Table 5-7
ters (CPU Direct I/O R/W). Note that in Table 5-7, which gives
the SBBase register bit formats, some registers may also be
accessed through ALBase. However, use only one Base register for accessing.
SBBase Registers for FM and DAP Applications
7
6
5
4
3
SBBase+00h (or ALBase+00h)
Left FM Status Register (RO)
SBBase+00h (or ALBase+00h)
Left FM Address Port Register (WO)
SBBase+01h (or ALBase+01h)
Left FM Data Port Register (WO)
SBBase+02h (or ALBase+02h)
Right FM Address Port Register (WO)
SBBase+03h (or ALBase+03h)
Right FM Data Port Register (WO)
SBBase+04h
Mixer Address Port Register (WO)
SBBase+05h
Mixer Data Port Register (WO)
SBBase+06h
DAP Reset Register
Don't care
2
1
0
DAP software
reset at end of
the I/O write
command:
0 = Disable
1 = Enable(1)
(1) When bit 0 is enabled, it sets a software reset flag. This software reset is terminated by performing another write at this location with bit 0
= 0. A system reset will reset the software reset flag, thus terminating the software reset
SBBase+08h
FM Status Port Register (RO)
SBBase+08h
FM Address Port Register (WO)
SBBase+09h
FM Data Port Register (WO)
SBBase+0Ah
DAP Read Data Register (RO)
SBBase+0Ch
DAP Data/Command Register (WO)
SBBase+0Ch
DAP Write Buffer Status Register (RO)
DAP Input
buffer full:(1)
SBBase+A[6:0]
0 = Empty
1 = Full
(1) This flag is set when the host CPU writes data in the input data bus buffer and cleared when the data is read by the internal DAP.
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Table 5-7
SBBase Registers for FM and DAP Applications (cont.)
7
6
5
SBBase+0Eh
4
3
2
1
0
DAP Output Buffer Status Register (RO
DAP output
buffer is full:(1)
Output Buffer
0 = Empty
1 = Full
(1) This flag is set in the DAP when data is written in the output data bus buffer and cleared when the host CPU or the DMA controller reads
the data in the output data bus buffer.
Note:
Reading this register will also clear the Digital Audio Processor interrupt request.
5.4
WSBase Register
Two types of registers can be accessed through WSBase:
• Windows Sound System (WSS) and Codec registers
These registers are accessed through the WSBase register
and use the same type of indexing scheme as MCBase (CPU
Table 5-8
WSBase Registers for Windows Sound System Applications
7
6
WSBase+00h-03h
IRQ sense
source:
0 = Normal
1 = auto-interrupt selection
WSBase+00h-03h
0 = DRQ0/1/3
and
IRQ7/9/10/
11 available
5
4
3
2
1
0
WSS Configuration Register (W0)
Reserved
Channel
available:
Direct I/O R/W). The bit formats for WSS-related registers are
given in Table 5-8 and Table 5-9 shows the Codec-related
registers.
Default = 00h
WSS IRQ select:
WSS DRQ select:
000 = Disable
001 = IRQ7
010 = IRQ9
011 = IRQ10
100 = IRQ11
101 = IRQ5
110 = Reserved
111 = Reserved
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
WSS Version Register (R0)
IRQ sense:
Playback
Disable
DRQ0
DRQ1
DRQ3
Disabled
DRQ0
DRQ1
DRQ3
Capture
Disable
Disable
Disable
Disable
DRQ1
DRQ1
DRQ0
DRQ0
Default = 00h
Version: 04h
0 = No interrupt
1 = WSS interrupt active
1 = DRQ1/3 and
IRQ7/9
available
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Note that at the Codec Index Address Register
(WSBase+04h), bits 4 through 0 are used as the index
address for accessing the Codec Indirect Registers (CIR). A
write to or a read from the Codec Indexed Data Register
(WSBase+05h) will access the Indirect Register which is
indexed by the value most recently written to the Codec Index
Address Register.
Table 5-9
There are 31 Codec Indirect Registers, CIR0-CIR15 are
accessed normally. To access CIR16 through CIR31,
Expanded Mode registers, MCIR12[5] = 1 (MCBase Indirect
Register, bit 5). Table 5-10 gives the bit formats for CIR0CIR15 and Table 5-11 shows CIR16-CIR31.
WSBase Register for Codec/Mixer Applications
7
6
WSBase+04h
5
4
3
2
1
Codec Index Address Register (R/W, exists in Codec and shadowed in 82C931)
Initialization:
Mode change:
This bit is set
when the
codec is in a
state which cannot respond to
parallel bus
cycles.(1)
0 = Disable
1 = Enable
Transfer
request:(2)
0
Default = 00h
Index address:
These bits specify which Codec Indirect Register (CIR) is to be accessed.
Note CIR16 through CIR31 are Expanded Modes and require that MCIR12[5] = 1.
(Refer to Table 5-10 and Table 5-11 for these registers bit formats.)
0 = Transfers
enabled during
interrupt
1 = Transfers 00000 = CIR0: MIXOUTL Output Cntrl
disabled by
00001 = CIR1: MIXOUTR Output Cntrl
interrupt
00010 = CIR2: CDL Input Cntrl
00011 = CIR3: CDR Input Cntrl
00100 = CIR4: FML Input Cntrl
00101 = CIR5: FMR Input Cntrl
00110 = CIR6: DACL Input Cntrl
00111 = CIR7: DACR Input Cntrl
01000 = CIR8: Fs & Playback Data Format
01001 = CIR9: Interface Configuration
01010 = CIR10: Pin Cntrl
01011 = CIR11: Error Status & Initialization
01100 = CIR12: Mode and ID (Mode 2 Bit)
01101 = CIR13: Reserved
01110 = CIR14: Playback Upper Base
01111 = CIR15: Playback Lower Base
Expanded Mode Registers
10000 = CIR16: AUXL Input Cntrl
10001 = CIR17: AUXR Input Cntrl
10010 = CIR18: LINEL Input Cntrl
10011 = CIR19: LINER Input Cntrl
10100 = CIR20: MICL Input Cntrl
10101 = CIR21: MICR Input Cntrl
10110 = CIR22: OUTL Gain Cntrl
10111 = CIR23: OUTR Gain Cntrl
11000 = CIR24: Reserved
11001 = CIR25: Reserved
11010 = CIR26: Reserved
11011 = CIR27: Reserved
11100 = CIR28: Capture Data Format
11101 = CIR29: Reserved
11110 = CIR30: Capture Upper Base
11111 = CIR31: Capture Lower Base
(1) Immediately after reset and once the codec has left the initialization state, the initial value of this register will be "0100 0000" (40h). During
codec initialization, the Codec Index Register cannot be written and is always read 1000 0000 (80h).
(2) When bit 5 is set, DMA transfers cease when bit 0 of the Codec Status Register (WSBase+06h) = 1.
WSBase+05h
Codec Indexed Data Register (R/W, exists in Codec only)
Default = 00h
Contains the contents of the Codec register referenced by the Index Data Register.
During codec initialization, this register cannot be written and is always read as "1000 0000" (80h).
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Table 5-9
7
WSBase Register for Codec/Mixer Applications (cont.)
6
5
WSBase+06h
PIO capture
data is ready for
upper or lower
byte (RO):
0 = Lower
1 = Upper (or
any 8-bit mode)
4
3
2
1
Codec Status Register (R/W, exists in Codec only)
PIO capture
data is waiting
for right or left
channel ADC
(RO):
0 = Right
1 = Left (or
mono)
PIO Capture
Data Register
contains data
ready for reading by host
(RO):(1)
Sample
over/underrun
(RO):
PIO playback
data is needed
for upper or
lower byte
(RO):
Indicates that
the most recent
sample was not
0 = Lower
1 = Upper (or
0 = Stale ADC serviced in time;
data (do not re- therefore either any 8-bit mode)
an overrun for
read)
1 = Fresh ADC ADC capture or
underrun for
data (ready for
DAC playback
next host data
has occurred.(2)
read)
PIO playback
data is needed
for right or left
channel DAC
(RO):
0 = Right
1 = Left (or
mono)
0
Default = 44h
PIO Playback
Data Register
ready for more
data (RO):(1)
Interrupt:
0 = Disable
1 = Enable
0 = Valid DAC
data (do not
overwrite)
1 = Stale DAC
data (ready for
next host data
write value)
(1) These bits (5 and 1) should only be programmed when direct programmed I/O data transfers are desired.
(2) If both capture and playback are enabled, the source which set bit 4 ca be determined by reading COR and PUR. Bit 4 changes on a sample-by-sample basis.
Note:
Bits 5, 1, and 0 can change asynchronously to host accesses. The host may access this register while the bits are transitioning. The
host read may return a zero value just as these bits are changing (e.g., a value of 1 would not be read until the next host access).
This register’s initial state after reset is "1100 1100".
WSBase+07h
Codec Direct Data Register - Capture Mode (RO, exists in Codec only)
Default = 00h
The Codec Direct Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register
(PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0).
During initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read "1000 0000" (80h).
PIO Capture Data Register:
This is the control register where capture data is read during programmed I/O data transfers.
The reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. The
exact byte which is next to be read can be determined by reading the Status Register. Once all relevant bytes have been read, the state
machine will stay pointed to the last byte of the sample until a new sample is received from the ADCs. Once this has occurred, the state
machine and status register will point to the first byte of the sample. Until a new sample is received, reads from this register will return the most
significant byte of the sample.
WSBase+07h
Codec Direct Data Register - Playback Mode (WO, exists in Codec only)
Default = 00h
The Codec Direct Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register
(PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0).
During initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read "1000 0000" (80h).
PIO Playback Data Register:
This is the control register where playback data is written during programmed I/O data transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the
sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored. The state machine is reset when the
current sample is sent to the DACs.
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Table 5-10
Codec Indirect Registers
D7
D6
D5
CIR0
D4
D3
D2
D1
D0
MIXOUTL Output Control Register
Source select:
00 = LINE
01 = CD
10 = MIC
11 = MIXER
MIC +20dB
Gain:
Reserved
Gain select for MIXOUTL (dB):
0000 = 0
0001 = +1.5
0010 = +3.0
0011 = +4.5
0100 = +6.0
0101 = +7.5
0 = Disable
1 = Enable
CIR1
Default = 00h
0110 = +9.0
0111 = +10.5
1000 = +12.0
1001 = +13.5
1010 = +15.0
1011 = +16.5
1100 = +18.0
1101 = +19.5
1110 = +21.0
1111 = +22.5
MIXOUTR Output Control Register
Source select:
00 = LINE
01 = CD
10 = MIC
11 = MIXER
MIC +20dB
Gain:
Reserved
Default = 00h
Gain select for MIXOUTR (dB):
Refer to CIR0[3:0] for decode.
0 = Disable
1 = Enable
CIR2
CDL Input Control Register
Mute:
Reserved
Gain select for CDL (dB):
0 = Disable
1 = Enable
0000 = +12
0001 = +9
0010 = +6
0011 = +3
0100 = 0
0101 = –3
Note:
CIR3
Default = 88h
0110 = –6
0111 = –9
1000 = –12
1001 = –15
1010 = –18
Reserved
1011 = –21
1100 = –24
1101 = –27
1110 = –30
1111 = –33
This decode is also applicable for the MIC, LINE, AUX, and
FM inputs.
CDR Input Control Register
Mute:
Reserved
0 = Disable
1 = Enable
Gain select CDR (dB):
Default = 88h
Reserved
Refer to CIR2[4:1] for decode.
CIR4
FML Input Control Register
Mute:
Reserved
0 = Disable
1 = Enable
Gain select FML (dB):
Default = 88h
Reserved
Refer to CIR2[4:1] for decode.
CIR5
FMR Input Control Register
Mute:
Reserved
0 = Disable
1 = Enable
Gain select FMR (dB):
Default = 88h
Reserved
Refer to CIR2[4:1] for decode.
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Table 5-10
D7
Codec Indirect Registers (cont.)
D6
D5
D4
CIR6
D3
D2
D1
D0
DACL Input Control Register
Mute:
Reserved
Default = 80h
Gain select for DAC inputs (dB):
0 = Disable
1 = Enable
*00000 = 0
00001 = –1.5
00010 = –3.0
00011 = –4.5
00100 = –6.0
00101 = –7.5
00110 = –9.0
00111 = –10.5
CIR7
01000 = –12.0
01001 = –13.5
01010 = –15.0
01011 = –16.5
01100 = –18.0
01101 = –19.5
01110 = –21.0
01111 = –22.5
10000 = –24.0
10001 = –25.5
10010 = –27.0
10011 = –28.5
10100 = –30.0
10101 = –31.5
10110 = –33.0
10111 = –34.5
11000 = –36.0
11001 = –37.5
11010 = –39.0
11011 = –40.5
11100 = –42.0
11101 = –43.5
11110 = –45.0
11111 = –46.5
DACR Input Control Register
Mute:
Reserved
Gain select for DAC inputs (dB):
0 = Disable
1 = Enable
Refer to CIR6[4:0] for decode.
CIR8
Fs and Playback Data Format Register
Audio data format - linear PCM or companded
for all input and output data
(used in conjunction with bit 5):(1)
0 = Mono
1 = Stereo
Default = 00h
Clock frequency divide / audio sample
rate frequency:
Stereo/mono:(2)
000 = Linear, 8-bit unsigned
001 = µ-law, 8-bit companded
010 = Linear, 16-bit two’s complement, Little Endian
011 = A-Law, 8-bit companded
100 = Reserved
101 = ADPCM, 4-bit, IMA compatible
110 = Linear, 16-bit two’s complement, Big Endian
111 = Reserved
Note:
Default = 80h
0000 = 8.0kHz
0010 = 16.0kHz
0100 = 27.42857kHz
0110 = 32.0kHz
1000 = Reserved
1010 = Reserved
1100 = 48.0kHz
1110 = 9.6kHz
0001 = 5.5125kHz
0011 = 11.025kHz
0101 = 18.9kHz
0111 = 22.05kHz
1001 = 37.8kHz
1011 = 44.1kHz
1101 = 33.075kHz
1111 = 6.615kHz
Bit 7 is not available in Mode 1 (forced to 0).
(1) SB/WSS mode switch: In Sound Blaster mode, the software driver should set CDF to 8 bit PCM mode (R8: FM1,FM-,C_L).
(2) Selecting stereo results with alternating samples representing left and right audio channels. Mono playback plays the same audio sample
on both channels. Mono capture only captures data from the left audio channel.
Note:
The contents of this register can only be changed if the mode change bit (WSBase+04h[6]) is enabled (set to 1). Writes to this register
without the mode change bit enabled will have no affect.
CIR9
Interface Configuration Register
Transfer capture data via
DMA or PIO:
Transfer playback data via
DMA or PIO:
0 = DMA
1 = PIO
0 = DMA
1 = PIO
Reserved
Autocalibrate:
0 = Disable
1 = Enable
(autocalibration
after power
down/reset or
mode change
Default = 00h
DMA channel
mode:(1)
0 = Dual
1 = Single
Capture data in
format
selected:(2)
Playback data
in format
selected:(3)
0 = Disable
1 = Enable
0 = Disable
1 = Enable
(1) In Sound Blaster mode, bit 2 is set when playback or capture DMA starts and is reset when DMA ends.
(2) The codec generates CDRQ and responds to CDAK# when bit 1 = 1 and bit 7 = 0. If bit 7 = 1, bit 1 enables PIO capture mode.
(3) The codec generates PDRQ and repents to PDAK# when bit 0 = 1 and bit 6 = 0. If bit 6 = 1, bit 1 enables PIO playback mode
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Table 5-10
Codec Indirect Registers (cont.)
D7
D6
D5
D4
CIR10
D3
D2
D1
D0
Pin Control Register
Default = 00h
Reserved
Interrupt
pin:(1)
Reserved
0 = Disable
1 = Enable
(Interrupt pin
goes active high
when the number of samples
programmed in
the Base Count
Register is
reached.)
2. In Sound Blaster mode, the software driver should set bit 1 = 1.
CIR11
Error Status and Initialization Register (RO)
Capture
overrun:(1)
Playback
underrun:(1)
Autocalibration
state:
This bit is set
when capture
data has not
been read by
the host before
the next sample arrives. The
sample being
read will not be
overwritten by
the new sample. The new
sample is
ignored.
This bit is set
when playback
data has not
arrived from
the host in time
to be played.
This results in a
midscale value
sent to the
DACs.
0 = In progress
Current status
of PDRQ and
CDRQ:
1 = Not in
progress
0 = Inactive
(low)
Default = 00h
Indicates under/over range on
right input channel:(1)
Indicates under/over range on
left input channel:(1)
0 = Less than –1dB under range
0 = Less than –1dB under range
1 = Between –1dB and 0dB under 1 = Between –1dB and 0dB under
range
range
1 = Active (high) 2 = Between 0dB and +1dB over
range
2 = Between 0dB and +1dB over
range
3 = Greater than +1dB over range 3 = Greater than +1dB over range
(1) Bit changes on a sample-by-sample basis.
(2) The occurrence of a capture overrun and/or playback underrun is designated in the Status Register's sample overrun/underrun bit
(WSBase+06h[4]). The sample overrun/underrun bit is the logical OR of bits 7 and 6. This enables a polling host CPU to detect an overrun/underrun condition while checking other status bits.
CIR12
ID Register
Default = 0Ah
Reserved
Revision ID (RO):
These bits define the revision level of the codec.
CIR13
Reserved
Default = 00h
CIR14
Playback Upper Base Count Register
Default = 00h
Upper Base Count:
This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register.
Reads from this register return the same value which was written The current count contained in the counters can not be read.
When enabled for SB Mode, this register is used for both the Playback and Capture Base Registers.
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82C931
Table 5-10
D7
Codec Indirect Registers (cont.)
D6
D5
CIR15
D4
D3
D2
D1
Playback Lower Base Count Register
D0
Default = 00h
Lower Base Count:
This byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register.
Reads from this register return the same value which was written The current count contained in the counters can not be read.
When enabled for SD Mode, this register is used for both the Playback and Capture Base Registers.
Table 5-11
7
Expanded Mode CIR
6
5
CIR16
Mute:
Reserved
Reserved
Gain select for LINEL (dB):
LINER Input Control Register
Reserved
0 = Disable
1 = Enable
Default = 88h
Reserved
Default = 88h
Reserved
Default = 88h
Reserved
Gain select for LINER inputs (dB):
Default = 88h
Reserved
Refer to CIR2[4:1] for decode.
CIR20
MICL Input Control Register
MICR mixed
into OUTL:
Reserved
Gain select for MICL (dB):
Default = 88h
Reserved
Refer to CIR2[4:1] for decode.
0 = Disable
1 = Enable
CIR21
Mute:
0
Refer to CIR2[4:1] for decode.
CIR19
0 = Disable
1 = Enable
Gain select for AUXR (dB):
LINEL Input Control Register
Reserved
0 = Disable
1 = Enable
Mute:
1
Refer to CIR2[4:1] for decode.
CIR18
0 = Disable
1 = Enable
Gain select for AUXL (dB):
AUXR Input Control Register
0 = Disable
1 = Enable
Mute:
2
Refer to CIR2[4:1] for decode.
CIR17
Mute:
3
AUXL Input Control Register
0 = Disable
1 = Enable
Mute:
4
MICR Input Control Register
MICL mixed
into OUTR:
Reserved
Gain select for MICR (dB):
Default = 88h
Reserved
Refer to CIR2[4:1] for decode.
0 = Disable
1 = Enable
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82C931
Table 5-11
Expanded Mode CIR (cont.)
7
6
5
CIR22
4
3
2
1
OUTL Output Control Register
Mute:
Reserved
0 = Disable
1 = Enable
Default = 80h
Gain select for OUTL (dB):
00000 = 0
00001 = –3
00010 = –6
00011 = –9
00100 = –12
00101 = –15
00110 = –18
00111 = –21
CIR23
01000 = –24
01001 = –27
01010 = –30
01011 = –33
01100 = –36
01101 = –39
01110 = –42
01111 = –45
10000 = –48
10001 = –51
10010 = –54
10011 = –57
10100 = –60
10101 = –63
10110 = –66
10111 = –69
Reserved
11000 = –72
11001 = –75
11010 = –78
11011 = –81
11100 = –84
11101 = –87
11110 = –90
11111 = –93
OUTR Output Control Register
Mute:
Reserved
0 = Disable
1 = Enable
0
Default = 80h
Gain select for OUTR (dB):
Reserved
Refer to CIR22[5:1] for decode.
CIR24-CIR27
CIR28
Audio data format - linear PCM or companded
for all input and output data
(used in conjunction with bit 5):(1)
Reserved
Default = 00h
Capture Data Format
Default = 00h
Stereo/mono:(2)
Reserved
0 = Mono
1 = Stereo
000 = Linear, 8-bit unsigned
001 = µ-law, 8-bit companded
010 = Linear, 16-bit two’s complement, Little Endian
011 = A-Law, 8-bit companded
100 = Reserved
101 = ADPCM, 4-bit, IMA compatible
110 = Linear, 16-bit two’s complement, Big Endian
111 = Reserved
Note:
Bit 7 is not available in Mode 1 (forced to 0).
(1) SB/WSS mode switch: In Sound Blaster mode, the software driver should set CDF to 8 bit PCM mode (R8: FM1,FM-,C_L).
(2) Selecting stereo results with alternating samples representing left and right audio channels. Mono playback plays the same audio sample
on both channels. Mono capture only captures data from the left audio channel.
Note:
The contents of this register can only be changed if the mode change bit (WSBase+04h[6]) is enabled (set to 1). Writes to this register
without the mode change bit enabled will have no affect.
CIR29
Reserved
Default = 00h
CIR30
Capture Upper Base Count
Default = 00h
Upper Base Count:
This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register.
Reads from this register return the same value which was written.
CIR31
Capture Lower Base Count
Default = 00h
Upper Base Count:
This byte is the lower byte of the base count register containing the eight most significant bits of the 16-bit base register.
Reads from this register return the same value which was written.
OPTi
®
Page 44
912-3000-035
Revision: 2.1
82C931
6.0
Electrical Specifications
Stresses above those listed in the following tables may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification are not implied.
6.1
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
4.5
5.5
V
AVCC
Analog Supply Voltage
4.75
5.25
V
VIN
Input Voltage
–0.5
VCC + 0.5
V
VOUT
Output Voltage
–0.5
VCC + 0.5
V
TOP
Operating Temperature
0
70
°C
–40
125
°C
1000
V
Storage Temperature
TSTG
ESD
*
*
6.2
ESD Tolerance (Human Body
Model MIL883C, 3015.7, Notice 8)
ESD senstive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test
equipment and can discharge without detection. Although the 82C931 features ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
DC Characteristics: 5.0 Volt (VCC = 5.0V ±5%, TA = 0°C to +70°C)
Symbol
Parameter
Min
Max
Unit
Condition
VIL
Low Level Input Voltage
–0.3
0.8
V
VCC = 5.5V
VIH
High Level Input Voltage
2.4
VCC + 0.3
V
VCC = 4.5V
VIHa
High Level Input Voltage for RESET
3.5
VCC + 0.3
V
VCC = 4.5V
VOL
Low Level Output Voltage
0.2
V
IOL = 4mA, VCC = 4.5
VOH
High Level Output Voltage
5.5
V
IOH = –4mA VCC = 5.5V
IIL
Input Leakage Current
10
µA
VCC = 5.5V
IILa
Input Leakage Current with 5K
ohm Pull-up Resistor
–100
–500
µA
VIN = 0V
IILb
Input Leakage Current with 50K
ohm Pull-up Resistor
–10
–50
µA
VIN = 0V
IOL
Output Leakage Current
10
µA
VCC = 5.5V
IPD
Static or Power-down Mode Current
300
µA
VCC = 5.5V
VCC – 0.5
OPTi
®
912-3000-035
Revision: 2.1
Page 45
82C931
6.3
General Specifications: 5.0 Volt (VCC = 5.0V ±5%, TA = 0°C to +70°C)
Symbol
Parameter
Min
IIL
Low Level Input Current
IIH
Typ
Max
Unit
Condition
–10
10
µA
VIN = GND
High Level Input Current
–10
10
µA
VIN = VCC
IOZ
Tristate Output Leakage Current
–10
10
µA
VOUT = 0/VCC
V-
Schmitt Negative Threshold
0.8
1.5
1.3
2.5
V
TTL-STATIC
CMOS-STATIC
V+
Schmitt Positive Threshold
1.4
2.5
2.1
3.5
V
TTL-STATIC
CMOS-STATIC
VH
Schmitt Hysteresis
V
TTL-STATIC
CMOS-STATIC
VIL
low Level Input Voltage
V
TTL-STATIC
VIH
High Level Input Voltage
V
TTL-STATIC
VOL
Low Level Output Voltage
V
TTL-STATIC
VOH
High Level Output Voltage
2.4
V
TTL-STATIC
RPD
Pull-down Resistance
50
200
KΩ
VIN = VCC
RPU
Pull-up Resistance
50
200
KΩ
VIN = VCC
CIN
Input Capacitance
5
pF
Frequency = 1MHZ @ 0V
COUT
Output Capacitance
5
pF
Frequency = 1MHZ @ 0V
CIO
Bidirectional Capacitance
5
pF
Frequency = 1MHZ @ 0V
IOS
Short Circuit Output Current
25
mA
VOUT = 0V
IKLU
I/O Latch-Up Current
100
mA
V < GND, V > VCC
VESD
Electrostatic Protection
2000
V
0.6
1.0
0.8
2.0
0.4
2
C = 100pF, R = 1.5KΩ
OPTi
®
Page 46
912-3000-035
Revision: 2.1
82C931
6.4
Pin Specifications - Analog (VCC = 5.0V, 25°C)
Pin Name
Parameter
Min
Signal Bandwidth
Input Range
OUTR, OUTL
MIXOUTR,
MIXOUTL
Typ
Max
Unit
Condition
10
0.5
20K
3.0
Hz
V
Sine Wave
Signal Bandwidth
Output Range
10
0.5
20K
3.0
Hz
V
Sine Wave
Load = 10KΩ, 25pF
Signal Bandwidth
Output Range
10
20K
Hz
Sine Wave
V
DC
DC
Inputs
MICR, MICL,
LINER, LINEL,
CDR, CDL,
AUXR, AUXL,
CINR, CINL
Outputs
VREF1
VREF2
6.5
1.75
1.85
Volume Setting
Parameter
Input Gain/Atten. Range:
16 levels (MIC, LINE, CD, AUX)
16 levels (ADC)
32 levels (DAC)
32 levels (LOUT)
Step Size:
16 levels (MIC, LINE, CD, AUX)
16 levels (ADC)
32 levels (DAC)
Min
Typ
Max
Unit
dB
Test Conditions
Input @ 1Hz, 2.5Vpp wrt ACOM
12
22.5
0
0
–33
0
–93
–46.5
dB
2.6
1.3
2.6
2.0
3.0
1.5
3.0
3.0
3.4
1.7
3.4
4.0
1.3
1.5
1.7
90 to -81dB)
(-84 to -93dB)
32 levels (LOUT)
Mute Level
–80
dB
Signal to Noise Ratio
–80
dB
Total Harmonic Distortion
0.04
%
Total Dynamic Range
80
dB
Interchannel Isolation
60
dB
Interchannel Gain Mismatch
Gain Drift
6.6
–0.5
0.5
100
dB
ppm/°C
Analog Characteristics
Test conditions
Temp=25 °C, VDD, VCC=+5v, Input signal= 1kHz sine wave, Analog output passband: 20 Hz to 20kHz, Sample freq = 44.1 kHz
OPTi
®
912-3000-035
Revision: 2.1
Page 47
82C931
DAC test conditions
16-bit linear mode, Full Scale input, 10 kΩ output load, measured at Line Out.
ADC test conditions
16-bit linear mode, 0 dB Gain, Line Input.
6.6.1
Analog Inputs
Parameters
Min
Typ
Max
Units
Input voltage
2.6
2.8
3.1
Vp-p
MIC with 0dB gain
2.6
2.8
3.1
Vp-p
MIC with 20dB gain
0.26
0.28
0.31
Vp-p
10
20
LINE/CD/AUX/CIN
Input impedance
Input capacitance
6.6.2
kΩ
15
pF
Analog Outputs (10kΩ, 25pF)
Parameters
Min
Typ
Max
Units
Full-scale output voltage (OUTR & OUTL)
2.5
2.8
3.1
Vp-p
Vref
1.85
Output impedance
External load impedance
6.6.3
Volts
600
10
W
kΩ
Volume Settings
Parameter
Min
Typ
Max
Units
Master volume step size
1.3
1.5
1.7
dB
Master volume output atten range
Mute level
46.5
dB
80
dB
OPTi
®
Page 48
912-3000-035
Revision: 2.1
82C931
6.6.4
Analog-to-Digital Converters
Parameters
Min
Typ
Resolution
Total dynamic range
75
Max
16
bits
85
dB
THD
.025
Interchannel isolation:
Units
80
%
dB
Line to Line/CD/Aux/Mic
Interchannel gain mismatch
-0.5
Gain drift
6.6.5
+0.5
100
ppm/°C
Digital-to-Analog Converters
Parameters
Min
Typ
Resolution
Total dynamic range
78
Max
bits
95
dB
.022
Interchannel isolation:
80
Interchannel gain mismatch
-0.5
Gain drift
Units
16
THD
6.7
dB
%
dB
+0.5
100
dB
ppm/°C
AC Timings
Symbol
Parameter
Min
Max
Unit
tOSCP
OSC (14.318MHz) Frequency
14.0
14.5
MHz
tOSCH
OSC High Width
32
40
ns
tOSCL
OSC Low Width
32
40
ns
tSCKP
SYSCLK Frequency
8
9
MHz
tSCKH
SYSCLK High Width
50
70
ns
tSCKL
SYSCLK Low Width
55
70
ns
tRST
RESET to RESET#
40
80
ns
tCMDW
IOR#/IOW# Command Width
120
ns
tWDSU
Write Data Setup to IOW# Rising
30
ns
tWDHD
Write Data Hold from IOW# Rising
15
ns
tRAC
Read Access Time
20
Condition
ISA Bus
50
ns
OPTi
®
912-3000-035
Revision: 2.1
Page 49
82C931
Symbol
Parameter
Min
Max
Unit
tASU
Address Setup to IOR#/IOW# Falling
50
ns
tAHD
Address Hold from IOR#/IOW# Rising
30
ns
tDKSU
DACK# Setup to IOR#/IOW# Falling
40
ns
tDKHD
DACK# Hold from IOR#/IOW# Rising
160
ns
tDHR
SD Hold from IOR# Rising
0
20
ns
tDRHD
DRQ Hold from IOR#/IOW# Falling
0
25
ns
tCA
SA to CA Delay
3
20
ns
tXCS
SA to IDECS1#/3#
5
20
ns
tCMDD
IOR#/IOW# to XIOR#/XIOW# Delay
3
20
ns
Condition
CD-ROM
Figure 6-1
RESET and CLK Timing Waveform
tOSCH
tOSCL
OSC
RESET
tRST
RESET#
OPTi
®
Page 50
912-3000-035
Revision: 2.1
82C931
Figure 6-2
CD-ROM I/O Read Cycle
SA[15:0]
tAHD
SD[7:0]
tRDHD
tCMDW
IOR#
tASU
tCA
CA[2:0]
tXCS
IDECSn#
tCMDD
XIOR#
Note: For the above timing, AEN = 0, DRQ = 0, and DACKn# = 1.
Figure 6-3
CD-ROM I/O Write Cycle
SA[15:0]
tAHD
SD[7:0]
tWDSU
tWDHD
tCMDW
IOW#
tASU
tCA
CA[2:0]
tXCS
IDECSn#
tCMDD
XIOW#
Note: For the above timing, AEN = 0, DRQ = 0, and DACKn# = 1.
OPTi
®
912-3000-035
Revision: 2.1
Page 51
82C931
Figure 6-4
DMA Write/Playback Cycle
DRQ
DACKn#
tDKHD
SD[7:0]
tDKSU
tWDHD
tCMDW
IOW#
tCMDD
XIOW#
Note: For the above timing, AEN = 1.
Figure 6-5
DMA Read/Capture Cycle
DRQ
DACKn#
tDKHD
SD[7:0]
tDKSU
tRDHD
tCMDW
IOR#
tCMDD
XIOR#
Note: For the above timing, AEN = 1.
OPTi
®
Page 52
912-3000-035
Revision: 2.1
82C931
7.0
Mechanical Packages
Figure 7-1
100-pin PQFP, Plastic Quad Flat Pack
OPTi
®
912-3000-035
Revision: 2.1
Page 53
82C931
Figure 7-2
Note:
100-pin TQFP, Thin Quad Flat Package
Pinout for TQFP package is identical to pinout of PQFP package.
OPTi
®
Page 54
912-3000-035
Revision: 2.1
OPTi
®
Sales Information
HEADQUARTERS:
OPTi Inc.
888 Tasman Drive
Milpitas, CA 95035
tel: 408-486-8000
fax: 408-486-8011
SALES OFFICES:
Japan
OPTi Japan KK
Murata Building 6F, 2-22-7
Ohhashi Meguro-ku
Tokyo 153, Japan
tel: 81-3-5454-0178
fax: 81-3-5454-0168
Taiwan
OPTi Inc.
9F, No 303, Sec 4, Hsin Yih Road
Taipei, Taiwan, ROC
tel: 886-2-325-8520
fax: 886-2-325-6520
United States
OPTi Inc.
20405 State Highway 249, Ste. #220
Houston, TX 77070
tel: 281-257-1856
fax: 281-257-1825
REPRESENTATIVES:
United States
Alabama/Mississippi
Concord Component Reps
190 Line Quarry Rd., Ste. #102
Madison, AL 35758
tel: 205-772-8883
fax: 205-772-8262
Michigan
Wisconsin
Singapore
Jay Marketing
44752 Helm Street., Ste. A
Plymouth, MI 48170
tel: 313-459-1200
fax: 313-459-1697
Micro-Tex, Inc.
22660 Broadway, Ste. #4A
Waukesha, WI 53186
tel: 414-542-5352
fax: 414-542-7934
New Jersey
Instep Microsolutions Pte Ltd.
18, Tannery Lane, #05-02
Lian Tong Building
Singapore 347780
tel: 65-741-7507
fax: 65-741-1478
International
S-J Associates, Inc.
131-D Gaither Dr.
Mt. Laurel, NJ 08054
tel: 609-866-1234
fax: 609-866-8627
New York
S-J Associates, Inc.
265 Sunrise Highway
Rockville Centre, NY 11570
tel: 516-536-4242
fax: 516-536-9638
S-J Associates, Inc.
735 Victor-Pittsford
Victor, NY 14564
tel: 716-924-1720
North & South Carolina
Switzerland
Legend Electronic Components. Ltd. Datacomp AG
Silbernstrasse 10
Unit 413, Hong Kong Industrial
8953 Dietikon
Technology Centre
Switzerland
72 Tat Chee Avenue
tel: 41-1-740-5140
Kowloon Tong, Hong Kong
fax: 41-1-741-3423
tel: 852-2776-7708
fax: 852-2652-2301
United Kingdom
France
Germany
Lyons Corp.
4812 Fredrick Rd., Ste. #101
Dayton, OH 45414
tel: 513-278-0714
fax: 513-278-3609
Kamaka
Rheinsrasse 22
76870 Kandel
Germany
tel: 49-7275-958211
fax: 49-7275-958220
Lyons Corp.
248 N. State St.
Westerville, OH 43081
tel: 614-895-1447
fax: Same
Georgia
Texas
Concord Component Reps
6825 Jimmy Carter Blvd., Ste. #1303
Norcross, GA 30071
tel: 770-416-9597
fax: 770-441-0790
Axxis Technology Marketing, Inc.
701 Brazos, Suite 500
Austin, TX 78701
tel: 512-320-9130
fax: 512-320-5730
Illinois
Axxis Technology Marketing, Inc.
6804 Ashmont Drive
Plano, TX 75023
tel: 214-491-3577
fax: 214-491-2508
S-J Associates, Inc.
267 Boston Road
Corporate Place, Ste. #3
N. Billerica, MA 01862
tel: 508-670-8899
fax: 508-670-8711
China
Ohio/W. Pennsylvania
Engineered Solutions Ind., Inc.
1000 E. Atlantic Blvd., Ste. #202
Pompano Beach, FL 33060
tel: 305-784-0078
fax: 305-781-7722
Massachusetts
Uniao Digital
Rua Guido Caloi
Bloco B, Piso 3
Sao Paulo-SP, CEP 05802-140 Brazil
tel: 55-11-5514-3355
fax: 55-11-5514-1088
Concord Component Reps
10608 Dunhill Terrace
Raleigh, NC 27615
tel: 919-846-3441
fax: 919-846-3401
Florida
Virginia
S-J Associates, Inc.
900 S. Washington St., Ste. #307
Falls Church, VA 22046
tel: 703-533-2233
fax: 703-533-2236
South America
Braemac Pty. Ltd.
Unit 6, 111 Moore St., Leichhardt
Sydney, 2040 Australia
tel: 61-2-550-6600
fax: 61-2-550-6377
Tekelec Airtronic, France
5, Rue Carle Vernet
92315 Sevres Cedex
France
tel: 33-1-46-23-24-25
fax: 33-1-45-07-21-91
Lyons Corp.
4615 W. Streetsboro
Richfield, OH 44286
tel: 216-659-9224
fax: 216-659-9227
Micro-Tex, Inc.
1870 North Roselle Rd., Ste. #107
Schaumburg, IL 60195-3100
tel: 708-885-8200
fax: 708-885-8210
Australia
India
Spectrum
2 Grange Mews,
Station Road
Launton, Bicester
Oxfordshire,OX6 0DX
UK
tel: 44-1869-325174
fax: 44-1869-325175
MMD
3 Bennet Court,
Bennet Road
Reading
Berkshire, RG2 0QX
UK
tel: 44 1734 313232
fax: 44 1734 313255
Spectra Innovation
Unit S-822 Manipal Centre
47 Dickenson Road
Bangalore 560-042
Kamataka, India
tel: 91-80-558-8323/3977
fax: 91-80-558-6872
Israel
Ralco Components (1994) Ltd.
11 Benyamini St.
67443 Tel Aviv
Israel
tel: 972-3-6954126
fax: 972-3-6951743
Korea
Woo Young Tech Co., Ltd.
5th Floor Koami Bldg
13-31 Yoido-Dong
Youngduengpo-Ku
Seoul, Korea 150-010
tel: 02-369-7099
fax: 02-369-7091
The information contained within this document is subject to change without notice. OPTi Inc. reserves the right to make changes in this manual at any time as well
as in the products it describes, at any time without notice or obligation. OPTi Inc. assumes no responsibility for any errors contained within. In no event will OPTi Inc.
be liable for any damages, direct, indirect, incidental or consequential resulting from any error, defect, or omission in this specification.
Copyright © 1997 by OPTi Inc. All rights reserved. OPTi is a trademark of OPTi Incorporated. All other brand and product names are trademarks or copyrights of
their respective owners.
June 27, 1997
OPTi Inc. · 888 Tasman Drive · Milpitas, CA 95035 · (408) 486-8000
OPTi Inc.
888 Tasman Drive
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
www.opti.com
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