PIC12C67X - Wayne C. Gramlich

PIC12C67X - Wayne C. Gramlich
M
PIC12C67X
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter
Devices included in this Data Sheet:
PIC12C671 and PIC12C672 are 8-bit microcontrollers
with 8-bit A/D Converter packaged in 8-lead packages.
They are based on the 14-bit PIC16/17 architecture.
High-Performance RISC CPU:
• Only 35 single word instructions to learn
• All instructions are single cycle (1 µs) except for
program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 1 µs instruction cycle
Device
EPROM
• Selectable oscillator options:
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
- XT:
Standard crystal/resonator
- HS:
High speed crystal/resonator
- LP:
Power saving, low frequency crystal
• Internal pull-up on MCLR pin
CMOS Technology:
RAM
Pin Diagram
PDIP, SOIC
VDD
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP3/MCLR/VPP
Peripheral Features:
1
2
3
4
PIC12C671
PIC12C672
PIC12C671
1024 x 14
128 x 8
PIC12C672
2048 x 14
128 x 8
• 14-bit wide instructions
• 8-bit wide data path
• Interrupt capability
• Special function hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes for
data and instructions
• Internal 4 MHz oscillator with programmable
calibration
• Selectable clockout
• In-circuit serial programming
• 4-channel 8-bit analog-to-digital converter
• Low power, high speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.5V to 5.5V
- Industrial: 2.5V to 5.5V
- Extended: 4.5V to 5.5V
• Low power consumption
- < 2 mA @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 KHz
- < 1 µA typical standby current
8
7
6
5
VSS
GP0/AN0
GP1/AN1/VREF
GP2/T0CKI/
AN2/INT
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Power-On Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OSC)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Interrupt on pin change (GP0, GP1, GP3)
• Internal pull-ups on I/O pins (GP0, GP1, GP3)
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 1
PIC12C67X
Table of Contents
1.0
General Description............................................................................................................................................3
2.0
PIC12C67X Device Varieties .............................................................................................................................5
3.0
Architectural Overview .......................................................................................................................................7
4.0
Memory Organization .......................................................................................................................................11
5.0
I/O Ports ...........................................................................................................................................................23
6.0
Timer0 Module .................................................................................................................................................25
7.0
Analog-to-Digital Converter (A/D) Module........................................................................................................31
8.0
Special Features of the CPU............................................................................................................................39
9.0
Instruction Set Summary ..................................................................................................................................55
10.0
Development Support.......................................................................................................................................69
11.0
Electrical Characteristics for PIC12C67X ........................................................................................................73
12.0
DC and AC Characteristics - PIC12C67X ........................................................................................................89
13.0
Packaging Information......................................................................................................................................93
Appendix A: Compatibility .............................................................................................................................................97
Index............................................................................................................................................................................101
PIC12C67X Product Identification System..................................................................................................................109
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
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DS30561A-page 2
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
1.0
GENERAL DESCRIPTION
The PIC12C67X device is a low-cost, high-performance, CMOS, fully-static, 8-bit microcontroller with
integrated analog-to-digital (A/D) converter, in the
PIC12CXXX Microcontroller family.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC12C67X microcontrollers
have enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
PIC12C67X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC12C67X devices have 128 bytes of RAM and 6
I/O pins. In addition a timer/counter is available. Also a
4-channel high-speed 8-bit A/D is provided. The 8-bit
resolution is ideally suited for applications requiring
low-cost analog interface, e.g. thermostat control, pressure sensing, etc.
The PIC12C67X device has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
The PIC12C67X products are equipped with special
features that reduce system cost and power requirements. The Power-On Reset (POR), Power-up Timer
(PWRT), and Oscillator Start-up Timer (OST) eliminate
the need for external reset circuitry. There are five oscillator configurations to choose from, including INTRC
precision internal oscillator mode and the power-saving
LP (Low Power) oscillator. Power saving SLEEP mode,
Watchdog Timer and code protection features improve
system cost, power and reliability.The SLEEP (powerdown) feature provides a power saving mode. The user
can wake up the chip from SLEEP through several
external and internal interrupts and resets.
 1997 Microchip Technology Inc.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
A UV erasable windowed package version is ideal for
code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production
in any volume. The customer can take full advantage of
Microchip’s price leadership in OTP microcontrollers
while benefiting from the OTP’s flexibility.
The PIC12C67X device fits perfectly in applications
ranging from security and remote sensors to appliance
control and automotive. The EPROM technology
makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for
all applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC12C67X very versatile even in areas
where no microcontroller use has been considered
before (e.g. timer functions, communications and
coprocessor applications).
1.1
Family and Upward Compatibility
The PIC12C67X products are compatible with other
members of the PIC16CXXX family.
1.2
Development Support
The PIC12C67X device is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
Preliminary
DS30561A-page 3
PIC12C67X
TABLE 1-1:
PIC12CXXX FAMILY OF DEVICES
PIC12C509
PIC12C508
Clock
Memory
Peripherals
Features
PIC12C671
10
PIC12C672
Maximum Frequency
of Operation (MHz)
4
4
10
EPROM Program Memory
512 x 12
1024 x 12
1024 x 14
2048 x 14
Data Memory (bytes)
25
41
128
128
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
A/D Converter (8-bit) Channels
—
—
4
4
Wake-up from SLEEP on
pin change
Yes
Yes
Yes
Yes
Interrupt Sources
—
—
4
4
I/O Pins
5
5
5
5
Input Pins
1
1
1
1
Internal Pull-ups
Yes
Yes
Yes
Yes
Voltage Range (Volts)
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Number of Instructions
33
33
35
35
Packages
8-pin DIP, JW,
SOIC
8-pin DIP, JW,
SOIC
8-pin DIP, JW,
SOIC
8-pin DIP, JW,
SOIC
All PIC12CXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12CXXX devices use serial programming with data pin GP0 and clock pin GP1.
DS30561A-page 4
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
2.0
PIC12C67X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC12C67X Product Identification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For the PIC12C67X, there are two device “types” as
indicated in the device number:
1.
2.
2.1
C, as in PIC12C671. These devices have
EPROM type memory and operate over the
standard voltage range.
LC, as in PIC12LC671. These devices have
EPROM type memory and operate over an
extended voltage range.
UV Erasable Devices
The UV erasable version, offered in windowed package, is optimal for prototype development and pilot programs.
The UV erasable version can be erased and reprogrammed to any of the configuration modes.
Microchip's PICSTART Plus and PRO MATE programmers both support the PIC12C67X. Third party
programmers also are available; refer to the Microchip
Third Party Guide for a list of sources.
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
CAUTION: Calibration values must be read before
erasing.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 5
PIC12C67X
NOTES:
DS30561A-page 6
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12C67X family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC12C67X uses a Harvard architecture, in which
program and data are accessed from separate memories using separate buses. This improves bandwidth
over traditional von Neumann architecture in which program and data are fetched from the same memory
using the same bus. Separating program and data
buses also allow instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are 14bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35)
execute in a single cycle (1 µs @ 4 MHz) except for program branches.
The table below lists program memory (EPROM) and
data memory (RAM) for each PIC12C67X device.
Device
PIC12C671
PIC12C672
The PIC12C67X can directly or indirectly address its
register files or data memory. All special function registers, including the program counter, are mapped in the
data memory. The PIC12C67X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC12C67X simple yet efficient. In addition, the learning curve is reduced significantly.
PIC12C67X devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
Program
Memory
Data Memory
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
1K x 14
2K x 14
128 x 8
128 x 8
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 7
PIC12C67X
FIGURE 3-1:
PIC12C67X BLOCK DIAGRAM
Device
Program Memory
Data Memory (RAM)
PIC12C671
PIC12C672
1K x 14
2K x 14
128 x 8
128 x 8
13
EPROM
Program
Memory
Program
Bus
RAM Addr (1)
GPIO
GP0/AN0
GP1/AN1/VREF
GP2/T0CKI/AN2/INT
GP3/MCLR/Vpp
GP4/OSC2/AN3/CLKOUT
GP5/OSC1/CLKIN
RAM
128 bytes
File
Registers
8 Level Stack
(13 bit)
14
8
Data Bus
Program Counter
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
Internal
4 MHz Clock
Timing
Generation
Oscillator
Start-up Timer
Watchdog
Timer
Power-on
Reset
MUX
ALU
8
W reg
Timer0
MCLR
VDD, VSS
A/D
Note 1: Higher order bits are from the STATUS register.
DS30561A-page 8
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
TABLE 3-1:
PIC12C67X PINOUT DESCRIPTION
DIP
Pin #
SOIC
Pin #
I/O/P
Type
GP0/AN0
7
7
I/O
TTL/ST Bi-directional I/O port/serial programming data/analog
input 0. Can be software programmed for internal
weak pull-up and interrupt on pin change. This buffer is
a Schmitt Trigger input when used in serial programming mode.
GP1/AN1/VREF
6
6
I/O
TTL/ST Bi-directional I/O port/serial programming clock/analog
input 1/voltage reference. Can be software programmed for internal weak pull-up and interrupt on pin
change. This buffer is a Schmitt Trigger input when
used in serial programming mode.
GP2/T0CKI/AN2/INT
5
5
I/O
ST
Bi-directional I/O port/analog input 2. Can be configured as T0CKI or external interrupt.
GP3/MCLR/VPP
4
4
I
TTL
Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation.
Can be software programmed for internal weak pull-up
and interrupt on pin change. Weak pull-up always on if
configured as MCLR .
GP4/OSC2/AN3/
CLKOUT
3
3
I/O
TTL
Bi-directional I/O port/oscillator crystal output/analog
input 3. Connections to crystal or resonator in crystal
oscillator mode (XT and LP modes only, GPIO in other
modes). In EXTRC and INTRC modes, the pin output
can be configured to CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle
rate.
GP5/OSC1/CLKIN
2
2
I/O
VDD
1
1
P
—
Positive supply for logic and I/O pins
VSS
8
8
P
—
Ground reference for logic and I/O pins
Name
Buffer
Type
Description
TTL/ST Bidirectional IO port oscillator crystal input/external
clock source input (GPIO in INTRC mode only, OSC1
in all other oscillator modes). Schmitt trigger in EXTRC
mode only.
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 9
PIC12C67X
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute
are pipelined such that fetch takes one instruction
cycle while decode and execute takes another
instruction cycle. However, due to the pipelining,
each instruction effectively executes in one cycle. If
an instruction causes the program counter to change
(e.g. GOTO) then two cycles are required to complete
the instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the “Instruction Register" (IR) in cycle
Q1. This instruction is then decoded and executed
during the Q2, Q3, and Q4 cycles. Data memory is
read during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(EXTRC and
INTRC modes)
EXAMPLE 3-1:
1. MOVLW 55h
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
Tcy0
Tcy1
Fetch 1
Execute 1
2. MOVWF GPIO
3. CALL
SUB_1
4. BSF
GPIO, BIT3 (Forced NOP)
Fetch 2
Tcy2
Tcy3
Tcy4
Tcy5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1
5. Instruction @ address SUB_1
Execute SUB_1
l instructions are single cycle, except for any program branches. These take two cycles since the fetch
struction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30561A-page 10
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
4.2
The PIC12C67X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space.
For the PIC12C671 the first 1K x 14 (0000h-03FFh) is
implemented.
For the PIC12C672, the first 2K x 14 (0000h-07FFh) is
implemented. Accessing a location above the physically implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1:
PIC12C67X PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
The data memory is partitioned into two Banks which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers. Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
Also note that F0h through FFh on the PIC12C67X is
mapped into Bank 0 registers 70h-7Fh.
4.2.1
13
Data Memory Organization
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR
(Section 4.5).
Stack Level 1
Stack Level 8
Reset Vector
0000h
Peripheral Interrupt Vector
0004h
0005h
On-chip Program
Memory
(PIC12C672 only)
03FFh
0400h
07FFh
0800h
1FFFh
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 11
PIC12C67X
FIGURE 4-2:
PIC12C67X REGISTER FILE
MAP
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
STATUS
FSR
GPIO
INDF(1)
OPTION
PCL
STATUS
FSR
TRIS
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
OSCCAL
ADRES
ADCON0
ADCON1
General
Purpose
Register
General
Purpose
Register
70h
7Fh
Mapped
in Bank 0
Bank 0
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
A0h
BFh
C0h
EFh
F0h
FFh
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
DS30561A-page 12
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
TABLE 4-1:
Address Name
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets(3)
0000 0000
0000 0000
Bank 0
00h(1)
INDF
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
03h(1)
STATUS
04h(1)
FSR
Addressing this location uses contents of FSR to address data memory (not a physical register)
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
05h
GPIO
--xx xxxx
--uu uuuu
—
Unimplemented
—
—
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
—
Unimplemented
09h
PCLATH
—
0Bh(1)
INTCON
0Ch
PIR1
—
GP5
GP4
GP3
GP2
GP1
—
—
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
—
ADIF
—
—
—
—
—
GP0
000q quuu
uuuu uuuu
06h
0Ah(1,2)
—
0001 1xxx
xxxx xxxx
—
—
---0 0000
---0 0000
GPIF
0000 000x
0000 000u
—
-0-- ----
-0-- ----
Write Buffer for the upper 5 bits of the Program Counter
0Dh
—
Unimplemented
—
—
0Eh
—
Unimplemented
—
—
0Fh
—
Unimplemented
—
—
10h
—
Unimplemented
—
—
11h
—
Unimplemented
—
—
12h
—
Unimplemented
—
—
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
—
Unimplemented
—
—
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
1Eh
ADRES
1Fh
ADCON0
Unimplemented
A/D Result Register
ADCS1
ADCS0
r
CHS1
CHS0
GO/DONE
r
ADON
—
—
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X, always maintain these bits clear.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 13
PIC12C67X
TABLE 4-1:
Address Name
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets(3)
0000 0000
0000 0000
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
83h(1)
STATUS
84h(1)
FSR
85h
TRIS
Addressing this location uses contents of FSR to address data memory (not a physical register)
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
GPIO Data Direction Register
1111 1111
1111 1111
0000 0000
0000 0000
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
--11 1111
--11 1111
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
—
Unimplemented
89h
8Ah(1,2)
PCLATH
—
8Bh(1)
INTCON
8Ch
PIE1
8Dh
—
8Eh
PCON
—
—
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
—
ADIE
—
—
—
—
—
—
—
---0 0000
---0 0000
GPIF
0000 000x
0000 000x
—
-0-- ----
-0-- ----
Write Buffer for the upper 5 bits of the PC
Unimplemented
—
—
—
—
—
—
—
—
POR
—
---- --0-
---- --u-
CAL3
CAL2
CAL1
CAL0
CALFST
CALSLW
—
—
8Fh
OSCCAL
0111 00--
uuuu uu--
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
ADCON1
---- -000
---- -000
—
—
—
—
—
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X, always maintain these bits clear.
DS30561A-page 14
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
4.2.2.1
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
STATUS REGISTER
The STATUS register, shown in Figure 4-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12C67X and should be
maintained clear. Use of these bits as
general purpose R/W bits is NOT recommended, since this may affect upward
compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
FIGURE 4-3:
R/W-0
IRP
bit7
bit 7:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved, always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 15
PIC12C67X
4.2.2.2
OPTION REGISTER
Note:
The OPTION register is a readable and writable register which contains various control bits to configure the
TMR0/WDT prescaler, the External INT Interrupt,
TMR0, and the weak pull-ups on GPIO.
FIGURE 4-4:
R/W-1
GPPU
bit7
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer by setting bit PSA
(OPTION<3>).
OPTION REGISTER (ADDRESS 81h)
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
bit0
bit 7:
GPPU: Weak pullup enable
1 = Weak pullups disabled
0 = Weak pullups enabled (GP0, GP1, GP3)
bit 6:
INTEDG: Interrupt edge
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI/AN2 pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI/AN2 pin
0 = Increment on low-to-high transition on GP2/T0CKI/AN2 pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS30561A-page 16
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
4.2.2.3
INTCON REGISTER
Note:
The INTCON Register is a readable and writable register which contains various enable and flag bits for the
TMR0 register overflow, GPIO Port change and External GP2/INT Pin interrupts.
FIGURE 4-5:
R/W-0
GIE
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
GPIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
GPIF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: INT External Interrupt Enable bit
1 = Enables the external interrupt on GP2/INT pin
0 = Disables the external interrupt on GP2/INT pin
bit 3:
GPIE: GPIO Interrupt on Change Enable bit
1 = Enables the GPIO Interrupt on Change
0 = Disables the GPIO Interrupt on Change
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: INT External Interrupt Flag bit
1 = The external interrupt on GP2/INT pin occurred (must be cleared in software)
0 = The external interrupt on GP2/INT pin did not occur
bit 0:
GPIF: GPIO Interrupt on Change Flag bit
1 = GP0, GP1, or GP3 pins changed state (must be cleared in software)
0 = Neither GP0, GP1, nor GP3 pins have changed state
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 17
PIC12C67X
4.2.2.4
PIE1 REGISTER
Note:
This register contains the individual enable bits for the
Peripheral interrupts.
FIGURE 4-6:
U-0
—
bit7
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
ADIE
U-0
—
U-0
—
U-0
—
U-0
—
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
DS30561A-page 18
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
4.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 4-7:
U-0
—
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
ADIF
U-0
—
U-0
—
U-0
—
U-0
—
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 19
PIC12C67X
4.2.2.6
PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), an external MCLR Reset, and WDT Reset.
FIGURE 4-8:
U-0
—
bit7
PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
Unimplemented: Read as '0'
DS30561A-page 20
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
4.2.2.7
OSCCAL REGISTER
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains four
bits for fine calibration and two other bits to either
increase or decrease frequency.
FIGURE 4-9:
R/W-0
CAL3
bit7
OSCCAL REGISTER (ADDRESS 8Fh)
R/W-1
CAL2
R/W-1
CAL1
R/W-1
CAL0
R/W-0
CALFST
R/W-0
CALSLW
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-4: CAL<3:0>: Fine calibration
bit 3:
CALFST: Calibration Fast
1 = Increase frequency
0 = No change
bit 2:
CALSLW: Calibration Slow
1 = Decrease frequency
0 = No change
bit 1-0: Unimplemented: Read as '0'
Note:
If CALFST = 1 and CALSLW = 1, CALFST has precedence.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 21
PIC12C67X
4.3
PCL and PCLATH
4.3.2
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any reset, the PC is cleared. Figure 4-10 shows the
two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-10: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
5
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
4.3.1
The PIC12C67X family has an 8 level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event
of a RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
Note 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
4.4
GOTO, CALL
STACK
Program Memory Paging
The PIC12C67X ignores both paging bits
PCLATH<4:3>, which are used to access program
memory when more than one page is available. The
use of PCLATH<4:3> as general purpose read/write
bits for the PIC12C67X is not recommended since this
may affect upward compatibility with future products.
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
DS30561A-page 22
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
4.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-1:
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
movlw
movwf
clrf
incf
btfss
goto
NEXT
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-11. However, IRP
is not used in the PIC12C67X.
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
FIGURE 4-11: DIRECT/INDIRECT ADDRESSING
Direct Addressing
(1)RP1
RP0
bank select
6
from opcode
Indirect Addressing
(1)
0
IRP
7
bank select
location select
00
01
10
FSR register
0
location select
11
00h
00h
not used
Data
Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For register file map detail see Figure 4-2.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 23
PIC12C67X
NOTES:
DS30561A-page 24
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
5.0
I/O PORT
5.3
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF GPIO,W) always read the
I/O pins independent of the pin’s input/output modes.
On RESET, all I/O ports are defined as input (inputs
are at hi-impedance) since the I/O control registers are
all set.
5.1
The equivalent circuit for an I/O port pin is shown in
Figure 5-2. All port pins, except GP3 which is input
only, may be used for both input and output
operations. For input operations these ports are nonlatching. Any input must be present until read by an
input instruction (e.g., MOVF GPIO,W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O’s to
alternate functions. When acting as alternate functions
the pins will read as ‘0’ during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with interrupt on change. The interrupt on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, the weak
pull-up is always on. Interrupt on change for this pin is
not set and GP3 will read as '0'. Interrupt on change is
enabled by setting INTCON<3>. Note that external
oscillator use overrides the GPIO functions on GP4
and GP5.
5.2
I/O Interfacing
Note:
On a Power-on Reset, GP0, GP1, GP2,
GP4 are configured as analog inputs and
read as '0'.
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Data
Latch
WR
Port
CK
VDD
Q
P
TRIS Register
This register controls the data direction for GPIO. A '1'
from a TRIS register bit puts the corresponding output
driver in a hi-impedance mode. A '0' puts the contents
of the output data latch on the selected pins, enabling
the output buffer. The exceptions are GP3 which is
input only and its TRIS bit will always read as '1'.
Note:
D
TRIS ‘f’
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
TABLE 5-1:
I/O
pin(1)
Q
TRIS
Latch
CK
VSS
Q
Reset
RD Port
Upon reset, the TRIS register is all '1's, making all pins
inputs.
Address
N
W
Reg
Note 1: I/O pins have protection diodes to VDD and VSS.
GP3 is input only with no data latch and no
output drivers.
SUMMARY OF PORT REGISTERS
Name
Bit 7
Bit 6
—
—
INTEDG
85h
TRIS
81h
OPTION
GPPU
03h
STATUS
(1)
05h
GPIO
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
Power-on
Reset
Value on
all other
Resets
--11 1111
--11 1111
PS0
1111 1111
1111 1111
Bit 0
GPIO Data Direction Register
(1)
T0CS
T0SE
PSA
PS2
PS1
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,
q = see tables in Section 7.7 for possible values.
Note 1: The IRP and RP1 bits are reserved on the PIC12C67X, always maintain these bits clear.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 25
PIC12C67X
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
Example 5-1 shows the effect of two sequential readmodify-write instructions on an I/O port.
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of GPIO will cause all eight bits of GPIO to be read into
the CPU. Then the BSF operation takes place on bit5
and GPIO is written to the output latches. If another bit
of GPIO is used as a bi-directional I/O pin (e.g., bit0)
and it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU
and rewritten to the data latch of this particular pin,
overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched to an output, the content of the data
latch may now be unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
FIGURE 5-2:
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;
;
GPIO latch GPIO pins
;
---------- ---------BCF
GPIO, 5
;--01 -ppp
--11 pppp
BCF
GPIO, 4
;--10 -ppp
--11 pppp
MOVLW 007h
;
TRIS GPIO
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
MOVWF GPIO
PC + 1
MOVF GPIO,W
PC + 2
PC + 3
NOP
NOP
GP5:GP0
Port pin
written here
Instruction
executed
DS30561A-page 26
MOVWF GPIO
(Write to
GPIO)
Port pin
sampled here
MOVF GPIO,W
(Read
GPIO)
This example shows a write to GPIO followed
by a read from GPIO.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
NOP
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
6.0
TIMER0 MODULE
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 6.2.
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 6.3 details the operation
of the prescaler.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
6.1
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Source Edge Select bit T0SE (OPTION<4>). Clearing
FIGURE 6-1:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP. See Figure 64 for Timer0 interrupt timing.
TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
Sync with
Internal
clocks
1
Programmable
Prescaler
GP2/T0CKI/
AN2
8
PSout
1
0
TMR0
PSout
(2 cycle delay)
T0SE
3
Set interrupt
flag bit T0IF
on overflow
PSA
PS2, PS1, PS0
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).
FIGURE 6-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
T0
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0+1
Instruction
Executed
 1997 Microchip Technology Inc.
PC+2
MOVF TMR0,W
PC+3
MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Preliminary
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
Read TMR0
reads NT0 + 1
NT0+2
T0
Read TMR0
reads NT0 + 2
DS30561A-page 27
PIC12C67X
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
PC+3
Instruction
Execute
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Read TMR0
reads NT0
Write TMR0
executed
FIGURE 6-4:
PC+4
MOVF TMR0,W
T0+1
T0
TMR0
PC+2
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
T0IF bit
(INTCON<2>)
FFh
00h
01h
02h
1
1
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS30561A-page 28
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
6.2
Using Timer0 with an External Clock
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the
desired device.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
6.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay
from the external clock edge to the timer incrementing.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 29
PIC12C67X
6.3
Prescaler
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 6-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
FIGURE 6-6:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
GP2/T0CKI/
AN2
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS30561A-page 30
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
6.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.
The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program
execution.
Note:
To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 6-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
EXAMPLE 6-1:
BCF
CLRF
BSF
CLRWDT
MOVLW
MOVWF
BCF
EXAMPLE 6-2:
BSF
MOVLW
MOVWF
BCF
;Clear WDT and
;prescaler
STATUS, RP0 ;Bank 1
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
OPTION_REG ;clock source
STATUS, RP0 ;Bank 0
CHANGING PRESCALER
(TIMER0→WDT)
STATUS, RP0
TMR0
STATUS, RP0
b'xxxx1xxx'
OPTION_REG
STATUS, RP0
TABLE 6-1:
CLRWDT
CHANGING PRESCALER
(WDT→TIMER0)
;Bank 0
;Clear TMR0 & Prescaler
;Bank 1
;Clears WDT
;Select new prescale
;value & WDT
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Address Name
01h
TMR0
0Bh/8Bh
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
Value on
POR
Value on
all other
Resets
xxxx xxxx
uuuu uuuu
0000 000x
0000 000u
81h
OPTION GPPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
85h
TRIS
TRIS5
TRIS4
TRIS3
TRIS2
TRIS1
TRIS0
--11 1111
--11 1111
—
—
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 31
PIC12C67X
NOTES:
DS30561A-page 32
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The analog-to-digital (A/D) converter module has four
analog inputs.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s positive supply voltage (VDD)
or the voltage level on the GP1/AN1/VREF pin. The A/D
converter has a unique feature of being able to operate
while the device is in SLEEP mode.
FIGURE 7-1:
The ADCON0 register, shown in Figure 7-1, controls
the operation of the A/D module. The ADCON1 register, shown in Figure 7-2, configures the functions of the
port pins. The port pins can be configured as analog
inputs (GP1 can also be a voltage reference) or as digital I/O.
Note:
If the port pins are configured as analog
inputs (reset condition), reading the port
(MOVF GP,W) results in reading '0's.
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
r
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE
R/W-0
r
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an RC oscillation)
bit 5:
Reserved
bit 4-3: CHS1:CHS0: Analog Channel Select bits
00 = channel 0, (GP0/AN0)
01 = channel 1, (GP1/AN1)
10 = channel 2, (GP2/AN2)
11 = channel 3, (GP4/AN3)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1:
Reserved
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 33
PIC12C67X
FIGURE 7-2:
U-0
—
bit7
ADCON1 REGISTER (ADDRESS 9Fh)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n =Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1-0: PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
GP4
GP2
GP1
GP0
VREF
000(1)
A
A
A
A
VDD
001
010
011
100
101
110
111
A
D
D
D
D
D
D
A
A
A
D
D
D
D
VREF
A
VREF
A
VREF
D
D
A
A
A
A
A
A
D
GP1
VDD
GP1
VDD
GP1
VDD
—
A = Analog input
D = Digital I/O
Note 1: Value on reset.
Note:
Any instruction that reads a pin configured as an analog input will read a '0'.
DS30561A-page 34
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
2.
The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF (PIE1<6>) is set. The block diagrams of the A/D
module are shown in Figure 7-3.
3.
4.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine sample time, see Section 7.1. After
this acquisition time has elapsed the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
1.
5.
OR
6.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 7-3:
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
7.
• Waiting for the A/D interrupt
Read A/D Result register (ADRES), clear bit
ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
A/D BLOCK DIAGRAM
CHS1:CHS0
11
VIN
GP4/AN3
10
(Input voltage)
GP2/AN2
01
A/D
Converter
GP1/AN1/VREF
00
GP0/AN0
VDD
000
010
100
110
001
011
101
VREF
(Reference
voltage)
or
or
or
or
or
or
PCFG2:PCFG0
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 35
PIC12C67X
7.1
A/D Sampling Requirements
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 7-4. The maximum recommended impedance for analog sources is 10 kΩ. After the analog
input channel is selected (changed) this acquisition
must be done before the conversion can be started.
To calculate the minimum acquisition time, Equation 71 may be used. This equation assumes that 1/2 LSb
error is used (512 steps for the A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
EQUATION 7-1:
A/D MINIMUM CHARGING
TIME
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specification.
Note 4: After a conversion has completed, a
2.0 TAD delay must complete before
acquisition can begin again. During this
time the holding capacitor is not connected to the selected A/D input channel.
EXAMPLE 7-1:
CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
VHOLD = (VREF - (VREF/512)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
Temperature Coefficient
or
TACQ = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
Tc = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
Example 7-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
TC =
-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
Rs = 10 kΩ
-0.921 µs (-6.2146)
1/2 LSb error
5.724 µs
VDD = 5V → Rss = 7 kΩ
TACQ = 5 µs + 5.724 µs + [(50°C - 25°C)(0.05 µs/°C)]
Temp (system max.) = 50°C
10.724 µs + 1.25 µs
VHOLD = 0 @ t = 0
11.974 µs
FIGURE 7-4:
ANALOG INPUT MODEL
VDD
Rs
RAx
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS RSS
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
DS30561A-page 36
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
Preliminary
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
 1997 Microchip Technology Inc.
PIC12C67X
7.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selected. The four possible options for TAD are:
•
•
•
•
2TOSC
8TOSC
32TOSC
Precision internal 4 MHz oscillator
Configuring Analog Port Pins
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 7-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 7-1:
7.3
Note 1: When reading the port register, all pins
configured as analog input channel will
read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN3:AN0
pins), may cause the input buffer to consume current that is out of the devices
specification.
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency
AD Clock Source (TAD)
Operation
ADCS1:ADCS0
4 MHz
2TOSC
00
8TOSC
01
500
2.0 µs
32TOSC
10
8.0 µs
ns(2)
1.25 MHz
333.33 kHz
1.6 µs
6 µs
6.4 µs
24 µs(3)
25.6 µs(3)
96 µs(3)
11
Internal ADC RC Oscillator(5)
2 - 6 µs(1,4)
2 - 6 µs(1,4)
2 - 6 µs(1)
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 37
PIC12C67X
7.4
A/D Conversions
Example 7-2 show how to perform an A/D conversion.
The GP pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC.
The conversion is performed on the GP0 channel.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
EXAMPLE 7-2:
BSF
CLRF
BSF
BCF
MOVLW
MOVWF
BCF
BSF
BSF
;
;
;
;
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed
conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started
on the selected channel.
DOING AN A/D CONVERSION
STATUS,
ADCON1
PIE1,
STATUS,
0xC1
ADCON0
PIR1,
INTCON,
INTCON,
RP0
ADIE
RP0
ADIF
PEIE
GIE
;
;
;
;
;
;
;
;
;
Select Page 1
Configure A/D inputs
Enable A/D interrupts
Select Page 0
RC Clock, A/D is on, Channel 0 is selected
Clear A/D interrupt flag bit
Enable peripheral interrupts
Enable all interrupts
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
:
ADCON0, GO
DS30561A-page 38
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
; is cleared upon completion of the A/D Conversion.
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
7.7
A/D Accuracy/Error
The overall accuracy of the A/D is less than ± 1 LSb for
VDD = 5V ± 10% and the analog VREF = VDD. This overall accuracy includes offset error, full scale error, and
integral error. The A/D converter is guaranteed to be
monotonic. The resolution and accuracy may be less
when either the analog reference (VDD) is less than
5.0V or when the analog reference (VREF) is less than
VDD.
Note:
An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
7.9
Transfer Function
The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input
voltage (VAIN) is 1 LSb (or Analog VREF / 256)
(Figure 7-5).
FIGURE 7-5:
The maximum pin leakage current is ± 5 µA.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be
≤ 8 µs for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock transitions. This reduces, to a large extent,
the effects of digital switching noise. This is not possible
with the RC derived clock. The loss of accuracy due to
digital switching noise can be significant if many I/O
pins are active.
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
 1997 Microchip Technology Inc.
For the PIC12C67X, care must be taken
when using the GP4 pin in A/D conversions due to its proximity to the OSC1 pin.
Preliminary
A/D TRANSFER FUNCTION
FFh
FEh
04h
03h
02h
01h
00h
256 LSb
(full scale)
7.6
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, the GO/DONE bit
must be set, followed by the SLEEP instruction.
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conversion is out of specification.
255 LSb
Note:
Connection Considerations
4 LSb
Turning off the A/D places the A/D module in its lowest
current consumption state.
7.8
3 LSb
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the ADRES
register is not modified for a Power-on Reset. The
ADRES register will contain unknown data after a
Power-on Reset.
2 LSb
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
Effects of a RESET
0.5 LSb
1 LSb
A/D Operation During Sleep
Digital code output
7.5
Analog input voltage
DS30561A-page 39
PIC12C67X
FIGURE 7-6:
FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
A/D Clock
= RC?
Yes
SLEEP Yes
Instruction?
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
GO = 0
ADIF = 1
No
No
Yes
Device in
SLEEP?
Abort Conversion
GO = 0
ADIF = 0
Finish Conversion
GO = 0
ADIF = 1
Wake-up Yes
From Sleep?
Wait 2 TAD
No
No
SLEEP
Power-down A/D
Finish Conversion
GO = 0
ADIF = 1
Stay in Sleep
Power-down A/D
Wait 2 TAD
Wait 2 TAD
TABLE 7-2:
SUMMARY OF A/D REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets(1)
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
—
—
—
—
—
-0-- ----
-0-- ----
8Ch
PIE1
—
ADIE
—
—
—
—
—
—
-0-- ----
-0-- ----
1Eh
ADRES
A/D Result Register
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
ADCS0
r
CHS1
CHS0
GO/DONE
r
ADON
0000 0000
0000 0000
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
---- -000
--xx xxxx
--uu uuuu
05h
GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
85h
TRIS
—
—
TRIS5 TRIS4 TRIS3
TRIS2
TRIS1
TRIS0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', r = reserved. Shaded cells are not used for A/D conversion.
Note 1: These registers can be addressed from either bank.
DS30561A-page 40
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
8.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC12C67X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection. These are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
CP1
CP0
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The EXTRC oscillator option saves system cost while
the LP crystal option saves power. A set of configuration bits are used to select various options.
8.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The PIC12C67X has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
FIGURE 8-1:
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h3FFFh), which can be accessed only during
programming.
CONFIGURATION WORD
CP1
CP0
CP1
CP0 MCLRE
CP1
CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0
bit13
bit0
bit 13-8
6-5:
CP1:CP0: Code Protection bits (1)
11 = Code protection off
10 = Locations 400h through 7FFh code protected (do not use for PIC12C671)
01 = Locations 200h through 7FFh code protected
00 = All memory is code protected
bit 7:
MCLRE: Master Clear Reset Enable bit
1 = Master Clear Enabled
0 = Master Clear Disabled
bit 4:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0:
FOSC2:FOSC0: Oscillator Selection bits
111 = EXTRC, Clockout on OSC2
110 = EXTRC, OSC2 is I/O
101 = INTRC, Clockout on OSC2
100 = INTRC, OSC2 is I/O
011 = Invalid Selection
010 = HS Oscillator
001 = XT Oscillator
000 = LP Oscillator
Register:
Address
CONFIG
2007h
Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 41
PIC12C67X
8.2
Oscillator Configurations
8.2.1
OSCILLATOR TYPES
TABLE 8-1:
The PIC12C67X can be operated in seven different
oscillator modes. The user can program three
configuration bits (FOSC2:FOSC0) to select one of
these seven modes:
•
•
•
•
•
LP:
HS:
XT:
INTRC*:
EXTRC*:
Low Power Crystal
High Speed Crystal Resonator
Crystal/Resonator
Internal 4 MHz Oscillator
External Resistor/Capacitor
*Can be configured to support CLKOUT
8.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(XT, HS OR LP OSC
CONFIGURATION)
C1(1)
OSC1
PIC12C67X
SLEEP
XTAL
RS(2)
RF(3)
OSC2
To internal
logic
C2(1)
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen
(approx. value = 10 MΩ).
FIGURE 8-3:
Resonator
Freq
Cap. Range
C1
Cap. Range
C2
XT
455 kHz
22-100 pF
22-100 pF
2.0 MHz
15-68 pF
15-68 pF
4.0 MHz
15-68 pF
15-68 pF
HS
4.0 MHz
15-68 pF
15-68 pF
8.0 MHz
10-68 pF
10-68 pF
10.0 MHz
10-22 pF
10-22 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
TABLE 8-2:
In XT, HS or LP modes, a crystal or ceramic resonator
is connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 8-2). The
PIC12C67X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications. When in XT, HS or LP modes, the
device can have an external clock source drive the
GP5/OSC1/CLKIN pin (Figure 8-3).
FIGURE 8-2:
Osc
Type
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12C67X
Osc
Type
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC12C67X
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
32 kHz(1)
15 pF
15 pF
100 kHz
15-30 pF
30-47 pF
200 kHz
15-30 pF
15-82 pF
200-300 pF
15-30 pF
XT
100 kHz
100-200 pF
15-30 pF
200 kHz
15-100 pF
15-30 pF
455 kHz
15-30 pF
15-30 pF
1 MHz
15-30 pF
15-30 pF
2 MHz
15-47 pF
15-47 pF
4 MHz
HS
4 MHz
15-30 pF
15-30 pF
8 MHz
15-30 pF
15-30 pF
10 MHz
15-30 pF
15-30 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.
LP
EXTERNAL CLOCK INPUT
OPERATION (XT, HS OR LP
OSC CONFIGURATION)
OSC1
PIC12C67X
Clock from
ext. system
Open
DS30561A-page 42
OSC2
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
8.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
8.2.4
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 8-4 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 8-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
74AS04
PIC12C67X
10k
10k
20 pF
Figure 8-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 8-5:
74AS04
74AS04
74AS04
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
FIGURE 8-6:
EXTERNAL RC OSCILLATOR
MODE
VDD
Internal
clock
OSC1
To Other
Devices
330
Figure 8-6 shows how the R/C combination is
connected to the PIC12C67X. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
Rext
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).
CLKIN
XTAL
20 pF
EXTERNAL RC OSCILLATOR
N
Cext
PIC12C67X
PIC12C67X
VSS
FOSC/4
CLKIN
OSC2/CLKOUT
0.1 µF
XTAL
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 43
PIC12C67X
8.2.5
8.3
INTERNAL 4 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C, see "Electrical
Specifications" section for information on variation over
voltage and temperature.
In addition, a calibration instruction is programmed into
the last address of the program memory which contains the calibration value for the internal RC oscillator.
This value is programmed as a RETLW XX instruction
where XX is the calibration value. In order to retrieve
the calibration value, issue a CALL YY instruction where
YY is the last location in program memory (03FFh for
the PIC12C671, 07FFh for the PIC12C672). Control
will be returned to the user’s program with the calibration value loaded into the W register. The program
should then perform a MOVWF OSCCAL instruction to
load the value into the internal RC oscillator trim
register.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. Bits <7:4>, CAL3-CAL0
are used for fine calibration while bit 3, CALFST, and bit
2, CALSLW are used for more coarse adjustment.
Adjusting CAL3-0 from 0000 to 1111 yields a higher
clock speed. Set CALFST = 1 for greater increase in
frequency or set CALSLW = 1 for greater decrease in
frequency. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying
OSCCAL for compatibility with future devices.
Note:
8.2.6
Reset
The PIC12C67X differentiates between various kinds
of reset:
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (normal operation)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP. They are
not affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different reset situations
as indicated in Table 8-4. These bits are used in software to determine the nature of the reset. See Table 85 for a full description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 8-7.
The PIC12C67X has a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
CLKOUT
The PIC12C67X can be configured to provide a clock
out signal CLKOUT on pin 3 when the configuration
word address (2007h) is programmed with FOSC2,
FOSC1, FOSC0 equal to 101 for INTRC or 111 for
EXTRC. The oscillator frequency, divided by 4 can be
used for test purposes or to synchronize other logic.
DS30561A-page 44
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 8-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Weak
Pull-up
GP3/MCLR/VPP Pin
MCLRE
INTERNAL MCLR
WDT SLEEP
Module
WDT Time-out
VDD rise
detect
Power-on Reset
VDD
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 8-3 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 45
PIC12C67X
8.4
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
8.4.1
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
8.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
TABLE 8-3:
8.4.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
8.4.4
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 8-8,
Figure 8-9, and Figure 8-10 depict time-out sequences
on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 8-9). This is useful for testing purposes or to
synchronize more than one PIC12C67X device operating in parallel.
Table 8-5 shows the reset conditions for all the registers.
8.4.5
POWER CONTROL/STATUS REGISTER
(PCON)
The power control/status register, PCON (address
8Eh) has one bit. See Figure 4-8 for register.
Bit1 is POR (Power-on Reset). It is cleared on a Poweron Reset and is unaffected otherwise. The user set this
bit following a Power-on Reset. On subsequent resets
if POR is ‘0’, it will indicate that a Power-on Reset must
have occurred.
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
XT, HS, LP
INTRC, EXTRC
TABLE 8-4:
Power-up
PWRTE = 0
PWRTE = 1
72 ms + 1024TOSC
1024TOSC
72 ms
—
Wake-up from SLEEP
1024TOSC
—
STATUS BITS AND THEIR SIGNIFICANCE
POR
TO
PD
0
0
0
1
1
1
1
1
0
x
0
0
u
1
1
x
0
1
0
u
0
DS30561A-page 46
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
TABLE 8-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0-
MCLR Reset during normal operation
000h
0001 1uuu
---- --u-
MCLR Reset during SLEEP
000h
0001 0uuu
---- --u-
WDT Reset during normal operation
000h
0000 1uuu
---- --u-
PC + 1
uuu0 0uuu
---- --u-
uuu1 0uuu
---- --u-
Condition
WDT Wake-up from SLEEP
Interrupt wake-up from SLEEP
(1)
PC + 1
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 8-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or Interrupt
W
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
0000 0000
0000 0000
0000 0000
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
PC + 1(2)
STATUS
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
xxxx xxxx
uuuu uuuu
uuuu uuuu
GPIO
--xx xxxx
--uu uuuu
--uu uuuu
PCLATH
---0 0000
---0 0000
---u uuuu
INTCON
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
-0-- ----
-0-- ----
-u-- ----(1)
ADCON0
0000 0000
0000 0000
uuuu uuuu
OPTION
1111 1111
1111 1111
uuuu uuuu
TRIS
--11 1111
--11 1111
--uu uuuu
PIE1
-0-- 0000
-0-- 0000
-u-- uuuu
PCON
---- --0-
---- --u-
---- --u-
OSCCAL
0111 00--
uuuu uu--
uuuu uu--
ADCON1
---- -000
---- -000
---- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 8-5 for reset value for specific condition.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 47
PIC12C67X
FIGURE 8-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 8-9:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30561A-page 48
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 8-11: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 8-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
D
VDD
33k
VDD
10k
R
R1
4.3k
MCLR
C
MCLR
PIC12C67X
PIC12C67X
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal brown-out detection should be
disabled when using this circuit.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
3: Resistors should be adjusted for the characteristics of the transistor.
FIGURE 8-13: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
4.3k
PIC12C67X
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
R1
= 0.7V
VDD •
R1 + R2
2: Internal brown-out detection should be
disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 49
PIC12C67X
8.5
Interrupts
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
There are four sources of interrupt:
Interrupt Sources
TMR0 overflow interrupt
External interrupt GP2/INT pin
GPIO Port change interrupts (pins GP0, GP1, GP3)
A/D Interrupt
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The GP2/INT, GPIO port change interrupt and the
TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag ADIF, is contained in the
special function register PIR1. The corresponding interrupt enable bit is contained in special function register
PIE1, and the peripheral interrupt enable bit is contained in special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles. The exact latency depends when the
interrupt event occurs (Figure 8-15). The latency is the
same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
FIGURE 8-14: INTERRUPT LOGIC
Wakeup
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
GPIF
GPIE
ADIF
ADIE
PEIE
GIE
DS30561A-page 50
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 8-15: INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF flag
(INTCON<1>)
Interrupt Latency 2
5
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
Inst (PC+1)
Inst (PC)
0004h
PC+1
PC+1
—
Dummy Cycle
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTRC and EXTRC oscillator modes.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 51
PIC12C67X
8.5.1
8.6
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 6.0)
8.5.2
INT INTERRUPT
External interrupt on GP2/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up.
See Section 8.8 for details on SLEEP mode.
8.5.3
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
Example 8-1 store and restore the STATUS and W registers. The register, W_TEMP, must be defined in both
banks and must be defined at the same offset from the
bank base address (i.e., if W_TEMP is defined at 0x20
in bank 0, it must also be defined at 0xA0 in bank 1).
The example:
a)
b)
c)
d)
e)
Stores the W register.
Stores the STATUS register in bank 0.
Executes the ISR code.
Restores the STATUS register (and bank select
bit).
Restores the W register.
GPIO INTCON CHANGE
An input change on GP3, GP1 or GP0 sets flag bit
GPIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit GPIE
(INTCON<3>). (Section 5.2)
EXAMPLE 8-1:
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
BCF
MOVWF
:
:(ISR)
:
SWAPF
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
;Copy W to TEMP
;Swap status to
;Change to bank
;Save status to
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
DS30561A-page 52
register, could be bank one or zero
be saved into W
zero, regardless of current bank
bank zero STATUS_TEMP register
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
8.7
Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 8.1).
8.7.1
The CLRWDT and SLEEP instructions clear the WDT and
the postscaler, if assigned to the WDT, and prevent it
from timing out early and generating a premature
device RESET condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
8.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note:
WDT PERIOD
When the prescaler is assigned to the
WDT, always execute a CLRWDT instruction
before changing the prescale value, otherwise a WDT reset may occur.
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
FIGURE 8-16: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
1
WDT Timer
Postscaler
M
U
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 6-6)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
FIGURE 8-17: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits(1)
81h
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLRE
CP1
CP0
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 8-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 53
PIC12C67X
8.8
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input if enabled should also be at VDD or VSS for
lowest current consumption. The contribution from onchip pull-ups on GPIO should be considered.
The MCLR pin if enabled must be at a logic high level
(VIHMC).
8.8.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
GP2/INT interrupt, interrupt GPIO port change,
or some Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupt can wake the device
from SLEEP:
1.
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
8.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the the execution of
a SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep . The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction was
executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
A/D conversion (when A/D clock source is RC).
DS30561A-page 54
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 8-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
GPIO pin
GPIF flag
(INTCON<0>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst(PC) = SLEEP
Instruction
executed
Inst(PC - 1)
Note 1:
2:
3:
4:
8.9
PC+1
PC+2
Inst(PC + 2)
SLEEP
Inst(PC + 1)
8.10
Program Verification/Code Protection
Microchip does not recommend code protecting windowed devices.
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID
location are used.
8.11
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
PC+2
Inst(PC + 1)
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A 6bit command is then supplied to the device. Depending
on the command, 14-bits of program data are then supplied to or from the device, depending if the command
was a load or a read. For complete details of serial programming, please refer to the PIC12C67X Programming Specifications.
FIGURE 8-19: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
In-Circuit Serial Programming
PIC12C67X microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 (clock) becomes the programming
clock and GP0 (data) becomes the programming data.
Both GP0 and GP1 are Schmitt Trigger inputs in this
mode.
 1997 Microchip Technology Inc.
Preliminary
External
Connector
Signals
To Normal
Connections
PIC12C67X
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1
Data I/O
GP0
VDD
To Normal
Connections
DS30561A-page 55
PIC12C67X
NOTES:
DS30561A-page 56
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
9.0
INSTRUCTION SET SUMMARY
Each PIC12C67X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC12C67X instruction set summary in Table 9-2 lists byte-oriented, bitoriented, and literal and control operations. Table 91 shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
Table 9-2 lists the instructions recognized by the
MPASM assembler.
Figure 9-1 shows the three general formats that the
instructions can have.
Note:
To maintain upward compatibility with
future PIC12C67X products, do not use
the OPTION and TRIS instructions.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 9-1:
All examples use the following format to represent a
hexadecimal number:
OPCODE FIELD
DESCRIPTIONS
0xhh
Field
Description
where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label Label name
TOS Top of Stack
PC Program Counter
f
W
b
k
x
FIGURE 9-1:
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
[ ]
( )
→
<>
∈
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8 7
OPCODE
Global Interrupt Enable bit
Watchdog Timer/Counter
Time-out bit
Power-down bit
Destination either the W register or the specified
register file location
Options
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
PCLATH Program Counter High Latch
GIE
WDT
TO
PD
dest
GENERAL FORMAT FOR
INSTRUCTIONS
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
Contents
11
OPCODE
Assigned to
10
0
k (literal)
k = 11-bit immediate value
Register bit field
In the set of
italics User defined term (font is courier)
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 57
PIC12C67X
9.1
Special Function Registers as
Source/Destination
9.1.3
The PIC12C67X’s orthogonal instruction set allows
read and write of all file registers, including special
function registers. There are some special situations
the user should be aware of:
9.1.1
STATUS AS DESTINATION
PCL AS SOURCE OR DESTINATION
Read, write or read-modify-write on PCL may have the
following results:
Read PC:
PCL → dest
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
Read-Modify-Write:
PCL→ ALU operand
PCLATH → PCH;
8-bit result → PCL
If an instruction writes to STATUS, the Z, C and DC bits
may be set or cleared as a result of the instruction and
overwrite the original data bits written. For example,
executing CLRF STATUS will clear register STATUS, and
then set the Z bit leaving 0000 0100b in the register.
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
9.1.2
9.1.4
TRIS AS DESTINATION
Bit 3 of the TRIS register always reads as a '1' since
GP3 is an input only pin. This fact can affect some readmodify-write operations on the TRIS register.
DS30561A-page 58
BIT MANIPULATION
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
TABLE 9-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 59
PIC12C67X
9.2
Instruction Descriptions
ANDLW
And Literal with W
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
(W) + k → (W)
Operation:
(W) .AND. (k) → (W)
C, DC, Z
Status Affected:
Z
ADDLW
Add Literal and W
Syntax:
[ label ] ADDLW
Operands:
Operation:
Status Affected:
Encoding:
11
k
111x
kkkk
kkkk
Encoding:
11
k
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Words:
1
1
Cycles:
1
Cycles:
Example
ADDLW
Example
0x15
=
W
0x10
=
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
=
0xA3
After Instruction
After Instruction
W
0x5F
Before Instruction
Before Instruction
W
ANDLW
W
0x25
=
0x03
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
00
f,d
0111
dfff
ffff
Encoding:
00
f,d
0101
dfff
ffff
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ADDWF
FSR, 0
Example
Before Instruction
W =
FSR =
DS30561A-page 60
FSR, 1
Before Instruction
0x17
0xC2
W =
FSR =
After Instruction
W =
FSR =
ANDWF
0x17
0xC2
After Instruction
0xD9
0xC2
W =
FSR =
Preliminary
0x17
0x02
 1997 Microchip Technology Inc.
PIC12C67X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] BCF
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example
BCF
Encoding:
FLAG_REG = 0x47
bfff
ffff
Words:
1
Cycles:
1(2)
Before Instruction
FLAG_REG = 0xC7
10bb
Description:
FLAG_REG, 7
After Instruction
01
If bit 'b' in register 'f' is '0' then the next
instruction is skipped.
If bit 'b' is '0' then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a 2 cycle
instruction.
Example
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC =
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
1 → (f<b>)
Status Affected:
None
Encoding:
01
f,b
01bb
bfff
Description:
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Example
BSF
FLAG_REG,
ffff
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 61
PIC12C67X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 127
Operation:
00h → (f)
1→Z
Status Affected:
Z
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
Description:
01
11bb
bfff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a 2 cycle
instruction.
Words:
1
Cycles:
1(2)
Example
HERE
FALSE
TRUE
Encoding:
00
f
0001
1fff
ffff
Description:
The contents of register 'f' are cleared
and the Z bit is set.
Words:
1
Cycles:
1
Example
CLRF
FLAG_REG
Before Instruction
FLAG_REG
BTFSC
GOTO
•
•
•
=
0x5A
=
=
0x00
1
After Instruction
FLAG,1
PROCESS_CODE
FLAG_REG
Z
Before Instruction
PC =
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CALL
Call Subroutine
CLRW
Clear W
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRW
Operands:
0 ≤ k ≤ 2047
Operands:
None
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
00h → (W)
1→Z
Status Affected:
Z
Status Affected:
None
Encoding:
Encoding:
Description:
10
kkkk
kkkk
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two cycle instruction.
Words:
1
Cycles:
2
Example
0kkk
00
0001
0xxx
xxxx
Description:
W register is cleared. Zero bit (Z) is
set.
Words:
1
Cycles:
1
Example
CLRW
Before Instruction
W
HERE
CALL
=
0x5A
After Instruction
THERE
W
Z
Before Instruction
=
=
0x00
1
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
DS30561A-page 62
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
CLRWDT
Clear Watchdog Timer
DECF
Decrement f
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] DECF f,d
Operands:
None
Operands:
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (dest)
Status Affected:
Z
Status Affected:
Encoding:
Description:
Encoding:
TO, PD
00
0000
0110
0100
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
Words:
1
Cycles:
1
Example
00
0011
dfff
Description:
Words:
1
Cycles:
1
Example
DECF
CNT, 1
Before Instruction
CLRWDT
CNT
Z
Before Instruction
WDT counter =
WDT counter =
WDT prescaler=
TO
=
PD
=
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
=
=
0x01
0
=
=
0x00
1
After Instruction
?
CNT
Z
After Instruction
0x00
0
1
1
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest);
Status Affected:
Z
Status Affected:
None
Encoding:
00
1001
f,d
dfff
ffff
Description:
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Words:
1
Cycles:
1
Example
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
COMF
REG1,0
Before Instruction
REG1
=
0x13
=
=
0x13
0xEC
After Instruction
REG1
W
Encoding:
00
skip if result = 0
1011
dfff
ffff
Description:
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
Words:
1
Cycles:
1(2)
Example
HERE
DECFSZ
GOTO
CONTINUE •
•
•
CNT, 1
LOOP
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT
PC
if CNT
PC
 1997 Microchip Technology Inc.
Preliminary
=
=
=
≠
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
DS30561A-page 63
PIC12C67X
GOTO
Unconditional Branch
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 2047
Operands:
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (dest), skip if result = 0
None
Status Affected:
None
Status Affected:
Encoding:
GOTO k
10
1kkk
kkkk
kkkk
Description:
GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruction.
Words:
1
Cycles:
2
Example
GOTO THERE
After Instruction
PC =
Address THERE
Encoding:
00
INCFSZ f,d
1111
dfff
ffff
Description:
The contents of register 'f' are incremented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOP is executed instead making it a
two cycle instruction.
Words:
1
Cycles:
1(2)
Example
HERE
INCFSZ
GOTO
CONTINUE •
•
•
CNT,
LOOP
1
Before Instruction
PC
=
address HERE
After Instruction
CNT =
if CNT=
PC
=
if CNT≠
PC
=
CNT + 1
0,
address CONTINUE
0,
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
(f) + 1 → (dest)
Operation:
(W) .OR. k → (W)
Operation:
Status Affected:
Z
Status Affected:
Z
Encoding:
Description:
INCF f,d
Encoding:
00
1010
dfff
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
kkkk
Words:
1
1
Cycles:
Cycles:
1
Example
IORLW
0x35
Before Instruction
CNT, 1
W
Before Instruction
CNT
Z
kkkk
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
1
INCF
1000
Description:
Words:
Example
11
IORLW k
=
0x9A
After Instruction
=
=
0xFF
0
=
=
0x00
1
W
Z
=
=
0xBF
1
After Instruction
CNT
Z
DS30561A-page 64
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Z
Status Affected:
Z
Encoding:
00
IORWF
f,d
0100
dfff
ffff
Description:
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words:
1
Cycles:
1
Example
IORWF
RESULT, 0
Before Instruction
RESULT =
W
=
0x13
0x91
Encoding:
MOVF f,d
00
1000
Words:
1
Cycles:
1
Example
MOVF
FSR, 0
After Instruction
RESULT =
W
=
Z
=
0x13
0x93
1
W = value in FSR register
Z =1
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operation:
k → (W)
Operation:
(W) → (f)
Status Affected:
None
Status Affected:
None
Encoding:
MOVLW k
00xx
kkkk
kkkk
Description:
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Words:
1
Cycles:
1
Example
Encoding:
1fff
ffff
Words:
1
Cycles:
1
MOVWF
OPTION
Before Instruction
After Instruction
=
0000
f
Description:
0x5A
W
00
MOVWF
Move data from W register to register
'f'.
Example
MOVLW
ffff
Description:
After Instruction
11
dfff
The contents of register f is moved to
a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
OPTION =
W
=
0x5A
0xFF
0x4F
After Instruction
OPTION =
W
=
 1997 Microchip Technology Inc.
Preliminary
0x4F
0x4F
DS30561A-page 65
PIC12C67X
NOP
No Operation
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS → PC,
1 → GIE
Status Affected:
None
Encoding:
00
NOP
0000
0xx0
0000
RETFIE
No operation.
Encoding:
Words:
1
Description:
Cycles:
1
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Words:
1
Cycles:
2
Description:
Example
00
NOP
Example
0000
0000
1001
RETFIE
After Interrupt
PC =
GIE =
OPTION
Load Option Register
RETLW
Return with Literal in W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
(W) → OPTION
Operation:
k → (W);
TOS → PC
Status Affected:
None
OPTION
Status Affected: None
Encoding:
Description:
Words:
Cycles:
00
0000
0110
0010
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
TOS
1
Encoding:
RETLW k
11
01xx
kkkk
kkkk
Description:
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
1
Words:
1
1
Cycles:
2
Example
Example
To maintain upward compatibility
with future PIC12C67X products,
do not use this instruction.
CALL TABLE
•
•
•
TABLE ADDWF
RETLW
RETLW
•
•
•
RETLW
;W contains table
;offset value
;W now has table value
PC
k1
k2
;W = offset
;Begin table
;
kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
DS30561A-page 66
Preliminary
=
value of k8
 1997 Microchip Technology Inc.
PIC12C67X
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
Operation:
TOS → PC
0 ≤ f ≤ 127
d ∈ [0,1]
Status Affected:
None
Operation:
See description below
Status Affected:
C
Encoding:
Description:
00
0000
0000
1000
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
Words:
1
Cycles:
2
Example
RETURN
Encoding:
Description:
RRF f,d
00
1100
dfff
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
C
Register f
RETURN
After Interrupt
PC =
TOS
Words:
1
Cycles:
1
Example
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
0111 0011
0
After Instruction
REG1
W
C
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
None
Operation:
See description below
Operation:
Status Affected:
C
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Encoding:
Description:
RLF
00
1101
dfff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
C
Words:
1
Cycles:
1
Example
f,d
Encoding:
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0000
0110
0011
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
1
Cycles:
1
Example:
SLEEP
Register f
RLF
00
SLEEP
After Instruction
REG1
W
C
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 67
PIC12C67X
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k - (W) → (W)
0 ≤ f ≤ 127
d ∈ [0,1]
Status
Affected:
C, DC, Z
Operation:
(f) - (W) → (dest)
C, DC, Z
Encoding:
11
Status
Affected:
Description:
SUBLW k
110x
kkkk
kkkk
The W register is subtracted (2’s complement method) from the eight bit literal
'k'. The result is placed in the W register.
Words:
1
Cycles:
1
Example 1:
SUBLW
0x02
Before Instruction
W
C
=
=
Encoding:
Description:
1
Cycles:
1
Example 1:
SUBWF
1
?
Example 2:
=
=
=
=
Example 3:
=
=
=
=
REG1
W
C
2
?
Example 2:
0
1; result is zero
3
2
?
=
=
=
1
2
1; result is positive
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
3
?
REG1
W
C
After Instruction
W =
C
=
tive
=
=
=
After Instruction
Before Instruction
W
C
ffff
REG1,1
REG1
W
C
1
1; result is positive
After Instruction
W
C
dfff
Before Instruction
Before Instruction
W
C
0010
Subtract (2’s complement method) W register from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Words:
After Instruction
W
C
00
SUBWF f,d
0xFF
0; result is nega-
Example 3:
=
=
=
0
2
1; result is zero
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
DS30561A-page 68
Preliminary
=
=
=
0xFF
2
0; result is negative
 1997 Microchip Technology Inc.
PIC12C67X
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Operation:
(W) .XOR. k → (W)
Status Affected:
Z
Status Affected:
None
Encoding:
Description:
00
Encoding:
1110
dfff
ffff
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the
result is placed in W register. If 'd' is 1
the result is placed in register 'f'.
Description:
1
1
XORLW
Words:
1
Cycles:
1
Example:
Example
SWAPF REG,
11
1010
0xAF
W
Before Instruction
=
W
=
=
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
Operands:
5≤f≤7
Operation:
(W) → TRIS register f;
Description:
00
0000
XORWF
f
0110
0fff
The instruction is supported for code
compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly
address them.
Words:
1
Cycles:
1
0xB5
=
0x1A
0xA5
0x5A
Status Affected: None
Encoding:
=
After Instruction
0xA5
After Instruction
REG1
W
kkkk
Before Instruction
0
REG1
kkkk
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Words:
Cycles:
XORLW k
Example
To maintain upward compatibility
with future PIC12C67X products,
do not use this instruction.
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (dest)
Status Affected:
Z
Encoding:
00
0110
f,d
dfff
ffff
Description:
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Words:
1
Cycles:
1
Example
XORWF
REG
1
Before Instruction
REG
W
=
=
0xAF
0xB5
=
=
0x1A
0xB5
After Instruction
REG
W
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 69
PIC12C67X
NOTES:
DS30561A-page 70
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
10.0
DEVELOPMENT SUPPORT
10.1
Development Tools
10.3
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH−MP)
10.2
ICEPIC: Low-Cost PIC16CXXX
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXXX families of 8-bit
OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
10.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
10.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 71
PIC12C67X
10.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
10.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
10.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
DS30561A-page 72
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
10.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
10.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator
System.
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
MPASM has the following features to assist in developing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
10.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
10.12
C Compiler (MPLAB-C)
10.14
MP-DriveWay – Application Code
Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
10.15
SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
10.16
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC16/17 family of microcontrollers. The compiler provides powerful integration
capabilities and ease of use not found with other
compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display.
10.13
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 73
Emulator Products
Software Tools
DS30561A-page 74
Preliminary
Programmers
✔
KEELOQ
Evaluation Kit

PICDEM-3
PICDEM-2
PICDEM-1
SEEVAL
Designers Kit

KEELOQ
Programmer
PRO MATE II
Universal
Programmer

PICSTART
Plus Low-Cost
Universal Dev. Kit

PICSTART
Lite Ultra Low-Cost
Dev. Kit
Total Endurance
Software Model
✔
✔
✔
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
MP-DriveWay
Applications
Code Generator
✔
MPLAB C
Compiler
✔
✔
MPLAB
Integrated
Development
Environment
ICEPIC Low-Cost
In-Circuit Emulator
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
✔
✔
✔
✔
✔
✔
PIC14000
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C5X
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16CXXX
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
✔
✔
✔
✔
Available
3Q97
PIC17C75X
✔
✔
✔
24CXX
25CXX
93CXX
✔
✔
✔
HCS200
HCS300
HCS301
TABLE 10-1:
Demo Boards
PIC12C5XX
PIC12C67X
DEVELOPMENT TOOLS FROM MICROCHIP
 1997 Microchip Technology Inc.
PIC12C67X
11.0
ELECTRICAL CHARACTERISTICS FOR PIC12C67X
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................. .–40° to +125°C
Storage temperature ............................................................................................................................. –65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)................................................... –0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Total power dissipation (Note 1)...........................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................200 mA
Maximum current into VDD pin ..............................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by GPIO pins combined ...................................................................................................100 mA
Maximum current sourced by GPIO pins combined..............................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 75
PIC12C671-10
PIC12C672-10
PIC12LC671-04
PIC12LC672-04
PIC12C671/JW
PIC12C672/JW
Preliminary
 1997 Microchip Technology Inc.
VDD: 3.0V to 5.5V
VDD: 3.0V to 5.5V
VDD: 2.5V to 5.5V
VDD: 3.0V to 5.5V
IDD: 5 mA max. at 5.5V
IDD: 2.7 mA typ. at 5.5V
IDD: 2.0 mA typ. at 2.5V
IDD: 5 mA max. at 5.5V
INTRC
IPD: 21 µA max. at 4V
IPD: 1.5 µA typ. at 4V
IPD: 0.9 µA typ. at 2.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 2.5V to 5.5V
VDD: 3.0V to 5.5V
VDD: 3.0V to 5.5V
VDD: 3.0V to 5.5V
IDD: 5 mA max. at 5.5V
IDD: 2.7 mA typ. at 5.5V
IDD: 2.0 mA typ. at 2.5V
IDD: 5 mA max. at 5.5V
EXTRC
IPD: 21 µA max. at 4V
IPD: 1.5 µA typ. at 4V
IPD: 0.9 µA typ. at 2.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 3.0V to 5.5V
VDD: 3.0V to 5.5V
VDD: 2.5V to 5.5V
VDD: 3.0V to 5.5V
IDD: 5 mA max. at 5.5V
IDD: 2.7 mA typ. at 5.5V
IDD: 2.0 mA typ. at 2.5V
IDD: 5 mA max. at 5.5V
XT
IPD: 21 µA max. at 4V
IPD: 1.5 µA typ. at 4V
IPD: 0.9 µA typ. at 2.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 3.0V to 5.5V
IDD: 13.5 mA typ. at 5.5V
IDD: 30 mA max. at 5.5V
IDD: 30 mA max. at 5.5V
HS
Do not use in HS mode
IPD: 1.5 µA typ. at 4.5V
IPD: 1.5 µA typ. at 4.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 10 MHz max.
Freq: 10 MHz max.
VDD: 3.0V to 5.5V
VDD: 2.5V to 5.5V
VDD: 2.5V to 5.5V
IDD: 52.5 µA typ. at 32 kHz, 4.0V
IDD: 48 µA max. at 32 kHz, 2.5V IDD: 48 µA max. at 32 kHz, 2.5V
LP
Do not use in LP mode
IPD: 0.9 µA typ. at 4.0V
IPD: 5.0 µA max. at 2.5V
IPD: 5.0 µA max. at 2.5V
Freq: 200 kHz max.
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the
user select the device type that ensures the specifications required.
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC12C671-04
PIC12C672-04
PIC12C67X
TABLE 11-1:
DS30561A-page 76
OSC
PIC12C67X
11.1
DC Characteristics:
PIC12C671-04 (Commercial, Industrial, Extended(5))
PIC12C671-10 (Commercial, Industrial, Extended(5))
PIC12C672-04 (Commercial, Industrial, Extended(5))
PIC12C672-10 (Commercial, Industrial, Extended(5))
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
–40°C ≤ TA ≤ +125˚C (extended)
DC CHARACTERISTICS
Param.
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
D001
D001A
Supply Voltage
VDD
3.0
4.5
-
5.5
5.5
V
V
XT, INTRC, EXTRC and LP osc configuration
HS osc configuration
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
Device in SLEEP mode
D003
VDD start voltage to
ensure internal Poweron Reset signal
VPOR
-
VSS
-
V
See section on Power-on Reset for details
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D010
Supply Current (Note 2)
IDD
-
2.7
5
mA
7.7
5
mA
-
13.5
30
mA
-
5.5
1.5
1.5
1.5
D010C
D013
D020
D021
D021A
D021B
*
†
Note 1:
2:
3:
4:
5:
Power-down Current
(Note 3)
IPD
V/ms See section on Power-on Reset for details
µA
µA
µA
µA
XT, EXTRC osc configuration
(PIC12C67X-04)
FOSC = 4 MHz, VDD = 5.5V (Note 4)
INTRC osc configuration
FOSC = 4 MHz, VDD = 5.5V
HS osc configuration (PIC12C67X-10)
FOSC = 20 MHz, VDD = 5.5V
VDD = 4.0V, WDT enabled, –40°C to +85°C
VDD = 4.0V, WDT disabled, 0°C to +70°C
VDD = 4.0V, WDT disabled, –40°C to +85°C
VDD = 4.0V, WDT disabled, –40°C to +125°C
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For EXTRC osc configurations, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
Extended operating range is Advance Information for this device.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 77
PIC12C67X
11.2
DC Characteristics:
PIC12LC671-04 (Commercial, Industrial)
PIC12LC672-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min
Typ† Max Units
Conditions
D001
Supply Voltage
VDD
2.5
-
5.5
V
XT, INTRC, EXTRC and LP osc configuration
(DC - 4 MHz)
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
Device in SLEEP mode
D003
VDD start voltage to
ensure internal
Power-on Reset
signal
VPOR
-
VSS
-
V
See section on Power-on Reset for details
D004*
VDD rise rate to
ensure internal
Power-on Reset
signal
SVDD
0.05
-
-
D010
Supply Current
(Note 2)
IDD
-
2.0
3.8
mA
2.0
3.8
48
mA
D010B
D010A
D020
D021
D021A
*
†
Note 1:
2:
3:
4:
Power-down Current
(Note 3)
IPD
-
V/ms See section on Power-on Reset for details
22.5
µA
5.5
0.9
0.9
µA
µA
µA
XT, EXTRC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
INTRC osc configuration
FOSC = 4 MHz, VDD = 3.0V
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
VDD = 3.0V, WDT enabled, –40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, –40°C to +85°C
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For EXTRC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
DS30561A-page 78
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
11.3
DC Characteristics:
PIC12C671-04 (Commercial, Industrial, Extended(4))
PIC12C671-10 (Commercial, Industrial, Extended(4))
PIC12C672-04 (Commercial, Industrial, Extended(4))
PIC12C672-10 (Commercial, Industrial, Extended(4))
PIC12LC671-04 (Commercial, Industrial)
PIC12LC672-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D030
D031
D032
D033
D040
D040A
D041
D042
D042A
D043
D070
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
(in RC mode)
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
with TTL buffer
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
–40°C ≤ TA ≤ +125˚C (extended)
Operating voltage VDD range as described in DC spec Section 11.1 and
Section 11.2.
Sym
Min
Typ Max Units
Conditions
†
VIL
D060
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D083
D083A
†
Note 1:
2:
3:
4:
-
0.5V
0.2VDD
0.2VDD
V
V
V
VSS
-
0.3VDD
V
Note1
2.0
0.8VDD
0.8VDD
0.8VDD
0.7VDD
0.9VDD
50
250
VDD
VDD
VDD
VDD
VDD
VDD
400
V
V
V
V
V
V
µA
4.5 ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
-
-
±1
-
-
±5
±5
-
-
0.6
VIH
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
OSC1 (XT, HS and LP)
OSC1 (in EXTRC mode)
GPIO weak pull-up current
IPUR
Input Leakage Current (Notes 2, 3)
I/O ports
IIL
D080A
VSS
VSS
VSS
VOL
Note1
VDD = 5V, VPIN = VSS
µA Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
IOL = 8.5 mA, VDD = 4.5V,
–40°C to +85°C
0.6
V IOL = 7.0 mA, VDD = 4.5V,
–40°C to +125°C
OSC2/CLKOUT
0.6
V IOL = 1.6 mA, VDD = 4.5V,
–40°C to +85°C
0.6
V IOL = 1.2 mA, VDD = 4.5V,
–40°C to +125°C
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC12C67X be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Extended operating range is Advance Information for this device.
 1997 Microchip Technology Inc.
Preliminary
V
DS30561A-page 79
PIC12C67X
DC CHARACTERISTICS
Param
No.
Characteristic
Output High Voltage
I/O ports (Note 3)
D090
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
–40°C ≤ TA ≤ +125˚C (extended)
Operating voltage VDD range as described in DC spec Section 11.1 and
Section 11.2.
Sym
Min
Typ Max Units
Conditions
†
VOH
D090A
D092
OSC2/CLKOUT
D092A
Capacitive Loading Specs on
Output Pins
OSC2 pin
D100
D101
†
Note 1:
2:
3:
4:
COSC2
VDD - 0.7
-
-
V
VDD - 0.7
-
-
V
VDD - 0.7
-
-
V
VDD - 0.7
-
-
V
-
-
15
pF
IOH = -3.0 mA, VDD = 4.5V,
–40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
–40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
–40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
–40°C to +125°C
In XT, HS and LP modes when
external clock is used to drive
OSC1.
All I/O pins and OSC2
CIO
50
pF
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC12C67X be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Extended operating range is Advance Information for this device.
DS30561A-page 80
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
11.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 11-1: LOAD CONDITIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
 1997 Microchip Technology Inc.
for all pins except OSC2
for OSC2 output
Preliminary
DS30561A-page 81
PIC12C67X
11.5
Timing Diagrams and Specifications
FIGURE 11-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 11-2:
Parameter
No.
CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fos
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and EXTRC osc mode
DC
—
4
MHz HS osc mode (PIC12C67X-04)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz EXTRC osc mode
(Note 1)
.455
—
4
MHz XT osc mode
4
—
4
MHz HS osc mode (PIC12C67X-04)
4
—
10
MHz HS osc mode (PIC12C67X-10)
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and EXTRC osc mode
(Note 1)
250
—
—
ns
HS osc mode (PIC12C67X-04)
100
—
—
ns
HS osc mode (PIC12C67X-10)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
EXTRC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (PIC12C67X-04)
100
—
250
ns
HS osc mode (PIC12C67X-10)
5
—
—
µs
LP osc mode
2
TCY Instruction Cycle Time (Note 1) 200
—
DC
ns
TCY = 4/FOSC
3
TosL, External Clock in (OSC1) High
50
—
—
ns
XT oscillator
TosH or Low Time
2.5
—
—
µs
LP oscillator
10
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise
—
—
25
ns
XT oscillator
TosF or Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected
(has no loading) for the PIC12C67X.
DS30561A-page 82
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 11-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 11-1 for load conditions.
TABLE 11-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
15
30
ns
Note 1
11*
TosH2ckH
OSC1↑ to CLKOUT↑
—
15
30
ns
Note 1
12*
TckR
CLKOUT rise time
—
5
15
ns
Note 1
13*
TckF
CLKOUT fall time
—
5
15
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
16*
TckH2ioI
17*
TosH2ioV
18*
TosH2ioI
19*
20*
21*
—
—
0.5TCY + 20
ns
Note 1
0.25TCY + 25
—
—
ns
Note 1
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
OSC1↑ (Q1 cycle) to
Port out valid
—
—
80 - 100
ns
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in hold time)
TBD
—
—
ns
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
ns
TioR
Port output rise time
PIC12C67X
—
10
25
ns
PIC12LC67X
—
—
60
ns
PIC12C67X
—
10
25
ns
PIC12LC67X
—
—
60
ns
TioF
Port output fall time
22††*
Tinp
INT pin high or low time
20
—
—
ns
23††*
Trbp
GPIO change INT high or low time
20
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 83
PIC12C67X
FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
36
34
31
34
I/O Pins
TABLE 11-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
Parameter
No.
Sym
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, –40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, –40˚C to +125˚C
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
Power up Timer Period
28
72
132
ms
VDD = 5V, –40˚C to +125˚C
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
µs
*
†
32
Tost
33*
Tpwrt
34
TIOZ
Characteristic
Min
Typ†
Max
Units
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30561A-page 84
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 11-5: TIMER0 CLOCK TIMINGS
GP2/T0CKI
41
40
42
TMR0
Note: Refer to Figure 11-1 for load conditions.
TABLE 11-5:
TIMER0 CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40
Tt0H
T0CKI High Pulse Width
41
Tt0L
T0CKI Low Pulse Width
42
Tt0P
T0CKI Period
Min
No Prescaler
0.5TCY + 20*
With Prescaler
No Prescaler
With Prescaler
48
—
—
ns
10*
—
—
ns
0.5TCY + 20*
—
—
ns
10*
—
—
ns
Greater of:
20µs or TCY + 40*
N
—
—
ns
2Tosc
—
7Tosc
—
Tcke2tmrI Delay from external clock edge to timer increment
*
†
Typ† Max Units Conditions
N = prescale value
(1, 2, 4,..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 85
PIC12C67X
TABLE 11-6:
VDD (Volts)
GPIO PULL-UP RESISTOR RANGES
Temperature (°C)
Min
Typ
Max
Units
62K
73K
80K
81K
22K
27K
33K
36K
84K
84K
84K
84K
27K
31K
40K
43K
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
710K
890K
1.1M
1.2M
410K
470K
550K
585K
965K
1.2M
1.5M
1.6M
510K
580K
670K
715K
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
GP0/GP1
2.5
5.5
–40
25
85
125
–40
25
85
125
50K
63K
63K
63K
19K
25K
28K
31K
–40
25
85
125
–40
25
85
125
490K
610K
769K
810K
310K
360K
430K
465K
GP3
2.5
5.5
*
These parameters are characterized but not tested.
DS30561A-page 86
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
TABLE 11-7:
Parameter
No.
A/D CONVERTER CHARACTERISTICS:
PIC12C671-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))
PIC12C671-10 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))
PIC12C672-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))
PIC12C672-10 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
Resolution
—
—
8-bits
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NINT
Integral error
—
—
less than
±1 LSb
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NDIF
Differential error
—
—
less than
±1 LSb
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NFS
Full scale error
—
—
less than
±1 LSb
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NOFF
Offset error
—
—
less than
±1 LSb
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
—
Monotonicity
—
guaranteed
—
—
VSS ≤ AIN ≤ VREF
3.0V
—
VDD + 0.3
V
NR
VREF
Reference voltage
VAIN
Analog input voltage
VSS - 0.3
—
VREF + 0.3
V
ZAIN
Recommended
impedance of analog
voltage source
—
—
10.0
kΩ
IAD
A/D conversion current (VDD)
—
180
—
µA
Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current
(Note 2)
—
—
1
10
mA
µA
During sampling
All other times
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.
3: Extended operating range is Advance Information for this device.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 87
PIC12C67X
TABLE 11-8:
Parameter
No.
A/D CONVERTER CHARACTERISTICS:
PIC12LC671-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(4))
PIC12LC672-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(4))
Sym
Min
Typ†
Max
Units
Resolution
—
—
8-bits
—
VREF = VDD = 3.0V (Note 1)
NINT
Integral error
—
—
less than
±1 LSb
—
VREF = VDD = 3.0V (Note 1)
NDIF
Differential error
—
—
less than
±1 LSb
—
VREF = VDD = 3.0V (Note 1)
NFS
Full scale error
—
—
less than
±1 LSb
—
VREF = VDD = 3.0V (Note 1)
NOFF
Offset error
—
—
less than
±1 LSb
—
VREF = VDD = 3.0V (Note 1)
—
guaranteed
—
—
VSS ≤ AIN ≤ VREF
3.0V
—
VDD + 0.3
V
NR
—
*
†
Note 1:
2:
3:
4:
Characteristic
Monotonicity
Conditions
VREF
Reference voltage
VAIN
Analog input voltage
VSS - 0.3
—
VREF + 0.3
V
ZAIN
Recommended
impedance of analog voltage source
—
—
10.0
kΩ
IAD
A/D conversion current (VDD)
—
90
—
µA
Average current consumption when
A/D is on. (Note 2)
IREF
VREF input current
(Note 3)
—
—
1
10
mA
µA
During sampling
All other times
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF
When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.
Extended operating range is Advance Information for this device.
DS30561A-page 88
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 11-6: A/D CONVERSION TIMING
BSF ADCON0, GO
1 Tcy
(TOSC/2) (1)
131
Q4
130
132
A/D CLK
7
A/D DATA
6
5
4
3
2
1
NEW_DATA
OLD_DATA
ADRES
0
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 11-9:
A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
130
TAD
A/D clock period
1.6
2.0
130
TAD
A/D Internal RC
Oscillator source
TCNV
Conversion time
(not including S/H
time). Note 1
132
TACQ
Acquisition time
Max
Units
—
—
µs
µs
Conditions
VREF ≥ 3.0V
VREF full range
ADCS1:ADCS0 = 11
(RC oscillator source)
6.0
9.0
µs
PIC12LC67X, VDD = 3.0V
2.0
4.0
6.0
µs
PIC12C67X
—
9.5TAD
—
—
Note 2
20
—
µs
3.0
131
Typ†
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 89
PIC12C67X
NOTES:
DS30561A-page 90
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
12.0
DC AND AC CHARACTERISTICS - PIC12C67X
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some
graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is
for information only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 12-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
4.2
4.15
Frequency (MHz)
4.1
4.05
4.0
3.95
3.9
3.85
3.8
3.75
3.7
-40
25
85
125
Temperature (°C)
FIGURE 12-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 3.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
4.1
Frequency (MHz)
4.0
3.9
3.8
3.7
3.6
3.5
-40
25
85
125
Temperature (°C)
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 91
PIC12C67X
FIGURE 12-3: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 5.5V)
4.80
4.65
Frequency (MHz)
4.50
4.20
-40°C
+25°C
4.05
+85°
4.35
C
3.90
5°C
+12
3.75
3.60
3.45
3.30
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
E0
F0
OSCCAL Value (Hex)
FIGURE 12-4: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 3.5V)
4.80
4.65
Frequency (MHz)
4.50
4.35
C
-40°
+25°C
4.20
4.05
+85°
C
3.90
5°C
+12
3.75
3.60
3.45
3.30
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
OSCCAL Value (Hex)
DS30561A-page 92
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
TABLE 12-1:
DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C
Oscillator
Frequency
External RC
4 MHz
Internal RC
4 MHz
XT
4 MHz
LP
32 KHz
*Does not include current through external R&C.
VDD = 2.5V
VDD = 5.5V
250 µA*
420 µA
251 µA
7 µA
620 µA*
1.1 mA
775 µA
37 µA
FIGURE 12-5: WDT TIMER TIME-OUT
PERIOD vs. VDD
50
45
40
WDT period (µs)
35
30
Max +125°C
25
Max +85°C
20
Typ +25°C
15
10
MIn –40°C
5
2
DS30561A-page 93
3
4
5
VDD (Volts)
6
7
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
FIGURE 12-6: IOH vs. VOH, VDD = 2.5 V
FIGURE 12-8: IOL vs. VOL, VDD = 2.5 V
25
0
-1
20
Max –40°C
15
-3
IOL (mA)
IOH (mA)
-2
-4
Typ +25°C
10
Min +85°C
-5
Max –40°C
Typ +25°C
-6
Min +125°C
5
5°C
in +12
M
85°C
Min +
-7
500m
1.0
1.5
2.0
2.5
0
VOH (Volts)
0
250.0m
500.0m
1.0
VOL (Volts)
FIGURE 12-7: IOH vs. VOH, VDD = 5.5 V
FIGURE 12-9: IOL vs. VOL, VDD = 5.5 V
0
50
-5
Max –40°C
40
30
-15
°C
25
-20
+1
Min +125°C
–4
-25
0°
C
Ty
p
+2
5°
M
C
in
Min +85°C
20
+8
5°
C
in
M
Typ +25°C
IOL (mA)
IOH (mA)
-10
M
ax
10
-30
3.5
4.0
4.5
5.0
5.5
0
VOH (Volts)
250.0m
500.0m
750.0m
1.0
VOL (Volts)
DS30561A-page 94
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
13.0
PACKAGING INFORMATION
13.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
MMMMMMMM
XXXXXCDE
AABB
12C671/P
04ISAZ
9625
Example
8-Lead SOIC (208 mil)
MMMMMMM
XXXXXXX
AABBCDE
12C671
04I/SM
9624SAZ
8-Lead Windowed Ceramic Side Brazed (300 mil)
JW
MM
12C671
MMMMMM
Legend: MM...M
XX...X
AA
BB
C
D
E
Note:
*
Example
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
T = Tempe, Arizona, U.S.A.
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking
beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in
QTP price.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 95
PIC12C67X
13.2
8-Lead Plastic Dual In-line (300 mil)
N
α
C
E1 E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
e1
B
A1 A2 A
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
–
0.381
3.048
0.355
1.397
0.203
9.017
7.620
7.620
6.096
2.489
7.620
7.874
3.048
8
0.889
0.254
DS30561A-page 96
Inches
Notes
Min
Max
10°
0°
10°
4.064
–
3.810
0.559
1.651
0.381
10.922
7.620
8.255
7.112
2.591
7.620
9.906
3.556
8
–
–
–
0.015
0.120
0.014
0.055
0.008
0.355
0.300
0.300
0.240
0.098
0.300
0.310
0.120
8
0.035
0.010
0.160
–
0.150
0.022
0.065
0.015
0.430
0.300
0.325
0.280
0.102
0.300
0.390
0.140
8
–
–
Typical
Reference
Typical
Reference
Preliminary
Notes
Typical
Reference
Typical
Reference
 1997 Microchip Technology Inc.
PIC12C67X
13.3
8-Lead Plastic Surface Mount (SOIC - Medium, 208 mil Body)
e
h x 45°
B
N
Index
Area
E
H
α
C
L
Chamfer
h x 45°
1
2
3
D
Seating
Plane
Base
Plane
CP
A1
A
Package Group: Plastic SOIC (SM)
Millimeters
Symbol
Min
Max
α
0°
A
A1
B
C
D
E
e
H*
h
L
N
CP
1.778
0.101
0.355
0.190
5.080
5.156
1.270
7.670
0.381
0.508
14
–
 1997 Microchip Technology Inc.
Inches
Notes
Min
Max
8°
0°
8°
2.00
0.249
0.483
0.249
5.334
5.411
1.270
8.103
0.762
1.016
14
0.102
0.070
0.004
0.014
0.007
0.200
0.203
0.050
0.302
0.015
0.020
14
–
0.079
0.010
0.019
0.010
0.210
0.213
0.050
0.319
0.030
0.040
14
0.004
Reference
Preliminary
Notes
Reference
DS30561A-page 97
PIC12C67X
13.4
8-Lead Ceramic Side Brazed Dual In-Line with Window (JW) (300 mil)
N
α
E1 E
C
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
e1
B
A1 A3 A A2
D1
Package Group: Ceramic Side Brazed Dual In-Line (CER)
Millimeters
Inches
Symbol
α
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
S
S1
DS30561A-page 98
Min
Max
0°
3.937
0.635
2.921
1.778
0.406
1.371
0.228
13.004
7.416
7.569
7.112
2.540
7.620
7.620
3.302
2.540
0.127
10°
5.030
1.143
3.429
2.413
0.508
1.371
0.305
13.412
7.824
8.230
7.620
2.540
7.620
9.652
4.064
3.048
—
Notes
Typical
Typical
BSC
Typical
BSC
Preliminary
Min
Max
0°
0.155
0.025
0.115
0.070
0.016
0.054
0.009
0.512
0.292
0.298
0.280
0.100
0.300
0.300
0.130
0.100
0.005
10°
0.198
0.045
0.135
0.095
0.020
0.054
0.012
0.528
0.308
0.324
0.300
0.100
0.300
0.380
0.160
0.120
—
Notes
Typical
Typical
BSC
Typical
BSC
 1997 Microchip Technology Inc.
PIC12C67X
APPENDIX A: COMPATIBILITY
To convert code written for PIC16C5X to PIC12C67X,
the user should take the following steps:
1.
2.
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to 0000h.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 99
PIC12C67X
NOTES:
DS30561A-page 100
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
INDEX
A
A/D
Accuracy/Error ........................................................... 39
ADCON0 Register ...................................................... 33
ADIF bit ...................................................................... 35
Analog Input Model Block Diagram ............................ 36
Analog-to-Digital Converter ........................................ 33
Configuring Analog Port Pins ..................................... 37
Configuring the Interrupt ............................................ 35
Configuring the Module .............................................. 35
Connection Considerations ........................................ 39
Conversion Clock ....................................................... 37
Conversions ............................................................... 38
Converter Characteristics .......................................... 87
Delays ........................................................................ 36
Effects of a Reset ....................................................... 39
Equations ................................................................... 36
Flowchart of A/D Operation ........................................ 40
GO/DONE bit ............................................................. 35
Internal Sampling Switch (Rss) Impedence ............... 36
Operation During Sleep ............................................. 39
Sampling Requirements ............................................. 36
Sampling Time ........................................................... 36
Source Impedence ..................................................... 36
Time Delays ............................................................... 36
Transfer Function ....................................................... 39
Absolute Maximum Ratings ............................................... 75
ADDLW Instruction ............................................................ 60
ADDWF Instruction ............................................................ 60
ADIE bit .............................................................................. 18
ADIF bit .............................................................................. 19
ADRES Register .................................................... 13, 33, 35
ALU ...................................................................................... 7
ANDLW Instruction ............................................................ 60
ANDWF Instruction ............................................................ 60
Application Notes
AN546 ........................................................................ 33
AN556 ........................................................................ 22
Architecture
Harvard ........................................................................ 7
Overview ...................................................................... 7
von Neumann ............................................................... 7
Assembler
MPASM Assembler .................................................... 72
B
BCF Instruction .................................................................. 61
Bit Manipulation ................................................................. 58
Block Diagrams
Analog Input Model .................................................... 36
On-Chip Reset Circuit ................................................ 45
Timer0 ........................................................................ 27
Timer0/WDT Prescaler .............................................. 30
Watchdog Timer ......................................................... 53
BSF Instruction .................................................................. 61
BTFSC Instruction .............................................................. 61
BTFSS Instruction .............................................................. 62
C
C bit .................................................................................... 15
CAL0 bit ............................................................................. 21
CAL1 bit ............................................................................. 21
CAL2 bit ............................................................................. 21
CAL3 bit ............................................................................. 21
 1997 Microchip Technology Inc.
CALFST bit .........................................................................21
CALL Instruction .................................................................62
CALSLW bit ........................................................................21
Carry bit ................................................................................7
Clocking Scheme ................................................................10
CLRF Instruction .................................................................62
CLRW Instruction ...............................................................62
CLRWDT Instruction ...........................................................63
Code Examples
Changing Prescaler (Timer0 to WDT) ........................31
Changing Prescaler (WDT to Timer0) ........................31
Indirect Addressing .....................................................23
Code Protection ........................................................... 41, 55
COMF Instruction ...............................................................63
Computed GOTO ...............................................................22
Configuration Bits ...............................................................41
D
DC bit ..................................................................................15
DC Characteristics
PIC12C671 .................................................................77
PIC12C672 .................................................................77
DECF Instruction ................................................................63
DECFSZ Instruction ............................................................63
Development Support .................................................... 3, 71
Development Tools .............................................................71
Diagrams - See Block Diagrams
Digit Carry bit ........................................................................7
Direct Addressing ...............................................................23
E
Electrical Characteristics
PIC12C67X .................................................................75
External Brown-out Protection Circuit .................................49
External Power-on Reset Circuit ........................................49
F
Family of Devices
PIC12CXXX ..................................................................4
Features ...............................................................................1
FSR Register ......................................................... 13, 14, 23
Fuzzy Logic Dev. System (fuzzyTECH-MP) .....................73
G
General Description ..............................................................3
GIE bit .................................................................................50
GOTO Instruction ...............................................................64
GPIF bit ..............................................................................52
GPIO ............................................................................ 25, 47
GPIO Register ....................................................................13
GPPU bit .............................................................................16
I
I/O Interfacing .....................................................................25
I/O Ports .............................................................................25
I/O Programming Considerations .......................................26
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............71
ID Locations ........................................................................41
INCF Instruction ..................................................................64
INCFSZ Instruction .............................................................64
In-Circuit Serial Programming ..................................... 41, 55
INDF Register .............................................................. 14, 23
Indirect Addressing .............................................................23
Initialization Conditions for All Registers ............................47
Instruction Cycle .................................................................10
Instruction Flow/Pipelining ..................................................10
Instruction Format ...............................................................57
Preliminary
DS30561A-page 101
PIC12C67X
Instruction Set
ADDLW ...................................................................... 60
ADDWF ...................................................................... 60
ANDLW ...................................................................... 60
ANDWF ...................................................................... 60
BCF ............................................................................ 61
BSF ............................................................................ 61
BTFSC ....................................................................... 61
BTFSS ....................................................................... 62
CALL .......................................................................... 62
CLRF .......................................................................... 62
CLRW ........................................................................ 62
CLRWDT .................................................................... 63
COMF ........................................................................ 63
DECF ......................................................................... 63
DECFSZ ..................................................................... 63
GOTO ........................................................................ 64
INCF ........................................................................... 64
INCFSZ ...................................................................... 64
IORLW ....................................................................... 64
IORWF ....................................................................... 65
MOVF ......................................................................... 65
MOVLW ..................................................................... 65
MOVWF ..................................................................... 65
NOP ........................................................................... 66
OPTION ..................................................................... 66
RETFIE ...................................................................... 66
RETLW ...................................................................... 66
RETURN .................................................................... 67
RLF ............................................................................ 67
RRF ............................................................................ 67
SLEEP ....................................................................... 67
SUBLW ...................................................................... 68
SUBWF ...................................................................... 68
SWAPF ...................................................................... 69
TRIS ........................................................................... 69
XORLW ...................................................................... 69
XORWF ...................................................................... 69
Section ....................................................................... 57
INTCON Register ............................................................... 17
INTEDG bit ......................................................................... 16
Internal Sampling Switch (Rss) Impedence ....................... 36
Interrupts ............................................................................ 41
A/D ............................................................................. 50
GP2/INT ..................................................................... 50
GPIO Port .................................................................. 50
Section ....................................................................... 50
TMR0 ......................................................................... 52
TMR0 Overflow .......................................................... 50
IORLW Instruction .............................................................. 64
IORWF Instruction .............................................................. 65
IRP bit ................................................................................ 15
K
KeeLoq Evaluation and Programming Tools ................... 73
L
Loading of PC .................................................................... 22
M
MCLR ........................................................................... 44, 47
Memory
Data Memory ............................................................. 11
Program Memory ....................................................... 11
Program Memory Map
PIC12C67X ........................................................ 11
Register File Map
DS30561A-page 102
PIC12C67X ........................................................ 12
MOVF Instruction ............................................................... 65
MOVLW Instruction ............................................................ 65
MOVWF Instruction ........................................................... 65
MP-DriveWay - Application Code Generator .................. 73
MPLAB C ........................................................................ 73
MPLAB Integrated Development Environment Software 72
N
NOP Instruction ................................................................. 66
O
Opcode .............................................................................. 57
OPTION Instruction ........................................................... 66
OPTION Register ............................................................... 16
Orthogonal ........................................................................... 7
OSC selection .................................................................... 41
OSCCAL Register .............................................................. 21
Oscillator
EXTRC ...................................................................... 46
HS .............................................................................. 46
INTRC ........................................................................ 46
LP .............................................................................. 46
XT .............................................................................. 46
Oscillator Configurations .................................................... 42
Oscillator Types
EXTRC ...................................................................... 42
HS .............................................................................. 42
INTRC ........................................................................ 42
LP .............................................................................. 42
XT .............................................................................. 42
P
Package Marking Information ............................................ 95
Packaging Information ....................................................... 95
Paging, Program Memory .................................................. 22
PCL .................................................................................... 58
PCL Register ......................................................... 13, 14, 22
PCLATH ............................................................................. 47
PCLATH Register .................................................. 13, 14, 22
PCON Register ............................................................ 20, 46
PD bit ........................................................................... 15, 44
PIC12C67X DC and AC Characteristics ............................ 91
PICDEM-1 Low-Cost PIC16/17 Demo Board .................... 72
PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 72
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............... 72
PICMASTER In-Circuit Emulator ..................................... 71
PICSTART Plus Entry Level Development System ......... 71
PIE1 Register ..................................................................... 18
Pinout Description
PIC12C67X .................................................................. 9
PIR1 Register .................................................................... 19
POP ................................................................................... 22
POR ................................................................................... 46
Oscillator Start-up Timer (OST) ........................... 41, 46
Power Control Register (PCON) ................................ 46
Power-on Reset (POR) .................................. 41, 46, 47
Power-up Timer (PWRT) ..................................... 41, 46
Power-Up-Timer (PWRT) .......................................... 46
Time-out Sequence ................................................... 46
Time-out Sequence on Power-up .............................. 48
TO .............................................................................. 44
POR bit .............................................................................. 20
Power ................................................................................. 44
Power-down Mode (SLEEP) .............................................. 54
Prescaler, Switching Between Timer0 and WDT ............... 31
PRO MATE II Universal Programmer .............................. 71
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
Product Identification System - PIC12C67X .................... 115
Program Branches ............................................................... 7
Program Memory
Paging ........................................................................ 22
Program Memory Map
PIC12C67X ................................................................ 11
Program Verification .......................................................... 55
PS0 bit ............................................................................... 16
PS1 bit ............................................................................... 16
PS2 bit ............................................................................... 16
PSA bit ............................................................................... 16
PUSH ................................................................................. 22
R
RC Oscillator ...................................................................... 43
Read Modify Write ............................................................. 26
Read-Modify-Write ............................................................. 26
Register File ....................................................................... 11
Registers
Map
PIC12C67X ........................................................ 12
Reset Conditions ........................................................ 47
Reset ............................................................................ 41, 44
Reset Conditions for Special Registers ............................. 47
RETFIE Instruction ............................................................. 66
RETLW Instruction ............................................................. 66
RETURN Instruction .......................................................... 67
RLF Instruction ................................................................... 67
RP0 bit ......................................................................... 11, 15
RP1 bit ............................................................................... 15
RRF Instruction .................................................................. 67
S
SEEVAL Evaluation and Programming System .............. 73
Services
One-Time-Programmable (OTP) ................................. 5
Quick-Turnaround-Production (QTP) ........................... 5
Serialized Quick-Turnaround Production (SQTP) ........ 5
SFR .................................................................................... 58
SFR As Source/Destination ............................................... 58
SLEEP ......................................................................... 41, 44
SLEEP Instruction .............................................................. 67
Software Simulator (MPLAB SIM) ................................... 73
Special Features of the CPU ............................................. 41
Special Function Register
PIC12C67X ................................................................ 13
Special Function Registers ................................................ 58
Special Function Registers, Section .................................. 12
Stack .................................................................................. 22
Overflows ................................................................... 22
Underflow ................................................................... 22
STATUS Register .............................................................. 15
SUBLW Instruction ............................................................. 68
SUBWF Instruction ............................................................ 68
SWAPF Instruction ............................................................. 69
Interrupt ..............................................................27
Interrupt Timing ..................................................28
Prescaler ............................................................30
Prescaler Block Diagram ....................................30
Section ...............................................................27
Switching Prescaler Assignment ........................31
Synchronization ..................................................29
T0CKI .................................................................29
T0IF ....................................................................52
Timing .................................................................27
TMR0 Interrupt ...................................................52
Timing Diagrams
A/D Conversion ..........................................................89
CLKOUT and I/O ........................................................83
External Clock Timing .................................................82
Time-out Sequence ....................................................48
Timer0 ................................................................. 27, 85
Timer0 Interrupt Timing ..............................................28
Timer0 with External Clock .........................................29
Wake-up from Sleep via Interrupt ...............................55
TO bit ..................................................................................15
TOSE bit .............................................................................16
TRIS Instruction ..................................................................69
TRIS Register .............................................................. 14, 25
Two’s Complement ...............................................................7
U
UV Erasable Devices ............................................................5
W
W Register
ALU ...............................................................................7
Wake-up from SLEEP ........................................................54
Watchdog Timer (WDT) ................................... 41, 44, 47, 53
WDT ...................................................................................47
Block Diagram ............................................................53
Period .........................................................................53
Programming Considerations .....................................53
Timeout .......................................................................47
X
XORLW Instruction .............................................................69
XORWF Instruction .............................................................69
Z
Z bit .....................................................................................15
Zero bit .................................................................................7
T
T0CS bit ............................................................................. 16
TAD ..................................................................................... 37
Timer0
RTCC ......................................................................... 47
Timers
Timer0
Block Diagram ................................................... 27
External Clock .................................................... 29
External Clock Timing ........................................ 29
Increment Delay ................................................. 29
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 103
PIC12C67X
LIST OF EXAMPLES
Example 3-1: Instruction Pipeline Flow ............................
Example 4-1: Indirect Addressing ....................................
Example 5-1: Read-Modify-Write Instructions
on an I/O Port ............................................
Example 6-1: Changing Prescaler (Timer0→WDT) .........
Example 6-2: Changing Prescaler (WDT→Timer0) .........
Example 7-1: Calculating the Minimum Required
Sample Time..............................................
Example 7-2: Doing an A/D Conversion ..........................
Example 8-1: Saving STATUS and W Registers
in RAM .......................................................
10
23
26
31
31
36
38
52
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
Figure 4-10:
Figure 4-11:
Figure 5-1:
Figure 5-2:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 8-1:
Figure 8-2:
Figure 8-3:
Figure 8-4:
Figure 8-5:
Figure 8-6:
Figure 8-7:
Figure 8-8:
Figure 8-9:
Figure 8-10:
Figure 8-11:
PIC12C67X Block Diagram .......................... 8
Clock/Instruction Cycle ............................... 10
PIC12C67X Program Memory Map
and Stack.................................................... 11
PIC12C67X Register File Map.................... 12
Status Register (Address 03h, 83h)............ 15
OPTION Register (Address 81h) ................ 16
INTCON Register (Address 0Bh, 8Bh) ....... 17
PIE1 Register (Address 8Ch) ..................... 18
PIR1 Register (Address 0Ch) ..................... 19
PCON Register (Address 8Eh) ................... 20
OSCCAL Register (Address 8Fh) ............... 21
Loading of PC In Different Situations.......... 22
Direct/Indirect Addressing........................... 23
Equivalent Circuit for a Single I/O Pin......... 25
Successive I/O Operation ........................... 26
Timer0 Block Diagram ................................ 27
Timer0 Timing: Internal Clock/
No Prescale ................................................ 27
Timer0 Timing: Internal Clock/
Prescale 1:2 ................................................ 28
Timer0 Interrupt Timing .............................. 28
Timer0 Timing with External Clock ............. 29
Block Diagram of the Timer0/
WDT Prescaler ........................................... 30
ADCON0 Register (Address 1Fh)............... 33
ADCON1 Register (Address 9Fh)............... 34
A/D Block Diagram ..................................... 35
Analog Input Model..................................... 36
A/D Transfer Function................................. 39
Flowchart of A/D Operation ........................ 40
Configuration Word ..................................... 41
Crystal Operation (or Ceramic Resonator)
(XT, HS or LP OSC Configuration) ............. 42
External Clock Input Operation
(XT, HS or LP OSC Configuration) ............. 42
External Parallel Resonant Crystal
Oscillator Circuit.......................................... 43
External Series Resonant Crystal
Oscillator Circuit......................................... 43
External RC Oscillator Mode ...................... 43
Simplified Block Diagram of On-chip
Reset Circuit ............................................... 45
Time-out Sequence on Power-up
(MCLR not Tied to VDD): Case 1 ................ 48
Time-out Sequence on Power-up
(MCLR Not Tied To VDD): Case 2............... 48
Time-out Sequence on Power-up
(MCLR Tied to VDD)................................... 48
External Power-on Reset Circuit
(for Slow VDD Power-up)............................. 49
DS30561A-page 104
Figure 8-12:
Figure 8-13:
Figure 8-14:
Figure 8-15:
Figure 8-16:
Figure 8-17:
Figure 8-18:
Figure 8-19:
Figure 9-1:
Figure 11-1:
Figure 11-2:
Figure 11-3:
Figure 11-4:
Figure 11-5:
Figure 11-6:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 12-6:
Figure 12-7:
Figure 12-8:
Figure 12-9:
External Brown-out Protection Circuit 1 ..... 49
External Brown-out Protection Circuit 2 ..... 49
Interrupt Logic ............................................ 50
INT PIN Interrupt Timing ............................ 51
Watchdog Timer Block Diagram................. 53
Summary of Watchdog Timer Registers .... 53
Wake-up from Sleep Through Interrupt ...... 55
Typical In-Circuit Serial Programming
Connection ................................................. 55
General Format for Instructions.................. 57
Load Conditions ......................................... 81
External Clock Timing ................................ 82
CLKOUT and I/O Timing ............................ 83
Reset, Watchdog Timer, Oscillator
Start-Up Timer, and Power-Up Timer
Timing......................................................... 84
Timer0 Clock Timings................................. 85
A/D Conversion Timing .............................. 89
Calibrated Internal RC Frequency Range
vs. Temperature (VDD = 5.0V)
(Internal RC is Calibrated to 25°C, 5.0V) ... 91
Calibrated Internal RC Frequency Range
vs. Temperature (VDD = 3.0V)
(Internal RC is Calibrated to 25°C, 5.0V) ... 91
Internal RC Frequency vs. Calibration
Value (VDD = 5.5V)..................................... 92
Internal RC Frequency vs. Calibration
Value (VDD = 3.5V)..................................... 92
WDT Timer Time-out Period vs. VDD ......... 93
IOH vs. VOH, VDD = 2.5 V............................ 94
IOH vs. VOH, VDD = 5.5 V............................ 94
IOL vs. VOL, VDD = 2.5 V............................. 94
IOL vs. VOL, VDD = 5.5 V............................. 94
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 4-1:
Table 5-1:
Table 6-1:
Table 7-1:
Table 7-2:
Table 8-1:
Table 8-2:
Table 8-3:
Table 8-4:
Table 8-5:
Table 8-6:
Table 9-1:
Table 9-2:
Table 10-1:
Table 11-1:
Table 11-2:
Table 11-3:
Table 11-4:
Table 11-5:
Table 11-6:
Preliminary
PIC12CXXX Family of Devices .................... 4
PIC12C67X Pinout Description .................... 9
PIC12C67X Special Function Register
Summary .................................................... 13
Summary of Port Registers ........................ 25
Registers Associated with Timer0 .............. 31
TAD vs. Device Operating Frequencies ...... 37
Summary of A/D Registers ......................... 40
Capacitor Selection
For Ceramic Resonators - PIC12C67X ...... 42
Capacitor Selection
For Crystal Oscillator - PIC12C67X............ 42
Time-out in Various Situations ................... 46
Status Bits and Their Significance.............. 46
Reset Condition for Special Registers........ 47
Initialization Conditions for all registers ...... 47
Opcode Field Descriptions ......................... 57
Instruction Set Summary ........................... 59
Development Tools From Microchip........... 74
Cross Reference of Device Specs for
Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) ................................ 76
Clock Timing Requirements ....................... 82
CLKOUT and I/O Timing Requirements ..... 83
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer ................. 84
Timer0 Clock Requirements ....................... 85
GPIO Pull-up Resistor Ranges................... 86
 1997 Microchip Technology Inc.
PIC12C67X
Table 11-7:
Table 11-8:
Table 11-9:
Table 12-1:
A/D Converter Characteristics:
PIC12C671-04 (Commercial, Industrial,
Automotive(3))
PIC12C671-10 (Commercial, Industrial,
Automotive(3))
PIC12C672-04 (Commercial, Industrial,
Automotive(3))
PIC12C672-10 (Commercial, Industrial,
Automotive(3)) ............................................. 87
A/D Converter Characteristics:
PIC12LC671-04 (Commercial, Industrial,
Automotive(4))
PIC12LC672-04 (Commercial, Industrial,
Automotive(4)) ............................................. 88
A/D Conversion Requirements ................... 89
Dynamic IDD (Typical) WDT Enabled, 25°C ................................... 93
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 105
PIC12C67X
NOTES:
DS30561A-page 106
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel
for you to use in extending your technical staff with
microcontroller and memory experts.
To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
the latest component data and software tool updates,
provides technical help and embedded systems
insights, and discusses how Microchip products provide project solutions.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers. To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either
the Internet or the CompuServe communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the
address: mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense. The
Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
 1997 Microchip Technology Inc.
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allow multiple users various baud rates
depending on the local point of access.
The following connect procedure applies in most locations.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
will appear.
5. Type MCHIPBBS, depress the <Enter> key and you
will be connected to the Microchip BBS.
In the United States, to find the CompuServe phone
number closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with “Host Name:”, type NETWORK, depress
the <Enter> key and follow CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
number.
Microchip regularly uses the Microchip BBS to distribute
technical information, application notes, source code,
errata sheets, bug reports, and interim patches for
Microchip systems software products. For each SIG, a
moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files
are accepted from the user community in general to
limit the spread of computer viruses.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
970301
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. FlexROM, MPLAB and fuzzyLAB, are
trademarks and SQTP is a service mark of Microchip in
the U.S.A.
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
trademark of Intel Corporation. Windows is a trademark
and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of
their respective companies.
Preliminary
DS30561A-page 107
PIC12C67X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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RE:
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Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC12C67X
Y
N
Literature Number: DS30561A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30561A-page 108
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
PIC12C67X PRODUCT IDENTIFICATION SYSTEM
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
Package:
SM
P
JW
I
E
04
10
Temperature
Range:
Frequency
Range:
Device
=
=
=
=
=
=
=
=
a)
208 mil SOIC
300 mil PDIP
300 mil Windowed Ceramic Side Brazed
b)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4 MHz
c)
10 MHz
PIC12C671-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
PIC12C671-04I/SM
Industrial Temp., SOIC
package, 4 MHz, normal
VDD limits
PIC12C671-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
PIC12C671
PIC12C672
PIC12C671T (Tape & reel for SOIC only)
PIC12C672T (Tape & reel for SOIC only)
PIC12LC671
PIC12LC672
PIC12LC671T (Tape & reel for SOIC only)
PIC12LC672T (Tape & reel for SOIC only)
Please contact your local sales office for exact ordering procedures.
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 109
PIC12C67X
NOTES:
DS30561A-page 110
Preliminary
 1997 Microchip Technology Inc.
PIC12C67X
NOTES:
 1997 Microchip Technology Inc.
Preliminary
DS30561A-page 111
WORLDWIDE SALES & SERVICE
AMERICAS
ASIA/PACIFIC
EUROPE
Corporate Office
Hong Kong
United Kingdom
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Technical Support: 602 786-7627
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India
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JAPAN
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Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122
3/24/97
Microchip Technology Inc.
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Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc.
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Toronto
Microchip Technology Inc.
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Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
All rights reserved.  1997, Microchip Technology Incorporated, USA.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30561A - page 112
 1997 Microchip Technology Inc.
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