903A 1 924. i
US 20050280742A1
(19) United States
(12) Patent Application Publication (10) Pub. N0.: US 2005/0280742 A1
(43) Pub. Date:
J affe
(54)
HDTV CHIP WITH A SINGLE IF STRIP FOR
HANDLING ANALOG AND DIGITAL
Dec. 22, 2005
Publication Classi?cation
RECEPTION
(51)
(52)
Int. Cl.7 ..................................................... .. H04N 5/44
US. Cl. .......................................... .. 348/726; 348/725
(76) Inventor: Steven Todd Ja?'e, Irvine, CA (US)
Correspondence Address:
(57)
MCANDREWS HELD & MALLOY, LTD
500 WEST MADISON STREET
SUITE 3400
Methods and systems for processing television signals are
CHICAGO, IL 60661
(21) Appl' NO‘:
.
ABSTRACT
disclosed herein, and may comprise communicating analog
and digital intermediate frequency (IF) signals via a single
processing path that couples a TV radio frequency (RF)
11/197’735
_
tuner to an IF demodulator and/or to a decoder, that pro
(22) Flled'
Aug‘ 2’ 2005
cesses said analog and digital IF signals. The analog and
Related US Application Data
digital IF signals may be ?ltered via a surface acoustic Wave
(SAW) ?lter, for example. The ?ltered analog and digital IF
(63) Continuation-in-part of application No. 10/448,062,
5i_gI_1a15 maybe ampli?ed The ampli?ed ?ltered analog and
?led on May 30, 2003, which is a continuationdmpart
of application No. 09/739,349, ?led on Dec. 15, 2000.
digital IF signals may' be received. The ampli?ed ?ltered
analog and dlgltel IF slgnels may be IF demodulated by the
(60) Provisional application No. 60/401,043, ?led on Aug.
6, 2002
AH aIldiO portion 0f the IF deIIlOdlllated Output Signal may
be decoded via a BTSC decoder, for example.
IF demodulator to generate an IF demodulated output signal.
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Patent Application Publication Dec. 22, 2005 Sheet 12 0f 12
START
US 2005/0280742 A1
l
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Filtering analog and digital intermediate frequency (IF) telev ision signals utilizing a surface acoustic wave (SAW) ?lter, for
example
902eS
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Amplifying the ?ltered analog and digital IF signals.
Communicating the ampli?ed ?ltered analog and digital lF signals via a single processing path that couples a TV radio
’frequency (RF) tuner to an IF demodulator and/or a decoder, that processes the ampli?ed ?ltered analog and digital lF
signals.
QOSeS
.
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IF demodulating the ampli?ed ?ltered analog and digital IF signals by the IF demodulator to generate an IF demodulated
output signal.
908aS
.
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Decoding an audio portion ofthe IF demodulated output signal to generate an 'audio output signal.
Decoding a video portion of the IF demodulated output signal to generate a video output signal‘
912eS
FINISH
FIG. 8E
Dec. 22, 2005
US 2005/0280742 A1
HDTV CHIP WITH A SINGLE IF STRIP FOR
HANDLING ANALOG AND DIGITAL RECEPTION
CROSS-REFERENCE TO RELATED
[0001]
APPLICATIONS/INCORPORATION BY
Congress mandated that current broadcast television service
REFERENCE
must, in time, be completely converted to digital television.
While digital television (DTV) utiliZes the same broadcast
This application is a Continuation-In-Part of US.
Non-Provisional Application entitled “Digital IF Demodu
lator With Carrier Recovery,” Ser. No. 10/448,062, ?led
May 30, 2003, Which is a Continuation-In-Part of US.
Non-Provisional Application entitled “Digital IF Demodu
lator for Video Applications,” Ser. No. 09/739,349, ?led
Dec. 15, 2000, and Which also claims the bene?t of U S.
Provisional Patent Application 60/401,043, ?led on Aug. 6,
2002.
[0002]
[0011] Broadcasters utiliZing digital television systems
may also have the capability to provide multicasting and
datacasting services using the same bandWidth allocated for
conventional analog television systems. For these reasons,
This application also makes reference to:
[0003] US. application Ser. No. 10/774,037 (Attorney
Docket No. 15424US01) ?led Feb. 6, 2004;
[0004] US. application Ser. No. 10/943,267 (Attorney
Docket No. 15440US02) ?led Sep. 17, 2004;
[0005] US. application Ser. No. 10/943,596 (Attorney
Docket No. 15458US02) ?led Sep. 17, 2004; and
[0006] US. application Ser. No. 11/137,528 (Attorney
Docket No. 16411US02) ?led May 25, 2005.
[0007] All of the above stated applications are hereby
incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
very high frequency (VHF) spectral band and ultra-high
frequency spectral (UHF) band as conventional television
broadcasting systems, digital television utiliZes different
modulation techniques than conventional analog television
broadcasting systems. Conventional analog television
broadcasting systems modulate video using amplitude
modulation
and the accompanying audio is modulated
using frequency modulation
DTV utiliZes a plurality
of modulation techniques for transmitting and receiving
packetiZed digital signals. In the United States of America,
an eight level vestigial sideband (VSB) modulation scheme
is utiliZed. In some regions of Europe and Asia, for example,
coded orthogonal frequency division multiplexing is the
modulation scheme of choice. On the other hand, digital
satellite systems (DSS) utiliZe quadrature phase shift keying,
While cable television (CATV) system utiliZes quadrature
amplitude modulation
[0012] In the United States, a plurality of broadcast for
mats promulgated by the Advanced Television Standards
Committee (ATSC) has been adopted for DTV applications.
Some of these formats comprise progressive-scan video
comprising 480 scan lines referred to as 480p, interlaced 4:3
video having 480 scan lines referred to as 480i, interlaced
video having 1080 scan lines referred to as 1080i and
progressive-scan video having 720 scan lines referred to as
720p. Standard de?nition (SD) television (SDTV) utiliZes
[0008]
Certain embodiments of the invention relate to high
the interlaced 480i and progressive 480p formats. The
de?nition television (HDTV). More speci?cally, certain
picture quality provided by SDTV is comparable in certain
embodiments of the invention relate to a method and system
respects to conventional NTSC 525 lines systems. High
for a HDTV chip With a single intermediate frequency (IF)
de?nition (HD) television (HDTV) utiliZes the interlaced
strip for handling analog and digital signals.
1080i and progressive 720p formats in a 16:9 aspect ratio.
The resolution of the HDTV interlaced 1080i and progres
sive 720p formats may be converted to loWer resolution such
as the interlaced 480i and progressive 480p formats pro
BACKGROUND OF THE INVENTION
[0009] Digital television, popularly referred to as DTV, is
an enhanced television system capable of transmitting and
vided by SDTV.
receiving digitiZed signals, displaying digital images and
[0013]
playing digital audio. While some of these features may be
present in current analog television systems such as national
on an RF carrier using 8-level VSB or 8 VSB, and trans
television standards committee (NTSC), sequential couleur
avec memoire (SECAM) and phase alternate line (PAL), the
combination of digitiZed transmission, reception, video and
audio distinguishes digital television from current analog
television systems.
[0010] Digital television employs various digital signal
In the US for example, DTV signals are modulated
mitted in a six (6) MHZ channel as compressed 4:2:0
MPEG-2 formatted packetiZed streams. These packetiZed
streams contain both audio and video information. For this
reason, a conventional analog system is unable to receive a
transmitted DTV signal. In order to decode a received
8-level VSB signal, an ATSC-compliant DTV receiver or a
set-top box is required.
processing techniques and utiliZes scarce bandWidth in a
more spectrally ef?cient manner to transport and present
audio and video signals in a Way that is superior to current
[0014] In some conventional HDTV application, different
integrated circuits are coupled to provide various analog and
digital services. These non-integrated solutions are cost
analog television systems. In this regard, digital television
prohibitive, especially for loW to mid range television (TV)
alloWs more channels containing more information to be
manufacturers. Existing integrated TV-on-a-chip solutions
broadcasted Within an equivalent bandWidth utiliZed by
current analog television systems. Accordingly, any excess
HDMI, and POD/CableCard. In addition, existing integrated
bandWidth can be re-allocated for use by other types of
do not support analog video input, and lacks support for
TV-on-a-chip solutions do not have 3D and 2D comb ?lters
and motion adaptive deinterlacer functionalities. Further
communication systems. Broadcasters utiliZing digital tele
vision systems are therefore, capable of providing over-the
air television signals containing higher picture resolutions
more, existing integrated TV-on-a-chip solutions receive
analog and digital video signals via separate paths, thereby
than current analog broadcast television systems
increasing the silicon surface and cost of implementation.
Dec. 22, 2005
US 2005/0280742 A1
[0015] Further limitations and disadvantages of conven
tional and traditional approaches Will become apparent to
one of skill in the art, through comparison of such systems
With some aspects of the present invention as set forth in the
remainder of the present application With reference to the
drawings.
[0028]
in accordance With an embodiment of the invention.
[0029] FIG. 8E is a How diagram illustrating exemplary
steps for processing television signals, in accordance With an
embodiment of the invention.
BRIEF SUMMARY OF THE INVENTION
[0016]
DETAILED DESCRIPTION OF THE
INVENTION
A system and/or method for a HDTV chip With a
single intermediate frequency (IF) strip for handling analog
and digital signals, substantially as shoWn in and/or
described in connection With at least one of the ?gures, as set
forth more completely in the claims.
[0017] Various advantages, aspects and novel features of
the present invention, as Well as details of an illustrated
FIG. 8D illustrates a television receiver for pro
cessing analog and digital signals utiliZing a single IF strip,
[0030]
Certain embodiments of the invention may be
found in a method and system for a high de?nition television
(HDTV) chip With a single intermediate frequency (IF) strip
for handling analog and digital signals. The single integrated
HDTV chip for analog and digital reception may support
digital and dual analog signal processing of video signals
embodiment thereof, Will be more fully understood from the
acquired via an IF input, a high de?nition multimedia
folloWing description and draWings.
interface (HDMI)/digital video interface (DVI) input, an
analog baseband input (component HD video, composite
BRIEF DESCRIPTION OF SEVERAL VIEWS OF
THE DRAWINGS
[0018]
FIG. 1 is a block diagram of an exemplary system
for single integrated high de?nition television chip for
analog and digital reception, in accordance With an embodi
ment of the invention.
[0019]
FIG. 2 is a block diagram of the inband analog
front end block 220 of FIG. 2, in accordance With an
embodiment of the invention.
[0020] FIG. 3 is a functional block diagram of the NTSC
demodulator block 222 of FIG. 2, in accordance With an
embodiment of the invention.
[0021] FIG. 4 is a block diagram illustrating the out-of
band (OOB) receiver block 257 of FIG. 2, in accordance
With an embodiment of the invention.
[0022]
FIG. 5 is a functional block diagram of an exem
plary system for single integrated high de?nition television
chip for analog and digital reception, in accordance With an
embodiment of the invention.
[0023]
FIG. 6 is a block diagram of an exemplary system
con?guration of the single integrated high de?nition televi
sion chip for analog and digital reception illustrating various
usage modes, in accordance With an embodiment of the
invention.
[0024] FIG. 7 is a How chart illustrating exemplary steps
that may be utiliZed for processing television signals, in
accordance With an aspect of the invention.
[0025]
FIG. 8A illustrates an exemplary television
receiver for processing analog and digital signals, Which
may be utiliZed in accordance With an embodiment of the
invention.
[0026] FIG. 8B illustrates a high level diagram of a signal
processing system utiliZing a TV tuner and audio signal
decoder With a single IF strip, in accordance With an
embodiment of the invention.
[0027] FIG. 8C illustrates a high level diagram of a signal
processing system utiliZing a TV tuner and video signal
demodulator With a single IF strip, in accordance With an
embodiment of the invention.
video, S-video), ITU656 input, and/or a HD-DVI input. The
IF input may comprise a vestigial sideband (VSB) input, a
quadrature amplitude modulation (QAM) input, and an
NTSC input. In this regard, the single integrated high
de?nition television chip for analog and digital reception
may provide picture-in-picture functionalities, 3D and 2D
comb ?ltering and motion adaptive deinterlacer functional
ities Without the need for off-chip processing. Furthermore,
the single integrated high de?nition television chip for
analog and digital reception may be adapted to receive
analog and digital signals via a single communication path.
In this regard, the single integrated high de?nition television
chip for analog and digital reception may utiliZe a single
intermediate frequency (IF) strip for communicating analog
and/or digital signals for processing, thereby increasing
processing speed and decreasing implementation costs.
[0031]
FIG. 1 is a block diagram of an exemplary system
for single integrated high de?nition television chip for
analog and digital reception, in accordance With an embodi
ment of the invention. Referring to FIG. 1, the single
integrated HDTV chip for analog and digital reception 202
may comprise an HDMI receiver 258, multiplexers 236, . .
. , 240, a video front end 242, a dual video decoder 204, a
video and graphics processor 206, 2D graphics generator
208, peripheral inputs 230, HD/SD video encoder 210, video
digital-to-analog converters (DACs) 232, and an in-band
analog front end 220. The single integrated HDTV chip for
analog and digital reception 202 may also comprise an
NTSC demodulator 222, audio processor 224, MPEG-2
video decoder 212, audio DACs 234, QAM/VSB demodu
lator 218, MPEG-2 demultiplexer 216, MIPS processor 214,
OOB receiver block 257, common interface hardWare con
troller 252, EIA/CEA 909 smart antenna interface 248,
POD/CableCard interface 250, DDR interface 246, and a
PCI interface 244.
[0032]
The multiplexers 236, . . . , 240 may each be
adapted to select an analog signal and communicate the
selected signal to the video front end block 242 for process
ing. The single integrated HDTV chip for analog and digital
reception 202 may support digital and dual analog signal
processing of video signals acquired via an IF input (VSB,
QAM, NTSC), an HDMI/DVI input, an analog baseband
input (component HD video, composite video, S-video),
ITU656 input, and/or a HD-DVI input. Component (Y)
US 2005/0280742 A1
signals and S-video (L) signals may be multiplexed by the
multiplexer 236. Component (Pr) signals and S-video (C)
signals may be multiplexed by the multiplexer 238. Simi
larly, component (Pb) signals and a ?rst composite signal
may be multiplexed by the multiplexer 240.
[0033] The video front end block 242 may comprise
suitable circuitry and/or logic and may be adapted to convert
the analog signal communicated from one or more of the
multiplexers 236, . . . , 240 to a digital format. The converted
digital signal may then be communicated to the dual video
decoder 204 for processing. In one aspect of the invention,
the video front end block may comprise three 10-bit A/D
converters for converting analog signals received from the
multiplexers 236, . . . , 240.
[0034] The dual video decoder 204 may comprise suitable
circuitry and/or logic and may be adapted to decode a dual
analog signal for PIP functionality. The dual video decoder
204 may decode component, S-video, and/or composite
video signals received from the video front end block 242.
NTSC/PAL composite video signal may be decoded into
digital component video signals. The dual video decoder 204
may be adapted to accept composite (480i), S-video (480i),
and component HD input (480i, 480p, 720p, 1080i). In one
aspect of the invention, the dual video decoder 204 may
comprise a primary and a secondary decoder, for example.
The primary decoder may be supported by a vertical blank
ing interval (VBI) decoder for Teletext, North American
basic teletext standard (NABTS), Close Caption, copy gen
eration management system for analog (CGMS-A) and/or
Wide screen sWitching (WSS).
Dec. 22, 2005
and may be adapted to scale, deinterlace and/or further
enhance the decoded video signals received from the dual
video decoder 204. For example, the video and graphics
processor 204 may comprise a scaler With a scaling range
from 1/32 (doWn scaling) to 32 (upscaling). HoriZontal scal
ing modes may comprise tWo half-band ?lter stages and one
?nal 8-tap poly-phase ?lter, for example. Vertical scaling
modes may comprise 2-tap FIR, 4-tap FIR, and block
averaging. Non-linear scaling may-also be utiliZed With a
full screen display of a 4:3 video on a 16:9 television.
[0038] In another aspect of the invention, the graphics
processor 206 may comprise a motion adaptive de-interlac
ing (MAD) block 209 and a picture enhancement processor
(PEP) 207. The MAD block may utiliZe reverse 3:2 and 2:2
pulldoWn and may accept 489i and generated 489p video
signals. In addition, the MAD block may utiliZe ?ve ?elds
of video to determine motion and may provide cross
chrominance removal. The PEP 207 may utiliZe user-con
trolled color space and brightness to improve image quality.
The PEP 207 may be adapted to provide color adjustment,
luma adjustment, color clip protection for illegal pixel
values, and letterbox and center cut detection. Chroma and
luma adjustments may be achieved by the PEP 207 utiliZing,
for example, a look-up table (LUT) for maximum ?exibility.
[0039] The 2D graphics generator 208 may comprise
suitable circuitry and/or logic and may be adapted to gen
erate graphics, such as menus, for rendering the generated
graphics on top of the video signals processed by the video
and graphics processor 206. The 2D graphics generator 208
may also be adapted to acquire input from the peripheral
[0035] Teletext information may be generated, for
example, by a data communications information service
input block 230 and render 2D graphics based on the
used to transmit information from remote data banks to
inputs from a keypad; IR receiver, IR Blaster, UARTs,
vieWers. The secondary decoder may be adapted to accept
PWM, SmartCard interface, an I2C master interface, an SPI
composite (480i) input and may be utiliZed for analog PIP
master interface, and general purpose input/output interface,
for example.
mode. In this regard, the dual video decoder may comprise
a 3D comb ?lter 226 and a 2D comb ?lter 228 for ?ltering
composite video signals. The 3D comb ?lter 226 may be
utiliZed to ?lter a composite video signal for a main video
signal output and the 2D comb ?lter 228 may be adapted to
?lter a composite video signal for a PIP display signal. A
more detailed description of a 3D comb ?lter, Which may be
representative of 3D comb ?lter 226, is disclosed in US.
application Ser. No. 10/943,267 (Attorney Docket No.
15440US02), Which is incorporated herein by reference in
its entirety. A more detailed description of a 2D comb ?lter,
Which may be representative of 2D comb ?lter 228, is
disclosed in Us. application Ser. No. 10/943,596 (Attorney
Docket No. 15458US02), Which is incorporated herein by
reference in its entirety.
[0036] In an exemplary aspect of the invention, the dual
video decoder 204 may also be adapted to acquire ITU656
SD video signals and/or HD-DVI video signals for decod
ing. The HD-DVI input port, as Well as the HD-DVO digital
output port of the single integrated HDTV chip for analog
and digital reception 202, may supports SD, HD and/or
VESA formats, 12-bit and 24-bit data formats, and 4:4:4
RGB, 4:4:4 YCrCb, and 4:2:2 YCrCb pixel formats.
[0037]
Decoded video signals may be communicated from
the dual video decoder 204 to the video and graphics
processor 206 for further processing. The video and graphics
processor 206 may comprise suitable circuitry and/or logic
acquired input. The peripheral input block 230 may acquire
[0040] The HD/SD video encoder 210 may comprise
suitable circuitry, logic and/or code and may be adapted to
acquire a processed video signal from the video and graphics
processor 206 and encode the signal into NTSC, PAL,
component (480i, 480p, 720p, 1080i), S-video, and/or com
posite formats. In addition, the HD/SD video encoder 210
may support digital standards, such ITU-R 656 and DVI
signal encoding. VBI-encoded data may be combined With
appropriate lines of video prior to generating the encoded
output signal. In an exemplary aspect of the invention, the
HD/SD encoder 210 may communicate digitiZed encoded
signal to the video DACs block 232. The video DACs block
232 may then generate composite, component, and/or
S-video signal outputs.
[0041] The audio processor 224 may comprise suitable
circuitry, logic and/or code and may be adapted to decode
audio signals acquired via the 12S interface and/or via the
SPDIF interface of the single integrated HDTV chip for
analog and digital reception 202. The single integrated
HDTV chip for analog and digital reception 202 may be
adapted to acquire audio signals via an 125 interface and/or
via an SPDIF interface. The acquired audio signals may be
communicated to the audio processor 224 for decoding. The
audio processor 224 may be adapted to process Dolby digital
and MPEG layer 1,2 signals. In addition, the audio processor
224 may support SPDIF pass-through of digital theatre
Dec. 22, 2005
US 2005/0280742 A1
systems (DTS) and advanced audio coding (MC) audio
streams, packetiZed elementary stream (PBS) or elementary
stream (ES) output of MPEG MC.
[0042] The audio processor 224 may also support MPEG
Layer 1, 2, and 3, DTS, and Dolby digital for interface to an
external decoder, compressed MC, MPEG Layer 1, 2, and 3,
DTS, and Dolby digital on an 12S output, and decoding
compressed audio signals from system DRAM, for example.
The audio processor 224 may support Dolby 5.1-channel
audio coding for data rates 32, 40, 48, 56, 64, 80, 96, 112,
128, 160, 192, 224, 256, 320,384, 448, 512, 576, 640 kbps,
frequencies. The internal programmable gain ampli?er 302
may comprise suitable logic, circuitry, and/or code that may
be adapted to adjust a gain of incoming signal. The auto
matic gain control block 304 may utiliZe closed loop auto
matic gain control. In accordance With an embodiment of the
invention the A/D converter 306 in the inband analog front
end block 220 may comprise a 12-bit A/D converter, for
example. Composite baseband signals may be communi
cated from the inband analog front end block 220 to the dual
video decoder 204 for processing. NTSC and BTSC signals
may be communicated to the NTSC demodulator 222.
for example. In addition, the audio processor 224 may
support MPEG Layer 1 audio coding for data rates 32, 64,
Similarly, digital content signals may be communicated to
the QAM/VSB demodulator 218.
96, 128, 160, 192, 224, 256, 288, 320, 352, 384, 416, 448
[0048] FIG. 3 is a functional block diagram of the NTSC
demodulator block 222 of FIG. 2, in accordance With an
embodiment of the invention. Referring to FIG. 4, the
NTSC demodulator block 222 may comprise a demodulator
block 402, an audio data path block 404, and a video data
path block 406. The output of the audio data path block 404
may comprise an analog multiplexed modulated IF audio
output and the output of the video data path block 406 may
comprise an NTSC output, for example. The demodulator
block 402 may be adapted to receive an output signal from
the inband analog front end 220, for example, Which may be
tranferred to a digital mixer 403 in the demodulator block
402. The digital mixer 403 may convert the IF data in the
output signal from the inband analog front end 220 to a
kbps, for example. The audio processor 224 may also
provide support for MPEG Layer 2 audio coding for data
rates 32, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256,
320, 384 kbps, for example.
[0043] Decoded digital audio signals may be communi
cated from the audio processor 224 to the audio DACs 234
and/or to audio signal outputs of the single integrated HDTV
chip for analog and digital reception 202. Decoded audio
signals may be communicated by the audio processor 224 as
audio signal outputs utiliZing an SPDIF output interface, an
I2S output interface, and/or a compressed audio output
interface. The audio DACs 234 may be adapted to generate
stereo digital audio outputs.
[0044] The HDMI receiver 258 may comprise suitable
circuitry and/or code and may be adapted to support stan
dard, enhanced, or high-de?nition video, as Well as multi
channel digital audio on a single cable. The HDMI receiver
258 may also be adapted to process signals in any ATSC
HDTV standard, as Well as 8-channel digital audio signals.
Decoded audio and video signals may be communicated by
the HDMI receiver 258 to the audio decoder 224 and the
video and graphics processor 206, respectively, for further
processing. In an exemplary embodiment of the invention,
the single integrated HDTV chip for analog and digital
reception 202 may utiliZe a high-de?nition multimedia inter
face (HDMI) receiver 258 to receive and process HDMI
signals via a DVI-HDMI port. HDMI may provide a secure
interface betWeen an audio/video source, such as a set-top
box, DVD player, and audio/video receiver and an audio
and/or video monitor, such as a digital television (DTV).
[0045] FIG. 2 is a block diagram of the inband analog
front end block 220 of FIG. 2, in accordance With an
embodiment of the invention. Referring to FIG. 2, the
inband analog front end block 220 may comprise a pro
grammable gain ampli?er (PGA) block 302, an automatic
gain control block (AGC) 304 and an analog-to-digital
(A/D) converter 306.
[0046] The automatic gain control block 304 may com
prise a digital AGC circuit Which may be adapted to control
or adjust various poWer levels seen by the VSB/QAM
demodulator 218 and the NTSC demodulator 222, all shoWn
in FIG. 2. Adjustment of these voltage levels may be utiliZed
to remove or otherWise mitigate the effects of any amplitude
variation in the signals entering the single chip integrated
DTV receiver. An optimal loading of the A/D converters in
the inband analog front end block 220 may be provided by
adjusting these voltage levels.
[0047]
The inband analog front end block 220 may be
con?gured to receive analog signals at the common IF center
complex baseband data stream. Apilot recovery loop may be
utiliZed to control operation of the digital mixer 403. The
output of the digital mixer 403 may be ?ltered and tranferred
to the audio data path block 404.
[0049] The audio data path block 404 may comprise a
complex mixer, a ?lter-and-decimate stage, and a frequency
demodulation stage. The complex mixer may translate a PM
audio carrier, for example, a 4.5 MHZ NTSC carrier, to a
baseband signal. The ?lter-and-decimate stage may be
adapted to remove the video from the signal and reduce its
sampling rate. The resulting decimated signal may be fre
quency demodulated to produce a monaural, or a baseband
BTSC multiplexed signal.
[0050] The video data path block 406 may comprise a
Nyquist ?lter, a group delay ?lter, an audio trap ?lter, and a
gain/DC-level compensation block. The Nyquist ?lter may
be con?gured to perform Nyquist shaping, Which is tradi
tionally done by a SAW ?lter at IF. The group-delay ?lter
may provide group delay compensation Within a speci?ed
FCC mask. The audio trap ?lter may be adapted to remove
the audio signal from the video signal. Different audio trap
?lters may be implemented for different audio carrier loca
tions. The gain/DC-level compensation block may acquire
AGC and DC-level information from a video decoder and
adjust the signal accordingly so as to attain a proper signal
loading and DC-level for a composite video broadcasting
signal (CVBS). The output of the video data path 406 may
be routed through the dual video decoder 204 (FIG. 2) in the
single integrated HDTV chip for analog and digital recep
tion 202. The multiplexed modulated IF audio output from
the audio data path 404 communicated to the audio proces
sor 224 for further processing.
[0051] The NTSC demodulator block 222 may comprise a
BTSC decoder 223 Which may be adapted to receive input
United States Broadcast Television Systems Committee
Dec. 22, 2005
US 2005/0280742 A1
(BTSC) compliant baseband multiplexed TV audio signals
from an NTSC IF demodulator block Within the NTSC
front end block 220. The QAM/VSB demodulator 218 may
operate in any of a plurality of standardiZed modes such as
the CATV ITU-T J.83 Annex A/C mode. The ITU-T J.83
demodulator 222. The BTSC decoder 223 may be adapted to
operate, for example, in a single channel mode supporting a
plurality of output rates such as 32 KHZ, 44.1 KHZ, and 48
KHZ I2S outputs. The BTSC decoder 223 Within the NTSC
demodulator block 222 may also be adapted to produce
Annex A/C standard is utiliZed primarily outside the United
States for digital cable television applications. In Europe, the
ITU-T J .83 Annex A/C standard is knoWn as the Digital
Video Broadcast for Cable (DVB-C) standard. The Digital
stereo output, single or dual monaural output, or an inde
Audio-Visual Council (DAVIC) has adopted the DVB-C
pendent separate audio programming (SAP) output.
standard along With various extensions to support 256
QAM. The IEEE 802.14 committee has adopted Annex A/C
as one of tWo possible physical layer standards for cable
modems. Notwithstanding, the QAM/VSB demodulator 218
may provide support for the full standard, including up to 8
[0052]
In another aspect of the invention, the BTSC
decoder 223 may be adapted to function as a digital multi
channel television sound decoder. Abaseband analog BTSC
composite signal extracted by the NTSC IF demodulator
Within the NTSC demodulator block 222 may be received by
the BTSC decoder and processed fully in digital logic to
recover the main left and right channels (L+R), stereo (L/R)
channel, or SAP channels. The stereo decoding may include
sum (L+R) channel, difference (L-R) channel decoding and
rematrixing of sum and difference channel to retrieve left (L)
and right (R) channel. The main channel (sum or mono
channel) decoding may be processed as a subset of the stereo
decoding. The difference channel decoding may comprise
pilot tone recovery by using, for example, a phase locked
loop (PLL), double side band (DSB) demodulation, and loW
pass ?ltering of the decoded difference signal. A variable
de-emphasis circuit may provide DBX-TV compliant noise
reduction. The sum channel decoding may comprise loW
pass ?ltering and de-emphasis. A second audio program
ming (SAP) decoding function may comprise FM demodu
lation and DBX variable de-emphasis and an integrated
poWer detector may be utiliZed for pilot tone and SAP FM
carrier. The BTSC decoder may automatically sWitch
betWeen stereo and monaural modes based on a pilot tone
poWer or SAP decoding. Muting may be achieved based on
a poWer associated With the SAP FM carrier.
[0053]
The decoded PCM output from the BTSC decoder
block Within the NTSC demodulator block 222 may be
programmed to sampling rates of, for example, 32 KHZ,
MHZ channeliZation, as described in ITU-T J .83 Annex A
and C, as Well as all DAVIC extensions.
[0056] The QAM/VSB demodulator 218 may also be
adapted to operate in a ITU-T J .83 Annex B mode, and may
provide support for ITU-T J .83 Annex B standard, Which is
currently the dominant standard for digital television deliv
ery over CATV netWorks in the United States. ITU-T J .83
Annex B has been adopted as the physical layer standard by
various organiZations such as the Society of Cable Telecom
munications Engineers (SCTE DVS-031), the Multimedia
Cable Network Systems (MCNS-DOCSIS), and the IEEE
802.14 Committee.
[0057] Demodulated digital signals may be communicated
from the QAM/VSB demodulator 218 to the MPEG-2
demultiplexer 216 for demultiplexing. The MPEG-2 demul
tiplexer 216 may comprise DES/DVB descrambler for up to
32 PIDs utiliZing 64-bit and 56-bit DES keys, for example.
The MPEG-2 demultiplexer 216 may be adapted to parse a
plurality of independent transport streams. In one embodi
ment of the invention, the MPEG-2 demultiplexer 216 may
be adapted to parse ?ve independent transport streams. In
addition, the MPEG-2 demultiplexer 216 may utiliZe PES
packet extraction for up to 32 PID channels and may support
32 section ?lters. The MPEG-2 demultiplexer 216 may also
be adapted to acquire MPEG stream from an external port,
44.1 KHZ, and 48 KHZ. These data rates may be supported
a SmartCard port, and/or from an IEEE 1394 port. A
by the on-chip audio DACs 234. Additionally, the left/right
channel PCM may be output digitally through either the 12S
POD/CableCard port 250 may also be utiliZed to supply data
to the MPEG-2 demultiplexer 216.
bus or the on-chip Audio DACs 234.
[0054]
The ATSC A/53 Digital Television Standard Was
developed by the Digital HDTV Grand Alliance of vendors
and is the accepted standard for the terrestrial transmission
of SDTV and HDTV signals in the United States. The ATSC
A/53 Digital Television Standard is based on an 8-level
vestigial sideband (8-VSB) trellis coded modulation format
With a nominal payload data rate of about 19.4 Mbps in a 6
MHZ channel. A high data rate, adopted for use in a cable
[0058]
The demultiplexed MPEG video stream may be
communicated to the MPEG-2 video decoder 212 for decod
ing. The MPEG-2 video decoder 212 may comprise an
MPEG-V processor, a motion compute engine, a Huff-man
decoder, inverse quantiZer, an inverse discrete cosine trans
former (IDCT) module, and a pixel reconstructor. The
MPEG-2 video decoder 212 may be adapted to decode an
HD [email protected] video stream and generate a standard de?ni
tion (SD) output With reduced memory requirement. The
television environment, is also speci?ed by the standard.
decoded MPEG video stream may then be communicated to
The ATSC A/53 Digital Television Standard may utiliZes
16-VSB to provide a payload data rate of 38.8 Mbps in a 6
MHZ channel. This mode is also compliant With Annex D of
the video and graphics processor 206 for further processing.
The demultiplexed audio stream may be communicated
from the MPEG-2 demultiplexer 216 to the audio processor
the ITU-T J .83 speci?cations. The QAM/VSB demodulator
224 for processing.
218 in the single integrated HDTV chip for analog and
digital reception 202 is compliant With the ATSC A/53
Digital Television Standard’s normal mode and high data
rate mode.
[0055] The QAM/VSB demodulator 218 may comprise
suitable circuitry and/or logic and may be adapted to
demodulate digital signals acquired from the inband analog
[0059] The OOB receiver block 257 may comprise an
QOB analog front end block 256 and a QPSK OOB demodu
lator block 254. The OOB receiver block 257 may be
adapted to process OOB IF signals Within the single inte
grated HDTV chip for analog and digital reception 202.
FIG. 4 is a block diagram illustrating the out-of-band (OOB)
receiver block 257 of FIG. 2, in accordance With an embodi
Dec. 22, 2005
US 2005/0280742 A1
ment of the invention. Referring to FIG. 4, the out-of-band
receiver block 257 may comprise an out-of-band (OOB)
integral plus-proportional ?lter. An output of the loop ?lter
analog front end
integrator may be read to provide loop monitoring and/or
directly Written to provide control by an acquisition proces
256, an out-of-band (OOB) QPSK
demodulator 254, a DVS-167 FEC/DVS-178 FEC block
506, and and out-of-band output interface block 508. The
OOB AFE block 256 may comprise a programmable gain
ampli?er, an A/D converter, an automatic gain control
(AGC), and a voltage controlled oscilator (VCO).
The OOB receiver block 257 integrated Within the
[0060]
may be utiliZed to control, for eXample, a derotator. The
sor.
[0065]
The OOB QPSK demodulator block 254 may com
prise a decision feedback equaliZer (DFE) With feed-forWard
taps and feedback taps, Which may be adapted to remove or
single integrated HDTV chip for analog and digital recep
otherWise mitigate the effects of ISI generated by Worst-case
coaXial cable channels including a Wide variety of impair
tion 202 may be utiliZed With an an IF centered signal. The
ments such as un-terminated stubs. The equaliZer coef?
OOB AFE block 256 integrated Within the OOB receiver
block 257 may utiliZe a frequency agile local oscillator (LO)
that may be adapted to doWnconvert any channel in, for
eXample, the 70-150 MHZ frequency range to a SAW
centered IF. The desired channel may then be sub-sampled
by an A/D converter.
cients may be updated at, for eXample, every baud cycle to
provide fast convergence.
[0061] The OOB QPSK demodulator block 254 may be
adapted to receive an IF sampled input from the A/D
converter and may doWnconvert the sampled input to base
band With a full quadrature miXer driven by a carrier
recovery loop, for eXample. The resulting true-baseband
[0066] The DVS-167 (DAVIC) FEC/DVS-178 (DIGICI
PHERII) FEC block 506, Which may also be referred to as
an out-of-band FEC block 506, may comprise a frame
synchroniZation function, a deinterleaving function, a Reed
Solomon (RS) decoding function, and a derandomiZation
function, for eXample. At least some of these functions may
be programmable so that the out-of-band FEC block 506
may be adapted to handle both the DigiCipher II and DAVIC
out-of-band FEC speci?cations. The OOB output interface
508 may be utiliZed to communicate OOB output signals
data stream may be resampled under control of a clock
recovery loop to produce a data stream that is correctly
from the OOB receiver 257 to the common interface hard
sampled in both frequency and phase. The I and Q baseband
signal components may then be ?ltered by dual square-root
Ware, controller 252 and/or to the MPEG-2 demultipleXer
216.
Nyquist ?lters.
[0062] The OOB receiver block 257 may also comprise,
for eXample, tWo automatic gain control loops (AGC). The
?rst loop may be closed locally at the programmable gain
[0067] The MIPS processor 214 may utiliZe caches With
bridging to memory and a local bus, Where external periph
erals may be attached. Integrated peripherals may be
accessed through the peripherals block 230 and may com
ampli?er and may be referred to as the inner IF loop, or the
AGC loop. The second loop may be closed at the tuner and
prise UARTS, counter/timers, GPIO, keypad, LED, IR
may be referred to as the outer tuner loop, or the delayed
eXample. The MIPS processor 214 may comprise 16 k
2-Way I-cache, 16 KB 2 Way D-cache, and a memory
management unit (MMU) With a table look-aside buffer
AGC loop. Accordingly, gain control may be divided
betWeen the inner and outer tuner loops. Each loop may
comprise a poWer estimate, a threshold comparison, and a
?rst order loop ?lter. The ?lter output may be utiliZed to
directly control the PGA gain in the case of the inner loop
TX/RX, IR Keyboard, BSC (12C) and SP1 controllers, for
(TLB), for eXample. Further, 16-bit instruction support and
EJTAG support may also be provided by the MIPS processor
214.
and may be fed into a sigma-delta modulator to generate an
analog control voltage in the case of the outer loop.
[0063] A baud recovery loop comprising a timing error
discriminant, a loop ?lter and a digital timing recovery block
may be utiliZed to control a digital resampler. The timing
error discriminant may be adapted to output a neW value for
each baud that is ?ltered by a digital integral-plus-propor
[0068] The PCI interface 244 may comprise a 32-bit PCI
33 MHZ interface may be PCI revision 2.3 compliant and
may provide PCI host and client modes, PCI master and
target modes, 2 DMA engines (TX and RX), full bandWidth
burst at 32 bytes/transfer; and 2 mailboX and 2 doorbell
registers for inter-processor communication.
[0069] The POD/CableCard interface 250 may comprise
an Open Cable compliant CableCARD/POD direct interface
tional loWpass ?lter, Which features programmable coef?
cients. The loop integrator may be read in order to provide
loop monitoring or Written for direct control by the acqui
With glue-less interface to a POD module. The single
sition processor block 240. Data from the loop ?lter may be
integrated HDTV chip for analog and digital reception 202
applied to a digitally controlled frequency synthesiZer that
may utiliZe the DDR interface 246 to communicate With
off-chip memory. The DDR interface 246 may comprise a
may permit the baud rate to be varied over.
[0064]
The OOB receiver block 257 may also comprise
32-bit 200 MHZ DDR-DRAM controller, for eXample.
OOB carrier frequency/phase recovery and tracking loops,
[0070]
Which may be all-digital loops that are con?gured to simul
taneously offer a Wide acquisition range and a large phase
plary system for single integrated high de?nition television
FIG. 5 is a functional block diagram of an eXem
noise tracking capability. The OOB carrier frequency/phase
chip for analog and digital reception, in accordance With an
embodiment of the invention. Referring to FIG. 5, the single
recovery and tracking loops may be adapted to estimate the
integrated HDTV chip for analog and digital reception 102
angle and/or direction for frequency/phase compensation.
may comprise a QAM/VSB demodulator 218, an out-of
band (OOB) receiver 257, an NTSC demodulator 222, an
HDMI receiver 258, an MPEG-2 transport processor/demul
tipleXer 216, an audio processor 224, a dual video decoder
204, an HD/SD video encoder 210, an MPEG-2 video
An integral plus-proportional ?lter may be utiliZed to ?lter
the out-of-band carrier frequency/phase recovery and track
ing loops. The bandWidth of the loop may be adjusted by
programming the integrator and linear coef?cients of the
Dec. 22, 2005
US 2005/0280742 A1
decoder 212, and an EIA/CEA 909 smart antenna interface
interface to a POD/CableCard. OOB signals generated by
248. Analog and/or digital signals may be acquired by the
single integrated HDTV chip for analog and digital recep
the ?rst tuner 104 or the second tuner 106 may be commu
tion 102 via IF inputs, such as VSB, QAM, and NTSC, an
HDTV chip for analog and digital reception 102.
HDMI/DVI input, a plurality of analog baseband inputs, an
ITU656 input, and/or a HD-DVI input, for example. The
HD-DVI video input may be adapted to supply digital video
signals, such as 24-bit digital video. The analog baseband
integrated HDTV chip for analog and digital reception 102
inputs may comprise component video inputs, composite
video inputs, and/or S-video inputs.
nicated to the OOB receiver 257 Within the single integrated
[0075] Audio signals may be communicated to the single
via an 125 port or an SPDIF port, for example. The single
integrated HDTV chip for analog and digital reception 102
may also utiliZe an off-chip DDR-SDRAM and/or a ?ash
memory during signal processing. Peripheral inputs may be
[0071] The IF inputs may comprise in-band and/or out
utiliZed to add 2D graphic support for the output video
of-band signals received from a ?rst tuner 104 and/or a
second tuner 106. The ?rst tuner 104 and the second tuner
signal, for example. The single integrated HDTV chip for
106 may comprise suitable circuitry and/or logic and may be
HD or SD analog or digital video and audio signals.
adapted to receive an input signal 112, such as a cable or an
Advanced Television Systems Committee (ATSC) signal.
The ?rst tuner 104 and the second tuner 106 may then
generate corresponding IF in-band and out-of-band signals,
Which may be communicated to the single integrated HDTV
chip for analog and digital reception 102. In this regard, the
?rst tuner 104 and the second tuner 106 may comprise an
in-band processing block 108 and an out-of-band processing
block 110. The in-band IF signals may comprise VSB
signals, QAM signals, and/or NTSC/PAL signals, for
example. In an exemplary aspect of the invention, signal
outputs from both tuners 104 and 106 may be communicated
to the single integrated HDTV chip for analog and digital
reception 102 for processing by a dual analog signal pro
cessor, for example. The dual analog signals may then be
analog and digital reception 102 may generate as outputs
[0076]
FIG. 6 is a block diagram of an exemplary system
con?guration of the single integrated high de?nition televi
sion chip for analog and digital reception illustrating various
usage modes, in accordance With an embodiment of the
invention. Referring to FIG. 6, there is shoWn a single
integrated HDTV chip for analog and digital reception 702,
a CableCard interface 732, a smart antenna interface 734, a
video encoder 728 an A/D converter 730, DDR SDRAM
722, an optional IEEE 1394 interface 724, a ?ash or ROM
memory 720, an optional PIP block 712, a stereo A/D
converter 718, an optional PIP 708, a dual tuner 706,
HDMI/Component converters 736 and 738, and an audio/
video
sWitch board 704.
utiliZed for picture-in-picture (PIP) functionality.
[0077] In an exemplary aspect of the invention, the single
integrated HDTV chip for analog and digital reception 702
may be adapted to support a plurality of display con?gura
[0072] The ?rst NTSC/PAL analog video decoder Within
the dual NTSC/PAL decoder 136 may be supported by
motion adaptive de-interlacing and a 3D comb ?lter. The
second NTSC/PAL decoder Within the dual NTSC/PAL
decoder 136 may be utiliZed for analog picture-in-picture
tions utiliZing video signals received from the dual tuner
706, the A/V sWitch board 704, the DDR SDRAM 722, the
?ash/ROM 720, and/or the optional PIP 712. For example,
there may be a main display and a picture-in-picture (PIP)
(PIP) functionality. In this -regard, the second NTSC/PAL
decoder may support composite and/or S-video inputs.
Advanced 2D graphics processing capability may be pro
analog and digital reception 702. The main display may be
HD or SD (480i, 480p, 720p, 1080i) compatible. The
display supported by the single integrated HDTV chip for
vided by an integrated processor, such as an advanced 2D
picture-in-picture (PIP) display may be a WindoW Within the
main display. The tWo displays may be fed from a plurality
Graphics Processor offered by Broadcom Corporation of
Irvine, Calif.
of sources. These sources may comprise a digital MPEG
[0073]
The cable/terrestrial receiver may be adapted to
directly sample a tuner output, such as an output from tuner
104 or tuner 106, With an A/D converter. The cable/terres
trial receiver may also digitally re-sample and demodulate
the signal With recovered clock and carrier timing. Further,
the cable/terrestrial receiver may ?lter and equaliZe the data
Decoder (480i, 480p, 720p, 1080i), a digital HD_DVI (480i,
480p, 720p, 1089i and 60 HZ VESA modes), an analog
base-band Video, CVBS (480i), S-Video(480i), Component
(480i, 480p, 720p, 1080i), ITU656 digital video input
(480i), HDMI Analog input (480i, 480p, 720p, 1080i)
[0078] The single integrated HDTV chip for analog and
Annex A/B/C compatible decoder. The HDTV chip for
digital reception 702 may be adapted to receive MPEG data
via a plurality of external transport stream inputs, namely
xport1, xport2, for example. In one embodiment of the
single integrated analog and digital reception 102 may also
invention, the xport1 input may be adapted to be primarily
comprise a CEA/EIA-909 smart antenna interface 128, a
dedicated to the POD module. The xport2 input may be
and pass soft decisions to an ATSC A/53 and ITU-T 1.83
high speed IEEE 1394 FireWire interface 130, and an
adapted to receive MPEG or MPEGx transport data from an
EBI/PCI bus support 132 for USB, SmartCard, Ethernet,
and/or 802.11 capabilities.
external source, as long as the SD/HD MPEG resources are
[0074]
The OOB receiver 257 may be adapted to directly
not used by the other inputs.
sample and digitiZe a surface acoustical Wave (SAW) cen
[0079] The dual tuner 706 may be adapted to provide
cable and/or terrestrial IF video signals to the single inte
tered IF OOB signal, for example. The OOB receiver 257
may also demodulate the signal With recovered clock and
carrier timing, ?lter and equaliZe the data, and incorporate a
A/V sWitch board 704, and/or to the optional PIP block 708.
Analog and digital signals may be communicated to the
grated HDTV chip for analog and digital reception 702, the
DigiCipher II/Digital Audio Video Council (DAVIC)-com
single integrated HDTV chip for analog and digital recep
patible forWard error correction (FEC) decoder. A common
hardWare interface may be utiliZed to provide a direct
tion 702 utiliZing the IF strip IF1. The dual tuner 706 may
utiliZe a single IF strip 706a to communicate analog and/or
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