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CY7C1339G
4-Mbit (128K x 32) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1339G operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A 0, A 1, A
M ODE
A DV
CLK
A DSC
A DSP
BW
D
BW
C
BW
B
DQ
D
BY TE
W RITE REGISTER
DQ
C
BY TE
W RITE REGISTER
DQ
B
BY TE
W RITE REGISTER
DQ
A
BY TE
W RITE REGISTER
ENA BLE
REGISTER
A DDRESS
REGISTER
2 A
[1:0]
BURST
COUNTER
CLR
A ND
Q0
LOGIC
Q1
PIPELINED
ENA BLE
DQ
D
BY TE
W RITE DRIVER
DQ
C
BY TE
W RITE DRIVER
DQ
B
BY TE
W RITE DRIVER
DQ
A
BY TE
W RITE DRIVER
M EM ORY
A RRA Y
SENSE
A M PS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
A
BW E
GW
CE
1
CE
2
CE
3
OE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
D Q s
Cypress Semiconductor Corporation
Document #: 38-05520 Rev. *F
• 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Revised July 5, 2006
[+] Feedback
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configurations
CY7C1339G
250 MHz
2.6
325
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
4.0
225
40
Unit ns mA mA
100-Pin TQFP Pinout
BYTE C
BYTE D
NC
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
NC
25
26
27
28
29
30
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
CY7C1339G
56
55
54
53
52
51
60
59
58
57
64
63
62
61
68
67
66
65
72
71
70
69
76
75
74
73
80
79
78
77
NC
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
NC
BYTE B
BYTE A
Document #: 38-05520 Rev. *F Page 2 of 18
[+] Feedback
Pin Configurations
(continued)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
V
DDQ
NC/288M
NC/144M
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
NC
A
NC/72M
NC
3
A
A
A
V
SS
V
SS
V
SS
BW c
V
SS
NC
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
A
NC
119-Ball BGA Pinout
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
NC
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
NC
5
A
A
A
6
A
NC/9M
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
NC/36M
NC
7
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
CY7C1339G
Pin Definitions
Name
A
0
, A
1
, A
BW
A
, BW
B
BW
C
, BW
D
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Description
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1 are fed to the two-bit counter..
, CE
2
, and CE
3 are sampled active. A1, A0
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE when a new external address is loaded.
1
is sampled only
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.CE
2 is sampled only when a new external address is loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
1 and CE
2
to select/deselect the device. CE
3
is sampled only when a new external address is loaded. Not connected for BGA. Where referenced, CE
3 document for BGA.
is assumed active throughout this
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Document #: 38-05520 Rev. *F Page 3 of 18
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CY7C1339G
Pin Definitions
(continued)
Name
ADV
ADSP
ADSC
ZZ
DQs
V
DD
V
SS
V
DDQ
V
SSQ
MODE
NC,NC/9M,
NC/18M.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
I/O-
Synchronous
Description
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs are placed in a tri-state condition.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O Power
Supply
Power supply for the I/O circuitry.
I/O Ground Ground for the I/O circuitry.
Input-
Static
–
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DD
or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
CO
(250-MHz device).
) is 2.6 ns
The CY7C1339G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486
™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[A:D]
) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE
1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE
1
is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address
Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE
Document #: 38-05520 Rev. *F Page 4 of 18
[+] Feedback
CY7C1339G signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately.
to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
1
, CE
2
, CE
3
are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW
[A:D]
ADV inputs are ignored during this first cycle.
) and
ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BW
[A:D] signals. The CY7C1339G provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte
Write (BW
[A:D]
) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE, and BW
[A:D]
) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ t
ZZS t
ZZREC t
ZZI t
RZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
Burst Sequences
The CY7C1339G provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must remain inactive for the duration of t
ZZREC returns LOW.
after the ZZ input
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1, A0
00
01
10
11
First
Address
A1, A0
00
01
10
11
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Second
Address
A1, A0
01
00
11
10
Second
Address
A1, A0
01
10
11
00
0
Third
Address
A1, A0
10
11
00
01
Third
Address
A1, A0
10
11
00
01
Min.
2t
CYC
Max.
40
2t
CYC
2t
CYC
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
Fourth
Address
A1, A0
11
00
01
10
Unit mA ns ns ns ns
Document #: 38-05520 Rev. *F Page 5 of 18
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CY7C1339G
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Add. Used CE
1
None H
None L
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
None
None
None
None
External
External
External
External
L
L
L
L
L
X
L
L
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
External
Next
Next
Next
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
Next
Next
WRITE Cycle, Continue Burst Next
READ Cycle, Suspend Burst Current
READ Cycle, Suspend Burst Current
READ Cycle, Suspend Burst Current
READ Cycle, Suspend Burst Current
WRITE Cycle, Suspend Burst Current
WRITE Cycle, Suspend Burst Current
H
X
H
X
X
H
L
X
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
H
H
H
X
X
X
L
CE
2
X
L
CE
X
X
3
H L
X L
H L
X H
ZZ ADSP ADSC ADV WRITE OE CLK
L X L X X X L-H
DQ
Tri-State
L L X X X X L-H Tri-State
L
H
H
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H
L-H
L-H
X
Tri-State
Tri-State
Tri-State
Tri-State
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
L
L
L
H
H
H
X
X
X
X
X
L
L
L
X
X
L
H
H
H
H
H
L L-H
X L-H
L L-H
Q
H L-H Tri-State
D
Q
H L-H Tri-State
L L-H Q
H L-H Tri-State
L L-H Q
L
L
L
L
L
L
L
L
L
X
H
H
X
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
L
H
H
L
L
H
H
L
H L-H Tri-State
X L-H D
X L-H
L L-H
D
Q
H L-H Tri-State
L L-H Q
H L-H Tri-State
X L-H D
X L-H D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
A
(BW
A
, BW
B
, BW
C
, BW
D
), BWE, GW = H.
, BW
B
, BW
C
, BW
D
) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
1
, CE
2
, and CE
3
are available only in the TQFP package. BGA package has only 2 chip selects CE
1
and CE
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
[A: D]
.
. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05520 Rev. *F Page 6 of 18
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CY7C1339G
Partial Truth Table for Read/Write
[2, 8]
Function
Read
Read
Write Byte A – DQ
A
Write Byte B – DQ
B
Write Bytes B, A
Write Byte C– DQ
C
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D– DQ
D
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
GW
H
H
L
L
L
L
L
L
L
L
L
X
L
L
BWE
H
L
L
L
L
L
BW
D
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BW
C
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BW
B
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
L
H
L
H
L
H
L
H
L
X
L
H
BW
A
X
H
L
H
L
H
Note:
8.Table only lists a partial listing of the byte write combinations. Any combination of BW
X is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05520 Rev. *F Page 7 of 18
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
DD
Relative to GND........ –0.5V to +4.6V
Supply Voltage on V
DDQ
Relative to GND ...... –0.5V to +V
DD
DC Voltage Applied to Outputs in tri-state ............................................ –0.5V to V
DDQ
+ 0.5V
CY7C1339G
DC Input Voltage ................................... –0.5V to V
DD
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
Automotive –40°C to +125°C
V
DD
3.3V
–5%/+10%
V
DDQ
2.5V –5% to V
DD
Electrical Characteristics
Over the Operating Range
[9, 10]
I
I
I
I
Parameter
V
DD
V
DDQ
V
OH
V
V
V
X
OL
IH
IL
OZ
DD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Output HIGH Voltage for 3.3V I/O, I
OH
= –4.0 mA for 2.5V I/O, I
OH
= –1.0 mA
Output LOW Voltage for 3.3V I/O, I
OL
= 8.0 mA for 2.5V I/O, I
OL
= 1.0 mA
Input HIGH Voltage
[9] for 3.3V I/O for 2.5V I/O
Input LOW Voltage
[9]
Input Leakage Current except ZZ and MODE for 3.3V I/O for 2.5V I/O
GND
≤ V
I
≤ V
DDQ
Input Current of MODE Input = V
SS
Input Current of ZZ
Input = V
DD
Input = V
SS
Input = V
DD
Output Leakage Current GND
≤ V
I
≤ V
DDQ,
Output Disabled
V
DD
Operating Supply
Current
V
DD
= Max., I
OUT
= 0 mA, f = f
MAX
= 1/t
CYC
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
SB1
Automatic CE
Power-down
Current—TTL Inputs
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
V
DD
V
IN
= Max, Device Deselected,
≥ V f = f
MAX
IH
or V
IN
≤ V
= 1/t
CYC
IL
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
Industrial/
Commercial
7.5-ns cycle, 133 MHz
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
V
IN f = 0
= Max, Device Deselected,
≤ 0.3V or V
IN
> V
Automotive 7.5-ns cycle, 133 MHz
All speeds
DDQ
– 0.3V,
Notes:
9. Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
10. TPower-up: Assumes a linear ramp from 0V to V
DD
IL
(AC) > –2V (Pulse width less than t
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
CYC
/2).
DD
.
2.0
1.7
–0.3
–0.3
–5
Min.
3.135
2.375
2.4
2.0
–30
–5
–5
240
225
120
110
30
5
325
265
100
90
Max.
Unit
3.6
V
DD
V
V
V
V
0.4
0.4
V
V
V
DD
+ 0.3V
V
V
DD
+ 0.3V
V
0.8
V
0.7
5
V
µA
5 mA mA mA mA
µA
µA
µA
µA
µA mA mA mA mA
115
40 mA mA
Document #: 38-05520 Rev. *F Page 8 of 18
[+] Feedback
CY7C1339G
Electrical Characteristics
Over the Operating Range
[9, 10]
(continued)
I
I
Parameter
SB3
Description
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
V
IN
Test Conditions
= Max, Device Deselected, or
≤ 0.3V or V f = f
MAX
IN
> V
= 1/t
CYC
DDQ
– 0.3V
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
SB4
Automatic CE
Power-down
Current—TTL Inputs
V
DD
V
IN
= Max, Device Deselected,
≥ V
IH
or V
IN
≤ V
IL
, f = 0
7.5-ns cycle, 133 MHz
All Speeds
Capacitance
[11]
Parameter Description
C
IN
C
CLK
C
I/O
Clock Input Capacitance
Input/Output Capacitance
Thermal Resistance
[11]
Test Conditions
T
A
= 25
°C, f = 1 MHz,
V
DD
= 3.3V.
V
DDQ
= 3.3V
TQFP
Package
5
5
5
Min.
BGA
Package
5
5
7
Max.
Unit
105 mA
95
85
75
45 mA mA mA mA
Unit pF pF pF
Θ
Θ
Parameter
JA
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and procedures for measuring thermal impedance, per
EIA/JESD51
TQFP
Package
30.32
6.85
BGA
Package
34.1
14.0
Unit
°C/W
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
0
= 50
Ω
V
T
3.3V
R
L
= 50
Ω
OUTPUT
= 1.5V
5 pF
INCLUDING
JIG AND
SCOPE
(a)
R = 317
Ω
R = 351
Ω
V
DDQ
10%
GND
≤ 1 ns
ALL INPUT PULSES
90%
90%
10%
≤ 1 ns
(c)
(b)
R = 1667
Ω
= 50
Ω
= 50
Ω
R = 1538
Ω
Note:
11. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05520 Rev. *F Page 9 of 18
[+] Feedback
CY7C1339G
Switching Characteristics
Over the Operating Range
[12, 13, 14, 15, 16, 17]
Parameter t
POWER
Clock t
AH t
ADH t
ADVH t
WEH t
DH t
CEH t
AS t
ADS t
ADVS t
WES t
DS t
CES
Hold Times t
CYC t
CH t
CL
Output Times t
CO t
DOH t
CLZ t
CHZ t
OEV t
OELZ t
OEHZ
Set-up Times
Description
V
DD
(Typical) to the first Access
[12]
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[13, 14, 15]
Clock to High-Z
[13, 14, 15]
OE LOW to Output Valid
OE LOW to Output Low-Z
[13, 14, 15]
OE HIGH to Output High-Z
[13, 14, 15]
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
X
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
–250 –200
Min.
Max.
Min.
Max.
–166
Min.
Max.
–133
Min.
Max.
Unit
1 1 1 1 ms
4.0
1.7
1.7
1.0
0
0
0.3
0.3
0.3
0.3
0.3
0.3
1.2
1.2
1.2
1.2
1.2
1.2
2.6
2.6
2.6
2.6
5.0
2.0
2.0
1.0
0
0
0.5
0.5
0.5
0.5
0.5
0.5
1.2
1.2
1.2
1.2
1.2
1.2
2.8
2.8
2.8
2.8
6.0
2.5
2.5
1.5
0
0
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
1.5
3.5
3.5
3.5
3.5
7.5
3.0
3.0
1.5
0
0
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
1.5
4.0
ns ns ns
4.0
ns
4.0
ns ns
4.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes:
12. This part has a voltage regulator internally; t
POWER can be initiated.
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
13. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05520 Rev. *F Page 10 of 18
[+] Feedback
CY7C1339G
Switching Waveforms
Read Cycle Timing
[18] tCYC
CLK t
CH t
CL t
ADS t
ADH
ADSP tADS tADH
ADSC tAS tAH
A1 ADDRESS tWES tWEH
A2 A3
Burst continued with new base address
GW, BWE,
BW[A:D] tCES tCEH
Deselect cycle
CE tADVS tADVH
ADV
OE
Data Out (Q) High-Z tCLZ tCO
Single READ tOEHZ
Q(A1) tOEV tOELZ
Q(A2) tCO tDOH
Q(A2 + 1)
ADV suspends burst.
Q(A2 + 2) Q(A2 + 3) tCHZ
Q(A2) Q(A2 + 1)
Burst wraps around to its initial state
BURST READ
DON’T CARE UNDEFINED
Note:
18. On this diagram, when CE is LOW, CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH, CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
Document #: 38-05520 Rev. *F Page 11 of 18
[+] Feedback
CY7C1339G
Switching Waveforms
(continued)
Write Cycle Timing
[18, 19] tCYC
CLK tCH tADS tADH tCL
ADSP tADS tADH
ADSC
ADDRESS tAS tAH
A1
Byte write signals are ignored for first cycle when
ADSP initiates burst
A2
BWE,
BW[A :D]
ADSC extends burst tADS tADH
A3 tWES tWEH tWES tWEH
GW tCES tCEH
CE t
ADVS t
ADVH
ADV
ADV suspends burst
OE
Data In (D)
Data Out (Q)
High-Z tDS tDH t
OEHZ
D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2)
BURST READ Single WRITE BURST WRITE
DON’T CARE UNDEFINED
Note:
19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
[A:D]
LOW.
D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)
Extended BURST WRITE
Document #: 38-05520 Rev. *F Page 12 of 18
[+] Feedback
CY7C1339G
Switching Waveforms
(continued)
Read/Write Cycle Timing
[18, 20, 21] tCYC
CLK tCH tCL tADS tADH
ADSP
ADSC
ADDRESS A1
BWE,
BW[A:D] tAS tAH
A2 tCES tCEH
CE
A3 tWES tWEH
A4
ADV
A5 A6
OE
Data In (D)
Data Out (Q) tCO
High-Z
High-Z tCLZ tOEHZ
Q(A1)
Back-to-Back READs
Q(A2) tDS tDH
D(A3)
Single WRITE tOELZ
Q(A4) Q(A4+1)
BURST READ
Q(A4+2) Q(A4+3)
DON’T CARE UNDEFINED
Notes:
20. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
21. GW is HIGH.
D(A5) D(A6)
Back-to-Back
WRITEs
Document #: 38-05520 Rev. *F Page 13 of 18
[+] Feedback
CY7C1339G
Switching Waveforms
(continued)
ZZ Mode Timing
[22, 23]
CLK t
ZZ
ZZ t
ZZI
I
SUPPLY
ALL INPUTS
(except ZZ)
I
DDZZ
Outputs (Q) t
ZZREC t
RZZI
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05520 Rev. *F Page 14 of 18
[+] Feedback
CY7C1339G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
CY7C1339G-133AXC
Package
Diagram Package Type
Operating
Range
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1339G-133BGC
CY7C1339G-133BGXC
CY7C1339G-133AXI
CY7C1339G-133BGI
51-85115
51-85050
51-85115
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
166
CY7C1339G-133BGXI
CY7C1339G-133AXE
CY7C1339G-166AXC
CY7C1339G-166BGC
CY7C1339G-166BGXC
CY7C1339G-166AXI
CY7C1339G-166BGI
CY7C1339G-166BGXI
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Automotive
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Industrial
200
250
CY7C1339G-200AXC
CY7C1339G-200BGC
CY7C1339G-200BGXC
CY7C1339G-200AXI
CY7C1339G-200BGI
CY7C1339G-200BGXI
CY7C1339G-250AXC
CY7C1339G-250BGC
CY7C1339G-250BGXC
CY7C1339G-250AXI
CY7C1339G-250BGI
CY7C1339G-250BGXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Industrial
Document #: 38-05520 Rev. *F Page 15 of 18
[+] Feedback
CY7C1339G
Package Diagrams
1
100
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
81
80
0.30±0.08
1.40±0.05
R 0.08 MIN.
0.20 MAX.
GAUGE PLANE
0.25
0°-7°
0.60±0.15
1.00 REF.
30
31
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
DETAIL
A
50
51
0.65
TYP.
12°±1°
(8X)
SEE DETAIL
A
0.20 MAX.
1.60 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
51-85050-*B
Document #: 38-05520 Rev. *F Page 16 of 18
[+] Feedback
CY7C1339G
Package Diagrams
(continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
A1 CORNER
1 2 3 4 5 6 7
G
H
J
M
N
K
L
A
B
C
D
E
F
T
U
P
R
0.70 REF.
12.00
30° TYP.
Ø1.00(3X) REF.
A
B
0.15(4X)
Ø0.05 M C
Ø0.25 M C A B
Ø0.75±0.15(119X)
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
T
U
P
R
1.27
3.81
7.62
14.00±0.20
51-85115-*B
C
SEATING PLANE
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05520 Rev. *F Page 17 of 18
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1339G
Document History Page
Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM
Document Number: 38-05520
REV.
**
ECN NO. Issue Date
224368 See ECN
Orig. of
Change Description of Change
*A 288909 See ECN
RKF New data sheet
VBL In Ordering Info section, Changed TQFP to PB-free TQFP
Added PB-free BG package
*B 332895 See ECN
*C
*D
351194
366728
See ECN
See ECN
SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Package as per JEDEC standards and updated the Pin Definitions accordingly
Modified V
OL,
Replaced TBDs for
Θ tance table
V
OH test conditions
JA
and
Θ
JC
to their respective values on the Thermal Resis-
Updated the Ordering Information by shading and unshading MPNs as per availability
PCI Updated Ordering Information Table
*E 420883 See ECN
PCI Added V
DD
/V
DDQ
test conditions in DC Table
Modified test condition in note# 10 from V
IH
< V
DD to V
IH
< V
DD
RXU Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Information table
Replaced Package Diagram of 51-85050 from *A to *B
Added Automotive Range in Operating Range Table
Updated the Ordering Information
*F 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on V
DDQ
Updated the Ordering Information table.
Relative to GND.
Document #: 38-05520 Rev. *F Page 18 of 18
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