A Training on High-Speed I/O Interfaces: USB3

A Training on High-Speed I/O Interfaces: USB3
High Speed I/O Interfaces:
USB 3.0
FTF-NET-F0156
Jimmy Zhao | PE, System and Applications Engineering
APR.2014
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Session Introduction
•
Introduction of USB 3.0
− Understand
USB 3.0 architecture
− The differences between USB 3.0 and USB 2.0
•
USB 3.0 on LS1
•
Time allocation
− 45
min presentation
− 5 min Q&A
•
Author
− Jimmy
Zhao, PE, System and Application Engineer, Digital Networking
− SME for USB, SPI, SDHC
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Session Objectives
•
After completing this session you will be able to:
− Know
the differences between USB 3.0 and USB 2.0
− Understand USB 3.0
 USB
3.0 Feature
 Layered
Protocol Architecture
•
Details on Protocol layer
•
Details on Link layer
•
Details on Physical layer
− USB
 Data
3.0 on LS1
structure and Memory map
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Agenda
•
USB 3.0 Introduction
− Features
− Architecture
− Cable/Connectors
− Layered
 Protocol
 Link
Layer
Layer
 Physical
•
Protocol Architecture
Layer
LS1 USB Information
− Introduction
− Data
structure and Register memory map
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USB 3.0 Introduction / Features
•
10x performance increase over USB 2.0
−5
•
Gbps vs. 480 Mbps
Backward compatible
−
Legacy devices continue to work when plugged into new host connector
− New devices work when plugged into legacy systems albeit at USB 2.0 speeds
− Existing class drivers continue to work
•
Same USB Device Modes
− Pipe Model
−
USB Framework
− Transfer Types
•
Power Efficient
−
Provides excellent power characteristics (especially for idle links)

−
•
Both on the device and platform
Eliminate need for polling
Extensible
− Protocol designed to efficiently scale up
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Agenda
•
USB 3.0 Introduction
− Features
− Architecture
− Cable/Connectors
− Layered
 Protocol
 Link
Layer
Layer
 Physical
•
Protocol Architecture
Layer
LS1 USB Information
− Introduction
− Data
structure and Register memory map
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USB 3.0 Architecture
•
Dual-bus Architecture SuperSpeed bus operates concurrently
with USB2.0
−
−
−
•
Electrically/mechanically backward and forward compatible
Devices discovered / configured at fastest signaling rate
Hubs provide additional connection points
SuperSpeed USB
−
−
−
−
Dual simplex signaling
Packets routed to device
Hubs store and forward
Asynchronous notifications
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USB 3.0 Architecture (continued)
•
Dual-bus architecture for
backward compatibility
• USB 3.0 Host
− Supports
•
USB 3.0 Hub
− Supports
•
SS and USB 2.0
SS and USB 2.0
USB 3.0 Device
− Supports
SS and HS (FS/LS
optional)
− Concurrent SS and USB 2.0
traffic is not allowed
•
FSL USB 2.0 Host: works for
couple USB 3.0 HDDs
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Agenda
•
USB 3.0 Introduction
− Features
− Architecture
− Cable/Connectors
− Layered
 Protocol
 Link
Layer
Layer
 Physical
•
Protocol Architecture
Layer
LS1 USB Information
− Introduction
− Data
structure and Register memory map
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USB 3.0 Connectors
•
Standard-A Connector
•
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Standard-B Connector
•
Micro-AB/A
USB 3.0 Cable
•
Embeds physical USB2 bus in parallel with the USB3
SuperSpeed bus
• USB 2.0 and 3.0 packets operate independently
Note:
STP: Shield Twisted Pair
UTP: Unshield Twisted Pair
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Agenda
•
USB 3.0 Introduction
− Features
− Architecture
− Cable/Connectors
− Layered
 Protocol
 Link
Layer
Layer
 Physical
•
Protocol Architecture
Layer
LS1 USB Information
− Introduction
− Data
structure and Register memory map
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USB 3.0 Layered Protocol Architecture
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USB 3.0 Protocol Layer
•
Convert the requests from the functional layer into transactions
consisting of packets
• Manage the end-to-end data flow between the host and the device
• Reliability for packets
− Sending
Acknowledgement packets
− Request/retransmit lost/corrupted data
− Packet payload (not in Link)
•
Power management
− Enter
reduced power states after a NRDY response
− Unicast vs. broadcast packets
•
Bandwidth management
− Stream
support for performance
− Asynchronous notification ERDY be device vs. host polling
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USB 3.0 Protocol Layer – Packets
•
Start from transmitter protocol layer terminated at the receiver
protocol layer
• Application data embedded in the data packet Payload
• Host initiates all data transfers.
• Header and Data packet Payload
− Address
triple: device address, endpoint number, direction
− Route string: the path between the host and the device
•
Device response
− Response
immediately: device => host
− Deferred response: restarted synchronously by the device
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USB 3.0 Protocol Layer – Packets Format
•
16-byte Header
− 12
•
bytes header information
Four packet types:
−
Link Management Packet (LMP)
− Transaction Packet (TP)
− Data Packet (DP)
− Isochronous Timestamp Packet
(ITP)
•
Only DP has a Data Packet
Payload (DPP) besides Packet
Header
• LMP and ITP not routable
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USB 3.0 Protocol Layer – Packet Types
•
Link Management Packet (LMP)
− Sent
directly to connected ports
between link partners
− No addressing information
 Not
routable
− Used
to manage the link
− Subtypes
 Set
Link Function
 U2 Inactive Timeout
 Vendor Device Test
 Port Capability
 Port Configuration
 Port Configuration Response
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USB 3.0 Protocol Layer – Packet Types
•
Isochronous Timestamp Packet (ITP)
− Only
sent out when root port link is in U0
around bus interval boundary
− Replace SOF/uSOF in USB 2.0
− Multicast to all active links, no routing
information
− Delayed bit is set when ITP is delayed
by Hub
− Send host SS 125 uSec bus
interval/service interval timing to any
device
− Devices:
 Not
respond
 Lock an internal time base to the host timing
 Ignore it if delayed flag set
 Needs to be in U0 if expecting ITP
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USB 3.0 Protocol Layer – Packet Types
•
Transaction Packet (TP)
− Control
the data flow, configure
devices and hubs
− Subtypes
 ACK
 NRDY
 ERDY
 STATUS
 STALL
 DEV_NOTOFICATION
 PING
 PING_RESPONSE
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USB 3.0 Protocol Layer – Types of Transaction Packets
•
IN
ACK(0001b)
− IN:
Received without error
− OUT: Rx buffers available
•
DATA
ACK
NRDY(0010b)
No data packets available
− OUT: Rx buffers unavailable
− Non-ISO device EP
ERDY(0011b)
Host
IN
ACK
NRDY
OUT
DATA
NRDY
Device
NRDY
− IN:
•
OUT
ACK
ACK
DATA
ACK
IN
− IN:
…
ERDY
OUT
DATA
NRDY
…
ERDY
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ERDY
Data packets available now
− OUT: Rx buffers available now
− Non-ISO device EP
ACK
NRDY
USB 3.0 Protocol Layer – Types of Transaction Packets
(continued)
•
STALL (0101b)
•
IN
halted / Control transfer invalid
ACK
STALL
DEV_NOTIFICATION (0110b)
− Asynchronous
OUT
change in a device /
DATA
STALL
interface state
 Function
Wake
 Latency Tolerance
 Bus Interval Adjustment
•
DEV_NOTIFICATION
change of a control transfer
STATUS
PING (0111b)
− Ensure
device is in U0 before
sending the ISO packets
•
Device
STATUS (0100b)
− Status
•
Host
PING RESPONSE (1000b)
− Confirm
device still reminds in U0
until the ISO packets are received
− Send for every PING
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STALL
− EP
PING
PING RESPONSE
USB 3.0 Protocol Layer – Flow Control
•
•
•
It is in flow control when a device EP is
not ready to send/receive data
Not apply to Isochronous Eps
Flow control mechanisms:
− Sends
•
ACK(1,4)
a DP with the EOB = 1
ACK(2,4)
…
DATA(0, -)
DATA(1, -)
NRDY
…
ERDY
DATA(2, -)
ACK(3,4)
an ACK with NumP = 0
Terminating flow control
− Device
Host Rx
ACK(0,4)
ACK(2,4)
− OUT
 Sends
Host Tx
NRDY/ERDY
− IN
 Sends
IN Transaction
ACK(3,4)
…
DATA(3, -)
…
OUT Transaction
Host Tx
Host Rx
sends an ERDY
DATA(0,-)
ACK(0,4)
…
DATA(0,-)
(Seq#, NumP)
NumP:
IN: number of packets requested
OUT: Buffer space availability
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DATA(1,-)
DATA(2,-)
…
NRDY
…
ERDY(-,4)
ACK(1,4)
ACK(2, 4)
…
USB 3.0 Protocol Layer – Transactions
•
Bulk Transactions
• Control Transactions
− Same
3
or 2 stages: Setup, Data (optional), Status
− Max
•
as USB 2.0
packet size: 512 bytes
Interrupt Transactions
− Max
packet size: 1024 bytes
− For infrequent data transfer with guaranteed bounded latency
− Up to burst of 3 packets / interval
•
Isochronous Transactions (No Retry)
− Max
packet size: 1024 bytes
− Up to 48 packets / interval (375 MB/s)
− Interval: 125 µs * 2**(Binterval-1) => (125 µs, … 4 s)
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USB 3.0 Protocol Layer – Bulk Transaction
•
Up to 16 bursts
• Support streams
• Max packet size: 1024 bytes
• Guarantee error-free delivery of data
− Error
detection
IN Basic Retry Sequence
Host Tx
Host Rx
ACK(0,1)
DATA(0, -)
ACK(0,1)
Retry Set
Error
DATA(1, -)
ACK(1,0)
− Retry
•
Flow control
• Basic Retry
OUT Basic Retry Sequence
− Set
Seq# = Seq# of the bad/missing
data packet
Host Tx
DATA(0,-)
Error
Host Rx
ACK(0,1)
Retry Set
DATA(0,-)
ACK(1,1)
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USB 3.0 Protocol Layer – Bulk Transaction (Burst)
•
Host knows max. burst
size for EP during
enumeration
• Max. number of packets
sent without getting an
ACK is limited:
− Min
of {(Max. burst size),
NumP}
•
NumP can be incremented
anytime by the host or a
device
• Burst terminate
IN Burst Retry Sequence
Host Tx
Host Rx
ACK(0,4)
=0
− A short packet
ACK(1,4)
ACK(2,4)
ACK(2,4)
Retry Set
24
DATA(1,-)
DATA(2,-)
Error
DATA(3, -)
Discard
DATA(2,-)
Error
DATA(3,-)
DATA(2,-)
DATA(2,-)
DATA(3, -)
ACK(3,4)
Discard
ACK(1,4)
ACK(2,4)
ACK(2,4)
Retry Set
DATA(3,-)
ACK(3,4)
DATA(4,-)
…
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Host Rx
DATA(0,-)
DATA(1, -)
ACK(5,4)
TM
Host Tx
DATA(0, -)
DATA(4,-)
ACK(4,4)
− NumP
OUT Burst Retry Sequence
…
…
DATA(4,4)
DATA(4,4)
…
USB 3.0 Protocol Layer – Bulk Transaction (SS Streaming)
•
Multiplexing multiple independent logic data streams
• Up to 65533 streams
• Managed by the Stream Protocol
− Host
or a device setup CStream ID (Current Stream) associated with
an EP
− CStream ID
 Host:
To select the command/operation specific EP buffers for data transfer
 Device: To select the Function Data buffers
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USB 3.0 Link Layer
•
Manage the port-port flow of data between the host and the device
• Manage/control the logic portion of the link: reliability, flow control,
data integrity, link power management
• Link Training
− Link
Training and Status State Machine (LTSSM)
− Bit-Lock, Symbol-Lock, and Rx Equalization
•
Power Management
−4
Link Power States: U0, U1, U2, U3
− Low Frequency Periodic Signaling (LFPS)
•
Error Handling
− Bit,
Link, Packet errors
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USB 3.0 Link Layer – Power Management
Link
Description
State
U0
U1
U2
U3
•
Operational State
RX & TX Circuit Quiesced
- PLL remains on / Clock gating / P1
N/A
NA
Hardware
μs
Link idle
- Slow Exit
Clock Generation Circuit Quiesced
- PLL can be turned off / Clock gating / P2
Hardware
μs to ms
Link Suspend
Portions of device power removed
-Clock generation circuit can be turned off
/ Clock gating / P3
Entry: Software
Exit: Hardware
or Software
Downstream port inactivity time

−
Port_U1_TimeOut ( Can be as low as 10us )
Device hardware initiated

Exit
Latency
Link Active
Link Idle
- Fast Exit
U0 to U1 entry based on
−
•
Key Characteristics
State
Transition
Initiator
Based on implementation specific knowledge
In both cases - Always initiated with Link command
LGO_U1 -> LAU
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ms
USB 3.0 Link Layer – Link States
•
Connection
− Idle:
•
Rx.Detect
Link Training
− Polling
•
states
Normal State: U0
− Descriptors
•
Low Power States
− U1
− U2
− U3
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USB 3.0 Link Layer – Link Training
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USB 3.0 Link Layer – Header Packet Framing
•
Header Packet Framing (20 Bytes)
−4
bytes of Packet start framing
 SHP,
− 12
SHP, SHP, EPF
bytes Packet Header
 LMPs,
End Packet Framing
TPs, ITPs, DPHs
−2
byte CRC
− 2 bytes Link Control Word
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Start Header Packet
30
USB 3.0 Link Layer – Link Command
•
For data integrity, flow control, link
power management
• Only from Transmitter link layer to
Receiver link layer
Start Link Command
End Packet Framing
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USB 3.0 Link Layer – Link Command
•
LGOOD_n
− Everyting
•
Good
LBAD
− Invalid
header packet
− Bad/corrupted CRC
− Resend all header packets after the last one with LGOOD_n
•
LRTY
− Send
•
before resending the 1st header packet after LBAD
LCRD_x (x: A, B, C, D) Header Buffer Credit index
− Indicate
a single Rx Header Buffer Credit is available
− Sent after received packet meet:
 LGOOD_n
is sent
 Header packet has been processed, a Rx Header Buffer Credit is available
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USB 3.0 Link Layer – Link Command
•
LGO_U1/U2/U3
− Requesting
enter to U1/U2/U3
− Upstream port must accept U3
•
LAU
−A
•
LXU
−A
•
port rejecting the request to enter U1/U2
LPMA
−A
•
port accepting the request to enter U1/U2
port receiving LAU
LUP
− Device
is in U0
− Sent by an upstream port every 10 uS when there is no packets or
other link commands to be sent
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USB 3.0 Link Layer – Link Command, Retry
HP, HSEQ#=0
HP, HSEQ#=0
HP,HSEQ#=0
HP,HP,
HSEQ#=0,
HSEQ=0Bad CRC
LBAD
LRTY
1
1
43
B
B
LCRD_A
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4
HP, HSEQ#=0
34
USB 3.0 Physical Layer
•
Actual physical connection
between 2 ports
− Two
differential data pairs
 One
Transmit
 One Receive
•
8b/10b encode/decode
− ANSI
X3.230-1994
•
Scramble/descramble
• Spread Clock CDR (Clock
Data Recovery)
• Elasticity Buffer/Skips
•
Low Frequency Period
Signaling (LFPS)
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USB 3.0 Physical Layer (continued)
Transmitter Functions
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Receiver Functions
USB 3.0 Physical Layer - PIPE
•
•
•
•
PCLK from PHY to MAC:
Rx and Tx Data:
Rx and Tx DataK:
Command Signals:
500/250/125 MHz
8-, 16-, or 32-bits
1-, 2- or 4-bits
12- or 16-bits
− PHYMode,
Rxdetect/loopback, TxElecIdle, RxPolority, TxEqua,
TxComplicance, Rate, TxMargin, TxDeep, RxTerm, TxSwing, etc.
•
Status Signals:
− PHYStatus,
6- or 7-bits
RxValid, RxStatus, RxElecIdle, PowerPresent
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Agenda
•
USB 3.0 Introduction
− Features
− Architecture
− Cable/Connectors
− Layered
 Protocol
 Link
Layer
Layer
 Physical
•
Protocol Architecture
Layer
LS1 USB Information
− Introduction
− Data
structure and Register memory map
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LS1 Architecture
•
One USB 2.0 with ULPI
(UTMI+Low Pin Interface)
• OTG (On The Go) 2.0
• USB Dual-Role Controller
• One USB 3.0 with internal PHY
−
−
−
−
−
•
Super-speed (SS) – 5 Gbps
High-Speed (HS) – 480 Mbps
Full-Speed (FS) – 12 Mbps
Low-Speed (LS) – 2 Mbps (only
for USB 2.0 host mode)
Support 8 programmable,
bidirectional endpoints
Compatible with xHCI spec
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USB 3.0 Controller and PHY
SoC Bus
USB Controller
System
CPU
Master
System
Memory
Slave
Bus
Interface,
Registers,
List
Processor
Application
USB PHY
USB 3.0
MAC &
LINK
SuperSpeed
Function
(PIPE 3)
USB 2.0
MAC
High-Speed
Function
(UTMI)
Buffer Management
Tx Data FIFO
RAM
Rx Data FIFO
RAM
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tx <#> _p
tx <#> _m
rx <#> _p
rx <#> _m
DP <#> , DM <#>
Power supplies,
Clocks, …
Descriptor
Register Cache
RAM
USB 3.0 eXtensible Host Controller Interface (xHCI)
CCSR
(Configuration,
Control, and Status
Register)
USB Base
Address
(310_0000H)
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USB 3.0 Controller Memory Map/Registers
•
USB 3.0 Registers
− 32-bits
wide
− Address: 32-bit block aligned
− Access the register
 Only
32-bit units
 8-bit or 16-bit illegal
•
Global Registers
• Device Registers
• OTG Registers
• xHCI Host Registers
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USB 3.0 Host Memory Map/Registers
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USB 3.0 Host Memory Map/Registers
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Session Summary
•
Discussed the differences between USB 3.0 and USB 2.0
•
Described USB 3.0 Feature
•
Presented Layered Protocol Architecture
− Details
on Protocol layer
− Details on Link layer
− Details on Physical layer
•
Discussed USB 3.0 on LS1
− Data
structure and Memory map
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For Further Information
•
URLs
− http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1
021A&nodeId=018rH325E4017B
− http://www.usb.org/developers/ssusb/
− http://www.synopsys.com/dw/ipdir.php?ds=dwc_usb_3
•
Contact information
− Jimmy
Zhao, PE, System and Applications Engineering, DN
− [email protected]
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QorIQ LS2 Family
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•
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•
•
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•
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TM
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•
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•
•
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TM
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49
TM
www.Freescale.com
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