Si2456/33/14/03URT-EVB
S i 2 4 5 6 / 3 3 / 1 4 / 0 3 U R T- E V B
E V A L U A T I O N B O A R D F O R T H E Si2456/33/14/03 W I T H A
UART I N T E R F A C E
Description
The Si2456/33/14/03URT-EVB evaluation board
provides the system designer an easy way to evaluate
the Si2456/33/14/03 ISOmodem™. The Si2456/33/14/
03URT-EVB consists of a motherboard with a power
supply, an RS-232 interface, other ease-of-use features,
and a complete removable modem module on a
daughter card. (A functional block diagram of the
Si2456/33/14/03URT-EVB is shown below.) The
Si2456/33/14/03 ISOmodem is a complete controllerbased modem chipset with an integrated and
programmable direct access arrangement (DAA) that
meets global telephone line requirements. Available as
a combination of one 16-pin small outline (SOIC)
package and one 24-pin thin shrunk small outline
(TSSOP) package, the Si2456/33/14/03 ISOmodem
eliminates the need for a separate DSP data pump,
modem controller, memories, analog front end (AFE),
isolation transformer, relays, opto-isolators, and a 2- to
4-wire hybrid. The Si2456/33/14/03 is ideal for
embedded modem applications due to its small board
area, controller-based architecture, low power
consumption, and global compliance. The Si2456/33/
14/03URT-EVB provides an RJ-11 jack and a DB9
connector for interfacing the Si2456/33/14/03URT-EVB
to the phone line and a PC or data terminal serial port.
This allows the ISOmodem to operate as a serial
modem for straightforward evaluation of the Si2456/33/
14/03. To evaluate the Si2456/33/14/03 ISOmodem in
an embedded system, the daughter card can be used
independently or with the motherboard. A direct access
header (JP3) is available on the motherboard to bypass
the RS-232 transceivers and connect the Si2456/33/14/
03 ISOmodem directly to a target system. In addition, a
10-pin connector (JP4) is available for evaluation of the
PCM voice features. This connector is compatible with
other Silicon Laboratories evaluation boards.
Power is supplied through a screw terminal (J3) or a
standard 2 mm power jack (J4). An on-board rectifier,
filter, and voltage regulator allows the power input to be
7.5 V–13 V ac or dc (either polarity). The Si2456/33/14/
03URT-EVB can drive an external speaker for call
monitoring or a piezoelectric speaker can be mounted
directly on the board in the space provided.
Features
The Si2456/33/14/03URT-EVB includes the following:
Dual RJ-11 connection to phone line
Serial interface to PC
Audio connector for call monitoring
Direct access to Si2456/33/14/03 for embedded
application evaluation
Easy power connection to common 7.5 V–13.5 V
power supplies
9 V ac adaptor
Support for daisy chain operation
Simple installation and operation
Functional Block Diagram
PCM Data/
Control
9 V dc at 300 mA ac
Adaptor
7.5–13.5 V dc or
peak ac
UART
Rectifier
Filter
PCM
Interboard
Connector
Voltage
Regulator
3.3 V
Audio
Out
Audio
Amplifier
Direct
Access HDR
Daughter Board Boundary
5V
DB9
RS-232
Transceivers
Interface
Selection
Jumpers
AOUT
Si2456/33/14/03
RESET
XTALO
Si3015
Interface
Circuit
RJ-11
phone
line
XTALI
Push Button
Reset
Power-On
Reset
Rev. 0.7 1/02
Copyright © 2002 by Silicon Laboratories
Si2456/33/14/03URT-EVB-07
Si2456/33/14/03URT- EVB
Si2456/33/14/03URT-EVB Setup and
Evaluation
This section explains how to set up the Si2456/33/14/
03URT-EVB for evaluation as a serial interface modem.
Jumper settings, power connection, PC/terminal
connections, and terminal program configuration
settings are given. The initial modem setup after power
is applied along with a basic tutorial on modem
operation is also provided. Si2456/33/14/03URT-EVB
configurations for evaluating additional features are
discussed separately. See the Si2456/33/14/03 data
sheet and Programmer’s Guide for complete details.
Si2456/33/14/03URT-EVB Quick Start
1. Set jumpers according to Figure 1
2. Connect
Jumper Settings
Check all jumper settings on the Si2456/33/14/03URTEVB before applying power. Figure 1 shows the
standard factory jumper settings. These settings
configure the Si2456/33/14/03URT-EVB for RS-232
serial operation. Any standard terminal program
configured to communicate through a PC COM port can
be used to communicate with the Si2456/33/14/03URTEVB. The transceiver jumper (JP8) should be
connected whenever the RS-232 UART interface is
used. For normal operation, JP6 should have jumpers
at positions 1-2, 4-5, 7-8, and 10-11. If access to the
interrupt pin (INT_N) is desired, it can be connected to
ring detect (RD) on the PC by removing the jumper at
JP6 pins 4-5 and placing it at JP6 pins 5-6 instead. This
replaces the RI_N signal with INT_N on RD (pin 9 of
J1).
DB-9 to PC COM 1
RJ-11 to phone line or test box
the 9 V ac adaptor
3. Bring up
Turn on power to modem
Set Terminal Program for 19.2 kbps 8N1
4. Type “AT”
Figure 1. Standard Factory Jumper Settings (outlined in gray)
2
Rev. 0.7
Si2456/33/14/03URT-EVB
Power Requirements
The Si2456/33/14/03URT-EVB has an on-board diode
bridge, filter capacitor, and voltage regulator (U8).
Power can be supplied from any source capable of
providing 7.5 V–13 V dc or 7.5 V–13 V peak ac and at
least 100 mA. (Additional current may be required if a
speaker is connected for monitoring call progress
tones.) Power may be applied to the Si2456/33/14/
03URT-EVB through the screw terminals (J3) or the
2 mm power jack (J4). The on-board full-wave rectifier
and filter ensures the correct polarity is applied to
Si2456/33/14/03URT-EVB. Daughter card power is
supplied through voltage regulator U7 and must always
be set at 3.3 V by connecting JP7 pins 1 and 2.
Daughter card current can be measured by connecting
an ammeter between JP7 pins 1 and 2. These pins
must always be connected. Failure to connect pins 1
and 2 of JP7 through either a jumper or a low
impedance ammeter may result in damage to the
Si2456/33/14/03URT-EVB.
Terminal and Line Connections
The Si2456/33/14/03 can be tested as a standard serial
data modem by connecting the Si2456/33/14/03URTEVB to a personal computer or other data terminal
equipment (DTE), phone line, and power. Connect a
serial port on a PC to the DB9 connector on the Si2456/
33/14/03URT-EVB with a pass-through cable. The RS232 transceivers on the EVB can communicate with the
DTE at rates up to 230.4 kbps. Any standard terminal
program such as HyperTerminal or ProComm running
on a PC will communicate with the Si2456/33/14/
03URT-EVB. Configure the terminal emulation program
to 19200 bps, 8 data bits, no parity, one stop bit, and
hardware (CTS) handshaking. Connect the RJ-11 jack
on the Si2456/33/14/03URT-EVB to an analog phone
line or telephone line simulator such as a Teltone TLS 5.
Making Connections
With the terminal program properly configured and
running, apply power to the Si2456/33/14/03URT-EVB.
Type “AT<cr>” and the modem should return “OK”
indicating the modem is working in the command mode
and communicating with the terminal. If the “OK”
response is not received, try resetting the modem by
pressing the manual reset switch (S1) then again type
“AT<cr>.” Next type “ATI6<cr>.” The modem should
respond with “2433” or “2414” indicating the terminal is
communicating with a Si2456/33/14/03.
Type “ATS0=2<cr>” to configure the modem to answer
on the second ring.
To take the modem off-hook, type “ATH1<cr>.” The
modem should go to the off-hook state, draw loop
current, and respond with an “OK.” Next type “ATH<cr>”
or “ATH0<cr>” and the modem should hang up (go onhook) and stop drawing loop current.
To make a modem connection, type “ATDT(called
modem phone number)<cr>.” Once the connection is
established, a “CONNECT” message will appear
indicating the two modems are in the data mode and
communicating. Typing on one terminal should appear
on the other terminal. To return to the command mode
without interrupting the connection between the two
modems, type “+++.” Approximately two seconds later
“OK” will appear. The modem is now in command mode
and will accept “AT” commands. To return to the data
mode, type “ATO.” The modem will resume the data
connection and no longer accept AT commands. Type
“ATH” (or “ATH0”) to terminate the data connection.
Si2456/33/14/03URT-EVB Functional
Description
The Si2456/33/14/03URT-EVB is a multipurpose
evaluation system. The modem daughter card
illustrates the small size and few components required
to implement an entire controller-based modem with
global compatibility. The daughter card can be used
independently of, or in conjunction with, the
motherboard. The motherboard adds features that
enhance the ease of evaluating the many capabilities of
the Si2456/33/14/03 ISOmodem.
Motherboard
The motherboard provides a convenient interface to the
Si2456/33/14DC daughter card. The versatile power
supply allows for a wide range of ac and dc voltages to
power the board. RS-232 transceivers and a DB9
connector allow the Si2456/33/14/03URT-EVB to be
easily connected to a PC or other terminal device.
Jumper options allow direct access to the LVCMOS/TTL
level serial inputs to the Si2456/33/14/03, bypassing the
RS-232 transceivers. This is particularly useful for
directly connecting the Si2456/33/14/03 to embedded
systems.
Additionally, The Si2456/33/14/03URT-EVB is designed
to support a daisy chain connection to an external voice
codec (Si3000) or an external Silicon Laboratories DAA
(Si3021 +Si3015) or both through the JP4 connector.
This allows a system designer to evaluate the Si2456/
33/14/03 ISOmodem for use in a voice or multiple line
application.
The Si2456/33/14/03URT-EVB motherboard connects
to the daughter card through two connectors, JP1 and
JP2. JP1 is an 8x2 socket providing connection to all
Si2456/33/14/03 digital signals and regulated 3.3 V
Rev. 0.7
3
Si2456/33/14/03URT- EVB
power for the Si2456/33/14/03. The Si2456/33/14/03
digital signals appearing at JP1 (daughter card
interface) are LVCMOS and TTL compatible. Note that
the Si2456/33/14/03 must be powered by 3.3 V. Be sure
that JP7 pins 1 and 2 are connected any time the
daughter card is used in conjunction with the
motherboard. Likewise, be sure the power supplied to
the daughter card, when used independently, is 3.3 V.
Connecting the Si2456/33/14/03 to a 5 V supply will
cause permanent damage to the device. JP2 is a 4x1
socket providing connection between the daughter card,
the RJ-11 phone jack and chassis ground.
Voltage Regulator/Power Supply
The input voltage to either J3 or J4 must be between 7.5
and 13.5 V dc or 7.5 and 13.5 VPEAK ac. The
motherboard includes a diode bridge (D1–D4) to guard
against a polarity reversal of the dc voltage or to rectify
an ac voltage. The power source must be capable of
continuously supplying at least 100 mA. C50 serves as
a filter cap for an ac input. The voltage regulator U8
provides 5 V for the motherboard and the input for
voltage regulator U7 which outputs 3.3 V for use on the
motherboard and to power the daughter card. The
daughter card MUST be powered by 3.3 V (JP7 pins 1
and 2 connected). Failure to set this jumper correctly
can result in permanent damage to the Si2456/33/14/
03URT-EVB. Si2456/33/14/03 power consumption can
be measured by placing a meter between pins 1 and 2
of JP7. The connection between JP7 pins 1 and 2 must
be made at all times when power is applied to the
Si2456/33/14/03URT-EVB either through a jumper
block or a low impedance meter to avoid damage to the
Si2456/33/14/03URT-EVB.
DS1818
The DS1818 is a small low-cost device that monitors the
voltage on VD and an external reset pushbutton. If VD
drops below 3.0 V or if the reset pushbutton is
depressed, the DS1818 provides a 220 ms active-low
reset pulse. On power-up, the DS1818 also outputs an
active low reset pulse for 220 ms after VD reaches 90%
of the nominal 3.3 V value. The DS1818 will output a
220 ms reset pulse any time the power supply voltage
exceeds the 3.3 V ±10% window.
RC Time Constant (Optional)
The RESET_N signal is connected to the junction of
R11 and C49. The other ends of R11 and C49 are
connected to VD and ground, respectively. Just prior to
power-up, C49 is discharged and RESET_N is at
ground. Once power is applied, C49 charges
exponentially toward VD according to the equation:
–t ------------------
V RESET_N
The values of R11 and C49 must be chosen to ensure
that the RESET_N voltage remains below the low-tohigh voltage threshold of 0.8 V for at least 5 ms after the
power supply voltage stabilizes. For the purpose of
illustration it will be assumed that the power supply
voltage is stable after 20 ms. The R11 C49 time
constant must be such that the voltage on C49 is less
than 0.8 V for at least 25 ms (20 ms for power to
stabilize and 5 ms for reset). It will be further assumed
that R11 = 20K. Solving the equation above for C49
yields:
t
C 49 = ----------------------------------------------------------------V RESET_N

–R 11 ⋅ ln  1 – ---------------------------
VD
Reset Circuitry
The Si2456/33/14/03 requires a reset pulse to remain
low for at least 5.0 ms after the power supply has
stabilized during the power-up sequence or for at least
5.0 ms during a power-on reset. Most production
Si2456/33/14/03 modem chipset applications will
require that RESET be controlled by the host processor.
Certain Si2456/33/14/03 operation modes, including
Power Down and \U Test mode, require a hardware
reset to recover.
The Si2456/33/14/03URT-EVB contains three reset
options, an automatic power-on reset device, U6
(DS1818) (default), a manual reset switch (S1) to permit
resetting the chip without removing power, and an
optional RC time constant determined by R11 and C49
(not populated). Any reset, regardless of the
mechanism, will cause all modem settings to revert to
factory default values. See Figure 6 on page 12.
4

R 11 C 49
= VD  1 – e



25 ms
C 49 = ---------------------------------------------------- = 4.5 µF
0.8
( –20K ) ⋅ ln  1 – --------
3.3
Allowing for a ±10% tolerance on the resistor, a ±30%
tolerance on the capacitor the closest standard
capacitor value is 10 µF.
Manual Reset
The manual reset switch (S1) can be used in
conjunction with either the DS1818 or the RC time
constant power-up reset scheme. Pressing S1 performs
a power-on reset. This resets the Si2456/33/14/03 to
factory defaults without turning off power. If S1 is used
in conjunction with U6, pressing S1 will activate the
reset monitor in the DS1818 and produce a 220 ms
active low reset pulse. Pressing S1 when used with the
RC time constant power-up reset scheme will discharge
Rev. 0.7
Si2456/33/14/03URT-EVB
C49 and begin the charging of C49 through R11 once
S1 is released.
Interface Selection
The serial interface of the Si2456/33/14/03URT-EVB
can be connected to a computer, terminal, embedded
system, or any other Data Terminal Equipment (DTE)
via a standard RS-232 interface or through a direct TTL
serial interface. Additionally, a PCM interface is
provided for connection to optional Silicon Labs codec
evaluation boards to test the daisy chain connection to
the Si3000 voice codec or the Si3021 + Si3015 solid
state DAA for a multiple-line application.
11. If access to the interrupt pin (INT_N) is desired, it
can be connected to ring detect (RD) on the PC by
removing the jumper at JP6 position 4-5 and placing it
at 5-6 instead. This replaces the RI_N signal with INT_N
on RD (pin 9 of J1). The signals available on the
Si2456/33/14/03URT-EVB
serial
interface
(DB9
connector) are listed in Table 2.
Table 2. DB9 Pin Connections
Symbol
Name
DB9 Pin
CD
Carrier Detect
1
The Si2456/33/14/03 can be tested as a standard data
modem by connecting the Si2456/33/14/03URT-EVB to
a personal computer or other DTE, power and a phone
line. The RS-232 transceivers on the Si2456/33/14/
03URT-EVB can communicate at rates between
300 bps and 230.4 kbps. A PC can communicate with
the Si2456/33/14/03URT-EVB using a standard terminal
program such as HyperTerm or ProComm.
RXD
Received Data
2
TXD
Transmit Data
3
DTR
Data Terminal Ready
4
Signal Ground
5
DSR
Data Set Ready
6
RTS
Ready to Send
7
Jumper settings determine how the Si2456/33/14/
03URT-EVB is connected to the DTE. Table 1 lists the
interface controlled by each motherboard jumper. See
Figures 6 and 11.
CTS
Clear to Send
8
RD
Ring Indicator (RI_N/INT)
9*
Table 1. Interface Selection Jumpers
Jumper
SG
*Note: JP6 jumper option.
Direct Access Interface
Function
JP1
Daughter card Phone Line Connector
JP2
Daughter card Digital Connector
JP3
Direct Access Header
JP4
PCM Connector
JP5
EOFR/CD Option (Si2400 support)
JP6
RS-232 Jumpers
JP7
3.3 V Power for Si2456/33/14/03
JP8
RS-232 Transceiver TXD Jumper
The Si2456/33/14/03 motherboard supplies power,
power-on reset and an RJ-11 jack for the modem. The
direct access interface (JP3) is used to connect the
motherboard to an embedded system. JP3 provides
access to all of the Si2456/33/14/03 signals available on
the daughter card. It is necessary to remove all jumpers
from JP6 and JP8 to disconnect the RS232 transceivers
to prevent signal contention. Leave the jumper between
JP7 pins 1 and 2. Figure 2 illustrates the jumper settings
required for the direct access mode using the
motherboard.
RS-232 Interface
This operation mode uses the standard factory jumper
settings illustrated in Figure 1 on page 2. The Maxim
MAX232A transceivers interface directly with the TTL
levels available at the serial interface of the Si2456/33/
14/03 and, using internal charge pumps, make these
signals compatible with the RS-232 standard. This
simplifies the connection to PCs and other Data
Terminal Equipment (DTE). The transmit jumper (JP8)
should be connected whenever the RS-232 UART
interface is used. For normal RS-232 operation, JP6
should have jumpers at positions 1-2, 4-5, 7-8, and 10Rev. 0.7
5
Si2456/33/14/03URT- EVB
Figure 2. Direct Access Jumper Settings (outlined in gray)
6
Rev. 0.7
Si2456/33/14/03URT-EVB
PCM Connector
Modem Module Operation
The PCM connector (JP4) is designed to connect other
Silicon Laboratories evaluation boards to the Si2456/33/
14/03URT-EVB. These include the Si3000SSI-EVB to
demonstrate and prototype applications including
speakerphone and voice features, the Si3044PPT-EVB
to demonstrate and prototype multi-line applications or
the combination of the Si3000SSI-EVB and the
Si3044PPT-EVB to demonstrate voice and multi-line
functions. Consult the board-specific documentation of
these additional evaluation boards and the Si2456/33/
14/03 data sheet for further information regarding the
combination of these features with the Si2456/33/14/
03URT-EVB.
The Si2456/33/14/03DC daughter card is a complete
modem solution perfectly suited for use in an embedded
system. The daughter card requires a 3.3 V supply
capable of providing at least 35 mA and communicates
with the system via LVCMOS/TTL compatible digital
signals on JP1. Chassis ground and the RJ-11 jack (TIP
and RING) are connected via JP2. Be sure to provide
the proper power-on reset pulse to the daughter card if
it is used in the stand-alone mode just described.
Audio Output
Audio output is provided from the Si2456/33/14/03 on
the pin AOUT. This pulse width modulated (PWM) signal
allows the user to monitor call progress signals such as
dial tone, DTMF dialing, ring, busy signals, and modem
negotiation. Control of this signal is provided by AT
commands (ATMn) and register settings. The AOUT
signal can be connected to an amplifier such as the
LM386 (the default stuffing option on the Si2456/33/14/
03URT-EVB) for a high quality output. AOUT can also
be connected to a summing amplifier or multiplexer in
an embedded application as part of an integrated audio
system.
Amplifier (LM386)
The audio amplifier circuit consists of U5 (LM386), C45,
R3, R4, C47, C44, C48, R5, C46, and an optional
loudspeaker (LS1). The LM386 has an internally set
voltage gain of 20. R3 and R4 provide a voltage divider
to reduce the AOUT signal to prevent overdriving the
LM386. C45 provides dc blocking for the input signal
and forms a high-pass filter with R3+R4 while R4 and
C47 form a low-pass filter. These four components limit
the bandwidth of the AOUT signal. C44 provides high
frequency power supply bypassing for the LM386 and
should be connected to a hard ground and located very
close to the amplifier’s power supply and ground pins.
C48 and R5 form a compensation circuit to prevent
oscillation of the high current pnp transistor in the
LM386 output stage on negative signal peaks. These
oscillations can occur between 2–5 MHz and can pose
a radiation compliance problem if C48 and R5 are
omitted. C46 provides dc blocking for the output of the
LM386, which is biased at approximately 2.5 V (VCC/2),
and forms a high-pass filter with the impedance of the
loudspeaker (LS1). The output from the LM386 amplifier
circuit is available on the RCA jack, J2.
Reset Requirements
The Si2456/33/14/03 ISOmodem daughter card must
be properly reset at power up. The reset pin (pin 12) of
the Si2456/33/14/03, (JP1, pin 13), must be held low for
at least 5.0 ms after power is applied and stabilized to
ensure the device is properly reset (See “Motherboard”
section and the Si2456/33/14/03 data sheet for further
details).
Crystal Requirements
Clock accuracy and stability are important in modem
applications. To ensure reliable communication between
modems, the clock must remain within ±100 ppm of the
design value over the life of the modem. The crystal
selected for use in a modem application must have a
frequency tolerance of less than ±100 ppm for the
combination of initial frequency tolerance, drift over the
normal operating temperature range, and five year
aging. Other considerations such as production
variations in PC board capacitance and the tolerance of
loading capacitors must also be taken into account.
Protection
The Si2456/33/14/03URT-EVB will meet or exceed all
FCC and international PTT requirements and
recommendations for high-voltage surge and isolation
testing without any modification. The protection/isolation
circuitry includes C1, C4, C24, C25, FB1, FB2, RV1, F1,
Z4, Z5, D3, D4, Z1, and C30. The PCB layout is also a
key “component” in the protection circuitry. The Si2456/
33/14/03URT-EVB will provide isolation to 3 kV. Contact
Silicon Laboratories for information about designing to
higher levels of isolation.
Design
The following section contains the schematics, bill of
materials, and layout for the Si2456/33/14/03 including
the daughter card and motherboard.
Rev. 0.7
7
C26
Y1
2
1
VCC
VCC
U3
CLKOUT
FSYNC
R TS_N
RXD
TXD
CTS_N
RESET_N
CLKIN/XT ALI
XT ALO
CLKOUT/A0
FSYNC/D6
VD3. 3
GND
VDA
R TS/D7
RXD/RD
TXD/WR
CTS/CS
RESET
JP1
SDO/D5
DCD/D4
ESC/D3
C1A
ISOB
VD 3. 3
1 GND
VDB
SDI/D 2
RI/D 1
INT/D0
AOUT/IN T
24
23
22
21
20
19
18
7
16
15
14
13
SDO
DCD_N
ESC
R27
C1A
2
1
2
3
4
5
6
7
8
9
10
11
12
SDI
RI_N
INT_N
AOUT
CLKOUT
FSYNC
R TS_N
RXD
TXD
CTS_N
RESET_N
VCC
1
3
5
7
9
11
13
15
SDO
DCD_N
2
4
6
8
10
12
14
16
ESC
SDI
RI_N
INT_N
AOUT
D3
Z4
C40
3
HEADER 8X2
C30
Si2456
Si2433
Si2414
C35
C36
C37
C3
1
C10
S i2403
C30 may be used
for reducing
emissions.
Rev. 0.7
JP2
TI P
RING
Figure 3. Si2456/33/14/03 Schematic
Serial
Mode
CLKOUT
FSYNC
RTS_N
RXD
TXD
CTS_N
RESET_N
SDO
DCD_N
ESC
SDI
RI_N
INT_N
AOUT
Parallel
A0
D6
D7
RD_N
WR_N
CS_N
RESET_N
D5
D4
D3
D2
D1
D0
INT_N
Mode
Si2456/33/14/03URT- EVB
8
C27
I s ol a ti on Ba r r i e r
R efer to Appendix B and Application Note
AN48 for Layout G uidelines
Q4
Al l tr a c e s i n the DAA a r e a (e nc l os e d i n box)
mus t be s e pa r a te d f r om othe r c i r c ui ts by 2. 5
mm s pa c i ng f or gl oba l s a f e ty c ompl i a nc e .
T hi s s pa c i ng a ppl i e s to the te r mi na l s
be twe e n e a c h i s ol a ti on c a pa c i tor . T he
i s ol a ti on c a pa c i tor s a r e a s f ol l ows : C1, C4,
C24, C25.
Q1
R5
R8
R7
R 15
+
C 12
C 13
R 24
U2
C1
R 28
Unl e s s s pe c i f i e d othe r wi s e , r e s i s tor s a r e
+/-5 %, 1/16 W
16
15
14
13
12
11
10
9
C5
Q2
R6
R 11
R 12
R2
C 20
D4
C41, C42, C43, C44 a r e pr ovi de d f or
di f f e r e nt popul a ti on opti ons to a l l ow
f or s ur ge te s ti ng gr e a te r tha n 3kV.
R 18
C 22
2
C 41
S i3015
T S TA/QE 2 T X/F ILT 2
T S T B /DC T NC /F ILT
IG ND
RX
C 1B
R E XT
R NG 1
DC T /R E XT 2
R NG 2
NC /R E F
QB
NC /V R E G 2
QE
VR E G
+
C 1A
1
2
3
4
5
6
7
8
Unl e s s s pe c i f i e d othe r wi s e , c a pa c i tor s a r e
+/- 20 %, 16V
Z1
C 16
3
R 19
R 17
R 16
Z5
C 14 +
R 13
1
C6
C 44
Q3
C9
C4
C8
R 10
FB2
L2
F1
1
2
T IP
C 39
R 32
C 19
D2
R 26
R V1
C 38
R 31
D1
C 18
R 25
C7
L1
R9
FB1
R ING
C 42
C 43
C 25
C 24
C41, C42, C43, C44 a r e pr ovi de d f or
di f f e r e nt popul a ti on opti ons to a l l ow
f or s ur ge te s ti ng gr e a te r tha n 3kV.
Figure 4. Si3015 DAA Schematic
9
Si2456/33/14/03URT-EVB
Rev. 0.7
F 1 ma y not be ne e de d.
S e e the s e c ti on on
UL 1950 i n AN17 f or
de ta i l s .
Si2456/33/14/03URT- EVB
Table 3. Daughter Card Bill of Materials
Component
C1,C4
C3,C13,C35,C36
C5
C6,C10,C16,C37
C7,C8
C9
C12
C14
C18,C19
C20
C22
C24,C25
C26,C27
C30
C38,C39
D1,D2
D3,D4
FB1,FB2
F1
JP1
JP2
L1,L2
Q1,Q3
Q2
Q4
RV1
R2
R5
R6
R7,R8,R15,R16,R17,R19
R9,R10
R11
R12
R13
R18
R24
R25,R26
R27,R28
R31,R32
U2
U3
Y1
Z1
Z4,Z5
10
Value
150 pF, 3 kV, X7R, ±10%
0.22 µF, 25 V, X7R, ±20%
0.1 µF, 50 V, Tant, ±20%
0.1 µF, 16 V, X7R, ±20%
560 pF, 250 V, X7R, ±10
22 nF, 250 V, X7R, ±10
1.0 µF, 35 V, Tant, ±10%
0.68 µF, 16 V, Tant, ±10%
3.9 nF, 16 V, X7R, ±10%
0.01 µF, 16 V, X7R, ±10%
1800 pF, 50 V, X7R, ±10%
1000 pF, 3 kV, X7R, ±10%
33 pF, 16 V, NPO, ±5%
10 pF, 10 V, X7R, ±20%
47 pF, 16 V, X7R, ±10%
Dual Diode, 300 V, 225 mA
BAV99 Dual Diode, 100 V, 300 mA
Ferrite Bead
Fuse
HEADER 8X2
4X1 Header_0
68 µH, 150 mA, 4 Ω max, ±10%
NPN, 300 V
PNP, 300 V
NPN, 80 V
SiDactor, 275 V, 100 A
402 Ω, 1/16 W, ±1%
100 kΩ, 1/16 W, ±1%
120 kΩ, 1/16 W, ±5%
5.36 kΩ, 1/4 W, ±1%
56 kΩ, 1/10 W, ±5%
9.31 kΩ, 1/16 W, ±1%
78.7 Ω, 1/16 W, ±1%
215 Ω, 1/16 W, ±1%
2.2 kΩ, 1/10 W, ±5%
150 Ω, 1/10 W, ±5%
10 MΩ, 1/10 W, ±5%
10 Ω, 1/16 W, ±5%
470 Ω, 1/16 W, ±5%
Si3015
Si2456/33/14/03
4.9152 MHz, 20 pF, 50 ppm, 150 ESR
Zener, 43 V, 300 mW
Zener, 5.6 V, 500 mW
Rev. 0.7
Supplier
Novacap
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
AVX
Venkel
Venkel
Venkel
Novacap
Venkel
Venkel
Venkel
Central Semiconductor
Diodes, Inc.
Murata
Teccor
Samtec
Berg
Murata
Motorola
Motorola
Motorola
Teccor
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Venkel
Silicon Laboratories
Silicon Laboratories
CTS Reeves
General Semi
Diodes, Inc.
+5V
+5V
0
R XD_R
2
T XD_R
3
DT R _R
4
5
C D(o)
DS R (o)
R XD(o)
R T S (i)
T XD(i)
C T S (o)
DT R (i)
R D(o)
6
7
R T S _R
8
C T S _R
9
R D_R
C 37
1 uF
1
U1.3
3
U1.4
C 39
1 uF
SG
J1
DB 9-R S 232_1
U1.1
U1.5
4
5
11
R XD
C 1+
C 1-
V+
2
U2
U1.2
C 38
1 uF
NI
C 2+
V-
6
C 2T _OUT 1
T _IN2
T _OUT 2
U3.1
1
U3.3
3
U3.4
4
U3.5
5
U1.6
C 40
1 uF
T _IN1
C 41
1 uF
R XD_R
14
11
RD
10
CD
12
R _OUT 1
R _IN1
10
R _OUT 2
R _IN2
12
U3.9
T XD
T _IN1
T _OUT 1
T _IN2
T _OUT 2
9
R _OUT 1
R _IN1
R _OUT 2
R _IN2
"GND"
3
U1.4
4
U1.5
5
C 1-
16
U4
V+
MAX232A
C 2+
7
C T S _R
13
DT R _R
8
T XD_R
+5V
V-
2
U1.2
U3.1
U3.3
3
6
U1.6
U3.4
4
U3.5
5
1
V CC
U1.3
C 1+
14
G ND
JP8
"T XD"
V CC
1
R D_R
C 1+
C 1-
V+
MAX232A
C 2+
V-
2
U3.2
6
U3.6
TP2
11
CD
10
U1.12
12
S ta ndof f s i n ea c h c or ner of boa r d.
TP5
T _OUT 1
T _IN2
T _OUT 2
R _OUT 1
R _IN1
R _OUT 2
R _IN2
14
R XD_R
RD
11
7
C D_R
C T S _N
10
13
U1.13
DT R
12
8
R T S _R
U3.9
9
15
TP4
9
T _IN1
G ND
R TS
TP3
C 2-
C 2T _IN1
T _OUT 1
T _IN2
T _OUT 2
R _OUT 1
R _IN1
R _OUT 2
R _IN2
14
R D_R
7
C T S _R
13
DT R _R
8
T XD_R
G ND
R XD
15
"GND"
TP6
NOT E : U3 f ootpr i nt S OI C16-. 150 wi de to f i t
i ns i de U1 f ootpr i nt S OI C16-. 300 wi de.
Us e
s a me pi n 1 s i de pa ds f or both pa r ts .
Figure 5. RS-232 Transceiver Schematic
NOT E : U4 f ootpr i nt S OI C16-. 150 wi de to f i t
i ns i de U2 f ootpr i nt S OI C16-. 300 wi de.
Us e
s a me pi n 1 s i de pa ds f or both pa r ts .
11
Si2456/33/14/03URT-EVB
Rev. 0.7
U3
U1.1
U3.6
C 42
1 uF
+5V
TP1
6
C 2-
G ND
S i 2400
DCD or E OF R
AL E RT
ESC
none
V-
U3.2
15
S i 2414
DCD
RI or I NT
ESC
RT S
NI
C 2+
2
R T S _R
8
15
RS -232
CD
RD
DT R
RT S
9
R TS
C 1-
V+
U1.13
13
DT R
RS -232 Pi n F unc ti ons (pr i nt on s i l ks c r een)
C 1+
C D_R
7
C T S _N
U1.12
C 36
1 uF
16
16
1
C 34
1 uF
C 35
1 uF
V CC
C D_R
U1
V CC
C 33
1 uF
16
R1
T I P a nd RI NG mi ni mum 20 mi l s wi de a nd a s f a r a s pos s i bl e f r om gr ound.
JP3
C LK OUT
F S Y NC
R T S _N
R XD
T XD
C T S _N
R E S E T _N
R J1
JP1
1
3
5
7
9
11
13
15
T XD
R E S E T _N
C 43
0.1 uF
T IP
R ING
ESC
S DI
R I_N
INT _N
AOUT
C 32
NI
S OC K E T 8X2
S DO
DC D_N
2
4
6
8
10
12
14
16
ESC
S DI
R I_N
INT _N
AOUT
HE ADE R 8X2
Connec tor f or I S OModem modul e.
+5V
T a bl e NOT on s i l ks c r een
S i 2400
JP?
NC
1
NC
2
NC
3
4
NC
5
CL KOUT
6
GND
7
T XD
8
GPI O1
RXD
9
10
GPI O2
CT S
11
GPI O3
12
13
RE S E T
14
GPI O4
VD
15
AOUT
16
C 44
0.1 uF
C 45
R3
AOUT
VD
JP4
C LK OUT
1
3
5
7
9
0.1 uF
S DO
R E S E T _N
JP5
JP6
"E OF R"
1
47 k
C 47
R4
3k
820 pF
F S Y NC
2
4
6
8
10
3
7
2
+5V
Ri ght a ngl e c onnec tor on boa r d edge
ESC
DC D_N
C 31
NI
1
3
5
7
9
11
13
15
LS 1
+
C 46
1
5
+
Net na mes c or r es pond to
S i 24xx.
S ee ta bl e f or
S i 2400 equi va l ents
2
4
6
8
10
12
14
16
1
2
3
4
5
6
7
8
9
10
11
12
6
1
C T S _N
JP2
S DO
DC D_N
100 uF
2
NI
-
C 48
U5
4
8
R 17
3k
R XD
C LK OUT
F S Y NC
R T S _N
LM386M-1
S DI
0.1 uF
R C A J AC K
J2
R5
R6
R7
10
0
0
HE ADE R 5X2
3
"PCM"
R I_N
4
INT _N
6
5
RD
ESC
7
R I_N
9
"CD"
TP7
"Si 2400"
ESC
R9
0
"GPI O1"
TP8
S DI
"GPI O2"
8
DT R
R T S _N
10
TP9
12
"GPI O3"
AOUT
"GPI O4"
C LK OUT
VD
VD
T P 10
R I_N
"AOUT "
11
T P 12
T P 11
INT _N
U6
3
+5V
VC C
RST
DS 1818
OPT I ONAL
JP7
2.1 mm P ower jack
R 12
0
"5V"
U7
D1
1
D2
U8
2
R 13
1
D4
1.6
IN
OUT
3
3
4
G ND
D3
+
C 50
470 uF
C 52
0.1 uF
7805
G ND R E S E T /P G
EN
F B /NC
IN(1)
OUT (1)
IN(2)
OUT (2)
8
"5V f or S i 2400 ONL Y"
+3.3V
7
"3. 3V"
OPT I ONAL
S1
C 49
NI
"RE S E T "
R 14
196k
6
R 15
5
0
C 51
10 uF
T P S 77601DR
C 53
10 uF
R E S E T _N
1
G ND
3/4
2
J4
1/2
P ower C onnector
2
1
2
R 11
1k
"AI N"
OPT I ONAL
1
J3
S W P US HB UTTON
R TS
"7-12V AC or DC"
2
Rev. 0.7
"Si 2414"
S DI
2
CD
R 16
110k
Figure 6. Si2456/33/14/03URT-EVB Motherboard Power, Connector, Audio Schematic
Si2456/33/14/03URT- EVB
12
VD
VD
Si2456/33/14/03URT-EVB
Table 4. Motherboard Bill of Materials
Component
Value
Supplier
C31,C32
C33,C34,C35,C36,C37,C38,
C39,C40,C41,C42
C43,C44,C45,C48,C52
C46
C47
R2,R12,R15,C49
C50
C51,C53
D1,D2,D3,D4
JP1
JP2
JP3
JP4
JP7,JP5
JP6
JP8
J1
J2
J3
J4
LS1
RJ1
R1,R6,R7
R3
R4,R17
R5
R9
R11
R13
R14
R16
S1
TP1,TP2
TP3,TP4,TP5,TP6
TP7,TP8,TP9,TP10,TP11,
TP12
U1,U2
U3,U4
U5
U6
U7
U8
NI, Radial 7.5 mm space, not installed
1 µF, 25 V, ±10%, 0805,C0805X7R250-105KNE
Venkel
0.1 µF, 25 V, ±10%, 0805,C0805X7R250-104KNE
100 µF, 16 V, ±10%, radial 6.3x11,UVX1C101MEA1TD
820 pF, 50 V, ±5%, 0805,C0805COG500-821JNE
Not installed
470 µF, 25 V, ±20%, radial 10x16,UVX1E471MPA
10 µF, 16 V, ±10%, 1206,C1206X7R100-106KNE
DIODE, 30 V, 0.5 A, SOD-123,MBR0530T1
SOCKET 8X2, 8x2 100 mil, SSW-108-01-T-D
4X1 Socket, 4x1 100 mil, SSW-104-01-T-S
HEADER 8X2, 8x2 100 mil, TSW-108-07-T-D
HEADER 5X2, 5x2 100 mil, TSW-105-25-T-D-RA
3X1 Header, 3x1 100 mil, 68000-403
3X4_Jumper, 4X3X.1
2X1 Header, 2x1 100 mil,68000-403
DB9-RS232_1, thru-hole,K22-E9S-030
RCA JACK, thru-hole,16PJ097
Power Connector, thru-hole 2,TSA-2
2.1 mm Power jack, thru-hole 3,ADC-002-1
Not installed
MTJG-2-64-2-2-1, RJ11x2,MTJG-2-64-2-2-1
0, 1/16W, 5%, 0603,CR0603-16W-000J
47 k, 1/10 W, ±5%, 0805,NRC10J473TR
3 k, 1/10 W, ±5%, 0805,NRC10J302TR
10, 1/10 W, ±1%, 0805,NRC10F10R0TR
0, 1/10 W, 0603,CR0603-10W-000JT
1k, 1/10 W, ±5%, 0603,CR0603-10W-103JT
1.6, 1/8 W, +-5%, 1206,CR1206-8W-1R6JT
196k, 0805,MCHRIDEZHFX1963E
110k, 0805,CR21-114J-T
SW PUSHBUTTON, thru-hole,101-0161
Test Point, .040 PTH,151-203
Test Point, .125 PTH
Test Point, .040 PTH,151-205
NIC Components
Venkel
Motorola
Samtec
Samtec
Samtec
Samtec
Berg
Samtec
Berg
Kycon
Mouser
Adam Tech
Adam Tech
JL World
Adam Tech
Venkel
NIC Components
NIC Components
NIC Components
Venkel
Venkel
Venkel
Classic Comp
Classic Comp
Mouser
Mouser
Plastic Standoffs
Mouser
NI, SOIC16-.300,MAX232ACWE, not installed
MAX232A,SOIC16-.150,MAX232ACSE
OP-AMP,M,LM386M-1
DS1818,SOT-23,DS1818-10
TPS77601DR,8-Pin SOIC,TPS77601DR
7805,TO-220AB,uA7805CKC
Maxim
Maxim
National Semi
Dallas
Texas Instruments
Texas Instruments
Rev. 0.7
Venkel
Nichicon
Venkel
13
Rev. 0.7
Si2456/33/14/03URT- EVB
14
Figure 7. Daughter Card Component Side Silkscreen
15
Si2456/33/14/03URT-EVB
Rev. 0.7
Figure 8. Daughter Card Solder Side Silkscreen
Rev. 0.7
Si2456/33/14/03URT- EVB
16
Figure 9. Daughter Card Component Side Layout
17
Si2456/33/14/03URT-EVB
Rev. 0.7
Figure 10. Daughter Card Solder Side Layout
Rev. 0.7
Si2456/33/14/03URT- EVB
18
Figure 11. Motherboard Silkscreen
19
Si2456/33/14/03URT-EVB
Rev. 0.7
Figure 12. Motherboard Component Side Layout
Rev. 0.7
Si2456/33/14/03URT- EVB
20
Figure 13. Motherboard Solder Side Layout
Si2456/33/14/03URT-EVB
Complete Design Package on CD (see sales representative for details)
Silicon Laboratories can provide a complete design package of the Si2456/33/14/03URT-EVB including the
following:
OrCad Schematics
Gerber Files
BOM
Documentation
Please contact your local sales representative or Silicon Laboratories headquarter sales for ordering information.
Rev. 0.7
21
Si2456/33/14/03URT- EVB
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ISOmodem are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
22
Rev. 0.7
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