Standard Repair Process Detail Technical Manual

Standard Repair Process Detail Technical Manual
Internal Use Only
North/Latin America
http://aic.lgservice.com
Europe/Africahttp://eic.lgservice.com
Asia/Oceaniahttp://biz.lgservice.com
LED TV
SERVICE MANUAL
CHASSIS : LB48V
MODEL : 55UB820T
55UB829Y
55UB820T-TH
55UB829Y-TH
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL68084542 (1511-REV01)
Printed in Korea
CONTENTS
CONTENTS . ............................................................................................. 2
SAFETY PRECAUTIONS ......................................................................... 3
SERVICING PRECAUTIONS..................................................................... 4
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 14
BLOCK DIAGRAM................................................................................... 22
EXPLODED VIEW .................................................................................. 23
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-2-
LGE Internal Use Only
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by
in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-3-
LGE Internal Use Only
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the
following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precautions. Remember: Safety First.
General Servicing Precautions
1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board
module or any other receiver assembly.
b. Disconnecting or reconnecting any receiver electrical plug
or other electrical connection.
c. Connecting a test substitute in parallel with an electrolytic
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explosion hazard.
2. Test high voltage only by measuring it with an appropriate
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".
3. Do not spray chemicals on or near this receiver or any of its
assemblies.
4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication
of contacts in not required.
5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.
6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks
are correctly installed.
7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. Use with this receiver only the test fixtures specified in this
service manual.
CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors
and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component damage caused by static by static electricity.
1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder
ES devices.
4. Use only an anti-static type solder removal device. Some solder removal devices not classified as “anti-static” can generate
electrical charges sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.
6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or
comparable conductive material).
7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will
be installed.
CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity sufficient to damage an ES device.)
General Soldering Guidelines
1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within
the range or 500 °F to 600 °F.
2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. U
se the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.
(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Q
uickly draw the melted solder with an anti-static, suctiontype solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
(500 °F to 600 °F)
b. First, hold the soldering iron tip and solder the strand
against the component lead until the solder melts.
c. Q
uickly move the soldering iron tip to the junction of the
component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. Closely inspect the solder area and remove any excess or
splashed solder with a small wire-bristle brush.
-4-
LGE Internal Use Only
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
Removal
1. Desolder and straighten each IC lead in one operation by
gently prying up on the lead with the soldering iron tip as the
solder melts.
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing
the IC.
Replacement
1. Carefully insert the replacement IC in the circuit board.
2. Carefully bend each IC lead against the circuit foil pad and
solder it.
3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).
"Small-Signal" Discrete Transistor
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close
as possible to the component body.
2. Bend into a "U" shape the end of each of three leads remaining on the circuit board.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. Carefully remove the transistor from the heat sink of the circuit
board.
4. Insert new transistor in the circuit board.
5. Solder each transistor lead, and clip off excess lead.
6. Replace heat sink.
Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connections).
1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).
2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.
4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly connected to the affected copper pattern.
3. C
onnect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-5-
LGE Internal Use Only
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This specification is applied to the LED TV used LB48V
chassis.
3. Test method
2. Requirement for Test
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC specification
Each part is tested as below without special appointment.
1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
4. Model General Specification
No.
Item
Specification
1
Market
Asia, Oceania, Africa, Middle East(PAL/DVB Market)
2
Broadcasting system
Digital : DVB-T
Analog : PAL-BG, DK, I/I’, SECAM-DK/BG/I
3
Receiving system
Digital : COFDM, QAM
Analog : Upper Heterodyne
5
Video Input (1EA)
PAL, SECAM, NTSC
6
7
Component Input (1EA)
HDMI Input (3EA)
Y/Cb/Cr, Y/Pb/Pr
Side (1:HDCP2.2 ,2:ARC ,3:MHL)
8
Audio Input (1EA)
Component, AV, DVI
9
10
SPDIF out(1EA)
Analog audio out(1EA)
Optical Audio out
Headphone and External speaker out
11
USB Input(3EA)
EMF, DivX HD, For SVC (download)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-6-
Remarks
DTV & Analog
* DTV Region: Australia/NewZealand(AU),
Singapore(SG), Malaysia(MY), Vietnam(VN),
South Africa(ZA), Iran(IR), Israel(IL)
▪ Australia/India : only PAL-BG(B)
▪ DVB-T
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
4 System : PAL, SECAM, NTSC, PAL60
Rear (gender)
Rear (Phone-Jack Type)
HDMI Input 1,2,3
Rear (AV Gender)
Component, AV and DVI use same jack.
Rear (1EA)
Rear (1EA)
Side JPEG, MP3, DivX HD
(USB 3.0 : 1EA, USB 2.0 : 2EA)
LGE Internal Use Only
5. External Input Format
5.1. Component (Y, PB, PR)
No.
1.
Resolution
H-freq(kHz)
V-freq(Hz)
Pixel clock(MHz)
Proposed
720*480i
15.73
59.94
13.50
SDTV, DVD 480I(525I)
2
720*480i
15.73
60.00
13.51
SDTV, DVD 480I(525I)
3.
720*576i
15.63
50.00
13.50
SDTV, DVD 576I(625I) 50Hz
4
720*480p
31.47
59.94
27.00
SDTV 480P
5
720*480p
31.50
60.00
27.03
SDTV 480P
6
720*576p
31.25
50.00
27.00
SDTV 576P 50Hz
7
1280*720
44.96
59.94
74.18
HDTV 720P
8
1280*720
45.00
60.00
74.25
HDTV 720P
9
1280*720
45.00
50.00
74.25
HDTV 720P 50Hz
10
1920*1080
28.13
50.00
74.25
HDTV 1080I 50Hz,
11
1920*1080
33.72
59.94
74.18
HDTV 1080I
12
1920*1080
33.75
60.00
74.25
HDTV 1080I
13
1920*1080
56.25
50.00
148.50
HDTV 1080P
14
1920*1080
67.50
60.00
148.50
HDTV 1080P
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-7-
LGE Internal Use Only
5.2. HDMI(PC/DTV)
(1) DTV mode
No.
Resolution
H-freq(kHz)
V-freq.(kHz)
Pixel clock(MHz)
Proposed
1
640*480
31.47
59.94
25.13
SDTV 480P
2
640*480
31.50
60.00
25.13
SDTV 480P
Remarks
3
720*480
15.73
59.94
13.50
SDTV, DVD 480I(525I)
4
720*480
15.75
60.00
13.51
SDTV, DVD 480I(525I)
5
720*576
15.63
50.00
13.50
SDTV, DVD 576I(625I) 50Hz
6
720*480
31.47
59.94
27.00
SDTV 480P
7
720*480
31.50
60.00
27.03
SDTV 480P
8
720*576
31.25
50.00
27.00
SDTV 576P
9
1280*720
44.96
59.94
74.18
HDTV 720P
10
1280*720
45.00
60.00
74.25
HDTV 720P
11
1280*720
37.50
50.00
74.25
HDTV 720P
12
1920*1080
28.13
50.00
74.25
HDTV 1080I
13
1920*1080
33.72
59.94
74.18
HDTV 1080I
14
1920*1080
33.75
60.00
74.25
HDTV 1080I
15
1920*1080
26.97
23.98
63.30
HDTV 1080P
16
1920*1080
27.00
24.00
63.36
HDTV 1080P
17
1920*1080
33.71
29.97
79.12
HDTV 1080P
18
1920*1080
33.75
30.00
79.20
HDTV 1080P
19
1920*1080
56.25
50.00
148.50
HDTV 1080P
20
1920*1080
67.43
59.94
148.35
HDTV 1080P
21
1920*1080
67.50
60.00
148.50
HDTV 1080P
22
3840*2160
53.95
23.98
297.00
UDTV 2160P
23
3840*2160
54.00
24.00
297.00
UDTV 2160P
24
3840*2160
56.25
25.00
297.00
UDTV 2160P
25
3840*2160
61.43
29.97
297.00
UDTV 2160P
26
3840*2160
67.50
30.00
297.00
UDTV 2160P
27
3840*2160
112.50
50.00
594.00
UDTV 2160P
8 bit / YCbCr 4:2:0
28
3840*2160
135.00
59.94
593.41
UDTV 2160P
8 bit / YCbCr 4:2:0
29
3840*2160
135.00
60.00
594.00
UDTV 2160P
8 bit / YCbCr 4:2:0
30
4096*2160
53.95
23.98
297.00
UDTV 2160P
31
4096*2160
54.00
24.00
297.00
UDTV 2160P
32
4096*2160
56.25
25.00
297.00
UDTV 2160P
33
4096*2160
61.43
29.97
297.00
UDTV 2160P
34
4096*2160
67.50
30.00
297.00
UDTV 2160P
35
4096*2160
112.50
50.00
594.00
UDTV 2160P
8 bit / YCbCr 4:2:0
36
4096*2160
135.00
59.94
593.41
UDTV 2160P
8 bit / YCbCr 4:2:0
37
4096*2160
135.00
60.00
594.00
UDTV 2160P
8 bit / YCbCr 4:2:0
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-8-
Spec. out but display
LGE Internal Use Only
(2) PC mode
No.
Resolution
H-freq(kHz)
V-freq.(kHz)
Pixel clock(MHz)
Proposed
1
640*350
31.47
70.09
25.17
EGA
2
720*400
31.47
70.08
28.32
DOS
3
640*480
31.47
59.94
25.17
VESA(VGA)
4
800*600
37.88
60.32
40.00
VESA(SVGA)
5
1024*768
48.36
60.00
65.00
VESA(XGA)
6
1360*768
47.71
60.02
84.75
VESA(WXGA)
7
1152*864
54.35
60.05
80.00
VESA
8
1280*1024
63.98
60.02
109.00
SXGA
9
1920*1080
67.50
60.00
158.40
WUXGA(Reduced Blanking)
10
3840*2160
54.00
24.00
297.00
UDTV 2160P
11
3840*2160
56.25
25.00
297.00
UDTV 2160P
12
3840*2160
67.50
30.00
297.00
UDTV 2160P
13
4096*2160
53.95
23.98
297.00
UDTV 2160P
14
4096*2160
54.00
24.00
297.00
UDTV 2160P
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-9-
Remarks
LGE Internal Use Only
6. 3D Mode
6.1. RF Input
No.
Resolution
H-freq(kHz)
V-freq.(kHz)
Pixel clock(MHz)
Proposed
Remarks
1
1280*720
37.500
50
74.25
HDTV 720P
2D to 3D, Side by Side, Top & Bottom
2
1920*1080
28.125
50
74.25
HDTV 1080I
2D to 3D, Side by Side, Top & Bottom
6.2. HDMI Input
(1) HDMI 1.4/2.0(3D Supported mode manually)
No.
Resolution
H-freq(kHz) V-freq.(kHz)
Pixel clock(MHz)
Proposed
3D input proposed mode
1
720*480
31.50
60.00
27.03
SDTV 480P
2
720*576
31.25
50.00
27.00
SDTV 576P
3
1280*720
45.00
60.00
74.25
HDTV 720P
37.50
50.00
74.25
HDTV 720P
33.75
60.00
74.25
HDTV 1080I
28.13
50.00
74.25
HDTV 1080I
27.00
24.00
74.25
HDTV 1080P
28.12
25.00
74.25
HDTV 1080P
33.75
30.00
74.25
HDTV 1080P
67.50
60.00
148.50
HDTV 1080P
56.25
50.00
148.50
HDTV 1080P
2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Single Frame Sequential, Row
Interleaving, Column Interleaving
53.95
23.98
297.00
54.00
24.00
296.70
56.25
25.00
297.00
HDTV 2160P
2D to 3D, Top & Bottom(half), Side by Side(half),
61.43
29.97
297.00
67.50
30.00
296.70
112.50
50.00
594.00
HDTV 2160P
135.00
60.00
594.00
HDTV 2160P
2D to 3D, Top & Bottom(half), Side by Side(half),
(8 bit, YCbCr 4:2:0)
4
5
1920*1080
3840*2160
4096*2160
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 10 -
2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Frame Sequential, Row Interleaving, Column Interleaving
2D to 3D, Side by Side(Half), Top & Bottom
2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Row Interleaving, Column
Interleaving
LGE Internal Use Only
(2) HDMI 1.4b (3D Supported mode automatically)
No.
1
2
3
4
5
Resolution
640*480
720*480
720*576
1280*720
1920*1080
H-freq(kHz)
V-freq.(Hz)
31.47 / 31.50
59.94/ 60.00
25.13/25.20
1
31.47 / 31.50
59.94/ 60.00
50.35/50.40
1
62.94 / 63.00
59.94/ 60.00
50.35/50.40
1
31.47 / 31.50
59.94 / 60.00
27.00/27.03
2,3
31.47 / 31.50
59.94 / 60.00
54.00/54.06
2,3
62.94 /63.00
59.94 / 60.00
54.00/54.06
2,3
31.25
50.00
27.00
17,18
31.25
50.00
54.00
17,18
62.50
50.00
54.00
17,18
15.63
50.00
27.00
21
37.50
50.00
74.25
19
37.50
50.00
148.50
19
44.96 / 45.00
59.94 / 60.00
74.17/74.25
4
44.96 / 45.00
59.94 / 60.00
148.35/148.50
4
75.00
50.00
148.50
19
89.91/90.00
59.94 / 60.00
148.35/148.50
4
28.13
50.00
74.25
20
28.13
50.00
148.50
20
33.72 / 33.75
59.94 / 60.00
74.17/74.25
5
33.72 / 33.75
59.94 / 60.00
148.35/148.50
5
56.25
50.00
148.50
20
67.43/67.50
59.94 / 60.00
148.35/148.50
5
26.97 / 27.00
23.97 / 24.00
74.17 / 74.25
32
26.97 / 27.00
23.97 / 24.00
148.35 / 148.50
32
28.12
25.00
74.25
33
28.12
25.00
148.50
33
3D input proposed mode
Top-and-Bottom
Side-by-side(half)
Side-by-side(Full)
Frame packing
Line alternative
Top-and-Bottom
Side-by-side(half)
Side-by-side(Full)
Frame packing
Line alternative
Top-and-Bottom
Side-by-side(half)
Side-by-side(Full)
Frame packing
Line alternative
Frame packing
Field alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Top-and-Bottom
Side-by-side(half)
Side-by-side(Full)
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Line alternative
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Side-by-side(Full)
Frame packing
Field alternative
Frame packing
Field alternative
Top-and-Bottom
Side-by-side(half)
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Side-by-side(Full)
33.72 / 33.75
29.98 / 30.00
74.18/74.25
34
Side-by-side(Full)
33.72 / 33.75
29.98 / 30.00
148.35/148.50
34
43.94/54.00
23.97 / 24.00
148.35/148.50
32
56.25
25.00
148.50
33
67.43 / 67.5
29.98 / 30.00
148.35/148.50
34
56.25
50.00
148.50
31
67.43 / 67.50
59.94 / 60.00
148.35/148.50
16
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Pixel clock(MHz)
- 11 -
VIC
Frame packing
Line alternative
Frame packing
Line alternative
Frame packing
Line alternative
Frame packing
Line alternative
Top-and-Bottom
Side-by-side(half)
Top-and-Bottom
Side-by-side(half)
Proposed
Secondary(SDTV 480P)
Secondary(SDTV 480P)
(SDTV 480P)
Secondary(SDTV 480P)
(SDTV 480P)
Secondary(SDTV 480P)
Secondary(SDTV 480P)
(SDTV 480P)
Secondary(SDTV 480P)
(SDTV 480P)
Secondary(SDTV 576P)
Secondary(SDTV 576P)
(SDTV 576P)
Secondary(SDTV 576P)
(SDTV 576P)
Secondary(SDTV 576I)
(SDTV 576I
(SDTV 576I
Secondary(SDTV 576I)
Secondary(SDTV 576I)
Primary(HDTV 720P)
Primary(HDTV 720P)
(HDTV 720P)
Primary(HDTV 720P)
Primary(HDTV 720P)
(HDTV 720P)
Primary(HDTV 720P)
(HDTV 720P)
Primary(HDTV 720P)
(HDTV 720P)
Secondary(HDTV 1080I)
Primary(HDTV 1080I)
(HDTV 1080I)
Secondary(HDTV 1080I)
Primary(HDTV 1080I)
(HDTV 1080I)
Primary(HDTV 1080I)
(HDTV 1080I)
Primary(HDTV 1080I)
(HDTV 1080I)
Primary(HDTV 1080P)
Primary(HDTV 1080P)
(HDTV 1080P)
Secondary(HDTV 1080P)
Secondary(HDTV 1080P)
(HDTV 1080P)
Primary(HDTV 1080P)
Secondary(HDTV 1080P)
(HDTV 1080P)
Primary(HDTV 1080P)
(HDTV 1080P)
Secondary(HDTV 1080P)
(HDTV 1080P)
Primary(HDTV 1080P)
(HDTV 1080P)
Primary(HDTV 1080P)
Secondary(HDTV 1080P)
Primary(HDTV 1080P)
Secondary(HDTV 1080P)
LGE Internal Use Only
(3) HDMI-PC Input (3D) (3D Supported mode manually)
No.
Resolution
H-freq(kHz) V-freq.(kHz)
Pixel clock(MHz)
Proposed
3D input proposed mode
1
1024*768
48.36
60.00
65.00
HDTV 768P
2D to 3D, Side by Side(half), Top & Bottom
2
1920*1080
67.500
60
148.50
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom,
Checker Board, Single Frame Sequential,
Row Interleaving, Column Interleaving
54.00
24.00
296.70
3
3840*2160
56.25
25.00
297.00
HDTV 2160P
67.50
30.00
296.70
2D to 3D, Top & Bottom(half), Side by
Side(half),
54
24.00
297.00
HDTV 2160P
2D to 3D,
Top & Bottom(half), Side by Side(half),
-
640*350
720*400
640*480
800*600
1152*864
2D to 3D, Side by Side(half), Top & Bottom
4
5
4096*2160
Others
-
-
(4) Component Input (3D) (3D Supported mode manually)
No.
1
Resolution
1280*720
H-freq(kHz) V-freq.(kHz)
37.50
50.00
Pixel clock(MHz)
74.25
Proposed
HDTV 720P
3D input proposed mode
2D to 3D, Side by Side(half), Top & Bottom
2
1280*720
45.00
60.00
74.25
HDTV 720P
2D to 3D, Side by Side(half), Top & Bottom
3
1280*720
44.96
59.94
74.18
HDTV 720P
2D to 3D, Side by Side(half), Top & Bottom
4
1920*1080
33.75
60.00
74.25
HDTV 1080I
2D to 3D, Side by Side(half), Top & Bottom
5
1920*1080
33.72
59.94
74.18
HDTV 1080I
2D to 3D, Side by Side(half), Top & Bottom
6
1920*1080
28.12
50.00
74.25
HDTV 1080I
2D to 3D, Side by Side(half), Top & Bottom
7
1920*1080
67.50
60.00
148.50
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
8
1920*1080
67.43
59.94
148.35
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
9
1920*1080
27.00
24.00
74.25
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
10
1920*1080
28.12
25.00
74.25
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
11
1920*1080
56.25
50.00
74.25
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
12
1920*1080
26.97
23.98
74.18
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
13
1920*1080
33.75
30.00
74.25
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
14
1920*1080
33.71
29.97
74.18
HDTV 1080P
2D to 3D, Side by Side(half), Top & Bottom
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 12 -
LGE Internal Use Only
6.3. USB - Movie (3D) (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
3D input proposed mode
1
Under 704x480
-
-
-
2D to 3D
2
Over 704x480
Under 1080P
interlaced
-
-
-
2D to 3D, Side by Side(Half), Top & Bottom
-
50 / 60
-
3
Over 704x480
Under 1080P
progressive
2D to 3D, Side by Side(Half), Top & Bottom, Checker
Board, Row Interleaving, Column Interleaving, Frame
Sequential
-
others
-
2D to 3D, Side by Side(Half), Top & Bottom, Checker
Board, Row Interleaving, Column Interleaving
4
Over 2160P
-
24/25/30
-
2D to 3D, Side by Side(Half), Top & Bottom
6.4. USB, DLNA - Photo (3D) (3D supported mode manually)
No.
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
1
Under 320x240
Resolution
-
-
-
2D to 3D
3D input proposed mode
2
Over 320x240
-
-
-
2D to 3D, Side by Side(Half), Top & Bottom
6.5. USB, DLNA (3D) (3D supported mode automatically)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
1
1080p
33.75
30.00
74.25
2
2160p
67.50
30.00
297.00
3D input proposed mode
Side by Side(Half), Top & Bottom, Checker Board
MPO(Photo), JPS(Photo)
6.6. Miracast, Widi (3D supported mode manually)
No.
1
Resolution
1024*768p
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
-
30/60
-
2
1280*720p
-
30/60
-
3
1920*1080p
-
30/60
-
4
Others
-
-
-
3D input proposed mode
2D to 3D, Side by Side(Half), Top & Bottom
2D to 3D
■ Remark: 3D Input mode
No.
1
Side by Side
L
R
Top & Bottom
Checker board
LLLLL
R
L
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Single Frame
Sequential
R
Frame Packing
Line
Interleaving
Column
Interleaving
L
- 13 -
LGE Internal Use Only
ADJUSTMENT INSTRUCTION
1. Application Range
This specification sheet is applied to all of the LED TV with
LB48V chassis.
3.2. LAN Inspection
3.2.1. Equipment & Condition
▪ Each other connection to LAN Port of IP Hub and Jig
2. Designation
(1) Because this is not a hot chassis, it is not necessary to
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240
V~, 50/60 Hz.
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15.
3.2.2. LAN inspection solution
▪ LAN Port connection with PCB
▪ Network setting at MENU Mode of TV
▪ Setting automatic IP
▪ Setting state confirmation
- If automatic setting is finished, you confirm IP and MAC
Address.
In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
hours.
In case of keeping module is in the circumstance of below
-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
3.2.3. WIDEVINE key Inspection
- Confirm key input data at the "IN START" MENU Mode.
3. Automatic Adjustment
3.1. M
AC address D/L, CI+ key D/L, Widevine
key D/L, ESN D/L, HDCP20 D/L
Connect: USB port
Communication Prot connection
▪ Com 1,2,3,4 and 115200(Baudrate)
Mode check: Online Only
▪ Check the test process
: DETECT → ESN → Widevine → CI → HDCP20
* DTCP key is downloaded only for EU suffix models, for
example, 47LA660S-ZA.KEUYLJG
▪ Play: Press Enter key
▪ Result: Ready, Test, OK or NG
▪ Printer Out (MAC Address Label)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 14 -
LGE Internal Use Only
3.3. LAN PORT INSPECTION(PING TEST)
3.5. CI+ Key checking method
Connect SET → LAN port == PC → LAN Port
SET
- Check the Section 3.1
Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).
PC
3.3.1. Equipment setting
(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program.
*IP Number : 12.12.2.2
=> Check the Download to CI+ Key value in LGset.
3.5.1. Check the method of CI+ Key value
(1) Check the method on Instart menu
(2) Check the method of RS232C Command
1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1
CMD 2
Data 0
3.3.2. LAN PORT inspection(PING TEST)
(1) Play the LAN Port Test Program.
(2) Connect each other LAN Port Jack.
(3) Play Test (F9) button and confirm OK Message.
(4) Remove LAN cable.
A
A
0
0
2) Check the key download for transmitted command
(RS232: ci 00 10)
CMD 1
CMD 2
C
I
Data 0
1
0
3) Result value
- Normally status for download : OKx
- Abnormally status for download : NGx
3.5.2. Check the method of CI+ key value(RS232)
1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1
CMD 2
Data 0
3.4. Model name & Serial number Download
A
3.4.1. Model name & Serial number D/L
A
0
0
2) Check the mothed of CI+ key by command
(RS232: ci 00 20)
Press "P-ONLY" key of service remote control.
(Baud rate : 115200 bps)
▪ Connect RS-232C Signal to USB Cable to USB.
▪ Write Serial number by use USB port.
▪ Must check the serial number at Instart menu.
▪
CMD 1
CMD 2
C
I
Data 0
2
0
3) Result value
i 01 OK 1d1852d21c1ed5dcx
3.4.2. Method & notice
(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0.
CI+ Key Value
3.6. WIFI MAC ADDRESS CHECK
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always)
It is impossible to download by bar code scan, so It need
Manual download.
1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "7.Model Number D/L" like below photo.
3) Input the Factory model name(ex 47LB650V-ZA) or Serial
number like photo.
(1) Using RS232 Command
Transmission
H-freq(kHz)
V-freq.(Hz)
[A][I][][Set ID][][20][Cr]
[O][K][X] or [NG]
(2) Check the menu on in-start
4) Check the model name Instart menu. → Factory name
displayed. (ex 47LB650V-ZA)
5) C heck the Diagnostics.(DTV country only) → Buyer
model displayed. (ex 47LB650V-ZA)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 15 -
LGE Internal Use Only
4. Manual Adjustment
4.1. EDID(The
Extended Display Identification
Data)/DDC(Display Data Channel) download
4.1.1. Overview
It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information sharing without any necessity
of user input. It is a realization of "Plug and Play".
4.1.2. Equipment
- Since embedded EDID data is used, EDID download JIG,
HDMI cable and D-sub cable are not need.
- Adjustment remote control
4.1.3. Download method
(1) Press "ADJ" key on the Adjustment remote control, then
select "12.EDID D/L", By pressing "Enter" key, enter EDID
D/L menu.
For HDMI EDID
DVI-D to HDMI or HDMI to HDMI
(1) EDID for Non 3D Model
# HDMI 1(C/S: E7 2D)
EDID Block 0, Bytes 0-127 [00H-7FH]
0
10
20
30
40
50
60
70
0
00
01
0F
01
45
40
3E
00
80
90
A0
B0
C0
D0
E0
F0
0
02
22
09
03
71
00
00
00
1
FF
18
50
01
00
70
1E
4C
2
FF
01
54
01
40
36
53
47
3
FF
03
A1
01
84
00
10
20
4
FF
80
08
01
63
40
00
54
5
FF
A0
00
01
00
84
0A
56
6
FF
5A
31
02
00
63
20
0A
7
00
78
40
3A
1E
00
20
20
8
1E
0A
45
80
66
00
20
20
9
6D
EE
40
18
21
1E
20
20
A
01
91
61
71
50
00
20
20
B
00
A3
40
38
B0
00
20
20
C
01
54
71
2D
51
00
00
20
D
01
4C
40
40
00
FD
00
20
E
01
99
81
58
1B
00
00
01
F
01
26
80
2C
30
3A
FC
E7
B
03
06
20
66
00
84
00
00
C
02
C0
00
01
00
63
00
00
D
12
15
80
1D
9E
00
00
00
E
20
07
01
80
01
00
00
00
F
21
50
02
18
1D
1E
00
2D
B
00
A3
40
38
B0
00
20
20
C
01
54
71
2D
51
00
00
20
D
01
4C
40
40
00
FD
00
20
E
01
99
81
58
1B
00
00
01
F
01
26
80
2C
30
3A
FC
E7
B
03
06
20
66
00
84
00
00
C
02
C0
00
01
00
63
00
00
D
12
15
80
1D
9E
00
00
00
E
20
07
01
80
01
00
00
00
F
21
50
02
18
1D
1E
00
1D
B
03
06
20
66
00
84
00
00
C
02
C0
00
01
00
63
00
00
D
12
15
80
1D
9E
00
00
00
E
20
07
01
80
01
00
00
00
F
21
50
02
18
1D
1E
00
1D
EDID Block 1, Bytes 128-255 [80H-FFH]
1
03
15
57
04
1C
72
00
00
2
3C
01
07
E3
16
51
00
00
3
F1
5D
6E
05
20
D0
00
00
4
54
5E
03
03
58
1E
00
00
5
10
5F
0C
01
2C
20
00
00
6
9F
62
00
E5
25
6E
00
00
7
04
63
10
0E
00
28
00
00
8
13
64
00
60
40
55
00
00
9
05
29
B8
61
84
00
00
00
A
14
3D
3C
65
63
40
00
00
# HDMI2 (C/S: E7 1D)
EDID Block 0, Bytes 0-127 [00H-7FH]
(2) S elect "Start" button by pressing "Enter" key, HDMI1/
HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG.
4.1.4. EDID DATA
▪ Reference
- HDMI1 ~ HDMI3
- In the data of EDID, bellows may be different by Input mode.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0
00
1
2
3
4
5
FF FF FF FF FF
ⓒ
01 03 80 A0
0F 50 54 A1 8 00
01 01 01 01 01 01
45 00 40 84 63 00
40 70 36 00 40 84
3E 1E 53 10 00 0A
02
22
03
15
3A F1 4E 10
01 29 3D 06
2D
71
00
00
ⓕ
40
1C
72
00
10 28 10
58 2C 45 00
16 20 58 2C
51 D0 1E 20
00 00 00 00
6
7
8
FF 00 1E
5A 78 0A
31 40 45
02 3A 80
00 1E 66
63 00 00
20 20 20
ⓓ
9F 04 13
C0 15 07
ⓕ
E3 05 03
40 84 63
25 00 40
6E 28 55
00 00 00
9
6D
EE
40
18
21
1E
20
05
50
B C D E
F
ⓐ
ⓑ
91 A3 54 4C 99 26
61 40 71 40 81 80
71 38 2D 40 58 2C
50 B0 51 00 1B 30
00 00 00 FD 00 3A
ⓓ
20 20
01 ⓔ1
14 03 02 12 20 21
ⓕ
01
00
84
00
00
02
00
63
40
00
00
10
20
30
40
50
60
70
0
00
01
0F
01
45
40
3E
00
80
90
A0
B0
C0
D0
E0
F0
0
02
22
09
03
71
00
00
00
80 18 71 38
01 1D 80 18
00 9E 01 1D
63 00 00 1E
00 00 00 ⓔ2
ⓐ Product ID
ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ → ‘01’, Year : ‘2014’ → ‘18’
ⓓ Model Name(Hex): LGTV
ⓔ Checksum(LG TV): Changeable by total EDID data.
ⓕ Vendor Specific(HDMI)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 16 -
2
FF
01
54
01
40
36
53
47
3
FF
03
A1
01
84
00
10
20
4
FF
80
08
01
63
40
00
54
5
FF
A0
00
01
00
84
0A
56
6
FF
5A
31
02
00
63
20
0A
7
00
78
40
3A
1E
00
20
20
8
1E
0A
45
80
66
00
20
20
9
6D
EE
40
18
21
1E
20
20
A
01
91
61
71
50
00
20
20
EDID Block 1, Bytes 128-255 [80H-FFH]
A
3A
1E
00
84
00
1
FF
18
50
01
00
70
1E
4C
1
03
15
57
04
1C
72
00
00
2
3C
01
07
E3
16
51
00
00
3
F1
5D
6E
05
20
D0
00
00
4
54
5E
03
03
58
1E
00
00
5
10
5F
0C
01
2C
20
00
00
6
9F
62
00
E5
25
6E
00
00
7
04
63
20
0E
00
28
00
00
8
13
64
00
60
40
55
00
00
9
05
29
B8
61
84
00
00
00
A
14
3D
3C
65
63
40
00
00
# HDMI3 (C/S: E7 0D)
EDID Block 0, Bytes 0-127 [00H-7FH]
80
90
A0
B0
C0
D0
E0
F0
0
02
22
09
03
71
00
00
00
1
03
15
57
04
1C
72
00
00
2
3C
01
07
E3
16
51
00
00
3
F1
5D
6E
05
20
D0
00
00
4
54
5E
03
03
58
1E
00
00
5
10
5F
0C
01
2C
20
00
00
6
9F
62
00
E5
25
6E
00
00
7
04
63
20
0E
00
28
00
00
8
13
64
00
60
40
55
00
00
9
05
29
B8
61
84
00
00
00
A
14
3D
3C
65
63
40
00
00
LGE Internal Use Only
4.2.4. Adj. Command (Protocol)
EDID Block 1, Bytes 128-255 [80H-FFH]
80
90
A0
B0
C0
D0
E0
F0
0
02
22
09
03
71
00
00
00
1
03
15
57
04
1C
72
00
00
2
3C
01
07
E3
16
51
00
00
3
F1
5D
6E
05
20
D0
00
00
4
54
5E
03
03
58
1E
00
00
5
10
5F
0C
01
2C
20
00
00
6
9F
62
00
E5
25
6E
00
00
7
04
63
30
0E
00
28
00
00
8
13
64
00
60
40
55
00
00
9
05
29
B8
61
84
00
00
00
A
14
3D
3C
65
63
40
00
00
B
03
06
20
66
00
84
00
00
C
02
C0
00
01
00
63
00
00
D
12
15
80
1D
9E
00
00
00
E
20
07
01
80
01
00
00
00
<Command Format>
F
21
50
02
18
1D
1E
00
0D
START 6E
50
A LEN A 03
A
CMD
A
00
A
VAL
A
CS STOP
- LEN: Number of Data Byte to be sent
- CMD: Command
- VAL: FOS Data value
- CS: Checksum of sent data
- A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
* Checksum(HDMI1/2/3)
Input
A
▪ RS-232C Command used during auto-adjustment.
FFh (Checksum)
HDMI1
E7
2D
HDMI2
E7
1D
HDMI3
E7
0D
RS-232C COMMAND
[CMD
ID DATA]
wb
00
00
wb
00
10
wb
00
1f
wb
00
20
wb
00
2f
4.2. White Balance Adjustment
wb
4.2.1. Overview
▪ W/B adj. Objective & How-it-works
(1) Objective: To reduce each Panel's W/B deviation
(2) How-it-works : When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one
of R/G/B is fixed at 192, and the other two is lowered to
find the desired value.
(3) Adjustment condition : normal temperature
1) Surrounding Temperature : 25 °C ± 5 °C
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
▪ Adj. Map
Adj. item
Cool
Data Range
(Hex.)
CMD1
CMD2
MIN
MAX
R Gain
j
g
00
C0
G Gain
j
h
00
C0
B Gain
j
i
00
C0
R Gain
j
a
00
C0
G Gain
j
b
00
C0
B Gain
j
c
00
C0
R Gain
j
d
00
C0
G Gain
j
e
00
C0
B Gain
j
f
00
C0
Default
(Decimal)
R Cut
B Cut
Medium
R Cut
G Cut
B Cut
Co m p ut er
RS -232C
Command
(lower case ASCII)
G Cut
RS -232C
Probe
ff
wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f -> Gain adj. completed
*(wb 00 20(Start), wb 00 2f(end)) -> Off-set adj.
wb 00 ff -> End white balance auto-adj.
4.2.3. Equipment connection MAP
Co lo r Analyzer
Begin White Balance adjustment
Gain adjustment(internal white pattern)
Gain adjustment completed
Offset adjustment(internal white pattern)
Offset adjustment completed
End White Balance adjustment
(internal pattern disappears)
Ex)
4.2.2. Equipment
(1) Color Analyzer: CA-210 (LED Module : CH 14)
(2) Adjustment Computer(During auto adj., RS-232C protocol
is needed)
(3) Adjustment Remote control
(4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model: 204, Pattern: 49)
→ Only when internal pattern is not available
• Color Analyzer Matrix should be calibrated using CS-100.
00
Explanation
RS -232C
Pat t ern Generat o r
Warm
Signal Source
R Cut
* If TV internal pattern is used, not needed
G Cut
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 17 -
LGE Internal Use Only
4.2.5. Adj. method
(1) Auto adj. method
1) Set TV in adj. mode using POWER ON key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable.(RS-232C to USB)
4) Select mode in adj. Program and begin adj.
5) When adj. is complete (OK Sign), check adj. status pre
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj.
4.2.6. Reference (White balance Adj. coordinate and
color temperature)
▪ Luminance : 206 Gray
▪ Standard color coordinate and temperature using CS-1000
(over 26 inch)
Coordinate
Mode
Temp
∆uv
x
y
Cool
▪ W/B Adj. must begin as start command “wb 00 00” , and
finish as end command “wb 00 ff”, and Adj. offset if need.
(2) Manual adjustment. method
1) Set TV in Adj. mode using POWER ON.
2) Zero Calibrate the probe of Color Analyzer, then place it
on the center of LCD module within 10 cm of the surface.
3) Press ADJ key → EZ adjust using adj. R/C → 7. WhiteBalance then press the cursor to the right(key ►).
(When right key(►) is pressed 216 Gray internal pattern
will be displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.
5) Adjustment is performed in COOL, MEDIUM, WARM 3
modes of color temperature.
0.270
13000 K
0.0000
Medium
0.286
0.289
9300 K
0.0000
Warm
0.313
0.329
6500 K
0.0000
▪ Standard color coordinate and temperature using CA-210(CH 14)
Coordinate
Mode
Temp
∆uv
x
y
Cool
0.271 ± 0.002
0.270 ± 0.002
13000 K
0.0000
Medium
0.286 ± 0.003
0.289 ± 0.003
9300 K
0.0000
Warm
0.313 ± 0.002
0.329 ± 0.002
6500 K
0.0000
4.2.7. EDGE & IOL LED White balance table
** G-fix adjustment
Adjust modes (Cool), Fix the G gain to 172 (default data)
and change the others (G/B Gain).
Adjust two modes(Medium / Warm), Fix the one of R/G/B
gain to 192 (default data) and decrease the others.
▪ If internal pattern is not available, use RF input. In EZ Adj.
menu 7.White Balance, you can select one of 2 Testpattern: ON, OFF. Default is inner(ON). By selecting OFF,
you can adjust using RF signal in 216 Gray pattern.
▪ Adjustment condition and cautionary items
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer(CA-210) probe should be within 10 cm
and perpendicular of the module surface (80° ~ 100°)
3) Aging time
- After Aging Start, Keep the Power ON status during 5
Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
0.271
- 18 -
▪ Edge&ALEF LED module change color coordinate because
of aging time.
▪ Apply under the color coordinate table, for compensated
aging time.
▪ (Normal line) Edge & ALEF LED White balance table
- gumi(Mar. ~ Dec.) & Global
Model : (normal line) LGD, CMI
NC
4.0
Aging
time
(Min)
1
2
3
4
5
6
7
8
9
0-2
3-5
6-9
10-19
20-35
36-49
50-79
80-119
Over 120
Cool
x
y
271
270
282
289
281
287
279
284
277
280
275
277
274
274
273
272
272
271
271
270
Medium
x
y
286
289
297
308
296
306
294
303
292
299
290
296
289
293
288
291
287
290
286
289
Warm
x
y
313
329
324
348
323
346
321
343
319
339
317
336
316
333
315
331
314
330
313
329
- gumi Winter table(Jan., Fab.)- Gumi producing model use only
Model : (normal line) LGD, CMI
NC
4.0
Agingtime
(Min)
1
2
3
4
5
6
7
8
9
0-2
3-5
6-9
10-19
20-35
36-49
50-79
80-119
Over 120
Cool
x
y
271
270
283
292
282
290
280
288
277
284
275
279
274
275
273
272
272
271
271
270
Medium
x
y
286
289
297
315
296
313
294
311
291
307
289
302
288
298
287
295
286
294
286
289
Warm
x
y
313
329
322
347
321
345
319
343
316
339
314
334
313
330
312
327
311
326
313
329
LGE Internal Use Only
4.5. 3D function test
▪ (Aging Chamber) Edge & ALEF
Model : (aging chamber)LGD, CMI
NC
4.0
Aging
time
(Min)
1
2
3
4
5
6
7
8
9
0-5
6-10
11-20
21-30
31-40
41-50
51-80
81-119
Over 120
Cool
x
271
280
276
272
269
267
266
265
264
264
y
270
285
280
275
272
268
265
263
261
260
Medium
x
y
285
293
294
308
290
303
286
298
283
295
281
291
280
288
279
286
278
284
278
283
(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
* HDMI mode NO. 872 , pattern No.83
(1) Please input 3D test pattern like below.
Warm
x
313
319
315
311
308
306
305
304
303
303
y
329
340
335
330
327
323
320
318
316
315
(2) When 3D OSD appear automatically, then select green key.
4.3. Local Dimming Function Check
(1) Turn on TV.
(2) A t the Local Dimming mode, module Edge Backlight
moving right to left Back light of IOP module moving.
(3) Confirm the Local Dimming mode.
(4) Press “exit” Key.
(3) Don't wear a 3D Glasses, Check the picture like below.
4.4. Magic Motion Remote control test
- E quipment : RF Remote control for test, IR-KEY-Code
Remote control for test
- You must confirm the battery power of RF-Remote control
before test(recommend that change the battery per every lot)
- Sequence (test)
1) If you select the ‘start key(OK)’ on the Adjustment remote
control, you can pairing with the TV SET.
2) You can check the cursor on the TV Screen, when select
the "OK" key on the Adjustment remote control.
3) You must remove the pairing with the TV Set by select
‘Mute + OK Key’ on the Adjustment remote control.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
4.6. Option selection per country
4.6.1. Overview
- Option selection is only done for models in AJ/JA/IL
4.6.2.Method
- 19 -
(1) Press "ADJ" key on the Adjustment remote control, then
select Country Group Menu.
(2) Depending on destination, select Country Group Code or
Country Group then on the lower Country option, select
US, CA, MX. Selection is done using +, - or ►◄ KEY.
LGE Internal Use Only
5. GND and Internal Pressure check
4.7. HDMI ARC Function Inspection
(1) Test equipment
- Optic Receiver Speaker
- MSHG-600 (SW: 1220 ↑)
- HDMI Cable (for 1.4 version)
5.1. Method
(2) Test method
1) Insert the HDMI Cable to the HDMI ARC port from the
master equipment. (HDMI 1)
2) Check the sound from the TV Set.
(1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET. (If
loose, re-insert)
(2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX.)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the pallet
to move on to next process.
5.2. Checkpoint
▪ TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
▪ TEST time: 1 second
▪ TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
▪ LEAKAGE CURRENT: At 0.5 mArms
3) Check the Sound from the Speaker or using AV & Optic
TEST program (It’s connected to MSHG-600)
4.8. Tool Option selection
- Method : Press "ADJ" key on the Adjustment remote control,
then select Tool option.
6. Audio
4.9. Ship-out mode check (In-stop)
- After final inspection, press In-Stop key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.
No.
1
2
Item
Audio practical max
Output, L/R (Distortion=10% max Output)
Speaker
(8 Ω Impedance)
Min
Typ
Max
Unit
10
12
W
8.10 10.8 Vrms
10
12
W
EQ Off
AVL Off
Clear Voice Off
EQ On
AVL On
Clear Voice On
Measurement condition:
(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 20 -
LGE Internal Use Only
7. USB S/W Download(Service only)
(1) Put the USB Stick to the USB socket.
(2) Automatically detecting update file in USB Stick.
- If your downloaded program version in USB Stick is Low,
it didn't work. But your downloaded version is High, USB
data is automatically detecting.(Download Version High &
Power only mode, Set is automatically Download)
(3) Show the message "Copying files from memory".
(4) Updating is starting.
(5) Updating Completed, The TV will restart automatically.
(6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn't
have a DTV/ATV test on production line.
* After downloading, have to adjust TOOL OPTION again.
1) Push "IN-START" key in service remote control.
2) Select "Tool Option 1" and push "OK" key.
3) Punch in the number. (Each model has their number.)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 21 -
LGE Internal Use Only
R
E
A
R
(H)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 22 -
HDMI1 (HDCP2.2)
HDMI2 (ARC)
LNB
DEMOD
(S2)
Serial
Flash(4MB)
HDCP2.2
R9531AN
Sil9617
X_TAL
27MHz
TUNER
(S2)
TUNER
( T2/C/A)
HDMI3 (MHL)
DVB-S
Air/
Cable
T2/C/S2 W/O AD
ETHERNET
LAN
CVBS/RGB
CVBS/YPbPr
HDMI
MUX
USB
IR/KEY
I2S Out
I2C 4
Vx1
I2C 1
B
I2C 0
USB_WIFI
A
DDR3 1866 X 16
(512MB X 2EA)
Mstar LM14
T/C Demod
Analog Demod
P_TS
SPDIF OUT
LGE7411
OCP
1.5A
OCP
2A
CVBS
P_TS
X_TAL
24MHz
OPTIC
(IN/OUT)
SCART
AV/COMP
H/P
USB2
USB3
(2.0)
USB1
(HDD)
P_TS
IF (+/-)
P_TS
CI Slot
X_TAL
32.768KHz
Sub Micom
(RENESAS
R5F100GEAFB)
LOGO LIGHT(Ready)
WIFI/BT Combo
IR / KEY
MAIN Audio AMP
(NTP7514)
Video 4K@30p/2K@60p(Vx1 4 lane),
OSD FHD@60p(Vx1 2 lane)
eMMC
(4GB)
SYSTEM EEPROM
(256Kb)
DDR3 1866 X 16
(512MB X 2EA)
SUB
ASSY
LGE7411
BLOCK DIAGRAM
LGE Internal Use Only
Mux
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
502
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Stand screw
A10
- 23 -
Option
A2
200
A22
200T
820
120
LV1
530
121
504
540
501
500
521
522
503
410
570
900
400
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by
in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
LGE Internal Use Only
NVRAM
+3.3V_NORMAL
IC102
AT24C256C-SSHL-T
C103
0.1uF
EAN61133501
F10
PWM_DIM
I2C_SDA1
F12
E9
PWM_PM
AE32
PWM0/GPIO150
B0M
PWM1/GPIO151
B0P
PWM2/GPIO152
B1M
PWM3/GPIO153
B1P
PWM_PM/GPIO7
B2M/VBY7N
B2P/VBY7P
I2C for AMP&MODULE
I2C_SCL7
G5
I2C_SDA7
G4
+3.3V_NORMAL
B3
CVBS_OUT_SEL
G6
SAR0/GPIO43
BCKP/VBY6P
SAR1/GPIO44
B3M/VBY5P
SAR2/GPIO45
B3P/VBY5P
SAR3/GPIO46
B4M/VBY4N
OPT
4.7K
A4
B5
B6
C6
+3.3V_NORMAL
SPI_DI
SPI_CK/GPIO1
A0M/VBY3N
SPI_DI/GPIO2
A0P/VBY3P
SPI_DO/GPIO3
A1M/VBY2N
SPI_CZ0/GPIO0
A1P/VBY2P
SPI_CZ1/GPIO_PM6/GPIO16
A2M/VBY1N
SPI_CZ2/GPIO_PM10/GPIO20
A2P/VBY1P
R181
10K
OPT
PWM_PM
ACKP/VBY0P
FRC_FLASH_WP
R182
10K
A3M/LOCKN
H4
DDCA_CK
H5
DDCA_DA
DDCA_CK/UART0_RX/GPIO8
A3P/HTTPDN
DDCA_DA/UART0_TX/GPIO9
A4M
F7
I2C_SCL6
I2C_SDA6
CHIP_CONFIG[3:0]
{LED1, SPI_DI,LED0, PWM_PM}
E7
D7
E8
MUX_EN
Mode
Description
SB51_ExtSPI
51 boot from SPI
HEMCU_ExtSPI
ARM boot from SPI
HEMCU_ROM_EMMC
ARM boot from ROM; outer storage is eMMC
HEMCU_ROM_NAND
ARM boot from ROM; outer storage is NAND
DBUS
for test only
SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication
SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication
HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication;
D9
BIT5
BIT6
F8
T6
BIT7
T5
BIT8
AH10
EB_DATA[5]
AG13
AG30
TXVBY1_6N
EB_DATA[6]
AJ9
EB_DATA[7]
AJ12
AH31
TXVBY1_6P
AJ31
TXVBY1_5N
AJ32
TXVBY1_5P
EB_ADDR[0]
TXVBY1_4N
EB_ADDR[1]
AK17
TXVBY1_4P
EB_ADDR[2]
AM20
A3
AM19
AK30
TXVBY1_3P
EB_ADDR[6]
AL22
AL31
TXVBY1_2N
EB_ADDR[7]
AM17
AL30
TXVBY1_2P
EB_ADDR[8]
AM30
RX1/GPIO61
AL29
AM29
AK28
AH29
AJ29
BIT2
EJ_RSTZ/GPIO53
RX2/GPIO63
EJ_TRSTZ/GPIO54
TX3/GPIO64
EJ_TCK/GPIO55
RX3/GPIO65
EJ_TMS/GPIO56
TX4/GPIO69
EJ_TDI/GPIO57
RX4/GPIO70
EJ_TDO/GPIO58
TX5/GPIO87
EJ_DINT/GPIO59
AH28
BIT4
AJ28
R180
R189
10K
OPT
+3.3V_NORMAL
AG28
BIT3
URSA9_CONNECT
0
AH27
AJ27
BIT8_1
R124
10K
BIT0
BIT1
BIT2
AK15
EB_ADDR[10]
AG11
EB_ADDR[11]
AG12
HTPDAn_OSD
EB_ADDR[12]
AM22
LOCKAn_Video
PCM2_CEN/GPIO112
GPIO67
PCM2_IRQA/GPIO113
U5
A10
I2C_SCL1
I2C_SDA1
C10
I2C_SCL4
I2C_SDA4
V5
I2C_SCL5
I2C_SDA5
T4
I2C_SCL2
I2C_SDA2
W6
V6
U6
W5
AL27
EB_ADDR[13]
AL16
EB_ADDR[14]
AM16
CAM_IREQ_N
D12
TRST_N0
F4
TCK0
F6
TMS0
EB_WE_N
D4
TDI0
E5
TDO0
E4
01
CN/HK
11
BIT(2/3)
TPI_CLK
AH20
TPI_VAL
AG18
TPI_SOP
PCMADR[5]/GPIO137
TS0DATA_[2]/GPIO175
PCMADR[6]/GPIO136
TS0DATA_[3]/GPIO176
PCMADR[7]/GPIO135
TS0DATA_[4]/GPIO177
PCMADR[8]/GPIO129
TS0DATA_[5]/GPIO178
PCMADR[9]/GPIO127
TS0DATA_[6]/GPIO179
PCMADR[10]/GPIO123
TS0DATA_[7]/GPIO180
PCMADR[11]/GPIO125
TS0CLK/GPIO183
PCMADR[12]/GPIO134
TS0VALID/GPIO181
PCMADR[13]/GPIO130
TS0SYNC/GPIO182
AH13
FE_DEMOD1_TS_DATA[0]
AG17
FE_DEMOD1_TS_DATA[1]
AJ17
FE_DEMOD1_TS_DATA[2]
AH14
FE_DEMOD1_TS_DATA[3]
AG14
FE_DEMOD1_TS_DATA[4]
AG16
FE_DEMOD1_TS_DATA[5]
AG15
FE_DEMOD1_TS_DATA[6]
AH15
FE_DEMOD1_TS_DATA[7]
AJ15
FE_DEMOD1_TS_CLK
AH17
FE_DEMOD1_TS_VAL
AH16
FE_DEMOD1_TS_SYNC
AJ26
TS2CLK/GPIO210
TS2SYNC/GPIO209
AG26
AH26
AG25
TS2VALID/GPIO208
Close to MSTAR
PCMRST/GPIO148
R140
AL19
100
C118
IF_P
0.1uF
OPT
PCMREG/GPIO142
CAM_WAIT_N
AL7
PCMIOWR/GPIO128
VIFP
PCMWAIT/GPIO138
VIFM
DTV_IF
C122
AM7
R141
100
C119
IF_N
0.1uF
OPT
C123
33pF
OPT
C126
33pF
AK7
E13
LED0
F13
LED1
US
F11
KR
AG23
EMMC_RST
HP_DET
AH23
AJJA
R123BIT8_0
10K
IF_AGC
AK24
AV1_CVBS_DET
SC_DET
EMMC_RSTN/GPIO204
AK23
EMMC_CMD
EMMC_CMD/GPIO206
AL24
EMMC_CLK
EMMC_DATA[0-7]
EMMC_DATA[1] AL26
EMMC_DATA[2] AG24
EMMC_DATA[6] AK26
TCON3/GPIO158
J5
TCON4/GPIO159
GPIO_PM0/GPIO10
SPI1_CK/GPIO104
GPIO_PM2/GPIO12
VSYNC_LIKE/GPIO103
GPIO_PM3/GPIO13
SPI1_DI/GPIO105
GPIO_PM4/GPIO14
GPIO_PM8/GPIO18
GPIO81/SCK0
GPIO_PM9/GPIO19
GPIO82/SDA0
GPIO_PM13/GPIO23
DDCR_CK/GPIO52
GPIO_PM17/GPIO27
DDCR_DA/GPIO51
GPIO_PM18/GPIO28
COMP1_DET
N6
R190
L_DIM_EN
0
N5
J6
PCM_5V_CTL
R175
22
5V_DET_HDMI_2
R9531_RESET
L5
L6
North.AM
T/C
T/C
01
T2/C/S2/ATV_EXT
10
T2/C
ATV_INT
DTV_EXT
Default
R143
0
IF_AGC
GPIO85/SCK5
+3.3V_NORMAL
GPIO86/SDA5
GPIO89/SCK2
P5
GPIO_PM1/GPIO11
GPIO_PM11/GPIO21
VID0/GPIO48
Jtag I/F
For Main
/USB_OCD1
P6
USB_CTL1
URSA_RESET_SoC
K6
K5
SIL9617_RESET
GPIO_PM12/GPIO22
C102
0.1uF
JTAG
VID1/GPIO49
P100
LED0/GPIO29
12505WS-10A00
JTAG
LED1/GPIO30
BR
ATSC_PIP
ATSC_PIP
T2/C_PIP
ATV_SOC
ATV_SOC
T2/C
ATV_EXT
ATV_EXT
R5
1
TRST_N0
2
TDI0
3
TDO0
4
TMS0
5
TCK0
6
SOC_RESET
G7
JP
ATV_INT
DTV_INT
Default
8
9
10
URSA9 VIDEO/OSD LOCKn
11
T2/C/S2/AT
T2/C/S2
Low
BIT4
BIT5
High
Vx1 Division 2-Division
Resolution
Non-Division
FHD
UHD
* BIT4: LM14 TX Division OPT
(LM14+URSA9: Non Division)
Low
BIT6
MODEL
BIT7
Reserved
BIT8
Reserved
RS232C_Debug
LOCKAn_Video
High
LM14+URSA9 LM14 ONLY
R191
11
I2C PULL UP
33
33
I2C_SDA_MICOM
I2C_SCL_MICOM
+3.3V_TUNER
MSTAR_DEBUG_OLD
P101
UART_4PIN_WAFER
12505WS-04A00
12507WS-04L
R137
R138
I2C_SDA_MICOM_SOC
GPIO PULL UP
I2C_SCL_MICOM_SOC
+3.3V_LNA_TU
+3.3V_NORMAL
+3.3V_NORMAL
P102
4
SOC_TX
I2C_SDA1
10K
R152
10K
10K
R151
10K
10K
R150
AMP_RESET_N
I2C for NVRAM
/USB_OCD2
USB_CTL2
TCON_I2C_EN
I2C_SCL1
I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC
I2C_SDA4
I2C_SCL4
10K
RF_SWITCH_CTL
I2C for R9531AN
I2C_SCL6
3
OPT
10K
/TU_RESET2
I2C for Main Amp & LCD Module
/USB_OCD3
USB_CTL3
M_RFModule_RESET
E
I2C for URSA9 (URSA9 Only)
PCM_5V_CTL
B
I2C_SDA5
I2C_SCL5
R139
LD101
SML-512UW
VBY1_LOCK_LED
I2C_SCL7
I2C_SDA6
R172
I2C_SDA7
22
SOC_RX
220
3
+3.3V_NORMAL
VBY1_LOCK_LED
VBY1_LOCK_LED
2
3
LOCKAn_OSD
LOCKAn_OSD
/TU_RESET1
R192
2
2
I2C for SIL9617
I2C_SCL8
R171
I2C_SDA8
R149
R186
1.8K
R184
1.8K
R185
1.8K
R132
1.8K
R183
1.8K
R131
1.8K
R136
1.8K
R135
1.8K
R134
1.8K
R133
1.8K
R130
1.8K
R129
1.8K
R128
1.8K
R127
1.8K
R148
1.8K
R147
1.8K
1
5
Q100
MMBT3906(NXP)
VBY1_LOCK_LED
C
1
5
E
B
P103
4
LOCKAn_Video
+3.3V_NORMAL
+3.5V_ST
12507WS-04L
1
C125
0.1uF
R142
10K
NAND_DQS/GPIO203
PCM2_CD/GPIO116
1K
R101
00
+3.3V_NORMAL
L100
BLM18PG121SN1D
GPIO84/SDA4
WOL/GPIO50
KR
USB_CTL3
R146
300
OPT
NAND_CE1Z/GPIO196
AJ24
TEST
CN/HK
ANALOG SIF
Close to MSTAR
/USB_OCD3
5V_DET_HDMI_3
R9531_FLASH_WP
L4
TU_SIF
C124
1000pF
OPT
C127
0.047uF
25V
AV_LINK
TW/COL
47
NAND_RBZ/GPIO202
AH24
HDMI_MUX_SEL
AK6
47
0.1uF R145
NAND_WEZ/GPIO199
EMMC_DATA[0] AK25
EMMC_DATA[7] AH25
TCON_I2C_EN
AL5
0.1uF R144
C121
NAND_REZ/GPIO198
EMMC_DATA[3] AL25
5V_DET_HDMI_1
K4
TGPIO3/GPIO172
C120
USB_CTL2
NAND_CLE/GPIO197
EMMC_DATA[4] AM25
P4
TGPIO2/GPIO171
NAND_WPZ/GPIO200
/USB_OCD2
NAND_CEZ/GPIO195
EMMC_DATA[5] AM26
R6
NAND_ALE/GPIO201
AL8
GPIO83/SCK4
JP
AJJA
TGPIO0/GPIO169
TGPIO1/GPIO170
CI
EU/CIS
AM8
EMMC_CLK/GPIO205
TCON2/GPIO157
BR
EU
AM5
SIL9617_INT
AH22
7
R121BIT7_0
10K
TPI_DATA[7]
AG19
PCMCD/GPIO149
AJ11
EB_BE_N0
AJ21
PCMWEN/GPIO132
AK20
CAM_REG_N
TPI_DATA[6]
PCMCEN/GPIO122
AL18
BIT8
BIT6_0
R119
10K
TS0DATA_[1]/GPIO174
PCMIORD/GPIO126
AH12
PCM_RESET
AG21
22
TW/COL
10
BIT5_0
R117
10K
PCMADR[4]/GPIO139
PCMOEN/GPIO124
AK16
CAM_CD1_N
D5
TPI_DATA[5]
R173
LD100
SML-512UW
VBY1_LOCK_LED
00
JP
ATSC
BIT7
BIT4_0
R115
10K
TS0DATA_[0]/GPIO173
PCMIRQA/GPIO133
AK18
/PCM_CE1
TPI_DATA[4]
AH18
FE_DEMOD1_TS_DATA[0-7]
PCMADR[3]/GPIO140
TS2DATA_[0]/GPIO207
AJ14
TPI_DATA[3]
AH21
220
DVB
M_RFModule_RESET
BIT3_0
R111
10K
TS1SYNC/GPIO185
AG20
TPI_DATA[0-7]
R174
BIT(0/1)
BIT6
BIT2_0
R109
10K
PCMADR[1]/GPIO143
TPI_DATA[2]
VBY1_LOCK_LED
VBY1_LOCK_LED
BIT5
R107BIT1_0
10K
TS1VALID/GPIO186
PCMADR[2]/GPIO141
AG10
EB_OE_N
TCON1/GPIO156
E12
VID1
BIT0_0
R103
10K
TS1DATA_[7]/GPIO187
PCMADR[0]/GPIO144
AL17
HTPDAn_OSD
R126
10K
PCM2_RESET/GPIO115
GPIO90/SDA2
VID0
BIT4
5
PCMDATA[7]/GPIO121
PCMADR[14]/GPIO131
TCON0/GPIO155
BIT3
DDCA_DA
TS1DATA_[6]/GPIO188
LOCKAn_OSD
AG22
GPIO66
GPIO_PM5/GPIO15
4
TS1DATA_[5]/GPIO189
PCMDATA[6]/GPIO120
10K
BIT7_1
R122
10K
BIT6_1
R120
10K
I2C_SCL_MICOM_SOC
I2C_SDA_MICOM_SOC
DDCA_CK
PCMDATA[5]/GPIO119
TPI_DATA[1]
AJ20
AL6
GPIO_PM7/GPIO17
MSTAR_DEBUG_NEW
TS1DATA_[4]/GPIO190
SIFP
Don’t use! LM14+URSA9: GPIO AH27/AJ27 U4
Mstart Debug
TS1DATA_[3]/GPIO191
PCMDATA[4]/GPIO118
TPI_DATA[0]
AH19
10K
LM14 HW Option
BIT5_1
R118
10K
EB_ADDR[9]
HTPDAn_Video
HTPDAn_Video
F5
TX2/GPIO62
TS1DATA_[2]/GPIO192
PCMDATA[3]/GPIO117
TS1CLK/GPIO184
AL15
EB_BE_N1
AG29
BIT1
R188
10K
OPT
BIT4_1
R116
10K
AK19
EB_ADDR[5]
AK27
PCMDATA[2]/GPIO147
AJ18
SIFM
+3.3V_NORMAL
BIT3_1
R112
10K
AL20
EB_ADDR[4]
TXVBY1_3N
R125
10K
B4
/TU_RESET1
BIT0
BIT2_1
R110
10K
EB_ADDR[3]
AK31
AL28
TS1DATA_[1]/GPIO193
AM23
AK32
AM28
TS1DATA_[0]/GPIO194
PCMDATA[1]/GPIO146
EB_ADDR[0-14]
AJ30
TX1/GPIO60
PCM2_WAIT/GPIO114
BIT1_1
R108
10K
AH11
EB_DATA[4]
TXVBY1_7P
PCMDATA[0]/GPIO145
RX5/GPIO88
/TU_RESET2
BIT0_1
R104
10K
EB_DATA[3]
TXVBY1_7N
A4P
D6
AK21
AG31
E6
SOC_TX
SOC_RX
AK22
EB_DATA[2]
R160
4.7K
OPT
4.7K
R164
ACKM/VBY0N
R166
R162
R158
4.7K
OPT
4.7K
LED0
AL21
EB_DATA[1]
R159
4.7K
R163
C5
SPI_DI
EB_DATA[0]
AG32
B4P/VBY4P
A5
LED1
Value
4’b1000
4’b1001
4’b1010
4’b1011
4’b1100
4’b0000
4’b0001
4’b0011
AF31
Place capacitor
Close to the wafer
R165
R161
R157
OPT
4.7K
4.7K
SAR5
AF32
10K
CHIP CONFIG
BCKM/VBY6P
H6
V-BY-ONE
MSB/LSB swap
AF30
10K
33
E11
RF_SWITCH_CTL
AMP_RESET_N
R169
R114
F9
PWM_DIM2
I2C_SCL1
R170
SDA
33
1K
R106 JTAG
R113
10K
5
SCL
OPT
10K
4
6
R153
A0’h
R154
GND
3
1K
R105 JTAG
A2
IC100
LGE4331
EB_DATA[0-7]
WP
1K
R102 JTAG
7
IC100
LGE4331
JTAG
2
Write Protection
- Low : Normal Operation
- High : Write Protection
VCC
1K
R100
8
R176
10K
A1
1
R177
47K
A0
I2C for tuner
Q101
MMBT3906(NXP)
VBY1_LOCK_LED
C
I2C_SDA2
I2C_SCL2
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
I2C for tuner&LNB
UB83
LM14 SYSTEM
2013-10-28
01
LGE Internal Use Only
IC100
LGE4331
IC100
LGE4331
+1.1V_VDDC
GND_41
VDDC_CPU_12
GND_42
VDDC_CPU_13
GND_43
VDDC_CPU_14
GND_44
VDDC_CPU_15
GND_45
VDDC_CPU_16
GND_46
VDDC_CPU_17
GND_47
VDDC_CPU_18
GND_48
VDDC_CPU_19
GND_49
GND_50
L7
DVDD_NODIE
C210
1uF
25V
GND_51
GND_52
GND_53
Y19
VSENSE
+1.1V_DVDD_DDR
GND_54
GND_55
GND_56
GND_57
N19
N20
P19
P20
DVDD_DDR_1
GND_58
DVDD_DDR_2
GND_59
DVDD_DDR_3
GND_60
DVDD_DDR_4
GND_61
GND_62
+3.3V_AVDD33
GND_63
GND_64
GND_65
P7
R7
U7
V7
+3.3V_AVDD_AU33
W7
AA7
AB7
+3.3V_AVDD_DMPLL
AF7
AE7
AF10
AVDD_NODIE
GND_66
AVDDP3P_ETH
GND_67
AVDDP3P_USB
GND_68
AVDDP3P_DVI_1
GND_69
AVDDP3P_DVI_2
GND_70
AVDDP3P_DADC
GND_71
AVDDP3P_ADC
GND_72
AVDD_AU33
GND_73
AVDD_EAR33
GND_74
AVDD_DMPLL
GND_75
GND_76
+3.3V_VDDP33
GND_77
GND_78
GND_79
AF15
AF14
AE14
AF12
AVDD_MOD
GND_80
AVDD_PLL
GND_81
AVDD_LPLL
GND_82
VDDP_1
GND_83
DVDD18_EMMC
GND_84
GND_85
+3.3V_VDDP33
GND_86
AF17
AF18
VDDP_3318_A
GND_87
VDDP_2
GND_88
GND_89
VDDC15_M0
GND_90
GND_91
L19
L20
L21
M19
M20
M21
AVDD_DDR0_1
GND_92
AVDD_DDR0_2
GND_93
AVDD_DDR0_3
GND_94
AVDD_DDR0_4
GND_95
AVDD_DDR0_5
GND_96
AVDD_DDR0_6
GND_97
GND_98
L22
M22
N21
N22
P21
P22
AVDD_DDR1_1
GND_99
AVDD_DDR1_2
GND_100
AVDD_DDR1_3
GND_101
AVDD_DDR1_4
GND_102
AVDD_DDR1_5
GND_103
AVDD_DDR1_6
GND_104
AVDD5V_MHL
GND_105
GND_106
AF6
AVDD_HDMI_5V_PC
GND_107
GND_108
GND_109
D3
VDDC15_M0
GND_EFUSE
GND_110
GND_111
GND_112
0.22uF
0.1uF
0.1uF
C200
C201
GND_114
A11
0.22uF
C212
0.22uF
C202
0.1uF
0.1uF
C203
C204
0.22uF
C213
0.22uF
C205
0.22uF
C214
0.22uF
GND_113
C211
B11
A13
B13
AVDD04_DDR_A_1
AVDD04_DDR_A_2
GND_116
AVDD11_DDR_A_1
GND_117
AVDD11_DDR_A_2
GND_118
GND_119
GND_120
AB31
C206
AB32
AD31
AD32
AVDD04_DDR_B_1
GND_121
AVDD04_DDR_B_2
GND_122
AVDD11_DDR_B_1
GND_123
AVDD11_DDR_B_2
0.22uF
GND_126
M17
0.22uF
C215
M18
L17
0.22uF
C216
0.22uF
C217
L18
AVDD04_DDR_A_3
GND_127
AVDD04_DDR_A_4
GND_128
AVDD11_DDR_A_3
GND_129
AVDD11_DDR_A_4
GND_130
GND_131
GND_132
R22
0.22uF
C218
T22
R21
0.22uF
0.22uF
C219
T21
C220
+1.1V_AVDDL_MOD
AVDD04_DDR_B_3
AE30
0.1uF
C209
GND_133
AVDD04_DDR_B_4
GND_134
AVDD11_DDR_B_3
GND_135
AVDD11_DDR_B_4
GND_136
GND_137
GND_138
AE31
C208
GND_124
GND_125
C207
0.1uF
GND_115
AVDDL_MOD_3
GND_139
AVDDL_MOD_4
GND_140
G14
R19
G15
R20
G16
R23
G17
R24
G18
G19
R25
G20
R26
G22
T7
G23
T8
G24
T9
G25
T12
G26
T13
G27
T14
G30
T15
H3
H7
T16
H8
T17
H9
T18
H10
T19
H11
T20
H12
T23
H13
T24
H14
H15
T25
T26
H16
H17
U8
H18
U9
H19
U12
H20
U13
H21
U14
H22
U15
H23
U16
H24
U17
H25
U18
H26
H27
U19
J7
U20
J8
U21
J9
U22
J10
U23
J11
U24
J12
U25
J13
J14
U26
U29
J15
J16
J17
U32
V8
J18
V9
J19
V12
J20
V13
J21
V14
J22
V15
J23
J24
V16
V17
J25
J26
V18
K7
V19
K8
V20
K9
V21
K12
V22
K13
V23
K14
V24
K15
V25
K16
V26
K18
K19
W8
K21
W9
K23
W10
K24
W11
K25
W12
K26
W13
L8
W14
L9
W15
L12
W16
L13
L14
W17
L15
W18
L16
W19
L24
W22
L25
W23
L26
W24
L29
W25
L32
W26
M7
Y7
M8
M9
Y8
M14
Y9
M15
Y10
M16
Y11
M23
Y12
M24
Y13
M25
Y14
M26
Y15
N7
Y16
N8
N9
Y17
N10
Y18
N11
Y25
N12
Y26
N13
Y29
N14
Y32
AA8
AA9
AA10
GND_336
GND_207
GND_337
GND_208
GND_338
GND_209
GND_339
GND_210
GND_340
GND_211
GND_341
GND_212
GND_342
GND_213
GND_343
GND_214
GND_344
GND_215
GND_345
GND_216
GND_346
GND_217
GND_347
GND_218
GND_348
GND_219
GND_349
GND_220
GND_350
GND_221
GND_351
GND_222
GND_352
GND_223
GND_353
GND_224
GND_354
GND_225
GND_355
GND_226
GND_356
GND_227
GND_357
GND_228
GND_358
GND_229
GND_359
GND_230
GND_360
GND_231
GND_361
GND_232
GND_362
GND_233
GND_363
GND_234
GND_364
GND_235
GND_365
GND_236
GND_366
GND_237
GND_367
GND_238
GND_368
GND_239
GND_369
GND_240
GND_370
GND_241
GND_371
GND_242
GND_372
GND_243
GND_373
GND_244
GND_374
GND_245
GND_375
GND_246
GND_376
GND_247
GND_377
GND_248
GND_378
GND_249
GND_379
GND_250
GND_380
GND_251
GND_381
GND_252
GND_382
GND_253
GND_383
GND_254
GND_384
GND_255
GND_385
GND_256
GND_386
GND_257
GND_387
GND_258
GND_388
GND_259
GND_389
GND_260
GND_390
GND_261
GND_391
GND_262
GND_392
GND_263
GND_393
GND_264
GND_394
GND_265
GND_395
GND_266
GND_396
GND_267
GND_397
GND_268
GND_398
GND_269
GND_399
0.1uF
GND_335
GND_206
0.1uF
GND_334
GND_205
C283
GND_204
C282
GND_333
0.1uF
GND_203
0.1uF
GND_332
C281
GND_202
C280
GND_331
0.1uF
GND_330
GND_201
0.1uF
GND_329
GND_200
C279
GND_199
C278
GND_328
0.1uF
GND_327
GND_198
0.1uF
GND_197
C275
GND_326
C277
GND_325
GND_196
0.1uF
GND_195
C276
GND_324
0.1uF
GND_194
0.1uF
GND_323
0.1uF
GND_322
GND_193
C273
GND_321
GND_192
C274
GND_320
GND_191
0.1uF
GND_319
GND_190
C270
GND_189
0.1uF
GND_318
0.1uF
GND_317
GND_188
C271
GND_316
GND_187
0.1uF
GND_186
C266
GND_315
C267
GND_314
GND_185
0.1uF
GND_313
GND_184
C262
GND_183
0.1uF
GND_312
0.1uF
GND_311
GND_182
C263
GND_181
0.1uF
GND_310
C258
GND_180
C259
GND_309
0.1uF
GND_308
GND_179
C254
GND_178
0.1uF
GND_307
0.1uF
GND_306
GND_177
C248
GND_176
0.1uF
GND_305
0.1uF
GND_175
AC18
AC19
AC20
AC25
AC26
AC27
AC28
AC29
+3.3V_Bypass Cap
AC30
AC31
AD7
+3.3V_AVDD_DMPLL
+3.3V_NORMAL
AD8
AD9
AD10
L206
BLM18PG121SN1D
AD11
AD12
AD13
2A
AD14
AD15
C237
10uF
10V
C222
10uF
10V
AD16
AD17
C250 C253
0.1uF 0.1uF
AD18
AD19
AD20
AD21
+3.3V_AVDD33
AD22
L203
BLM18PG121SN1D
AD23
AD24
AD25
AD26
2A
AD27
AD28
AD29
AD30
AE8
AE9
AE10
AE11
+3.3V_AVDD_AU33
AE12
AE13
L204
BLM18PG121SN1D
AE15
AE16
AE17
2A
AE18
AE19
AE20
AE21
AE22
AE23
AE24
+3.3V_VDDP33
AE25
AE26
L205
BLM18PG121SN1D
AE27
AE28
AE29
2A
AF1
C240
10uF
10V
AF2
AF8
AF9
AF13
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AG1
GND JIG POINT
AG2
AG3
+1.5V_Bypass Cap
AG7
AG8
AG9
AG27
AH3
AH4
+1.5V_DDR
JP205
VDDC_CPU_11
R18
GND_304
JP204
AC24
GND_40
G13
GND_303
GND_174
AC17
JP203
AC23
GND_39
VDDC_CPU_10
R17
GND_173
AC16
JP202
AC22
VDDC_CPU_9
G12
GND_302
0.1uF
AC21
GND_38
R16
GND_172
AC14
0.1uF
AB24
VDDC_CPU_8
G11
GND_301
C272
AB23
GND_37
GND_300
GND_171
AC13
C268
AB22
GND_36
VDDC_CPU_7
R15
GND_170
AC12
0.1uF
AB21
VDDC_CPU_6
G10
GND_299
0.1uF
AB20
GND_35
R14
GND_298
GND_169
2A
C269
AA24
VDDC_CPU_5
G9
GND_297
GND_168
C229
10uF
10V
0.1uF
AA23
GND_34
R13
G8
GND_167
AC9
C265
AA22
VDDC_CPU_4
F28
R12
GND_296
C284
10uF
10V
AC8
0.1uF
AA21
GND_33
R11
F27
GND_166
4A
AC7
C264
AA20
VDDC_CPU_3
R10
F26
GND_295
C260
Y24
GND_32
R9
F25
GND_294
GND_165
0.1uF
Y23
VDDC_CPU_2
F24
GND_293
GND_164
0.1uF
Y22
GND_31
GND_163
C261
GND_30
VDDC_CPU_1
F23
R8
AB30
C257
Y21
P32
L207
BLM18PG121SN1D
AB29
0.1uF
GND_29
Y20
P29
F21
GND_292
L202
BLM18SG700TN1D
AB28
C256
+1.1V_VDDC_CPU
E31
GND_162
AB27
C255
GND_28
E30
GND_291
0.1uF
GND_27
GND_290
GND_161
C252
GND_26
P26
GND_289
GND_160
+1.1V_VDDC_CPU
0.1uF
GND_25
AVDDL_SSUSB_2
E29
GND_159
+1.1V_DVDD_DDR
+1.15V_CPU
AB26
0.1uF
AVDDL_SSUSB_1
P25
AB25
C249
M13
P24
E1
AB19
0.1uF
M12
P23
D32
AB18
0.1uF
GND_24
D31
GND_288
C251
GND_23
GND_287
GND_158
AB17
C244
GND_22
AVDDL_MOD_2
P18
GND_157
AB14
0.1uF
AVDDL_MOD_1
D27
GND_286
4A
C245
W20
P17
GND_156
AB13
0.1uF
GND_21
W21
D24
GND_285
C246
GND_20
P16
GND_284
GND_155
VDDC15_M0
AH5
AH6
AH7
AH8
AH9
AH30
AJ6
L200
BLM18PG121SN1D
0.1uF
AVDDV_DVI
D20
GND_283
GND_154
C247
GND_19
P15
GND_282
GND_153
C228
10uF
10V
C242
GND_18
VDDC_19
D17
GND_152
AB12
C243
VDDC_16
C32
P14
C221
10uF
10V
AB9
0.1uF
GND_17
P13
5A
AB8
C238
VDDC_13
C31
GND_281
AA26
0.1uF
GND_16
P12
C14
GND_151
AA25
C239
VDDC_18
C13
GND_280
0.1uF
GND_15
P11
GND_279
GND_150
C235
GND_14
VDDC_17
C12
GND_149
AA19
C232
GND_13
VDDC_15
P10
GND_278
C241
AB16
GND_12
VDDC_14
C11
GND_277
GND_148
+1.1V_AVDDL_MOD
L208
BLM18SG700TN1D
1uF
AC15
+1.1V_AVDDL_MOD
VDDC_12
P9
GND_276
GND_147
L201
MLB-201209-0120P-N2
AA18
0.1uF
AB15
GND_11
C3
GND_146
+1.1V_VDDC
+1.1V_VDDC
AA17
C234
AA15
VDDC_11
P8
+1.1V_CORE
4.7uF
AC11
GND_10
N26
B31
AA16
C236
+1.1V_DVDD_DDR
GND_9
VDDC_10
N25
B14
GND_275
AA14
C233
AC10
VDDC_9
B12
GND_145
+1.1V_Bypass Cap
AA12
0.1uF
AB11
GND_8
GND_274
0.1uF
AB10
GND_7
VDDC_8
N24
GND_273
GND_144
C231
V11
GND_6
VDDC_7
N23
A29
GND_143
C230
V10
VDDC_6
A26
GND_272
0.1uF
U11
GND_5
N18
A23
GND_271
GND_142
0.1uF
U10
GND_4
VDDC_5
A20
AA11
GND_141
C227
T11
VDDC_4
N17
0.1uF
T10
GND_3
N16
A17
C226
M11
VDDC_3
A14
C225
M10
GND_2
0.1uF
L11
GND_1
VDDC_2
0.1uF
L10
VDDC_1
C224
K11
C223
N15
K10
AJ7
AJ8
AJ23
AK5
5V_HDMI_3
AVDD5V_MHL
AK8
AK29
AL2
AL3
R200
10
AL4
AL23
AM14
GND_270
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
UB83
LM14 POWER
2013-10-28
02
11/05/31
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Clock for MSD808KWD
R336
100
HP_LOUT
4
3
10pF
C331
1M
GND_2
X-TAL_2
OPT
OPT
22K
R334
HP_ROUT_MAIN
C334
0.01uF
XIN_MAIN
R324
GND_1
R335
100
HP_ROUT
1
2
C330
24MHz
X300
10pF
X-TAL_1
MAIN Clock(24Mhz)
OPT
22K
R333
HP_LOUT_MAIN
OPT C335
0.01uF
XOUT_MAIN
System Clock for Analog block(24Mhz)
Close to Main soc
HDMI Input from URSA9
IC100
LGE4331
IC100
LGE4331
V2
HDMI_RX0-
W3
HDMI_RX0+
W2
HDMI_RX1-
Y3
HDMI_RX1+
Y2
HDMI_RX2-
Y1
HDMI_RX2+
V3
HDMI_CLK-
V1
HDMI_CLK+
HDMI_TX_DDC_CLK
HDMI_TX_DDC_SDA
R300
22
AC4
R301
22
AE4
AD5
RXA0N
RXA0P
LINE_IN_0L
RXA1P
LINE_IN_0R
RXA2N
LINE_IN_2L
RXA2P
LINE_IN_2R
T2
U3
U2
U1
R3
R1
AC6
I2C_SCL8
AB4
I2C_SDA8
AC5
AJ1
2.2uF
C302
AK3
2.2uF
C303
AK1
2.2uF
C304
COMP1/AV1/DVI_R_IN
SC_R_IN
SC_B
AH2
DDCDA_CK/GPIO35
LINE_OUT_0L
L3
L2
L1
J3
J1
Y4
Y5
AA5
DDCDA_DA/GPIO36
LINE_OUT_0R
HOTPLUGA/GPIO31
EAR_OUT_L
AJ4
AJ5
EAR_OUT_R
N2
P3
P2
P1
M3
M1
AA6
AB6
AB5
0.047uF
C316
AC2
33
68
0.047uF
C317
C318
AC3
0.047uF
R315
33
0.047uF
C319
AB3
R316
68
0.047uF
C320
AA1
R317
33
0.047uF
C321
AA3
C322
AA2
AD6
HP_LOUT
R318
68
0.047uF
C323 AF3
HP_ROUT
R319
33
68
0.047uF
0.047uF
R321
33
0.047uF
C324 AE2
C325 AE3
C326 AD2
R322
68
0.047uF
R323
33
0.047uF
COMP1_Pr
RXB0P
R320
COMP1_Y
RXB1N
RXB1P
Y6
HDMI_ARC
ARC0
AB2
AE5
SC_FB
RXB0N
COMP1_Pb
1000pF
RXB2N
C327 AD3
C328 AC1
C329 AD1
AM13
RIN0M
TN
RIN0P
TP
GIN0M
RN
GIN0P
RP
RXBCKN
AUVAG
DDCDB_CK/GPIO37
AUVRM
C332
10uF
10V
AK4
DDCDB_DA/GPIO38
SOGIN0
ET_TX_CLK/GPIO76
VSYNC0
ET_COL/GPIO72
ET_MDC/GPIO78
RIN1M
ET_TX_EN/GPIO75
RIN1P
ET_TXD[0]/GPIO74
GIN1M
ET_TXD[1]/GPIO73
GIN1P
ET_RXD[0]/GPIO77
BIN1M
ET_RXD[1]/GPIO80
BIN1P
ET_MDIO/GPIO79
AL12
AL11
AK11
AM10
AK10
AL10
H2
SOC_RESET
AM3
XIN_MAIN
AM4
XOUT_MAIN
XOUT
IRIN
B10
I2S_IN_BCK/GPIO92
I2S_IN_SD/GPIO93
RXC2N
I2S_IN_WS/GPIO91
RXC2P
C9
B9
A7
I2S_OUT_BCK/GPIO98
I2S_OUT_MCK/GPIO97
DDCDC_CK/GPIO39
I2S_OUT_WS/GPIO96
DDCDC_DA/GPIO40
I2S_OUT_SD/GPIO99
HOTPLUGC/GPIO33
I2S_OUT_SD1/GPIO100
I2S_OUT_SD2/GPIO101
C7
A8
G2
USB0_DM
R304
22
R305
22
B8
R306
22
AUD_SCK
R307
22
AUD_LRCK
B7
C4
R308 68
0.047uF
AUD_LRCH
C309
22pF
USB0_DP
AE6
VCOM
TU_CVBS
SC_CVBS_IN
C307
22pF
C312
AUD_MASTER_CLK
C8
R309
33
C313
0.047uF AF4
R310
33
C314
0.047uF AF5
R311
AV1_CVBS_IN
33
C315
0.047uF AG5
C308
22pF
RXD1N
USB1_DM
USB1_DP
CVBS0
USB2_DM
CVBS1
USB2_DP
CVBS2
USB3_DM
C310
22pF
C311
1000pF
OPT
50V
USB_SSTXN
RXD2N
USB_DM
RXD2P
DTV/MNT_V_OUT
RXDCKP
R325
2.2
R326
2.2
AL14
AK14
F2
F3
R329
2.2
USB_DM3
R327
2.2
USB_DP3
R328
2.2
WIFI_DM
WIFI_DP
R330
2.2
USB_DM2
USB_DP2
E3
F1
B2
USB_SSTXP
RXD1P
RXDCKN
G3
USB3_DP
I2S_OUT_SD3/GPIO102
RXD0P
USB_DP
AG6
CVBSOUT1
USB_SSRXP
C2
C1
D2
D1
R332
2.2
R331
2.2
USB_DM1
USB_DP1
E2
USB_SSRXN
DDCDD_CK/GPIO41
DDCDD_DA/GPIO42
N4
GPIO_PM14/GPIO24
GPIO_PM15/GPIO25
CEC/GPIO5
AK9
H1
RXC1P
HOTPLUGD/GPIO34
AL9
HWRESET
1uF
C333
BLM18PG121SN1D
L300
RXC1N
W4
EPHY_RDP
AM11
HSYNC0
XIN
RXC0P
RXD0N
EPHY_RDN
AL13
BIN0P
RXC0N
RXCCKP
EPHY_TDP
AK12
BIN0M
AK2
RXBCKP
RXCCKN
EPHY_TDN
AK13
SOGIN1
RXB2P
M2
N3
68
R314
SC_ID
SCART_Lout
SCART_Rout
AJ3
J2
K2
R312
R313
1000pF
RXACKP
HOTPLUGB/GPIO32
K3
SC_G
SC_L_IN
C305
2.2uF
COMP1/AV1/DVI_L_IN
RXACKN
R2
T3
SC_R
AJ2
RXA1N
GPIO_PM16/GPIO26
M5
M6
MHL_DET_LM14
/MHL_OCP
D10
SPDIF_OUT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
E10
SPDIF_IN/GPIO94
SPDIF_OUT/GPIO95
UB83
LM14 INPUT
2013-10-28
03
LGE Internal Use Only
EAN63053201
EAN63053201
M0_DDR_DQS_N2
F7
F2
F8
H3
H8
G2
H7
VSS_10
DQL4
VSS_11
DQL5
C3
C8
C2
A7
M0_DDR_DQ12
A2
M0_DDR_DQ13
B8
M0_DDR_DQ14
A3
M0_DDR_DQ15
M0_DDR_DQ18
P9
M0_DDR_DQ19
T1
M0_DDR_DQ20
T9
M0_DDR_DQ21
DQL6
M0_DDR_DQ22
DQL7
M0_DDR_DQ23
VSSQ_1
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
M0_DDR_DQ24
D1
M0_DDR_DQ25
D8
M0_DDR_DQ26
E2
M0_DDR_DQ27
E8
F9
H7
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
C3
C8
C2
A7
A2
G1
B8
M0_DDR_DQ30
G9
A3
M0_DDR_DQ31
M1_DDR_DQS1
M1_DDR_DQS_N1
J2
M1_DDR_DM0
J8
M1_DDR_DM1
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
0.1uF
0.1uF
0.1uF
C409
0.1uF
0.1uF
OPT
C4000
10uF
10V
OPT
C4004
1uF
25V
C4011
0.1uF
16V
4th layer
G3
B7
D3
M1_DDR_DQ0
P1
M1_DDR_DQ1
P9
M1_DDR_DQ2
T1
M1_DDR_DQ3
T9
M1_DDR_DQ4
F2
F8
H3
H8
M1_DDR_DQ5
G2
H7
M1_DDR_DQ7
B9
D1
M1_DDR_DQ8
D8
M1_DDR_DQ9
E2
M1_DDR_DQ10
E8
M1_DDR_DQ11
F9
M1_DDR_DQ12
G1
M1_DDR_DQ13
G9
M1_DDR_DQ14
C8
C2
A7
A2
B8
A3
M1_DDR_DQ15
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8
M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15
M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_WEN
M0_DDR_ODT
M0_DDR_CKE
M0_DDR_RESET_N
M0_D_CLK
M0_D_CLKN
M0_DDR_CS1
M0_DDR_CS2
E16
F17
B17
E17
A16
D16
C15
E15
B18
B16
D19
F15
B15
E19
E18
C17
F18
F20
F19
E20
G21
C18
F14
A19
B19
E14
D14
G28
A_DDR3_A0
B_DDR3_A0
A_DDR3_A1
B_DDR3_A1
A_DDR3_A2
B_DDR3_A2
A_DDR3_A3
B_DDR3_A3
A_DDR3_A4
B_DDR3_A4
A_DDR3_A5
B_DDR3_A5
A_DDR3_A6
B_DDR3_A6
A_DDR3_A7
A_DDR3_A8
A_DDR3_A9
B_DDR3_A7
B_DDR3_A8
B_DDR3_A9
A_DDR3_A10
B_DDR3_A10
A_DDR3_A11
B_DDR3_A11
A_DDR3_A12
B_DDR3_A12
A_DDR3_A13
B_DDR3_A13
A_DDR3_A14
B_DDR3_A14
A_DDR3_A15
B_DDR3_A15
A_DDR3_BA0
B_DDR3_BA0
A_DDR3_BA1
A_DDR3_BA2
B_DDR3_BA1
B_DDR3_BA2
A_DDR3_RASZ
B_DDR3_RASZ
A_DDR3_CASZ
B_DDR3_CASZ
A_DDR3_WEZ
B_DDR3_WEZ
A_DDR3_ODT
B_DDR3_ODT
A_DDR3_CKE
B_DDR3_CKE
A_DDR3_RST
B_DDR3_RST
A_DDR3_MCLK
A_DDR3_MCLKZ
B_DDR3_MCLK
B_DDR3_MCLKZ
A_DDR3_CSB1
B_DDR3_CSB1
A_DDR3_CSB2
B_DDR3_CSB2
J31
H29
J27
J30
H28
J32
G31
H32
F30
K30
H30
K29
F31
H31
L28
K28
K31
J28
M27
L27
K27
M28
L31
F32
M32
L30
F29
E32
M1_DDR_A0
M0_DDR_A8
M1_DDR_A2
M0_DDR_A11
M0_DDR_A6
M1_DDR_A4
OPT
OPT
C4005
1uF
25V
C4001
10uF
10V
C4010
0.1uF
16V
4th layer
M1_DDR_A6
M1_DDR_A7
M0_DDR_A4
M0_DDR_A12
M1_DDR_A10
M0_DDR_BA1
M1_DDR_A11
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15
M1_DDR_BA0
M1_DDR_BA1
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DM0
M0_DDR_DQS0
M0_DDR_DQS_N0
B21
B23
C20
B24
C19
C23
C21
B20
A22
B22
R31
A_DDR3_DQ[0]
B_DDR3_DQ[0]
A_DDR3_DQ[1]
B_DDR3_DQ[1]
A_DDR3_DQ[2]
B_DDR3_DQ[2]
A_DDR3_DQ[3]
B_DDR3_DQ[3]
A_DDR3_DQ[4]
B_DDR3_DQ[4]
A_DDR3_DQ[5]
B_DDR3_DQ[5]
A_DDR3_DQ[6]
B_DDR3_DQ[6]
A_DDR3_DQ[7]
M0_DDR_A2
B_DDR3_DQ[7]
A_DDR3_DQM[0]
B_DDR3_DQM[0]
A_DDR3_DQS[0]
B_DDR3_DQS[0]
A_DDR3_DQSB[0]
N30
R30
N31
T30
M31
T31
P31
M30
R32
M1_DDR_ODT
M0_DDR_A3
P30
B_DDR3_DQSB[0]
M0_DDR_DQ9
M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15
M0_DDR_DM1
M0_DDR_DQS1
M0_DDR_DQS_N1
M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23
M0_DDR_DM2
M0_DDR_DQS2
M0_DDR_DQS_N2
M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31
M0_DDR_DM3
M0_DDR_DQS3
M0_DDR_DQS_N3
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
F22
E24
E21
E25
D22
D26
D21
D25
E23
D23
E22
P28
A_DDR3_DQ[8]
A_DDR3_DQ[9]
B_DDR3_DQ[8]
B_DDR3_DQ[9]
A_DDR3_DQ[10]
B_DDR3_DQ[10]
A_DDR3_DQ[11]
B_DDR3_DQ[11]
A_DDR3_DQ[12]
B_DDR3_DQ[12]
A_DDR3_DQ[13]
B_DDR3_DQ[13]
A_DDR3_DQ[14]
B_DDR3_DQ[14]
A_DDR3_DQ[15]
B_DDR3_DQ[15]
A_DDR3_DQM[1]
A_DDR3_DQS[1]
A_DDR3_DQSB[1]
B_DDR3_DQM[1]
B_DDR3_DQS[1]
B28
A25
C28
C24
A28
B26
B25
B27
C26
A_DDR3_DQ[16]
B_DDR3_DQ[16]
A_DDR3_DQ[17]
B_DDR3_DQ[17]
A_DDR3_DQ[18]
B_DDR3_DQ[18]
A_DDR3_DQ[19]
B_DDR3_DQ[19]
A_DDR3_DQ[20]
B_DDR3_DQ[20]
A_DDR3_DQ[21]
B_DDR3_DQ[21]
A_DDR3_DQ[22]
B_DDR3_DQ[22]
A_DDR3_DQ[23]
B_DDR3_DQ[23]
A_DDR3_DQM[2]
A_DDR3_DQS[2]
B_DDR3_DQM[2]
D29
E28
D30
E27
C30
B30
A30
B29
U28
N27
T27
N29
T29
R28
R27
P27
B_DDR3_DQS[2]
V31
Y30
V32
AA30
U31
AA31
V30
U30
W30
W31
B_DDR3_DQSB[2]
V28
A_DDR3_DQ[24]
B_DDR3_DQ[24]
A_DDR3_DQ[25]
B_DDR3_DQ[25]
A_DDR3_DQ[26]
B_DDR3_DQ[26]
A_DDR3_DQ[27]
B_DDR3_DQ[27]
A_DDR3_DQ[28]
B_DDR3_DQ[28]
A_DDR3_DQ[29]
B_DDR3_DQ[29]
A_DDR3_DQ[30]
B_DDR3_DQ[30]
A_DDR3_DQ[31]
B_DDR3_DQ[31]
A_DDR3_DQM[3]
B_DDR3_DQM[3]
A_DDR3_DQS[3]
B_DDR3_DQS[3]
A_DDR3_DQSB[3]
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
M1_D_CLKN
M1_DDR_CS1
M0_DDR_BA0
M1_DDR_CS2
M0_DDR_BA2
M1_DDR_DQ0
M1_DDR_DQ2
M1_DDR_DQ3
M0_DDR_WEN
M1_DDR_DQ4
M0_DDR_CASN
M1_DDR_DQ5
M0_DDR_RASN
M1_DDR_DQ6
M0_DDR_ODT
M1_DDR_DQ7
M1_DDR_DQS_N0
B_DDR3_DQSB[3]
Y27
U27
AA28
W28
AA29
V27
AA27
W27
Y28
W29
RAS
VDDQ_8
CAS
VDDQ_9
T2
RESET
NC_2
M1_DDR_DQS_N3
C7
B7
D3
VSS_1
DQSU
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
F7
M1_DDR_DQ17
F2
M1_DDR_DQ18
P9
F8
M1_DDR_DQ19
T1
M1_DDR_DQ20
T9
M1_DDR_DQ21
VSS_12
DQL7
VSS_6
E3
M1_DDR_DQ16
P1
H3
H8
G2
H7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
VSSQ_1
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
M1_DDR_DQ24
D1
M1_DDR_DQ25
D8
M1_DDR_DQ26
E2
M1_DDR_DQ27
E8
M1_DDR_DQ28
F9
M1_DDR_DQ29
G1
M1_DDR_DQ30
G9
M1_DDR_DQ31
H2
C490
0.1uF
H9
C491
0.1uF
J9
L1
L9
C8
C2
A7
A2
B8
A3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
VSSQ_1
D7
C3
B3
DQL6
DQL7
B1
DQU0
F1
A9
DQSU
E7
M1_DDR_DM3
M9
E9
DQSL
J8
M1
D2
DQSL
M1_DDR_DM2
J2
C9
NC_4
F3
G3
C1
J1
NC_1
E1
G8
M1_DDR_DQ23
M1_DDR_A6
0.1uF
M1_DDR_A1
M1_DDR_A12
M1_DDR_BA1
C428
0.1uF
C429
0.1uF
M1_DDR_RESET_N
M1_DDR_A7
M1_DDR_A9
0.1uF
M1_DDR_A5
C431
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
+1.5V_Bypass Cap
Close to DDR Power Pin
OPT
C4002
10uF
10V
OPT
C4006
1uF
25V
OPT
C4009
0.1uF
16V
4th layer
OPT
OPT
C4003
10uF
10V
C4007
1uF
25V
OPT
C4008
0.1uF
16V
4th layer
C453
0.1uF
C454
0.1uF
C455
0.1uF
C456
0.1uF
C457
0.1uF
C458
0.1uF
C459
0.1uF
0.1uF
C433
0.1uF
M0_DDR_CKE
R405
C460
M1_DDR_A0
R433
M1_DDR_BA0
10K
R422
10K
10K
0.1uF
10K
M0_DDR_RESET_N
AR411
100
1/16W
C432
M1_DDR_CKE
VDDC15_M0
VDDC15_M0
R418
M1_DDR_A3
0.1uF
M1_DDR_RESET_N
C461
0.1uF
C462
0.1uF
M1_DDR_BA2
M1_DDR_A15
M1_DDR_A10
C434
0.1uF
C435
0.1uF
C436
0.1uF
C437
0.1uF
M1_DDR_WEN
C463
0.1uF
C464
0.1uF
M1_DDR_ODT
C465
0.1uF
C466
0.1uF
R427
56
1%
C477
0.01uF
50V
C497
0.01uF
50V
R428
56
1%
R413
56
1%
M1_DDR_CASN
M1_DDR_RASN
M1_D_CLK
M0_D_CLK
R412
56
1%
AR412
100
1/16W
M1_D_CLKN
M0_D_CLKN
AR413
100
1/16W
AR406
100
1/16W
M1_DDR_DM0
M1_DDR_DQS3
B3
DQL6
M1_DDR_A11
AR405
100
1/16W
M1_DDR_DQ1
A9
M1_DDR_DQ22
M1_DDR_A14
AR404
100
1/16W
M1_D_CLK
M1_DDR_DQ8
0.1uF
C427
M0_DDR_CKE
M0_D_CLK
M1_DDR_CKE
M1_D_CLKN
M1_D_CLK
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
* DDR_VTT
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15
M1_DDR_DM1
M1_DDR_DQS1
VDDC15_M0
M1_DDR_DQS_N1
+3.3V_NORMAL
IC402
TPS51200DRCR
R401
10K 1%
M1_DDR_DQ16
M1_DDR_DQ17
R402
10K
1%
M1_DDR_DQ18
M1_DDR_DQ19
C421
1000pF
REFIN
VLDOIN
M1_DDR_DQ21
2
M1_DDR_DQ22
M1_DDR_DQ23
DDR_VTT
M1_DDR_DM2
M1_DDR_DQS2
L400
UBW2012-121F
M1_DDR_DQS_N2
C422
22uF
10V
VO
PGND
M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
C414
0.1uF
C417
100uF
[EP]
10
1
M1_DDR_DQ20
VOSNS
D28
E26
N28
Y31
A_DDR3_DQSB[2]
C29
T28
B_DDR3_DQSB[1]
C27
C25
VSS_2
VDDQ_7
NC_3
M1_DDR_A2
M0_DDR_A0
M1_DDR_RESET_N
M1_DDR_DQS0
C426
C430
M0_D_CLKN
M0_DDR_DQ8
VSS_1
ODT
WE
M1_DDR_RESET_N
M1_DDR_DQS_N2
DQSU
L3
M1_DDR_WEN
DQSL
DQSU
K3
M1_DDR_CASN
M1_DDR_DQS2
AR410
100
1/16W
M0_DDR_A10
C22
0.1uF
AR403
100
1/16W
M0_DDR_A5
L9
J3
M1_DDR_RASN
VDDQ_6
M1_DDR_A13
M0_DDR_A7
M1_DDR_CASN
L1
K1
CS
A8
AR409
100
1/16W
M0_DDR_A9
M1_DDR_WEN
J9
VDDQ_5
M1_DDR_A4
M0_DDR_A15
M0_DDR_DQ0
0.1uF
C425
M0_DDR_A13
M1_DDR_RASN
0.1uF
VDDQ_4
AR408
100
1/16W
M0_DDR_RESET_N
M1_DDR_BA2
M1_DDR_CKE
C424
AR402
100
1/16W
M1_DDR_A12
C469
VDDQ_3
CKE
M1_DDR_A8
M0_DDR_A1
M1_DDR_A8
M1_DDR_A9
H9
VDDQ_2
CK
DDR_VTT
AR401
100
1/16W
M1_DDR_A5
0.1uF
CK
L2
M1_DDR_ODT
R9
AR407
100
1/16W
M0_DDR_A14
M1_DDR_A1
M1_DDR_A3
C468
K9
M1_DDR_CS2
9
3
8
4
7
5
6
L401
UBW2012-121F
VIN
PGOOD
C443
4700pF
VDDC15_M0
VDDC15_M0
M1_1_DDR_VREFDQ
M0_1_DDR_VREFDQ
M1_DDR_VREFDQ
M0_DDR_VREFDQ
EN
REFOUT
C442
0.1uF
M1_DDR_DQ27
M1_DDR_DQ28
VDDC15_M0
VDDC15_M0
GND
R410
M0_DDR_A4
C16
H2
NC_4
DDR_VTT
F16
F1
K7
R1
A1
VDDQ_1
J7
M1_D_CLK
M1_D_CLKN
N9
VDD_9
BA1
BA2
M1_DDR_CKE
+1.5V_Bypass Cap
Close to DDR Power Pin
OPT
11
M0_DDR_A3
E9
M3
M1_DDR_BA2
BA0
N1
VDDC15_M0
THERMAL
M0_DDR_A1
NC_2
D7
C3
D2
N8
M1_DDR_BA1
DQSL
E3
F7
C9
J1
NC_1
E7
AR400
100
1/16W
M0_DDR_A0
VDDQ_9
C1
VDD_8
M2
M1_DDR_BA0
K8
VDDC15_M0
IC100
LGE4331
M0_DDR_A2
CAS
C7
M9
+1.5V_Bypass Cap
Close to DDR Power Pin
OPT
VDDQ_8
RESET
M1
B1
DQU0
RAS
F3
M1_DDR_DQ6
D7
VDDQ_7
T2
G8
VSS_12
VSSQ_1
VDDQ_6
ODT
NC_3
DQL6
DQL7
M0_DDR_DQ29
C408
C407
0.1uF
0.1uF
C406
C405
0.1uF
0.1uF
C404
C403
0.1uF
G2
DQL1
VDDQ_5
CS
WE
M1_DDR_RESET_N
VDDC15_M0
C402
0.1uF
H8
M0_DDR_DQ28
VDDC15_M0
C401
H3
VSS_7
B1
+1.5V_Bypass Cap
Close to DDR Power Pin
C400
F8
L3
M1_DDR_WEN
E1
0.1uF
M0_DDR_DQ11
F2
DQL0
0.1uF
M0_DDR_DQ9
M0_DDR_DQ17
P1
VSS_12
D7
M0_DDR_DQ8
M0_DDR_DQ10
F7
K3
M1_DDR_CASN
B3
C439
M0_DDR_DQ7
DQL3
M0_DDR_DQ16
M9
VSS_6
E3
0.1uF
M0_DDR_DQ6
VSS_9
M1
C438
M0_DDR_DQ5
DQL2
VSS_5
0.1uF
M0_DDR_DQ4
VSS_8
DMU
J8
C423
M0_DDR_DQ3
DQL1
VSS_4
0.1uF
M0_DDR_DQ2
VSS_7
M0_DDR_DM3
DML
C420
M0_DDR_DQ1
DQL0
VSS_3
0.1uF
M0_DDR_DQ0
VSS_2
VDDQ_4
A8
VDD_7
C472
0.1uF
C474
1000pF
50V
C479
0.1uF
C483
1000pF
50V
R431
VSS_6
E3
D3
J3
A9
VSS_1
DQSU
VDDQ_3
NC_5
K2
C470
0.1uF
C471
1000pF
50V
1K 1%
VSS_5
M0_DDR_DM2
J2
K1
M1_DDR_RASN
M1_DDR_DQS_N0
DQSU
VDDQ_2
CK
L2
M1_DDR_ODT
DQSL
E7
CK
CKE
M1_DDR_CS1
M1_DDR_DQS0
C7
B7
L9
K9
VDD_6
1%
DMU
M0_DDR_DQS_N3
J9
L1
NC_4
K7
A14
G7
R432
VSS_4
NC_2
E1
G8
0.1uF
VDDQ_1
J7
M1_D_CLK
M1_D_CLKN
M1_DDR_CKE
DQSL
C419
M0_DDR_DM1
DML
M0_DDR_DQS3
B3
C441
A1
VDD_5
1K
D3
RESET
F3
0.1uF
M0_DDR_DM0
A9
H9
0.1uF
J1
NC_1
T2
G3
C440
BA2
VDD_4
A13
R425
VSS_3
VDDQ_9
H2
M1_DDR_BA2
BA1
M1_DDR_A15
VDD_3
A12/BC
1K 1%
VSS_2
CAS
F1
M3
VDD_9
M7
VDD_2
A11
1%
VSS_1
DQSU
VDDQ_8
NC_3
DQSL
DQSU
RAS
WE
M0_DDR_RESET_N
M0_DDR_DQS2
E7
VDDQ_7
M1_DDR_BA1
BA0
M1_DDR_A14
A10/AP
R426
B7
L9
L3
M0_DDR_WEN
DQSL
C7
M0_DDR_DQS1
M0_DDR_DQS_N1
L1
K3
M0_DDR_CASN
ODT
E9
N8
R9
T3
T7
1K
G3
J9
NC_4
J3
M0_DDR_RASN
VDDQ_6
D2
M1_DDR_BA0
R1
N7
M1_DDR_A13
0.1uF
NC_3
K1
M0_DDR_ODT
CS
C9
VDD_8
M2
N9
R7
M1_DDR_A11
M1_DDR_A12
D9
0.1uF
NC_2
L2
M0_DDR_CS2
C1
VDD_7
N1
VDD_1
C489
RESET
F3
M0_DDR_DQS_N0
0.1uF
J1
NC_1
T2
M0_DDR_RESET_N
M0_DDR_DQS0
C411
VDDQ_5
A8
NC_5
K8
A9
0.1uF
WE
H9
0.1uF
VDDQ_4
VDD_6
K2
B2
C488
VDDQ_9
C410
VDDQ_3
CKE
A14
M1_DDR_A10
G7
240
VDDC15_M0
A8
C487
CAS
H2
VDDQ_2
CK
VDD_5
R419
ZQ
A7
0.1uF
VDDQ_8
CK
VDD_4
A13
L8
A6
0.1uF
RAS
F1
K9
M1_DDR_A15
VDD_3
A12/BC
A5
C486
L3
M0_DDR_WEN
VDDQ_7
K7
M7
VDD_2
A11
A4
0.1uF
K3
M0_DDR_CASN
ODT
E9
J7
M0_D_CLK
M0_D_CLKN
M1_DDR_A14
A10/AP
VREFDQ
C485
J3
M0_DDR_RASN
VDDQ_6
A1
VDDQ_1
T7
M8
VREFCA
H1
A3
0.1uF
K1
CS
D2
VDD_9
BA1
BA2
M0_DDR_CKE
R9
T3
A2
C484
VDDQ_5
L2
M0_DDR_CS1
M0_DDR_ODT
C9
R1
N7
M1_DDR_A13
0.1uF
VDDQ_4
C1
M3
M0_DDR_BA2
BA0
N9
R7
M1_DDR_A11
L7
A1
C481
CKE
A8
N8
M0_DDR_BA1
M1_DDR_A10
M1_DDR_A12
M1_DDR_A9
D9
0.1uF
VDDQ_3
VDD_8
M2
M0_DDR_BA0
N1
VDD_1
C480
VDDQ_2
CK
VDD_7
K8
A9
R3
0.1uF
CK
NC_5
K2
T8
M1_DDR_A8
C476
K9
VDD_6
A14
G7
R2
M1_DDR_A7
B2
R416
K7
VDD_5
M1_DDR_A6
VDDC15_M0
A8
A0
1K 1%
VDDQ_1
J7
M0_D_CLK
M0_D_CLKN
M0_DDR_CKE
VDD_4
A13
R8
C475
A1
VDD_3
A12/BC
240
P2
1%
BA2
VDD_2
A11
C418
M0_DDR_BA2
BA1
M7
M0_DDR_A15
A10/AP
L7
R404
ZQ
A7
P8
R417
M3
VDD_9
M0_DDR_A14
0.1uF
M0_DDR_BA1
BA0
T7
M1_DDR_A9
L8
A6
N2
1K
N8
R9
T3
C416
M0_DDR_BA0
R1
N7
M0_DDR_A13
D9
R3
1K 1%
VDD_8
M2
N9
R7
M0_DDR_A11
M0_DDR_A12
R2
T8
M1_DDR_A5
1%
VDD_7
N1
VDD_1
M1_DDR_A8
M1_DDR_A4
A5
R411
NC_5
K8
A9
R8
M1_DDR_A6
M1_DDR_A7
B2
A4
1K
VDD_6
K2
240
VDDC15_M0
A8
P3
M1_DDR_A2
M1_DDR_A3
DDR3 1.5V bypass Cap - Place these caps near Memory
A14
M0_DDR_A10
G7
ZQ
A7
P2
M1_DDR_A5
P7
M1_DDR_A1
H1
VREFDQ
DDR3
4Gbit
(x16)
N3
M1_DDR_A0
VREFCA
0.1uF
VDD_5
A6
R403
M8
DDR3
4Gbit
(x16)
A3
0.1uF
VDD_4
A13
L8
A2
C467
VDD_3
A12/BC
P8
M1_DDR_A4
A5
A1
C452
VDD_2
A11
L7
A4
A0
0.1uF
A10/AP
M0_DDR_A9
D9
N2
0.1uF
VDD_1
0.1uF
M0_DDR_A15
A9
R3
P3
C451
M7
T8
C415
M0_DDR_A14
R2
M0_DDR_A7
P7
M1_DDR_A3
0.1uF
T7
M0_DDR_A6
M0_DDR_A8
B2
VREFDQ
C450
T3
240
VDDC15_M0
A8
N3
M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
H1
A3
0.1uF
N7
R400
ZQ
A7
R8
M8
VREFCA
C449
R7
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
L8
A6
P2
C413
M0_DDR_A10
M0_DDR_A5
A2
0.1uF
L7
M0_DDR_A4
A5
C412
M0_DDR_A9
A4
P8
A1
C448
R3
M0_DDR_A3
VREFDQ
A0
0.1uF
T8
H1
N2
C447
R2
M0_DDR_A8
P3
C446
R8
M0_DDR_A6
M0_DDR_A7
P7
M0_DDR_A1
M0_DDR_A2
A3
DDR3
4Gbit
(x16)
N3
M0_DDR_A0
VREFCA
0.1uF
P2
A2
0.1uF
P8
M0_DDR_A4
M0_DDR_A5
A1
C444
N2
M0_DDR_A3
M8
DDR3
4Gbit
(x16)
A0
EAN63053201
EAN63053201
C445
P3
DDR3 1.5V bypass Cap - Place these caps near Memory
P7
M0_DDR_A2
M1_1_DDR_VREFDQ
IC404
H5TQ4G63AFR-RDC
IC403
H5TQ4G63AFR-RDC
DDR3 1.5V bypass Cap - Place these caps near Memory
N3
M0_DDR_A0
M0_DDR_A1
M1_DDR_VREFDQ
M0_1_DDR_VREFDQ
IC401
H5TQ4G63AFR-RDC
DDR3 1.5V bypass Cap - Place these caps near Memory
M0_DDR_VREFDQ
IC400
H5TQ4G63AFR-RDC
C473
0.1uF
C478
1000pF
50V
Close to REFOUT pin
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31
M1_DDR_DM3
M1_DDR_DQS3
M1_DDR_DQS_N3
UB83
LM14 DDR
2013-10-28
04
LGE Internal Use Only
+12V
L509
MLB-201209-0120P-N2
2
+12V
C521
10uF
25V
OPT
3
EAG63590902
P500
SMAW200-H24S5
C523
0.1uF
25V
C502
0.1uF
16V
PWM_TIN
G+
S1
+12V
UBW2012-121F
1
2
INV CTL
R507
3
4
PDIM#2
R562
3.5V
5
6
GND
7
8
GND
9
10
GND
11
12
12V
12V
13
14
12V
12V
15
16
GND
17
18
24V
UBW2012-121F
24V
19
20
24V
24V
21
22
24V
GND
23
24
GND
C527
10uF
25V
INV_CTL
100
100
S2
C528
10uF
25V
S3
G
1
8
AO4423
7
2
3
6
4
5
PD_+3.5V
R545
0
5%
+3.5V_ST
R555
10K
OPT
IC505
APX803D29
D4
VCC
3
2
POWER_DET
RESET
D3
R531
2K
OPT
R528
2K
OPT
D1
C531
10uF
25V
OPT
C534
0.1uF
25V
1
C547
0.1uF
16V
PD_+12V
R535
1.2K
1%
D2
PWM_DIM2
GND
R518
10K
L507
UBW2012-121F
PANEL_CTL
+24V
C518
0.1uF
50V
L508
UBW2012-121F
C529
10uF
25V
C
Q502
2SC3052
B
Q503-*1
AO4447A
S_1
S_2
E
S_3
G
1
+24V
8
AO4447
7
2
3
6
4
5
PD_20_24V
IC506
D_3
PD_20V
R542-*1
5.6K
1%
PD_UHD_24V
R542-*2
9.1K
1%
D_2
D_1
PD_24V
R542
8.2K
1%
APX803D29
VCC
PD_20V
R543-*1
1.3K
1%
PD_UHD_24V
R543-*2
1.6K
1%
25
+12V
C516
10uF
16V
C533
0.1uF
16V
D_4
3
L504
C515
10uF
16V
not to RESET
at 8kV ESD
R556
0
5%
PD_20_24V
R549
100K
EBK61313102
OPT
C557
0.1uF
16V
OPT
R526
1.8K
3.5V
12V
GND
L503
C505
0.1uF
50V
PWR ON
PDIM#1
3.5V
EBK61313101
R525
10K
OPT
R569
33
Q503
AO4423
0.01uF
50V
R509
1K
R516
0
NON_G+
R561 100
PD_+12V
R534
2.7K
1%
C525
PWM_TOUT
PWM_DIM
R550
100K
PANEL_VCC
G+
R568
33
L502
UBW2012-121F
+3.5V_ST
MLB-201209-0120P-N2
+3.3V_NORMAL
+3.5V_ST
Power_DET
TYP 6000mA
L510
Q500
R500
10K
RL_ON
1
R501
10K
PANEL_POWER
MMBT3906(NXP)
+3.5V_ST
PD_24V
R543
1.5K
1%
2
C548
GND
0.1uF
16V
PD_20_24V
POWER_DET_1
R557 0
RESET
OPT
1
5%
24V-->3.48V
20V-->3.51V
12V-->3.58V
ST_3.5V-->3.5V
C517
10uF
16V
’14 UHD POWER
+12V
Core 1.1V or 1.15V
+12V
DDR +1.5V
L511
+1.15V_CPU
+1.5V_DDR
POWER_ON/OFF2_3
BLM18PG121SN1D
L514
POWER_ON/OFF2_4
BLM18PG121SN1D
VBY1_LOCK_LED
B
EN
EN
R547
10K
R539
120K
1%
R508 22
R514 1.5K
Q501
2SC3052
VBY1_LOCK_LED VBY1_LOCK_LED VBY1_LOCK_LED
+3.3V_NORMAL
8
VID0
0
VREG5
G
5%
S
7
3
6
VIN
VBST
C553
0.1uF
16V
R1
L516
3.6uH
SW
R517
R519
18K
1%
3.6K
1%
R558
16K
1%
C543
1uF
10V
4
3A
5
GND
6
VIN
16V
0.1uF
C526
VBST
L512
3.6uH
SW
SM-8040
4
3A
5
GND
C532
22uF
10V
C530
22uF
10V
C524
3300pF
50V
C522
1uF
10V
R2
Switching freq: 700K
Vout=0.765*(1+R1/R2)=1.516V
R559
5.6K
1%
Switching freq: 700K
7
3
SS
R520
22K
1%
C558
22uF
10V
C545
3300pF
50V
8
2
VREG5
C520
100pF
50V
C555
22uF
10V
1
VFB
SM-8040
Q504
2N7002A
D
2
1%
R2-1.1V
R570
10K
R536
VFB
SS
R540
100K
1%
+1.8V - eMMC 4.51(LG1311-B0)
& Vx1 pull-up
1
R1
R2-1.15V
50V
100pF
C542
C510
22uF
10V
C
C509
0.1uF
16V
C506
22uF
10V
VBY1_LOCK_LED
LD500
+3.5V_ST
C504
0.1uF
16V
[EP]GND
10K
R510
10K
11K
R515
VBY1_LOCK_LED
L505
BLM18PG121SN1D
E
L501
BLM18PG121SN1D
IC507
TPS54327DDAR [EP]GND
R521
10K
EAN61832901
R560
9
+3.3V_NORMAL
ZD503
5V
DVDD18_EMMC
9
+1.8V
3.3V_EMMC
C568
0.1uF
C519
10uF
16V
IC504
TPS54327DDAR
C567
0.1uF
THERMAL
+3.3V_NORMAL
C537
10uF
16V
THERMAL
eMMC POWER
Vout=0.765*(1+R1/R2)=1.119V
Vout=0.765*(1+R1/R2)=1.154V
+1.8V
+3.3V_NORMAL
IC501
AZ1117EH-ADJTRG1
EAN62868801
C503
0.1uF
16V
OPT
FB
4
R565
10K
1%
C564
100uF
R1
5
SW_1
EN
COMP
R502
20K
C508
0.0068uF
50V
C535
10uF
10V
C512
100uF
C514
47pF
50V
OPT
R511
1.5K
1%
R1
C507
0.1uF
16V
POWER_ON/OFF2_1
R513
10K
1%
R2-1.13V
R564
10K
R573
150K
1%
R512
30K
1%
R566
10K
1%
R567
13K
1%
+3.3V_NORMAL
R2
R503
10K
C562
0.1uF
16V
R2
C541
0.0068uF
50V
FB
COMP
SS
22
23
24
16K
1%
R544 150K 1%
RLIM
25
RSET2
AGND
R541
16K 1%
C565
47pF
50V
POWER_ON/OFF2_4
SW_2
20
LX_2
19
LX_1
18
BST
R548
0
C556
10uF
10V
R553
51K
1%
L515
4.7uH
16
SW_IN1
15
NFAULT1
14
13
12
7
11
R533
0
5%
LX_3
C570
22uF
10V
C550
0.047uF
25V
+5V_NORMAL
R551
100K
5%
R554
100K
5%
C552
1uF
10V
/USB_OCD3
C566
10uF
10V
82pF
50V
21
C569
22uF
10V
R1
C551
NFAULT2
C563
0.0068uF
50V
6A
SW_EN1
COMP
R563
6.8K
R552
6.8K
1%
17
EAN62911501
6
SW_EN2
5
EN
5
SW_OUT1
6A
SW_1
C549
0.047uF
25V
/USB_OCD2
7
6
6A
4
6
C546
100pF
50V
OPT
SN1302001(TPS65286RHDR)
SW_IN2
USB_CTL3
8
3
FB
7
Vout=0.6*(1+R1/R2)
R574
180K
1%
Vout=0.8*(1+R1/R2)
R572
10K
D
R571
VID1
R1:10K/R2:23K, V=1.148V
R1:10K/R2:21.5K, V=1.172V
Voltage drop 0.042V
Voltage drop 0.042V
0
G
5%
S
Q505
2N7002A
C501
10uF
16V
2
L506
2uH
3
SW_2
V7V
[EP]
ZD501
5V
AGND
C500
10uF
16V
1
9
VIN
THERMAL
PGND
Placed on SMD-TOP
2
PGND_3
IC503
USB_CTL2
EAN62653301
C561
0.1uF
16V
OPT
4
+5V_USB_3
IC500
BD86106EFJ
L500
BLM18PG121SN1D
C560
10uF
16V
L518
2uH
26
R537
VIN
AGND
C559
10uF
16V
PGND_1
THERMAL
29
10
Placed on SMD-TOP
+3.3V_NORMAL
+12V
8
2
3
PGND_2
25V
1uF
C539
+3.3V_NORMAL
1
9
PGND
VIN_2
VIN_3
[EP]
ZD502
5V
EAN62653301
C540
0.1uF
50V
SW_OUT2
IC502
BD86106EFJ
L517
BLM18PG121SN1D
A
THERMAL
MAX
C538
10uF
35V
+5V_USB_2
+12V
C536
10uF
35V
OPT
R2
C544
2200pF
50V
R546
10K
1
POWER_ON/OFF1
+1.1V_CORE
27
VIN_1
9
+1.1V or +1.13V _CORE
EN
L513
120-ohm
28
[EP]
C513
10uF
10V
8
C511
10uF
10V
R505
33
1%
+24V
MODE/SYNC
OPT
R504
75
1%
R538
10K
R506
1
ADJ/GND
RSET1
+5.0V normal & USB
OUT
ZD500
2.5V
IN
R2-1.1V
Vout=0.8*(1+R1/R2)
POWER UP SEQUENCE
5V/3.3V->1.5V/1.1V->1.0V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
POWER
2013-10-28
05
LGE Internal Use Only
Renesas MICOM
For Debug
12pF
32.768KHz
2
MICOM_DEBUG
HDMI_WAUP:HDMI_INIT
MICOM_DEBUG
X600
1
R616
LOGO_LIGHT
LOGO_LIGHT
C603
MICOM_RESET
C602
Don’t remove R612,
not making float P40
12pF
CAM_PWR_ON_CMD
1K
R611
P600
12507WS-04L
10K
MICOM_DEBUG
R608
MICOM_DEBUG
+3.5V_ST
+3.5V_ST
3
MHL_DET_LM14
MICOM_RESET
4
4.7M
OPT
TP601
10K
5
P123/XT1
P124/XT2/EXCLKS
RESET
P40/TOOL0
P41/TI07/TO07
P120/ANI19
43
42
41
40
39
38
37
270K
OPT
P137/INTP0
44
+3.5V_ST
R619
22
P122/X2/EXCLK
45
C601
C600
0.1uF
R617
P121/X1
CAM_PWR_ON_CMD
REGC
46
0.47uF
VSS
47
C604
0.1uF
16V
48
+3.5V_ST
MICOM_RESET_SW
SW600
JTP-1127WEM
R618
POWER_DET_1
10K
GND
VDD
R615
MHL_DET_LM14
2
1
4
3
CAM_RESET
CAM_RESET
R614
10K
LM14 Power SEQUENCE
P60/SCLA0
1
36
P140/PCLBUZ0/INTP6
P61/SDAA0
2
35
P00/TI00/TXD1
P62
3
34
P01/TO00/RXD1
33
P130
IC600
32
P20/ANI0/AVREFP
I2C_SCL_MICOM
POWER_ON/OFF!(5V)
I2C_SDA_MICOM
MODEL1_OPT_4
4
5
P75/KR5/INTP9/SCK01/SCL01
6
R5F100GEAFB#30
31
P21/ANI1/AVREFM
P74/KR4/INTP8/SI01/SDA01
7
30
P22/ANI2
R623
EAN62632101
0
OPT
IR
POWER_ON/OFF2_3(1.5V)
HDMI_CEC_MICOM
29
P72/KR2/SO21
9
28
P24/ANI4
10
27
P25/ANI5
P71/KR1/SI21/SDA21
MODEL1_OPT_1
MODEL_OPT_5
MODEL1_OPT_3
MODEL1_OPT_2
MODEL1_OPT_1
P147/ANI18
24
23
P146
P10/SCK00/SCL00
22
21
P11/SI00/RXD0/TOOLRXD/SDA00
20
19
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
18
P14/RXD2/SI20/SDA20
22
R629
R613
R612
3.3K
EYE_Q
3.3K
EYE_Q
P17/TI02/TO02
OPT
Reserved
NON_GED
P15/PCLBUZ1/SCK20/SCL20
LM14
MODEL_OPT_4
P16/TI01/TO01/INTP5
Reserved
22
Reserved
MODEL_OPT_2
MODEL_OPT_3
MODEL1_OPT_0
MICOM_LOGO_LIGHT
P51/INTP2/SO11
MICOM_NON_LOGO_LIGHT
MODEL_OPT_1
OPT
MICOM_LOGO_LIGHT
R609
10K
OPT
R606
10K
OPT
R604
10K
OPT
R600
10K
MICOM_LM14
R602
10K
MICOM_GED
R626
10K
MODEL_OPT_0
1
R627
0
17
P27/ANI7
16
25
15
12
14
26
P30/INTP3/RTC1HZ/SCK11/SCL11
CAM_SLEEP
13
11
P26/ANI6
EYE_SCL
+3.5V_ST
MODEL1_OPT_0
SIDE_HP_MUTE
P70/KR0/SCK21/SCL21
SOC_RESET
MICOM MODEL OPTION
KEY1
8
EYE_SDA
MICOM MODEL OPTION
KEY2
P23/ANI3
POWER_ON/OFF2_3
+3.5V_ST
POWER_ON/OFF2_1
P73/KR3/SO01
MODEL1_OPT_5
POWER_ON/OFF2_4(1.1V)
TP600
SCART_MUTE
POWER_ON/OFF2_4
P63
WOL/WIFI_POWER_ON
CAM_SLEEP
SCART_MUTE
POWER_ON/OFF2_4
P31/TI03/TO03/INTP4
PANEL_CTL
P50/INTP1/SI11/SDA11
POWER_ON/OFF2_1(3.3V)
RL_ON
GED
MODEL1_OPT_2
URSA_RESET_MICOM
URSA_RESET_MICOM
AMP_MUTE
SOC_RX
SOC_TX
INV_CTL
LED_R
EDID_WP
For CEC
R630
SOC_RESET
EDID_WP
10K
MICOM_LM14
LED_R
POWER_ON/OFF1
MICOM_NON_LOGO_LIGHT
R610
10K
OPT
R607
10K
OPT
R605
10K
OPT
R603
10K
OPT
R601
10K
MICOM_NON_GED
R631
10K
MODEL1_OPT_5
POWER_DET
MODEL1_OPT_3
MODEL1_OPT_4
+3.5V_ST
LM14 : Active high reset
H13 : Active low reset
R621
120K
G
R620
27K
D600
Q600
RUE003N02
HDMI_CEC_FET_ROHM
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
MICOM
S
D
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
HDMI_CEC_MICOM
S
D
BAT54_SUZHO
G
HDMI_CEC
Q600-*1
SI1012CR-T1-GE3
HDMI_CEC_FET_VISHAY
2013-10-28
06
LGE Internal Use Only
R9531 +1.0V
SPI FLASH (2MBit)
10
9
8
7
6
5
4
3
2
1
TMDS_CLK_SHIELD
1
10
TMDS_CLK+
2
9
76
RSVDNC_25
60
RSVD_5
17
59
RSVD_4
4.7K R3288
RSVDNC_2
18
58
RSVD_3
4.7K R3290
RSVDNC_3
19
57
RSVDNC_24
RSVDNC_4
20
56
RSVD_2
4.7K R3291
4.7K R3292
R3237
RSVDNC_9
25
51
SBVCC5V
C3294
10uF
10V
C3292
10uF
10V
I2C_SDA6
TMDS_DATA0_SHIELD
4
TMDS_DATA0+
5
C3266
0.1uF
16V
C3298
0.1uF
16V
C3271
0.1uF
16V
C3299
0.1uF
16V
DDC pull-up
+5V_NORMAL
5V_HDMI_1
5V_HDMI_2
+5V_NORMAL
+3.5V_ST
5V_HDMI_3
+5V_NORMAL
A2
A1
A2
A2
MMBD6100
D3210
MMBD6100
D3209
C
C
MMBD6100
D3208
C
A1
MMBD6100
D3218
C3293
0.1uF
16V
A1
XTAL_VCC33_R9531
A2
L3213
BLM18PG121SN1D
C3274
0.1uF
16V
A1
50
+5V_NORMAL
C3277
0.1uF
16V
C3276
10uF
10V
3.3V Power Separation
R3254
10
+5V_NORMAL
5V_HDMI_1
R3253
5.1K
AR3203
47K
1/16W
DDC_SDA_2
DDC_SCL_MHL
DDC_SCL_2
DDC_SDA_MHL
G
1uF
DDC_SDA_1_R9531
DDC_SCL_1_R9531
HDMI_3.3V
R3208
10K
+3.3V_NORMAL
C3275
AR3200
47K
1/16W
AR3201
47K
1/16W
PWRMUX_OUT
ARC
C3268
100uF
6.3V
C3269
22uF
10V
AO3438
Q3204
C3235
10uF
10V
CK+_HDMI2_JACK
3
C3245
0.1uF
16V
AVDD33_R9531
C3290
10uF
10V
VCC33_OUT
C3288
0.1uF
16V
I2C_SCL6
C3273
10uF
10V
HDMI_HPD_1
R3282
R0PWR5V
CBUS_HPD0
DSCL0
DSDA0
INT
10K
CI2CA_TPWR
4.7K
R3283
HDMI_ARC
49
33
48
R3236
RSVDL_2
47
33
52
46
CSCL
24
45
CSDA
53
RSVDNC_8
44
54
23
43
55
22
42
21
RSVDNC_7
OPT
C3202
0.1uF
16V
C3280
0.1uF
16V
L3215
BLM18PG121SN1D
RSVDNC_6
R3252
10K
C3278
2.2uF
10V
HDMI_3.3V
RSVD_1
DVDD10_R9531 AVDD33_R9531
C3257
10uF
10V
AVDD33_R9531
RSVDNC_5
CVDD10_R9531
C3282
0.1uF
16V
C
77
78
61
16
RSVDNC_1
DDC_SCL_1_R9531
C3201
1uF
79
80
15
AVDD33_1
D
10V
81
82
AVDD10_1
PWRMUX_OUT
C3289
0.1uF
16V
L3211
BLM18PG121SN1D
CK-_HDMI2_JACK
TMDS_DATA0-
SPI_DI_R9531
D
TMDS_CLK-
R3278
10K
CK+_HDMI_TX_R9531
D2+_HDMI_TX_R9531
D2-_HDMI_TX_R9531
CK-_HDMI_TX_R9531
TPVDD10
T0XC-
T0XC+
T0X0-
T0X0+
TDVDD10
T0X1-
T0X2-
T0X2+
CVDD10_3
ARCRX_TX
RSVDNC_28
RSVDNC_29
T0X1+
83
84
85
86
87
4.7K R3287
G
C3284
0.1uF
16V
S
D3200
IP4294CZ10-TBR
CEC
VA3216
ESD_HDMI
OPT
R3231
3.9K
SCL
HDMI_CEC
SPI_CK_R9531
DIO[IO0]
DDC_SCL_1
4.7K R3286
DDC_SDA_1_R9531
SDA
RESERVED
GND
DVDD10_R9531
DDC_SDA_1
RSVD_6
+3.3V_NORMAL
C3279
10uF
10V
1.8K R3296
OPT
RSVD_7
Q3202
SI1012CR-T1-GE3
VA3214
OPT
VA3212
OPT
ZD3202
2.5V
OPT
1.8K R3293
62
5V_HDMI_2
C3244
10uF
10V
R3285
63
AVDD33_R9531
DDC/CEC_GND
4.7K R3284
14
S
R3221
3.3K
5
C3281
CLK
APLL10_R9531
+5V_NORMAL
13
R9531_RESET
OPT
R3230
1K
R3207
1.8K
4
HOLD
L3207
BLM18PG121SN1D
APLL10_R9531
R0X2+
DDC_SDA_2
DDC_SCL_2
XTAL_VCC33_R9531
CVDD10_1
RESET_N
5.1
12
RSVDNC_23
R3299
HOT_PLUG_DETECT
VDD[+5V]
6
R9531_XTAL_OUT
8
OPT
7
D0-_HDMI2_JACK
6
D0+_HDMI2_JACK
TMDS_DATA1-
D3201
IP4294CZ10-TBR
TMDS_DATA1_SHIELD
TMDS_DATA1+
TMDS_DATA2-
1
10
2
9
3
8
HDMI_3.3V
D1-_HDMI2_JACK
TMDS_DATA2_SHIELD
TMDS_DATA2+
OPT
4
3.3V_Sil9617
+5V_NORMAL
5V_MHL
D1+_HDMI2_JACK
Current Limit
5V_HDMI_3
R3914
BLM31PG500SN1
50-ohm
IC3207
TPS2553DBV
5V_MHL
L3208
BLM18PG121SN1D
L3202
BLM18PG121SN1D
7
D0-_HDMI3_JACK
11
AR3202
33
1/16W
88
0
OPT
R3277 5.1
D0+_HDMI3_JACK
12
RSVDNC_30
0
64
R3913
11
R0X2-
HDMI_HPD_2
20
13
RSVDNC_31
R3912
RSVD_8
10
R0X1+
VA3209
ESD_HDMI
89
RSVDNC_26
R0X1-
5.1
5V_DET_HDMI_2
BODY_SHIELD
15
RSVDNC_32
RSVDNC_27
65
R3273
26
5V_HDMI_2
90
66
5.1
R3274 5.1
R3276
DVDD10_R9531
R3223
33
16
RSVDNC_33
TX_DSDA0
IC3202
R9531AN
RSVDNC_10
VA3201
ESD_HDMI
91
TX_DSCL0 4.7K
67
AVDD33_R9531
14
RSVDNC_34
TX_HPD0
68
9
CVDD10_R9531
HDMI2 With ARC
92
69
8
R0X0+
41
D2+_HDMI1_R9531
ESD_HDMI
VA3205
17
RSVDNC_35
7
R0X0-
40
D2+_HDMI1_R9531
6
JK3200
93
R0XC+
5.1
R3264 5.1
RSVDNC_22
D2-_HDMI1_R9531
5
05008WR-H19C.
18
RSVDNC_36
R3257 5.1
R3263
RSVDNC_21
D2-_HDMI1_R9531
7
94
RSVD_9
39
OPT
D1-_HDMI1_R9531
D1+_HDMI1_R9531
95
70
38
D0+_HDMI1_R9531
D1-_HDMI1_R9531
D1+_HDMI1_R9531
96
6
RSVDNC_20
8
97
R0XC-
RSVDNC_19
9
3
4
19
SS_GPIO8
APLL10
37
10
2
7
3
0.1uF
WP
R9531_FLASH_WP
CVDD10_R9531
C3246
10uF
10V
XTALVCC33
RSVDNC_18
1
SPI_DO_R9531
C3262
10uF
10V
R9531_XTAL_IN
71
36
TMDS_DATA2-
TMDS_DATA2+
XTALIN
72
RSVDNC_17
D0-_HDMI1_R9531
XTALGND
74
73
35
CK+_HDMI1_R9531
D3203
IP4294CZ10-TBR
75
5
RSVDNC_16
CK-_HDMI1_R9531
TMDS_DATA1+
TMDS_DATA2_SHIELD
2
VCC
L3210
BLM18PG121SN1D
4
3
34
D0+_HDMI1_R9531
TMDS_DATA1TMDS_DATA1_SHIELD
8
Vout=0.6*(1+R1/R2)
GPIO6
D0-_HDMI1_R9531
6
1
C3241
1uF
+1.0V_R9531
RSVDL_1
CK+_HDMI1_R9531
7
5
R3275
33 DO[IO1]
NC
R9531_XTAL_OUT
C3270
18pF
50V
XTALOUT
8
OPT
CS
SPI_CS_R9531
5
EAN61387601
3
C3239
0.1uF
R1
VOUT
2A
4
+5V_NORMAL
4
2
ADJ
VCTRL
X-TAL_2
C3267
18pF
50V
DVDD10_R9531
THERMAL
101
AVDD33_2
4
TMDS_DATA0+
2
33
1
3
TMDS_DATA0_SHIELD
1
SD0_IN_SPDIF0_IN
AVDD10_2
3
2
TMDS_DATA0-
GPIO5
CK-_HDMI1_R9531
32
4
9
31
5
10
2
30
6
1
TMDS_CLK+
CVDD10_2
7
R3204
33
SCLK_GPIO9
SPI_CK_R9531
TMDS_CLK_SHIELD
RSVDNC_15
8
TMDS_CLK-
RSVDNC_14
9
D3202
IP4294CZ10-TBR
29
10
1
GND_1
IC3203
W25X20CLSNIG
6
VIN
C3240
0.1uF
16V
GND_2
HDMI_CEC
CEC
RSVDNC_13
11
SCL
RESERVED
98
12
Solder Preform
Attach at R9531 thermal pad
99
13
VA3207
OPT
VA3204
OPT
SDA
28
14
R3220
3.3K
DDC/CEC_GND
27
15
DDC_SCL_1_R9531
R3206
1.8K
VDD[+5V]
RSVDNC_12
16
HOT_PLUG_DETECT
[EP]
17
100
18
R3297
120K
X3201
27MHz
X-TAL_1
R9531_XTAL_IN
7
S3204
RAC33437501
DDC_SDA_1_R9531
RSVDNC_11
19
D1+_HDMI_TX_R9531
AR3207
33
1/16W
CVDD10_R9531
AVDD33_R9531
IOVCC33
ESD_HDMI
20
SPI_DO_R9531
D1-_HDMI_TX_R9531
S3203
RAC33437501
VA3203
BODY_SHIELD
SPI_CS_R9531
AR3208
33
D0+_HDMI_TX_R9531
HDMI_HPD_1
D0-_HDMI_TX_R9531
S3202
RAC33437501
SDO_GPIO10
R3298
33
SPI_DI_R9531
5V_DET_HDMI_1
EN
+3.3V_NORMAL
R2
GND
3
SDI_GPIO11
5V_HDMI_1
C3243
0.1uF
DVDD10_R9531
S3201
RAC33437501
1.8K
HDMI1 With HDCP2.2
2
9
PG
R3280
8
THERMAL
1
R3279
OPT10K
S3200
RAC33437501
+1.0V_R9531
[EP]
1.2K
IC3204
AP2132MP-2.5TRG1
R3281
R3915
+3.3V_NORMAL
VA3200
ESD_HDMI
else : Max 0.7A
POWER_ON/OFF2_4
10K
HDMI (HDMI1 HDCP2.2 / HDMI2 ARC / HDMI4 MHL)
D2-_HDMI2_JACK
6
3.3V_Sil9617
+1.0V_R9531
CK-_HDMI3_JACK
5.1
CK+_HDMI3_JACK
C3249
0.1uF
16V
ZD3200
5V
OPT
GND
EN
MHL_DET
1
6
2
5
3
D3211
OUT
1%
ILIM
FAULT
4
20K
R3295
30V
OPT
R3289
100K
From HDMI2&3_SIL9617
C3242
10uF
10V
D2+_HDMI_TX_MHL
D2-_HDMI_TX_MHL
D1+_HDMI_TX_MHL
/MHL_OCP
D1-_HDMI_TX_MHL
R3294
10K
R3203
C3236
0.1uF
16V
C3219
22uF
10V
R3202 5.1
D2+_HDMI3_JACK
C3218
0.1uF
16V
ESD_HDMI
VA3206
D1-_HDMI3_JACK
IN
D2+_HDMI2_JACK
JK3201
D2-_HDMI3_JACK
D1+_HDMI3_JACK
5
05008WR-H19C.
D0+_HDMI_TX_MHL
D0-_HDMI_TX_MHL
CK+_HDMI_TX_MHL
AVDD10_2
4
9
CK+_HDMI3_JACK
8
OPT
7
D0-_HDMI3_JACK
5
TMDS_DATA0+
6
5V_HDMI_3
R3320
10
C3315
1uF
10V
D0+_HDMI3_JACK
R3321
5.1K
D3205
IP4294CZ10-TBR
SIL9617_INT
+3.3V_NORMAL
+3.5V_ST
1
TMDS_DATA2-
10
S
D1-_HDMI3_JACK
2
TMDS_DATA2_SHIELD
9
3
TMDS_DATA2+
4
D1+_HDMI3_JACK
8
OPT
Q3203
SI1012CR-T1-GE3
G
7
6
C
R3228
1K
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
D
+3.3V_NORMAL
SDA_B
SCL_B OPT 0 R3504
SDA_A OPT 0 R3505
SCL_A
40
41
42
[EP]GND
3.3K
R3318
OPT
R3502
10K
C3314
22uF
10V
OPT
R3503
10K
VCC
2
EN
36
3
SCL
D1+_HDMI_TX_MHL
D1-A
35
4
SDA
D1-_HDMI_TX_MHL
D2+A
34
5
D0+
D2-A
33
6
D0-
CK+_HDMI_TX_MHL
D3+A
32
7
D1+
CK-_HDMI_TX_MHL
D3-A
31
8
D1-
HDMI_RX1-_URSA9_0_RP
NC_2
30
9
NC_1
HDMI_RX0+_URSA9_0_RP
D2+_HDMI_TX_R9531
D0+B
29
10
D2+
HDMI_RX0-_URSA9_0_RP
D2-_HDMI_TX_R9531
D0-B
28
11
D2-
D1+_HDMI_TX_R9531
B1+B
27
12
D3+
D1-_HDMI_TX_R9531
B1-B
26
13
D3-
D2+B
25
14
HPD
CK+_HDMI_TX_R9531
D2-B
24
15
CEC
CK-_HDMI_TX_R9531
D3+B
23
16
SEL1
D3-B
22
17
SEL2
+5V_NORMAL
From HDMI1_R9531AN
R3224 R3226 R3229 R3246
47K
47K
47K
47K
0
1
37
D1+A
OPT
R3500
OPT
R3501
33
RXBSCL_URSA9
33
RXBSDA_URSA9
HDMI_RX2+_URSA9_0_RP
HDMI_RX2-_URSA9_0_RP
HDMI OUTPUT_0 DDC to URSA9
HDMI_RX1+_URSA9_0_RP
HDMI_CLK+_URSA9_0_RP
HDMI_CLK-_URSA9_0_RP
+3.3V_NORMAL
HDMI_MUX_SEL
B
D2+_HDMI3_JACK
JK3202
1/16W
5%
C
MHL_DET
Q3201
R3232
180K
C3200
0.1uF
16V
OPT
B
MMBT3904(NXP) E
(CD_SENCE)
SEL2(LM14_GPIO116)
Low
High
Function
CH A (HDMI2&3_SIL9617) enable
CH B (HDMI1_R9531AN) enable
R3233
120K
ESD_HDMI
VA3208
E MMBT3906(NXP)
Q3205
R3235
10K
D2-_HDMI3_JACK
5
05008WR-H19C.
PWRMUX_OUT_SIL9617
MUX_EN
R3300
38
D0-A
D0-_HDMI_TX_R9531
TMDS_DATA1+
L13413
BLM18PG121SN1D
D0+A
D0+_HDMI_TX_R9531
+3.3V_MUX
+3.3V_NORMAL
+3.3V_NORMAL
D2+_HDMI_TX_MHL
D2-_HDMI_TX_MHL
D0-_HDMI_TX_MHL
TMDS_DATA1TMDS_DATA1_SHIELD
39
From HDMI2&3_SIL9617
D0+_HDMI_TX_MHL
R1PWR5V
DSCL1
CBUS_HPD1
DSDA1
RSVDL_5
RSVDL_4
RSVDH_4
RSVDH_3
RSVDL_3
RSVDL_2
RSVDH_2
RSVDH_1
R3250
5.1K
C3300
10uF
10V
R3319
10K
38
DDC_SDA_2
R3251
10
C3220
1uF
10V
43
DDC_SCL_2
10
C3301
0.1uF
16V
+3.3V_MUX
18
R3249
HDMI_HPD_2
19
3
TMDS_DATA0_SHIELD
DSCL4[VGA]
2
TMDS_DATA0-
CD_SENSE
10
CK-_HDMI3_JACK
TMDS_CLK+
DSDA4[VGA]
1
TMDS_CLK_SHIELD
RESET_N
TMDS_CLK-
INT
D3204
IP4294CZ10-TBR
5V_HDMI_2
+5V_NORMAL
20
DSDA0
I2C_SDA8
21
39
37
19
36
TXCN
35
DSCL0
34
CBUS_HPD0
40
33
R0PWR5V
41
18
32
SBVCC5
42
17
TXCP
31
43
16
TX0N
30
15
TX0P
29
TX1N
28
33
+3.3V_MUX
CEC_A
58
R1XCN
VDD33_1
59
60
R1XCP
61
R1X0N
62
R1X1N
R1X1P
R1X0P
63
64
65
R1X2P
R1X2N
66
67
RSVD_9
68
RSVD_11
RSVD_10
69
RSVD_12
R3239
20
PWRMUX_OUT
HPD_A
1
44
CEC_B
2
14
IC3302
TS3DV642A0RUAR
I2C_SCL8
HPD_B
3
TX1P
HDMI_HPD_3_MHL
4
33
DDC_SCL_MHL
5
R3238
DDC_SDA_MHL
6
CSDA
R3215 5.1K
7
CSCL
45
HDMI_CEC
CEC
DDC_SCL_1
DDC_SDA_1
C3213
10uF
R3227
SPDIF_IN 10K
46
RESERVED
TI 2:1 Mux
PWRMUX_OUT_SIL9617
47
R3213 47K
8
CK-_HDMI_TX_MHL
IC3206
SIL9617
12
13
R3211 47K
R3212 5.1K
9
SCL
11
MHL_DET
10
CK+_HDMI_TX_MHL
RSVD_13
ARC
10
D0-_HDMI2_JACK
CK-_HDMI2_JACK
TX2N
RSVDL_1
11
D0+_HDMI_TX_MHL
D0-_HDMI_TX_MHL
RSVD_14
48
9
DDC_SDA_MHL
DDC_SCL_MHL
D0+_HDMI2_JACK
5.1
CK+_HDMI2_JACK
TX2P
TPWR_CI2CA
12
D1-_HDMI_TX_MHL
VA3215
OPT
VA3213
OPT
RSVD_15
49
VDD10_2
R3210
4.7K
13
D1+_HDMI_TX_MHL
R3222
3.3K
SDA
D1-_HDMI2_JACK
50
8
R3209
47K
14
R3216
1.8K
DDC/CEC_GND
R3256
D2-_HDMI2_JACK
D1+_HDMI2_JACK
R0XCN
TAVDD10
CK-_HDMI_TX_MHL
THERMAL
15
VDD[+5V]
R3255 5.1
R0XCP
VDD10_1
TP3203
D2+_HDMI2_JACK
51
R3201
10K
16
DDC_SCL_MHL
53
R0X0P
52
R3200
47K
17
D2+_HDMI_TX_MHL
D2-_HDMI_TX_MHL
DDC_SDA_MHL
R0X1N
7
SIL9617_RESET
18
AR3204
33
1/16W
HOT_PLUG_DETECT
R3234
10K
19
R0X1P
54
6
RSVD_8
ESD_HDMI
20
R0X2N
55
RSVD_6
26
VA3211
R0X2P
56
R0X0N
RSVD_7
BODY_SHIELD
RSVD_16
5
57
RSVD_5
27
HDMI_HPD_3_MHL
THERMAL
77
25
R3225
33
70
4
71
3
RSVD_3
RSVD_4
72
2
RSVD_2
73
1
RSVD_1
74
AVDD10_1
24
5V_DET_HDMI_3
23
5V_HDMI_3
22
VA3202
ESD_HDMI
75
HDMI3 With MHL
76
C3211
0.1uF
16V
21
C3210
0.1uF
16V
VDD33_2
10uF
10V
C3209
0.1uF
16V
77
C3203
[EP]GND
/MHL_OCP
UB83
HDMI JACK
2013-10-28
07
LGE Internal Use Only
JK801
JSTIB15
+3.3V_NORMAL
R800
33
VIN
A
VCC
B
GND
C
Fiber Optic
SPDIF OUT
SPDIF_OUT
C801
0.1uF
16V
4
SHIELD
C800
47pF
50V
VA800
5.5V
OPT
COMPONENT 1 PHONE JACK
+3.3V_NORMAL
CVBS 1 PHONE JACK
OPT
C802
18pF
+3.3V_NORMAL
R801
10K
R805
1K
R812
47K
R816
10K
COMP1_DET
E
VA801
5.6V
B
VA804
5.6V
JK800
PEJ038-3B6111
5
JK802
PEJ038-3B611
M5_GND
4
M4
3
M3_DETECT
1
M1
6
M6
C805
0.1uF
16V
AV1_CVBS_DET
for audio Hum noise (L)
5
M5_GND
4
M4
3
M3_DETECT
1
M1
6
M6
MMBT3906(NXP)
Q800
C
R821
10K
COMP1_Y
ZD800
COMP_ESD
R817
10K
COMP1/AV1/DVI_L_IN
R802
75
ZD801
COMP_ESD
EAG61030017
VA802
5.6V
COMP_LR_ZENER
R810
470K
C806
1000pF
50V
OPT
R818
10K
COMP1_Pb
ZD802
COMP_ESD
R819
12K
EAG61030016
COMP1/AV1/DVI_R_IN
VA803
5.6V
COMP_LR_ZENER
R803
75
ZD803
COMP_ESD
R811
470K
C807
1000pF
50V
OPT
R820
12K
COMP1_Pr
ZD804
COMP_ESD
R804
75
AV1_CVBS_IN
ZD805
COMP_ESD
ZD806
AV2_CVBS_ZENER_ROHM
ZD807
AV2_CVBS_ZENER_ROHM
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
R814
75
1%
3216
C808
47pF
50V
UB83
AV&COMP JACK
2013-10-28
08
LGE Internal Use Only
P900
SMAW200-H18S5
+3.3V_NORMAL
L900
BLM18PG121SN1D
C909
M_RFModule_RESET
1
2
+3.5V_WOL
BT_RESET
3
4
USB_DM
NC
5
6
USB_DP
7
8
GND
10
GND
C902
0.1uF
R909
100
WOL/WIFI_POWER_ON
R904
100
EYE_SDA
EYE_SCL
WOL
SDA
C903
0.1uF
R905
100
+3.5V_ST
R907
10K
5%
9
SCL
11
12
KEY1
GND
13
14
KEY2
15
16
+3.5V_ST
18
GND
IR
IR
C904
100pF
50V
LED_R
17
22uF
10V
C907
0.1uF
WIFI_DM
D900
RCLAMP0502BA
R908
100
GND
WIFI_DP
Place Near Wafer
C908
C906
5pF
5pF
50V
50V
+3.5V_ST
R910
10K
5%
OPT
R911
10K
5%
R912
100
KEY1
R913
100
KEY2
+3.5V_ST
C910
0.1uF
OPT
C905
1000pF
50V
OPT
C911
0.1uF
OPT
R906
1.8K
19
OPT
C901
0.1uF
16V
GND
LED_R
SMD bottom for ESD_UB8
SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X10.5H
M900
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M901
SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X10.5H
M902
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M903
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M904
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M905
SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X10.5H
M906
SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X10.5H
M907
MDS62110225
MDS62110225
MDS62110225
MDS62110225
MDS62110225
MDS62110225
MDS62110225
MDS62110225
SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X10.5H
M908
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M909
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M910
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M911
SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X10.5H
M912
SMD_GASKET_for_EMS_UB83
GASKET_8.0X6.0X10.5H
M913
MDS62110225
MDS62110225
MDS62110225
MDS62110225
MDS62110225
MDS62110225
OPT
GASKET_8.0X6.0X10.5H
M917
OPT
GASKET_8.0X6.0X10.5H
M923
OPT
GASKET_8.0X6.0X10.5H
M924
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M925
MDS62110225
MDS62110225
MDS62110225
MDS62110225
only for proto board
10.5T
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M916
MDS62110225
13.5T
IR
SMD T0P for EMI_UB8
SMD_GASKET_for_ESD_UB83_US
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
GASKET_8.0X6.0X10.5H
M914
M915
MDS62110225
MDS62110225
SMD_GASKET_for_ESD_UB83_US
SMD_GASKET_for_ESD_UB83_US
SMD_GASKET_for_ESD_UB83_US GASKET_8.0X6.0X13.5H
GASKET_8.0X6.0X13.5H
GASKET_8.0X6.0X13.5H
M919
M920
M918
MDS62110221
MDS62110221
MDS62110221
GND
1/10W
5%
IR_PROTO
G
IR_PROTO
R901
47
IC900
AO-R123C7G-LG
1/16W
5%
IR_PROTO
R900
330
+3.5V_ST
OPT
SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X13.5H
GASKET_8.0X6.0X13.5H
M927
M926
MDS62110221
V
O
VS
MDS62110221
SMD_GASKET_for_ESD_UB83_US
OPT
GASKET_8.0X6.0X13.5H
GASKET_8.0X6.0X13.5H
M921
M922
MDS62110221
SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X13.5H
GASKET_8.0X6.0X13.5H
M928
M929
MDS62110221
MDS62110221
MDS62110221
OPT
GASKET_8.0X6.0X13.5H
M930
MDS62110221
OUT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
IR/KEY/WIFI/BT
2013-10-28
09
LGE Internal Use Only
USB2 (2.0)
MAX 1.0A
USB3 (2.0)
MAX 1.0A
+5V_USB_3
OPT
10uF
10V
OPT
C1003
10uF
10V
ZD1002
5V
3
2
USB DOWN STREAM
USB_DP3
4
ZD1001
5V
USB_DM3
RCLAMP0502BA
D1004
2
C1002
3
USB_DP2
4
USB_DM2
5
10uF
10V
ZD1000
5V
4
C1001
5
USB_DP1
3
RCLAMP0502BA
D1000
USB_DM1
RCLAMP0502BA
D1003
2
USB DOWN STREAM
1
USB DOWN STREAM
1
3AU04S-385-ZC-(LG).
JK1002
1
3AU04S-385-ZC-(LG).
JK1001
3AU04S-385-ZC-(LG).
JK1000
5
+5V_USB_2
USB1 (2.0)
MAX 1.0A
+5V_USB_1
OPT
OCP USB1
+5V_USB_1
+3.3V_NORMAL
+5V_NORMAL
IC1000
BD2242G
GND
EN
/USB_OCD1
6
2
5
3
4
VOUT
ILIM
OC
1%
C1000
0.1uF
16V
1
14K
R1002
VIN
R1001
4.7K
USB_CTL1
R1000
10K
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
USB JACK
2013-10-28
10
LGE Internal Use Only
Ethernet Block
C1100
0.1uF
16V
C1101
0.01uF
50V
C1102
0.1uF
16V
C1103
0.01uF
50V
JK1100
BS-R570098
LAN_UDE
1
2
3
4
5
6
7
8
9
10
11
D1
D2
D3
D4
P1[CT]
P2[TD+]
EPHY_TDP
P3[TD-]
EPHY_TDN
P4[RD+]
EPHY_RDP
P5[RD-]
EPHY_RDN
P6[CT]
VA1100
VA1101
VA1102
VA1103
5.5V
5.5V
5.5V
5.5V
P7
P8
9
EMI
P10[GND]
R1100
0
P11
YL_C
YL_A
GN_C
GN_A
12
SHIELD
JK1100-*1
TLA-6T764
LAN_TDK
1
2
3
4
5
6
7
8
9
10
11
D1
D2
D3
D4
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10[GND]
R11
YL_C
YL_A
GN_C
GN_A
12
SHIELD
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
LAN JACK
2013-10-28
11
LGE Internal Use Only
Main AMP
+3.3V_NORMAL
R1213
AMP_RESET_N 100
L1201
1/16W
L1202
10uH
C1227
1000pF
50V
SPK_L+
SP-7850_10
B
10K
PVDD1A
PVDD1B
31
32
OUT1A
33
PGND1A
34
C1206
BST1A
RESET
26
NC_4
25
AGND
SDATA
7
NTP7514
EAN62886101
24
VDR2
WCK
8
23
BST2A
BCK
9
22
PGND2A
SDA
10
21
OUT2A
18
19
20
OUT2B
PVDD2B
PVDD2A
17
22000pF
4.7K
SPEAKER_L
L1205
10uH
SPK_LSP-7850_10
C1212
22000pF
50V
C1214
1uF
10V
C1215
1uF
10V
C1213
22000pF
50V
SPK_R+
+24V_AMP
R1207
5.6
1/10W
C1211
0.1uF
50V
C1218
390pF
50V
C1221
0.47uF
50V
R1211
0.1uF
50V
4.7K
C1225
R1212
0.1uF
50V
4.7K
SPEAKER_R
C1219
390pF
50V
R1208
5.6
1/10W
C1224
L1204
10uH
SPK_RSP-7850_10
I2S_AMP
50V
R1210
L1203
10uH
C1209
C1207
C1223
0.1uF
50V
4.7K
SP-7850_10
10uF
35V
100
C1200
Q1200
1000pF
MMBT3904(NXP)
50V
E
36
CLK_I
AD
37
IC1200
6
I2S_AMP
C
R1200
AMP_MUTE
5
DVDD
PGND2B
R1204
VDR1
NC_3
16
R1201
10K
BST1B
27
15
+3.3V_NORMAL
28
4
BST2B
C1202
33pF
50V
3
GND
MONITOR_2
C1201
33pF
50V
NC_2
14
R1203
100
I2C_SCL7
PGND1B
MONITOR_1
I2C_SDA7
OUT1B
13
R1202
100
R1206
5.6
1/10W
29
0x54
R1209
C1220
0.47uF
50V
30
THERMAL
41
C1222
0.1uF
50V
C1217
390pF
50V
2
MONITOR_0
AUD_SCK
C1216
390pF
50V
C1210
0.1uF
50V
1
12
AUD_LRCK
C1208
10uF
35V
NC_1
11
From DACLRCH
AUD_LRCH
R1205
5.6
1/10W
VDD_PLL
FAULT
C1204
1uF
10V
+24V_AMP
SCL
C1203
1uF
10V
GND_IO
16V
38
0.1uF
40
10V
39
10uF
L1200
UBW2012-121F
C1205
[EP]GND
C1226
VDD_IO
+24V_AMP
35
+24V
50V
AUD_MASTER_CLK
22000pF
BLM18PG121SN1D
WAFER-ANGLE
SPK_L+
SPK_L-
SPK_R+
SPK_R-
4
3
2
1
P1200
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
MAIN AMP
2013-10-28
12
LGE Internal Use Only
EARPHONE AMP
IC1400
TPA6138A2
HP_ROUT_AMP
C1401
180pF
HP_OUT
R1402
43K
HP_OUT
R1408
0
HP_BYPASS
HP_ROUT_MAIN
HP_OUT
R1400
10K
1%
R1401
33K
-INR
HP_OUT
C1403
10pF
OUTR
50V
GND_1
+3.3V_NORMAL
MUTE
4.7K
R1403
HP_OUT
SIDE_HP_MUTE
VSS
HP_OUT
C1402
1uF
10V
CN
14
1
2
HP_OUT
13
3
12
4
11
5
10
6
9
7
8
+INL
-INL
OUTL
UVP
GND_2
VDD
CP
HP_OUT
R1404
43K
HP_OUT 1%
C1405
10pF
50V
C1407
180pF HP_OUT
R1406
10K
R1405
33K
+3.3V_NORMAL
C1409
1uF
10V
HP_OUT
HP_BYPASS
R1407
0
+INR
C1400
1uF
10V
HP_LOUT_MAIN
HP_LOUT_AMP
HP_OUT
L1400
120-ohm
BLM18PG121SN1D
HP_OUT
C1406
1uF
10V
HP_OUT
C1408
0.1uF
16V
C1404
1uF
10V
HP_OUT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
HEADPHONE AMP
2013-10-28
14
LGE Internal Use Only
1. should be guarded by ground
2. No via on both of them
3. Signal Width >= 12mils
Signal to Signal Width = 12mils
Ground Width >= 24mils
+3.3V_TU
L1500
BLM18PG121SN1D
1
close to TUNER
+3.3V_LNA_TU
C1500
0.1uF
2
RF_SWITCH_CTL_TU
3
IF_AGC_TU
R1514 1K
C1503
0.1uF
RF_SWITCH_CTL
R1508
10K
close to Tuner
33
I2C_SCL5
R1510 33
10
IF_P
IF_P_TU
should be guarded by ground,Match GND VIA
R1505
10
L1501
OPT
IF_N
IF_N_TU
L1504
BLM18PG121SN1D
C1511
0.1uF
16V
I2C_SDA5
ATV_OUT
C1504
15pF
50V
OPT
C1502
15pF
50V
OPT
R1504
L1505
BLM18PG121SN1D
+3.3V_TU
R1511
EU
5
I2C_SDA5_TU
7
IF_AGC
1608 perallel
because of derating
R1517
200
C1519
0.1uF
16V
C1520
22uF
10V
OPT
R1518
200
R1523
100
I2C_SCL5_TU
6
100
C1501
0.1uF
16V
4
+3.3V_TU
+3.3V_NORMAL
R1513
TU_CVBS
E
8
TU_CVBS_TU
9
TU_SIF_TU
B
R1509
150
TU_SIF
C
Q1500
MMBT3906(NXP)
+3.3V_TU
L1502
BLM18PG121SN1D
TU_Q/N/M/W
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_VAL
17 FE_DEMOD1_1_TS_DATA[0]
R1502
TU_Q/N/M/W
C1515
0.1uF
TU_Q/N/M/W
C1513
0.1uF
16V
1
8
PG
2
TU_Q/N/M/W
EN
R1520
10K
0 FE_DEMOD1_1
3
ADJ
FE_DEMOD1_TS_DATA[1]
VOUT
19
FE_DEMOD1_TS_DATA[2]
20
FE_DEMOD1_TS_DATA[3]
21
FE_DEMOD1_TS_DATA[4]
22
FE_DEMOD1_TS_DATA[5]
23
FE_DEMOD1_TS_DATA[6]
24
FE_DEMOD1_TS_DATA[7]
25
/TU_RESET1_TU
4
+5V_NORMAL
FE_DEMOD1_TS_DATA[0-7]
2A
5
NC
VCTRL
FE_DEMOD1_TS_DATA[0]
EAN61387601
Example of Option name
TU_Q_T2 = apply TDSQ type tuner and T2 country
TU_M/W = apply TDSM&TDSW Type Tuner
13’ Tuner Type
TDS’S’-G501D :
TDS’Q’-G501D :
TDS’Q’-G601D :
TDS’Q’-G651D :
TDS’M’-C601D :
TDS’W’-J551F :
TDS’W’-B651F :
TDS’W’-A651F :
TDS’W’-K651F :
for Global
T/C Half NIM Horizontal Type
T/C/S2 Combo Horizontal type
T2/C/S2 Combo Horizontal Type
T2/C/S2 Combo Vertical Type
China NIM with Isolater Type
Japan Dual NIM
Brazil 2Tuner
Taiwan 2Tuner
Colombia DVB-T2 2Tuner
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
TU_Q/N/M/W
C1514
1uF
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[6]
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Vout=0.6*(1+R1/R2)
FE_DEMOD1_TS_DATA[7]
R1519
100
26
+3.3V_DEMOD_TU
27
I2C_SCL2_TU
28
D_Demod_Core
+3.3V_TU
L1503
BLM18PG121SN1D
C1505
0.1uF
29
LNB_TX
30
I2C_SDA2_TU
31
LNB_OUT
C1507
15pF
50V
OPT
/TU_RESET1
C1512
16V
0.1uF
C1510
0.1uF
R1516
33
L1506 D_Demod_Core_1
BLM18PG121SN1D
I2C_SCL2
LNB_TX
R1515
33
LNB_OUT
C1517
0.1uF
LNB
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
TU_Q/N/M/W
C1516
10uF
10V
FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[4]
Global F/E Option Name
1. TU
2. Tuner Name = TDS’S’,TDS’Q’...
3. Country Name = T,T2,S2,KR,US,BR ...
R1
6
VIN
18
R2
GND
7
1/16W
1%
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_SYNC
1/16W
1%
FE_DEMOD1_TS_SYNC
TU_1.1V TU_1.1V
R1522-*1 R1521-*1
18K
15K
15
D_Demod_Core_1
[EP]
FE_DEMOD1_TS_CLK
1/16W
1%
TU_1.2V
IC1500
AP2132MP-2.5TRG1
R1521
10K
FE_DEMOD1_TS_ERROR
0 FE_DEMOD1_1
1/16W
1%
TU_1.2V
FE_DEMOD1_1_TS_CLK
R1501
R1522
10K
0
+3.3V_NORMAL
14
16
R1507
FE_DEMOD1_TS_ERROR_TU
C1509
0.1uF
9
12
T2 : Max 1.7A
else : Max 0.7A
+3.3V_TUNER
THERMAL
11
C1508
15pF
50V
OPT
I2C_SDA2
C1518
18pF
LNB
UB83
TU CIRCUIT
2013-10-28
15
LGE Internal Use Only
DEV_TDJM_G251D
DEV_TDJM_H151F
DEV_TDJM-K151F
DEV_TDJH_H251F
TU1602
TDJM-G251D
TU1603
TDJM-H151F
TU1607
TDJM-K151F
TU1604
TDJH-H251F
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2
NC_2
28
NC_10
29
SDA_DEMOD
27
B4[+1.1V]
28
F22_OUTPUT
26
SCL_DEMOD
27
B4[+1.1V]
25
B3[+3.3V]
26
SCL_DEMOD
24
S_RESET_DEMOD
25
B3[+3.3V]
23
NC_9
24
RESET_DEMOD
22
NC_8
23
D7
21
NC_7
22
D6
20
NC_6
21
D5
19
NC_5
20
D4
18
NC_4
19
D3
17
NC_3
18
D2
16
S_DATA
17
D1
15
S_VAILD
16
D0
14
S_SYNC
15
VAILD
13
S_MCLK
14
SYNC
12
GND_1
13
MCLK
11
S_ERROR
12
GND_1
10
B2[+3.3V]
11
ERROR
9
NC_2
10
B2[+3.3V]
8
S_CVBS
9
NC_5
7
S_SIF
8
CVBS
6
M_DIF[N]
7
SIF
5
M_DIF[P]
6
NC_4
4
SDA_RF
5
NC_3
3
SCL_RF
4
SDA_RF
2
M_DIF_AGC
3
SCL_RF
1
NC_1
29
SDA_DEMOD
30
30
A1
B1
B1
A1
3
SCL_RF
4
SDA_RF
5
AIF[P]
6
AIF[N]
7
NC_1
8
NC_2
9
2
DIF_AGC
3
SCL
4
SDA
5
DIF[P]
6
DIF[N]
7
SIF
8
CVBS
9
B[+3.3V]
+3.3V_LNA_TU
RF_SW_CTL
RF_SWITCH_CTL_TU
IF_AGC
IF_AGC_TU
SCL
I2C_SCL5_TU
SDA
I2C_SDA5_TU
IF[P]
IF_P_TU
IF[N]
IF_N_TU
NC_1
TU_SIF_TU
NC_2
TU_CVBS_TU
NC_3
NC_4
A1
+3.3V_TUNER
ERROR
A1
B1
B1
A1
47
A1
B1
B1
47
FE_DEMOD1_TS_ERROR_TU
GND
MCLK
FE_DEMOD1_1_TS_CLK
SYNC
SHIELD
FE_DEMOD1_TS_SYNC
VAILD
SHIELD
FE_DEMOD1_TS_VAL
D0
FE_DEMOD1_1_TS_DATA[0]
D1
FE_DEMOD1_TS_DATA[1]
D2
FE_DEMOD1_TS_DATA[2]
D3
FE_DEMOD1_TS_DATA[3]
D4
FE_DEMOD1_TS_DATA[4]
D5
FE_DEMOD1_TS_DATA[5]
D6
FE_DEMOD1_TS_DATA[6]
D7
FE_DEMOD1_TS_DATA[7]
RESET_DEMOD
/TU_RESET1_TU
B2[+3.3V]
+3.3V_DEMOD_TU
SCL_DEMOD
I2C_SCL2_TU
B3[+1.2V]
D_Demod_Core
NC_5
LNB_TX
SDA_DEMOD
I2C_SDA2_TU
SHIELD
B1
B1
SHIELD
TU_GND_B
TU_GND_A
TU_GND_B
SHIELD
A1
47
TU_GND_A
47
TU_GND_A
AIF_AGC
TU_GND_B
B1
TU_GND_B
B1
2
1
NC
LNB_OUT
A1
GND_2
TU_GND_A
A1
1
RF_SW_CTL
EBL61400002
LNB
47
A1
B1[+3.3V]
TU_GND_B
4
1
NC_1
B1[+3.3V]
TU_GND_A
3
B1[+3.3V]
EBL61380102
TU_GND_B
2
B1[+3.3V]
EBL61400802
TU1606
TDJK-T151F
TU_GND_B
1
EBL61400602
TU_GND_A
EBL61400503
DEV_TDJK-T151F
TU1603-*2
TDJM-C351D
0 R1601
C1601-*1
2
3
4
5
6
3300pF
7
630V
8
TU_H/M/W_KR/US/CN/JP/TW/BR/EU/AJ_3300pF
0
R1600
R1602
C1600
1000pF
630V
TU_H/M/W_KR/US/CN/JP/TW/BR/EU/AJ
TU_GND_A
C1601
1000pF
630V
TU_H/M/W_KR/US/CN/JP/TW/BR/EU/AJ_1000pF
C1604
3300pF
630V
TU_H/M_KR/US/JP/EU
C1603
3300pF
630V
TU_H/M_KR/US/JP/EU
C1605
3300pF
630V
C1606
1000pF
630V
TU_M/W_CN/HK/TW/BR/EU_1000pF
TU_GND_B
TU_M/W_CN/HK/TW/BR/EU_3300pF
630V
C1602
1000pF
630V
TU_M/W_CN/HK/TW/BR/EU_1000pF
TU_M/W_EU_3300pF
3300pF
TU_M/W_EU_3300pF
TU_M/W_EU_3300pF
C1606-*1
0
DEV_TDJM_C351D
1
9
10
11
12
13
14
15
16
17
18
GND_3
19
20
for tuner EMS (S4) testing
21
22
23
24
25
26
27
28
29
30
A1
A1
B1
47
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
RF_SW_CTL
2
NC_1
3
SCL_RF
4
SDA_RF
5
NC_2
6
NC_3
7
SIF
8
CVBS
9
NC_4
10
NC_5
11
ERROR
12
GND_1
13
MCLK
14
SYNC
15
VAILD
16
D0
17
D1
18
D2
19
D3
20
D4
21
D5
22
D6
23
D7
24
RESET_DEMOD
25
B2[+3.3V]
26
SCL_DEMOD
27
B3[+1.1V]
28
NC_6
29
SDA_DEMOD
B1
30
A1
A1
B1
47
SHIELD
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
TU1602-*1
TDJM-G255D
DEV_TDJM_G255D
1
B1[+3.3V]
TU1603-*1
TDJM-H101F
B1[+3.3V]
DEV_TDJM_H101F
1
NC_1
2
NC_2
3
SCL_RF
4
SDA_RF
5
NC_3
6
NC_4
7
SIF
8
CVBS
9
NC_5
10
B2[+3.3V]
11
ERROR
12
GND_1
13
MCLK
14
SYNC
15
VAILD
16
D0
17
D1
18
D2
19
D3
20
D4
21
D5
22
D6
23
D7
24
RESET_DEMOD
25
B3[+3.3V]
26
SCL_DEMOD
27
B4[+1.2V]
28
F22_OUTPUT
29
SDA_DEMOD
30
B1
A1
A1
B1
B1[+3.3V]
NC_1
M_DIF_AGC
SCL_RF
SDA_RF
M_DIF[P]
M_DIF[N]
S_SIF
S_CVBS
NC_2
B2[+3.3V]
S_ERROR
GND_1
S_MCLK
S_SYNC
S_VALID
S_DATA
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
S_RESET_DEMOD
B3[+3.3V]
SCL_DEMOD
B4[+1.1V]
NC_10
SDA_DEMOD
B1
47
SHIELD
SHIELD
UB83
TU_SYMBOL
2013-10-28
16
LGE Internal Use Only
RS-232C Control INTERFACE
JK1700
PEJ038-3B61
RS232C_PHONE
R1700
100
+3.5V_ST
RS232C_PHONE
R1701
100
C1700
OPT
ZD1700
ADUC 20S 02 010L
20V
0.33uF
RS232C_PHONE
C1705
0.1uF
RS232C_PHONE
RS232C_PHONE
IC1700
GND
5
L
4
DETECT
3
R
1
OPT
ZD1701
ADUC 20S 02 010L
20V
MAX3232CDR
C1+
RS232C_PHONE
C1701
0.1uF
RS232C_PHONE
C1702
0.1uF
V+
C1-
C2+
RS232C_PHONE
C1703
0.1uF
C2-
V-
RS232C_PHONE
C1704
0.1uF
DOUT2
RIN2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
GND
DOUT1
RIN1
ROUT1
SOC_RX
DIN1
SOC_TX
DIN2
ROUT2
EAN41348201
HP OUT
R1703-*1
1uF
10V
HP_BYPASS
HP_OUT
L1701
BLM18PG121SN1D
HP_LOUT_AMP
HP_OUT
R1703
150
HP_OUT
C1707
0.22uF
10V
1/10W
5%
+3.3V_NORMAL
R1706
HP_OUT
R1705
100
10K
HP_OUT
HP_DET
HP_OUT
L1700
BLM18PG121SN1D
HP_ROUT_AMP
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
HP_OUT
R1704
150
HP_OUT
C1706
0.22uF
10V
1/10W
5%
R1704-*1
1uF
10V
HP_BYPASS
1/16W
5%
ZD1702
5.6V
HP_OUT
UB83
RS232C
2013-10-28
17
LGE Internal Use Only
DVB-S2 LNB Part Allegro
(Option:LNB)
Input trace widths should be sized to conduct at least 3A
3A
Ouput trace widths should be sized to conduct at least 2A
+12V
2A
D1802-*1
SS23L
D1804-*1
Max 1.3A
30V
DIODE_SS23L
40V
LNB_SX34
GNDLX
NC_2
LX
16
17
NC_3
19
18
BOOST
ISET
IC1800
A_GND
R1803
39K
TCAP
C1812
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LNB
LNB_TX
I2C_SDA2
I2C_SCL2
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
1/16W
1%
LNB
0.1uF
C1811
A_GND
TDO
D1803-*1
LNB_SX34
40V
13
4A8303SESTR-T12
LNB
5
11
3
A_GND
LNB
0.22uF
C1802
0.22uF
25V
TDI
R1804
0
LNB
10
LNB
C1804
0.1uF
50V
VREG
EAN62653701
TONECTRL
Close to Tuner
Surge protectioin
LNB
14
2
9
D1800
LNB
R1800
2.2K
1W
LNB
NC_1
ADD
C1801
33pF
LNB
D1803
LNB_SMAB34
40V
8
30V
DIODE_ONSEMI
GND
7
LNB_OUT
VIN
THERMAL
21
Caution!! need isolated GND
C1810
0.1uF
50V
15
1
SDA
LNB
R1802 33
VCP
20
DIODE_SS23L
D1801
MBR230LSFT1G
6
A_GND
SS23L
D1801-*1
close to VIN pin(#15)
SCL
30V
C1809
10uF
25V
LNB
A_GND
A_GND
LNB
R1801 33
close to Boost pin(#1)
[EP]GND
C1807
10uF
25V
LNB
IRQ
C1806
10uF
25V
LNB
LNB
C1805
10uF
25V
LNB
C1808 0.1uF
C1803
0.01uF
50V
LNB
SP-7850_15
15uH
L1800
LNB
40V
LNB_SMAB34
30V
C1800
18pF
LNB
3.5A
D1804
LNB
D1802
DIODE_ONSEMI
UB83
LNB
2013-10-28
18
LGE Internal Use Only
eMMC I/F
1/16W
10K
AR1904
R1901
10K
1/16W
10K
AR1903
R1900
10K
DVDD18_EMMC
IC1900
THGBMAG5A1JBAIR
IC1900-*1
THGBMAG6A2JBAIR
EAN62886901
A3
EMMC_DATA[1]
A4
A5
EMMC_DATA[2]
B2
EMMC_DATA[3]
EMMC_DATA[4]
B3
EMMC_DATA[5]
B4
EMMC_DATA[6]
EMMC_DATA[7]
B5
AR1901
22
1/16W
B6
C8
DAT0
NC_23
DAT1
NC_24
DAT2
NC_25
DAT3
NC_26
DAT4
NC_27
DAT5
NC_28
DAT6
NC_29
DAT7
NC_30
NC_31
NC_32
M6
M5
CLK
NC_33
CMD
NC_34
NC_35
NC_36
A6
A7
C5
E5
AR1902
22
E8
E9
EMMC_CLK
DAT7
E10
EMMC_CMD
EMMC_RST
F10
G3
G10
H5
OPT
C1901
10pF
50V
J5
K6
K7
K10
P7
P10
RFU_1
NC_37
RFU_2
NC_38
NC_21
NC_39
RFU_3
NC_40
RFU_4
NC_41
RFU_5
NC_42
RFU_6
NC_43
RFU_7
NC_44
RFU_8
NC_45
RFU_9
NC_46
RFU_10
NC_47
RFU_11
NC_48
RFU_12
NC_49
RFU_13
NC_50
RFU_14
NC_51
RFU_15
NC_52
RFU_16
NC_53
RST_N
OPT
C1900
0.1uF
16V
C6
M4
3.3V_EMMC
DVDD18_EMMC
N4
P3
EMMC_RESET_BALL
EMMC_CMD_BALL
EMMC_CLK_BALL
DAT5
DAT6
DAT4
DAT3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
C1902
0.1uF
16V
C1903
2.2uF
10V
E6
F5
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
EMMC_VDDI
pattern 0.2mm
C2
VDDI
C1906
1uF
10V
E7
G5
H10
K8
C1904
0.1uF
16V
C1905
2.2uF
10V
C4
N2
N5
P4
P6
VSS_1
VSS_2
VSS_3
VSS_4
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
TOSHIBA_EMMC_4GB_V4.5
NC_54
K5
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
DAT3
DAT4
DAT7
A2
A8
A9
A10
A11
A12
A13
A14
B1
B7
B8
B9
B10
B11
B12
Don’t Connect Power At VDDI
B13
EMMC_VDDI
B14
C1
(Just Interal LDO Capacitor)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
DAT5
NC_86
A1
C3
C7
IC1900-*2
THGBMAG7A2JBAIR
EAN62740501
A3
A4
EMMC_DATA[0]
NC_1
NC_87
NC_2
NC_88
NC_3
NC_89
NC_4
NC_90
NC_5
NC_91
NC_6
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
NC_107
A5
B2
B3
C9
B4
B5
B6
C10
C12
A6
A7
C13
E5
E8
C14
E9
E10
F10
D2
DAT4
NC_27
DAT5
NC_28
DAT6
CLK
CMD
C5
G3
DAT5
G10
H5
J5
K6
K7
D3
K10
P7
P10
D4
RFU_1
RFU_2
NC_21
RFU_3
RFU_4
RFU_5
RFU_6
RFU_7
RFU_8
RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
RFU_16
K5
D12
RST_N
D13
C6
M4
N4
D14
P3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
E1
E6
F5
E2
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
E3
C2
VDDI
E12
E7
G5
E13
H10
K8
E14
C4
N2
N5
F1
F2
P4
DAT6
P6
VSS_1
VSS_2
VSS_3
VSS_4
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
A1
F3
A2
A8
A9
F12
A10
A11
A12
F13
A13
A14
B1
F14
B7
B8
G1
B9
B10
B11
G2
B12
B13
B14
G12
C1
C3
C7
G13
NC_24
NC_25
NC_26
M6
M5
NC_23
DAT1
DAT2
DAT3
DAT7
C11
D1
DAT0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_52
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_93
NC_94
NC_95
NC_96
NC_97
NC_98
NC_99
NC_100
NC_101
NC_102
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
NC_107
C8
A3
C9
A4
C10
A5
C11
B2
C12
B3
C13
B4
C14
B5
D1
B6
C8
DAT0
DAT4
DAT5
DAT6
DAT7
D2
D3
D4
M6
D12
M5
CLK
CMD
D13
D14
E1
A6
E2
A7
E3
C5
E12
E5
E13
E8
E14
E9
F1
E10
F2
F10
F3
G3
F12
G10
F13
H5
F14
J5
G1
K6
G2
G12
K7
K10
G13
P7
G14
P10
RFU_1
RFU_2
NC_21
RFU_3
RFU_4
RFU_5
RFU_6
RFU_7
RFU_8
RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
RFU_16
H1
H2
H3
K5
RST_N
H12
H13
H14
C6
J1
M4
J2
N4
J3
P3
J12
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
J13
J14
K1
E6
K2
F5
K3
J10
K12
K9
VCC_1
VCC_2
VCC_3
VCC_4
K13
K14
L1
C2
VDDI
L2
L3
L12
E7
L13
G5
L14
M1
H10
K8
M2
C4
M3
N2
M7
N5
M8
P4
M9
P6
VSS_1
VSS_2
VSS_3
VSS_4
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
M10
M11
M12
M13
A1
M14
A2
N1
A8
N3
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
B8
N14
B9
P1
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
P13
C3
P14
C7
NC_23
DAT1
DAT2
DAT3
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_24
TOSHIBA_EMMC_16GB_V4.5
AR1900
22
1/16W
TOSHIBA_EMMC_8GB_V4.5
EMMC_DATA[0-7]
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_52
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_93
NC_94
NC_95
NC_96
NC_97
NC_98
NC_99
NC_100
NC_101
NC_102
NC_103
NC_104
NC_105
NC_20
NC_106
NC_22
NC_107
C9
C10
C11
C12
C13
C14
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G12
G13
G14
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14
G14
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
EMMC_RESET_BALL
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
EMMC_CLK_BALL
M7
M8
M9
M10
M11
M12
M13
M14
N1
N3
EMMC_CMD_BALL
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14
UB83
EMMC
2013-10-28
19
LGE Internal Use Only
EU
EU_CVBSOUT
R2116
1K
EU
C2106
0.1uF
VA2101
5.6V
OPT
R2118
10K
SC_DET
CVBS_OUT_SEL
E
16
15
14
13
12
11
EU
C2110
1uF
IC2100
MM1756DURE(4M)
DTV/MNT_V_OUT1
SCART_OUT_BYPASS
75
R2102
SYNC_OUT
SYNC_GND
RGB_IO
OPT
C2103
68pF
50V
EU
R2112
22
OPT
C2107
68pF
50V
VCC
PS
EU_CVBSOUT
R2124
75
SC_FB
R_OUT
VA2102
5.6V
EU
R_GND
EU
R2108
75
G_OUT
R2122
75
EU_CVBSOUT
R2123
75
OPT
R2125
1K
R2121
200
EU_CVBSOUT
RTR030P02
Q2103
D
EU_CVBSOUT
R2113
0
SYNC_IN
C
+3.3V_CVBS_out
AV_DET
17
EU_CVBSOUT
MMBT3906(NXP)
Q2102
C
OPT
C2102
47pF
50V
19
VA2108
5.5V
OPT
B
OUT
6
1
EU_CVBSOUT
5
2
4
3
DTV/MNT_V_OUT1
10
C2114
0.1uF
EU_CVBSOUT
EU_CVBSOUT
C2109
0.1uF
IN
GND
C2113
0.1uF
3216
EU
EU_CVBSOUT
MMBT3906(NXP)
Q2104
B
EU_CVBSOUT
75
R2105
VA2107
5.5V
EU
EU_CVBSOUT
DTV/MNT_V_OUT
E
COM_GND
OPT
EU_CVBSOUT
ATV_OUT
18
R2120
1K
1/16W
5%
OPT
C2112
1uF
10V
Q2100
2SC3052
E
SC_CVBS_IN
SHIELD
EU_CVBSOUT
R2127
0
CVBS_OUT_SEL
C
B
1/16W
5%
OPT
C2108
1uF
R2126
200
G
R2119
1.8K
CLOSE TO JUNCTION
EU_CVBSOUT
EU
R2114
10K
EU_CVBSOUT
EU_CVBSOUT
+3.3V_NORMAL
G
EU_CVBSOUT
S
+3.3V_CVBS_out
D
EU_CVBSOUT
S
+3.3V_CVBS_out
L2100
BLM18PG121SN1D
RTR030P02
Q2101
+3.3V_NORMAL
Full Scart(18 Pin Gender)
BIAS
EU_CVBSOUT
C2111
4.7uF
SCART_OUT_BYPASS
G_GND
9
R2128
0
SC_R
ID
8
VA2103
5.5V
EU
B_OUT
7
AUDIO_L_IN
DTV/MNT_V_OUT1
EU
R2106
75
DTV/MNT_V_OUT
1/16W
5%
6
B_GND
5
SC_G
AUDIO_GND
4
3
AUDIO_R_IN
CVBS_OUT_SEL
0
1
EU
R2109
75
VA2104
5.5V
EU
AUDIO_L_OUT
DTV_MNT_V_OUT1
DTV OUT
ATV OUT
2
AUDIO_R_OUT
1
SC_B
EU
R2107
75
VA2105
5.5V
EU
DA1R018H91E
JK2100
EU
EU
R2115
15K
EU
SC_ID
R2103
10K
VA2100
20V
EU
VA2109
5.6V
EU
SC_L_IN
EU
R2117
3.9K
R2110
12K
EU
EU
R2100
470K
EU
R2104
10K
VA2106
5.6V
EU
SC_R_IN
R2111
12K
EU
EU
R2101
470K
DTV/MNT_L_OUT
EU
C2100
1000pF
50V
DTV/MNT_R_OUT
EU
C2101
1000pF
50V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
SCART JACK
2013-10-28
21
LGE Internal Use Only
+12V
EU
L2200
AUD_OUT >> EU/CHINA_HOTEL_OPT
EU
EU
OPT
OPT
R2203
C2203
470K
6800pF
33K
EU
IN1-
R2204
C2204
33pF
EU
IN1+
VEE
8
VCC
2
7
OUT2
4
6
IN2-
R2209
5
OPT
R2210
33K
OPT
DTV/MNT_L_OUT
10uF
C2209
6800pF
EU
C
C2208 EU
33pF
Q2200
MMBT3904(NXP)
EU
1/16W
5%
EU
B
E
R2212
1K
EU_SCART_MUTE_ISAHAYA
Q2202
RT1P141C-T112
EU
C
1/16W
5%
EU
R2220
100K
SCART_AMP_R_FB
R2221
100K
1/16W
5%
EU
R2218
100K
EU
C2215
2.2uF
10V
[SCART AUDIO MUTE]
EU
C2210
IN2+
1/16W
5%
220K
R2215
EU
EU
330pF
C2211
EU
R2219
100K
SCART_Lout
EU
470K
SCART_AMP_L_FB
EU
R2214
5.6K
EU
R2211
2.2K
DTV/MNT_R_OUT
EU
3
C2207
0.1uF
50V
SIGN74002423
EU
R2216
5.6K
SCART_MUTE
SCART_Rout
EU
R2217
220K
DTV/MNT_R_OUT
EU
C2212
330pF
EU
C
Q2201
MMBT3904(NXP)
CLOSE TO MSTAR
R2213
1K
B
B
PDTA114ET
Q2202-*1
E
C2202
10uF
1
C
OUT1
E
R2202
B
2.2K
DTV/MNT_L_OUT
C2216
2.2uF
10V
EU
IC2200
AZ4580MTR-E1
E
EU
EU_SCART_MUTE_NXP
CLOSE TO MSTAR
Near Place Scart AMP
EU
EU
SCART_AMP_R_FB
4.7uF
C2213
EU
10K
R2201
EU
SCART_AMP_L_FB
4.7uF
C2214
10K
R2200
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
UB83
SCART JACK
2013-10-28
21
LGE Internal Use Only
CI Region
* Option name of this page : CI_SLOT
(because of Hong Kong)
CI SLOT
CI TS INPUT
CI_DATA[0-7]
CI_DATA[0-7]
+5V_NORMAL
C2303
10uF
10V
R2308
10K
CI_SLOT_JACK
AR2303
FE_DEMOD1_TS_DATA[7]
CI_MDI[7]
FE_DEMOD1_TS_DATA[6]
CI_MDI[6]
FE_DEMOD1_TS_DATA[5]
CI_MDI[5]
FE_DEMOD1_TS_DATA[4]
CI_MDI[4]
P2300
10125901-015LF
/CI_CD1
AR2304
35
1
36
2
37
3
TPI_DATA[4]
38
4
TPI_DATA[5]
39
5
TPI_DATA[6]
TPI_DATA[7]
40
6
41
7
42
8
AR2300
33
R2310
10K
43
9
CI_IORD
44
10
CI_IOWR
45
11
46
12
CI_MDI[0]
47
13
CI_MDI[1]
48
14
CI_MDI[2]
49
15
CI_MDI[3]
50
16
51
17
52
18
CI_MDI[4]
53
19
CI_MDI[5]
54
20
55
21
56
22
57
23
C2301
0.1uF
GND
CI_MDI[6]
R2300
10K
CI_MDI[7]
R2311
R2303
47
58
24
R2304
47
59
25
60
26
61
27
62
28
63
29
64
30
65
31
TPI_DATA[0]
66
32
TPI_DATA[1]
67
33
TPI_DATA[2]
TPI_DATA[3]
68
PCM_RESET
CLOSE TO MSTAR
10K
CAM_WAIT_N
REG
R2305
TPI_CLK
TPI_VAL
R2306
R2307
TPI_SOP
33
33
33
AR2301
33
CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]
R2318
47
69
R2320
10K
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[1]
CI_MDI[1]
FE_DEMOD1_TS_DATA[0]
CI_MDI[0]
FE_DEMOD1_TS_DATA[0-7]
CI_ADDR[10]
/PCM_CE1
CI_ADDR[11]
CI_OE
CI_MISTRT
CI_MIVAL_ERR
R2322
33
R2323
33
R2324
100
FE_DEMOD1_TS_CLK
CI_MCLKI
CI_ADDR[8]
R2321
10K
CI_ADDR[13]
CI_ADDR[14]
R2319
CI_WE
100
CAM_IREQ_N
C2305
0.1uF
C2304
0.1uF
CI HOST I/F
GND
CI_ADDR[12]
CI_ADDR[7]
CLOSE TO MSTAR
GND
CI_ADDR[6]
AR2310
33
CI_ADDR[5]
CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[0]
EB_ADDR[0]
EB_ADDR[1]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[1]
CI_ADDR[2]
EB_ADDR[2]
CI_ADDR[0]
CI_ADDR[3]
EB_ADDR[3]
CI_DATA[0]
CI_DATA[1]
CI_DATA[2]
CI_ADDR[0-14]
AR2302
33
CI_ADDR[4]
G1
/CI_CD2
EB_ADDR[4]
CI_ADDR[5]
EB_ADDR[5]
CI_ADDR[6]
EB_ADDR[6]
CI_ADDR[7]
EB_ADDR[7]
GND
GND
C2300
2pF
50V
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
+5V_NORMAL
CI_ADDR[9]
R2312
100
+5V_NORMAL
FE_DEMOD1_TS_DATA[3]
CI_MDI[2]
34
G2
33
CI_MDI[3]
CI_DATA[3]
CI_DATA[0-7]
R2314
100
+5V_NORMAL
33
FE_DEMOD1_TS_DATA[0-7]
+5V_CI_ON
AR2308
R2309
10K
GND
CLOSE TO MSTAR
EB_ADDR[8]
EB_ADDR[9]
CI_ADDR[10]
EB_ADDR[10]
CI_ADDR[11]
EB_ADDR[11]
AR2309
CI_MISTRT
CI_MIVAL_ERR
CI_MCLKI
33
CI_ADDR[8]
CI_ADDR[9]
33
CI_ADDR[12]
EB_ADDR[12]
CI_ADDR[13]
EB_ADDR[13]
CI_ADDR[14]
EB_ADDR[14]
CAM_REG_N
REG
AR2307 33
CI DETECT
CI_OE
EB_OE_N
CI_WE
EB_WE_N
CI_IORD
EB_BE_N1
CI_IOWR
EB_BE_N0
+3.3V_NORMAL
OR_GATE_CI_PHILIPS
IC2300
74LVC1G32GW
B
1
A
2
GND
3
+3.3V_NORMAL
5
VCC
4
Y
/CI_CD2
B
OR_GATE_CI_TI
OR_GATE_CI_TOSHIBA
IC2300-*1
SN74LVC1G32DCKR
IC2300-*2
TOSHIBA ELECTRONICS KOREA CORPORATION
1
5
IN_B
VCC
IN_A
2
3
4
GND
Y
1
5
VCC
3
CAM_CD1_N
R2316
47
2
4
AR2305
33
CI_DATA[1]
EB_DATA[0]
EB_DATA[1]
CI_DATA[2]
EB_DATA[2]
CI_DATA[3]
EB_DATA[3]
CI_DATA[4]
AR2306
33
EB_DATA[4]
CI_DATA[5]
EB_DATA[5]
CI_DATA[6]
EB_DATA[6]
CI_DATA[7]
EB_DATA[7]
OUT_Y
EB_DATA[0-7]
A
GND
CI_DATA[0]
R2313
10K
CI_DATA[0-7]
/CI_CD1
EB_DATA[0-7]
CI_DATA[0-7]
CI POWER ENABLE CONTROL
IC2301
AP2151WG-7
+5V_NORMAL
IN
5
+5V_CI_ON
1
2
R2302
100
PCM_5V_CTL
EN
4
3
L2300
BLM18PG121SN1D
OUT
GND
FLG
C2302
1uF
10V
R2317
100K
R2301
10K
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
NC5_M1A
PCMCI
2013.04.29
19
LGE Internal Use Only
+3.3V_NORMAL
VDDP
4st Layer
L2190
BLM18PG121SN1D
C2190
10uF
10V
IC2500
LGE7411(URSA9)
C2195
10uF
10V
C2128
1uF
10V
C2120
10uF
10V
C2143
0.1uF
16V
C2139
0.1uF
16V
C2134
0.1uF
16V
C2145
0.1uF
16V
C13314
0.1uF
16V
C13315
10uF
10V
AG2
AG1
AH3
AH1
AH2
AJ3
AJ2
AK2
AK1
AL1
AM2
AL2
RB0N
RB0P
Close to Chip side
RB1N
RB2N
L2101
BLM18PG121SN1D
RB2P
RBCKN
RBCKP
AM17
RB3N
VX1_0-
RB3P
VX1_0+
RB4N
VX1_1-
RB4P
VX1_1+
VX1_2VX1_2+
AK3
AL3
AK4
AL4
AM4
AK5
AM5
AL5
AK6
AL6
AK7
AL7
RC0N
VX1_3-
RC0P
VX1_3+
RC1N
VX1_4-
RC1P
VX1_4+
RC2N
VX1_5-
RC2P
VX1_5+
RCCKN
VX1_6-
RCCKP
VX1_6+
RC3N
VX1_7-
RC3P
VX1_7+
RC4N
VX1_8-
RC4P
VX1_8+
VX1_9VX1_9+
AM7
AK8
AM8
AL8
AK9
AL9
AK10
AL10
AM10
AK11
AM11
AL11
RD0N
VX1_10-
RD0P
VX1_10+
RD1N
VX1_11-
RD1P
VX1_11+
RD2N
VX1_12-
RD2P
VX1_12+
RDCKN
VX1_13-
RDCKP
VX1_13+
RD3N
VX1_14-
RD3P
VX1_14+
RD4N
RD4P
VX1_15VX1_15+
VX1_16VX1_16+
AK12
AL12
AK13
AL13
AM13
AK14
AM14
AL14
AK15
AL15
AK16
AL16
RE0N
VX1_17-
RE0P
VX1_17+
RE1N
VX1_18-
RE1P
VX1_18+
RE2N
VX1_19-
RE2P
VX1_19+
AK17
C2105
10uF
10V
AL18
AK18
AM19
AM20
AK22
0.1uF
C13008
TXDBN7_L
AL21
0.1uF
C13009
AK23
0.1uF
C13010
TXDBN6_L
AM22
0.1uF
C13011
TXDBP6_L
C13012
TXDBN5_L
AK24
0.1uF
AL23
0.1uF
C13013
TXDBP5_L
AL25
0.1uF
C13014
TXDBN4_L
AK25
0.1uF
C13015
TXDBP4_L
AM26
0.1uF
C13016
TXDBN3_L
AK26
0.1uF
C13017
TXDBP3_L
AL27
0.1uF
C13018
TXDBN2_L
AK27
C13019
TXDBP2_L
AM28
0.1uF
C13020
TXDBN1_L
AL28
0.1uF
C13021
0.1uF
0.1uF
C13022
TXDBN0_L
AM29
0.1uF
C13023
TXDBP0_L
D3
0.1uF
C13024
TXDAN7_L
HDMI_CLK-_URSA9_0_RP
0.1uF
C13025
TXDAP7_L
AL32
HDMI_RX0+_URSA9_0_RP
0.1uF
C13026
TXDAN6_L
AL31
0.1uF
C13027
TXDAP6_L
HDMI_RX0-_URSA9_0_RP
TXDAN5_L
HDMI_RX1+_URSA9_0_RP
E3
D2
F3
AK31
0.1uF
C13028
AK32
0.1uF
C13029
TXDAP5_L
AJ30
0.1uF
C13030
TXDAN4_L
HDMI_RX1-_URSA9_0_RP
AJ31
0.1uF
C13031
TXDAP4_L
AH30
HDMI_RX2+_URSA9_0_RP
0.1uF
C13064
TXDAN3_L
AH32
0.1uF
C13065
TXDAP3_L
0.1uF
C13066
TXDAN2_L
0.1uF
C13067
TXDAP2_L
AE31
0.1uF
C13068
TXDAN1_L
AF30
0.1uF
C13069
AD32
0.1uF
C13070
TXDAN0_L
AE30
0.1uF
C13071
TXDAP0_L
OSD
TXVBY1_2N
TXVBY1_2P
0.1uF
C13037
AE1
AD2
AE3
TXVBY1_3N
0.1uF
C13040
AC2
TXVBY1_3P
0.1uF
C13041
AD3
AC3
AC1
E2
F1
F2
C13045
AB1
TXVBY1_5N
0.1uF
C13048
Y2
TXVBY1_5P
0.1uF
C13049
AA3
AA2
Y3
Y1
0.1uF
TXVBY1_6P
0.1uF
C13052
W2
C13053
W1
V2
W3
TXVBY1_7N
0.1uF
C13056
U2
TXVBY1_7P
0.1uF
C13057
V3
U3
U1
Close to Chip side
HDMI_RX0N_0
HDMI_RX1P_0
4th Layer
VDDC
VDDC
HDMI_RX1N_0
HDMI_RX2P_0
C2198
10uF
10V
C2194
10uF
10V
C2122
10uF
10V
C2132
10uF
10V
C2137
1uF
10V
C2144
0.1uF
16V
C2147
0.1uF
16V
C2146
0.1uF
16V
C2148
0.1uF
16V
C2149
0.1uF
16V
C13307
0.1uF
16V
C2150
10uF
10V
C2196
10uF
10V
AVDDL_MOD
RECKP
AH29
RE3N
VX1_HTDPN
RE3P
VX1_LOCKN
RE4N
L2104
BLM18PG121SN1D
R1938
10K
URSA_TX_HTPD_pulldown
G1
G2
VBY1_RXM[0]
J3
VBY1_RXP[0]
LOCKAn
VBY1_RXM[1]
VBY1_RXP[1]
H2
VBY1_RXM[2]
J1
VBY1_RXP[2]
VBY1_RXM[3]
Close to Chip side
4th Layer
HTPDAn
AG29
J2
+3.3V_NORMAL
HDMI_RXCP_1
C2115
0.1uF
16V
HDMI_RXCN_1
HDMI_RX0P_1
C2123
0.1uF
16V
C13311
10uF
10V
C13305
0.1uF
16V
C2154
10uF
10V
HDMI_RX0N_1
HDMI_RX1P_1
Close to Chip side
HDMI_RX1N_1
AVDDL_DRV
HDMI_RX2P_1
4th Layer
HDMI_RX2N_1
L2105
BLM18PG121SN1D
VBY1_RXM[4]
VBY1_RXP[4]
C2116
0.1uF
16V
VBY1_RXM[5]
VBY1_RXP[5]
VBY1_RXM[6]
VBY1_RXP[6]
C2124
0.1uF
16V
C13310
10uF
10V
C13304
0.1uF
16V
C2153
10uF
10V
VBY1_RXM[7]
VBY1_RXP[7]
TXVBY1_6N
C13306
0.1uF
16V
C2142
0.1uF
16V
RECKN
VBY1_RXM[8]
VBY1_RXP[8]
R1939
10K
HDMI_TX_DDC_CLK
Close to Chip side
DVDD_DDR
4th Layer
HDMI_TX_DDC_SDA
VBY1_RXM[9]
220
R1943
VIDEO
AB3
C2138
0.1uF
16V
HDMI_RX0P_0
TXDAP1_L
VBY1_RXP[9]
VBY1_RXM[10]
VBY1_RXP[10]
HDMI_TX_DDC_CLK
VBY1_RXM[11]
HDMI_TX_DDC_SDA
VBY1_RXP[11]
E Q1901
MMBT3906(NXP)
B
C
HDMI OUTPUT to LM14
C13044
0.1uF
C2133
0.1uF
16V
HDMI_RXCN_0
22
R1952
0.1uF
TXVBY1_4P
C2127
0.1uF
16V
HDMI_RXCP_0
C2191
10uF
10V
LD1900
SML-512UW
TXVBY1_4N
C2119
10uF
10V
HDMI_RX2N_0
HDMI_RX2-_URSA9_0_RP
VBY1_RXP[3]
AB2
C2193
10uF
10V
D1
HDMI_CLK+_URSA9_0_RP
AL30
AG31
4th Layer
C2104
10uF
10V
AM31
AG30
AVDD_MOD
L2102
BLM18PG121SN1D
TXDBP1_L
AL29
Close to Chip side
IC2500
LGE7411(URSA9)
TXDBP7_L
H3
AE2
C2151
10uF
10V
C13302
0.1uF
16V
AL20
G3
C13036
C2192
0.1uF
16V
AL19
RE4P
0.1uF
4st Layer
AVDD_PLL
RB1P
R1996
22
N4
R1997
22
M4
N1
HDMI_CLK+
P1
HDMI_CLK-
N3
HDMI_RX0+
N2
HDMI_RX0-
M3
HDMI_RX1+
M2
HDMI_RX1-
L1
HDMI_RX2+
L2
HDMI_RX2-
L2106
BLM18PG121SN1D
HDMITX_SCL
C2117
0.1uF
16V
HDMITX_SDA
HDMI_TXCP
C2125
0.1uF
16V
C13312
4.7uF
10V
C2152
10uF
10V
C13303
0.1uF
16V
C13313
4.7uF
10V
HDMI_TXCN
HDMI_TX0P
HDMI_TX0N
Close to Chip side
HDMI_TX1P
AVDDL_HDMI_TX_RX
HDMI_TX1N
HDMI_TX2P
L2107
BLM18PG121SN1D
HDMI_TX2N
C2118
0.1uF
16V
C2126
0.1uF
16V
C2131
0.1uF
16V
C13301
0.1uF
16V
C13308
10uF
10V
C13309
10uF
10V
GND Connection at Vx1 41pin wafer
AVDDL_LVDSRX
R12900 0
GND_Vx1_2
Non_LGD_Module
(pin 8)
R12901 0
GND_Vx1
(pin 5,11,14)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
L13300
BLM18PG121SN1D
C13300
0.1uF
16V
Non_UB95
BSD-14Y-UD-128-02-HD
2013.12.17
U_LVDS INPUT
LGE Internal Use Only
Vx1 LOCKAn/HTPDn
R13064
47K
R13063
1.5K
+1.8V
[51P Vx1
output wafer]
51pin_Wafer
LOCKAn
D
S
LOCKn_IN
[41P Vx1
output wafer]
Q1404
AO3438
G
P13000
FI-RE51S-HF-J-R1500
1
41pin_Wafer
2
TXDAP7_L
3
+1.8V
P13001
FI-RE41S-HF-J-R1500
TXDAN6_L
7
8
TXDAP5_L
9
TXDAN5_L
R209
4.7K
11
TXDAP4_L
12
TXDAN4_L
R221
0
URSA_TX_HTPD_Pullup
HTPDn_IN
R222
10K
URSA_TX_HTPD_Pullup
D9_I2C_SDA
Not Used Net (UB85/95/UC89)
HTPDAn
Q203
AO3438
URSA_TX_HTPD_Pullup
GND_Vx1
6
TXDBP11_L
7
TXDBN11_L
TXDBP11_L
TXDBN11_L
TXDBP10_L
8
GND_Vx1_2
TXDBN10_L
14
R220
0
OPT
TXDAP3_L
15
TXDAN3_L
17
TXDAP2_L
18
+3.3V_NORMAL
TXDAN2_L
19
20
R13034
10K
OPT
R13037
TXDAP1_L
+3.3V_NORMAL
21
9
TXDBP10_L
10
TXDBN10_L
TXDAN1_L
12
TXDBP9_L
13
TXDBN9_L
TXDBP8_L
TXDBN8_L
14
L/D_EN(Pin30)
- T-Con L/D Function
HIGH : Enable
LOW or NC : Disable
*LGD_120Hz: T240 module (UB98/95,D9)
0
TXDBP9_L
TXDBN9_L
11
16
GND_Vx1
L_DIM_EN
15
TXDBP8_L
16
TXDBN8_L
GND_Vx1_2
17
Non_AUO_Module
TXDAN0_L
25
HTPDn_IN
R13061
NON_D9_I2C
10K
Non_INX_Module
29
R13033
10K
R13019
4.7K
OPT
R13012 0
33
*Pin35(PCID)
High:PCID enable
Low or NC : PCID diable
3D_EN
3D_EN_LGD_120Hz
R13062
NON_D9_I2C
I2C_SDA7
R13059
37
R13005
Non_LGD_60Hz
R13000
0
*Pin38
Non_LGD_60Hz: T120 module(UB85)
PWM_TIN
G+
41
R13001
INV_CTL
45
46
47
48
49
R13009
0
R13002
Non_OLED & Non_AUO_Module
Non_OLED & Non_AUO_Module
42
44
27
TXDBP4_L
28
TXDBN4_L
30
TXDBP3_L
31
TXDBN3_L
33
TXDBP2_L
34
TXDBN2_L
R13016
0
Compensation_Done
36
TXDBP1_L
37
TXDBN1_L
38
LGD_Module
R13045
10K
LGD_Module
Compensation_Done
Data Input Format[1:0]
39
TXDBP0_L
40
TXDBN0_L
41
*Mode 3 (4 Division)
- Data Format 0(Pin37) = Low
Data Format 1(Pin36) = High
42
+3.3V_NORMAL
R13008
0
PWM_TOUT
R13040
10K
OPT
PANEL_VCC
51
0
Data_Format_1
OLED
R13010
0
50
35
R13044
10K
OPT
0
OLED
43
TXDBN5_L
+3.3V_NORMAL
39
40
TXDBP5_L
25
32
33 OPT
0
24
29
0
Non_AUO_Module
Q13005
2N7002A
36
38
Non_AUO_Module
TCON_I2C_EN
S
34
0
TXDBN6_L
23
D9_I2C_SDA
0
32
R13006
TXDBP6_L
22
26
+3.3V_NORMAL
D9_I2C
*Pin31(BIT_SEL)
HIGH or NC : 10Bit
LOW : 8Bit
I2C_SCL7
21
33 OPT
L13001
BLM18PG121SN1D
OLED
R13017
OPT
31
0
Q13004
2N7002A
R13055
EL_VDD_DETECT_22V
30
TXDBN7_L
20
D
R13011
TXDBP7_L
19
TCON_I2C_EN
D
LOCKn_IN
27
R13018
4.7K
OPT
R13013 0
R13004
10K
LGD_Module
S
26
18
D9_I2C_SCL
+3.3V_NORMAL
G
24
R13007
10K
Non_AUO_Module
G
R13003
10K
OPT
TXDAP0_L
D9_I2C
23
R13014 0
22
35
D9_I2C_SCL
3
5
13
28
2
4
S
10
1
R211
1.5K
G
6
+3.3V_NORMAL
D
TXDAP6_L
URSA_TX_HTPD_Pullup
5
URSA_TX_HTPD_Pullup
TXDAN7_L
4
*Mode 2 (2 Division)
- Data Format 0(Pin37) = High
Data Format 1(Pin36) = Low
G+
R13015
0
Data_Format_0
52
LGD_Module
L13000
MLB-201209-0120P-N2
51pin_12V
C13032
10uF
25V
51pin_12V
C13033
10uF
25V
51pin_12V
R13041
10K
LGD_Module
EL_VDD_DETECT_22V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-14Y-UD-130-HD
2013.12.17
Output_wafer
LGE Internal Use Only
IC2500
LGE7411(URSA9)
DDR PHY VREF
B_DDR3_A[0-15]
F14
D13
A_DDR3_A[3]
C14
A_DDR3_A[4]
F13
A_DDR3_A[5]
C13
A_DDR3_A[6]
B10
A_DDR3_A[7]
A12
A_DDR3_A[8]
C10
A_DDR3_A[9]
A14
A_DDR3_A[10]
B12
A_DDR3_A[11]
F15
A_DDR3_A[12]
C11
A_DDR3_A[13]
C12
A_DDR3_A[14]
D17
A_DDR3_A[15]
E14
A_DDR3_BA[0]
B14
A_DDR3_BA[1]
E15
A_DDR3_BA[2]
H27
A_DDR3_A0
B_DDR3_A0
A_DDR3_A1
B_DDR3_A1
A_DDR3_A2
B_DDR3_A2
A_DDR3_A3
B_DDR3_A3
A_DDR3_A4
B_DDR3_A4
A_DDR3_A5
B_DDR3_A5
A_DDR3_A6
B_DDR3_A6
A_DDR3_A7
B_DDR3_A7
A_DDR3_A8
B_DDR3_A8
A_DDR3_A9
B_DDR3_A9
A_DDR3_A10
B_DDR3_A10
A_DDR3_A11
B_DDR3_A11
A_DDR3_A12
B_DDR3_A12
A_DDR3_A13
B_DDR3_A13
A_DDR3_A14
B_DDR3_A14
A_DDR3_A15
B_DDR3_A15
A_DDR3_BA0
B_DDR3_BA0
A_DDR3_BA1
B_DDR3_BA1
A_DDR3_BA2
B_DDR3_BA2
C17
A_DDR3_CASZ
C16
A_DDR3_WEZ
F17
A_DDR3_ODT
C15
A_DDR3_CKE
B11
A_DDR3_RESET
A_DDR3_MCLK
B16
A16
A_DDR3_MCLKZ
C9
A_DDR3_CSB1
A9
A_DDR3_CSB2
A_DDR3_DQ[0-15]
A_DDR3_DQ[0]
D23
A_DDR3_DQ[1]
A19
A_DDR3_DQ[2]
E22
A_DDR3_DQ[3]
B18
A_DDR3_DQ[4]
C23
A_DDR3_DQ[5]
C18
B22
A_DDR3_DQ[6]
A18
A_DDR3_DQ[7]
A_DDR3_DQ[8]
E19
A_DDR3_DQ[9]
B21
A_DDR3_DQ[10]
F18
A_DDR3_DQ[11]
C22
A_DDR3_DQ[12]
D20
A_DDR3_DQ[13]
A_DDR3_DQ[14]
A_DDR3_DQ[15]
F22
E18
D22
B19
A_DDR3_DM0
E21
B_DDR3_A[2]
G29
B_DDR3_A[3]
H30
B_DDR3_A[4]
G27
B_DDR3_A[5]
G30
B_DDR3_A[6]
+1.5V_U_DDR
U_MVREFCA_A0
U_MVREFCA_A1
DDR_VTT_URSA_1
R13110
1K
1%
R13120
1K
1%
IC2600
H5TQ1G63EFR-RDC
B_DDR3_A[8]
D30
B_DDR3_A[9]
H32
B_DDR3_A[10]
F31
C13210
1000pF
C13222
0.1uF
R13121
1K
1%
C13230
1000pF
A_DDR3_RASZ
B_DDR3_RASZ
A_DDR3_CASZ
B_DDR3_CASZ
A_DDR3_WEZ
B_DDR3_WEZ
A_DDR3_ODT
B_DDR3_ODT
A_DDR3_CKE
A_DDR3_RESETB
A_DDR3_A[2]
B_DDR3_A[13]
A_DDR3_A[3]
A_DDR3_A[4]
L29
B_DDR3_A[15]
A_DDR3_MCLK
A_DDR3_MCLKZ
A_DDR3_CSB1
B_DDR3_CSB1
A_DDR3_CSB2
B_DDR3_CSB2
A_DDR3_DQ0
B_DDR3_DQ0
A_DDR3_DQ1
B_DDR3_DQ1
A_DDR3_DQ2
B_DDR3_DQ2
A_DDR3_DQ3
B_DDR3_DQ3
A_DDR3_DQ4
B_DDR3_DQ4
A_DDR3_DQ5
B_DDR3_DQ5
A_DDR3_DQ6
B_DDR3_DQ6
A_DDR3_DQ7
B_DDR3_DQ7
A_DDR3_DQ8
B_DDR3_DQ8
A_DDR3_DQ9
B_DDR3_DQ9
A_DDR3_DQ10
B_DDR3_DQ10
A_DDR3_DQ11
B_DDR3_DQ11
A_DDR3_DQ12
B_DDR3_DQ12
A_DDR3_DQ13
B_DDR3_DQ13
A_DDR3_DQ14
B_DDR3_DQ14
A_DDR3_DQ15
B_DDR3_DQ15
A_DDR3_DM0
P2
R8
R2
A_DDR3_A[7]
B_DDR3_BA[1]
A_DDR3_A[8]
B_DDR3_BA[2]
A_DDR3_A[9]
B_DDR3_RASZ
L27
T8
R3
L7
R7
A_DDR3_A[11]
B_DDR3_CASZ
A_DDR3_A[12]
B_DDR3_WEZ
A_DDR3_A[13]
B_DDR3_CKE
E31
N7
T3
A0
K32
+1.5V_U_DDR
A1
U_MVREFCA_B0
U_MVREFCA_B1
A_DDR3_MCLK
C13233
B_DDR3_CSB2
U29
B_DDR3_DQ[0]
N32
B_DDR3_DQ[1]
T28
B_DDR3_DQ[2]
M31
B_DDR3_DQ[3]
B_DDR3_DQ[0-15]
R13108
1K
1%
0.01uF
R13118
1K
1%
H1
A3
K7
K9
A_DDR3_CKE
R13109
1K
1%
C13201
0.1uF
R13119
1K
1%
C13221
0.1uF
C13229
1000pF
A_DDR3_CSB1
T31
B_DDR3_DQ[6]
A_DDR3_RASZ
M32
B_DDR3_DQ[7]
A_DDR3_CASZ
N28
B_DDR3_DQ[8]
A_DDR3_WEZ
R31
B_DDR3_DQ[9]
A5
L8
A6
T27
L3
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_8
BA0
A_DDR3_DQS1
B7
C20
A_DDR3_DQS1
C19
A_DDR3_DQ[16-31]
A_DDR3_DQS1
B_DDR3_DQS1
A_DDR3_DQS1B
A_DDR3_DQS1B
A_DDR3_DQ[16]
B27
A_DDR3_DQ[17]
A24
A_DDR3_DQ[18]
C27
A_DDR3_DQ[19]
C24
A_DDR3_DQ[20]
A28
A_DDR3_DQ[21]
E24
A_DDR3_DQ[22]
B28
A_DDR3_DQ[23]
B23
A_DDR3_DQ[24]
D25
A_DDR3_DQ[25]
E27
A_DDR3_DQ[26]
C25
A_DDR3_DQ[27]
D28
A_DDR3_DQ[28]
E26
A_DDR3_DQ[29]
E28
A_DDR3_DQ[30]
E25
A_DDR3_DQ[31]
C28
B24
A_DDR3_DM2
B26
N30
B_DDR3_DQS1B
A_DDR3_DQ16
B_DDR3_DQ16
A_DDR3_DQ17
B_DDR3_DQ17
A_DDR3_DQ18
B_DDR3_DQ18
A_DDR3_DQ19
B_DDR3_DQ19
A_DDR3_DQ20
B_DDR3_DQ20
A_DDR3_DQ21
B_DDR3_DQ21
A_DDR3_DQ22
B_DDR3_DQ22
A_DDR3_DQ23
B_DDR3_DQ23
A_DDR3_DQ24
B_DDR3_DQ24
A_DDR3_DQ25
B_DDR3_DQ25
A_DDR3_DQ26
B_DDR3_DQ26
A_DDR3_DQ27
B_DDR3_DQ27
A_DDR3_DQ28
B_DDR3_DQ28
A_DDR3_DQ29
B_DDR3_DQ29
A_DDR3_DQ30
B_DDR3_DQ30
A_DDR3_DQ31
B_DDR3_DQ31
A_DDR3_DM2
D26
A_DDR3_DQS3
C26
B_DDR3_DQS1B
A_DDR3_DQ[1]
F7
A_DDR3_DQ[2]
F2
A_DDR3_DQ[3]
F8
A_DDR3_DQ[4]
H3
A_DDR3_DQ[5]
H8
A_DDR3_DQ[6]
G2
A_DDR3_DQ[7]
H7
AA31
B_DDR3_DQ[16]
V32
B_DDR3_DQ[17]
AA30
B_DDR3_DQ[18]
V30
B_DDR3_DQ[19]
AB32
B_DDR3_DQ[20]
V28
B_DDR3_DQ[21]
AB31
B_DDR3_DQ[22]
U31
B_DDR3_DQ[23]
W29
B_DDR3_DQ[24]
AA28
B_DDR3_DQ[25]
W30
B_DDR3_DQ[26]
AB29
B_DDR3_DQ[27]
Y28
B_DDR3_DQ[28]
AB28
B_DDR3_DQ[29]
W28
B_DDR3_DQ[30]
AB30
B_DDR3_DQ[31]
B_DDR3_DQ[16-31]
+1.5V_U_DDR
CK
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
A_DDR3_DQS3
R13112
1K
R13102
1K
A_DDR3_RESET
A_DDR3_DQ[8]
D7
A_DDR3_DQ[9]
C3
A_DDR3_DQ[10]
C8
A_DDR3_DQ[11]
A_DDR3_DQ[12]
A_DDR3_DQ[13]
A_DDR3_DQ[14]
A_DDR3_DQ[15]
A_DDR3_A[10]
K2
A_DDR3_A[11]
K8
A_DDR3_A[12]
N1
A_DDR3_A[13]
N9
A_DDR3_A[14]
R1
L7
R7
N7
T3
NC_2
NC_4
DQSL
C2
A7
A2
B8
A3
A2
A3
A5
A6
A8
M3
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_6
VDD_8
BA0
C9
K7
A_DDR3_MCLKZ
D2
K9
A_DDR3_CKE
H2
A_DDR3_ODT
H9
A_DDR3_RASZ
K1
J3
K3
L3
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
WE
A_DDR3_WEZ
J9
RESET
A_DDR3_RESET
NC_2
L9
NC_3
T7
NC_4
A_DDR3_A[14]
NC_6
F3
A_DDR3_DQS2
G3
K8
N1
N9
R1
R9
DQSL
A8
C1
C9
D2
E9
F1
H2
H9
J1
NC_1
T2
L1
K2
+1.5V_U_DDR
VDDQ_2
L2
A_DDR3_CSB2
G7
A1
CK
E9
F1
+1.5V_U_DDR
D9
VDD_9
VDDQ_1
J7
A_DDR3_MCLK
240
1%
BA1
A8
C1
VDD_7
BA2
A_DDR3_BA[2]
R13134
B2
A9
M2
A_DDR3_BA[1]
L8
ZQ
A7
R9
N8
H1
VREFDQ
A4
NC_5
A_DDR3_BA[0]
VREFCA
A1
M7
A_DDR3_A[15]
J1
NC_1
M8
A0
J9
L1
L9
T7
A_DDR3_A[14]
NC_6
DQSL
A9
DQSU
VSS_1
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
C7
B3
A_DDR3_DQS3
E1
A_DDR3_DQS3B
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
DQSU
VSS_2
VSS_3
E7
J2
A_DDR3_DM2
J8
A_DDR3_DM3
M1
A_DDR3_DQ[16-31]
M9
P1
P9
T1
T9
B1
DQU0
VSS_1
G8
DQL6
VSSQ_1
B7
A9
DQSU
D3
A_DDR3_DQ[16]
E3
A_DDR3_DQ[17]
F7
A_DDR3_DQ[18]
F2
A_DDR3_DQ[19]
F8
A_DDR3_DQ[20]
H3
A_DDR3_DQ[21]
H8
A_DDR3_DQ[22]
G2
A_DDR3_DQ[23]
H7
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
B9
D8
E2
E8
F9
G1
G9
A_DDR3_DQ[24]
D7
A_DDR3_DQ[25]
C3
A_DDR3_DQ[26]
C8
A_DDR3_DQ[27]
C2
A_DDR3_DQ[28]
A7
A_DDR3_DQ[29]
A2
A_DDR3_DQ[30]
B8
A_DDR3_DQ[31]
A3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQL6
DQL7
D1
B3
B1
VSSQ_1
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
B_DDR3_CKE
B_DDR3_DM2
R13113
B_DDR3_DM3
1K
R13103
1K
B_DDR3_DQS2
B_DDR3_RESET
B_DDR3_DQS2B
Y29
B_DDR3_DQS3
R3
A_DDR3_CASZ
A_DDR3_CKE
+1.5V_U_DDR
W32
B_DDR3_DQS2B
T8
A_DDR3_A[9]
G7
A1
VDDQ_1
DQL7
W31
B_DDR3_DQS2
A_DDR3_DQS2B
A_DDR3_DQS3B
A_DDR3_DQS3B
B_DDR3_DQS1
E3
B_DDR3_DM3
A_DDR3_DQS2
D3
A_DDR3_DQ[0]
Y31
B25
A25
A_DDR3_DQ[0-15]
V31
B_DDR3_DM2
A_DDR3_DM3
A_DDR3_DM3
A_DDR3_DQS2
A_DDR3_DQS2B
A_DDR3_DM0
A_DDR3_DM1
B_DDR3_DQS0B
P30
R2
A_DDR3_A[7]
A_DDR3_A[8]
D9
+1.5V_U_DDR
DQSU
A_DDR3_DQS1B
B_DDR3_DQS0
P31
B_DDR3_DQS0B
R8
A_DDR3_A[6]
BA1
B_DDR3_DM1
B_DDR3_DQS0
A_DDR3_DQS0B
P2
VDD_9
C7
R32
A_DDR3_DQS0
P8
A_DDR3_DQS2B
B_DDR3_DM0
R28
VDD_7
E7
B20
N2
DQSL
A_DDR3_DQS0B
B_DDR3_DQ[15]
B_DDR3_DM1
VDD_6
NC_3
N31
A21
A_DDR3_DQS0
A_DDR3_DQS0B
1%
B2
A9
RESET
G3
P3
A_DDR3_A[5]
+1.5V_U_DDR
A8
WE
A_DDR3_DQS0
240
A7
F3
B_DDR3_DQ[14]
T29
K3
A_DDR3_RESET
B_DDR3_DQ[13]
M28
J3
R13126
ZQ
T2
B_DDR3_DQ[10]
B_DDR3_DQ[12]
K1
A_DDR3_ODT
P7
A_DDR3_A[4]
L2
C13209
1000pF
N3
A_DDR3_A[3]
J7
B_DDR3_DQ[4]
B_DDR3_DQ[11]
IC2700
H5TQ1G63EFR-RDC
AR13112
100
A_DDR3_A[2]
VREFDQ
A4
BA2
A_DDR3_MCLKZ
B_DDR3_DQ[5]
P29
M3
A_DDR3_BA[2]
M30
T30
N8
A_DDR3_BA[1]
U30
M27
AR13110
100
A_DDR3_A[1]
A2
NC_5
A_DDR3_BA[0]
B_DDR3_CSB1
C32
AR13108
100
A_DDR3_A[0]
M2
+1.5V_U_DDR
B_DDR3_MCLKZ
C30
AR13106
100
VREFCA
M7
A_DDR3_A[15]
B_DDR3_RESET
B_DDR3_MCLK
K31
AR13104
100
M8
B_DDR3_ODT
J30
B_DDR3_DM0
P8
A_DDR3_A[10]
K30
B_DDR3_MCLKZ
N2
A_DDR3_A[5]
B_DDR3_BA[0]
L30
B_DDR3_MCLK
P3
A_DDR3_A[6]
J28
B_DDR3_RESETB
P7
A_DDR3_A[1]
B_DDR3_A[11]
B_DDR3_A[12]
B_DDR3_A[14]
H28
B_DDR3_CKE
N3
A_DDR3_A[0]
F30
H31
AR13102
100
U_MVREFCA_A1
C13202
0.1uF
R13111
1K
1%
E30
J27
AR13100
100
U_MVREFCA_A0
B_DDR3_A[7]
F32
L28
A_DDR3_DM1
A_DDR3_DM1
+1.5V_U_DDR
B_DDR3_A[1]
G28
D31
E17
A_DDR3_RASZ
B_DDR3_A[0]
G31
56
E13
56
B13
A_DDR3_A[1]
R13123R13122
A_DDR3_A[0]
A_DDR3_A[2]
B_DDR3_DQS3
Y30
B_DDR3_DQS3B
B_DDR3_DQS3B
* DDR_VTT
DDR_VTT_URSA_0
+1.5V_U_DDR
+3.3V_NORMAL
IC13100
TPS51200DRCR
REFIN
VLDOIN
DDR_VTT_URSA
C13123
22uF
10V
VO
VOSNS
C13110
10uF
2
9
3
8
4
7
5
6
L13101
CIS21J121
C13199
10uF
10V
AR13101
100
PGOOD
EN
B_DDR3_A[1]
B_DDR3_A[2]
REFOUT
B_DDR3_A[3]
C13147
0.1uF
B_DDR3_A[4]
B_DDR3_A[5]
B_DDR3_A[6]
B_DDR3_A[7]
B_DDR3_A[8]
B_DDR3_A[9]
B_DDR3_A[10]
B_DDR3_A[11]
B_DDR3_A[12]
B_DDR3_A[13]
DDR_VTT_URSA
DDR_VTT_URSA_0
L13102
BLM18PG121SN1D
B_DDR3_A[15]
C13189
0.1uF
16V
C13151
0.1uF
16V
B_DDR3_BA[0]
0.01uF
56
C13234
DDR_VTT_URSA_1
L13103
BLM18PG121SN1D
56
B_DDR3_MCLK
DDR_VTT_URSA
N3
P7
P3
N2
B_DDR3_BA[1]
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
C13158
0.1uF
16V
C13174
0.1uF
16V
A3
N8
M3
K9
C13106
0.1uF
16V
B_DDR3_CASZ
L8
ZQ
K1
J3
K3
L3
A9
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_6
VDD_7
VDD_8
VDDQ_1
VDDQ_2
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
B_DDR3_DQS0
G3
NC_2
NC_4
B7
D3
Close to DDR Power pin
C13117
0.1uF
16V
C13128
0.1uF
16V
C13137
0.1uF
16V
C13146
0.1uF
16V
C13156
0.1uF
16V
C13164
0.1uF
16V
C13172
1uF
25V
C13178
0.1uF
16V
C13186
0.1uF
16V
C13194
10uF
10V
C13198
0.1uF
16V
C13206
0.1uF
16V
C13214
0.1uF
16V
C13218
0.1uF
16V
C13226
1uF
25V
B_DDR3_DQ[0]
E3
B_DDR3_DQ[1]
F7
B_DDR3_DQ[2]
F2
B_DDR3_DQ[3]
F8
B_DDR3_DQ[4]
H3
B_DDR3_DQ[5]
H8
B_DDR3_DQ[6]
G2
B_DDR3_DQ[7]
H7
B_DDR3_DQ[8]
D7
B_DDR3_DQ[10]
B_DDR3_DQ[11]
B_DDR3_DQ[12]
B_DDR3_DQ[13]
B_DDR3_DQ[14]
B_DDR3_DQ[15]
+1.5V_U_DDR
C13102
0.1uF
16V
Close to DDR Power pin
C13107
0.1uF
16V
C13115
1uF
25V
C13126
0.1uF
16V
C13135
0.1uF
16V
C13144
0.1uF
16V
C13154
0.1uF
16V
C13162
10uF
10V
C13170
0.1uF
16V
C13176
0.1uF
16V
C13184
0.1uF
16V
C13192
0.1uF
16V
C13196
0.1uF
16V
C13204
0.1uF
16V
C13212
1uF
25V
C13216
0.1uF
16V
C13224
0.1uF
16V
C13232
0.1uF
16V
C13100
10uF
10V
T3
B_DDR3_A[14]
B_DDR3_A[15]
N1
VSS_2
VSS_3
DML
VSS_4
VSS_5
VSS_6
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
C3
C8
C2
A7
A2
B8
A3
A1
A2
A3
A5
A6
R1
R9
B_DDR3_BA[1]
N8
M3
A9
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_6
A1
A8
B_DDR3_MCLKZ
K7
K9
B_DDR3_CKE
C1
C9
D2
E9
B_DDR3_ODT
F1
B_DDR3_RASZ
H2
B_DDR3_CASZ
H9
B_DDR3_WEZ
K1
J3
K3
L3
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
RESET
NC_2
NC_3
NC_4
F3
L9
B_DDR3_DQS2
T7
B_DDR3_DQS2B
G3
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
DQSL
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
N9
R1
R9
+1.5V_U_DDR
A8
C1
C9
D2
E9
F1
H2
H9
J9
L1
L9
T7
NC_6
B_DDR3_A[14]
B_DDR3_A[14]
A9
DQSU
VSS_1
DQSU
VSS_2
VSS_3
E7
E1
B_DDR3_DM2
G8
B_DDR3_DM3
J2
B7
B_DDR3_DQS3B
B3
B_DDR3_DQ[16-31]
D3
B_DDR3_DQ[16]
E3
J8
B_DDR3_DQ[17]
F7
M1
B_DDR3_DQ[18]
F2
M9
B_DDR3_DQ[19]
F8
P1
B_DDR3_DQ[20]
H3
P9
B_DDR3_DQ[21]
T1
B_DDR3_DQ[22]
T9
B_DDR3_DQ[23]
VSS_12
VSSQ_1
N1
DQSL
H8
G2
H7
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
DQL7
B_DDR3_DQ[24]
D7
B1
B_DDR3_DQ[25]
C3
B9
B_DDR3_DQ[26]
C8
D1
D8
E2
E8
F9
G1
B_DDR3_DQ[27]
B_DDR3_DQ[28]
B_DDR3_DQ[29]
B_DDR3_DQ[30]
B_DDR3_DQ[31]
C2
A7
A2
B8
A3
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQL6
DQL6
DQU0
K8
J1
NC_1
J9
L1
K2
A1
CK
WE
B_DDR3_RESET
G7
VDD_9
VDDQ_1
L2
B_DDR3_CSB2
D9
BA1
J7
B_DDR3_MCLK
VDD_7
VDD_8
BA0
240
1%
B2
BA2
B_DDR3_BA[2]
R13135
+1.5V_U_DDR
A8
M2
B_DDR3_BA[0]
L8
ZQ
A7
NC_5
N9
H1
VREFDQ
A4
M7
A9
VSS_1
DQL7
B_DDR3_DQ[9]
N7
B_DDR3_A[13]
K8
B_DDR3_DQS3
DQSU
DMU
B_DDR3_DM1
+1.5V_U_DDR
R7
VREFCA
C7
DQSU
E7
B_DDR3_DQ[0-15]
L7
B_DDR3_A[12]
K2
NC_6
C7
B_DDR3_DQS1B
B_DDR3_DM0
B_DDR3_A[9]
DQSL
B_DDR3_DQS0B
B_DDR3_DQS1
R3
B_DDR3_A[11]
G7
J1
NC_1
DQSL
T8
M8
A0
T2
NC_3
Decap removed
R2
+1.5V_U_DDR
CK
F3
R8
B_DDR3_A[10]
VDD_9
CK
RESET
B_DDR3_RESET
P2
B_DDR3_A[8]
D9
BA1
T2
P8
B_DDR3_A[7]
240
1%
B2
WE
B_DDR3_WEZ
R13127
+1.5V_U_DDR
A8
L2
B_DDR3_CSB1
N2
B_DDR3_A[5]
A7
BA0
P3
B_DDR3_A[6]
A5
A6
P7
B_DDR3_A[2]
VREFDQ
BA2
K7
B_DDR3_RASZ
C13109
0.1uF
16V
N3
B_DDR3_A[4]
H1
A4
J7
B_DDR3_ODT
C13104
0.1uF
16V
IC2900
H5TQ1G63EFR-RDC
AR13113
100
B_DDR3_A[3]
A2
NC_5
B_DDR3_CKE
C13132
0.1uF
16V
AR13111
100
B_DDR3_A[1]
VREFCA
A1
M7
B_DDR3_BA[2]
B_DDR3_MCLKZ
C13112
1uF
25V
AR13109
100
U_MVREFCA_B1
M8
A0
M2
C13105
0.1uF
16V
R13125R13124
C13179
0.1uF
16V
AR13107
100
B_DDR3_A[0]
Close to REFOUT pin
C13181
1uF
25V
AR13105
100
U_MVREFCA_B0
C13150
4700pF
GND
C13111 C13113
10uF
10uF
AR13103
100
IC2800
H5TQ1G63EFR-RDC
VIN
B_DDR3_A[0]
PGND
L13100
CIS21J121
[EP]
10
1
11
R13101 C13122
10K
1000pF
1%
THERMAL
R13100
10K 1%
B1
VSSQ_1
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
G9
C13101
10uF
10V
4th layer
+1.5V_U_DDR
Close to DDR Power pin
Decap removed
C13103
0.1uF
16V
C13108
0.1uF
16V
C13116
0.1uF
16V
BSD-14Y-UD-131-HD
+1.5V_U_DDR
Close to DDR Power pin
Decap removed
C13195
0.1uF
16V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
2013.12.17
4th layer
URSA7_DDR
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
+3.3V_NORMAL
LGD_Module
R1911 10K
URSA_BIT0_1
R1913 10K
URSA_BIT1_1
R1915 10K
URSA_BIT2_1
R1917 10K
OS_Module
R1912
10K
URSA_BIT0_0
R1914
10K
URSA_BIT1_0
R1916
10K
URSA_BIT2_0
R1918
10K
URSA_RX_LVDS
R1909 10K
OPT
R13215 10K
Div_BIT1_1
R13213 10K
Div_BIT1_0
R13214 10K
OPT
R13217 10K
Div_BIT0_1
R13202 10K
Non Division
0/1
2 Division
1/0
4 Division
1/1
8 Division
URSA_OPT_6
Div_BIT0
Division Type
Div_BIT1
URSA_OPT_4
URSA_OPT_0
URSA_RESET
URSA_OPT_1
BIT [2/1/0]
Module Type
Rx Interface
Tx Lane
Tx Lane
URSA_BIT0
0/0/0
0
R1930
XO_URSA
URSA_RESET_MICOM
0
R13221
URSA_RESET_MICOM
4K@120 (16lane)
0/0/1
4k@60 (8lane)
0/1/0
5k@120 (20lane)
0/1/1
OLED ULTRA HD
1/0/0
FHD@120 (4lane)
1/0/1
FHD@60 (2lane)
1/1/0
Reserved
1/1/1
Reserved
URSA_BIT1
URSA_BIT2
URSA_RX_VX1
R1910
10K
URSA_RESET_SoC
Reserved
R13216 10K
GND_2
Div_BIT0_0
R13212 10K
R1919
10K
URSA9_RST_PULLUP
0
R1924
D1900
1N4148W
24MHz
X1900
4
R1925
1M
3
0/0
Reserved
R13220 10K
X-TAL_1
GND_1
3
2
Module Division
URSA_OPT_5
+3.3V_NORMAL
OPT
C1996
22uF
10V
XIN_URSA
1
2
1
4
X-TAL_2
BIT [1/0]
SW1901
JTP-1127WEM
Reserved
R13218 10K
LM14_URSA9_crystalcap
C1993
8pF
50V
URSA Reset
+3.3V_NORMAL
100V
R1923
10K
C1992
8pF
50V
Clock for URSA9
OPT
R13219 10K
URSA9 Option
10K
R13226
URSA9_PQ_DEBUG
IC2500
LGE7411(URSA9)
+3.3V_NORMAL
URSA9_PQ_DEBUG
IC1901-*1
W25Q32BVSSIG
SPI Flash
/CS
DO[IO1]
/WP[IO2]
+3.3V_NORMAL
GND
IC1901
MX25L3206EM2I-12G
1
8
2
7
3
6
4
5
P1906
12507WS-04L
/HOLD[IO3]
33
2
SO/SIO1
33
SPI_DO_URSA9
FLASH_WP_URSA
2
7
WP#
1K
3
6
GND
4
5
AH24
AG24
C1995
0.1uF
16V
+3.3V_NORMAL
URSA9_SYS_DEBUG
HOLD#
12507WS-04L
1
SCLK
SPI_CK_URSA9
SI/SIO0
3
SPI_DI_URSA9
SPI2_CK/PWM0/GPIO56
I2CS_SCL
SPI2_DI/PWM1/GPIO57
SPI3_CK/DIM10/GPIO54
I2CM_SDA
A4
SPI3_DI/DIM11/GPIO55
SPI4_CK/DIM8/GPIO52
A5
Change pin from A5 to C4
URSA9_SYS_DEBUG
+3.3V_NORMAL
1K
R1954
OPT
C1997
0.1uF
16V
AD30
SPI_CK_URSA9
SPI_DI_URSA9
AR13200
33
AC31
AD29
SPI_DO_URSA9
DIM3/GPIO[35]
SPI_CK
DIM4/GPIO[36]
SPI_DI
DIM5/GPIO[37]
SPI_DO
33
R1981
AE28
OPT 33
R1933
AE27
10K
R1955
SPI_CZ
DIM6/GPIO[38]
INT_R20/GPIO[42]
GPIO44/TCON1
GPIO45/TCON2
C4
IRE
GPIO46/TCON3
GPIO47/TCON4
AD27
GPIO49/TCON6
GND_1
B6
Debugging for URSA9
B7
C5
C6
C7
I2C_S Port
D4
D5
P1905
12507WS-04L
D6
WAFER-STRAIGHT
URSA_DEBUG
OPT
10K
R1991
10K
R1990
E4
E5
2
1
I2C_SCL4
R1922
33
SCL2_+3.3V_DB
URSA_DEBUG
10K
4
R1907
R1921
10K
R1906
5
I2CS_SCL
R1958
0
URSA_MP
R1960
0
OPT
33
SDA2_+3.3V_DB
URSA_DEBUG
DIM2
OPT
D7
SW1902
JS2235S
10K
3
SCL2_+3.3V_DB
2
6
5
URSA_DEBUG_SW
3
4
3D_EN
R1937
10K
L_DIM_EN
OPT
R13203
33
I2C_SDA4
R1959
0
URSA_MP
I2CS_SDA
R1961
0
OPT
SDA2_+3.3V_DB
E6
E7
F4
F5
M5
M6
M7
N5
R7
P7
N7
N6
DIM0
AG20
+3.3V_NORMAL
DIM1
AH23
OPT
R13204
10K
DIM2
AH20
AG21
URSA_OPT_1
AH22
R13205
10K
URSA_BIT0
AG22
URSA_BIT1
AH21
URSA_BIT2
B3
A2
C3
B2
B1
C2
C1
GPIO50/TCON7
GND_2
AG4
GPIO[18]/TCON8
A7
DIM1
33
R1935
33
R1934
A3
GPIO43/TCON0
AC27
R1908
AG26
DIM7/GPIO[39]
GPIO48/TCON5
10K
R1902
AG27
INT_R21/GPIO[41]
URSA9 UART1_RX
OPT
URSA_OPT_6
AG23
DIM0/GPIO[32]
DIM2/GPIO[34]
URSA9_SYS_DEBUG
1
OPT
R1936
10K
URSA_OPT_5
AH27
AF28
DIM1/GPIO[33]
AD28
SPI_CZ_URSA9
33
DIM0
+3.3V_NORMAL
URSA_OPT_4
AG28
VSYNC_LIKE/PWM5/GPIO40
GPIO[2][UART1_TX]
GPIO[3][UART1_RX]
33
R13224
+3.3V_NORMAL
Div_BIT1
AF27
B5
R13225
TCON_I2C_EN Ready
URSA9_SYS_DEBUG
Debug/ISP ADDR
Slave (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3’d7:111:boot from SPI Flash
Module Division OPT
Div_BIT0
AJ29
OPT
GPIO[0][UART2_TX]
GPIO[1][UART2_RX]
4
Chip Config
URSA_OPT_0
AJ27
SPI4_DI/DIM9/GPIO53
B4
U_SPI_WP_f_SoC
5
I2CS_SDA
I2CM_SCL/VSYNC_LIKE1
C1998
0.1uF
16V
URSA9_PQ_DEBUG
5
AH25
AH28
SPI1_CK/PWM2/GPIO58
SPI1_DI/PWM3/GPIO59
AH26
33
4
2
1K
R1932
AR13201
33
C1991
47pF
50V
OPT
R13223
DI[IO0]
U_SPI_WP_f_URSA
FRC_FLASH_WP
C1990
47pF
50V
OPT
3
10K R1903
R1905
R13222 I2CS_SDA
I2CS_SCL
URSA9_PQ_DEBUG
CLK
P1907
R1904
XTALI
URSA9_PQ_DEBUG
VCC
XTALO
AJ24
10K
R13227
1
8
SPI_4MB_MACRONIX
R4
XO_URSA
I2C_HSC_SDA/VSYNC_LIKE2
I2C_HSC_SCL/VSYNC_LIKE3
R3
XIN_URSA
1
URSA9_SYS_DEBUG
CS#
AG25
RESET
VCC
SPI_4MB_Winbond
SPI_CZ_URSA9
AF29
URSA_RESET
NC_1
GPIO[19]/TCON9
NC_2
GPIO[20]/TCON10
NC_3
GPIO[21]/TCON11
NC_4
GPIO[22]/TCON12
NC_5
GPIO[23]/TCON13
NC_6
GPIO24/TCON14
NC_7
GPIO25/TCON15
NC_8
NC_9
GPIO[4]
NC_10
GPIO[5]
NC_11
GPIO[6]
NC_12
GPIO[7]
NC_13
GPIO[8]
NC_14
GPIO[9]
NC_15
GPIO[10]/PWM_DIM_IN[0]
NC_16
GPIO[11]/PWM_DIM_IN[1]
NC_17
GPIO[12]
NC_18
GPIO[13]
NC_19
GPIO[14]
NC_20
GPIO[15]
NC_21
GPIO[16]
NC_22
GPIO[17]
AG5
HDMI OUTPUT_SIL9617 DDC to URSA9_1
AH4
AH5
AH6
AJ4
AJ5
AJ6
AH16
R13210
0
AG16
R13211
0
Data_Format_1
Data_Format_0
HDMI OUTPUT_R9531AN DDC to URSA9_0
Y5
RXBSCL_URSA9
Y4
RXBSDA_URSA9
AB4
AB5
AG17
AH17
AG18
AJ20
AH18
For DFT JIG
OPT
R13207
OPT
R13208
33
R13206
100K
R13209
100K
33
10K
R13201
URSA_RX_Vx1_HTPDn
R13200
10K
URSA_RX_Vx1_HTPDn
URSA9_Vx1_RX_HTPD_GPIO
URSA9_CONNECT
AG19
LOCKAn_OSD
AH19
LOCKAn_Video
AJ21
FLASH_WP_URSA
NC_23
NC_24
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-14Y-UD-132-HD
2013.12.17
LGE Internal Use Only
IC2500
LGE7411(URSA9)
IC2500
LGE7411(URSA9)
D18
A8
B8
C8
D8
E8
F8
G8
H8
J8
K8
IC2500
LGE7411(URSA9)
L8
M8
N8
VDDC
P8
A6
M9
M10
M11
N9
N10
N11
P9
P10
P11
R9
R10
R11
T9
T10
T11
U9
U10
U11
V9
V10
V11
W9
W10
W11
Y9
VDDC_1
VSS_1
VDDC_2
VSS_2
VDDC_3
VSS_3
VDDC_4
VSS_4
VDDC_5
VSS_5
VDDC_6
VSS_6
VDDC_7
VSS_7
VDDC_8
VSS_8
VDDC_9
VSS_9
VDDC_10
VSS_10
VDDC_11
VSS_11
VDDC_12
VSS_12
VDDC_13
VSS_13
VDDC_14
VSS_14
VDDC_15
VSS_15
VDDC_16
VSS_16
VDDC_17
VSS_17
VDDC_18
VSS_18
VDDC_19
VSS_19
VDDC_20
VSS_20
VDDC_21
VSS_21
VDDC_22
VSS_22
VDDC_23
VSS_23
VDDC_24
VSS_24
VDDC_25
VSS_25
VDDC_26
VSS_26
VSS_27
VSS_28
AVDDL_HDMI_TX_RX
K1
R8
T1
T8
K2
U8
P2
V8
T2
AF2
K3
W8
Y8
AA8
T3
AF3
AD8
G4
AE8
H4
AF8
J4
AG8
K4
AH8
P4
AJ8
U4
V4
B9
D9
E9
W4
F9
AA4
G9
AC4
H9
AD4
J9
AE4
K9
AF4
L9
G5
J5
L4
AVDDL_LVDSRX
AA9
AA10
AB9
AVDDL_HDMITX_2
VSS_31
AVDDL_RX_1
VSS_32
AVDDL_RX_2
VSS_33
AVDDL_RX_3
VSS_34
Y11
AE9
L5
AF9
R5
AH9
AJ9
DVDD_DDR
VSS_35
AVDDL_DVI_2
VSS_36
VSS_37
M14
N14
AVDDL_MOD
DVDD_DDR_1
VSS_38
DVDD_DDR_2
VSS_39
VSS_40
Y20
Y21
Y22
AA19
AA20
AVDDL_DRV
AA21
AA22
AB20
AB21
AB22
AVDDL_MOD_1
VSS_41
AVDDL_MOD_2
VSS_42
AVDDL_MOD_3
VSS_43
AVDDL_MOD_4
VSS_44
AVDDL_MOD_5
VSS_45
AVDDL_DRV_1
VSS_46
U5
D10
V5
E10
AVDDL_DRV_3
AVDDL_DRV_4
AVDDL_DRV_5
AC20
AC21
AD21
AD20
VDDP
AD18
AC12
AC13
AD15
AC16
AC17
AD16
VSS_49
VSS_51
AVDD_MOD_2
VSS_52
AVDD_MOD_3
VSS_53
AVDD_MOD_LDO
VSS_54
VSS_55
VDDP_1
VSS_56
VDDP_2
VSS_57
VDDP_3
VSS_58
VSS_59
AD11
AD12
VSS_48
AVDD_MOD_1
AC18
AD17
VSS_47
VSS_50
AVDD_MOD
AVDD_DVI_1
AA5
H10
AC5
J10
AD5
K10
AE5
L10
AF5
AB10
F6
AC10
G6
AD10
H6
AE10
J6
AF10
K6
L6
AG10
AH10
P6
A11
R6
D11
T6
E11
U6
F11
V6
G11
W6
H11
Y6
J11
AA6
K11
AB6
AC6
AD6
L11
AA11
AB11
AE6
AC11
AF6
AE11
AG6
VSS_60
AF11
AG11
AVDD_DVI_2
AVDD_HDMITX_1
VSS_61
AVDD_HDMITX_2
VSS_62
AVDD_RX_1
VSS_63
AVDD_RX_2
VSS_64
AVDD_RX_3
VSS_65
AVDD_RX_4
VSS_66
F7
AH11
G7
AJ11
H7
J7
K7
L7
AD14
AC14
E12
F12
AC15
M18
M19
M20
M21
M16
M17
P22
R22
N21
N22
J12
AVDD_PLL_2
VSS_67
AVDD_DDR0_1
VSS_68
AVDD_DDR0_2
VSS_69
AVDD_DDR0_3
VSS_70
AVDD_DDR0_4
VSS_71
AVDD_DDR0_5
VSS_72
AVDD_DDR0_6
VSS_73
VSS_74
P21
R21
H12
AVDD_XTAL
AVDD_PLL_1
AVDD_DDR1_1
VSS_75
AVDD_DDR1_2
VSS_76
AVDD_DDR1_3
VSS_77
AVDD_DDR1_4
VSS_78
AVDD_DDR1_5
VSS_79
AVDD_DDR1_6
VSS_80
VSS_190
VSS_86
VSS_191
VSS_87
VSS_192
VSS_88
VSS_193
VSS_89
VSS_194
VSS_90
VSS_195
VSS_91
VSS_196
VSS_92
VSS_197
VSS_93
VSS_198
VSS_94
VSS_199
VSS_95
VSS_200
VSS_96
VSS_201
VSS_97
VSS_202
VSS_98
VSS_203
VSS_99
VSS_204
VSS_100
VSS_205
VSS_101
VSS_206
VSS_207
VSS_102
VSS_208
VSS_103
VSS_209
VSS_104
VSS_210
VSS_105
VSS_211
VSS_106
VSS_212
VSS_107
VSS_213
VSS_108
VSS_214
VSS_109
VSS_215
VSS_110
VSS_216
VSS_111
VSS_217
VSS_112
VSS_218
VSS_113
VSS_219
VSS_114
VSS_220
VSS_115
VSS_221
VSS_116
VSS_222
VSS_117
VSS_223
T7
K12
U7
L12
V7
M12
W7
N12
Y7
P12
AA7
R12
AB7
T12
AC7
U12
AD7
V12
AE7
W12
AF7
Y12
AG7
AA12
AH7
AB12
AJ7
N13
M13
U13
V13
W13
Y13
AA13
AB13
AD13
AE13
AF13
AG13
AH13
AJ13
G14
H14
J14
K14
L14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
AE14
AF14
AG14
AH14
AJ14
A15
B15
D15
G15
VSS_118
VSS_225
VSS_119
VSS_226
VSS_120
VSS_227
VSS_121
VSS_228
VSS_122
VSS_229
AE12
AF12
AG12
AH12
AJ12
VSS_230
VSS_231
VSS_124
VSS_232
VSS_125
VSS_233
VSS_126
VSS_234
VSS_127
VSS_235
VSS_128
VSS_236
VSS_129
VSS_237
VSS_130
VSS_238
VSS_131
VSS_239
VSS_132
VSS_240
VSS_133
VSS_241
VSS_134
VSS_242
VSS_135
VSS_243
VSS_136
VSS_244
VSS_137
VSS_245
VSS_138
VSS_246
VSS_139
VSS_247
VSS_140
VSS_248
VSS_141
VSS_249
G18
H18
J18
L18
N18
P18
R18
T18
U18
V18
W18
Y18
AA18
AB18
AE18
AF18
AJ18
F19
G19
H19
J19
K19
L19
N19
P19
R19
T19
U19
V19
W19
Y19
AB19
AC19
AD19
AE19
AF19
AK19
A20
E20
VSS_143
H15
J15
K15
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
G20
H20
J20
L20
N20
P20
R20
T20
U20
V20
W20
AE20
AF20
AK20
AA15
AE15
AF15
AG15
AH15
AJ15
E16
F16
G16
H16
J16
L16
VSS_250
VSS_144
VSS_251
VSS_145
VSS_252
VSS_146
VSS_253
VSS_147
VSS_254
VSS_148
VSS_255
VSS_149
VSS_256
VSS_150
VSS_257
VSS_151
VSS_258
VSS_152
VSS_259
VSS_153
VSS_260
VSS_154
VSS_261
N16
P16
F21
G21
H21
J21
K21
L21
T21
U21
V21
AE21
AF21
AK21
R16
V16
W16
Y16
VSS_159
VSS_265
VSS_160
VSS_266
VSS_161
VSS_267
VSS_162
VSS_268
VSS_163
VSS_269
VSS_164
VSS_270
VSS_165
VSS_271
VSS_166
VSS_272
VSS_167
VSS_273
VSS_168
VSS_274
VSS_169
VSS_275
VSS_170
VSS_276
VSS_171
VSS_277
VSS_172
VSS_278
VSS_173
VSS_279
VSS_174
VSS_280
VSS_175
VSS_281
VSS_176
VSS_282
H22
J22
AE16
AF16
M22
AM16
A17
B17
G17
H17
J17
V22
W22
AC22
AD22
AE22
AF22
AL22
K17
N17
P17
R17
T17
U17
V17
W17
E23
F23
G23
H23
J23
K23
Y17
AA17
J13
K13
L13
VSS_395
VSS_292
VSS_396
VSS_293
VSS_397
VSS_294
VSS_398
VSS_295
VSS_399
VSS_296
VSS_400
VSS_297
VSS_401
VSS_298
VSS_402
VSS_299
VSS_403
VSS_300
VSS_404
VSS_301
VSS_405
VSS_302
VSS_406
VSS_303
VSS_407
VSS_304
VSS_408
VSS_305
VSS_409
VSS_306
VSS_410
VSS_307
AE17
VSS_411
VSS_309
VSS_412
VSS_310
VSS_413
VSS_311
VSS_414
VSS_312
VSS_415
VSS_313
VSS_416
VSS_314
VSS_417
VSS_315
VSS_418
VSS_316
VSS_419
VSS_317
VSS_420
VSS_318
VSS_421
VSS_319
VSS_422
VSS_320
VSS_423
VSS_321
VSS_424
VSS_322
VSS_425
VSS_323
VSS_426
VSS_324
VSS_427
VSS_325
VSS_428
VSS_326
VSS_429
VSS_327
VSS_430
VSS_328
VSS_431
VSS_329
VSS_432
VSS_330
VSS_433
VSS_331
VSS_434
VSS_332
VSS_435
VSS_333
VSS_436
VSS_334
VSS_437
VSS_335
VSS_438
VSS_336
VSS_439
VSS_337
VSS_440
VSS_338
VSS_441
VSS_339
VSS_442
VSS_443
VSS_340
VSS_444
VSS_341
VSS_445
VSS_342
VSS_446
VSS_343
VSS_447
VSS_344
VSS_448
VSS_345
VSS_449
VSS_346
VSS_450
VSS_347
VSS_451
VSS_348
VSS_452
VSS_349
VSS_453
VSS_350
VSS_454
VSS_351
VSS_455
VSS_352
VSS_456
VSS_353
VSS_457
VSS_460
VSS_354
VSS_461
VSS_355
VSS_462
VSS_356
VSS_463
VSS_464
VSS_357
VSS_465
VSS_358
VSS_466
VSS_359
VSS_467
VSS_360
VSS_468
VSS_361
VSS_469
VSS_362
VSS_470
VSS_364
VSS_471
VSS_365
VSS_472
VSS_366
VSS_473
VSS_367
VSS_474
AJ17
AL17
VSS_476
VSS_368
VSS_477
VSS_369
VSS_478
VSS_370
VSS_479
VSS_371
VSS_480
VSS_372
VSS_481
VSS_373
VSS_482
VSS_374
VSS_483
VSS_484
W23
Y23
VSS_181
AC23
VSS_182
AD23
VSS_183
AE23
VSS_184
AF23
VSS_185
AJ23
AM23
VSS_485
VSS_486
VSS_376
AF17
G24
H24
J24
K24
L24
M24
N24
P24
R24
T24
U24
V24
W24
Y24
AA24
AB24
AC24
AD24
AE24
AF24
F25
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
V25
W25
Y25
AA25
AB25
AC25
AD25
AE25
AF25
AM25
A26
F26
G26
H26
J26
K26
L26
M26
N26
P26
R26
T26
U26
V26
W26
Y26
AA26
AB26
AC26
AD26
AE26
AF26
AJ26
AL26
D27
F27
K27
N27
P27
R27
U27
V27
W27
Y27
AA27
AB27
F28
VSS_363
P23
F24
AL24
VSS_308
VSS_375
AB17
AB23
H13
VSS_291
M23
AA23
G13
VSS_394
A23
V23
VSS_284
VSS_290
VSS_475
VSS_178
VSS_180
VSS_393
L17
T23
VSS_283
VSS_289
L22
VSS_177
VSS_179
VSS_392
G22
AA16
AJ16
VSS_264
VSS_288
U16
U22
VSS_158
VSS_391
VSS_459
VSS_156
VSS_263
VSS_390
VSS_287
VSS_458
VSS_155
VSS_262
VSS_389
VSS_286
T16
T22
VSS_157
D24
VSS_285
D21
W21
VSS_142
D12
G12
AVDD_PLL
+1.5V_U_DDR
G10
AJ10
AVDDL_DRV_2
VSS_189
VSS_85
VSS_123
T5
W5
AVDDL_DVI_1
VSS_84
AD9
F10
Y10
VSS_188
P13
F20
AG9
VSS_30
VSS_83
R13
VSS_224
K5
P5
AVDDL_HDMITX_1
VSS_187
H5
VSS_29
L3
VSS_186
VSS_82
AC8
AG3
T4
T13
VSS_81
VSS_487
VSS_488
VSS_377
VSS_489
VSS_378
VSS_490
VSS_379
VSS_491
VSS_380
VSS_492
VSS_381
VSS_493
VSS_382
VSS_494
VSS_383
VSS_495
VSS_384
VSS_496
VSS_385
VSS_497
VSS_386
VSS_498
VSS_387
VSS_499
VSS_388
VSS_500
VSS_501
VSS_502
VSS_503
VSS_504
VSS_505
VSS_506
K28
P28
U28
AC28
AK28
A29
C29
D29
E29
F29
J29
M29
R29
V29
AA29
AC29
AK29
A30
B30
AC30
AK30
AM30
A31
B31
C31
J31
L31
AD31
AF31
AH31
B32
E32
J32
L32
P32
U32
Y32
VSS_507
AE32
VSS_508
AG32
VSS_509
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-14Y-UD-133-HD
2013.12.17
U_Power
LGE Internal Use Only
MAX 4.7A
+12V
P13401
+1.5V_U_DDR
POWER_ON/OFF2_1
DCDC_TI
IC13403-*1
TPS54327DDAR [EP]GND
SS
4
3A
R13423
22K
1%
R2
5
GND
R13401
C13448
22uF
10V
C13449
22uF
10V
ZD13401
2.5V
OPT
0.1uF
16V
VDDC
OPT
ZD13400
2.5V
C13400 C13401
22uF
22uF
C13411
22uF
VIN_3
SW_3
8
16
VIN_2
SW_4
9
15
VIN_1
8A
20K
R13410
17
1/16W
1%
7
1%
1/16W
NC_2
SW_2
IC13402
TPS53513RVER
R13408
4.87K
VDD
18
SW_1
THERMAL
29
1/16W 1/16W
1%
1%
TRIP
VO
24
NC_3
19
6
C13405 NC_1
C13404
470pF
50V
25
GND1
GND2
[EP]
28
5
4
1/16W
5%
27
1%
1/16W
91K
R13406
VREG
VBST
L13403
1uH
Vout=0.765*(1+R1/R2)=1.516V
MODE
20
3
16V
0.1uF
C13402 R13400
2K
C13445 C13446
2200pF
1uF
10V
50V
1.0V_DCDC_ROHM
GND
21
2
EN
1K
POWER_ON/OFF2_3
22
PGOOD
L13412
2.2uH
NR5040T2R2N
FB
1
R13411R13409
100 5.1K
SW
R2
23
RF
+12V
L13402
C13407
C13408
1uF
10uF
10V
16V
C13409
10uF
16V
14
6
16V
0.1uF
C13447
PGND_5
3
7
BOOT
11
VREG
2
C13403
1000pF
50V
VIN
1%
1/16W
8
27K
R13405
1
R1
1/16W
5%
PGND_2
C13446-*1
3300pF
50V
R13407
39K
GND
10
3.6K
1%
FB
SS
[EP]FIN
PGND_1
TCON_PWR_5pin_Wafer
SW
D13400
18K
1%
C13444
100pF
50V
1.0V_DCDC_TI
TCON_PWR_5pin_Wafer
5
R13404
10K
VBST
R13403
4.7
R1
C13442
0.1uF
25V
TCON_PWR_5pin_Wafer
4
VIN
1/10W
5%
R13421 R13422
C13434
10uF
25V
6
OPT
30V
EN
TCON_PWR_5pin_Wafer
5
9
10K
4
6
7
3
R13402
3.3
IC13403
BD9D320EFJ
R13424
L13409
MLB-201209-0120P-N2
L13410
MLB-201209-0120P-N2
C13440
C13435
10uF
0.1uF
25V
25V
OPT
2
DCDC_ROHM
TCON_PWR_5pin_Wafer
3
8
1
13
VREG5
PGND_4
C13410
0.1uF
THERMAL
PANEL_VCC
C13443
10uF
16V
26
EN
VFB
2
12
1
PGND_3
BLM18PG121SN1D
9
T-con power
L13411
THERMAL
20037WR-05A00
+1.15V URSA9 Core
+1.5V URSA DDR
TCON_PWR_5pin_Wafer
C13406
2200pF
50V
Vout=0.6*(1+R1/R2)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-14Y-UD-134-HD
2013.12.17
LGE Internal Use Only
Contents of LCD TV Standard Repair Process
No.
Error symptom (High category)
Error symptom (Mid category)
Page
1
No video/Normal audio
1
2
No video/No audio
2
Picture broken/ Freezing
3
4
Color error
4
5
Vertical/Horizontal bar, residual image,
light spot, external device color error
5
6
No power
6
Off when on, off while viewing, power
auto on/off
7
No audio/Normal video
8
9
Wrecked audio/discontinuation/noise
9
10
Remote control & Local switch checking
10
MR(Magic Remocon) operating checking
11
12
Wifi operating checking
12
13
External device recognition error
13
3
A. Video error
B. Power error
7
8
Remarks
C. Audio error
11
D. Function error
145
E. Noise
Circuit noise, mechanical noise
14
15
F. Exterior error
Exterior defect
15
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Standard Repair Process
Error
symptom
LCD TV
A. Video error
Established
date
No video/ Normal audio
Revised date
2013.01.31
1/16
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, LVDS Cable, Speaker Cable, IR B/D Cable,,,)
☞A1
No video
Normal audio
Normal
audio
Y
☞A18
Check Back Light
On with naked eye
N
Move to No
video/No audio
Y
On
Check Power
Board
24V, 12V,3.5V etc.
N
☞A18
Y
Replace T-con/Main
Board or module
And Adjust VCOM
N
Repair Power
Board or parts
Check Power Board 24V output
Normal
voltage
Normal
voltage
Y
Replace Inverter
or module
End
N
Repair Power
Board or parts
※Precaution
☞A4 & A2
Always check & record S/W Version and White
Balance value before replacing the Main Board
Replace Main Board
1
Re-enter White Balance value
Standard Repair Process
LCD TV
Error
symptom
A. Video error
Established
date
No video/ No audio
Revised date
☞A18
No Video/
No audio
Check various
voltages of Power
Board ( 3.5V,12V,20V
or 24V…)
Normal
voltage?
Y
N
Check and
replace
MAIN B/D
End
Replace Power
Board and repair
parts
2
2013.01.31
2/16
Standard Repair Process
Error
symptom
LCD TV
☞ A3
Check RF Signal level
Normal
Signal?
Y
A. Video error
Established
date
Picture broken/ Freezing
Revised date
2013.01.31
3/16
. By using Digital signal level meter
. By using Diagnostics menu on OSD
( Setting→ Support → Signal Test )
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)
Check whether other equipments have problem or not.
(By connecting RF Cable at other equipment)
→ DVD Player ,Set-Top-Box, Different maker TV etc`
N
Check RF Cable
Connection
1. Reconnection
2. Install Booster
☞ A4
Normal
Picture?
Y
Check
S/W Version
Normal
Picture?
N
Check
Tuner soldering
N
Y
N
N
SVC
Bulletin?
S/W Upgrade
Contact with signal distributor
or broadcaster (Cable or Air)
Normal
Picture?
Y
Y
Close
Close
3
N
Replace
Main B/D
Y
Close
Standard Repair Process
LCD TV
Error
symptom
Established
date
Color error
Revised date
Color
error?
N
Y
※ Check
and replace
Link Cable
(V by one)
and contact
condition
Check Test pattern
4/16
Y
Color
error?
Y
Color
error?
Replace Main B/D
Replace module
N
N
Check error
color input
mode
☞A8
2013.01.31
☞ A7
☞A6
Check color by input
-External Input
-COMPONENT
-AV
-HDMI
A. Video error
End
External Input/
Component
error
Check
external
device and
cable
External
device /Cable
normal
Y
Replace Main/T-con B/D
N
Request repair
for external
device/cable
N
HDMI
error
Check external
device and
cable
4
Y
External
device /Cable
normal
Replace Main/T-con B/D
Standard Repair Process
LCD TV
Error
symptom
A. Video error
Established
date
Vertical / Horizontal bar, residual image,
light spot, external device color error
Revised date
2013.01.31
5/16
Vertical/Horizontal bar, residual image, light spot
Replace
Module
☞A6
☞ A7
Check color condition by input
-External Input
-Component
-HDMI
Screen Y
normal?
Check external
device
connection
condition
Y
Normal?
N
N
Check Test pattern
Screen N
normal?
Y
Request repair
for external
device
Replace
module
☞A8
Check and
replace Link
Cable
N
End
Screen
normal?
Replace Main/T-con B/D
(adjust VCOM)
For LGD panel
Y
Replace Main B/D
End
For other panel
External device screen error-Color error
Check S/W Version
Check
version
N
Y
External
Input
error
Component
error
S/W Upgrade
Normal
screen?
Check screen
condition by input
-External Input
-Component
-HDMI/DVI
N
HDMI/
DVI
Y
End
5
Connect other external
device and cable
(Check normal operation of
External Input, Component,
RGB and HDMI/DVI by
connecting Jig, pattern
Generator ,Set-top Box etc.
Connect other external
device and cable
(Check normal operation of
External Input, Component,
RGB and HDMI/DVI by
connecting Jig, pattern
Generator ,Set-top Box etc.
Screen
normal?
N
Replace
Main/T-con
B/D
Y
Request repair for
external device
Y
Screen
normal?
N
Replace
Main /T-con
B/D
Standard Repair Process
LCD TV
Error
symptom
B. Power error
Established
date
No power
Revised date
☞A17
Check
Logo LED
2013.01.31
6/16
☞A18
DC Power on
by pressing Power Key
On Remote control
Y
Power
LED On?
. Stand-By: Red or Turn On
N
. Operating: Turn Off
Normal N
operation?
Check Power
On ‘”High”
OK?
Y
Check Power cord
was inserted properly
Replace Main B/D
☞A18
Measure voltage of each output of Power B/D
N
Normal?
Y
Y
※
Close
Y
Check ST-BY 3.5V
Normal
Y
voltage?
☞A18
Normal
voltage?
Y
N
Replace Power B/D
N
Replace Power
B/D
6
Replace Main B/D
Replace
Power
B/D
Standard Repair Process
LCD TV
Error
symptom
B. Power error
Established
date
Off when on, off while viewing, power auto on/off
Revised date
2013.01.31
7/16
Check outlet
☞A19
Check A/C cord
Error?
N
Check Power Off
Mode
CPU
Abnormal
Replace Main B/D
Normal?
Y
End
N
Check for all 3- phase
power out
Y
☞A18
Fix A/C cord & Outlet
and check each 3
phase out
(If Power Off mode
is not displayed)
Check Power B/D
voltage
※ Caution
Check and fix exterior
of Power B/D Part
* Please refer to the all cases which
can be displayed on power off mode.
Replace Power B/D
Abnormal
1
Normal
voltage?
Y
Replace Main B/D
N
Replace Power B/D
Status
Power off List
"POWEROFF_REMOTEKEY"
"POWEROFF_OFFTIMER"
"POWEROFF_SLEEPTIMER"
"POWEROFF_INSTOP"
"POWEROFF_AUTOOFF"
Normal "POWEROFF_ONTIMER"
"POWEROFF_RS232C"
"POWEROFF_RESREC"
"POWEROFF_RECEND"
"POWEROFF_SWDOWN"
"POWEROFF_UNKNOWN"
"POWEROFF_ABNORMAL1"
Abnormal
"POWEROFF_CPUABNORMAL"
7
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
off
off
off
off
off
off
off
off
off
off
off
off
off
Explanation
by REMOTE CONTROL
by OFF TIMER
by SLEEP TIMER
by INSTOP KEY
by AUTO OFF
by ON TIMER
by RS232C
by Reservated Record
by End of Recording
by S/W Download
by unknown status except listed case
by abnormal status except CPU trouble
by CPU Abnormal
Standard Repair Process
LCD TV
Error
symptom
C. Audio error
Established
date
No audio/ Normal video
Revised date
☞A20
No audio
Screen normal
Check user
menu >
Speaker off
2013.01.31
8/16
☞A21+A18
N
Off
Check audio B+
24V of Power
Board
Normal
voltage
Y
N
Cancel OFF
Check
Speaker
disconnection
Y
Replace Power Board and repair parts
N
Disconnection
Y
Replace Speaker
8
Replace MAIN Board
End
Standard Repair Process
LCD TV
Error
symptom
C. Audio error
Established
date
Wrecked audio/ discontinuation/noise
Revised date
2013.01.31
9/16
→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio
Check input
signal
-RF
-External Input
signal
Wrecked audio/
Discontinuation/
Noise for
all audio
Signal
normal?
☞A21+A18
Check and replace
speaker and
connector
Check audio
B+ Voltage (24V)
Y
Y
Wrecked audio/
Discontinuation/
Noise only
for D-TV
N
N
Wrecked audio/
Discontinuation/
Noise only
for Analog
(When RF signal is not
received)
Request repair to external
cable/ANT provider
(In case of
External Input
signal error)
Check and fix
external device
Normal
voltage?
Replace Main B/D
Replace Power B/D
Replace Main B/D
Wrecked audio/
Discontinuation/
Noise only
for External Input
Connect and check
other external
device
Normal
audio?
N
Y
Check and fix external device
9
End
Standard Repair Process
LCD TV
Established
date
D. Function error
Error
symptom
Remote control & Local switch checking
2013.01.31
Revised date
10/16
1. Remote control(R/C) operating error
☞A22
Check R/C itself
Operation
☞A22
Check & Repair
Cable connection
Connector solder
Normal Y
operating?
N
Normal
operating?
N
Y
Check R/C Operating
When turn off light
in room
Check & Replace
Baterry of R/C
If R/C operate,
Explain the customer
cause is interference
from light in room.
Y
Normal
operating?
Replace
Main B/D
☞A22
Check B+
3.5V
On Main B/D
☞A18
Close
Normal
Voltage?
Y
Check IR
Output signal
N
Check 3.5v on Power B/D
Replace Power B/D or
Replace Main B/D
(Power B/D don’t have problem)
Close
N
Replace R/C
10
Normal
Signal?
N
Repair/Replace
IR B/D
Y
Standard Repair Process
LCD TV
Established
date
D. Function error
Error
symptom
MR operating checking
2013.01.31
Revised date
11/16
2. MR(Magic Remocon) operating error
☞A4
Check the
INSTART menu
RF Receiver ver
is “00.00”?
N Check MR itself
Operation
Normal Y
operating?
Press the
wheel
N
☞A23
Y
Y
Check & Replace
Battery of MR
Check & Repair
RF assy
connection
Y
Normal
operating?
☞A4
RF Receiver ver
is “00.00”?
N
Close
Turn off/on the
set and press
the wheel
Is show ok N
message?
Close
Close
Is show ok
message?
N
N
Press the back
key about 5sec
Y
Replace MR
Close
Y
Down load the Firmware
* If you conduct the loop at 3times, change the M4.
* INSTART MENU14.RF
Remocon Test3. Firmware
download
11
Standard Repair Process
LCD TV
Established
date
D. Function error
Error
symptom
Wifi operating checking
2013.01.31
Revised date
12/16
3.Wifi operating error
☞A4
Check the
INSTART menu
☞A24
Wi-Fi Mac value
is “NG”?
N
Check the Wifi wafer
1pin
Normal
Voltage?
Y
☞A24
Y
Close
Check & Repair
Wifi cable
connection
☞A4
Wi-Fi Mac value
is “NG”?
N
Close
Y
Change the Wifi
assy
12
N
Replace
Main B/D
Standard Repair Process
LCD TV
Check
input
signal
Error
symptom
Signal
input?
Y
N
Check and fix
external device/cable
D. Function error
Established
date
External device recognition error
Revised date
Check technical
information
- Fix information
- S/W Version
Technical
information?
N
External Input and
Component
Recognition error
2013.01.31
14/16
Replace Main B/D
Y
Fix in
accordance
with technical
information
14
HDMI/
DVI, Optical
Recognition error
Replace Main B/D
Standard Repair Process
LCD TV
Identify
nose
type
Error
symptom
Circuit
noise
Mechanical
noise
E. Noise
Established
date
Circuit noise, mechanical noise
Revised date
Check
location of
noise
2013.01.31
Replace PSU
Check location of
noise
※ Mechanical noise is a natural
phenomenon, and apply the 1st level
description. When the customer does not
agree, apply the process by stage.
※ Describe the basis of the description
in “Part related to nose” in the Owner’s
Manual.
OR
※ When the nose is severe, replace the module
(For models with fix information, upgrade the
S/W or provide the description)
※ If there is a “Tak Tak” noise from the
cabinet, refer to the KMS fix information and
then proceed as shown in the solution manual
(For models without any fix information,
provide the description)
15
15/16
Standard Repair Process
LCD TV
F. Exterior defect
Error
symptom
Zoom part with
exterior damage
Exterior defect
Module
damage
Replace module
Cabinet
damage
Replace cabinet
Remote
controller
damage
Stand
dent
Replace remote controller
Replace stand
16
Established
date
Revised date
2013.01.31
16/16
Contents of LCD TV Standard Repair Process Detail Technical Manual
No.
1
Error symptom
Content
Page
Check LCD back light with naked eye
A1
Check White Balance value
A2
TUNER input signal strength checking
method
A3
LCD-TV Version checking method
A4
Tuner Checking Part
A5
LCD TV connection diagram
A6
Check Link Cable (EPI) reconnection
condition
A7
9
Adjustment Test pattern - ADJ Key
A8
10
Exchange Main Board (1)
A-1/5
Exchange Main Board (2)
A-2/5
Exchange Power Board (PSU)
A-3/5
Exchange Module (1)
A-4/5
Exchange Module (2)
A-5/5
2
A. Video error_ No video/Normal
audio
4
5
A. Video error_ video error /Video
lag/stop
6
7
8
11
12
13
14
A. Video error _Vertical/Horizontal bar,
residual image, light spot
A. Video error_ Color error
<Appendix>
Defected Type caused by T-Con/
Inverter/ Module
Remarks
Continue to the next page
Contents of LCD TV Standard Repair Process Detail Technical Manual
Continued from previous page
No.
Error symptom
16
Content
Page
Check front display LED
A17
Check power input Voltage & ST-BY 3.5V
A18
POWER OFF MODE checking method
A19
Checking method in menu when there is
no audio
A20
Voltage and speaker checking method
when there is no audio
A21
Remote controller operation checking
method
A22
Motion Remote operation checking
method
A23
23
Wifi operation checking method
A24
24
Camera operation checking method
A25
Remarks
B. Power error_ No power
17
18
19
20
B. Power error_Off when on, off
while viewing
C. Audio error_ No audio/Normal
video
21
22
D. Function error
Not Used
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_No video/Normal audio
Content
Check LCD back light with naked eye
Established
date
Revised
date
2013.01.31
<XXUB83/820X-XX>
After turning on the power and disassembling the case, check with the naked eye,
whether you can see light from locations.
A1
* Tuner is different from region
A1
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_No video/Normal audio
Content
Check White Balance value
Established
date
Revised
date
2014.02.14
<ALL MODELS>
Entry
Entrymethod
method
1.1.Press
Pressthe
theADJ
ADJbutton
buttonononthe
theremote
remotecontroller
controllerforforadjustment.
adjustment.
2.2.Enter
Enterinto
intoWhite
WhiteBalance
Balanceofofitem
item6.10.
3.3.After
Afterrecording
recordingthe
theR,R,G,G,B B(GAIN,
(GAIN,Cut)
Cut)value
valueofofColor
ColorTemp
Temp
(Cool/Medium/Warm),
(Cool/Medium/Warm),re-enter
re-enterthe
thevalue
valueafter
afterreplacing
replacingthe
theMAIN
MAINBOARD.
BOARD.
A2
A2
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Video error, video lag/stop
Content
TUNER input signal strength checking method
Established
date
Revised
date
2014.02.14
A3
<ALL MODELS>
MENU  support  signal test
 select channel
When the signal is strong, use the
attenuator (-10dB, -15dB, -20dB etc.)
A3
Standard Repair Process Detail Technical Manual
LCD TV
<ALL MODELS>
Error
symptom
A. Video error_Video error, video lag/stop
Content
LCD-TV Version checking method
Established
date
Revised
date
1. Checking method for remote controller for adjustment
Version
Press the IN-START with the remote
controller for adjustment
A4
2014.02.14
A4
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Video error, video lag/stop
Content
TUNER checking part
Established
date
Revised
date
2014.02.14
<ALL MODELS>
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
2. After measuring each voltage from power supply, finally replace the MAIN BOARD.
A5
A5
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
A. Video error _Vertical/Horizontal bar,
residual image, light spot
LCD TV connection diagram (1)
Established
date
Revised
date
<ALL MODELS>
As the part connecting to the external input, check
the screen condition by signal
A6
2014.02.14
A6
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Color error
Content
Check Link Cable (LVDS) reconnection condition
Established
date
Revised
date
2014.02.14
A7
<ALL MODELS>
Check the contact condition of the Link Cable, especially dust or mis insertion.
A7
* Tuner is different from region
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Color error
Content
Adjustment Test pattern - ADJ Key
Established
date
Revised
date
2014.02.14
You can view 6 types of patterns using the ADJ Key
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
A8
A8
Appendix : Exchange Main Board (1)
Solder defect, CNT Broken
Solder defect, CNT Broken
Solder defect, CNT Broken
Solder defect, CNT Broken
T-Con
T-Con
Defect,
Defect,
CNT
CNT
Broken
Broken
Solder
defect,CNT
CNTBroken
Broken
T-Con
Defect,
Abnormal Power Section
Solder defect, Short/Crack
Abnormal Power Section
A - 1/5
Solder defect, Short/Crack
Appendix : Exchange Main Board (2)
Abnormal Power Section
Solder defect, Short/Crack
GRADATION
Abnormal Power Section
Solder defect, Short/Crack
Fuse Open, Abnormal power section
Abnormal Display
Noise
GRADATION
A - 2/5
Appendix : Exchange Power Board (PSU)
No Light
Dim Light
Dim Light
Dim Light
No picture/Sound Ok
A - 3/5
Appendix : Exchange the Module (1)
Panel Mura, Light leakage
Crosstalk
Panel Mura, Light leakage
Press damage
Press damage
Crosstalk
Un-repairable Cases
In this case please exchange the module.
Press damage
A - 4/5
Appendix : Exchange the Module (2)
Vertical Block
Source TAB IC Defect
Horizontal Block
Gate TAB IC Defect
Vertical Line
Source TAB IC Defect
Horizontal
Gate
TAB ICBlock
Defect
Gate TAB IC Defect
Vertical Block
Source TAB IC Defect
Horizontal line
Gate TAB IC Defect
Gate TAB IC Defect
Un-repairable Cases
In this case please exchange the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
A - 5/5
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _No power
Check front Power Indicator
<XXUB83/820X-XX>
ST-BY condition: On or Off
Power ON condition: Turn Off
A17
Established
date
Revised
date
2014.02.07
A17
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _No power
Check power input voltage and ST-BY 3.5V
Established
date
Revised
date
2014.02.05
Check the DC 24V, 12V, 3.5V.
P_main
Maker : Yeonho
28Pin SMAW200-H28S5K
28Pin map (LPB)
1
PWR ON
2
DVR_ON
3
P_DIM #1
4
PDIM #2
5
3.5V
6
GND
7
3.5V
8
3.5V
9
GND
10
GND
11
12V
12
12V
13
12V
14
12V
15
12V
16
GND
17
GND
18
24V
19
24V
20
24V
21
24V
22
24V
23
GND
24
GND
25
SCLK
26
GND
27
SIN
28
VSYNC
A18
A18
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _Off when on, off whiling viewing Established
date
POWER OFF MODE checking method
<ALL MODELS>
Entry method
1. Press the IN-START button of the remote
controller for adjustment
2. Check the entry into adjustment item 3
A19
Revised
date
2014.02.05
A19
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
C. Audio error_No audio/Normal video
Content
Checking method in menu when there is no audio
<XXUB83/820X-XX>
Checking method
1. Press the Setting button on the remote controller
2. Select the Sound function of the Menu
3. Select the Sound Out
4. Select TV Speaker
A20
Established
date
Revised
date
2014.02.05
A20
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
C. Audio error_No audio/Normal video
Content
Voltage and speaker checking method
when there is no audio
Established
date
Revised
date
2014.02.05
A21
<XXUB83/820X-XX>
②
1
PWR ON
2
DVR_ON
3
P_DIM #1
4
PDIM #2
5
3.5V
6
GND
7
3.5V
8
3.5V
9
GND
10
GND
11
12V
12
12V
13
12V
14
12V
15
12V
16
GND
17
GND
18
24V
19
24V
20
24V
21
24V
22
24V
23
GND
24
GND
25
SCLK
26
27
SIN
28
①
1
SPK_R-
2
SPK_R+
GND
3
SPK_L-
VSYNC
4
SPK_L+
③
Checking order when there is no audio
1.Check the contact condition of or 24V connector of Main Board
2. Measure the 24V input voltage supplied from Power Board
(If there is no input voltage, remove and check the connector)
3.Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.
A21
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
D. Function error
Content
Remote controller operation checking method
Established
date
Revised
date
2014.02.07
A22
<XXUB83/820X-XX>
Front
Back
③
②
①
Wifi/ BT Combo
Checking order to check remote controller
Checking order
1.Check IR cable condition between IR & Main board.( Check picture number① and ②)
2.Check the standby 3.5V on the terminal 16 pin (③)
3.AS checking the Pre-Amp(IR LED light) , the power is in ON condition, an Analog Tester
needle should move slowly, otherwise, it’s defective.
A22
1
GND
2
+3.5V WOL
3
BT_RESET
4
USB_DM
5
NC
6
USB_DP
7
WOL
8
GND
9
SDA
10
GND
11
SCL
12
KEY1
13
GND
14
KEY2
15
IR
16
+3.5V_ST
17
LED_R
18
GND
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
D. Function error
Motion Remote / Wifi operation checking method
Established
date
Revised
date
2014.02.07
A23
<XXUB83/820X-XX>
Front
Back
③
②
①
Wifi/ BT Combo
Checking order to check motion remote/wifi
Checking order
1.Check BT/Wifi cable condition between BT/Wifi assy & Main board.
2.Check the 3.5V on the terminal 16
A23
1
GND
2
+3.5V WOL
3
BT_RESET
4
USB_DM
5
NC
6
USB_DP
7
WOL
8
GND
9
SDA
10
GND
11
SCL
12
KEY1
13
GND
14
KEY2
15
IR
16
+3.5V_ST
17
LED_R
18
GND
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