OPAx187 0.005 μV/°C 漂移、低功耗轨到轨输出36V 运算

OPAx187 0.005 μV/°C 漂移、低功耗轨到轨输出36V 运算
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OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
OPAx187 0.005 µV/°C 漂移、低功耗轨到轨输出
36V 运算放大器
零漂移系列
1 特性
•
•
•
•
•
•
•
•
•
•
•
•
•
1
低偏移电压:10μV(典型值)
零漂移:0.005µV/°C
低噪声:20 nV/√Hz
电源抑制比 (PSRR):160dB
共模抑制比 (CMRR):140dB
AOL:160dB
静态电流:100µA
宽电源电压:±2.25V 至 ±18V
轨到轨输出运行
输入包括负电源轨
低偏置电流:100pA(典型值)
已滤除电磁干扰 (EMI) 的输入
微型封装
2 应用
•
•
•
•
•
•
•
•
•
•
桥式放大器
应力计
测试和测量仪器
变频器应用
温度测量
电子称
医疗仪表
热电阻 (RTD) 放大器
精密有源滤波器
低侧电流监控
OPAx187 器件的单通道版本采用微型 8 引脚超薄小外
形尺寸 (VSSOP) 封装、5 引脚 SOT-23 封装和 8 引脚
小外形尺寸集成电路 (SOIC) 封装。双通道版本采用 8
引脚超薄小外形尺寸无引线 (VSON) 封装、8 引脚
VSSOP 封装以及 8 引脚 SOIC 封装。该器件的四通道
版本采用 14 引脚小外形尺寸 (SO) 封装和 14 引脚薄
型小外形尺寸 (TSSOP) 封装。所有器件版本的额定工
作温度范围均为 -40°C 至 +125°C。
器件信息(1)
器件型号
封装
OPA187
OPA2187
OPA4187
4.90mm x 3.91mm
SOT-23 (5)
2.90mm x 1.60mm
VSSOP (8)
3.00mm × 3.00mm
SOIC (8)
4.90mm x 3.91mm
VSSOP (8)
3.00mm × 3.00mm
VSON (8)
3.00mm × 3.00mm
SOIC (14)
8.70mm × 3.90mm
TSSOP (14)
5.00mm x 4.40mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
OPAx187 具有高精度低侧电流测量功能
VSUPPLY
+
Load
100 k
±
GND
VSUPPLY
100
+
RSHUNT
3 说明
OPAx187 系列运算放大器采用自动归零技术,可在时
间和温度范围内同步提供低偏移电压 (1µV) 以及近似
为零的漂移。此类微型、高精度、低静态电流放大器提
供高输入阻抗和流入高阻抗负载的摆幅在 5mV 电源轨
范围内的轨到轨输出。输入共模范围包括负电源轨。单
电源或双电源可在 4.5V 至 36V(±2.25V 至 ±18V)范
围内使用。
封装尺寸(标称值)
SOIC (8)
VOUT
OPA187
100
±
GND
I
I
100 k
GND
G = 1000 ‡ 5SHUNT ‡ ,
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS807
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: OPAx187 ................................
Electrical Characteristics: High-Voltage Operation ..
Electrical Characteristics: Low-Voltage Operation...
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 20
15
15
16
19
器件支持 ...............................................................
文档支持 ...............................................................
相关链接................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
26
26
27
27
27
27
27
27
12 机械、封装和可订购信息 ....................................... 28
4 修订历史记录
2
日期
修订版本
注释
2016 年 12 月
*
最初发布。
Copyright © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
5 Pin Configuration and Functions
OPA187: D and DGK Packages
8-Pin SOIC and 8-pin VSSOP
Top View
OPA187: DBV Package
5-Pin SOT-23
Top View
V±
2
+IN
3
5
V+
1
±IN
2
+IN
3
V±
4
±
1
+
OUT
NC
4
8
NC
±
7
V+
+
6
OUT
5
NC
±IN
Not to scale
Not to scale
(1)
NC denotes no internal connection.
Pin Functions: OPA187
PIN
DBV
(SOT-23)
D (SOIC)
DGK (VSSOP)
I/O
+IN
3
3
I
Non-inverting input
–IN
4
2
I
Inverting input
NC
—
1, 5, 8
—
No connection (can be left floating)
OUT
1
6
O
Output signal
V+
5
7
—
Positive (highest) supply voltage
V–
2
4
—
Negative (lowest) supply voltage
NAME
DESCRIPTION
OPA2187: D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
OPA2187: DRG Package
8-Pin VSON
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
OUT A
1
±IN A
2
+IN A
3
V±
4
Thermal
Pad
8
V+
7
OUT B
6
±IN B
5
+IN B
Not to scale
Not to scale
Pin Functions: OPA2187
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Non-inverting input, channel A
–IN A
2
I
Inverting input, channel A
+IN B
5
I
Non-inverting input, channel B
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) supply voltage
V–
4
—
Negative (lowest) supply voltage
Copyright © 2016, Texas Instruments Incorporated
3
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
OPA4187: D and PW Packages
14-pin SOIC and 14-Pin TSSOP
Top View
OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Pin Functions: OPA4187
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Non-inverting input, channel A
–IN A
2
I
Inverting input, channel A
+IN B
5
I
Non-inverting input, channel B
–IN B
6
I
Inverting input, channel B
+IN C
10
I
Non-inverting input, channel C
–IN C
9
I
Inverting input, channel C
+IN D
12
I
Non-inverting input, channel D
–IN D
13
I
Inverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V+
4
—
Positive (highest) supply voltage
V–
11
—
Negative (lowest) supply voltage
4
Copyright © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply, VS = (V+) – (V–)
Differential
(V–) – 0.5
(3)
Signal input pin
Output short-circuit (5)
(V+) + 0.5
–10
10
–55
55
mA
Continuous
Continuous
Continuous
–55
150
Operating, TA
Junction, TJ
mA
150
Storage, Tstg
(1)
V
(V–) – 0.5
(2)
Signal output pin (4)
Temperature
(V+) + 0.5
±0.5
Signal output pin (4)
Current
UNIT
40
Common-mode
Signal input pin (2)
Voltage
MAX
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to ±10 mA or less.
Refer to the Electrical Overstress section for more information.
Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.5 V beyond the supply rails
should be current limited to ±55 mA or less.
Short-circuit to ground, one amplifier per package.
(2)
(3)
(4)
(5)
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
+
–
(V ) – (V )
Supply voltage
TA
Specified temperature
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
125
°C
6.4 Thermal Information: OPAx187
OPAx187
THERMAL METRIC (1)
8 PINS
UNIT
DGK (VSSOP)
RθJA
Junction-to-ambient thermal resistance
159
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37
°C/W
RθJB
Junction-to-board thermal resistance
49
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
77.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016, Texas Instruments Incorporated
5
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
6.5
www.ti.com.cn
Electrical Characteristics: High-Voltage Operation
at TA = 25°C, VS = ±4 V to ±18 V (VS = 8 V to 36 V), RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1) (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
±1
±10
±0.005
±0.05
μV/°C
VS = 4.5 V to 36 V, TA = –40°C to
+125°C
±0.01
±1
μV/V
VCM = VS / 2
±100
±350
pA
±5
nA
±500
pA
±5
nA
TA = –40°C to +125°C
μV
INPUT BIAS CURRENT
IB
Input bias current
IOS
TA = –40°C to +125°C
±100
Input offset current
TA = –40°C to +125°C
NOISE
en
Input voltage noise
in
f = 0.1 Hz to 10 Hz
0.4
µVPP
f = 0.1 Hz to 10 Hz
60
nVrms
Input voltage noise density
f = 1 kHz
20
nV/√Hz
Input current noise density
f = 1 kHz
160
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.1
(V+) – 2
V
(V–) – 0.1 V < VCM < (V+) – 2 V, VS =
±18 V
126
140
dB
(V–) < VCM < (V+) – 2 V, VS = ±18 V,
TA = –40°C to +125°C
130
145
dB
INPUT IMPEDANCE
ZID
Differential
100 || 6
MΩ || pF
ZIC
Common-mode
6 || 4.2
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
TA = –40°C to +125°C, VS = ±4 V to ±18
V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RL =
10 kΩ
132
160
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
550
kHz
VO = 10-V step, G = 1
0.2
V/μs
tS
Settling time
0.1%
VS = ±18 V, G = 1, 10-V step
46
μs
0.01%
VS = ±18 V, G = 1, 10-V step
48
tOR
Overload recovery time
VIN × G = VS
μs
8
THD+N
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 3.5 VRMS, No Load
μs
0.035%
OUTPUT
VS = ±4 V to ±18 V, No Load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
5
15
VS = ±4 V to ±18 V, RL = 10 kΩ
75
100
VS = ±4 V to ±18 V, RL = 10 kΩ,
TA = –40°C to +125°C
100
125
mV
VS = ±18 V, Sinking
–30
mA
VS = ±18 V, Sourcing
+30
mA
1.4
kΩ
f = 550 kHz, IO = 0, See 图 21
See Typical Characteristics
POWER SUPPLY
IQ
(1)
6
Quiescent current (per amplifier)
VS = ±4 V to VS = ±18 V
IO = 0 mA, TA = –40°C to +125°C
100
145
μA
150
μA
VS / 2 = midsupply.
Copyright © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
6.6
ZHCSFV2 – DECEMBER 2016
Electrical Characteristics: Low-Voltage Operation
at TA = +25°C, VS = ±2.25 V to < ±4 V (VS = +4.5 V to < 8 V), RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1)
(unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
±1
±15
TA = –40°C to +125°C
±0.005
±0.05
μV/°C
VS = 4.5 V to 36 V,
TA = –40°C to +125°C
±0.01
±1
μV/V
VCM = VS / 2
±100
±350
pA
±5
nA
±500
pA
±5
nA
μV
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = –40°C to +125°C
±100
TA = –40°C to +125°C
NOISE
en
Input voltage noise
in
f = 0.1 Hz to 10 Hz
0.4
µVPP
f = 0.1 Hz to 10 Hz
60
nVrms
Input voltage noise density
f = 1 kHz
20
nV/√Hz
Input current noise density
f = 1 kHz
160
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.1
(V+) – 2
V
(V–) – 0.1 V < VCM < (V+) – 2 V, VS =
±2.25 V
114
130
dB
(V–) < VCM < (V+) – 2 V, VS = ±2.25 V,
TA = –40°C to +125°C
120
137
dB
INPUT IMPEDANCE
ZID
Differential
100 || 6
MΩ || pF
ZIC
Common-mode
6 || 4.2
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
TA = –40°C to +125°C, VS = ±2.25 V
to ±4 V, (V–) + 0.3 V < VO < (V+) – 0.3
V, RL = 10 kΩ
120
140
dB
550
kHz
0.2
V/μs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
VO = 1-V step, G = 1
tOR
Overload recovery time
VIN × G = VS
THD+N
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 1 Vrms, No Load
8
μs
0.05%
OUTPUT
VS = ±2.25 V to ±4 V, No Load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
5
15
VS = ±2.25 V to ±4 V, RL = 10 kΩ
15
25
VS = ±2.25 V to ±4 V, RL = 10 kΩ, TA =
–40°C to +125°C
15
30
mV
VS = ±2.25, Sinking
–20
mA
VS = ±2.25, Sourcing
+20
mA
1.4
kΩ
f = 550 kHz, IO = 0, See 图 21
See Typical Characteristics
POWER SUPPLY
IQ
(1)
Quiescent current (per amplifier)
VS = ±2.25 V to VS = ±4 V
IO = 0 mA, TA = –40°C to +125°C
100
145
μA
150
μA
VS / 2 = midsupply.
版权 © 2016, Texas Instruments Incorporated
7
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
6.7 Typical Characteristics
表 1. Typical Characteristic Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
图1
Offset Voltage Drift Distribution
图2
Offset Voltage vs Temperature
图3
Offset Voltage vs Common-Mode Voltage
图4
Offset Voltage vs Power Supply
图5
Open-Loop Gain and Phase vs Frequency
图6
Closed-Loop Gain vs Frequency
图7
IB vs Common-Mode Voltage
图8
Input Bias Current vs Temperature
图9
Output Voltage Swing vs Output Current
图 10
CMRR and PSRR vs Frequency (Referred-to-Input)
图 11
CMRR vs Temperature
图 12
PSRR vs Temperature
图 13
0.1-Hz to 10-Hz Noise
图 14
Input Voltage Noise Spectral Density vs Frequency
图 15
THD+N Ratio vs Frequency
图 16
THD+N vs Output Amplitude
图 17
Quiescent Current vs Supply Voltage
图 18
Quiescent Current vs Temperature
图 19
Open-Loop Gain vs Temperature
图 20
Open-Loop Output Impedance vs Frequency
图 21
Small-Signal Overshoot vs Capacitive Load (G = 1) (10-mV Output Step)
图 22
No Phase Reversal
图 23
Positive Overload Recovery
图 24
Negative Overload Recovery
图 25
Small-Signal Step Response (10 mV)
图 26, 图 27
Large-Signal Step Response
图 28, 图 29
Large-Signal Settling Time (10-V Positive Step)
图 30
Large-Signal Settling Time (10-V Negative Step)
图 31
Short-Circuit Current vs Temperature
图 32
Maximum Output Voltage vs Frequency
图 33
Crosstalk vs Frequency
图 34
EMIRR IN+ vs Frequency
图 35
8
版权 © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
50
18
45
16
40
14
35
25
Offset Voltage (µV)
8
8
6
6
4
4
2
2
0
±2
±4
±6
±6
±8
±8
±10
0
25
50
75
100
125
Temperature (ƒC)
VCM = ±18.1 V
±20
±15
±10
0
±5
5
120
3
100
Open-loop Gain (dB)
2
1
0
±1
VS = ± 2.25 V
90
60
40
45
20
0
±20
±4
±40
0
1
±5
8.0 10.0 12.0 14.0 16.0 18.0 20.0
VSUPPLY (V)
图 5. Offset Voltage vs Power Supply
版权 © 2016, Texas Instruments Incorporated
0.05
135
Phase
80
±3
6.0
0.04
C003
Open-loop Gain
4.0
20
10
100
1k
10k
100k
1M
Open-loop Phase (ƒ)
4
2.0
15
图 4. Offset Voltage vs Common-Mode Voltage
140
0.0
10
VCM (V)
C001
图 3. Offset Voltage vs Temperature
VOS ( V)
VCM = 16 V
±10
150
5
±2
0.03
0
±2
±4
±25
C001
图 2. Offset Voltage Drift Distribution
10
VOS ( V)
VOS ( V)
图 1. Offset Voltage Production Distribution
10
±50
0.02
Offset Voltage Drift (µV/ƒC)
C002
±75
0.01
-0.05
10
8
5
-3
3
0
0
5
0
-5
10
2
-8
15
4
0
20
6
-0.01
8
30
-0.02
10
-0.03
12
-0.04
Amplifiers (%)
20
-10
Amplifiers (%)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
-45
10M
Frequency (Hz)
C001
C001
图 6. Open-Loop Gain and Phase vs Frequency
9
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
350
G = +1
G= +10
G= -1
20
250
Input Bias Current (pA)
Closed-loop Gain (dB)
40
0
-20
150
50
±50
±150
±250
-40
±350
100
1k
10k
100k
1M
10M
Frequency (Hz)
±20
±15
±10
0
±5
5
10
15
VCM (V)
C004
图 7. Closed-Loop Gain vs Frequency
20
C001
图 8. IB vs Common-Mode Voltage
15.0
3
2.5
Input Bias Current (nA)
12.5
2
1.5
10.0
VO (V)
1
7.5
5.0
0.5
125°C
0
±40°C
25°C
-0.5
-1
-1.5
2.5
-2
ios
-2.5
0.0
-3
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
150
0
30
40
50
图 10. Output Voltage Swing vs Output Current
0.001
Common-Mode Rejection Ratio (dB)
140
120
100
80
60
CMRR
40
+PSRR
20
±PSRR
170
0.01
160
150
0.1
140
130
120
1
10
100
1k
10k
100k
1M
Frequency (Hz)
图 11. CMRR and PSRR vs Frequency
(Referred-to-Input)
10M
C004
Common-Mode Rejection Ratio ( V/V)
160
0
60
C001
180
180
Common-Mode Rejection Ratio (dB)
20
IO (mA)
图 9. Input Bias Current vs Temperature
10
10
C001
1
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (ƒC)
C001
图 12. CMRR vs Temperature
版权 © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0.001
170
0.01
160
150
0.1
140
130
120
Voltage (100 nV/div)
Power-Supply Rejection Ratio (µV/V)
Power-Supply Rejection Ratio (dB)
180
Time (1 s/div)
1
±75 ±50 ±25
0
25
50
75
C017
100 125 150
Temperature (ƒC)
C001
图 14. 0.1-Hz to 10-Hz Noise
Total Harmonic Distortion + Noise (%)
1000
10
100
10
-40
G = -1, 10k- Load
G = -1, 2k- Load
G = -1, 600- Load
G = +1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
1
-60
-80
0.1
-100
0.01
-120
-140
20k
0.001
20
1
1
10
100
1k
10k
图 16. THD+N Ratio vs Frequency
-80
0.01
G = -1, 10k- Load
G = -1, 2k- Load
G = -1, 600- Load
G = +1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
0.1
-100
-120
1
10
Output Amplitude (VRMS)
120
100
IQ (µA)
0.1
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
140
-60
1
0.01
C004
C002
图 15. Input-Referred Voltage Noise Spectral Density vs
Frequency (G = +101)
0.0001
0.001
2k
Frequency (Hz)
100k
Frequency (Hz)
0.001
200
80
60
40
20
0
C004
0
2
4
6
8
10
12
14
16
18
Supply Voltage (V)
图 17. THD+N vs Output Amplitude
版权 © 2016, Texas Instruments Incorporated
Total Harmonic Distortion + Noise (dB)
Voltage Noise Spectral Density (nV/¥Hz)
图 13. PSRR vs Temperature
20
C001
图 18. Quiescent Current vs Supply Voltage
11
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
150
0.0001
200
VS = ± 2.25 V
DC Open-Loop Gain (dB)
IQ (µA)
90
60
30
190
VS = ± 18 V
0.001
180
170
160
0.01
150
0
140
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
150
0.1
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (ƒC)
C001
图 19. Quiescent Current vs Temperature
C001
图 20. Open-Loop Gain vs Temperature
10000
70
1000
60
RISO = 0 Ÿ
Overshoot (%)
Open-loop Output Impedance (Ÿ)
DC Open-Loop Gain (µV/V)
120
100
10
1
RISO = 25 Ÿ
RISO = 50 Ÿ
50
40
30
20
10
0.1
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
10
100M
100
Capacitive Load (pF)
C001
图 21. Open-Loop Output Impedance vs Frequency
C004
图 22. Small-Signal Overshoot vs
Capacitive Load (G = +1) (10-mV Output Step)
VIN
1 V/div
Voltage (5 V/div)
VOUT
VIN
VOUT
Time (40 ms/div)
Time (2 µs/div)
C017
图 23. No Phase Reversal
12
C017
图 24. Positive Overload Recovery
版权 © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
5 V/div
2 mV/div
VIN
VOUT
VOUT
VIN
Time (2 µs/div)
Time (1 µs/div)
C017
C017
图 25. Negative Overload Recovery
图 26. Small-Signal Step Response
(100 mV)
2 mV/div
2.5 V/div
VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (25 µs/div)
C017
C017
图 27. Small-Signal Step Response
(100 mV)
图 28. Large-Signal Step Response
VOUT
VIN
2.5 V/div
Output Voltage (1 mV/div)
0.01% Settling = “1mV
t0 = 45 µs
Time (25 µs/div)
45
C017
图 29. Large-Signal Step Response
版权 © 2016, Texas Instruments Incorporated
50
55
60
Time (5 µs/div)
65
C017
图 30. Large-Signal Settling Time
(10-V Positive Step)
13
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
60
0.01% Settling = “1mV
Output Voltage (1 mV/div)
50
ISC (mA)
30
10
t0 = 45 µs
50
0
55
60
65
Time (5 µs/div)
±75
±25
0
25
50
75
100
125
Temperature (ƒC)
150
C001
图 32. Short-Circuit Current vs Temperature
40
-60
Maximum output voltage without
slew-rate induced distortion.
35
±50
C017
图 31. Large-Signal Settling Time
(10-V Negative Step)
VS = ±18V
-80
Crosstalk (dB)
Output Voltage (VPP)
ISC, Source
20
45
30
ISC, Sink
40
25
20
15
VS = ±4V
-100
-120
10
-140
5
0
VS = ±2.25V
100
1k
10k
100k
-160
1M
Frequency (Hz)
1k
10k
100k
Frequency (Hz)
C001
图 33. Maximum Output Voltage vs Frequency
1M
C004
图 34. Crosstalk vs Frequency
180
160
EMIRR IN+ (dB)
140
120
100
80
60
40
20
0
10M
100M
1000M
Frequency (Hz)
C004
图 35. EMIRR IN+ vs Frequency
14
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www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
7 Detailed Description
7.1 Overview
The OPAx187 operational amplifier combines precision offset and drift with excellent overall performance,
making the device ideal for many precision applications. The precision offset drift of only 0.005 µV/°C provides
stability over the entire temperature range. In addition, this device offers excellent overall performance with high
CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
The OPAx187 device is part of a family of zero-drift, low-power, rail-to-rail output operational amplifiers. These
devices operate from 4.5 V to 36 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero input offset voltage
drift over temperature and time. This choice of architecture also offers outstanding ac performance, such as ultralow broadband noise and zero flicker noise.
7.2 Functional Block Diagram
图 36 shows a representation of the proprietary OPAx187 architecture. Functional blocks CHOP1 and CHOP2
operate such that the non-idealities of GM1 are cancelled while the input signal is left in-phase. The integrated
notch filter of the OPAx187 family suppresses most of the auto-zero amplifier carrier.
V+
C2
CHOP1
GM1
Notch
Filter
CHOP2
GM2
GM3
OUT
+IN
-IN
C1
GM_FF
VCopyright © 2016, Texas Instruments Incorporated
图 36. Functional Block Diagram
版权 © 2016, Texas Instruments Incorporated
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OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
7.3 Feature Description
The OPAx187 is unity-gain stable and free from unexpected output phase reversal. This device uses a
proprietary, periodic autocalibration technique to provide ultra-low input offset voltage and near zero input offset
voltage drift over temp and temperature. For lowest offset voltage and precision performance, optimize circuit
layout and mechanical conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in
the thermocouple junctions formed from connecting dissimilar conductors. Cancel these thermally-generated
potentials by making sure they are equal on both input pins. Other layout and design considerations include:
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
Thermally isolate components from power supplies or other heat sources.
Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which may cause
thermoelectric voltages of 0.1 µV/°C or higher, depending on the materials used.
7.3.1 Operating Characteristics
The OPAx187 device is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
7.3.2 Phase-Reversal Protection
The OPAx187 device has an internal phase-reversal protection. Many op amps exhibit a phase reversal when
the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output
to reverse into the opposite rail. The OPAx187 input prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. 图 37 shows this performance.
Voltage (5 V/div)
VIN
VOUT
Time (40 ms/div)
C017
图 37. No Phase Reversal
7.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers, such as the OPAx187, use switching on their inputs to correct for the intrinsic offset and drift
of the amplifier. Charge injection from the integrated switches on the inputs can introduce very short transients in
the input bias current of the amplifier. The extremely short duration of these pulses prevents them from being
amplified, however they may be coupled to the output of the amplifier through the feedback network. The most
effective method to prevent transients in the input bias current from producing additional noise at the amplifier
output is to use a low-pass filter such as an RC network.
7.3.4 Internal Offset Correction
The OPAx187 op amp uses an auto-calibration technique with a time-continuous 125-kHz op amp in the signal
path. This amplifier is zero-corrected every 22 μs using a proprietary technique. Upon power-up, the amplifier
requires approximately 100 μs to achieve the specified VOS accuracy. This design has no aliasing or flicker noise.
16
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OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
Feature Description (接
接下页)
7.3.5 EMI Rejection
The OPAx187 device uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx187
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. 图 38 shows the results of this testing on the OPAx187. 表 2 lists the EMIRR IN+ values for the OPAx187
at particular frequencies commonly encountered in real-world applications. Applications listed in 表 2 may be
centered on or operated near the particular frequency shown. Detailed information can also be found in EMI
Rejection Ratio of Operational Amplifiers, available for download from www.ti.com.
180
160
EMIRR IN+ (dB)
140
120
100
80
60
40
20
0
10M
100M
1000M
Frequency (Hz)
C004
图 38. EMIRR Testing
表 2. OPAx187 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION/ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency
(UHF) applications
81.8 dB
900 MHz
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
102.7 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band
(1 GHz to 2 GHz)
115.4 dB
®
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite, Sband (2 GHz to 4 GHz)
150.7 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
142.0 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
173.8 dB
7.3.6 Capacitive Load and Stability
The device dynamic characteristics are optimized for a range of common operating conditions. The combination
of low closed-loop gain and high capacitive loads decreases the amplifier phase margin and can lead to gain
peaking or oscillations. As a result, larger capacitive loads must be isolated from the output. The simplest way to
achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. 图 39
illustrates small-signal overshoot versus capacitive load for several values of ROUT. Also, for details of analysis
techniques and application circuits, refer to Feedback Plots Define Op Amp AC Performance, available for
download from www.ti.com.
版权 © 2016, Texas Instruments Incorporated
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OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
G = 1, RL = 10 kΩ, 10-mV Output Step
70
RISO = 0 Ÿ
Overshoot (%)
60
RISO = 25 Ÿ
RISO = 50 Ÿ
50
40
30
20
10
10
100
Capacitive Load (pF)
C004
图 39. Small-Signal Overshoot Versus Capacitive Load
7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See 图 40 for an illustration of the ESD circuits contained in the OPAx187 (indicated by the dashed line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal
to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx187
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in 图 40), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should
this condition occur, there is a risk that some internal ESD protection circuits may be biased on, and conduct
current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
图 40 shows a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
18
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OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source via the current-steering diodes. This state is not a
normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then
the current through the steering diodes can become quite high. The current level depends on the ability of the
input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, external TVS (Transient Voltage
Suppressor) diodes may be added to the supply pins, as shown in 图 40. The TVS voltage must be selected
such that the diode does not turn on during normal operation. However, the TVS voltage should be low enough
so that the TVS diode conducts if the supply pin begins to rise above the safe operating supply voltage level.
TVS
(See Note 2)
RF
V+
RI
+VS
ESD CurrentSteering Diodes
IN
(See Note 3)
RS
+IN
Op Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
(See
Note 1)
OUT
RL
V±
VS
TVS
(See Note 2)
Copyright © 2016, Texas Instruments Incorporated
NOTE 1: VIN = +VS + 500 mV.
NOTE 2: TVS: +VS(max) > VTVSBR (min) > +VS.
NOTE 3: Suggested value is approximately 1 kΩ.
图 40. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
The OPAx187 input terminals are protected from excessive differential voltage with back-to-back diodes, as
shown in 图 40. In most circuit applications, the input protection circuitry has no consequence. However, in lowgain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the
amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this
forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not
inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor
degrades the low-noise performance of the OPAx187. 图 40 shows an example configuration that implements a
current-limiting feedback resistor.
7.4 Device Functional Modes
The OPAx187 has a single functional mode, and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx187 is 36 V (±18 V).
版权 © 2016, Texas Instruments Incorporated
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OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx187 operational amplifier combines precision offset and drift with excellent overall performance,
making it ideal for many precision applications. The precision offset drift of only 0.005 µV/°C provides stability
over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR, and AOL dc performance
with outstanding low-noise operation. As with all amplifiers, applications with noisy or high-impedance power
supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
The following application examples highlight only a few of the circuits where the OPAx187 can be used.
8.2 Typical Applications
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in 图 41 is a high-side voltage-to-current (V-I) converter. The converter translates an input
voltage of 0 V to 2 V into an output current of 0 mA to 100 mA. 图 42 shows the measured transfer function for
this circuit. The low offset voltage and offset drift of the OPA2187 facilitate excellent dc accuracy for the circuit.
V+
RS2
470
RS3
4.7
IRS2
IRS3
R4
10 k
VRS2
VRS3
C7
2200 pF
R5
330
Q2
+
R3
200
+
Q1
C6
1000 pF
VIN
+
R2
10
±
VRS1
RS1
2k
IRS1
VLOAD
RLOAD
ILOAD
Copyright © 2016, Texas Instruments Incorporated
图 41. High-Side Voltage-to-Current (V-I) Converter
8.2.1.1 Design Requirements
The design requirements are:
20
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OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
Typical Applications (接
接下页)
•
•
•
Supply voltage: 5 V DC
Input: 0 V to 2 V DC
Output: 0 mA to 100 mA DC
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
This application benefits from an operational amplifier with low offset voltage, low temperature drift, and rail-torail output. The OPAx187 CMOS operational amplifier is a high-precision, ultra-low offset, ultra-low drift amplifier,
optimized for wide-voltage, single-supply operation, with an output swing to within 5 mV of the positive rail. The
OPAx187 family uses chopping techniques to provide low initial offset voltage and near-zero drift over time and
temperature. Low offset voltage and low drift reduce the offset error in the system, making this device
appropriate for precise dc control. The rail-to-rail output stage of the OPAx187 makes sure that the output swing
of the operational amplifier is able to fully control the gate of the MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in reference design
TIPD102, a step-by-step process to design a High-Side Voltage-to-Current (V-I) Converter.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD102, High-Side Voltage-to-Current (V-I) Converter (SLAU502).
8.2.1.3 Application Curves
图 42 shows the measured transfer function for the high-side voltage-to-current converter shown in 图 41.
0.1
Load
Output Current (A)
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
图 42. Measured Transfer Function for High-Side V-I Converter
8.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
注
The TINA-TI files shown in the following sections require that either the TINA software
(from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software
from the TINA-TI folder.
版权 © 2016, Texas Instruments Incorporated
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OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
图 43 shows an example of how the OPAx187 is used as a high-voltage, high-impedance front-end for a
precision, discreet instrumentation amplifier with attenuation. The INA159 provides the attenuation that allows
this circuit to easily interface with 3.3-V or 5-V analog-to-digital converters (ADCs). Click the following link
download the TINA-TI file: Discrete INA.
15 V
VOUTP
OPA187
5V
VDIFF / 2
- 15 V
RP
10 NŸ
Ref 1
VCM
10V
Ref 2
RG
500 Ÿ
+
VOUT(1)
INA159
Sense
15 V
±VDIFF / 2
OPA187
RN
10 NŸ
VOUTN
15 V
Copyright © 2016, Texas Instruments Incorporated
(1)
VOUT = VDIFF × (41 / 5) + (Ref 1) / 2.
图 43. Discrete INA + Attenuation for ADC With 3.3-V Supply
8.2.3 Bridge Amplifier
图 44 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI file:
Bridge Amplifier Circuit.
15 V
R
15 V
R
R
R
R
±
OPA187
VOUT
+
R
VREF
Copyright © 2016, Texas Instruments Incorporated
图 44. Bridge Amplifier
8.2.4 Low-Side Current Monitor
图 45 shows the OPAx187 configured in a low-side current-sensing application. The load current (ILOAD) creates
a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the OPAx187, with a gain of 201.
The load current is set from 0 A to 500 mA, which corresponds to an output voltage range from 0 V to 10 V. The
output range can be adjusted by changing the shunt resistor or gain of the configuration. Click the following link
to download the TINA-TI file: Current-Sensing Circuit.
22
版权 © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
V
Load
15 V
+
VOUT = ILOAD * RSHUNT(1 + RF / RIN)
VOUT
OPA187
±
ILOAD
RSHUNT
100 m
RIN
VOUT / ILOAD= 1 V / 49.75 mA
RF
100
20 k
CF
150
pF
Copyright © 2016, Texas Instruments Incorporated
图 45. Low-Side Current Monitor
8.2.5 Programmable Power Supply
图 46 shows the OPAx187 configured as a precision programmable power supply using the 16-bit, voltage output
DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter (DAC)
voltage by a value of five, and handles a large variety of capacitive and current loads. The OPAx187 in the frontend provides precision and low drift across a wide range of inputs and conditions. Click the following link to
download the TINA-TI file: Programmable Power-Supply Circuit.
C1
500 nF
R1
10 k
GND
R4
40 k
R2
1k
C2
500 nF
+30V
+15V
±
OPA187
DAC8581
±
R3
10 k
OPA548
+
+
VOUT
Output = ± 25V
±30V
±15V
Input = ± 5V
Copyright © 2016, Texas Instruments Incorporated
图 46. Programmable Power Supply
版权 © 2016, Texas Instruments Incorporated
23
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
8.2.6 RTD Amplifier With Linearization
See Analog Linearization Of Resistance Temperature Detectors, for an in-depth analysis of 图 47. Click the
following link to download the TINA-TI file: RTD Amplifier With Linearization.
15 V
(5 V)
Out
REF5050
In
1 µF
1 µF
R2
49.1 kŸ
R3
60.4 kŸ
R1
4.99 kŸ
OPA187
V OUT
0°C = 0 V
200°C = 5 V
R5
(1)
105.8 kŸ
RTD
Pt100
R4
1 kŸ
Copyright © 2016, Texas Instruments Incorporated
(1)
R5 provides positive-varying excitation to linearize output.
图 47. RTD Amplifier With Linearization
9 Power Supply Recommendations
The OPAx187 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. The Typical Characteristics presents parameters that can exhibit significant variance with
regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the
Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
24
版权 © 2016, Texas Instruments Incorporated
OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Low-ESR, 0.1-µF ceramic bypass capacitors must be connected between each supply pin and ground; place
the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is applicable
to single-supply applications.
• To reduce parasitic coupling, run the input traces as far away from the supply lines as possible.
• A ground plane helps distribute heat and reduces EMI noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
VOUT
GND
VOUT
Use low-ESR, ceramic
bypass capacitor
Ground (GND) plane on another layer
Copyright © 2016, Texas Instruments Incorporated
图 48. Layout Example
版权 © 2016, Texas Instruments Incorporated
25
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™(免费软件下载)
TINA™是一款简单、功能强大且易于使用的电路仿真程序,此程序基于 SPICE 引擎。 TINA-TI™是 TINA 软件的
一款免费全功能版本,除了一系列无源和有源模型外,此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有
传统的 SPICE 直流 (DC)、瞬态和频域分析以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center(模拟电子实验室设计中心)免费下载,它提供全面的后续处理能力,
使得用户能够以多种方式形成结果。虚拟仪器为用户提供选择输入波形和探测电路节点、电压和波形的功能,从而
创建一个动态的快速入门工具。
注
这些文件需要安装 TINA 软件(由 DesignSoft™提供)或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 TI 高精度设计
TI 高精度设计是由 TI 公司的高精度模拟 应用 专家创建的模拟解决方案,提供了许多实用电路的工作原理、组件选
择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。欲获取 TI 高精度设计,
请访问 http://www.ti.com/ww/en/analog/precision-designs/。
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer 是一款简单、功能强大且便于使用的有源滤波器设计程序。此WEBENCH
Designer 通过选择 TI 运算放大器以及 TI 供应商合作伙伴的无源组件来构建优化滤波器设计方案。
Filter
WEBENCH 设计中心以基于网络的工具形式提供 WEBENCH® Filter Designer,用户通过该工具可在短时间内完成
多级有源滤波器解决方案的设计、优化和仿真。
11.2 文档支持
11.2.1 相关文档 相关文档如下:
• 运算放大器增益稳定性,第 3 部分:交流增益误差分析
• 运算放大器增益稳定性,第 2 部分:直流增益误差分析
• 《在全差分有源滤波器中使用无限增益、MFB 滤波器拓扑》
• 运算放大器性能分析
• 运算放大器的单电源操作
• 调优放大器
• 无铅成品组件的储存寿命评估
26
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OPA187, OPA2187, OPA4187
www.ti.com.cn
ZHCSFV2 – DECEMBER 2016
11.3 相关链接
表 3 列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件,并且可以快速访问样片或购买链
接。
表 3. 相关链接
器件
产品文件夹
样片和购买
技术文档
工具与软件
支持和社区
OPA187
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
OPA2187
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
OPA4187
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
11.4 接收文档更新通知
如需接收文档更新通知,请访问 ti.com 上的器件产品文件夹。点击右上角的提醒我 (Alert me) 按钮注册后,即可每
周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录
11.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 商标
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
DesignSoft, TINA are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016, Texas Instruments Incorporated
27
OPA187, OPA2187, OPA4187
ZHCSFV2 – DECEMBER 2016
www.ti.com.cn
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
28
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2187ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2187
OPA2187IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16TV
OPA2187IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16TV
OPA2187IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2187
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Aug-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
重要声明
德州仪器 (TI) 公司有权按照最新发布的 JESD46 对其半导体产品和服务进行纠正、增强、改进和其他修改,并不再按最新发布的 JESD48 提
供任何产品和服务。买方在下订单前应获取最新的相关信息,并验证这些信息是否完整且是最新的。
TI 公布的半导体产品销售条款 (http://www.ti.com/sc/docs/stdterms.htm) 适用于 TI 已认证和批准上市的已封装集成电路产品的销售。另有其
他条款可能适用于其他类型 TI 产品及服务的使用或销售。
复制 TI 数据表上 TI 信息的重要部分时,不得变更该等信息,且必须随附所有相关保证、条件、限制和通知,否则不得复制。TI 对该等复制文
件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售 TI 产品或服务时,如果存在对产品或服务参数的虚假陈述,则会失去
相关 TI 产品或服务的明示或暗示保证,且构成不公平的、欺诈性商业行为。TI 对此类虚假陈述不承担任何责任。
买方和在系统中整合 TI 产品的其他开发人员(总称“设计人员”)理解并同意,设计人员在设计应用时应自行实施独立的分析、评价和判断,且
应全权 负责并确保 应用的安全性, 及设计人员的 应用 (包括应用中使用的所有 TI 产品)应符合所有适用的法律法规及其他相关要求。设计
人员就自己设计的 应用声明,其具备制订和实施下列保障措施所需的一切必要专业知识,能够 (1) 预见故障的危险后果,(2) 监视故障及其后
果,以及 (3) 降低可能导致危险的故障几率并采取适当措施。设计人员同意,在使用或分发包含 TI 产品的任何 应用前, 将彻底测试该等 应用
和 该等应用中所用 TI 产品的 功能。
TI 提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息,包括但不限于与评估模块有关的参考设计和材料(总称“TI 资
源”),旨在帮助设计人员开发整合了 TI 产品的 应用, 如果设计人员(个人,或如果是代表公司,则为设计人员的公司)以任何方式下载、
访问或使用任何特定的 TI 资源,即表示其同意仅为该等目标,按照本通知的条款使用任何特定 TI 资源。
TI 所提供的 TI 资源,并未扩大或以其他方式修改 TI 对 TI 产品的公开适用的质保及质保免责声明;也未导致 TI 承担任何额外的义务或责任。
TI 有权对其 TI 资源进行纠正、增强、改进和其他修改。除特定 TI 资源的公开文档中明确列出的测试外,TI 未进行任何其他测试。
设计人员只有在开发包含该等 TI 资源所列 TI 产品的 应用时, 才被授权使用、复制和修改任何相关单项 TI 资源。但并未依据禁止反言原则或
其他法理授予您任何TI知识产权的任何其他明示或默示的许可,也未授予您 TI 或第三方的任何技术或知识产权的许可,该等产权包括但不限
于任何专利权、版权、屏蔽作品权或与使用TI产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务
的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用 TI 资源可能需要您向第三方获得对该等第三方专利或其他知识产权
的许可。
TI 资源系“按原样”提供。TI 兹免除对资源及其使用作出所有其他明确或默认的保证或陈述,包括但不限于对准确性或完整性、产权保证、无屡
发故障保证,以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。TI 不负责任何申索,包括但不限于因组合产品所致或
与之有关的申索,也不为或对设计人员进行辩护或赔偿,即使该等产品组合已列于 TI 资源或其他地方。对因 TI 资源或其使用引起或与之有关
的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿,不管 TI 是否获悉可能会产生上述损害赔
偿,TI 概不负责。
除 TI 已明确指出特定产品已达到特定行业标准(例如 ISO/TS 16949 和 ISO 26262)的要求外,TI 不对未达到任何该等行业标准要求而承担
任何责任。
如果 TI 明确宣称产品有助于功能安全或符合行业功能安全标准,则该等产品旨在帮助客户设计和创作自己的 符合 相关功能安全标准和要求的
应用。在应用内使用产品的行为本身不会 配有 任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和 标准。设计人员不可将
任何 TI 产品用于关乎性命的医疗设备,除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是
指出现故障会导致严重身体伤害或死亡的医疗设备(例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设
备)。此类设备包括但不限于,美国食品药品监督管理局认定为 III 类设备的设备,以及在美国以外的其他国家或地区认定为同等类别设备的
所有医疗设备。
TI 可能明确指定某些产品具备某些特定资格(例如 Q100、军用级或增强型产品)。设计人员同意,其具备一切必要专业知识,可以为自己的
应用选择适合的 产品, 并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。
设计人员同意向 TI 及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和/或责任。
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