NCV8141 - Linear Regulator with Enable Reset and Watchdog

NCV8141 - Linear Regulator with Enable Reset and Watchdog

NCV8141

5.0 V, 500 mA Linear

Regulator with ENABLE,

RESET, and Watchdog

The NCV8141 is a linear regulator suited for microprocessor applications in automotive environments.

This ON Semiconductor part provides the power for the microprocessors along with many of the control functions needed in today’s computer based systems. Incorporating all of these features saves both cost, and board space.

The NCV8141 provides a low sleep mode current as compared to the CS8141. Consult your local sales representative for a low sleep mode current version of the CS8140.

Features

5.0 V

± 3.0%, 500 mA Output Voltage

Lower Quiescent Current

Improved Filtering for /RESET Functionality

• mP Compatible Control Functions

Watchdog

RESET

ENABLE

Low Dropout Voltage (1.25 V @ 500 mA)

Low Quiescent Current (7.0 mA @ 500 mA)

Low Noise, Low Drift

Low Current SLEEP Mode 50 mA (max)

Fault Protection

Thermal Shutdown

Short Circuit

60 V Peak Transient Voltage

These are Pb−Free Devices

NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes

http://onsemi.com

MARKING

DIAGRAM

1

D

2

PAK−7

DPS SUFFIX

CASE 936AB

NC

V8141

AWLYWWG

1

A = Assembly Location

WL = Wafer Lot

Y = Year

WW = Work Week

G = Pb−Free Package

1

PIN CONNECTIONS

Tab = GND

Pin 1. V

IN

2. ENABLE

3. RESET

4. GND

5. Delay

6. WDI

7. V

OUT

ORDERING INFORMATION

Device Package Shipping

NCV8141D2TG D

2

PAK

(Pb−Free)

NCV8141D2TR4G D

2

PAK

(Pb−Free)

50 Units/Rail

750/Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2009

October, 2009 − Rev. 13

1

Publication Order Number:

NCV8141/D

NCV8141

V

IN

Reference & Bias

Overvoltage

Overtemperature

Regulation

ENABLE

WDI

GND

Control Logic

ENABLE

RESET

Delay

Watchdog

Short Circuit

Undervoltage

Figure 1. Block Diagram

PIN FUNCTION DESCRIPTION

Pin

4

5

6

1

2

3

7

Symbol

V

IN

ENABLE

RESET

GND

Delay

WDI

V

OUT

Function

Supply voltage to IC, usually direct from the battery.

CMOS compatible logical input. V

OUT

is disabled when ENABLE is LOW and WDI is invalid.

CMOS compatible output lead. RESET goes low whenever V

OUT

drops 4.5% below its typical value for more than 2.0 ms or WDI signal falls below the watchdog threshold frequency.

Ground Connection.

Timing capacitor for Watchdog and RESET functions.

CMOS compatible input lead. The Watchdog function monitors the falling edge of the incoming digital pulse train. The signal is usually generated by the system microprocessor.

Regulated output voltage, 5.0 V (typ).

V

OUT

Sense

RESET

Delay

http://onsemi.com

2

NCV8141

MAXIMUM RATINGS

Rating

Input Operating Range

Peak Transient Voltage (46 V Load Dump @ 14 V V

BAT

)

Electrostatic Discharge (Human Body Model)

Value

−0.5 to 26

60

4.0

Unit

V

V kV

WDI Input Signal Range

Internal Power Dissipation

−0.3 to 7.0

Internally Limited

V

Junction Temperature Range (T

Storage Temperature Range

J

) −40 to +150

−65 to +150

°C

°C

ENABLE −0.3 to V

IN

V

Package Thermal Resistance, D

2

PAK 7−Pin

Junction−to−Case, R qJC

Junction−to−Ambient, R qJA

1.5

10−50†

°C/W

°C/W

Lead Temperature Soldering:

Reflow (SMD styles only) (Note 1) 225 peak (Note 2)

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

†Depending on thermal properties of substrate R qJA

= R

1. 60 seconds max above 183°C.

2. −5.0°C/+0°C allowable conditions.

qJC

+ R qCA

.

ELECTRICAL CHARACTERISTICS

(7.0 ≤ V

noted.) (Note 3)

IN

≤ 26 V, 5.0 mA ≤ I

OUT

≤ 500 mA, −40°C ≤ T

J

≤ 150°C, −40°C ≤ T

A

≤ 125°C, unless otherwise

Characteristic Test Conditions Min Typ Max Unit

Output Stage (V

OUT

)

Output Voltage, V

OUT

Dropout Voltage (V

IN

Line Regulation

Load Regulation

Output Impedance, R

− V

OUT

OUT

)

7.0 V ≤ V

IN

≤ 26 V, 5.0 mA < I

OUT

< 500 mA

I

OUT

= 500 mA

I

OUT

= 50 mA, 7.0 V ≤ V

IN

≤ 26 V,

V

IN

= 14 V, 50 mA ≤ I

OUT

≤ 500 mA

500 mA DC and 10 mA AC,

100 Hz ≤ f ≤ 10 kHz

4.85

Quiescent Current, (I

Active Mode

Sleep Mode

Ripple Rejection

Q

)

I

0 ≤ I

OUT

OUT

≤ 500 mA, 7.0 V ≤ V

= 0 mA, V

IN

IN

≤ 26 V

= 13 V, ENABLE = 0 V

7.0 V ≤ V

IN

≤ 17 V, I

OUT f = 120 Hz

= 250 mA,

60

7.0

25

75

Current Limit

Thermal Shutdown

Overvoltage Shutdown

ENABLE

Threshold

HIGH

LOW

Input Current

HIGH

LOW

V

IN

= 7.0 V, V

Guaranteed by Design

V

OUT

V

OUT

V

OUT

OUT

< 1.0 V

≥ 0.5 V, (V

OUT(ON)

< 0.5 V, (V

= 4.5 V

OUT(OFF)

ENABLE = 5.0 V

ENABLE = 0 V

)

)

600

150

30

3.5

−1.0

1200

180

34

4.05

3.95

35

0

Threshold Hysteresis (HIGH − LOW) − 80

3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.

5.0

1.25

5.0

5.0

200

5.15

1.50

25

80

75

1.0

15

50

2000

38

4.50

V

V mV mV mW mA mA dB mA

°C

V

V

V mA mA mV

http://onsemi.com

3

NCV8141

ELECTRICAL CHARACTERISTICS (continued)

(7.0 ≤ V

125°C, unless otherwise noted.) (Note 4)

IN

≤ 26 V, 5.0 mA ≤ I

OUT

≤ 500 mA, −40°C ≤ T

J

≤ 150°C, −40°C ≤ T

A

Characteristic Test Conditions Min Typ Max Unit

RESET

Threshold HIGH V

R(HI)

Threshold LOW V

R(LOW)

Threshold Hysteresis (V

RH

)

RESET Output Leakage

RESET = HIGH

V

OUT

V

OUT

V

Increasing

Decreasing

(HIGH − LOW)

OUT

≥ V

R(HI)

4.65

4.50

150

4.90

4.70

200

Output Voltage Low (V

L(LOW)

)

Output Voltage Low (V

Rpeak

)

Delay Time t

POR

Delay Time t

WDI(RESET)

Watchdog

1.0 V ≤ V

V

OUT

OUT

≤ V

, Power up, Power down

C

C

R(LOW)

DELAY

DELAY

, R

P

= 2.7 kW (Note 5)

= 0.1 mF

= 0.1 mF

30

0.5

0.1

0.6

47.5

1.0

Input Voltage High

Input Voltage Low

2.0

Input Current WDI ≤ V

OUT

− 0

Threshold Frequency f

WDI

C

DELAY

= 0.1 mF 64 77

4. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.

5. R

P

is connected to RESET and V

OUT.

V

OUT

− 0.05

4.90

250

25

0.8

10

105

0.4

1.0

65

1.5

ms ms

V

V

V

V mV mA

V

V mA

Hz

http://onsemi.com

4

NCV8141

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

0.6

0.4

0.2

1.4

1.2

1.0

−40°C

+25°C

+125°C

0

0

50 100 150 200 250 300 350

OUTPUT CURRENT (mA)

400 450

Figure 2. Dropout Voltage vs. Output Current over

Temperature

500

1.2

1.1

1.0

0.9

0.8

0.7

0.6

I out

= 500 mA

I out

= 350 mA

I out

= 100 mA

I out

= 10 mA

−20 0 20 40 60

TEMPERATURE (°C)

80 100 120

Figure 3. Dropout Voltage vs. Temperature

1000

Unstable Region

100

10

1

0.1

0.01

0

125°C

Stable Region

25°C

−40°C

C vout

= 1 mF to 10 mF

10 20 30 40 50

OUTPUT CURRENT (mA)

Figure 4. Output Stability

60 70

1000

Unstable Region

100

10 mF

0.1 mF

10

Stable Region

1

T = 25°C

0.1

0.01

0

NOTE: At 125°C an additional area of instability occurs

(0.1 mF only) for loads less than 5 mA and low ESR.

10 20 30 40 50

OUTPUT CURRENT (mA)

60 70

Figure 5. Output Stability with Capacitor Change

52

51

50

55

54

53

49

48

C delay

= 0.1 mF

−20 0 20 40 60 80

TEMPERATURE (°C)

100 120 140 160

Figure 6. Delay Time http://onsemi.com

5

NCV8141

DEFINITION OF TERMS

Dropout Voltage:

The input−output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature.

Input Voltage:

The DC voltage applied to the input terminals with respect to ground.

Line Regulation:

The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected.

Load Regulation:

The change in output voltage for a change in load current at constant chip temperature.

Quiescent Current:

The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current.

Ripple Rejection: The ratio of the peak−to−peak input ripple voltage to the peak−to−peak output ripple voltage.

Current Limit:

output.

Peak current that can be delivered to the

CIRCUIT DESCRIPTION

The NCV8141 is a 5.0 V Watchdog Regulator with protection circuitry and three logic control functions that allow a microprocessor to control its own power supply. The

NCV8141 is designed for use in automotive, switch mode power supply post regulator, and battery powered systems.

Basic regulator performance characteristics include a low noise, low drift, 5.0 V

±3.0% precision output voltage with low dropout voltage (1.25 V @ I

OUT

= 500 mA) and low quiescent current (7.0 mA @ I

OUT

= 500 mA). On board short circuit, thermal, and overvoltage protection make it possible to use this regulator in particularly harsh operating environments.

The Watchdog logic function monitors an input signal

(WDI) from the microprocessor or other signal source.

When the signal frequency goes below the externally programmable limit, a RESET signal is generated (RESET).

Proper operation has been verified at a frequency up to 100 kHz. No abnormal RESET signals will occur with frequencies lower than 100 kHz and the maximum

Threshold Frequency (96 Hz). An external capacitor

(C

DELAY

) programs the watchdog frequency limit as well as the power on reset (POR) and RESET delay.

The RESET function is activated by any of three conditions: the watchdog signal moves outside of its preset limits; the output voltage drops out of regulation by more than 4.5%; or the IC is in its power up sequence. The RESET signal is independent of V

IN

and reliable down to V

OUT

=

1.0 V.

In conjunction with the Watchdog, the ENABLE function controls the regulator’s power consumption. The

NCV8141’s output stage and its attendant circuitry are enabled by setting the ENABLE lead high. The regulator goes into sleep mode when the ENABLE lead goes low and the watchdog signal moves outside its preset limit. This unique combination of control functions in the NCV8141 gives the microprocessor control over its own power down sequence: i.e. it gives the microprocessor the flexibility to perform housekeeping functions before it powers down.

VOLTAGE REFERENCE AND OUTPUT CIRCUITRY

Precision Voltage Reference

The regulated output voltage depends on the precision band gap voltage reference in the IC. By adding an error amplifier into the feedback loop, the output voltage is maintained within

±3.0% over temperature and supply variation.

Output Stage

The composite PNP−NPN output structure (Figure 7)

provides 500 mA (min) of output current while maintaining a low drop out voltage (1.25 V) and drawing little quiescent current (7.0 mA).

V

IN

V

OUT

Figure 7. Composite Output Stage of the NCV8141

The NPN pass device prevents deep saturation of the output stage which in turn improves the IC’s efficiency by preventing excess current from being used and dissipated by the IC.

Output Stage Protection

The output stage is protected against overvoltage, short

circuit and thermal runaway conditions (Figure 8).

If the input voltage rises above 30 V (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients.

http://onsemi.com

6

NCV8141

Using an emitter sense scheme, the amount of current through the NPN pass transistor is monitored. Feedback circuitry insures that the output current never exceeds a preset limit.

> 30 V

V

IN

V

OUT

I

O

Load

Dump

Short

Circuit

Thermal

Shutdown

Figure 8. Typical Circuit Waveforms for Output

Stage Protection

Should the junction temperature of the power device exceed 180

°C (typ), the power transistor is turned off.

Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.

REGULATOR CONTROL FUNCTIONS

The NCV8141 differs from all other linear regulators in its unique combination of control features.

Watchdog and ENABLE Function

V

OUT

is controlled by the logic functions ENABLE and

Watchdog (Table 1).

Table 1. V

OUT

as a Function of ENABLE and Watchdog

V

OUT

(V)

WDI

ENABLE

H

L

Slow

5

0

Normal

5

5

High

5

0

Low

5

0

As long as ENABLE is high or ENABLE is low and the

Watchdog signal is normal, V

OUT

will be at 5.0 V (typ). If

ENABLE is low and the frequency of the Watchdog input goes below the threshold frequency, the output transistor turns off and the IC goes into SLEEP mode. Only the

ENABLE circuitry in the IC remains powered up, drawing a quiescent current of less than 50 mA.

The Watchdog monitors the frequency of an incoming

WDI signal. If the signal falls below the WDI limit, a frequency programmable pulse train is generated at the

RESET lead (Figure 9) until the correct Watchdog input

signal reappears at the lead (ENABLE = HIGH).

The threshold limit of the watchdog function is set by the value of C

DELAY

. The limit is determined according to the following equation for the NCV8141: tWDI + (1.3 105)CDELAY or

The capacitor C

DELAY

also determines the frequency of the RESET signal and the POWER−ON−RESET (POR) delay period.

RESET Function

The RESET function is activated when the Watchdog frequency signal is below the watchdog threshold

(Figure 9), when the regulator is in its power up state

(Figure 10) or when V

OUT

drops below V

OUT

−4.5% for more than 2.0

ms (Figure 11)

If the Watchdog signal falls outside of the preset voltage or below the frequency threshold, a frequency programmable pulse train is generated at the RESET lead

(Figure 9) until the correct Watchdog input signal reappears

at the lead. The duration of the RESET pulse is determined by C

DELAY

according to the following equation: tWDI(RESET) + (1.0 104)CDELAY

RESET CIRCUIT WAVEFORMS WITH DELAYS

INDICATED

If an undervoltage condition exists, the voltage on the

RESET lead goes low and the delay capacitor, C

DELAY

, is discharged. RESET remains low until output is in regulation, the voltage on C

DELAY

exceeds the upper

threshold and the Watchdog input signal is valid (Figures 10 and 11). The delay after the output is in regulation is:

tPOR(typ) + (4.75 105)CDELAY

The RESET delay circuit is also programmed with the external cap C

DELAY

.

The output of the reset circuit is an open collector NPN.

RESET is operational down to V

OUT

= 1.0 V. Both RESET and its delay are governed by comparators with hysteresis to avoid undesirable oscillations.

http://onsemi.com

7

V

OUT

When Watchdog is Held

High and ENABLE = HIGH

V

IN

ENABLE

WDI

RESET

V

OUT

0 V

0 V

0 V

NCV8141

Batt

Batt

POR Normal Operation

Batt

Batt

V

OUT

When Watchdog is Held Low and ENABLE = HIGH

V

IN

ENABLE

WDI

RESET

V

OUT

0 V

0 V

0 V

POR Normal Operation

V

OUT

When Watchdog is too Slow and ENABLE = HIGH

V

IN

ENABLE

WDI

RESET

V

OUT

0 V

0 V

0 V

Batt

Batt

POR Normal Operation

WDI held High

WDI held Low

Slow WDI signal

WDI Held High After a Normal Period of Operation; ENABLE = LOW

V

IN

ENABLE

WDI

RESET

V

OUT

0 V

0 V

0 V

Batt

Batt

POR Normal Operation

WDI high

Sleep Mode

Batt

Batt

POR Normal Operation

WDI Held Low or is too Slow after a Normal Period of Operation;

ENABLE = LOW

V

IN

ENABLE

WDI

RESET

V

OUT

0 V

0 V

0 V

POR

Normal

Operation

WDI low

Sleep Mode POR Normal Operation

Figure 9. Timing Diagrams for Watchdog and ENABLE Functions

V

OUT

V

R(HI)

V

R(LO)

RESET

V

R(PEAK)

V

R(LO) t

POR

Figure 10. Power RESET and Power Down

V

OUT

V

OUT

−4.5%

RESET

5.0 V

< 6.0 ms ≥ 6.0 ms t

POR

Figure 11. Undervoltage Triggered RESET http://onsemi.com

8

NCV8141

APPLICATION NOTES

NCV8141 DESIGN EXAMPLE

The NCV8141 with its unique integration of linear regulator and control features: RESET, ENABLE and

WATCHDOG, provides a single IC solution for a microprocessor power supply. The reset delay, reset duration and watchdog frequency limit are all determined by a single capacitor. For a particular microprocessor the overriding requirement is usually the reset delay (also known as power on reset). The capacitor is chosen to meet this requirement and the reset duration and watchdog frequency follow.

The reset delay is given by: tPOR(typ) + (4.75 105)CDELAY

Assume that the reset delay must be 200 ms minimum.

From the NCV8141 data sheet the reset delay has a $37% tolerance due to the regulator.

Assume the capacitor tolerance is $10%.

tPOR(min) + (4.75 105 0.63) CDELAY 0.9

CDELAY(min) + tPOR(min)

2.69 105

CDELAY(min) + 0.743 mF

Closest standard value is 0.82 mF.

Minimum and maximum delays using 0.82 mF are 220 ms and 586 ms.

The duration of the reset pulse is given by:

TWDI(RESET)(typ) + (1.0 104) CDELAY

This has a tolerance of ±50% due to the IC, and ±10% due to the capacitor.

The duration of the reset pulse ranges from 3.69 ms to

13.5 ms.

The watchdog signal can be expressed as a frequency or time. From a programmers point of view, time is more useful since they must ensure that a watchdog signal is issued consistently several times per second.

The watchdog time is given by: tWDI + (1.3 105)CDELAY

There is a tolerance of ±20% due to the NCV8141.

With a capacitor tolerance of

±10%: tWDI + (1.3 105) 1.2 1.1 CDelay tWDI + 141 ms (max) tWDI + (1.3 105) 0.8 0.9 CDELAY tWDI + 76 ms (min)

The software must be written so that a watchdog signal arrives at least every 76 ms.

FAIL

Hz ms

7

141

13

76

PASS

Figure 12. WDI Signal for C

Delay

NCV8141

= 0.82 mF using

ENERGY CONSERVATION AND SMART FEATURES

Energy conservation is another benefit of using a regulator with integrated microprocessor control features.

Using the NCV8141 as indicated in Figure 13, the

microprocessor can control its own power down sequence.

The momentary contact switch quickly charges C1 through

R1.

When the voltage across C1 reaches 3.95 V ( the enable threshold), the output switches on and V

OUT

rises to 5.0 V.

After a delay period determined by C

Delay

, a frequency programmable reset pulse train is generated at the reset output. The pulse train continues until the correct watchdog signal appears at the WDI lead. C1 is now left to discharge through the input impedance of the enable lead

(approximately 150 k W) and the enable signal disappears.

The output voltage remains at 5.0 V as long as the NCV8141 continues to receive the correct watchdog signal.

The microprocessor can power itself down by terminating its watchdog signal. When the microprocessor finishes its housekeeping or power down software routine, it stops sending a watchdog signal. In response, the regulator generates a reset signal and goes into a sleep mode where

V

OUT

drops to 0 V, shutting down the microprocessor.

http://onsemi.com

9

9.0 V

R

1

110 K

Switch

C

1

0.1 mF

NCV8141

V

IN

V

OUT

NCV8141

ENABLE

C

DELAY

C

2

0.1 mF

RESET

WDI

GND

10 mF

V

CC

2.7 kW

Microprocessor

RESET

WATCHDOG PORT

Figure 13. Application Diagram for NCV8141. The NCV8141 Provides a 5.0 V Tightly Regulated

Supply and Control Function to the Microprocessor. In this Application, the Microprocessor

Controls its own Power Down Sequence (see text).

http://onsemi.com

10

NCV8141

Battery

C

1

*

0.1 mF

(optional)

V

IN

NCV8141

V

OUT

C

2

*

10 mF*

2.7 kW

V

CC

Ignition

0.1 mF

ENABLE

DELAY

GND

RESET

WDI

RESET

WATCHDOG

PORT

R***

Microprocessor

*C1 is required if regulator is located far from the power source filter.

**C2 is required for stability.

***R ≤ 80 kW.

Figure 14. Application Diagram

STABILITY CONSIDERATIONS

The output or compensation capacitor C

2

in Figure 14

helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability.

The capacitor value and type should be based on cost, availability, size and temperature constraints. An aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25

°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.

The value for the output capacitor C

2

shown in Figure 14

should work for most applications, however it is not necessarily the optimized solution.

To determine an acceptable value for C

2

for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.

Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible.

Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions.

Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature.

Step 4: Maintain the worst case load conditions set in

Step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions.

Step 5: If the capacitor is adequate, repeat Steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat Steps 3 and 4 with the next larger standard capacitor value.

Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing.

Step 7: Increase the temperature to the highest specified operating temperature. Vary the load current as instructed in

Step 5 to test for any oscillations.

Once the minimum capacitor value with the maximum

ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than

50% of the maximum allowable ESR found in Step 3 above.

CALCULATING POWER DISSIPATION IN A SINGLE

OUTPUT LINEAR REGULATOR

The maximum power dissipation for a single output

regulator (Figure 15) is:

PD(max) +

NJ

VIN(max) * VOUT(min)

Nj

IOUT(max) ) VIN(max)IQ where:

V

IN(max)

is the maximum input voltage,

V

OUT(min)

is the minimum output voltage,

I

OUT(max)

is the maximum output current for the application, and

(1)

http://onsemi.com

11

I

Q

is the quiescent current the regulator consumes at

I

OUT(max)

.

I

IN

I

OUT

V

IN

SMART

REGULATOR

®

Control

Features

V

OUT

I

Q

Figure 15. Single Output Regulator With Key

Performance Parameters Labeled

Once the value of P

D(max)

is known, the maximum permissible value of R qJA

can be calculated:

RqJA +

150° C * TA

PD

(2)

The value of R qJA

can then be compared with those in the package section of the data sheet. Those packages with

R qJA

’s less than the calculated value in Equation 2 will keep the die temperature below 150 °C.

NCV8141

In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.

HEATSINKS

A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.

Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R qJA

.

RqJA + RqJC ) RqCS ) RqSA

(3) where:

R qJC

= the junction−to−case thermal resistance,

R

R

R qCS qSA qJC

R qJA

= the case−to−heatsink thermal resistance, and

= the heatsink−to−ambient thermal resistance.

appears in the package section of the data sheet. Like

, it too is a function of package type. R qCS

and R qSA

are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers.

http://onsemi.com

12

NCV8141

PACKAGE DIMENSIONS

L1

D

E

E/2

7X b

0.13

M B A M

e

H

A c

A

RECOMMENDED

SOLDERING FOOTPRINT*

0.424

A

D

2

PAK−7 (SHORT LEAD)

CASE 936AB−01

ISSUE B

B

SEATING

PLANE c2

DETAIL C

A

H

D1

0.10

M

E1

B A

VIEW A−A

M

B

A1

SEATING

PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH AND GATE PROTRUSIONS. MOLD FLASH

AND GATE PROTRUSIONS NOT TO EXCEED

0.005 MAXIMUM PER SIDE. THESE DIMENSIONS

TO BE MEASURED AT DATUM H.

4. THERMAL PAD CONTOUR OPTIONAL WITHIN

DIMENSIONS E, L1, D1, AND E1. DIMENSIONS

D1 AND E1 ESTABLISH A MINIMUM MOUNTING

SURFACE FOR THE THERMAL PAD.

INCHES MILLIMETERS

DIM

A

MIN MAX

0.170

0.180

A1

0.000

0.010

b

0.026

0.036

c c2

D

0.017

D1

0.270

E e

H

L

L1

L3

M

0.026

0.045

0.055

0.325

0.368

−−−

0.380

0.420

E1

0.245

−−−

0.050 BSC

0.539

0.058

0.078

−−− 0.066

MIN

4.32

0.00

0.66

0.43

1.14

8.25

6.86

9.65

6.22

−−−

1.27 BSC

0.579

13.69

1.47

−−−

14.71

1.98

1.68

0.010 BSC

0 ° 8 °

0.25 BSC

0 ° 8 °

MAX

4.57

0.25

0.91

0.66

1.40

9.53

−−−

10.67

L

M

0.310

L3

GAUGE

PLANE

DETAIL C

0.584

0.136

7X

0.040

0.050

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

http://onsemi.com

13

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative

NCV8141/D

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement