ASICs... the website

ASICs... the website
L ast E d ited by S P 14112 0 0 4
INTRODUCTION TO ASICs
An ASIC (pronounced a-sick; bold typeface defines a new term) is an
application-specific integrated circuit at least that is what the acronym stands for.
Before we answer the question of what that means we first look at the evolution
of the silicon chip or integrated circuit ( IC ).
Figure 1.1(a) shows an IC package (this is a pin-grid array, or PGA, shown
upside down; the pins will go through holes in a printed-circuit board). People
often call the package a chip, but, as you can see in Figure 1.1(b), the silicon chip
itself (more properly called a die ) is mounted in the cavity under the sealed lid.
A PGA package is usually made from a ceramic material, but plastic packages
are also common.
FIGURE 1.1 An integrated
circuit (IC). (a) A pin-grid
array (PGA) package. (b) The
silicon die or chip is under
the package lid.
The physical size of a silicon die varies from a few millimeters on a side to over
1 inch on a side, but instead we often measure the size of an IC by the number of
logic gates or the number of transistors that the IC contains. As a unit of measure
a gate equivalent corresponds to a two-input NAND gate (a circuit that performs
the logic function, F = A " B ). Often we just use the term gates instead of gate
equivalents when we are measuring chip sizenot to be confused with the gate
terminal of a transistor. For example, a 100 k-gate IC contains the equivalent of
100,000 two-input NAND gates.
The semiconductor industry has evolved from the first ICs of the early 1970s and
matured rapidly since then. Early small-scale integration ( SSI ) ICs contained a
few (1 to 10) logic gatesNAND gates, NOR gates, and so onamounting to a few
tens of transistors. The era of medium-scale integration ( MSI ) increased the
range of integrated logic available to counters and similar, larger scale, logic
functions. The era of large-scale integration ( LSI ) packed even larger logic
functions, such as the first microprocessors, into a single chip. The era of very
large-scale integration ( VLSI ) now offers 64-bit microprocessors, complete with
cache memory and floating-point arithmetic unitswell over a million transistors
on a single piece of silicon. As CMOS process technology improves, transistors
continue to get smaller and ICs hold more and more transistors. Some people
(especially in Japan) use the term ultralarge scale integration ( ULSI ), but most
people stop at the term VLSI; otherwise we have to start inventing new words.
The earliest ICs used bipolar technology and the majority of logic ICs used either
transistortransistor logic ( TTL ) or emitter-coupled logic (ECL). Although
invented before the bipolar transistor, the metal-oxide-silicon ( MOS ) transistor
was initially difficult to manufacture because of problems with the oxide
interface. As these problems were gradually solved, metal-gate n -channel MOS (
nMOS or NMOS ) technology developed in the 1970s. At that time MOS
technology required fewer masking steps, was denser, and consumed less power
than equivalent bipolar ICs. This meant that, for a given performance, an MOS
IC was cheaper than a bipolar IC and led to investment and growth of the MOS
IC market.
By the early 1980s the aluminum gates of the transistors were replaced by
polysilicon gates, but the name MOS remained. The introduction of polysilicon
as a gate material was a major improvement in CMOS technology, making it
easier to make two types of transistors, n -channel MOS and p -channel MOS
transistors, on the same ICa complementary MOS ( CMOS , never cMOS)
technology. The principal advantage of CMOS over NMOS is lower power
consumption. Another advantage of a polysilicon gate was a simplification of the
fabrication process, allowing devices to be scaled down in size.
There are four CMOS transistors in a two-input NAND gate (and a two-input
NOR gate too), so to convert between gates and transistors, you multiply the
number of gates by 4 to obtain the number of transistors. We can also measure an
IC by the smallest feature size (roughly half the length of the smallest transistor)
imprinted on the IC. Transistor dimensions are measured in microns (a micron, 1
m m, is a millionth of a meter). Thus we talk about a 0.5 m m IC or say an IC is
built in (or with) a 0.5 m m process, meaning that the smallest transistors are 0.5
m m in length. We give a special label, l or lambda , to this smallest feature size.
Since lambda is equal to half of the smallest transistor length, l ª 0.25 m m in a
0.5 m m process. Many of the drawings in this book use a scale marked with
lambda for the same reason we place a scale on a map.
A modern submicron CMOS process is now just as complicated as a submicron
bipolar or BiCMOS (a combination of bipolar and CMOS) process. However,
CMOS ICs have established a dominant position, are manufactured in much
greater volume than any other technology, and therefore, because of the economy
of scale, the cost of CMOS ICs is less than a bipolar or BiCMOS IC for the same
function. Bipolar and BiCMOS ICs are still used for special needs. For example,
bipolar technology is generally capable of handling higher voltages than CMOS.
This makes bipolar and BiCMOS ICs useful in power electronics, cars, telephone
circuits, and so on.
Some digital logic ICs and their analog counterparts (analog/digital converters,
for example) are standard parts , or standard ICs. You can select standard ICs
from catalogs and data books and buy them from distributors. Systems
manufacturers and designers can use the same standard part in a variety of
different microelectronic systems (systems that use microelectronics or ICs).
With the advent of VLSI in the 1980s engineers began to realize the advantages
of designing an IC that was customized or tailored to a particular system or
application rather than using standard ICs alone. Microelectronic system design
then becomes a matter of defining the functions that you can implement using
standard ICs and then implementing the remaining logic functions (sometimes
called glue logic ) with one or more custom ICs . As VLSI became possible you
could build a system from a smaller number of components by combining many
standard ICs into a few custom ICs. Building a microelectronic system with
fewer ICs allows you to reduce cost and improve reliability.
Of course, there are many situations in which it is not appropriate to use a custom
IC for each and every part of an microelectronic system. If you need a large
amount of memory, for example, it is still best to use standard memory ICs,
either dynamic random-access memory ( DRAM or dRAM), or static RAM (
SRAM or sRAM), in conjunction with custom ICs.
One of the first conferences to be devoted to this rapidly emerging segment of the
IC industry was the IEEE Custom Integrated Circuits Conference (CICC), and
the proceedings of this annual conference form a useful reference to the
development of custom ICs. As different types of custom ICs began to evolve for
different types of applications, these new ICs gave rise to a new term:
application-specific IC, or ASIC. Now we have the IEEE International ASIC
Conference , which tracks advances in ASICs separately from other types of
custom ICs. Although the exact definition of an ASIC is difficult, we shall look at
some examples to help clarify what people in the IC industry understand by the
term.
Examples of ICs that are not ASICs include standard parts such as: memory chips
sold as a commodity itemROMs, DRAM, and SRAM; microprocessors; TTL or
TTL-equivalent ICs at SSI, MSI, and LSI levels.
Examples of ICs that are ASICs include: a chip for a toy bear that talks; a chip
for a satellite; a chip designed to handle the interface between memory and a
microprocessor for a workstation CPU; and a chip containing a microprocessor as
a cell together with other logic.
As a general rule, if you can find it in a data book, then it is probably not an
ASIC, but there are some exceptions. For example, two ICs that might or might
not be considered ASICs are a controller chip for a PC and a chip for a modem.
Both of these examples are specific to an application (shades of an ASIC) but are
sold to many different system vendors (shades of a standard part). ASICs such as
these are sometimes called application-specific standard products ( ASSPs ).
Trying to decide which members of the huge IC family are application-specific is
trickyafter all, every IC has an application. For example, people do not usually
consider an application-specific microprocessor to be an ASIC. I shall describe
how to design an ASIC that may include large cells such as microprocessors, but
I shall not describe the design of the microprocessors themselves. Defining an
ASIC by looking at the application can be confusing, so we shall look at a
different way to categorize the IC family. The easiest way to recognize people is
by their faces and physical characteristics: tall, short, thin. The easiest
characteristics of ASICs to understand are physical ones too, and we shall look at
these next. It is important to understand these differences because they affect
such factors as the price of an ASIC and the way you design an ASIC.
1.1 Types of ASICs
ICs are made on a thin (a few hundred microns thick), circular silicon wafer ,
with each wafer holding hundreds of die (sometimes people use dies or dice for
the plural of die). The transistors and wiring are made from many layers (usually
between 10 and 15 distinct layers) built on top of one another. Each successive
mask layer has a pattern that is defined using a mask similar to a glass
photographic slide. The first half-dozen or so layers define the transistors. The
last half-dozen or so layers define the metal wires between the transistors (the
interconnect ).
A full-custom IC includes some (possibly all) logic cells that are customized and
all mask layers that are customized. A microprocessor is an example of a
full-custom ICdesigners spend many hours squeezing the most out of every last
square micron of microprocessor chip space by hand. Customizing all of the IC
features in this way allows designers to include analog circuits, optimized
memory cells, or mechanical structures on an IC, for example. Full-custom ICs
are the most expensive to manufacture and to design. The manufacturing lead
time (the time it takes just to make an ICnot including design time) is typically
eight weeks for a full-custom IC. These specialized full-custom ICs are often
intended for a specific application, so we might call some of them full-custom
ASICs.
We shall discuss full-custom ASICs briefly next, but the members of the IC
family that we are more interested in are semicustom ASICs , for which all of the
logic cells are predesigned and some (possibly all) of the mask layers are
customized. Using predesigned cells from a cell library makes our lives as
designers much, much easier. There are two types of semicustom ASICs that we
shall cover: standard-cellbased ASICs and gate-arraybased ASICs. Following
this we shall describe the programmable ASICs , for which all of the logic cells
are predesigned and none of the mask layers are customized. There are two types
of programmable ASICs: the programmable logic device and, the newest member
of the ASIC family, the field-programmable gate array.
1.1.1 Full-Custom ASICs
In a full-custom ASIC an engineer designs some or all of the logic cells, circuits,
or layout specifically for one ASIC. This means the designer abandons the
approach of using pretested and precharacterized cells for all or part of that
design. It makes sense to take this approach only if there are no suitable existing
cell libraries available that can be used for the entire design. This might be
because existing cell libraries are not fast enough, or the logic cells are not small
enough or consume too much power. You may need to use full-custom design if
the ASIC technology is new or so specialized that there are no existing cell
libraries or because the ASIC is so specialized that some circuits must be custom
designed. Fewer and fewer full-custom ICs are being designed because of the
problems with these special parts of the ASIC. There is one growing member of
this family, though, the mixed analog/digital ASIC, which we shall discuss next.
Bipolar technology has historically been used for precision analog functions.
There are some fundamental reasons for this. In all integrated circuits the
matching of component characteristics between chips is very poor, while the
matching of characteristics between components on the same chip is excellent.
Suppose we have transistors T1, T2, and T3 on an analog/digital ASIC. The three
transistors are all the same size and are constructed in an identical fashion.
Transistors T1 and T2 are located adjacent to each other and have the same
orientation. Transistor T3 is the same size as T1 and T2 but is located on the
other side of the chip from T1 and T2 and has a different orientation. ICs are
made in batches called wafer lots. A wafer lot is a group of silicon wafers that are
all processed together. Usually there are between 5 and 30 wafers in a lot. Each
wafer can contain tens or hundreds of chips depending on the size of the IC and
the wafer.
If we were to make measurements of the characteristics of transistors T1, T2, and
T3 we would find the following:
● Transistors T1 will have virtually identical characteristics to T2 on the
same IC. We say that the transistors match well or the tracking between
devices is excellent.
● Transistor T3 will match transistors T1 and T2 on the same IC very well,
but not as closely as T1 matches T2 on the same IC.
● Transistor T1, T2, and T3 will match fairly well with transistors T1, T2,
and T3 on a different IC on the same wafer. The matching will depend on
how far apart the two ICs are on the wafer.
● Transistors on ICs from different wafers in the same wafer lot will not
match very well.
● Transistors on ICs from different wafer lots will match very poorly.
For many analog designs the close matching of transistors is crucial to circuit
operation. For these circuit designs pairs of transistors are used, located adjacent
to each other. Device physics dictates that a pair of bipolar transistors will always
match more precisely than CMOS transistors of a comparable size. Bipolar
technology has historically been more widely used for full-custom analog design
because of its improved precision. Despite its poorer analog properties, the use of
CMOS technology for analog functions is increasing. There are two reasons for
this. The first reason is that CMOS is now by far the most widely available IC
technology. Many more CMOS ASICs and CMOS standard products are now
being manufactured than bipolar ICs. The second reason is that increased levels
of integration require mixing analog and digital functions on the same IC: this
has forced designers to find ways to use CMOS technology to implement analog
functions. Circuit designers, using clever new techniques, have been very
successful in finding new ways to design analog CMOS circuits that can
approach the accuracy of bipolar analog designs.
1.1.2 Standard-CellBased ASICs
A cell-based ASIC (cell-based IC, or CBIC a common term in Japan,
pronounced sea-bick) uses predesigned logic cells (AND gates, OR gates,
multiplexers, and flip-flops, for example) known as standard cells . We could
apply the term CBIC to any IC that uses cells, but it is generally accepted that a
cell-based ASIC or CBIC means a standard-cellbased ASIC.
The standard-cell areas (also called flexible blocks) in a CBIC are built of rows
of standard cellslike a wall built of bricks. The standard-cell areas may be used
in combination with larger predesigned cells, perhaps microcontrollers or even
microprocessors, known as megacells . Megacells are also called megafunctions,
full-custom blocks, system-level macros (SLMs), fixed blocks, cores, or
Functional Standard Blocks (FSBs).
The ASIC designer defines only the placement of the standard cells and the
interconnect in a CBIC. However, the standard cells can be placed anywhere on
the silicon; this means that all the mask layers of a CBIC are customized and are
unique to a particular customer. The advantage of CBICs is that designers save
time, money, and reduce risk by using a predesigned, pretested, and
precharacterized standard-cell library . In addition each standard cell can be
optimized individually. During the design of the cell library each and every
transistor in every standard cell can be chosen to maximize speed or minimize
area, for example. The disadvantages are the time or expense of designing or
buying the standard-cell library and the time needed to fabricate all layers of the
ASIC for each new design.
Figure 1.2 shows a CBIC (looking down on the die shown in Figure 1.1b, for
example). The important features of this type of ASIC are as follows:
● All mask layers are customizedtransistors and interconnect.
● Custom blocks can be embedded.
● Manufacturing lead time is about eight weeks.
FIGURE 1.2 A cell-based ASIC
(CBIC) die with a single
standard-cell area (a flexible
block) together with four fixed
blocks. The flexible block
contains rows of standard cells.
This is what you might see
through a low-powered
microscope looking down on the
die of Figure 1.1(b). The small
squares around the edge of the die
are bonding pads that are
connected to the pins of the ASIC
package.
Each standard cell in the library is constructed using full-custom design methods,
but you can use these predesigned and precharacterized circuits without having to
do any full-custom design yourself. This design style gives you the same
performance and flexibility advantages of a full-custom ASIC but reduces design
time and reduces risk.
Standard cells are designed to fit together like bricks in a wall. Figure 1.3 shows
an example of a simple standard cell (it is simple in the sense it is not maximized
for densitybut ideal for showing you its internal construction). Power and ground
buses (VDD and GND or VSS) run horizontally on metal lines inside the cells.
FIGURE 1.3 Looking down on the layout of a standard cell. This cell would be
approximately 25 microns wide on an ASIC with l (lambda) = 0.25 microns (a
micron is 10 6 m). Standard cells are stacked like bricks in a wall; the abutment
box (AB) defines the edges of the brick. The difference between the bounding
box (BB) and the AB is the area of overlap between the bricks. Power supplies
(labeled VDD and GND) run horizontally inside a standard cell on a metal layer
that lies above the transistor layers. Each different shaded and labeled pattern
represents a different layer. This standard cell has center connectors (the three
squares, labeled A1, B1, and Z) that allow the cell to connect to others. The
layout was drawn using ROSE, a symbolic layout editor developed by Rockwell
and Compass, and then imported into Tanner Researchs L-Edit.
Standard-cell design allows the automation of the process of assembling an
ASIC. Groups of standard cells fit horizontally together to form rows. The rows
stack vertically to form flexible rectangular blocks (which you can reshape
during design). You may then connect a flexible block built from several rows of
standard cells to other standard-cell blocks or other full-custom logic blocks. For
example, you might want to include a custom interface to a standard, predesigned
microcontroller together with some memory. The microcontroller block may be a
fixed-size megacell, you might generate the memory using a memory compiler,
and the custom logic and memory controller will be built from flexible
standard-cell blocks, shaped to fit in the empty spaces on the chip.
Both cell-based and gate-array ASICs use predefined cells, but there is a
differencewe can change the transistor sizes in a standard cell to optimize speed
and performance, but the device sizes in a gate array are fixed. This results in a
trade-off in performance and area in a gate array at the silicon level. The trade-off
between area and performance is made at the library level for a standard-cell
ASIC.
Modern CMOS ASICs use two, three, or more levels (or layers) of metal for
interconnect. This allows wires to cross over different layers in the same way that
we use copper traces on different layers on a printed-circuit board. In a two-level
metal CMOS technology, connections to the standard-cell inputs and outputs are
usually made using the second level of metal ( metal2 , the upper level of metal)
at the tops and bottoms of the cells. In a three-level metal technology,
connections may be internal to the logic cell (as they are in Figure 1.3). This
allows for more sophisticated routing programs to take advantage of the extra
metal layer to route interconnect over the top of the logic cells. We shall cover
the details of routing ASICs in Chapter 17.
A connection that needs to cross over a row of standard cells uses a feedthrough.
The term feedthrough can refer either to the piece of metal that is used to pass a
signal through a cell or to a space in a cell waiting to be used as a feedthrough
very confusing. Figure 1.4 shows two feedthroughs: one in cell A.14 and one in
cell A.23.
In both two-level and three-level metal technology, the power buses (VDD and
GND) inside the standard cells normally use the lowest (closest to the transistors)
layer of metal ( metal1 ). The width of each row of standard cells is adjusted so
that they may be aligned using spacer cells . The power buses, or rails, are then
connected to additional vertical power rails using row-end cells at the aligned
ends of each standard-cell block. If the rows of standard cells are long, then
vertical power rails can also be run in metal2 through the cell rows using special
power cells that just connect to VDD and GND. Usually the designer manually
controls the number and width of the vertical power rails connected to the
standard-cell blocks during physical design. A diagram of the power distribution
scheme for a CBIC is shown in Figure 1.4.
FIGURE 1.4 Routing the CBIC (cell-based IC) shown in Figure 1.2. The use of
regularly shaped standard cells, such as the one in Figure 1.3, from a library
allows ASICs like this to be designed automatically. This ASIC uses two
separate layers of metal interconnect (metal1 and metal2) running at right angles
to each other (like traces on a printed-circuit board). Interconnections between
logic cells uses spaces (called channels) between the rows of cells. ASICs may
have three (or more) layers of metal allowing the cell rows to touch with the
interconnect running over the top of the cells.
All the mask layers of a CBIC are customized. This allows megacells (SRAM, a
SCSI controller, or an MPEG decoder, for example) to be placed on the same IC
with standard cells. Megacells are usually supplied by an ASIC or library
company complete with behavioral models and some way to test them (a test
strategy). ASIC library companies also supply compilers to generate flexible
DRAM, SRAM, and ROM blocks. Since all mask layers on a standard-cell
design are customized, memory design is more efficient and denser than for gate
arrays.
For logic that operates on multiple signals across a data busa datapath ( DP )the
use of standard cells may not be the most efficient ASIC design style. Some
ASIC library companies provide a datapath compiler that automatically generates
datapath logic . A datapath library typically contains cells such as adders,
subtracters, multipliers, and simple arithmetic and logical units ( ALUs ). The
connectors of datapath library cells are pitch-matched to each other so that they
fit together. Connecting datapath cells to form a datapath usually, but not always,
results in faster and denser layout than using standard cells or a gate array.
Standard-cell and gate-array libraries may contain hundreds of different logic
cells, including combinational functions (NAND, NOR, AND, OR gates) with
multiple inputs, as well as latches and flip-flops with different combinations of
reset, preset and clocking options. The ASIC library company provides designers
with a data book in paper or electronic form with all of the functional
descriptions and timing information for each library element.
1.1.3 Gate-ArrayBased ASICs
In a gate array (sometimes abbreviated to GA) or gate-arraybased ASIC the
transistors are predefined on the silicon wafer. The predefined pattern of
transistors on a gate array is the base array , and the smallest element that is
replicated to make the base array (like an M. C. Escher drawing, or tiles on a
floor) is the base cell (sometimes called a primitive cell ). Only the top few layers
of metal, which define the interconnect between transistors, are defined by the
designer using custom masks. To distinguish this type of gate array from other
types of gate array, it is often called a masked gate array ( MGA ). The designer
chooses from a gate-array library of predesigned and precharacterized logic cells.
The logic cells in a gate-array library are often called macros . The reason for this
is that the base-cell layout is the same for each logic cell, and only the
interconnect (inside cells and between cells) is customized, so that there is a
similarity between gate-array macros and a software macro. Inside IBM,
gate-array macros are known as books (so that books are part of a library), but
unfortunately this descriptive term is not very widely used outside IBM.
We can complete the diffusion steps that form the transistors and then stockpile
wafers (sometimes we call a gate array a prediffused array for this reason). Since
only the metal interconnections are unique to an MGA, we can use the stockpiled
wafers for different customers as needed. Using wafers prefabricated up to the
metallization steps reduces the time needed to make an MGA, the turnaround
time , to a few days or at most a couple of weeks. The costs for all the initial
fabrication steps for an MGA are shared for each customer and this reduces the
cost of an MGA compared to a full-custom or standard-cell ASIC design.
There are the following different types of MGA or gate-arraybased ASICs:
● Channeled gate arrays.
● Channelless gate arrays.
●
Structured gate arrays.
The hyphenation of these terms when they are used as adjectives explains their
construction. For example, in the term channeled gate-array architecture, the
gate array is channeled , as will be explained. There are two common ways of
arranging (or arraying) the transistors on a MGA: in a channeled gate array we
leave space between the rows of transistors for wiring; the routing on a
channelless gate array uses rows of unused transistors. The channeled gate array
was the first to be developed, but the channelless gate-array architecture is now
more widely used. A structured (or embedded) gate array can be either channeled
or channelless but it includes (or embeds) a custom block.
1.1.4 Channeled Gate Array
Figure 1.5 shows a channeled gate array . The important features of this type of
MGA are:
● Only the interconnect is customized.
● The interconnect uses predefined spaces between rows of base cells.
● Manufacturing lead time is between two days and two weeks.
FIGURE 1.5 A channeled gate-array die.
The spaces between rows of the base cells
are set aside for interconnect.
A channeled gate array is similar to a CBICboth use rows of cells separated by
channels used for interconnect. One difference is that the space for interconnect
between rows of cells are fixed in height in a channeled gate array, whereas the
space between rows of cells may be adjusted in a CBIC.
1.1.5 Channelless Gate Array
Figure 1.6 shows a channelless gate array (also known as a channel-free gate
array , sea-of-gates array , or SOG array). The important features of this type of
MGA are as follows:
● Only some (the top few) mask layers are customizedthe interconnect.
● Manufacturing lead time is between two days and two weeks.
FIGURE 1.6 A channelless gate-array or
sea-of-gates (SOG) array die. The core
area of the die is completely filled with an
array of base cells (the base array).
The key difference between a channelless gate array and channeled gate array is
that there are no predefined areas set aside for routing between cells on a
channelless gate array. Instead we route over the top of the gate-array devices.
We can do this because we customize the contact layer that defines the
connections between metal1, the first layer of metal, and the transistors. When
we use an area of transistors for routing in a channelless array, we do not make
any contacts to the devices lying underneath; we simply leave the transistors
unused.
The logic densitythe amount of logic that can be implemented in a given silicon
areais higher for channelless gate arrays than for channeled gate arrays. This is
usually attributed to the difference in structure between the two types of array. In
fact, the difference occurs because the contact mask is customized in a
channelless gate array, but is not usually customized in a channeled gate array.
This leads to denser cells in the channelless architectures. Customizing the
contact layer in a channelless gate array allows us to increase the density of
gate-array cells because we can route over the top of unused contact sites.
1.1.6 Structured Gate Array
An embedded gate array or structured gate array (also known as masterslice or
masterimage ) combines some of the features of CBICs and MGAs. One of the
disadvantages of the MGA is the fixed gate-array base cell. This makes the
implementation of memory, for example, difficult and inefficient. In an
embedded gate array we set aside some of the IC area and dedicate it to a specific
function. This embedded area either can contain a different base cell that is more
suitable for building memory cells, or it can contain a complete circuit block,
such as a microcontroller.
Figure 1.7 shows an embedded gate array. The important features of this type of
MGA are the following:
● Only the interconnect is customized.
● Custom blocks (the same for each design) can be embedded.
● Manufacturing lead time is between two days and two weeks.
FIGURE 1.7 A structured or
embedded gate-array die showing
an embedded block in the upper
left corner (a static random-access
memory, for example). The rest of
the die is filled with an array of
base cells.
An embedded gate array gives the improved area efficiency and increased
performance of a CBIC but with the lower cost and faster turnaround of an MGA.
One disadvantage of an embedded gate array is that the embedded function is
fixed. For example, if an embedded gate array contains an area set aside for a 32
k-bit memory, but we only need a 16 k-bit memory, then we may have to waste
half of the embedded memory function. However, this may still be more efficient
and cheaper than implementing a 32 k-bit memory using macros on a SOG array.
ASIC vendors may offer several embedded gate array structures containing
different memory types and sizes as well as a variety of embedded functions.
ASIC companies wishing to offer a wide range of embedded functions must
ensure that enough customers use each different embedded gate array to give the
cost advantages over a custom gate array or CBIC (the Sun Microsystems
SPARCstation 1 described in Section 1.3 made use of LSI Logic embedded gate
arraysand the 10K and 100K series of embedded gate arrays were two of LSI
Logics most successful products).
1.1.7 Programmable Logic Devices
Programmable logic devices ( PLDs ) are standard ICs that are available in
standard configurations from a catalog of parts and are sold in very high volume
to many different customers. However, PLDs may be configured or programmed
to create a part customized to a specific application, and so they also belong to
the family of ASICs. PLDs use different technologies to allow programming of
the device. Figure 1.8 shows a PLD and the following important features that all
PLDs have in common:
● No customized mask layers or logic cells
● Fast design turnaround
● A single large block of programmable interconnect
● A matrix of logic macrocells that usually consist of programmable array
logic followed by a flip-flop or latch
FIGURE 1.8 A programmable
logic device (PLD) die. The
macrocells typically consist of
programmable array logic
followed by a flip-flop or latch.
The macrocells are connected
using a large programmable
interconnect block.
The simplest type of programmable IC is a read-only memory ( ROM ). The most
common types of ROM use a metal fuse that can be blown permanently (a
programmable ROM or PROM ). An electrically programmable ROM , or
EPROM , uses programmable MOS transistors whose characteristics are altered
by applying a high voltage. You can erase an EPROM either by using another
high voltage (an electrically erasable PROM , or EEPROM ) or by exposing the
device to ultraviolet light ( UV-erasable PROM , or UVPROM ).
There is another type of ROM that can be placed on any ASICa
mask-programmable ROM (mask-programmed ROM or masked ROM). A
masked ROM is a regular array of transistors permanently programmed using
custom mask patterns. An embedded masked ROM is thus a large, specialized,
logic cell.
The same programmable technologies used to make ROMs can be applied to
more flexible logic structures. By using the programmable devices in a large
array of AND gates and an array of OR gates, we create a family of flexible and
programmable logic devices called logic arrays . The company Monolithic
Memories (bought by AMD) was the first to produce Programmable Array Logic
(PAL ® , a registered trademark of AMD) devices that you can use, for example,
as transition decoders for state machines. A PAL can also include registers
(flip-flops) to store the current state information so that you can use a PAL to
make a complete state machine.
Just as we have a mask-programmable ROM, we could place a logic array as a
cell on a custom ASIC. This type of logic array is called a programmable logic
array (PLA). There is a difference between a PAL and a PLA: a PLA has a
programmable AND logic array, or AND plane , followed by a programmable
OR logic array, or OR plane ; a PAL has a programmable AND plane and, in
contrast to a PLA, a fixed OR plane.
Depending on how the PLD is programmed, we can have an erasable PLD
(EPLD), or mask-programmed PLD (sometimes called a masked PLD but usually
just PLD). The first PALs, PLAs, and PLDs were based on bipolar technology
and used programmable fuses or links. CMOS PLDs usually employ
floating-gate transistors (see Section 4.3, EPROM and EEPROM Technology).
1.1.8 Field-Programmable Gate Arrays
A step above the PLD in complexity is the field-programmable gate array (
FPGA ). There is very little difference between an FPGA and a PLDan FPGA is
usually just larger and more complex than a PLD. In fact, some companies that
manufacture programmable ASICs call their products FPGAs and some call them
complex PLDs . FPGAs are the newest member of the ASIC family and are
rapidly growing in importance, replacing TTL in microelectronic systems. Even
though an FPGA is a type of gate array, we do not consider the term gate-array
based ASICs to include FPGAs. This may change as FPGAs and MGAs start to
look more alike.
Figure 1.9 illustrates the essential characteristics of an FPGA:
● None of the mask layers are customized.
● A method for programming the basic logic cells and the interconnect.
● The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops).
● A matrix of programmable interconnect surrounds the basic logic cells.
● Programmable I/O cells surround the core.
● Design turnaround is a few hours.
We shall examine these features in detail in Chapters 48.
FIGURE 1.9 A field-programmable
gate array (FPGA) die. All FPGAs
contain a regular structure of
programmable basic logic cells
surrounded by programmable
interconnect. The exact type, size,
and number of the programmable
basic logic cells varies
tremendously.
1.2 Design Flow
Figure 1.10 shows the sequence of steps to design an ASIC; we call this a design
flow . The steps are listed below (numbered to correspond to the labels in
Figure 1.10) with a brief description of the function of each step.
FIGURE 1.10 ASIC design flow.
1. Design entry. Enter the design into an ASIC design system, either using a
hardware description language ( HDL ) or schematic entry .
2. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis
tool to produce a netlist a description of the logic cells and their
connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
1.1.8 Field-Programmable Gate Arrays
A step above the PLD in complexity is the field-programmable gate array (
FPGA ). There is very little difference between an FPGA and a PLDan FPGA is
usually just larger and more complex than a PLD. In fact, some companies that
manufacture programmable ASICs call their products FPGAs and some call them
complex PLDs . FPGAs are the newest member of the ASIC family and are
rapidly growing in importance, replacing TTL in microelectronic systems. Even
though an FPGA is a type of gate array, we do not consider the term gate-array
based ASICs to include FPGAs. This may change as FPGAs and MGAs start to
look more alike.
Figure 1.9 illustrates the essential characteristics of an FPGA:
● None of the mask layers are customized.
● A method for programming the basic logic cells and the interconnect.
● The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops).
● A matrix of programmable interconnect surrounds the basic logic cells.
● Programmable I/O cells surround the core.
● Design turnaround is a few hours.
We shall examine these features in detail in Chapters 48.
FIGURE 1.9 A field-programmable
gate array (FPGA) die. All FPGAs
contain a regular structure of
programmable basic logic cells
surrounded by programmable
interconnect. The exact type, size,
and number of the programmable
basic logic cells varies
tremendously.
1.3 Case Study
Sun Microsystems released the SPARCstation 1 in April 1989. It is now an old
design but a very important example because it was one of the first workstations
to make extensive use of ASICs to achieve the following:
● Better performance at lower cost
● Compact size, reduced power, and quiet operation
● Reduced number of parts, easier assembly, and improved reliability
The SPARCstation 1 contains about 50 ICs on the system motherboardexcluding
the DRAM used for the system memory (standard parts). The SPARCstation 1
designers partitioned the system into the nine ASlCs shown in Table 1.1 and
wrote specifications for each ASICthis took about three months 1 . LSI Logic
and Fujitsu designed the SPARC integer unit (IU) and floating-point unit ( FPU )
to these specifications. The clock ASIC is a fairly straightforward design and, of
the six remaining ASICs, the video controller/data buffer, the RAM controller,
and the direct memory access ( DMA ) controller are defined by the 32-bit
system bus ( SBus ) and the other ASICs that they connect to. The rest of the
system is partitioned into three more ASICs: the cache controller ,
memory-management unit (MMU), and the data buffer. These three ASICs, with
the IU and FPU, have the most critical timing paths and determine the system
partitioning. The design of ASICs 38 in Table 1.1 took five Sun engineers six
months after the specifications were complete. During the design process, the
Sun engineers simulated the entire SPARCstation 1including execution of the
Sun operating system (SunOS).
TABLE 1.1 The ASICs in the Sun Microsystems SPARCstation 1.
SPARCstation 1 ASIC
Gates (k-gates)
1 SPARC integer unit (IU)
20
2 SPARC floating-point unit (FPU)
50
3 Cache controller
9
4 Memory-management unit (MMU)
5
5 Data buffer
3
6 Direct memory access (DMA) controller
9
7 Video controller/data buffer
4
8 RAM controller
1
9 Clock generator
1
Table 1.2 shows the software tools used to design the SPARCstation 1, many of
which are now obsolete. The important point to notice, though, is that there is a
lot more to microelectronic system design than designing the ASICsless than
one-third of the tools listed in Table 1.2 were ASIC design tools.
TABLE 1.2 The CAD tools used in the design of the Sun Microsystems
SPARCstation 1.
Tool 2
Design level
Function
ASIC design
ASIC physical design
LSI Logic
Internal tools and UC Berkeley
ASIC logic synthesis
tools
ASIC simulation
LSI Logic
Board design
Schematic capture
Valid Logic
PCB layout
Valid Logic Allegro
Quad Design Motive and
Timing verification
internal tools
Mechanical design Case and enclosure
Autocad
Thermal analysis
Pacific Numerix
Structural analysis
Cosmos
Management
Scheduling
Suntrac
Documentation
Interleaf and FrameMaker
The SPARCstation 1 cost about $9000 in 1989 or, since it has an execution rate
of approximately 12 million instructions per second (MIPS), $750/MIPS. Using
ASIC technology reduces the motherboard to about the size of a piece of paper
8.5 inches by 11 incheswith a power consumption of about 12 W. The
SPARCstation 1 pizza box is 16 inches across and 3 inches highsmaller than a
typical IBM-compatible personal computer in 1989. This speed, power, and size
performance is (there are still SPARCstation 1s in use) made possible by using
ASICs. We shall return to the SPARCstation 1, to look more closely at the
partitioning step, in Section 15.3, System Partitioning.
1. Some information in Section 1.3 and Section 15.3 is from the
SPARCstation 10 Architecture GuideMay 1992, p. 2 and pp. 2728 and from two
publicity brochures (known as sparkle sheets). The first is Concept to System:
How Sun Microsystems Created SPARCstation 1 Using LSI Logic's ASIC
System Technology, A. Bechtolsheim, T. Westberg, M. Insley, and J. Ludemann
of Sun Microsystems; J-H. Huang and D. Boyle of LSI Logic. This is an LSI
Logic publication. The second paper is SPARCstation 1: Beyond the 3M
Horizon, A. Bechtolsheim and E. Frank, a Sun Microsystems publication. I did
not include these as references since they are impossible to obtain now, but I
would like to give credit to Andy Bechtolsheim and the Sun Microsystems and
LSI Logic engineers.
2. Names are trademarks of their respective companies.
1.4 Economics of ASICs
In this section we shall discuss the economics of using ASICs in a product and
compare the most popular types of ASICs: an FPGA, an MGA, and a CBIC. To
make an economic comparison between these alternatives, we consider the ASIC
itself as a product and examine the components of product cost: fixed costs and
variable costs. Making cost comparisons is dangerouscosts change rapidly and
the semiconductor industry is notorious for keeping its costs, prices, and pricing
strategy closely guarded secrets. The figures in the following sections are
approximate and used to illustrate the different components of cost.
1.4.1 Comparison Between ASIC
Technologies
The most obvious economic factor in making a choice between the different
ASIC types is the part cost . Part costs vary enormouslyyou can pay anywhere
from a few dollars to several hundreds of dollars for an ASIC. In general,
however, FPGAs are more expensive per gate than MGAs, which are, in turn,
more expensive than CBICs. For example, a 0.5 m m, 20 k-gate array might cost
0.010.02 cents/gate (for more than 10,000 parts) or $2$4 per part, but an
equivalent FPGA might be $20. The price per gate for an FPGA to implement the
same function is typically 25 times the cost of an MGA or CBIC.
Given that an FPGA is more expensive than an MGA, which is more expensive
than a CBIC, when and why does it make sense to choose a more expensive part?
Is the increased flexibility of an FPGA worth the extra cost per part? Given that
an MGA or CBIC is specially tailored for each customer, there are extra hidden
costs associated with this step that we should consider. To make a true
comparison between the different ASIC technologies, we shall quantify some of
these costs.
1.4.2 Product Cost
The total cost of any product can be separated into fixed costs and variable costs :
total product cost = fixed product cost + variable product cost ¥ products
sold
Fixed costs are independent of sales volume the number of products sold.
(1.1)
However, the fixed costs amortized per product sold (fixed costs divided by
products sold) decrease as sales volume increases. Variable costs include the cost
of the parts used in the product, assembly costs, and other manufacturing costs.
Let us look more closely at the parts in a product. If we want to buy ASICs to
assemble our product, the total part cost is
total part cost = fixed part cost + variable cost per part ¥ volume of parts. (1.2)
Our fixed cost when we use an FPGA is lowwe just have to buy the software and
any programming equipment. The fixed part costs for an MGA or CBIC are
higher and include the costs of the masks, simulation, and test program
development. We shall discuss these extra costs in more detail in Sections 1.4.3
and 1.4.4. Figure 1.11 shows a break-even graph that compares the total part cost
for an FPGA, MGA, and a CBIC with the following assumptions:
● FPGA fixed cost is $21,800, part cost is $39.
● MGA fixed cost is $86,000, part cost is $10.
● CBIC fixed cost is $146,000, part cost is $8.
At low volumes, the MGA and the CBIC are more expensive because of their
higher fixed costs. The total part costs of two alternative types of ASIC are equal
at the break-even volume . In Figure 1.11 the break-even volume for the FPGA
and the MGA is about 2000 parts. The break-even volume between the FPGA
and the CBIC is about 4000 parts. The break-even volume between the MGA and
the CBIC is higherat about 20,000 parts.
FIGURE 1.11 A break-even analysis for an FPGA, a masked gate array (MGA)
and a custom cell-based ASIC (CBIC). The break-even volume between two
technologies is the point at which the total cost of parts are equal. These
numbers are very approximate.
We shall describe how to calculate the fixed part costs next. Following that we
shall discuss how we came up with cost per part of $39, $10, and $8 for the
FPGA, MGA, and CBIC.
1.4.3 ASIC Fixed Costs
Figure 1.12 shows a spreadsheet, Fixed Costs, that calculates the fixed part costs
associated with ASIC design.
FIGURE 1.12 A spreadsheet, Fixed Costs, for a field-programmable gate array
(FPGA), a masked gate array (MGA), and a cell-based ASIC (CBIC). These
costs can vary wildly.
The training cost includes the cost of the time to learn any new electronic design
automation ( EDA ) system. For example, a new FPGA design system might
require a few days to learn; a new gate-array or cell-based design system might
require taking a course. Figure 1.12 assumes that the cost of an engineer
(including overhead, benefits, infrastructure, and so on) is between $100,000 and
$200,000 per year or $2000 to $4000 per week (in the United States in 1990s
dollars).
Next we consider the hardware and software cost for ASIC design. Figure 1.12
shows some typical figures, but you can spend anywhere from $1000 to
$1 million (and more) on ASIC design software and the necessary infrastructure.
We try to measure productivity of an ASIC designer in gates (or transistors) per
day. This is like trying to predict how long it takes to dig a hole, and the number
of gates per day an engineer averages varies wildly. ASIC design productivity
must increase as ASIC sizes increase and will depend on experience, design
tools, and the ASIC complexity. If we are using similar design methods, design
productivity ought to be independent of the type of ASIC, but FPGA design
software is usually available as a complete bundle on a PC. This means that it is
often easier to learn and use than semicustom ASIC design tools.
Every ASIC has to pass a production test to make sure that it works. With
modern test tools the generation of any test circuits on each ASIC that are needed
for production testing can be automatic, but it still involves a cost for design for
test . An FPGA is tested by the manufacturer before it is sold to you and before
you program it. You are still paying for testing an FPGA, but it is a hidden cost
folded into the part cost of the FPGA. You do have to pay for any programming
costs for an FPGA, but we can include these in the hardware and software cost.
The nonrecurring-engineering ( NRE ) charge includes the cost of work done by
the ASIC vendor and the cost of the masks. The production test uses sets of test
inputs called test vectors , often many thousands of them. Most ASIC vendors
require simulation to generate test vectors and test programs for production
testing, and will charge for a test-program development cost . The number of
masks required by an ASIC during fabrication can range from three or four (for a
gate array) to 15 or more (for a CBIC). Total mask costs can range from $5000 to
$50,000 or more. The total NRE charge can range from $10,000 to $300,000 or
more and will vary with volume and the size of the ASIC. If you commit to high
volumes (above 100,000 parts), the vendor may waive the NRE charge. The NRE
charge may also include the costs of software tools, design verification, and
prototype samples.
If your design does not work the first time, you have to complete a further design
pass ( turn or spin ) that requires additional NRE charges. Normally you sign a
contract (sign off a design) with an ASIC vendor that guarantees first-pass
successthis means that if you designed your ASIC according to rules specified
by the vendor, then the vendor guarantees that the silicon will perform according
to the simulation or you get your money back. This is why the difference between
semicustom and full-custom design styles is so importantthe ASIC vendor will
not (and cannot) guarantee your design will work if you use any full-custom
design techniques.
Nowadays it is almost routine to have an ASIC work on the first pass. However,
if your design does fail, it is little consolation to have a second pass for free if
your company goes bankrupt in the meantime. Figure 1.13 shows a profit model
that represents the profit flow during the product lifetime . Using this model, we
can estimate the lost profit due to any delay.
FIGURE 1.13 A profit model. If a product is introduced on time, the total sales
are $60 million (the area of the higher triangle). With a three-month (one fiscal
quarter) delay the sales decline to $25 million. The difference is shown as the
shaded area between the two triangles and amounts to a lost revenue of
$35 million.
Suppose we have the following situation:
● The product lifetime is 18 months (6 fiscal quarters).
● The product sales increase (linearly) at $10 million per quarter
independently of when the product is introduced (we suppose this is
because we can increase production and sales only at a fixed rate).
● The product reaches its peak sales at a point in time that is independent of
when we introduce a product (because of external market factors that we
cannot control).
● The product declines in sales (linearly) to the end of its lifea point in time
that is also independent of when we introduce the product (again due to
external market forces).
The simple profit and revenue model of Figure 1.13 shows us that we would lose
$35 million in sales in this situation due to a 3-month delay. Despite the obvious
problems with such a simple model (how can we introduce the same product
twice to compare the performance?), it is widely used in marketing. In the
electronics industry product lifetimes continue to shrink. In the PC industry it is
not unusual to have a product lifetime of 18 months or less. This means that it is
critical to achieve a rapid design time (or high product velocity ) with no delays.
The last fixed cost shown in Figure 1.12 corresponds to an insurance policy.
When a company buys an ASIC part, it needs to be assured that it will always
have a back-up source, or second source , in case something happens to its first or
primary source. Established FPGA companies have a second source that
produces equivalent parts. With a custom ASIC you may have to do some
redesign to transfer your ASIC to the second source. However, for all ASIC
types, switching production to a second source will involve some cost.
Figure 1.12 assumes a second-source cost of $2000 for all types of ASIC (the
amount may be substantially more than this).
1.4.4 ASIC Variable Costs
Figure 1.14 shows a spreadsheet, Variable Costs, that calculates some example
part costs. This spreadsheet uses the terms and parameters defined below the
figure.
FIGURE 1.14 A spreadsheet, Variable Costs, to calculate the part cost (that is
the variable cost for a product using ASICs) for different ASIC technologies.
●
●
●
●
●
●
The wafer size increases every few years. From 1985 to 1990, 4-inch to
6-inch diameter wafers were common; equipment using 6-inch to 8-inch
wafers was introduced between 1990 and 1995; the next step is the 300 cm
or 12-inch wafer. The 12-inch wafer will probably take us to 2005.
The wafer cost depends on the equipment costs, process costs, and
overhead in the fabrication line. A typical wafer cost is between $1000 and
$5000, with $2000 being average; the cost declines slightly during the life
of a process and increases only slightly from one process generation to the
next.
Moores Law (after Gordon Moore of Intel) models the observation that
the number of transistors on a chip roughly doubles every 18 months. Not
all designs follow this law, but a large ASIC design seems to grow by a
factor of 10 every 5 years (close to Moores Law). In 1990 a large ASIC
design size was 10 k-gate, in 1995 a large design was about 100 k-gate, in
2000 it will be 1 M-gate, in 2005 it will be 10 M-gate.
The gate density is the number of gate equivalents per unit area
(remember: a gate equivalent, or gate, corresponds to a two-input NAND
gate).
The gate utilization is the percentage of gates that are on a die that we can
use (on a gate array we waste some gate space for interconnect).
The die size is determined by the design size (in gates), the gate density,
●
●
●
●
●
●
●
and the utilization of the die.
The number of die per wafer depends on the die size and the wafer size
(we have to pack rectangular or square die, together with some test chips,
on to a circular wafer so some space is wasted).
The defect density is a measure of the quality of the fabrication process.
The smaller the defect density the less likely there is to be a flaw on any
one die. A single defect on a die is almost always fatal for that die. Defect
density usually increases with the number of steps in a process. A defect
density of less than 1 cm 2 is typical and required for a submicron CMOS
process.
The yield of a process is the key to a profitable ASIC company. The yield
is the fraction of die on a wafer that are good (expressed as a percentage).
Yield depends on the complexity and maturity of a process. A process may
start out with a yield of close to zero for complex chips, which then climbs
to above 50 percent within the first few months of production. Within a
year the yield has to be brought to around 80 percent for the average
complexity ASIC for the process to be profitable. Yields of 90 percent or
more are not uncommon.
The die cost is determined by wafer cost, number of die per wafer, and the
yield. Of these parameters, the most variable and the most critical to
control is the yield.
The profit margin (what you sell a product for, less what it costs you to
make it, divided by the cost) is determined by the ASIC companys fixed
and variable costs. ASIC vendors that make and sell custom ASICs have
huge fixed and variable costs associated with building and running
fabrication facilities (a fabrication plant is a fab ). FPGA companies are
typically fabless they do not own a fabthey must pass on the costs of the
chip manufacture (plus the profit margin of the chip manufacturer) and the
development cost of the FPGA structure in the FPGA part cost. The
profitability of any company in the ASIC business varies greatly.
The price per gate (usually measured in cents per gate) is determined by
die costs and design size. It varies with design size and declines over time.
The part cost is determined by all of the preceding factors. As such it will
vary widely with time, process, yield, economic climate, ASIC size and
complexity, and many other factors.
As an estimate you can assume that the price per gate for any process technology
falls at about 20 % per year during its life (the average life of a CMOS process is
24 years, and can vary widely). Beyond the life of a process, prices can increase
as demand falls and the fabrication equipment becomes harder to maintain.
Figure 1.15 shows the price per gate for the different ASICs and process
technologies using the following assumptions:
● For any new process technology the price per gate decreases by 40 % in
the first year, 30 % in the second year, and then remains constant.
●
●
●
●
●
A new process technology is introduced approximately every 2 years, with
feature size decreasing by a factor of two every 5 years as follows: 2 m m
in 1985, 1.5 m m in 1987, 1 m m in 1989, 0.80.6 m m in 19911993, 0.5
0.35 m m in 19961997, 0.250.18 m m in 19982000.
CBICs and MGAs are introduced at approximately the same time and
price.
The price of a new process technology is initially 10 % above the process
that it replaces.
FPGAs are introduced one year after CBICs that use the same process
technology.
The initial FPGA price (per gate) is 10 percent higher than the initial price
for CBICs or MGAs using the same process technology.
From Figure 1.15 you can see that the successive introduction of new process
technologies every 2 years drives the price per gate down at a rate close to 30
percent per year. The cost figures that we have used in this section are very
approximate and can vary widely (this means they may be off by a factor of 2 but
probably are correct within a factor of 10). ASIC companies do use spreadsheet
models like these to calculate their costs.
FIGURE 1.15 Example price per gate figures.
Having decided if, and then which, ASIC technology is appropriate, you need to
choose the appropriate cell library. Next we shall discuss the issues surrounding
ASIC cell libraries: the different types, their sources, and their contents.
1.5 ASIC Cell Libraries
The cell library is the key part of ASIC design. For a programmable ASIC the
FPGA company supplies you with a library of logic cells in the form of a design
kit , you normally do not have a choice, and the cost is usually a few thousand
dollars. For MGAs and CBICs you have three choices: the ASIC vendor (the
company that will build your ASIC) will supply a cell library, or you can buy a
cell library from a third-party library vendor , or you can build your own cell
library.
The first choice, using an ASIC-vendor library , requires you to use a set of
design tools approved by the ASIC vendor to enter and simulate your design.
You have to buy the tools, and the cost of the cell library is folded into the NRE.
Some ASIC vendors (especially for MGAs) supply tools that they have
developed in-house. For some reason the more common model in Japan is to use
tools supplied by the ASIC vendor, but in the United States, Europe, and
elsewhere designers want to choose their own tools. Perhaps this has to do with
the relationship between customer and supplier being a lot closer in Japan than it
is elsewhere.
An ASIC vendor library is normally a phantom library the cells are empty boxes,
or phantoms , but contain enough information for layout (for example, you would
only see the bounding box or abutment box in a phantom version of the cell in
Figure 1.3). After you complete layout you hand off a netlist to the ASIC vendor,
who fills in the empty boxes ( phantom instantiation ) before manufacturing your
chip.
The second and third choices require you to make a buy-or-build decision . If you
complete an ASIC design using a cell library that you bought, you also own the
masks (the tooling ) that are used to manufacture your ASIC. This is called
customer-owned tooling ( COT , pronounced see-oh-tee). A library vendor
normally develops a cell library using information about a process supplied by an
ASIC foundry . An ASIC foundry (in contrast to an ASIC vendor) only provides
manufacturing, with no design help. If the cell library meets the foundry
specifications, we call this a qualified cell library . These cell libraries are
normally expensive (possibly several hundred thousand dollars), but if a library is
qualified at several foundries this allows you to shop around for the most
attractive terms. This means that buying an expensive library can be cheaper in
the long run than the other solutions for high-volume production.
The third choice is to develop a cell library in-house. Many large computer and
electronics companies make this choice. Most of the cell libraries designed today
are still developed in-house despite the fact that the process of library
development is complex and very expensive.
However created, each cell in an ASIC cell library must contain the following:
● A physical layout
● A behavioral model
● A Verilog/VHDL model
● A detailed timing model
● A test strategy
● A circuit schematic
● A cell icon
● A wire-load model
● A routing model
For MGA and CBIC cell libraries we need to complete cell design and cell layout
and shall discuss this in Chapter 2. The ASIC designer may not actually see the
layout if it is hidden inside a phantom, but the layout will be needed eventually.
In a programmable ASIC the cell layout is part of the programmable ASIC
design (see Chapter 4).
The ASIC designer needs a high-level, behavioral model for each cell because
simulation at the detailed timing level takes too long for a complete ASIC design.
For a NAND gate a behavioral model is simple. A multiport RAM model can be
very complex. We shall discuss behavioral models when we describe Verilog and
VHDL in Chapter 10 and Chapter 11. The designer may require Verilog and
VHDL models in addition to the models for a particular logic simulator.
ASIC designers also need a detailed timing model for each cell to determine the
performance of the critical pieces of an ASIC. It is too difficult, too
time-consuming, and too expensive to build every cell in silicon and measure the
cell delays. Instead library engineers simulate the delay of each cell, a process
known as characterization . Characterizing a standard-cell or gate-array library
involves circuit extraction from the full-custom cell layout for each cell. The
extracted schematic includes all the parasitic resistance and capacitance elements.
Then library engineers perform a simulation of each cell including the parasitic
elements to determine the switching delays. The simulation models for the
transistors are derived from measurements on special chips included on a wafer
called process control monitors ( PCMs ) or drop-ins . Library engineers then use
the results of the circuit simulation to generate detailed timing models for logic
simulation. We shall cover timing models in Chapter 13.
All ASICs need to be production tested (programmable ASICs may be tested by
the manufacturer before they are customized, but they still need to be tested).
Simple cells in small or medium-size blocks can be tested using automated
techniques, but large blocks such as RAM or multipliers need a planned strategy.
We shall discuss test in Chapter 14.
The cell schematic (a netlist description) describes each cell so that the cell
designer can perform simulation for complex cells. You may not need the
detailed cell schematic for all cells, but you need enough information to compare
what you think is on the silicon (the schematic) with what is actually on the
silicon (the layout)this is a layout versus schematic ( LVS ) check.
If the ASIC designer uses schematic entry, each cell needs a cell icon together
with connector and naming information that can be used by design tools from
different vendors. We shall cover ASIC design using schematic entry in
Chapter 9. One of the advantages of using logic synthesis (Chapter 12) rather
than schematic design entry is eliminating the problems with icons, connectors,
and cell names. Logic synthesis also makes moving an ASIC between different
cell libraries, or retargeting , much easier.
In order to estimate the parasitic capacitance of wires before we actually
complete any routing, we need a statistical estimate of the capacitance for a net in
a given size circuit block. This usually takes the form of a look-up table known as
a wire-load model . We also need a routing model for each cell. Large cells are
too complex for the physical design or layout tools to handle directly and we
need a simpler representationa phantom of the physical layout that still contains
all the necessary information. The phantom may include information that tells the
automated routing tool where it can and cannot place wires over the cell, as well
as the location and types of the connections to the cell.
1.6 Summary
In this chapter we have looked at the difference between full-custom ASICs,
semi-custom ASICs, and programmable ASICs. Table 1.3 summarizes their
different features. ASICs use a library of predesigned and precharacterized logic
cells. In fact, we could define an ASIC as a design style that uses a cell library
rather than in terms of what an ASIC is or what an ASIC does.
TABLE 1.3 Types of ASIC.
ASIC type
Full-custom
Semicustom
Family member
Analog/digital
Cell-based (CBIC)
Masked gate array (MGA)
Field-programmable gate array
Programmable
(FPGA)
Programmable logic device (PLD)
Custom mask
layers
All
All
Some
Custom logic
cells
Some
None
None
None
None
None
None
You can think of ICs like pizza. A full-custom pizza is built from scratch. You
can customize all the layers of a CBIC pizza, but from a predefined selection, and
it takes a while to cook. An MGA pizza uses precooked crusts with fixed sizes
and you choose only from a few different standard types on a menu. This makes
MGA pizza a little faster to cook and a little cheaper. An FPGA is rather like a
frozen pizzayou buy it at the supermarket in a limited selection of sizes and
types, but you can put it in the microwave at home and it will be ready in a few
minutes.
In each chapter we shall indicate the key concepts. In this chapter they are
● The difference between full-custom and semicustom ASICs
● The difference between standard-cell, gate-array, and programmable
ASICs
● The ASIC design flow
● Design economics including part cost, NRE, and breakeven volume
● The contents and use of an ASIC cell library
Next, in Chapter 2, we shall take a closer look at the semicustom ASICs that
were introduced in this chapter.
1.7 Problems
1.1 (Break-even volumes, 60 min.) You need a spreadsheet program (such as
Microsoft Excel) for this problem.
● a. Build a spreadsheet, Break-even Analysis, to generate Figure 1.11.
● b. Derive equations for the break-even volumes (there are three:
FPGA/MGA, FPGA/CBIC, and MGA/CBIC) and calculate their values.
● c. Increase the FPGA part cost by $10 and use your spreadsheet to produce
the new break-even graph. Hint: (For users of Excel-like spreadsheets) use
the XY scatter plot option. Use the first column for the x -axis data.
● d. Find the new break-even volumes (change the volume until the cost
becomes the same for two technologies).
● e. Program your spreadsheet to automatically find the break-even volumes.
Now graph the break-even volume (for a choice between FPGA and CBIC)
for values of FPGA part costs ranging from $10$50 and CBIC costs
ranging from $2$10 (do not change the fixed costs from Figure 1.12).
● f. Calculate the sensitivity of the break-even volumes to changes in the part
costs and fixed costs. There are three break-even volumes and each of
these is sensitive to two part costs and two fixed costs. Express your
answers in two ways: in equation form and as numbers (for the values in
Section 1.4.2 and Figure 1.11).
● g. The costs in Figure 1.11 are not unrealistic. What can you say from your
answers if you are a defense contractor, primarily selling products in
volumes of less than 1000 parts? What if you are a PC board vendor
selling between 10,000 and 100,000 parts?
1.2 (Design productivity, 10 min.) Given the figures for the SPARCstation 1
ASICs described in Section 1.3 what was the productivity measured in
transistors/day? and measured in gates/day? Compare your answers with the
figures for productivity in Section 1.4.3 and explain any differences. How
accurate do you think productivity estimates are?
1.3 (ASIC package size, 30 min.) Assuming, for this problem, a gate density of
1.0 gate/mil 2 (see Section 15.4, Estimating ASIC Size, for a detailed
explanation of this figure), the maximum number of gates you can put in a
package is determined by the maximum die size for each of the packages shown
in Table 1.4. The maximum die size is determined by the package cavity size;
these are package-limited ASICs. Calculate the maximum number of I/O pads
that can be placed on a die for each package if the pad spacing is: (i) 5 mil, and
(ii) 10 mil. Compare your answers with the maximum numbers of pins (or leads)
on each package and comment. Now calculate the minimum number of gates that
you can put in each package determined by the minimum die size.
TABLE 1.4 Die size limits for ASIC packages.
Maximum die size 2
Package 1 Number of pins or
leads
(mil 2 )
PLCC
44
320 ¥ 320
PLCC
68
420 ¥ 420
PLCC
84
395 ¥ 395
PQFP
100
338 ¥ 338
PQFP
144
350 ¥ 350
PQFP
160
429 ¥ 429
PQFP
208
501 ¥ 501
CPGA
68
480 ¥ 480
CPGA
84
370 ¥ 370
CPGA
120
480 ¥ 480
CPGA
144
470 ¥ 470
CPGA
223
590 ¥ 590
CPGA
299
590 ¥ 590
PPGA
64
230 ¥ 230
PPGA
84
380 ¥ 380
PPGA
100
395 ¥ 395
PPGA
120
395 ¥ 395
PPGA
144
660 ¥ 655
PPGA
180
540 ¥ 540
PPGA
208
500 ¥ 500
Minimum die size 3
(mil 2 )
94 ¥ 94
154 ¥ 154
171 ¥ 171
124 ¥ 124
266 ¥ 266
248 ¥ 248
427 ¥ 427
200 ¥ 200
200 ¥ 200
175 ¥ 175
250 ¥ 250
290 ¥ 290
470 ¥ 470
120 ¥ 120
150 ¥ 150
150 ¥ 150
190 ¥ 190
230 ¥ 230
330 ¥ 330
395 ¥ 395
1.4 (ASIC vendor costs, 30 min.) There is a well-known saying in the ASIC
business: We lose money on every partbut we make it up in volume. This has a
serious side. Suppose Sumo Silicon currently has two customers: Mr. Big, who
currently buys 10,000 parts per week, and Ms. Smart, who currently buys 4800
parts per week. A new customer, Ms. Teeny (who is growing fast), wants to buy
1200 parts per week. Sumos costs are
wafer cost = $500 + ($250,000/ W ),
where W is the number of wafer starts per week. Assume each wafer carries 200
chips (parts), all parts are identical, and the yield is
yield = 70 + 0.2 ¥ ( W 80) % (1.3)
Currently Sumo has a profit margin of 35 percent. Sumo is currently running at
100 wafer starts per week for Mr. Big and Ms. Smart. Sumo thinks they can get
50 cents more out of Mr. Big for his chips, but Ms. Smart wont pay any more.
We can calculate how much Sumo can afford to lose per chip if they want
Ms. Teenys business really badly.
● a. What is Sumos current yield?
● b. How many good parts is Sumo currently producing per week? ( Hint: Is
this enough to supply Mr. Big and Ms. Smart?)
● c. Calculate how many extra wafer starts per week we need to supply
Ms. Teeny (the yield will changewhat is the new yield?). Think when you
give this answer.
● d. What is Sumos increase in costs to supply Ms. Teeny?
● e. Multiply your answer to part d by 1.35 (to account for Sumos profit).
This is the increase in revenue we need to cover our increased costs to
supply Ms. Teeny.
● f. Now suppose we charge Mr. Big 50 cents more per part. How much
extra revenue does that generate?
● g. How much does Ms. Teenys extra business reduce the wafer cost?
● h. How much can Sumo Silicon afford to lose on each of Ms. Teenys
parts, cover its costs, and still make a 35 percent profit?
1.5 (Silicon, 20 min.) How much does a 6-inch silicon wafer weigh? a 12-inch
wafer? How much does a carrier (called a boat) that holds twenty 12-inch wafers
weigh? What implications does this have for manufacturing?
● a. How many die that are 1-inch on a side does a 12-inch wafer hold? If
each die is worth $100, how much is a 20-wafer boat worth? If a factory is
processing 10 of these boats in different furnaces when the power is
interrupted and those wafers have to be scrapped, how much money is
lost?
● b. The size of silicon factories (fabs or foundries) is measured in wafer
starts per week. If a factory is capable of 5000 12-inch wafer starts per
week, with an average die of 500 mil on a side that sells for $20 and 90
percent yield, what is the value in dollars/year of the factory production?
What fraction of the current gross national (or domestic) product
(GNP/GDP) of your country is that? If the yield suddenly drops from 90
percent to 40 percent (a yield bust) how much revenue is the company
losing per day? If the company has a cash reserve of $100 million and this
revenue loss drops straight to the bottom line, how long does it take for
the company to go out of business?
● c. TSMC produced 2 million 6-inch wafers in 1996, how many 500 mil die
is that? TSMCs $500 million Camas fab in Washington is scheduled to
produce 30,000 8-inch wafers per month by the year 2000 using a 0.35 mm
process. If a 1 Mb SRAM yields 1500 good die per 8-inch wafer and there
are 1700 gross die per wafer, what is the yield? What is the die size? If the
SRAM cell size is 7 mm 2 , what fraction of the die is used by the cells?
What is TSMCs cost per bit for SRAM if the wafer cost is $2000? If a
16Mb DRAM on the same fab line uses a 16 mm 2 die, what is the cost per
bit for DRAM assuming the same yield?
1.6 (Simulation time, 30 min.) . . . The system-level simulation used
approximately 4000 lines of SPARC assembly language . . . each simulation
clock was simulated in three real time seconds (Sun Technology article).
● a. With a 20 MHz clock how much slower is simulated time than real
time?
● b. How long would it take to simulate all 4000 lines of test code? (Assume
one line of assembly code per cyclea good approximation compared to the
others we are making.)
The article continues: the entire system was simulated, running actual code,
including several milliseconds of SunOS execution. Four days after power-up,
SPARCstation 1 booted SunOS and announced: 'hello world' .
● c. How long would it take to simulate 5 ms of code?
● d. Find out how long it takes to boot a UNIX workstation in real time. How
many clock cycles is this?
● e. The machine is not executing boot code all this time; you have to wait
for disk drives to spin-up, file systems checks to complete, and so on.
Make some estimates as to how much code is required to boot an operating
system (OS) and how many clock cycles this would take to execute.
The number of clock cycles you need to simulate to boot a system is somewhere
between your answers to parts d and e.
● f. From your answers make an estimate of how long it takes to simulate
booting the OS. Does this seem reasonable?
● g. Could the engineers have simulated a complete boot sequence?
● h. Do you think the engineers expected the system to boot on first silicon,
given the complexity of the system and how long they would have to wait
to simulate a complete boot sequence? Explain.
1.7 (Price per gate, 5 min.) Given the assumptions of Section 1.4.4 on the price
per gate of different ASIC technologies, what has to change for the price per gate
for an FPGA to be less than that for an MGA or CBICif all three use the same
process?
1.8 (Pentiums, 20 min.) Read the online tour of the Pentium Pro at
http://www.intel.com (adapted from a paper presented at the 1995 International
Solid-State Circuits Conference). This is not an ASIC design; notice the section
on full-custom circuit design. Notice also the comments on the use of 'assert'
statements in the HDL code that described the circuits. Find out the approximate
cost of the Intel Pentium (3.3 million transistors) and Pentium Pro (5.5 million
transistors) microprocessors.
● a. Assuming there a four transistors per gate equivalent, what is the price
●
●
per gate?
b. Find out the cost of a 1 Mb, 4 Mb, 8 Mb, or 16 Mb DRAM. Assuming
one transistor per memory bit, what is the price per gate of DRAM?
c. Considering that both have roughly the same die size, are just as
complex to design and to manufacture, why is there such a huge difference
in price per gate between microprocessors and DRAM?
1.9 (Inverse embedded arrays, 10 min.) A relatively new cousin of the embedded
gate array, the inverse-embedded gate array , is a cell-based ASIC that contains
an embedded gate-array megacell. List the features as well as the advantages and
disadvantages of this type of ASIC in the same way as for the other members of
the ASIC family in Section 1.1.
1.10 (0.5-gate design, 60 min.) It is a good idea to complete a 0.5-gate ASIC
design (an inverter connected between an input pad and an output pad) in the first
week (day) of class. Capture the commands in a report that shows all the steps
taken to create your chip starting from an empty directory halfgate .
1.11 (Filenames, 30 min.) Start a list of filename extensions used in ASIC design.
Table 1.5 shows an example. Expand this list as you use more tools.
TABLE 1.5 CAD tool filename extensions.
Extension Description
From
To
Viewlogic startup file,
.ini
library
Viewlogic/Viewdraw Internal tools use
search paths, etc.
other Viewlogic tools
.wir
Schematic file
1. PLCC = plastic leaded chip carrier, PQFP = plastic quad flat pack, CPGA =
ceramic pin-grid array, PPGA = plastic pin-grid array.
2. Maximum die size is not standard and varies between manufacturers.
3. Minimum die size is an estimate based on bond length restrictions.
1.8 Bibliography
The Addison-Wesley VLSI Design Series covers all aspects of VLSI design.
Mead and Conway [1980] is an introduction to VLSI design. Glasser and
Dobberpuhl [1985] deal primarily with NMOS technology, but their book is still
a valuable circuit design reference. Bakoglus book [1990] concentrates on
system interconnect issues. Both editions of Weste and Eshraghian [1993]
describe full-custom VLSI design.
Other books on CMOS design include books by Kang and Leblebici [1996],
Wolf [1994], Price [1994], Hurst [1992], and Shoji [1988]. Alvarez [1993] covers
BiCMOS, but concentrates more on technology than design. Embabi, Bellaouar,
and Elmasry [1993] also cover BiCMOS design from a similar perspective.
Elmasrys book [1994] contains a collection of papers on BiCMOS design.
Einspruch and Hilbert [1991]; Huber and Rosneck [1991]; and Veendrick [1992]
are introductions to ASIC design for nontechnical readers. Long and Butner
[1990] cover gallium arsenide (GaAs) IC design. Most books on CMOS and
ASIC design are classified in the TK7874 section of the Library of Congress
catalog (T is for technology).
Several journals and magazines publish articles on ASICs and ASIC design. The
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN
1063-8210, TK7874.I3273, 1993) is dedicated to VLSI design. The IEEE
Custom Integrated Circuits Conference (ISSN 0886-5930, TK7874.C865, 1979)
and the IEEE International ASIC Conference (TK7874.6.I34a, 19881991;
TK7874.6.I35, ISSN 1063-0988, 1991) both cover the design and use of ASICs.
EE Times (ISSN 0192-1541, http://techweb.cmp.com/eet ) is a newsletter that
includes a wide-ranging coverage of system design, ASICs, and ASIC design.
Integrated System Design (ISSN 1080-2797), formerly ASIC & EDA ) is a
monthly publication that includes ASIC design topics. High Performance
Systems (ISSN 0887-9664), formerly VLSI Design (ISSN 0279-2834), deals
with system design including the use of ASICs. EDN (ISSN 0012-7515,
http://www.ednmag.com ) has broader coverage of the electronics industry,
including articles on VLSI and systems design. Computer Design (ISSN
0010-4566) is targeted at systems-level design but includes coverage of ASICs
(for example, a special issue in August 1996 was devoted to ASIC design).
The Electronic Industries Association (EIA) has produced a standard,
JESD12-1B, Terms and definitions for gate arrays and cell-based digital
integrated circuits, to define terms and definitions.
University Video Communication ( http://www.uvc.com ) produces several
videotapes on computer science and engineering topics including ASIC design.
Malys book [1987] is a picture book containing drawings and cross-sections of
devices, and shows how a transistor is fabricated.
It is difficult to obtain detailed technical information from ASIC companies and
vendors apart from the glossy brochures ( sparkle sheets ). It used to be possible
to obtain data books on cell libraries (now these are large and difficult to
produce, and are often only available in electronic form) as well as design
guidelines and handbooks. Fortunately there are now many resources available
on the World Wide Web, which are, of course, constantly changing. EDAC
(Electronic Design Automation Companies) has a Web page (
http://www.edac.org ) with links to most of the EDA companies. The Electrical
Engineering page on the World Wide Web (E2W3) ( http://www.e2w3.com )
contains links to many ASIC related areas, including distributors, ASIC
companies, and semiconductor companies. SEMATECH (Semiconductor
Manufacturing Technology) is a nonprofit consortium of U.S. semiconductor
companies and has a Web page ( http://www.sematech.org ) that includes links to
major semiconductor manufacturers. The MIT Semiconductor Subway (
http://www-mtl.mit.edu ) is more oriented toward devices, processes, and
materials but contains links to other VLSI industrial and academic areas. There is
a list of EDA companies at http://www.yahoo.com under
Business_and_Economy in
Companies/Computers/Software/Graphics/CAD/IC_Design .
The MOS Implementation Service (MOSIS), located at the Information Sciences
Institute (ISI) at the University of Southern California (USC), is a silicon broker
for universities in the United States and also provides commercial access to
fabrication facilities ( http://www.isi.edu ). Professor Don Bouldin maintains The
Microelectronic Systems Newsletter, formerly the MOSIS Users Group (MUG)
Newsletter, at http://www-ece.engr.utk.edu/ece .
NASA ( http://nppp.jpl.nasa.gov/dmg/jpl/loc/asic ) has an extensive online ASIC
guide, developed by the Office of Safety and Mission Assurance, that covers
ASIC management, vendor evaluation, design, and part acceptance.
1.9 References
Alvarez, A. R. (Ed.). 1993. BiCMOS Technology and Applications. Norwell,
MA: Kluwer. ISBN 0-7923-9384-8. TK7871.99.M44.
Bakoglu, H. B. 1990. Circuits, Interconnections, and Packaging for VLSI.
Reading, MA: Addison-Wesley, 527 p. ISBN 0-86341-165-7. TK7874.B345.
Based on a Stanford Ph.D. thesis and contains chapters on: devices and
interconnections, packaging, transmission lines, cross talk, clocking of
high-speed systems, system level performance.
Einspruch N. G., and J. L. Hilbert (Eds.). 1991. Application Specific Integrated
Circuit (ASIC) Technology. San Diego, CA: Academic Press. ISBN
0122341236. TK7874.V56 vol. 23. Includes: Introduction to ASIC technology,
Hilbert; Market dynamics of the ASIC revolution, Collett; Marketing ASICs,
Chakraverty; Design and architecture of ASIC products, Hickman et al.; Model
and library development, Lubhan; Computer-aided design tools and systems,
Rowson; ASIC manufacturing, Montalbo; Test and testability of ASICs,
Rosqvist; Electronic packaging for ASICs, Herrell and Prokop; Application and
selection of ASICs, Mitchell; Designing with ASICs, Wilkerson; Quality and
reliability, Young.
Elmasry, M. I. 1994. BiCMOS Integrated Circuit Design: with Analog, Digital,
and Smart Power Applications. New York: IEEE Press, ISBN 0780304306.
TK7871.99.M44.B53.
Embabi, S. H. K., A. Bellaouar, and M. I. Elmasry. 1993. Digital BiCMOS
Integrated Circuit Design. Norwell: MA: Kluwer, 398 p. ISBN 0-7923-9276-0.
TK7874.E52.
Glasser, L. A., and D. W. Dobberpuhl. 1985. The Design and Analysis of VLSI
Circuits. Reading, MA: Addison-Wesley, 473 p. ISBN 0-201-12580-3.
TK7874.G573. Detailed analysis of circuits, but largely nMOS.
Huber, J. P., and M. W. Rosneck. 1991. Successful ASIC Design the First Time
Through. New York: Van Nostrand Reinhold, 200 p. ISBN 0-442-00312-9.
TK7874.H83.
Hurst, S. L. 1992. Custom VLSI Microelectronics. Englewood Cliffs, NJ:
Prentice-Hall, 466 p. ISBN 0-13-194416-9. TK7874.H883.
Kang, S-M, and Y. Leblebici. 1996. CMOS Digital Integrated Circuits: Analysis
and Design. New York: McGraw-Hill, 614 p. ISBN 0070380465.
Long, S. I., and S. E. Butner. 1990. Gallium Arsenide Digital Integrated Circuit
Design. New York: McGraw-Hill, 486 p. ISBN 0-07-038687-0. TK7874.L66.
Maly, W. 1987. Atlas of IC Technologies: An Introduction to VLSI Processes.
Menlo Park, CA: Benjamin-Cummings, 340 p. ISBN 0-8053-6850-7.
TK7874.M254. Cross-sectional drawings showing construction of nMOS and
CMOS processes.
Mead, C. A., and L. A. Conway. 1980. Introduction to VLSI Systems. Reading,
MA: Addison-Wesley, 396 p. ISBN 0-201-04358-0. TK7874.M37.
Price, T. E. 1994. Introduction to VLSI Technology. Englewood Cliffs, NJ:
Prentice-Hall, 280 p. ISBN 0-13-500422-5. TK7874.P736.
Shoji, M. 1988. CMOS Digital Circuit Technology. Englewood Cliffs, NJ:
Prentice-Hall, 434 p. ISBN 0131388436. TK7871.99.M44. See also Shoji, M.,
High Speed Digital Circuits, Reading, MA: Addison-Wesley, 1996, 360 p., ISBN
0-201-63483-X, TK7874.65.S56
Weste, N. H. E., and K. Eshraghian. 1993. Principles of CMOS VLSI Design: A
Systems Perspective. 2nd ed. Reading, MA: Addison-Wesley, 713 p. ISBN
0-201-53376-6. TK7874.W46. Concentrates on full-custom design.
Wolf, W. H. 1994. Modern VLSI Design: A Systems Approach. Englewood
Cliffs, NJ: Prentice-Hall, 468 p. ISBN 0-13-588377-6. TK7874.65.W65.
Veendrick, H. J. M. 1992. MOS ICs from Basics to ASICs. New York: VCH,
ISBN 1-56081197-8. TK7874.V397.
L ast E d ited by S P 1411 2 0 0 4
CMOS LOGIC
A CMOS transistor (or device) has four terminals: gate , source , drain , and a
fourth terminal that we shall ignore until the next section. A CMOS transistor is a
switch. The switch must be conducting or on to allow current to flow between the
source and drain terminals (using open and closed for switches is confusingfor
the same reason we say a tap is on and not that it is closed ). The transistor source
and drain terminals are equivalent as far as digital signals are concernedwe do
not worry about labeling an electrical switch with two terminals.
● V AB is the potential difference, or voltage, between nodes A and B in a
circuit; V AB is positive if node A is more positive than node B.
●
●
●
●
●
●
Italics denote variables; constants are set in roman (upright) type.
Uppercase letters denote DC, large-signal, or steady-state voltages.
For TTL the positive power supply is called VCC (V CC or V CC ). The 'C'
denotes that the supply is connected indirectly to the collectors of the npn
bipolar transistors (a bipolar transistor has a collector, base, and emitter
corresponding roughly to the drain, gate, and source of an MOS
transistor).
Following the example of TTL we used VDD (V DD or V DD ) to denote
the positive supply in an NMOS chip where the devices are all n -channel
transistors and the drains of these devices are connected indirectly to the
positive supply. The supply nomenclature for NMOS chips has stuck for
CMOS.
VDD is the name of the power supply node or net; V DD represents the
value (uppercase since V DD is a DC quantity). Since V DD is a variable, it
is italic (words and multiletter abbreviations use romanthus it is V DD , but
V drain ).
Logic designers often call the CMOS negative supply VSS or VSS even if
it is actually ground or GND. I shall use VSS for the node and V SS for the
value.
CMOS uses positive logic VDD is logic '1' and VSS is logic '0'.
We turn a transistor on or off using the gate terminal. There are two kinds of
CMOS transistors: n -channel transistors and p -channel transistors. An n
-channel transistor requires a logic '1' (from now on Ill just say a '1') on the gate
to make the switch conducting (to turn the transistor on ). A p -channel transistor
requires a logic '0' (again from now on, Ill just say a '0') on the gate to make the
switch nonconducting (to turn the transistor off ). The p -channel transistor
symbol has a bubble on its gate to remind us that the gate has to be a '0' to turn
the transistor on . All this is shown in Figure 2.1(a) and (b).
FIGURE 2.1 CMOS transistors as switches. (a) An n -channel transistor. (b) A p
-channel transistor. (c) A CMOS inverter and its symbol (an equilateral triangle
and a circle ).
If we connect an n -channel transistor in series with a p -channel transistor, as
shown in Figure 2.1(c), we form an inverter . With four transistors we can form a
two-input NAND gate (Figure 2.2a). We can also make a two-input NOR gate
(Figure 2.2b). Logic designers normally use the terms NAND gate and logic gate
(or just gate), but I shall try to use the terms NAND cell and logic cell rather than
NAND gate or logic gate in this chapter to avoid any possible confusion with the
gate terminal of a transistor.
FIGURE 2.2 CMOS logic. (a) A two-input NAND logic cell. (b) A two-input
NOR logic cell. The n -channel and p -channel transistor switches implement the
'1's and '0's of a Karnaugh map.
2.1 CMOS Transistors
2.2 The CMOS Process
2.3 CMOS Design Rules
2.4 Combinational Logic Cells
2.5 Sequential Logic Cells
2.6 Datapath Logic Cells
2.7 I/O Cells
2.8 Cell Compilers
2.9 Summary
2.10 Problems
2.11 Bibliography
2.12 References
2.1 CMOS Transistors
Figure 2.3 illustrates how electrons and holes abandon their dopant atoms leaving
a depletion region around a transistors source and drain. The region between
source and drain is normally nonconducting. To make an n -channel transistor
conducting, we must apply a positive voltage V GS (the gate voltage with respect
to the source) that is greater than the n -channel transistor threshold voltage , V t n
(a typical value is 0.5 V and, as far as we are presently concerned, is a constant).
This establishes a thin ( ª 50 Å) conducting channel of electrons under the gate.
MOS transistors can carry a very small current (the subthreshold current a few
microamperes or less) with V GS < V t n , but we shall ignore this. A transistor
can be conducting ( V GS > V t n ) without any current flowing. To make current
flow in an n -channel transistor we must also apply a positive voltage, V DS , to
the drain with respect to the source. Figure 2.3 shows these connections and the
connection to the fourth terminal of an MOS transistorthe bulk ( well , tub , or
substrate ) terminal. For an n -channel transistor we must connect the bulk to the
most negative potential, GND or VSS, to reverse bias the bulk-to-drain and
bulk-to-source pn -diodes. The arrow in the four-terminal n -channel transistor
symbol in Figure 2.3 reflects the polarity of these pn -diodes.
FIGURE 2.3 An n -channel MOS transistor. The gate-oxide thickness, T OX , is
approximately 100 angstroms (0.01 m m). A typical transistor length, L = 2 l .
The bulk may be either the substrate or a well. The diodes represent pn
-junctions that must be reverse-biased.
The current flowing in the transistor is
current (amperes) = charge (coulombs) per unit time (second). (2.1)
We can express the current in terms of the total charge in the channel, Q (imagine
taking a picture and counting the number of electrons in the channel at that
instant). If t f (for time of flight sometimes called the transit time ) is the time
that it takes an electron to cross between source and drain, the drain-to-source
current, I DSn , is
I DSn = Q / t f . (2.2)
We need to find Q and t f . The velocity of the electrons v (a vector) is given by
the equation that forms the basis of Ohms law:
v= m
n
E , (2.3)
where m n is the electron mobility ( m p is the hole mobility ) and E is the electric
field (with units Vm 1 ).
Typical carrier mobility values are m n = 5001000 cm 2 V 1 s 1 and m p = 100
400 cm 2 V 1 s 1 . Equation 2.3 is a vector equation, but we shall ignore the
vertical electric field and concentrate on the horizontal electric field, E x , that
moves the electrons between source and drain. The horizontal component of the
electric field is E x = V DS / L, directed from the drain to the source, where L is
the channel length (see Figure 2.3). The electrons travel a distance L with
horizontal velocity v x = m n E x , so that
L2
L
tf=
=
. (2.4)
v x m n V DS
Next we find the channel charge, Q . The channel and the gate form the plates of
a capacitor, separated by an insulatorthe gate oxide. We know that the charge on
a linear capacitor, C, is Q = C V . Our lower plate, the channel, is not a linear
conductor. Charge only appears on the lower plate when the voltage between the
gate and the channel, V GC , exceeds the n -channel threshold voltage. For our
nonlinear capacitor we need to modify the equation for a linear capacitor to the
following:
Q = C ( V GC V
tn
) . (2.5)
The lower plate of our capacitor is resistive and conducting current, so that the
potential in the channel, V GC , varies. In fact, V GC = V GS at the source and V
GC = V GS V DS at the drain. What we really should do is find an expression for
the channel charge as a function of channel voltage and sum (integrate) the
charge all the way across the channel, from x = 0 (at the source) to x = L (at the
drain). Instead we shall assume that the channel voltage, V GC ( x ), is a linear
function of distance from the source and take the average value of the charge,
which is thus
Q = C [ ( V GS V
tn
) 0.5 V
DS
] . (2.6)
The gate capacitance, C , is given by the formula for a parallel-plate capacitor
with length L , width W , and plate separation equal to the gate-oxide thickness,
T ox . Thus the gate capacitance is
WL e ox
= WLC ox , (2.7)
C=
T ox
where e ox is the gate-oxide dielectric permittivity. For silicon dioxide, Si0 2 , e ox
ª 3.45 ¥ 10 11 Fm 1 , so that, for a typical gate-oxide thickness of 100 Å (1 Å = 1
angstrom = 0.1 nm), the gate capacitance per unit area, C ox ª 3 f F m m 2 .
Now we can express the channel charge in terms of the transistor parameters,
Q = WL C ox [ ( V GS V
tn
) 0.5 V
DS
] . (2.8)
Finally, the drainsource current is
I DSn = Q/ t f
= (W/L) m n C ox [ ( V GS V
= (W/L)k ' n [ ( V GS V
tn
tn
) 0.5 V
) 0.5 V
DS
DS
] V DS
] V DS .
(2.9)
The constant k ' n is the process transconductance parameter (or intrinsic
transconductance ):
k ' n = m n C ox . (2.10)
We also define b n , the transistor gain factor (or just gain factor ) as
b n = k ' n (W/L) . (2.11)
The factor W/L (transistor width divided by length) is the transistor shape factor .
Equation 2.9 describes the linear region (or triode region) of operation. This
equation is valid until V DS = V GS V t n and then predicts that I DS decreases
with increasing V DS , which does not make physical sense. At V DS = V GS V t
n = V DS (sat) (the saturation voltage ) there is no longer enough voltage between
the gate and the drain end of the channel to support any channel charge. Clearly a
small amount of charge remains or the current would go to zero, but with very
little free charge the channel resistance in a small region close to the drain
increases rapidly and any further increase in V DS is dropped over this region.
Thus for V DS > V GS V t n (the saturation region , or pentode region, of
operation) the drain current IDS remains approximately constant at the saturation
current , I DSn (sat) , where
I DSn (sat) = ( b n /2)( V GS V
tn
)2 ;
V GS > V t n . (2.12)
Figure 2.4 shows the n -channel transistor I DS V DS characteristics for a generic
0.5 m m CMOS process that we shall call G5 . We can fit Eq. 2.12 to the
long-channel transistor characteristics (W = 60 m m, L = 6 m m) in Figure 2.4(a).
If I DSn (sat) = 2.5 mA (with V DS = 3.0 V, V GS = 3.0 V, V t n = 0.65 V, T ox
=100 Å), the intrinsic transconductance is
2(L/W) I DSn (sat)
k'n=
(2.13)
( V GS V
tn
)2
2 (6/60) (2.5 ¥ 10 3 )
=
2
(3.0 0.65)
= 9.05 ¥ 10 5 AV 2
or approximately 90 m AV 2 . This value of k ' n , calculated in the saturation
region, will be different (typically lower by a factor of 2 or more) from the value
of k ' n measured in the linear region. We assumed the mobility, m n , and the
threshold voltage, V t n , are constantsneither of which is true, as we shall see in
Section 2.1.2.
For the p -channel transistor in the G5 process, I DSp (sat) = 850 m A ( V
3.0 V, V GS = 3.0 V, V t p = 0.85 V, W = 60 m m, L = 6 m m). Then
2 (L/W) ( I
DSp (sat)
)
k'p=
(2.14)
( V GS V
tp
)2
2 (6/60) (850 ¥ 10 6 )
=
(3.0 (0.85) )
2
= 3.68 ¥ 10 5 AV 2
The next section explains the signs in Eq. 2.14.
DS
=
(a)
(b)
FIGURE 2.4 MOS n -channel
transistor characteristics for a generic
(c)
0.5 m m process (G5). (a) A
short-channel transistor, with W = 6 m
m and L = 0.6 m m (drawn) and a
long-channel transistor (W = 60 m m,
L = 6 m m) (b) The 6/0.6
characteristics represented as a
surface. (c) A long-channel transistor
obeys a square-law characteristic
between I DS and V GS in the
saturation region ( V DS = 3 V). A
short-channel transistor shows a more
linear characteristic due to velocity
saturation. Normally, all of the
transistors used on an ASIC have short
channels.
2.1.1 P-Channel Transistors
The source and drain of CMOS transistors look identical; we have to know which
way the current is flowing to distinguish them. The source of an n -channel
transistor is lower in potential than the drain and vice versa for a p -channel
transistor. In an n -channel transistor the threshold voltage, V t n , is normally
positive, and the terminal voltages V DS and V GS are also usually positive. In a p
-channel transistor V t p is normally negative and we have a choice: We can write
everything in terms of the magnitudes of the voltages and currents or we can use
negative signs in a consistent fashion.
Here are the equations for a p -channel transistor using negative signs:
k ' p (W/L) [ ( V GS V
=
V tp
I DSp
I DSp (sat) = b
p
/2 ( V GS V
tp
tp
) 0.5 V
)2 ;
DS
] V DS ;
V DS < V GS V
tp
V DS > V GS
(2.15)
.
In these two equations V t p is negative, and the terminal voltages V DS and V GS
are also normally negative (and 3 V < 2 V, for example). The current I DSp is
then negative, corresponding to conventional current flowing from source to
drain of a p -channel transistor (and hence the negative sign for I DSp (sat) in
Eq. 2.14).
2.1.2 Velocity Saturation
For a deep submicron transistor, Eq. 2.12 may overestimate the drainsource
current by a factor of 2 or more. There are three reasons for this error. First, the
threshold voltage is not constant. Second, the actual length of the channel (the
electrical or effective length, often written as L eff ) is less than the drawn (mask)
length. The third reason is that Eq. 2.3 is not valid for high electric fields. The
electrons cannot move any faster than about v max n = 10 5 ms 1 when the electric
field is above 10 6 Vm 1 (reached when 1 V is dropped across 1 m m); the
electrons become velocity saturated . In this case t f = L eff / v max n , the drain
source saturation current is independent of the transistor length, and Eq. 2.12
becomes
I DSn (sat) =
Wv max n C ox ( V GS V
saturated).
tn
);
V DS > V DS (sat) (velocity
(2.16)
We can see this behavior for the short-channel transistor characteristics in
Figure 2.4(a) and (c).
Transistor current is often specified per micron of gate width because of the form
of Eq. 2.16. As an example, suppose I DSn (sat) / W = 300 m A m m 1 for the n
-channel transistors in our G5 process (with V DS = 3.0 V, V GS = 3.0 V, V t n =
0.65 V, L eff = 0.5 m m and T ox = 100 Å). Then E x ª (3 0.65) V / 0.5 m m ª 5 V
mm1 ,
I DSn (sat) /W
v max n =
(2.17)
C ox ( V GS V
tn
)
(300 ¥ 10 6 ) (1 ¥ 10 6 )
=
(3.45 ¥ 10 3 ) (3 0.65)
= 37,000 ms 1
and t f ª 0.5 m m/37,000 ms 1 ª 13 ps.
The value for v max n is lower than the 10 5 ms 1 we expected because the carrier
velocity is also lowered by mobility degradation due the vertical electric field
which we have ignored. This vertical field forces the carriers to keep bumping
in to the interface between the silicon and the gate oxide, slowing them down.
2.1.3 SPICE Models
The simulation program SPICE (which stands for Simulation Program with
Integrated Circuit Emphasis ) is often used to characterize logic cells. Table 2.1
shows a typical set of model parameters for our G5 process. The SPICE
parameter KP (given in m AV 2 ) corresponds to k ' n (and k ' p ). SPICE
parameters VT0 and TOX correspond to V t n (and V t p ), and T ox . SPICE
parameter U0 (given in cm 2 V 1 s 1 ) corresponds to the ideal bulk mobility
values, m n (and m p ). Many of the other parameters model velocity saturation
and mobility degradation (and thus the effective value of k ' n and k ' p ).
TABLE 2.1 SPICE parameters for a generic 0.5 m m process, G5 (0.6 m m
drawn gate length). The n-channel transistor characteristics are shown in
Figure 2.4.
.MODEL CMOSN NMOS LEVEL=3 PHI=0.7 TOX=10E-09 XJ=0.2U TPG=1
VTO=0.65 DELTA=0.7
+ LD=5E-08 KP=2E-04 UO=550 THETA=0.27 RSH=2 GAMMA=0.6
NSUB=1.4E+17 NFS=6E+11
+ VMAX=2E+05 ETA=3.7E-02 KAPPA=2.9E-02 CGDO=3.0E-10
CGSO=3.0E-10 CGBO=4.0E-10
+ CJ=5.6E-04 MJ=0.56 CJSW=5E-11 MJSW=0.52 PB=1
.MODEL CMOSP PMOS LEVEL=3 PHI=0.7 TOX=10E-09 XJ=0.2U TPG=-1
VTO=-0.92 DELTA=0.29
+ LD=3.5E-08 KP=4.9E-05 UO=135 THETA=0.18 RSH=2 GAMMA=0.47
NSUB=8.5E+16 NFS=6.5E+11
+ VMAX=2.5E+05 ETA=2.45E-02 KAPPA=7.96 CGDO=2.4E-10
CGSO=2.4E-10 CGBO=3.8E-10
+ CJ=9.3E-04 MJ=0.47 CJSW=2.9E-10 MJSW=0.505 PB=1
2.1.4 Logic Levels
Figure 2.5 shows how to use transistors as logic switches. The bulk connection
for the n -channel transistor in Figure 2.5(ab) is a p -well. The bulk connection
for the p -channel transistor is an n -well. The remaining connections show what
happens when we try and pass a logic signal between the drain and source
terminals.
FIGURE 2.5 CMOS logic levels. (a) A strong '0'. (b) A weak '1'. (c) A weak '0'.
(d) A strong '1'. ( V t n is positive and V t p is negative.) The depth of the
channels is greatly exaggerated.
In Figure 2.5(a) we apply a logic '1' (or VDD I shall use these interchangeably)
to the gate and a logic '0' ( V SS ) to the source (we know it is the source since
electrons must flow from this point, since V SS is the lowest voltage on the chip).
The application of these voltages makes the n -channel transistor conduct current,
and electrons flow from source to drain.
Suppose the drain is initially at logic '1'; then the n -channel transistor will begin
to discharge any capacitance that is connected to its drain (due to another logic
cell, for example). This will continue until the drain terminal reaches a logic '0',
and at that time V GD and V GS are both equal to V DD , a full logic '1'. The
transistor is strongly conducting now (with a large channel charge, Q , but there
is no current flowing since V DS = 0 V). The transistor will strongly object to
attempts to change its drain terminal from a logic '0'. We say that the logic level
at the drain is a strong '0'.
In Figure 2.5(b) we apply a logic '1' to the drain (it must now be the drain since
electrons have to flow toward a logic '1'). The situation is now quite differentthe
transistor is still on but V GS is decreasing as the source voltage approaches its
final value. In fact, the source terminal never gets to a logic '1'the source will
stop increasing in voltage when V GS reaches V t n . At this point the transistor is
very nearly off and the source voltage creeps slowly up to V DD V t n . Because
the transistor is very nearly off, it would be easy for a logic cell connected to the
source to change the potential there, since there is so little channel charge. The
logic level at the source is a weak '1'. Figure 2.5(cd) show the state of affairs for
a p -channel transistor is the exact reverse or complement of the n -channel
transistor situation.
In summary, we have the following logic levels:
● An n -channel transistor provides a strong '0', but a weak '1'.
● A p -channel transistor provides a strong '1', but a weak '0'.
Sometimes we refer to the weak versions of '0' and '1' as degraded logic levels .
In CMOS technology we can use both types of transistor together to produce
strong '0' logic levels as well as strong '1' logic levels.
2.2 The CMOS Process
Figure 2.6 outlines the steps to create an integrated circuit. The starting material
is silicon, Si, refined from quartzite (with less than 1 impurity in 10 10 silicon
atoms). We draw a single-crystal silicon boule (or ingot) from a crucible
containing a melt at approximately 1500 °C (the melting point of silicon at 1 atm.
pressure is 1414 °C). This method is known as Czochralski growth. Acceptor ( p
-type) or donor ( n -type) dopants may be introduced into the melt to alter the
type of silicon grown.
The boule is sawn to form thin circular wafers (6, 8, or 12 inches in diameter, and
typically 600 m m thick), and a flat is ground (the primary flat), perpendicular to
the <110> crystal axisas a this edge down indication. The boule is drawn so
that the wafer surface is either in the (111) or (100) crystal planes. A smaller
secondary flat indicates the wafer crystalline orientation and doping type. A
typical submicron CMOS processes uses p -type (100) wafers with a resistivity of
approximately 10 W cmthis type of wafer has two flats, 90° apart. Wafers are
made by chemical companies and sold to the IC manufacturers. A blank 8-inch
wafer costs about $100.
To begin IC fabrication we place a batch of wafers (a wafer lot ) on a boat and
grow a layer (typically a few thousand angstroms) of silicon dioxide , SiO 2 ,
using a furnace. Silicon is used in the semiconductor industry not so much for the
properties of silicon, but because of the physical, chemical, and electrical
properties of its native oxide, SiO 2 . An IC fabrication process contains a series
of masking steps (that in turn contain other steps) to create the layers that define
the transistors and metal interconnect.
FIGURE 2.6 IC fabrication. Grow crystalline silicon (1); make a wafer (23);
grow a silicon dioxide (oxide) layer in a furnace (4); apply liquid photoresist
(resist) (5); mask exposure (6); a cross-section through a wafer showing the
developed resist (7); etch the oxide layer (8); ion implantation (910); strip the
resist (11); strip the oxide (12). Steps similar to 412 are repeated for each layer
(typically 1220 times for a CMOS process).
Each masking step starts by spinning a thin layer (approximately 1 m m) of liquid
photoresist ( resist ) onto each wafer. The wafers are baked at about 100 °C to
remove the solvent and harden the resist before being exposed to ultraviolet (UV)
light (typically less than 200 nm wavelength) through a mask . The UV light
alters the structure of the resist, allowing it to be removed by developing. The
exposed oxide may then be etched (removed). Dry plasma etching etches in the
vertical direction much faster than it does horizontally (an anisotropic etch). Wet
etch techniques are usually isotropic . The resist functions as a mask during the
etch step and transfers the desired pattern to the oxide layer.
Dopant ions are then introduced into the exposed silicon areas. Figure 2.6
illustrates the use of ion implantation . An ion implanter is a cross between a TV
and a mass spectrometer and fires dopant ions into the silicon wafer. Ions can
only penetrate materials to a depth (the range , normally a few microns) that
depends on the closely controlled implant energy (measured in keVusually
between 10 and 100 keV; an electron volt, 1 eV, is 1.6 ¥ 10 19 J). By using layers
of resist, oxide, and polysilicon we can prevent dopant ions from reaching the
silicon surface and thus block the silicon from receiving an implant . We control
the doping level by counting the number of ions we implant (by integrating the
ion-beam current). The implant dose is measured in atoms/cm 2 (typical doses are
from 10 13 to 10 15 cm 2 ). As an alternative to ion implantation we may instead
strip the resist and introduce dopants by diffusion from a gaseous source in a
furnace.
Once we have completed the transistor diffusion layers we can deposit layers of
other materials. Layers of polycrystalline silicon (polysilicon or poly ), SiO 2 ,
and silicon nitride (Si 3 N 4 ), for example, may be deposited using chemical
vapor deposition ( CVD ). Metal layers can be deposited using sputtering . All
these layers are patterned using masks and similar photolithography steps to
those shown in Figure 2.6.
Mask/layer name
n -well
p -well
active
TABLE 2.2 CMOS process layers.
Derivation from
Alternative names for
drawn layers
mask/layer
bulk, substrate, tub, n
= nwell 1
-tub, moat
bulk, substrate, tub, p
= pwell 1
-tub, moat
thin oxide, thinox, island,
= pdiff + ndiff
gate oxide
= poly
poly, gate
MOSIS mask
label
CWN
CWP
CAA
polysilicon
n -diffusion implant
= grow (ndiff)
2
ndiff, n -select, nplus, n+ CSN
p -diffusion implant = grow (pdiff)
pdiff, p -select, pplus, p+ CSP
2
contact
= contact
metal1
metal2
= m1
= m2
via2
= via2
metal3
= m3
glass
= glass
contact cut, poly contact,
diffusion contact
first-level metal
second-level metal
metal2/metal3 via,
m2/m3 via
third-level metal
passivation, overglass,
pad
CPG
CCP and
CCA 3
CMF
CMS
CVS
CMT
COG
Table 2.2 shows the mask layers (and their relation to the drawn layers) for a
submicron, silicon-gate, three-level metal, self-aligned, CMOS process . A
process in which the effective gate length is less than 1 m m is referred to as a
submicron process . Gate lengths below 0.35 m m are considered in the
deep-submicron regime.
Figure 2.7 shows the layers that we draw to define the masks for the logic cell of
Figure 1.3. Potential confusion arises because we like to keep layout simple but
maintain a what you see is what you get (WYSIWYG) approach. This means
that the drawn layers do not correspond directly to the masks in all cases.
(a) nwell
(b) pwell
(c) ndiff
(d) pdiff
(e) poly
(f) contact
(g) m1
(h) via
(i) m2
(j) cell
(k) phantom
FIGURE 2.7 The standard cell shown in Figure 1.3. (a)(i) The drawn layers that
define the masks. The active mask is the union of the ndiff and pdiff drawn
layers. The n -diffusion implant and p -diffusion implant masks are bloated
versions of the ndiff and pdiff drawn layers. (j) The complete cell layout. (k) The
phantom cell layout. Often an ASIC vendor hides the details of the internal cell
construction. The phantom cell is used for layout by the customer and then
instantiated by the ASIC vendor after layout is complete. This layout uses
grayscale stipple patterns to distinguish between layers.
We can construct wells in a CMOS process in several ways. In an n-well process
, the substrate is p -type (the wafer itself) and we use an n -well mask to build the
n -well. We do not need a p -well mask because there are no p -wells in an n
-well processthe n -channel transistors all sit in the substrate (the wafer)but we
often draw the p -well layer as though it existed. In a p-well process we use a p
-well mask to make the p -wells and the n -wells are the substrate. In a twin-tub
(or twin-well ) process, we create individual wells for both types of transistors,
and neither well is the substrate (which may be either n -type or p -type). There
are even triple-well processes used to achieve even more control over the
transistor performance. Whatever process that we use we must connect all the n
-wells to the most positive potential on the chip, normally VDD, and all the p
-wells to VSS; otherwise we may forward bias the bulk to source/drain pn
-junctions. The bulk connections for CMOS transistors are not usually drawn in
digital circuit schematics, but these substrate contacts ( well contacts or tub ties )
are very important. After we make the well(s), we grow a layer (approximately
1500 Å) of Si 3 N 4 over the wafer. The active mask (CAA) leaves this nitride
layer only in the active areas that will later become transistors or substrate
contacts. Thus
CAA (mask) = ndiff (drawn) ( pdiff (drawn) , (2.18)
the ( symbol represents OR (union) of the two drawn layers, ndiff and pdiff.
Everything outside the active areas is known as the field region, or just field .
Next we implant the substrate to prevent unwanted transistors from forming in
the field regionthis is the field implant or channel-stop implant . The nitride over
the active areas acts as an implant mask and we may use another field-implant
mask at this step also. Following this we grow a thick (approximately 5000 Å)
layer of SiO 2 , the field oxide ( FOX ). The FOX will not grow over the nitride
areas. When we strip the nitride we are left with FOX in the areas we do not want
to dope the silicon. Following this we deposit, dope, mask, and etch the poly gate
material, CPG (mask) = poly (drawn). Next we create the doped regions that
form the sources, drains, and substrate contacts using ion implantation. The poly
gate functions like masking tape in these steps. One implant (using phosphorous
or arsenic ions) forms the n -type source/drain for the n -channel transistors and n
-type substrate contacts (CSN). A second implant (using boron ions) forms the p
-type sourcedrain for the p -channel transistors and p -type substrate contacts
(CSP). These implants are masked as follows
CSN (mask) = grow (ndiff (drawn)), (2.19)
CSP (mask) = grow (pdiff (drawn)), (2.20)
where grow means that we expand or bloat the drawn ndiff and drawn pdiff
layers slightly (usually by a few l ).
During implantation the dopant ions are blocked by the resist pattern defined by
the CSN and CSP masks. The CSN mask thus prevents the n -type regions being
implanted with p -type dopants (and vice versa for the CSP mask). As we shall
see, the CSN and CSP masks are not intended to define the edges of the n -type
and p -type regions. Instead these two masks function more like newspaper that
prevents paint from spraying everywhere. The dopant ions are also blocked from
reaching the silicon surface by the poly gates and this aligns the edge of the
source and drain regions to the edges of the gates (we call this a self-aligned
process ). In addition, the implants are blocked by the FOX and this defines the
outside edges of the source, drain, and substrate contact regions.
The only areas of the silicon surface that are doped n -type are
n -diffusion (silicon) = (CAA (mask) ' CSN (mask)) ' ( ÿ CPG (mask)) ; (2.21)
where the ' symbol represents AND (the intersection of two layers); and the ÿ
symbol represents NOT.
Similarly, the only regions that are doped p -type are
p -diffusion (silicon) = (CAA (mask) ' CSP (mask)) ' ( ÿ CPG (mask)) . (2.22)
If the CSN and CSP masks do not overlap, it is possible to save a mask by using
one implant mask (CSN or CSP) for the other type (CSP or CSN). We can do this
by using a positive resist (the pattern of resist remaining after developing is the
same as the dark areas on the mask) for one implant step and a negative resist
(vice versa) for the other step. However, because of the poor resolution of
negative resist and because of difficulties in generating the implant masks
automatically from the drawn diffusions (especially when opposite diffusion
types are drawn close to each other or touching), it is now common to draw both
implant masks as well as the two diffusion layers.
It is important to remember that, even though poly is above diffusion, the
polysilicon is deposited first and acts like masking tape. It is rather like
airbrushing a stripeyou use masking tape and spray everywhere without
worrying about making straight lines. The edges of the pattern will align to the
edge of the tape. Here the analogy ends because the poly is left in place. Thus,
n -diffusion (silicon) = (ndiff (drawn)) ' ( ÿ poly (drawn)) and (2.23)
p -diffusion (silicon) = (pdiff (drawn)) ' ( ÿ poly (drawn)) . (2.24)
In the ASIC industry the names nplus, n +, and n -diffusion (as well as the p -type
equivalents) are used in various ways. These names may refer to either the drawn
diffusion layer (that we call ndiff), the mask (CSN), or the doped region on the
silicon (the intersection of the active and implant mask that we call n -diffusion)
very confusing.
The source and drain are often formed from two separate implants. The first is a
light implant close to the edge of the gate, the second a heavier implant that
forms the rest of the source or drain region. The separate diffusions reduce the
electric field near the drain end of the channel. Tailoring the device
characteristics in this fashion is known as drain engineering and a process
including these steps is referred to as an LDD process , for lightly doped drain ;
the first light implant is known as an LDD diffusion or LDD implant.
FIGURE 2.8 Drawn layers and
an example set of
black-and-white stipple patterns
for a CMOS process. On top are
the patterns as they appear in
layout. Underneath are the
magnified 8-by-8 pixel patterns.
If we are trying to simplify
layout we may use solid black or
white for contact and vias. If we
have contacts and vias placed on
top of one another we may use
stipple patterns or other means
to help distinguish between
them. Each stipple pattern is
transparent, so that black shows
through from underneath when
layers are superimposed. There
are no standards for these
patterns.
Figure 2.8 shows a stipple-pattern matrix for a CMOS process. When we draw
layout you can see through the layersall the stipple patterns are ORed together.
Figure 2.9 shows the transistor layers as they appear in layout (drawn using the
patterns from Figure 2.8) and as they appear on the silicon. Figure 2.10 shows the
same thing for the interconnect layers.
FIGURE 2.9 The transistor layers. (a) A p -channel transistor as drawn in layout.
(b) The corresponding silicon cross section (the heavy lines in part a show the
cuts). This is how a p -channel transistor would look just after completing the
source and drain implant steps.
FIGURE 2.10 The interconnect
layers. (a) Metal layers as drawn
in layout. (b) The corresponding
structure (as it might appear in a
scanning-electron micrograph).
The insulating layers between
the metal layers are not shown.
Contact is made to the
underlying silicon through a
platinum barrier layer. Each via
consists of a tungsten plug. Each
metal layer consists of a
titaniumtungsten and aluminum
copper sandwich. Most deep
submicron CMOS processes use
metal structures similar to this.
The scale, rounding, and
irregularity of the features are
realistic.
2.2.1 Sheet Resistance
Tables 2.3 and 2.4 show the sheet resistance for each conducting layer (in
decreasing order of resistance) for two different generations of CMOS process.
TABLE 2.3 Sheet resistance (1 m m
CMOS).
Sheet
Units
Layer
resistance
kW/
n -well
1.15 ± 0.25
square
W/
poly
3.5 ± 2.0
square
W/
n -diffusion
75 ± 20
square
W/
p -diffusion
140 ± 40
square
mW/
m1/2
70± 6
square
mW/
m3
30± 3
square
TABLE 2.4 Sheet resistance (0.35 m
m CMOS).
Sheet
Units
Layer
resistance
kW/
n -well
1 ± 0.4
square
W/
poly
10 ± 4.0
square
W/
n -diffusion
3.5 ± 2.0
square
W/
p -diffusion
2.5 ± 1.5
square
mW/
m1/2/3
60 ± 6
square
mW/
metal4
30 ± 3
square
The diffusion layers, n -diffusion and p -diffusion, both have a high resistivity
typically from 1100 W /square. We measure resistance in W / square (ohms per
square) because for a fixed thickness of material it does not matter what the size
of a square isthe resistance is the same. Thus the resistance of a rectangular
shape of a sheet of material may be calculated from the number of squares it
contains times the sheet resistance in W / square. We can use diffusion for very
short connections inside a logic cell, but not for interconnect between logic cells.
Poly has the next highest resistance to diffusion. Most submicron CMOS
processes use a silicide material (a metallic compound of silicon) that has much
lower resistivity (at several W /square) than the poly or diffusion layers alone.
Examples are tantalum silicide, TaSi; tungsten silicide, WSi; or titanium silicide,
TiSi. The stoichiometry of these deposited silicides varies. For example, for
tungsten silicide W:Si ª 1:2.6.
There are two types of silicide process. In a silicide process only the gate is
silicided. This reduces the poly sheet resistance, but not that of the sourcedrain.
In a self-aligned silicide ( salicide ) process, both the gate and the sourcedrain
regions are silicided. In some processes silicide can be used to connect adjacent
poly and diffusion (we call this feature LI , white metal, local interconnect,
metal0, or m0). LI is useful to reduce the area of ASIC RAM cells, for example.
Interconnect uses metal layers with resistivities of tens of m W /square, several
orders of magnitude less than the other layers. There are usually several layers of
metal in a CMOS ASIC process, each separated by an insulating layer. The metal
layer above the poly gate layer is the first-level metal ( m1 or metal1), the next is
the second-level metal ( m2 or metal2), and so on. We can make connections
from m1 to diffusion using diffusion contacts or to the poly using polysilicon
contacts .
After we etch the contact holes a thin barrier metal (typically platinum) is
deposited over the silicon and poly. Next we form contact plugs ( via plugs for
connections between metal layers) to reduce contact resistance and the likelihood
of breaks in the contacts. Tungsten is commonly used for these plugs. Following
this we form the metal layers as sandwiches. The middle of the sandwich is a
layer (usually from 3000 Å to 10,000 Å) of aluminum and copper. The top and
bottom layers are normally titaniumtungsten (TiW, pronounced tie-tungsten).
Submicron processes use chemicalmechanical polishing ( CMP ) to smooth the
wafers flat before each metal deposition step to help with step coverage.
An insulating glass, often sputtered quartz (SiO 2 ), though other materials are
also used, is deposited between metal layers to help create a smooth surface for
the deposition of the metal. Design rules may refer to this insulator as an
intermetal oxide ( IMO ) whether they are in fact oxides or not, or interlevel
dielectric ( ILD ). The IMO may be a spin-on polymer; boron-doped
phosphosilicate glass (BPSG); Si 3 N 4 ; or sandwiches of these materials
(oxynitrides, for example).
We make the connections between m1 and m2 using metal vias , cuts , or just
vias . We cannot connect m2 directly to diffusion or poly; instead we must make
these connections through m1 using a via. Most processes allow contacts and vias
to be placed directly above each other without restriction, arrangements known as
stacked vias and stacked contacts . We call a process with m1 and m2 a two-level
metal ( 2LM ) technology. A 3LM process includes a third-level metal layer ( m3
or metal3), and some processes include more metal layers. In this case a
connection between m1 and m2 will use an m1/m2 via, or via1 ; a connection
between m2 and m3 will use an m2/m3 via, or via2 , and so on.
The minimum spacing of interconnects, the metal pitch , may increase with
successive metal layers. The minimum metal pitch is the minimum spacing
between the centers of adjacent interconnects and is equal to the minimum metal
width plus the minimum metal spacing.
Aluminum interconnect tends to break when carrying a high current density.
Collisions between high-energy electrons and atoms move the metal atoms over a
long period of time in a process known as electromigration . Copper is added to
the aluminum to help reduce the problem. The other solution is to reduce the
current density by using wider than minimum-width metal lines.
Tables 2.5 and 2.6 show maximum specified contact resistance and via resistance
for two generations of CMOS processes. Notice that a m1 contact in either
process is equal in resistance to several hundred squares of metal.
TABLE 2.5 Contact resistance (1 m m
CMOS).
Resistance
Contact/via type
(maximum)
m2/m3 via (via2) 5 W
m1/m2 via (via1) 2 W
m1/ p -diffusion
20 W
contact
m1/ n -diffusion
20 W
contact
m1/poly contact 20 W
TABLE 2.6 Contact resistance (0.35 m
m CMOS).
Resistance
Contact/via type
(maximum)
m2/m3 via (via2) 6 W
m1/m2 via (via1) 6 W
m1/ p -diffusion
20 W
contact
m1/ n -diffusion
20 W
contact
m1/poly contact 20 W
1. If only one well layer is drawn, the other mask may be derived from the drawn
layer. For example, p -well (mask) = not (nwell (drawn)). A single-well process
requires only one well mask.
2. The implant masks may be derived or drawn.
3. Largely for historical reasons the contacts to poly and contacts to active have
different layer names. In the past this allowed a different sizing or process bias to
be applied to each contact type when the mask was made.
2.3 CMOS Design Rules
Figure 2.11 defines the design rules for a CMOS process using pictures. Arrows
between objects denote a minimum spacing, and arrows showing the size of an
object denote a minimum width. Rule 3.1, for example, is the minimum width of
poly (2 l ). Each of the rule numbers may have different values for different
manufacturersthere are no standards for design rules. Tables 2.72.9 show the
MOSIS scalable CMOS rules. Table 2.7 shows the layer rules for the process
front end , which is the front end of the line (as in production line) or FEOL .
Table 2.8 shows the rules for the process back end ( BEOL ), the metal
interconnect, and Table 2.9 shows the rules for the pad layer and glass layer.
FIGURE 2.11 The MOSIS scalable CMOS design rules (rev. 7). Dimensions are
in l . Rule numbers are in parentheses (missing rule sets 1113 are extensions to
this basic process).
TABLE 2.7 MOSIS scalable CMOS rules version 7the process front end.
Layer
Rule Explanation
Value / l
well (CWN, CWP) 1.1
minimum width
10
minimum space (different potential, a hot
1.2
9
well)
1.3
minimum space (same potential)
0 or 6
1.4
minimum space (different well type)
0
active (CAA)
2.1/2.2 minimum width/space
2.3
source/drain active to well edge space
substrate/well contact active to well edge
2.4
space
minimum space between active (different
2.5
implant type)
poly (CPG)
3.1/3.2 minimum width/space
3.3
minimum gate extension of active
3.4
minimum active extension of poly
3.5
minimum field poly to active space
select (CSN, CSP)
4.1
3
5
3
0 or 4
2
2
3
1
minimum select spacing to channel of
transistor 1
minimum select overlap of active
minimum select overlap of contact
minimum select width and spacing 2
2
1
2
poly contact (CCP) 5.1.a
5.2.a
5.3.a
exact contact size
minimum poly overlap
minimum contact spacing
2¥2
1.5
2
active contact (CCA) 6.1.a
6.2.a
6.3.a
exact contact size
minimum active overlap
minimum contact spacing
2¥2
1.5
2
4.2
4.3
4.4
3
6.4.a
minimum space to gate of transistor
2
TABLE 2.8 MOSIS scalable CMOS rules version 7the process back end.
Layer
Rule Explanation
Value / l
metal1 (CMF) 7.1 minimum width
3
7.2.a minimum space
3
7.2.b minimum space (for minimum-width wires only) 2
7.3 minimum overlap of poly contact
1
7.4 minimum overlap of active contact
1
via1 (CVA) 8.1 exact size
2¥2
8.2 minimum via spacing
3
8.3 minimum overlap by metal1
1
8.4 minimum spacing to contact
2
8.5 minimum spacing to poly or active edge
2
metal2 (CMS) 9.1 minimum width
3
9.2.a minimum space
4
9.2.b minimum space (for minimum-width wires only) 3
9.3 minimum overlap of via1
1
via2 (CVS) 14.1 exact size
2¥2
14.2 minimum space
3
14.3 minimum overlap by metal2
1
14.4 minimum spacing to via1
2
metal3 (CMT) 15.1 minimum width
6
15.2 minimum space
4
15.3 minimum overlap of via2
2
TABLE 2.9 MOSIS scalable CMOS rules version 7the pads and overglass
(passivation).
Layer
Rule Explanation
Value
100 m m ¥ 100 m
glass (COG) 10.1 minimum bonding-pad width
m
10.2 minimum probe-pad width
75 m m ¥ 75 m m
10.3 pad overlap of glass opening
6mm
minimum pad spacing to unrelated metal2
10.4
30 m m
(or metal3)
minimum pad spacing to unrelated
10.5
15 m m
metal1, poly, or active
The rules in Table 2.7 and Table 2.8 are given as multiples of l . If we use
lambda-based rules we can move between successive process generations just by
changing the value of l . For example, we can scale 0.5 m m layouts ( l = 0.25 m
m) by a factor of 0.175 / 0.25 for a 0.35 m m process ( l = 0.175 m m)at least in
theory. You may get an inkling of the practical problems from the fact that the
values for pad dimensions and spacing in Table 2.9 are given in microns and not
in l . This is because bonding to the pads is an operation that does not scale well.
Often companies have two sets of design rules: one in l (with fractional l rules)
and the other in microns. Ideally we would like to express all of the design rules
in integer multiples of l . This was true for revisions 46, but not revision 7 of the
MOSIS rules. In revision 7 rules 5.2a/6.2a are noninteger. The original Mead
Conway NMOS rules include a noninteger 1.5 l rule for the implant layer.
1. To ensure source and drain width.
2. Different select types may touch but not overlap.
2.4 Combinational Logic Cells
The AND-OR-INVERT (AOI) and the OR-AND-INVERT (OAI) logic cells are
particularly efficient in CMOS. Figure 2.12 shows an AOI221 and an OAI321
logic cell (the logic symbols in Figure 2.12 are not standards, but are widely
used). All indices (the indices are the numbers after AOI or OAI) in the logic cell
name greater than 1 correspond to the inputs to the first level or stagethe AND
gate(s) in an AOI cell, for example. An index of '1' corresponds to a direct input
to the second-stage cell. We write indices in descending order; so it is AOI221
and not AOI122 (but both are equivalent cells), and AOI32 not AOI23. If we
have more than one direct input to the second stage we repeat the '1'; thus an
AOI211 cell performs the function Z = (A.B + C + D)'. A three-input NAND cell
is an OAI111, but calling it that would be very confusing. These rules are not
standard, but form a convention that we shall adopt and one that is widely used in
the ASIC industry.
There are many ways to represent the logical operator, AND. I shall use the
middle dot and write A · B (rather than AB, A.B, or A ' B); occasionally I may
use AND(A, B). Similarly I shall write A + B as well as OR(A, B). I shall use an
apostrophe like this, A', to denote the complement of A rather than A since
sometimes it is difficult or inappropriate to use an overbar ( vinculum ) or
diacritical mark (macron). It is possible to misinterpret AB' as A B rather than
AB (but the former alternative would be A · B' in my convention). I shall be
careful in these situations.
FIGURE 2.12 Naming and
numbering complex CMOS
combinational cells. (a) An
AND-OR-INVERT cell, an
AOI221. (b) An
OR-AND-INVERT cell, an
OAI321. Numbering is
always in descending order.
We can express the function of the AOI221 cell in Figure 2.12(a) as
Z = (A · B + C · D + E)' . (2.25)
We can also write this equation unambiguously as Z = OAI221(A, B, C, D, E),
just as we might write X = NAND (I, J, K) to describe the logic function
X = (I · J · K)'.
This notation is useful because, for example, if we write OAI321(P, Q, R, S, T,
U) we immediately know that U (the sixth input) is the (only) direct input
connected to the second stage. Sometimes we need to refer to particular inputs
without listing them all. We can adopt another convention that letters of the input
names change with the index position. Now we can refer to input B2 of an
AOI321 cell, for example, and know which input we are talking about without
writing
Z = AOI321(A1, A2, A3, B1, B2, C) . (2.26)
Table 2.10 shows the AOI family of logic cells with three indices (with branches
in the family for AOI, OAI, AO, and OA cells). There are 5 types and 14 separate
members of each branch of this family. There are thus 4 ¥ 14 = 56 cells of the
type X abc where X = {OAI, AOI, OA, AO} and each of the indexes a , b , and c
can range from 1 to 3. We form the AND-OR (AO) and OR-AND (OA) cells by
adding an inverter to the output of an AOI or OAI cell.
TABLE 2.10 The AOI family of cells with three index numbers or less.
Cell type 1 Cells
Number of unique cells
Xa1
X21, X31
2
Xa11
X211, X311
2
Xab
X22, X33, X32
3
Xab1
X221, X331, X321
3
Xabc
X222, X333, X332, X322
4
Total
14
2.4.1 Pushing Bubbles
The AOI and OAI logic cells can be built using a single stage in CMOS using
seriesparallel networks of transistors called stacks. Figure 2.13 illustrates the
procedure to build the n -channel and p -channel stacks, using the AOI221 cell as
an example.
FIGURE 2.13 Constructing a CMOS logic cellan AOI221. (a) First build the
dual icon by using de Morgans theorem to push inversion bubbles to the
inputs. (b) Next build the n -channel and p -channel stacks from series and
parallel combinations of transistors. (c) Adjust transistor sizes so that the nchannel and p -channel stacks have equal strengths.
Here are the steps to construct any single-stage combinational CMOS logic cell:
1. Draw a schematic icon with an inversion (bubble) on the last cell (the
bubble-out schematic). Use de Morgans theorems A NAND is an OR
with inverted inputs and a NOR is an AND with inverted inputsto push
the output bubble back to the inputs (this the dual icon or bubble-in
schematic).
2. Form the n -channel stack working from the inputs on the bubble-out
schematic: OR translates to a parallel connection, AND translates to a
series connection. If you have a bubble at an input, you need an inverter.
3. Form the p -channel stack using the bubble-in schematic (ignore the
inversions at the inputsthe bubbles on the gate terminals of the p -channel
transistors take care of these). If you do not have a bubble at the input gate
terminals, you need an inverter (these will be the same input gate terminals
that had bubbles in the bubble-out schematic).
The two stacks are network duals (they can be derived from each other by
swapping series connections for parallel, and parallel for series connections). The
n -channel stack implements the strong '0's of the function and the p -channel
stack provides the strong '1's. The final step is to adjust the drive strength of the
logic cell by sizing the transistors.
2.4.2 Drive Strength
Normally we ratio the sizes of the n -channel and p -channel transistors in an
inverter so that both types of transistors have the same resistance, or drive
strength . That is, we make b n = b p . At low dopant concentrations and low
electric fields m n is about twice m p . To compensate we make the shape factor,
W/L, of the p -channel transistor in an inverter about twice that of the n -channel
transistor (we say the logic has a ratio of 2). Since the transistor lengths are
normally equal to the minimum poly width for both types of transistors, the ratio
of the transistor widths is also equal to 2. With the high dopant concentrations
and high electric fields in submicron transistors the difference in mobilities is less
typically between 1 and 1.5.
Logic cells in a library have a range of drive strengths. We normally call the
minimum-size inverter a 1X inverter. The drive strength of a logic cell is often
used as a suffix; thus a 1X inverter has a cell name such as INVX1 or INVD1. An
inverter with transistors that are twice the size will be an INVX2. Drive strengths
are normally scaled in a geometric ratio, so we have 1X, 2X, 4X, and
(sometimes) 8X or even higher, drive-strength cells. We can size a logic cell
using these basic rules:
● Any string of transistors connected between a power supply and the output
in a cell with 1X drive should have the same resistance as the n -channel
transistor in a 1X inverter.
● A transistor with shape factor W 1 /L 1 has a resistance proportional to L 1
/W 1 (so the larger W 1 is, the smaller the resistance).
●
●
Two transistors in parallel with shape factors W 1 /L 1 and W 2 /L 2 are
equivalent to a single transistor (W 1 /L 1 + W 2 /L 2 )/1. For example, a 2/1
in parallel with a 3/1 is a 5/1.
Two transistors, with shape factors W 1 /L 2 and W 2 /L 2 , in series are
equivalent to a single 1/(L 1 /W 1 + L 2 /W 2 ) transistor.
For example, a transistor with shape factor 3/1 (we shall call this a 3/1) in series
with another 3/1 is equivalent to a 1/((1/3) + (1/3)) or a 3/2. We can use the
following method to calculate equivalent transistor sizes:
● To add transistors in parallel, make all the lengths 1 and add the widths.
● To add transistors in series, make all the widths 1 and add the lengths.
We have to be careful to keep W and L reasonable. For example, a 3/1 in series
with a 2/1 is equivalent to a 1/((1/3) + (1/2)) or 1/0.83. Since we cannot make a
device 2 l wide and 1.66 l long, a 1/0.83 is more naturally written as 3/2.5. We
like to keep both W and L as integer multiples of 0.5 (equivalent to making W
and L integer multiples of l ), but W and L must be greater than 1.
In Figure 2.13(c) the transistors in the AOI221 cell are sized so that any string
through the p -channel stack has a drive strength equivalent to a 2/1 p -channel
transistor (we choose the worst case, if more than one transistor in parallel is
conducting then the drive strength will be higher). The n -channel stack is sized
so that it has a drive strength of a 1/1 n -channel transistor. The ratio in this
library is thus 2.
If we were to use four drive strengths for each of the AOI family of cells shown
in Table 2.10, we would have a total of 224 combinational library cellsjust for
the AOI family. The synthesis tools can handle this number of cells, but we may
not be able to design this many cells in a reasonable amount of time. Section 3.3,
Logical Effort, will help us choose the most logically efficient cells.
2.4.3 Transmission Gates
Figure 2.14(a) and (b) shows a CMOS transmission gate ( TG , TX gate, pass
gate, coupler). We connect a p -channel transistor (to transmit a strong '1') in
parallel with an n -channel transistor (to transmit a strong '0').
FIGURE 2.14 CMOS transmission gate (TG). (a) An n- channel and p -channel
transistor in parallel form a TG. (b) A common symbol for a TG. (c) The
charge-sharing problem.
We can express the function of a TG as
Z = TG(A, S) , (2.27)
but this is ambiguousif we write TG(X, Y), how do we know if X is connected to
the gates or sources/drains of the TG? We shall always define TG(X, Y) when we
use it. It is tempting to write TG(A, S) = A · S, but what is the value of Z when S
='0' in Figure 2.14(a), since Z is then left floating? A TG is a switch, not an AND
logic cell.
There is a potential problem if we use a TG as a switch connecting a node Z that
has a large capacitance, C BIG , to an input node A that has only a small
capacitance C SMALL (see Figure 2.14c). If the initial voltage at A is V SMALL
and the initial voltage at Z is V BIG , when we close the TG (by setting S = '1') the
final voltage on both nodes A and Z is
C BIG V BIG + C SMALL V SMALL
VF=
. (2.28)
C BIG + C SMALL
Imagine we want to drive a '0' onto node Z from node A. Suppose C BIG = 0.2 pF
(about 10 standard loads in a 0.5 m m process) and C SMALL = 0.02 pF, V BIG = 0
V and V SMALL = 5 V; then
(0.2 ¥ 10 12 ) (0) + (0.02 ¥ 10 12 ) (5)
VF=
= 0.45 V . (2.29)
(0.2 ¥ 10 12 ) + (0.02 ¥ 10 12 )
This is not what we want at all, the big capacitor has forced node A to a voltage
close to a '0'. This type of problem is known as charge sharing . We should make
sure that either (1) node A is strong enough to overcome the big capacitor, or (2)
insulate node A from node Z by including a buffer (an inverter, for example)
between node A and node Z. We must not use charge to drive another logic cell
only a logic cell can drive a logic cell.
If we omit one of the transistors in a TG (usually the p -channel transistor) we
have a pass transistor . There is a branch of full-custom VLSI design that uses
pass-transistor logic. Much of this is based on relay-based logic, since a single
transistor switch looks like a relay contact. There are many problems associated
with pass-transistor logic related to charge sharing, reduced noise margins, and
the difficulty of predicting delays. Though pass transistors may appear in an
ASIC cell inside a library, they are not used by ASIC designers.
FIGURE 2.15 The CMOS multiplexer (MUX). (a) A noninverting 2:1 MUX
using transmission gates without buffering. (b) A symbol for a MUX (note how
the inputs are labeled). (c) An IEEE standard symbol for a MUX. (d) A
nonstandard, but very common, IEEE symbol for a MUX. (e) An inverting
MUX with output buffer. (f) A noninverting buffered MUX.
We can use two TGs to form a multiplexer (or multiplexorpeople use both
orthographies) as shown in Figure 2.15(a). We often shorten multiplexer to MUX
. The MUX function for two data inputs, A and B, with a select signal S, is
Z = TG(A, S') + TG(B, S) . (2.30)
We can write this as Z = A · S' + B · S, since node Z is always connected to one
or other of the inputs (and we assume both are driven). This is a two-input MUX
(2-to-1 MUX or 2:1 MUX). Unfortunately, we can also write the MUX function
as Z = A · S + B · S', so it is difficult to write the MUX function unambiguously
as Z = MUX(X, Y, Z). For example, is the select input X, Y, or Z? We shall
define the function MUX(X, Y, Z) each time we use it. We must also be careful
to label a MUX if we use the symbol shown in Figure 2.15(b). Symbols for a
MUX are shown in Figure 2.15(bd). In the IEEE notation 'G' specifies an AND
dependency. Thus, in Figure 2.15(c), G = '1' selects the input labeled '1'.
Figure 2.15(d) uses the common control block symbol (the notched rectangle).
Here, G1 = '1' selects the input '1', and G1 = '0' selects the input ' 1 '. Strictly this
form of IEEE symbol should be used only for elements with more than one
section controlled by common signals, but the symbol of Figure 2.15(d) is used
often for a 2:1 MUX.
The MUX shown in Figure 2.15(a) works, but there is a potential charge-sharing
problem if we cascade MUXes (connect them in series). Instead most ASIC
libraries use MUX cells built with a more conservative approach. We could
buffer the output using an inverter (Figure 2.15e), but then the MUX becomes
inverting. To build a safe, noninverting MUX we can buffer the inputs and output
(Figure 2.15f)requiring 12 transistors, or 3 gate equivalents (only the gate
equivalent counts are shown from now on).
Figure 2.16 shows how to use an OAI22 logic cell (and an inverter) to implement
an inverting MUX. The implementation in equation form (2.5 gates) is
ZN = A' · S' + B' · S
= [(A' · S')' · (B' · S)']'
= [ (A + S) · (B + S')]'
= OAI22[A, S, B, NOT(S)] . (2.31)
(both A' and NOT(A) represent an inverter, depending on which representation is
most convenientthey are equivalent). I often use an equation to describe a cell
implementation.
FIGURE 2.16 An inverting 2:1 MUX based on an
OAI22 cell.
The following factors will determine which MUX implementation is best:
1. Do we want to minimize the delay between the select input and the output
or between the data inputs and the output?
2. Do we want an inverting or noninverting MUX?
3. Do we object to having any logic cell inputs tied directly to the
source/drain diffusions of a transmission gate? (Some companies forbid
such transmission-gate inputs since some simulation tools cannot handle
them.)
4. Do we object to any logic cell outputs being tied to the source/drain of a
transmission gate? (Some companies will not allow this because of the
dangers of charge sharing.)
5. What drive strength do we require (and is size or speed more important)?
A minimum-size TG is a little slower than a minimum-size inverter, so there is
not much difference between the implementations shown in Figure 2.15 and
Figure 2.16, but the difference can become important for 4:1 and larger MUXes.
2.4.4 Exclusive-OR Cell
The two-input exclusive-OR ( XOR , EXOR, not-equivalence, ring-OR) function
is
A1 • A2 = XOR(A1, A2) = A1 · A2' + A1' · A2 . (2.32)
We are now using multiletter symbols, but there should be no doubt that A1'
means anything other than NOT(A1). We can implement a two-input XOR using
a MUX and an inverter as follows (2 gates):
XOR(A1, A2) = MUX[NOT(A1), A1, A2] , (2.33)
where
MUX(A, B, S) = A · S + B · S ' . (2.34)
This implementation only buffers one input and does not buffer the MUX output.
We can use inverter buffers (3.5 gates total) or an inverting MUX so that the
XOR cell does not have any external connections to source/drain diffusions as
follows (3 gates total):
XOR(A1, A2) = NOT[MUX(NOT[NOT(A1)], NOT(A1), A2)] . (2.35)
We can also implement a two-input XOR using an AOI21 (and a NOR cell),
since
XOR(A1, A2) = A1 · A2' + A1' · A2
= [ (A1 ·A2) + (A1 + A2)' ]'
= AOI21[A1, A2, NOR(A1, A2)], (2.36)
(2.5 gates). Similarly we can implement an exclusive-NOR (XNOR, equivalence)
logic cell using an inverting MUX (and two inverters, total 3.5 gates) or an
OAI21 logic cell (and a NAND cell, total 2.5 gates) as follows (using the MUX
function of Eq. 2.34):
XNOR(A1, A2) = A1 · A2 + NOT(A1) · NOT(A2
= NOT[NOT[MUX(A1, NOT (A1), A2]]
= OAI21[A1, A2, NAND(A1, A2)] .
(2.37)
1. Xabc: X = {AOI, AO, OAI, OA}; a, b, c = {2, 3}; { } means choose one.
2.5 Sequential Logic Cells
There are two main approaches to clocking in VLSI design: multiphase clocks or
a single clock and synchronous design . The second approach has the following
key advantages: (1) it allows automated design, (2) it is safe, and (3) it permits
vendor signoff (a guarantee that the ASIC will work as simulated). These
advantages of synchronous design (especially the last one) usually outweigh
every other consideration in the choice of a clocking scheme. The vast majority
of ASICs use a rigid synchronous design style.
2.5.1 Latch
Figure 2.17(a) shows a sequential logic cella latch . The internal clock signals,
CLKN (N for negative) and CLKP (P for positive), are generated from the system
clock, CLK, by two inverters (I4 and I5) that are part of every latch cellit is
usually too dangerous to have these signals supplied externally, even though it
would save space.
FIGURE 2.17 CMOS latch. (a) A positive-enable latch using transmission gates
without output buffering, the enable (clock) signal is buffered inside the latch.
(b) A positive-enable latch is transparent while the enable is high. (c) The latch
stores the last value at D when the enable goes low.
To emphasize the difference between a latch and flip-flop, sometimes people
refer to the clock input of a latch as an enable . This makes sense when we look
at Figure 2.17(b), which shows the operation of a latch. When the clock input is
high, the latch is transparent changes at the D input appear at the output Q (quite
different from a flip-flop as we shall see). When the enable (clock) goes low
(Figure 2.17c), inverters I2 and I3 are connected together, forming a storage loop
that holds the last value on D until the enable goes high again. The storage loop
will hold its state as long as power is on; we call this a static latch. A sequential
logic cell is different from a combinational cell because it has this feature of
storage or memory.
Notice that the output Q is unbuffered and connected directly to the output of I2
(and the input of I3), which is a storage node. In an ASIC library we are
conservative and add an inverter to buffer the output, isolate the sensitive storage
node, and thus invert the sense of Q. If we want both Q and QN we have to add
two inverters to the circuit of Figure 2.17(a). This means that a latch requires
seven inverters and two TGs (4.5 gates).
The latch of Figure 2.17(a) is a positive-enable D latch, active-high D latch, or
transparent-high D latch (sometimes people also call this a D-type latch). A
negative-enable (active-low) D latch can be built by inverting all the clock
polarities in Figure 2.17(a) (swap CLKN for CLKP and vice-versa).
2.5.2 Flip-Flop
Figure 2.18(a) shows a flip-flop constructed from two D latches: a master latch
(the first one) and a slave latch . This flip-flop contains a total of nine inverters
and four TGs, or 6.5 gates. In this flip-flop design the storage node S is buffered
and the clock-to-Q delay will be one inverter delay less than the clock-to-QN
delay.
FIGURE 2.18 CMOS flip-flop. (a) This negative-edgetriggered flip-flop
consists of two latches: master and slave. (b) While the clock is high, the master
latch is loaded. (c) As the clock goes low, the slave latch loads the value of the
master latch. (d) Waveforms illustrating the definition of the flip-flop setup time
t SU , hold time t H , and propagation delay from clock to Q, t PD .
In Figure 2.18(b) the clock input is high, the master latch is transparent, and node
M (for master) will follow the D input. Meanwhile the slave latch is disconnected
from the master latch and is storing whatever the previous value of Q was. As the
clock goes low (the negative edge) the slave latch is enabled and will update its
state (and the output Q) to the value of node M at the negative edge of the clock.
The slave latch will then keep this value of M at the output Q, despite any
changes at the D input while the clock is low (Figure 2.18c). When the clock
goes high again, the slave latch will store the captured value of M (and we are
back where we started our explanation).
The combination of the master and slave latches acts to capture or sample the D
input at the negative clock edge, the active clock edge . This type of flip-flop is a
negative-edgetriggered flip-flop and its behavior is quite different from a latch.
The behavior is shown on the IEEE symbol by using a triangular notch to
denote an edge-sensitive input. A bubble shows the input is sensitive to the
negative edge. To build a positive-edgetriggered flip-flop we invert the polarity
of all the clocksas we did for a latch.
The waveforms in Figure 2.18(d) show the operation of the flip-flop as we have
described it, and illustrate the definition of setup time ( t SU ), hold time ( t H ),
and clock-to-Q propagation delay ( t PD ). We must keep the data stable (a fixed
logic '1' or '0') for a time t SU prior to the active clock edge, and stable for a time t
H after the active clock edge (during the decision window shown).
In Figure 2.18(d) times are measured from the points at which the waveforms
cross 50 percent of V DD . We say the trip point is 50 percent or 0.5. Common
choices are 0.5 or 0.65/0.35 (a signal has to reach 0.65 V DD to be a '1', and reach
0.35 V DD to be a '0'), or 0.1/0.9 (there is no standard way to write a trip point).
Some vendors use different trip points for the input and output waveforms
(especially in I/O cells).
The flip-flop in Figure 2.18(a) is a D flip-flop and is by far the most widely used
type of flip-flop in ASIC design. There are other types of flip-flopsJ-K, T
(toggle), and S-R flip-flopsthat are provided in some ASIC cell libraries mainly
for compatibility with TTL design. Some people use the term register to mean an
array (more than one) of flip-flops or latches (on a data bus, for example), but
some people use register to mean a single flip-flop or a latch. This is confusing
since flip-flops and latches are quite different in their behavior. When I am
talking about logic cells, I use the term register to mean more than one flip-flop.
To add an asynchronous set (Q to '1') or asynchronous reset (Q to '0') to the
flip-flop of Figure 2.18(a), we replace one inverter in both the master and slave
latches with two-input NAND cells. Thus, for an active-low set, we replace I2
and I7 with two-input NAND cells, and, for an active-low reset, we replace I3
and I6. For both set and reset we replace all four inverters: I2, I3, I6, and I7.
Some TTL flip-flops have dominant reset or dominant set , but this is difficult
(and dangerous) to do in ASIC design. An input that forces Q to '1' is sometimes
also called preset . The IEEE logic symbols use 'P' to denote an input with a
presetting action. An input that forces Q to '0' is often also called clear . The
IEEE symbols use 'R' to denote an input with a resetting action.
2.5.3 Clocked Inverter
Figure 2.19 shows how we can derive the structure of a clocked inverter from the
series combination of an inverter and a TG. The arrows in Figure 2.19(b)
represent the flow of current when the inverter is charging ( I R ) or discharging (
I F ) a load capacitance through the TG. We can break the connection between the
inverter cells and use the circuit of Figure 2.19(c) without substantially affecting
the operation of the circuit. The symbol for the clocked inverter shown in
Figure 2.19(d) is common, but by no means a standard.
FIGURE 2.19 Clocked inverter. (a) An inverter plus transmission gate (TG).
(b) The current flow in the inverter and TG allows us to break the connection
between the transistors in the inverter. (c) Breaking the connection forms a
clocked inverter. (d) A common symbol.
We can use the clocked inverter to replace the inverterTG pairs in latches and
flip-flops. For example, we can replace one or both of the inverters I1 and I3
(together with the TGs that follow them) in Figure 2.17(a) by clocked inverters.
There is not much to choose between the different implementations in this case,
except that layout may be easier for the clocked inverter versions (since there is
one less connection to make).
More interesting is the flip-flop design: We can only replace inverters I1, I3, and
I7 (and the TGs that follow them) in Figure 2.18(a) by clocked inverters. We
cannot replace inverter I6 because it is not directly connected to a TG. We can
replace the TG attached to node M with a clocked inverter, and this will invert
the sense of the output Q, which thus becomes QN. Now the clock-to-Q delay
will be slower than clock-to-QN, since Q (which was QN) now comes one
inverter later than QN.
If we wish to build a flip-flop with a fast clock-to-QN delay it may be better to
build it using clocked inverters and use inverters with TGs for a flip-flop with a
fast clock-to-Q delay. In fact, since we do not always use both Q and QN outputs
of a flip-flop, some libraries include Q only or QN only flip-flops that are slightly
smaller than those with both polarity outputs. It is slightly easier to layout
clocked inverters than an inverter plus a TG, so flip-flops in commercial libraries
include a mixture of clocked-inverter and TG implementations.
2.6 Datapath Logic Cells
Suppose we wish to build an n -bit adder (that adds two n -bit numbers) and to exploit
the regularity of this function in the layout. We can do so using a datapath structure.
The following two functions, SUM and COUT, implement the sum and carry out for a
full adder ( FA ) with two data inputs (A, B) and a carry in, CIN:
SUM = A • B • CIN = SUM(A, B, CIN) = PARITY(A, B, CIN) , (2.38)
COUT = A · B + A · CIN + B · CIN = MAJ(A, B, CIN).
(2.39)
The sum uses the parity function ('1' if there are an odd numbers of '1's in the inputs).
The carry out, COUT, uses the 2-of-3 majority function ('1' if the majority of the inputs
are '1'). We can combine these two functions in a single FA logic cell, ADD(A[ i ], B[ i
], CIN, S[ i ], COUT), shown in Figure 2.20(a), where
S[ i ] = SUM (A[ i ], B[ i ], CIN) , (2.40)
COUT = MAJ (A[ i ], B[ i ], CIN) . (2.41)
Now we can build a 4-bit ripple-carry adder ( RCA ) by connecting four of these ADD
cells together as shown in Figure 2.20(b). The i th ADD cell is arranged with the
following: two bus inputs A[ i ], B[ i ]; one bus output S[ i ]; an input, CIN, that is the
carry in from stage ( i 1) below and is also passed up to the cell above as an output;
and an output, COUT, that is the carry out to stage ( i + 1) above. In the 4-bit adder
shown in Figure 2.20(b) we connect the carry input, CIN[0], to VSS and use COUT[3]
and COUT[2] to indicate arithmetic overflow (in Section 2.6.1 we shall see why we
may need both signals). Notice that we build the ADD cell so that COUT[2] is
available at the top of the datapath when we need it.
Figure 2.20(c) shows a layout of the ADD cell. The A inputs, B inputs, and S outputs
all use m1 interconnect running in the horizontal directionwe call these data signals.
Other signals can enter or exit from the top or bottom and run vertically across the
datapath in m2we call these control signals. We can also use m1 for control and m2 for
data, but we normally do not mix these approaches in the same structure. Control
signals are typically clocks and other signals common to elements. For example, in
Figure 2.20(c) the carry signals, CIN and COUT, run vertically in m2 between cells. To
build a 4-bit adder we stack four ADD cells creating the array structure shown in
Figure 2.20(d). In this case the A and B data bus inputs enter from the left and bus S,
the sum, exits at the right, but we can connect A, B, and S to either side if we want.
The layout of buswide logic that operates on data signals in this fashion is called a
datapath . The module ADD is a datapath cell or datapath element . Just as we do for
standard cells we make all the datapath cells in a library the same height so we can abut
other datapath cells on either side of the adder to create a more complex datapath.
When people talk about a datapath they always assume that it is oriented so that
increasing the size in bits makes the datapath grow in height, upwards in the vertical
direction, and adding different datapath elements to increase the function makes the
datapath grow in width, in the horizontal directionbut we can rotate and position a
completed datapath in any direction we want on a chip.
FIGURE 2.20 A datapath adder. (a) A full-adder (FA) cell with inputs (A and B), a
carry in, CIN, sum output, S, and carry out, COUT. (b) A 4-bit adder. (c) The layout,
using two-level metal, with data in m1 and control in m2. In this example the wiring is
completed outside the cell; it is also possible to design the datapath cells to contain the
wiring. Using three levels of metal, it is possible to wire over the top of the datapath
cells. (d) The datapath layout.
What is the difference between using a datapath, standard cells, or gate arrays? Cells
are placed together in rows on a CBIC or an MGA, but there is no generally no
regularity to the arrangement of the cells within the rowswe let software arrange the
cells and complete the interconnect. Datapath layout automatically takes care of most
of the interconnect between the cells with the following advantages:
● Regular layout produces predictable and equal delay for each bit.
● Interconnect between cells can be built into each cell.
There are some disadvantages of using a datapath:
● The overhead (buffering and routing the control signals, for example) can make a
narrow (small number of bits) datapath larger and slower than a standard-cell (or
even gate-array) implementation.
● Datapath cells have to be predesigned (otherwise we are using full-custom
design) for use in a wide range of datapath sizes. Datapath cell design can be
harder than designing gate-array macros or standard cells.
● Software to assemble a datapath is more complex and not as widely used as
software for assembling standard cells or gate arrays.
There are some newer standard-cell and gate-array tools that can take advantage of
regularity in a design and position cells carefully. The problem is in finding the
regularity if it is not specified. Using a datapath is one way to specify regularity to
ASIC design tools.
2.6.1 Datapath Elements
Figure 2.21 shows some typical datapath symbols for an adder (people rarely use the
IEEE standards in ASIC datapath libraries). I use heavy lines (they are 1.5 point wide)
with a stroke to denote a data bus (that flows in the horizontal direction in a datapath),
and regular lines (0.5 point) to denote the control signals (that flow vertically in a
datapath). At the risk of adding confusion where there is none, this stroke to indicate a
data bus has nothing to do with mixed-logic conventions. For a bus, A[31:0] denotes a
32-bit bus with A[31] as the leftmost or most-significant bit or MSB , and A[0] as the
least-significant bit or LSB . Sometimes we shall use A[MSB] or A[LSB] to refer to
these bits. Notice that if we have an n -bit bus and LSB = 0, then MSB = n 1. Also, for
example, A[4] is the fifth bit on the bus (from the LSB). We use a ' S ' or 'ADD' inside
the symbol to denote an adder instead of '+', so we can attach '' or '+/' to the inputs for
a subtracter or adder/subtracter.
FIGURE 2.21 Symbols for a datapath adder. (a) A data bus is shown by a heavy line
(1.5 point) and a bus symbol. If the bus is n -bits wide then MSB = n 1. (b) An
alternative symbol for an adder. (c) Control signals are shown as lightweight (0.5
point) lines.
Some schematic datapath symbols include only data signals and omit the control
signalsbut we must not forget them. In Figure 2.21, for example, we may need to
explicitly tie CIN[0] to VSS and use COUT[MSB] and COUT[MSB 1] to detect
overflow. Why might we need both of these control signals? Table 2.11 shows the
process of simple arithmetic for the different binary number representations, including
unsigned, signed magnitude, ones complement, and twos complement.
TABLE 2.11 Binary arithmetic.
Binary Number Representation
Signed
Ones
Operation
Unsigned
magnitude
complement
if positive
then MSB = 0 if negative then flip
no change
bits
else MSB = 1
3=
0011
0011
0011
3=
NA
1011
1100
zero =
0000
0000 or 1000 1111 or 0000
Twos
complement
if negative then {flip
bits; add 1}
0011
1101
0000
max.
1111 = 15
positive =
max.
0000= 0
negative =
addition =
S=A+B
= addend +
augend
S=A+B
SG(A) =
sign of A
addition
result:
OV =
overflow,
OR = out
of range
0111 = 7
0111 = 7
0111 = 7
1111 = 7
1000 = 7
1000 = 8
if SG(A) =
SG(B) then S S =
=A+B
A+B+
else { if B < A COUT[MSB]
then S = A B
else S = B
A}
S=A+B
COUT is carry out
if SG(A) =
OR =
COUT[MSB] SG(B) then OV =
OV =
OV =
COUT[MSB] XOR(COUT[MSB], XOR(COUT[MSB],
COUT[MSB1])
COUT[MSB 1])
COUT is
else OV = 0
carry out
(impossible)
if SG(A) =
SG(B) then
SG(S) =
SG(A)
SG(S) =
sign of S
NA
S=A+B
else { if B < A NA
then SG(S) =
SG(A)
NA
else SG(S) =
SG(B)}
subtraction
=
D=A B
D=A B
= minuend
SG(B) =
Z = B (negate);
NOT(SG(B));
D=A+Z
D=A+B
subtrahend
subtraction
result :
OR =
BOUT[MSB]
OV =
as in addition as in addition
overflow, BOUT is
OR = out borrow out
of range
Z = B (negate);
D=A+Z
as in addition
negation :
Z=A
(negate)
Z = A;
NA
Z = NOT(A)
SG(Z) =
NOT(SG(A))
Z = NOT(A) + 1
2.6.2 Adders
We can view addition in terms of generate , G[ i ], and propagate , P[ i ], signals.
method 1
G[i] = A[i] · B[i]
P[ i ] = A[ i ] • B[ i
C[ i ] = G[ i ] + P[ i ] · C[ i 1]
S[ i ] = P[ i ] • C[ i 1]
method 2
G[ i ] = A[ i ] · B[ i ]
P[ i ] = A[ i ] + B[ i ]
C[ i ] = G[ i ] + P[ i ] · C[ i 1]
S[ i ] = A[ i ] • B[ i ] • C[ i 1]
(2.42)
(2.43)
(2.44)
(2.45)
where C[ i ] is the carry-out signal from stage i , equal to the carry in of stage ( i + 1).
Thus, C[ i ] = COUT[ i ] = CIN[ i + 1]. We need to be careful because C[0] might
represent either the carry in or the carry out of the LSB stage. For an adder we set the
carry in to the first stage (stage zero), C[1] or CIN[0], to '0'. Some people use delete
(D) or kill (K) in various ways for the complements of G[i] and P[i], but unfortunately
others use C for COUT and D for CINso I avoid using any of these. Do not confuse the
two different methods (both of which are used) in Eqs. 2.422.45 when forming the
sum, since the propagate signal, P[ i ] , is different for each method.
Figure 2.22(a) shows a conventional RCA. The delay of an n -bit RCA is proportional
to n and is limited by the propagation of the carry signal through all of the stages. We
can reduce delay by using pairs of go-faster bubbles to change AND and OR gates to
fast two-input NAND gates as shown in Figure 2.22(a). Alternatively, we can write the
equations for the carry signal in two different ways:
either C[ i ] = A[ i ] · B[ i ] + P[ i ] · C[ i 1]
(2.46)
or
C[ i ] = (A[ i ] + B[ i ] ) · (P[ i ]' + C[ i 1]), (2.47)
where P[ i ]'= NOT(P[ i ]). Equations 2.46 and 2.47 allow us to build the carry chain
from two-input NAND gates, one per cell, using different logic in even and odd stages
(Figure 2.22b):
even stages
odd stages
C1[i]' = P[i ] · C3[i 1] · C4[i 1] C3[i]' = P[i ] · C1[i 1] · C2[i 1] (2.48)
C2[i] = A[i ] + B[i ]
C4[i]' = A[i ] · B[i ]
(2.49)
C[i] = C1[i ] · C2[i ]
C[i] = C3[i ] ' + C4[i ]'
(2.50)
(the carry inputs to stage zero are C3[1] = C4[1] = '0'). We can use the RCA of
Figure 2.22(b) in a datapath, with standard cells, or on a gate array.
Instead of propagating the carries through each stage of an RCA, Figure 2.23 shows a
different approach. A carry-save adder ( CSA ) cell CSA(A1[ i ], A2[ i ], A3[ i ], CIN,
S1[ i ], S2[ i ], COUT) has three outputs:
S1[ i ] = CIN ,
S2[ i ] = A1[ i ] • A2[ i ] • A3[ i ] = PARITY(A1[ i ], A2[ i ], A3[ i ]) ,
(2.51)
(2.52)
COUT = A1[ i ] · A2[ i ] + [(A1[ i ] + A2[ i ]) · A3[ i ]] = MAJ(A1[ i ], A2[ i ],
(2.53)
A3[ i ]) .
The inputs, A1, A2, and A3; and outputs, S1 and S2, are buses. The input, CIN, is the
carry from stage ( i 1). The carry in, CIN, is connected directly to the output bus S1
indicated by the schematic symbol (Figure 2.23a). We connect CIN[0] to VSS. The
output, COUT, is the carry out to stage ( i + 1).
A 4-bit CSA is shown in Figure 2.23(b). The arithmetic overflow signal for ones
complement or twos complement arithmetic, OV, is XOR(COUT[MSB], COUT[MSB
1]) as shown in Figure 2.23(c). In a CSA the carries are saved at each stage and
shifted left onto the bus S1. There is thus no carry propagation and the delay of a CSA
is constant. At the output of a CSA we still need to add the S1 bus (all the saved
carries) and the S2 bus (all the sums) to get an n -bit result using a final stage that is not
shown in Figure 2.23(c). We might regard the n -bit sum as being encoded in the two
buses, S1 and S2, in the form of the parity and majority functions.
We can use a CSA to add multiple inputsas an example, an adder with four 4-bit inputs
is shown in Figure 2.23(d). The last stage sums two input buses using a carry-propagate
adder ( CPA ). We have used an RCA as the CPA in Figure 2.23(d) and (e), but we can
use any type of adder. Notice in Figure 2.23(e) how the two CSA cells and the RCA
cell abut together horizontally to form a bit slice (or slice) and then the slices are
stacked vertically to form the datapath.
FIGURE 2.22 The carry-save adder (CSA). (a) A CSA cell. (b) A 4-bit CSA.
(c) Symbol for a CSA. (d) A four-input CSA. (e) The datapath for a four-input, 4-bit
adder using CSAs with a ripple-carry adder (RCA) as the final stage. (f) A pipelined
adder. (g) The datapath for the pipelined version showing the pipeline registers as well
as the clock control lines that use m2.
We can register the CSA stages by adding vectors of flip-flops as shown in
Figure 2.23(f). This reduces the adder delay to that of the slowest adder stage, usually
the CPA. By using registers between stages of combinational logic we use pipelining to
increase the speed and pay a price of increased area (for the registers) and introduce
latency . It takes a few clock cycles (the latency, equal to n clock cycles for an n -stage
pipeline) to fill the pipeline, but once it is filled, the answers emerge every clock cycle.
Ferris wheels work much the same way. When the fair opens it takes a while (latency)
to fill the wheel, but once it is full the people can get on and off every few seconds.
(We can also pipeline the RCA of Figure 2.20. We add i registers on the A and B
inputs before ADD[ i ] and add ( n i ) registers after the output S[ i ], with a single
register before each C[ i ].)
The problem with an RCA is that every stage has to wait to make its carry decision, C[
i ], until the previous stage has calculated C[ i 1]. If we examine the propagate signals
we can bypass this critical path. Thus, for example, to bypass the carries for bits 47
(stages 58) of an adder we can compute BYPASS = P[4].P[5].P[6].P[7] and then use a
MUX as follows:
C[7] = (G[7] + P[7] · C[6]) · BYPASS' + C[3] · BYPASS . (2.54)
Adders based on this principle are called carry-bypass adders ( CBA ) [Sato et al.,
1992]. Large, custom adders employ Manchester-carry chains to compute the carries
and the bypass operation using TGs or just pass transistors [Weste and Eshraghian,
1993, pp. 530531]. These types of carry chains may be part of a predesigned ASIC
adder cell, but are not used by ASIC designers.
Instead of checking the propagate signals we can check the inputs. For example we can
compute SKIP = (A[ i 1] • B[ i 1]) + (A[ i ] • B[ i ] ) and then use a 2:1 MUX to
select C[ i ]. Thus,
CSKIP[ i ] = (G[ i ] + P[ i ] · C[ i 1]) · SKIP' + C[ i 2] · SKIP . (2.55)
This is a carry-skip adder [Keutzer, Malik, and Saldanha, 1991; Lehman, 1961].
Carry-bypass and carry-skip adders may include redundant logic (since the carry is
computed in two different wayswe just take the first signal to arrive). We must be
careful that the redundant logic is not optimized away during logic synthesis.
If we evaluate Eq. 2.44 recursively for i = 1, we get the following:
C[1] = G[1] + P[1] · C[0]
= G[1] + P[1] · (G[0] + P[1] · C[1])
= G[1] + P[1] · G[0] .
(2.56)
This result means that we can look ahead by two stages and calculate the carry into
the third stage (bit 2), which is C[1], using only the first-stage inputs (to calculate G[0])
and the second-stage inputs. This is a carry-lookahead adder ( CLA ) [MacSorley,
1961]. If we continue expanding Eq. 2.44, we find:
C[2] = G[2] + P[2] · G[1] + P[2] · P[1] · G[0] ,
C[3] = G[3] + P[2] · G[2] + P[2] · P[1] · G[1] + P[3] · P[2] · P[1] · G[0] . (2.57)
As we look ahead further these equations become more complex, take longer to
calculate, and the logic becomes less regular when implemented using cells with a
limited number of inputs. Datapath layout must fit in a bit slice, so the physical and
logical structure of each bit must be similar. In a standard cell or gate array we are not
so concerned about a regular physical structure, but a regular logical structure
simplifies design. The BrentKung adder reduces the delay and increases the regularity
of the carry-lookahead scheme [Brent and Kung, 1982]. Figure 2.24(a) shows a regular
4-bit CLA, using the carry-lookahead generator cell (CLG) shown in Figure 2.24(b).
FIGURE 2.23 The BrentKung carry-lookahead adder (CLA). (a) Carry generation in a
4-bit CLA. (b) A cell to generate the lookahead terms, C[0]C[3]. (c) Cells L1, L2, and
L3 are rearranged into a tree that has less delay. Cell L4 is added to calculate C[2] that
is lost in the translation. (d) and (e) Simplified representations of parts a and c. (f) The
lookahead logic for an 8-bit adder. The inputs, 07, are the propagate and carry terms
formed from the inputs to the adder. (g) An 8-bit BrentKung CLA. The outputs of the
lookahead logic are the carry bits that (together with the inputs) form the sum. One
advantage of this adder is that delays from the inputs to the outputs are more nearly
equal than in other adders. This tends to reduce the number of unwanted and
unnecessary switching events and thus reduces power dissipation.
In a carry-select adder we duplicate two small adders (usually 4-bit or 8-bit adders
often CLAs) for the cases CIN = '0' and CIN = '1' and then use a MUX to select the
case that we needwasteful, but fast [Bedrij, 1962]. A carry-select adder is often used as
the fast adder in a datapath library because its layout is regular.
We can use the carry-select, carry-bypass, and carry-skip architectures to split a 12-bit
adder, for example, into three blocks. The delay of the adder is then partly dependent
on the delays of the MUX between each block. Suppose the delay due to 1-bit in an
adder block (we shall call this a bit delay) is approximately equal to the MUX delay. In
this case may be faster to make the blocks 3, 4, and 5-bits long instead of being equal in
size. Now the delays into the final MUX are equal3 bit-delays plus 2 MUX delays for
the carry signal from bits 06 and 5 bit-delays for the carry from bits 711. Adjusting
the block size reduces the delay of large adders (more than 16 bits).
We can extend the idea behind a carry-select adder as follows. Suppose we have an n
-bit adder that generates two sums: One sum assumes a carry-in condition of '0', the
other sum assumes a carry-in condition of '1'. We can split this n -bit adder into an i -bit
adder for the i LSBs and an ( n i )-bit adder for the n i MSBs. Both of the smaller
adders generate two conditional sums as well as true and complement carry signals.
The two (true and complement) carry signals from the LSB adder are used to select
between the two ( n i + 1)-bit conditional sums from the MSB adder using 2( n i + 1)
two-input MUXes. This is a conditional-sum adder (also often abbreviated to CSA)
[Sklansky, 1960]. We can recursively apply this technique. For example, we can split a
16-bit adder using i = 8 and n = 8; then we can split one or both 8bit adders againand
so on.
Figure 2.25 shows the simplest form of an n -bit conditional-sum adder that uses n
single-bit conditional adders, H (each with four outputs: two conditional sums, true
carry, and complement carry), together with a tree of 2:1 MUXes (Qi_j). The
conditional-sum adder is usually the fastest of all the adders we have discussed (it is the
fastest when logic cell delay increases with the number of inputsthis is true for all
ASICs except FPGAs).
FIGURE 2.24 The conditional-sum adder. (a) A 1-bit conditional adder that calculates
the sum and carry out assuming the carry in is either '1' or '0'. (b) The multiplexer that
selects between sums and carries. (c) A 4-bit conditional-sum adder with carry input,
C[0].
2.6.3 A Simple Example
How do we make and use datapath elements? What does a design look like? We may
use predesigned cells from a library or build the elements ourselves from logic cells
using a schematic or a design language. Table 2.12 shows an 8-bit conditional-sum
adder intended for an FPGA. This Verilog implementation uses the same structure as
Figure 2.25, but the equations are collapsed to use four or five variables. A basic logic
cell in certain Xilinx FPGAs, for example, can implement two equations of the same
four variables or one equation with five variables. The equations shown in Table 2.12
requires three levels of FPGA logic cells (so, for example, if each FPGA logic cell has
a 5 ns delay, the 8-bit conditional-sum adder delay is 15 ns).
TABLE 2.12 An 8-bit conditional-sum adder (the notation is described in Figure 2.25).
module m8bitCSum (C0, a, b, s, C8); // Verilog conditional-sum adder for an FPGA
input [7:0] C0, a, b; output [7:0] s; output C8;
wire
A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0,S8,S7,S6,S5,S4,S3,S2,S1,S0;
wire C0, C2, C4_2_0, C4_2_1, S5_4_0, S5_4_1, C6, C6_4_0, C6_4_1, C8;
assign {A7,A6,A5,A4,A3,A2,A1,A0} = a; assign {B7,B6,B5,B4,B3,B2,B1,B0} = b;
assign s = { S7,S6,S5,S4,S3,S2,S1,S0 };
assign S0 = A0^B0^C0 ; // start of level 1: & = AND, ^ = XOR, | = OR, ! = NOT
assign S1 = A1^B1^(A0&B0|(A0|B0)&C0) ;
assign C2 = A1&B1|(A1|B1)&(A0&B0|(A0|B0)&C0) ;
assign C4_2_0 = A3&B3|(A3|B3)&(A2&B2) ; assign C4_2_1 =
A3&B3|(A3|B3)&(A2|B2) ;
assign S5_4_0 = A5^B5^(A4&B4) ; assign S5_4_1 = A5^B5^(A4|B4) ;
assign C6_4_0 = A5&B5|(A5|B5)&(A4&B4) ; assign C6_4_1 =
A5&B5|(A5|B5)&(A4|B4) ;
assign S2 = A2^B2^C2 ; // start of level 2
assign S3 = A3^B3^(A2&B2|(A2|B2)&C2) ;
assign S4 = A4^B4^(C4_2_0|C4_2_1&C2) ;
assign S5 = S5_4_0& !(C4_2_0|C4_2_1&C2)|S5_4_1&(C4_2_0|C4_2_1&C2) ;
assign C6 = C6_4_0|C6_4_1&(C4_2_0|C4_2_1&C2) ;
assign S6 = A6^B6^C6 ; // start of level 3
assign S7 = A7^B7^(A6&B6|(A6|B6)&C6) ;
assign C8 = A7&B7|(A7|B7s)&(A6&B6|(A6|B6)&C6) ;
endmodule
Figure 2.26 shows the normalized delay and area figures for a set of predesigned
datapath adders. The data in Figure 2.26 is from a series of ASIC datapath cell libraries
(Compass Passport) that may be synthesized together with test vectors and simulation
models. We can combine the different adder techniques, but the adders then lose
regularity and become less suited to a datapath implementation.
FIGURE 2.25 Datapath adders. This data is from a series of submicron datapath
libraries. (a) Delay normalized to a two-input NAND logic cell delay (approximately
equal to 250 ps in a 0.5 m m process). For example, a 64-bit ripple-carry adder (RCA)
has a delay of approximately 30 ns in a 0.5 m m process. The spread in delay is due to
variation in delays between different inputs and outputs. An n -bit RCA has a delay
proportional to n . The delay of an n -bit carry-select adder is approximately
proportional to log 2 n . The carry-save adder delay is constant (but requires a
carry-propagate adder to complete an addition). (b) In a datapath library the area of all
adders are proportional to the bit size.
There are other adders that are not used in datapaths, but are occasionally useful in
ASIC design. A serial adder is smaller but slower than the parallel adders we have
described [Denyer and Renshaw, 1985]. The carry-completion adder is a variable delay
adder and rarely used in synchronous designs [Sklansky, 1960].
2.6.4 Multipliers
Figure 2.27 shows a symmetric 6-bit array multiplier (an n -bit multiplier multiplies
two n -bit numbers; we shall use n -bit by m -bit multiplier if the lengths are different).
Adders a0f0 may be eliminated, which then eliminates adders a1a6, leaving an
asymmetric CSA array of 30 (5 ¥ 6) adders (including one half adder). An n -bit array
multiplier has a delay proportional to n plus the delay of the CPA (adders b6f6 in
Figure 2.27). There are two items we can attack to improve the performance of a
multiplier: the number of partial products and the addition of the partial products.
FIGURE 2.26 Multiplication. A 6-bit array multiplier using a final carry-propagate
adder (full-adder cells a6f6, a ripple-carry adder). Apart from the generation of the
summands this multiplier uses the same structure as the carry-save adder of
Figure 2.23(d).
Suppose we wish to multiply 15 (the multiplicand ) by 19 (the multiplier ) mentally. It
is easier to calculate 15 ¥ 20 and subtract 15. In effect we complete the multiplication
as 15 ¥ (20 1) and we could write this as 15 ¥ 2 1 , with the overbar representing a
minus sign. Now suppose we wish to multiply an 8-bit binary number, A, by B =
00010111 (decimal 16 + 4 + 2 + 1 = 23). It is easier to multiply A by the canonical
signed-digit vector ( CSD vector ) D = 0010 1 001 (decimal 32 8 + 1 = 23) since this
requires only three add or subtract operations (and a subtraction is as easy as an
addition). We say B has a weight of 4 and D has a weight of 3. By using D instead of B
we have reduced the number of partial products by 1 (= 4 3).
We can recode (or encode) any binary number, B, as a CSD vector, D, as follows
(canonical means there is only one CSD vector for any number):
D i = B i + C i 2C
i+1
, (2.58)
where C i + 1 is the carry from the sum of B i + 1 + B i + C i (we start with C 0 = 0).
As another example, if B = 011 (B 2 = 0, B 1 = 1, B 0 = 1; decimal 3), then, using
Eq. 2.58,
D 0 = B 0 + C 0 2C
1
=1+0 2=1,
D 1 = B 1 + C 1 2C
2
= 1 + 1 2 = 0,
D 2 = B 2 + C 2 2C
3
= 0 + 1 0 = 1, (2.59)
so that D = 10 1 (decimal 4 1 = 3). CSD vectors are useful to represent fixed
coefficients in digital filters, for example.
We can recode using a radix other than 2. Suppose B is an ( n + 1)-digit twos
complement number,
B=B0+B12+B222+...+Bi2i+...+Bn
1
2n
1
B
n
2 n . (2.60)
We can rewrite the expression for B using the following sleight-of-hand:
B = B 0 + (B 0 B 1 )2 + . . . + (B i 1 B i )2 i + . . . + B n
2n
= (2B 1 + B 0 )2 0 + (2B 3 + B 2 + B 1 )2 2 + . . .
2B B =
+ (2B i + B i
1
+Bi
2
)2 i
+Bi
1
+Bi
2
)2 n
+ (2B
n
1
+ (2B
1
i+2
1
2n
1
B
n
+ B i + 1 + B i )2 i + 1 + . . .
.
(2.61)
This is very useful. Consider B = 101001 (decimal 9 32 = 23, n = 5),
B = 101001
= (2B 1 + B 0 )2 0 + (2B
((2 ¥ 0) + 1)2
0
3
+ B 2 + B 1 )2 2 + (2B
+ ((2 ¥ 1) + 0 + 0)2
2
5
+ B 4 + B 3 )2 4
+ ((2 ¥ 1) + 0 + 1)2
4
.
(2.62)
Equation 2.61 tells us how to encode B as a radix-4 signed digit, E = 12 1 (decimal 16
8 + 1 = 23). To multiply by B encoded as E we only have to perform a multiplication
by 2 (a shift) and three add/subtract operations.
Using Eq. 2.61 we can encode any number by taking groups of three bits at a time and
calculating
= 2B i + B i 1 + B i 2 ,
E j + 1 = 2B i + 2 + B i + 1 + B i , . . . , (2.63)
Ej
where each 3-bit group overlaps by one bit. We pad B with a zero, B n . . . B 1 B 0 0, to
match the first term in Eq. 2.61. If B has an odd number of bits, then we extend the
sign: B n B n . . . B 1 B 0 0. For example, B = 01011 (eleven), encodes to E = 1 11 (16
4 1); and B = 101 is E = 1 1. This is called Booth encoding and reduces the number of
partial products by a factor of two and thus considerably reduces the area as well as
increasing the speed of our multiplier [Booth, 1951].
Next we turn our attention to improving the speed of addition in the CSA array.
Figure 2.28(a) shows a section of the 6-bit array multiplier from Figure 2.27. We can
collapse the chain of adders a0f5 (5 adder delays) to the Wallace tree consisting of
adders 5.15.4 (4 adder delays) shown in Figure 2.28(b).
FIGURE 2.27 Tree-based multiplication. (a) The portion of Figure 2.27 that calculates
the sum bit, P 5 , using a chain of adders (cells a0f5). (b) We can collapse this chain to
a Wallace tree (cells 5.15.5). (c) The stages of multiplication.
Figure 2.28(c) pictorially represents multiplication as a sort of golf course. Each link
corresponds to an adder. The holes or dots are the outputs of one stage (and the inputs
of the next). At each stage we have the following three choices: (1) sum three outputs
using a full adder (denoted by a box enclosing three dots); (2) sum two outputs using a
half adder (a box with two dots); (3) pass the outputs directly to the next stage. The two
outputs of an adder are joined by a diagonal line (full adders use black dots, half adders
white dots). The object of the game is to choose (1), (2), or (3) at each stage to
maximize the performance of the multiplier. In tree-based multipliers there are two
ways to do thisworking forward and working backward.
In a Wallace-tree multiplier we work forward from the multiplier inputs, compressing
the number of signals to be added at each stage [Wallace, 1960]. We can view an FA as
a 3:2 compressor or (3, 2) counter it counts the number of '1's on the inputs. Thus, for
example, an input of '101' (two '1's) results in an output '10' (2). A half adder is a (2, 2)
counter . To form P 5 in Figure 2.29 we must add 6 summands (S 05 , S 14 , S 23 , S 32 ,
S 41 , and S 50 ) and 4 carries from the P 4 column. We add these in stages 17,
compressing from 6:3:2:2:3:1:1. Notice that we wait until stage 5 to add the last carry
from column P 4 , and this means we expand (rather than compress) the number of
signals (from 2 to 3) between stages 3 and 5. The maximum delay through the CSA
array of Figure 2.29 is 6 adder delays. To this we must add the delay of the 4-bit (9
inputs) CPA (stage 7). There are 26 adders (6 half adders) plus the 4 adders in the CPA.
FIGURE 2.28 A 6-bit Wallace-tree multiplier. The carry-save adder (CSA) requires 26
adders (cells 126, six are half adders). The final carry-propagate adder (CPA) consists
of 4 adder cells (2730). The delay of the CSA is 6 adders. The delay of the CPA is 4
adders.
In a Dadda multiplier (Figure 2.30) we work backward from the final product [Dadda,
1965]. Each stage has a maximum of 2, 3, 4, 6, 9, 13, 19, . . . outputs (each successive
stage is 3/2 times largerrounded down to an integer). Thus, for example, in
Figure 2.28(d) we require 3 stages (with 3 adder delaysplus the delay of a 10-bit output
CPA) for a 6-bit Dadda multiplier. There are 19 adders (4 half adders) in the CSA plus
the 10 adders (2 half adders) in the CPA. A Dadda multiplier is usually faster and
smaller than a Wallace-tree multiplier.
FIGURE 2.29 The 6-bit Dadda multiplier. The carry-save adder (CSA) requires 20
adders (cells 120, four are half adders). The carry-propagate adder (CPA, cells 2130)
is a ripple-carry adder (RCA). The CSA is smaller (20 versus 26 adders), faster (3
adder delays versus 6 adder delays), and more regular than the Wallace-tree CSA of
Figure 2.29. The overall speed of this implementation is approximately the same as the
Wallace-tree multiplier of Figure 2.29; however, the speed may be increased by
substituting a faster CPA.
In general, the number of stages and thus delay (in units of an FA delayexcluding the
CPA) for an n -bit tree-based multiplier using (3, 2) counters is
log 1.5 n = log 10 n /log 10 1.5 = log 10 n /0.176 . (2.64)
Figure 2.31(a) shows how the partial-product array is constructed in a conventional
4-bit multiplier. The FerrariStefanelli multiplier (Figure 2.31b) nests multipliersthe
2-bit submultipliers reduce the number of partial products [Ferrari and Stefanelli,
1969].
FIGURE 2.30 FerrariStefanelli multiplier. (a) A conventional 4-bit array multiplier
using AND gates to calculate the summands with (2, 2) and (3, 2) counters to sum the
partial products. (b) A 4-bit FerrariStefanelli multiplier using 2-bit submultipliers to
construct the partial product array. (c) A circuit implementation for an inverting 2-bit
submultiplier.
There are several issues in deciding between parallel multiplier architectures:
1. Since it is easier to fold triangles rather than trapezoids into squares, a
Wallace-tree multiplier is more suited to full-custom layout, but is slightly larger,
than a Dadda multiplierboth are less regular than an array multiplier. For
cell-based ASICs, a Dadda multiplier is smaller than a Wallace-tree multiplier.
2. The overall multiplier speed does depend on the size and architecture of the final
CPA, but this may be optimized independently of the CSA array. This means a
Dadda multiplier is always at least as fast as the Wallace-tree version.
3. The low-order bits of any parallel multiplier settle first and can be added in the
CPA before the remaining bits settle. This allows multiplication and the final
addition to be overlapped in time.
4. Any of the parallel multiplier architectures may be pipelined. We may also use a
variably pipelined approach that tailors the register locations to the size of the
multiplier.
5. Using (4, 2), (5, 3), (7, 3), or (15, 4) counters increases the stage compression
and permits the size of the stages to be tuned. Some ASIC cell libraries contain a
(7, 3) countera 2-bit full-adder . A (15, 4) counter is a 3-bit full adder. There is a
trade-off in using these counters between the speed and size of the logic cells and
the delay as well as area of the interconnect.
6. Power dissipation is reduced by the tree-based structures. The simplified
carry-save logic produces fewer signal transitions and the tree structures produce
fewer glitches than a chain.
7. None of the multiplier structures we have discussed take into account the
possibility of staggered arrival times for different bits of the multiplicand or the
multiplier. Optimization then requires a logic-synthesis tool.
2.6.5 Other Arithmetic Systems
There are other schemes for addition and multiplication that are useful in special
circumstances. Addition of numbers using redundant binary encoding avoids carry
propagation and is thus potentially very fast. Table 2.13 shows the rules for addition
using an intermediate carry and sum that are added without the need for carry. For
example,
binary
decimal redundant binary CSD vector
1010111
87
10101001
10 1 0 1 00 1
+ 1100101 101
+ 11100111
+ 01100101
01001110
= 11 00 1 100
1 1 00010 1
11000000
= 10111100 = 188 1 1 1000 1 00
10 1 00 1 100
addend
augend
intermediate sum
intermediate carry
sum
TABLE 2.13 Redundant binary addition.
Intermediate Intermediate
A[ i ] B[ i ] A[ i 1]
1
1
1
0
B[ i 1]
sum
x
x
0
A[i 1]=0/1 and B[i 1]=0/1 1
carry
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
A[i 1]= 1 or B[i 1]= 1
x
x
x
x
x
x
A[i 1]=0/1 and B[i 1]=0/1
A[i 1]= 1 or B[i 1]= 1
x
x
1
0
0
0
1
1
0
1
0
0
0
1
0
1
The redundant binary representation is not unique. We can represent 101 (decimal), for
example, by 1100101 (binary and CSD vector) or 1 1 100111. As another example, 188
(decimal) can be represented by 10111100 (binary), 1 1 1000 1 00, 10 1 00 1 100, or 10
1 000 1 00 (CSD vector). Redundant binary addition of binary, redundant binary, or
CSD vectors does not result in a unique sum, and addition of two CSD vectors does not
result in a CSD vector. Each n -bit redundant binary number requires a rather wasteful
2 n -bit binary number for storage. Thus 10 1 is represented as 010010, for example
(using sign magnitude). The other disadvantage of redundant binary arithmetic is the
need to convert to and from binary representation.
Table 2.14 shows the (5, 3) residue number system . As an example, 11 (decimal) is
represented as [1, 2] residue (5, 3) since 11R 5 = 11 mod 5 = 1 and 11R 3 = 11 mod 3 =
2. The size of this system is thus 3 ¥ 5 = 15. We add, subtract, or multiply residue
numbers using the modulus of each bit positionwithout any carry. Thus:
4
[4, 1] 12 [2, 0] 3
[3, 0]
+ 7 + [2, 1] 4 - [4, 1] ¥ 4 ¥ [4, 1]
= 11 = [1, 2] = 8 = [3, 2] = 12 = [2, 0]
TABLE 2.14 The 5, 3 residue number system.
n residue 5 residue 3 n residue 5 residue 3 n residue 5 residue 3
00
0
50
2
10 0
1
11
1
61
0
11 1
2
22
2
72
1
12 2
0
33
0
83
2
13 3
1
44
1
94
0
14 4
2
The choice of moduli determines the system size and the computing complexity. The
most useful choices are relative primes (such as 3 and 5). With p prime, numbers of the
form 2 p and 2 p 1 are particularly useful (2 p 1 are Mersennes numbers ) [Waser and
Flynn, 1982].
2.6.6 Other Datapath Operators
Figure 2.32 shows symbols for some other datapath elements. The combinational
datapath cells, NAND, NOR, and so on, and sequential datapath cells (flip-flops and
latches) have standard-cell equivalents and function identically. I use a bold outline (1
point) for datapath cells instead of the regular (0.5 point) line I use for scalar symbols.
We call a set of identical cells a vector of datapath elements in the same way that a bold
symbol, A , represents a vector and A represents a scalar.
FIGURE 2.31 Symbols for datapath elements. (a) An array or vector of flip-flops (a
register). (b) A two-input NAND cell with databus inputs. (c) A two-input NAND cell
with a control input. (d) A buswide MUX. (e) An incrementer/decrementer. (f) An
all-zeros detector. (g) An all-ones detector. (h) An adder/subtracter.
A subtracter is similar to an adder, except in a full subtracter we have a borrow-in
signal, BIN; a borrow-out signal, BOUT; and a difference signal, DIFF:
DIFF
= A • NOT(B) • NOT( BIN)
SUM(A, NOT(B), NOT(BIN))
(2.65)
NOT(BOUT) = A · NOT(B) + A · NOT(BIN) + NOT(B) · NOT(BIN)
MAJ(NOT(A), B, NOT(BIN))
(2.66)
These equations are the same as those for the FA (Eqs. 2.38 and 2.39) except that the B
input is inverted and the sense of the carry chain is inverted. To build a subtracter that
calculates (A B) we invert the entire B input bus and connect the BIN[0] input to
VDD (not to VSS as we did for CIN[0] in an adder). As an example, to subtract B =
'0011' from A = '1001' we calculate '1001' + '1100' + '1' = '0110'. As with an adder, the
true overflow is XOR(BOUT[MSB], BOUT[MSB 1]).
We can build a ripple-borrow subtracter (a type of borrow-propagate subtracter), a
borrow-save subtracter, and a borrow-select subtracter in the same way we built these
adder architectures. An adder/subtracter has a control signal that gates the A input with
an exclusive-OR cell (forming a programmable inversion) to switch between an adder
or subtracter. Some adder/subtracters gate both inputs to allow us to compute (A B).
We must be careful to connect the input to the LSB of the carry chain (CIN[0] or
BIN[0]) when changing between addition (connect to VSS) and subtraction (connect to
VDD).
A barrel shifter rotates or shifts an input bus by a specified amount. For example if we
have an eight-input barrel shifter with input '1111 0000' and we specify a shift of
'0001 0000' (3, coded by bit position) the right-shifted 8-bit output is '0001 1110'. A
barrel shifter may rotate left or right (or switch between the two under a separate
control). A barrel shifter may also have an output width that is smaller than the input.
To use a simple example, we may have an 8-bit input and a 4-bit output. This situation
is equivalent to having a barrel shifter with two 4-bit inputs and a 4-bit output. Barrel
shifters are used extensively in floating-point arithmetic to align (we call this normalize
and denormalize ) floating-point numbers (with sign, exponent, and mantissa).
A leading-one detector is used with a normalizing (left-shift) barrel shifter to align
mantissas in floating-point numbers. The input is an n -bit bus A, the output is an n -bit
bus, S, with a single '1' in the bit position corresponding to the most significant '1' in
the input. Thus, for example, if the input is A = '0000 0101' the leading-one detector
output is S = '0000 0100', indicating the leading one in A is in bit position 2 (bit 7 is the
MSB, bit zero is the LSB). If we feed the output, S, of the leading-one detector to the
shift select input of a normalizing (left-shift) barrel shifter, the shifter will normalize
the input A. In our example, with an input of A = '0000 0101', and a left-shift of S =
'0000 0100', the barrel shifter will shift A left by five bits and the output of the shifter is
Z = '1010 0000'. Now that Z is aligned (with the MSB equal to '1') we can multiply Z
with another normalized number.
The output of a priority encoder is the binary-encoded position of the leading one in an
input. For example, with an input A = '0000 0101' the leading 1 is in bit position 3
(MSB is bit position 7) so the output of a 4-bit priority encoder would be Z = '0011' (3).
In some cell libraries the encoding is reversed so that the MSB has an output code of
zero, in this case Z = '0101' (5). This second, reversed, encoding scheme is useful in
floating-point arithmetic. If A is a mantissa and we normalize A to '1010 0000' we have
to subtract 5 from the exponent, this exponent correction is equal to the output of the
priority encoder.
An accumulator is an adder/subtracter and a register. Sometimes these are combined
with a multiplier to form a multiplieraccumulator ( MAC ). An incrementer adds 1 to
the input bus, Z = A + 1, so we can use this function, together with a register, to negate
a twos complement number for example. The implementation is Z[ i ] = XOR(A[ i ],
CIN[ i ]), and COUT[ i ] = AND(A[ i ], CIN[ i ]). The carry-in control input, CIN[0],
thus acts as an enable: If it is set to '0' the output is the same as the input.
The implementation of arithmetic cells is often a little more complicated than we have
explained. CMOS logic is naturally inverting, so that it is faster to implement an
incrementer as
Z[ i (even)] = XOR(A[ i ], CIN[ i ]) and COUT[ i (even)] = NAND(A[ i ], CIN[ i ]).
This inverts COUT, so that in the following stage we must invert it again. If we push an
inverting bubble to the input CIN we find that:
Z[ i (odd)] = XNOR(A[ i ], CIN[ i ]) and COUT[ i (even)] = NOR(NOT(A[ i ]), CIN[ i
]).
In many datapath implementations all odd-bit cells operate on inverted carry signals,
and thus the odd-bit and even-bit datapath elements are different. In fact, all the adder
and subtracter datapath elements we have described may use this technique. Normally
this is completely hidden from the designer in the datapath assembly and any output
control signals are inverted, if necessary, by inserting buffers.
A decrementer subtracts 1 from the input bus, the logical implementation is Z[ i ] =
XOR(A[ i ], CIN[ i ]) and COUT[ i ] = AND(NOT(A[ i ]), CIN[ i ]). The
implementation may invert the odd carry signals, with CIN[0] again acting as an
enable.
An incrementer/decrementer has a second control input that gates the input, inverting
the input to the carry chain. This has the effect of selecting either the increment or
decrement function.
Using the all-zeros detectors and all-ones detectors , remember that, for a 4-bit number,
for example, zero in ones complement arithmetic is '1111' or '0000', and that zero in
signed magnitude arithmetic is '1000' or '0000'.
A register file (or scratchpad memory) is a bank of flip-flops arranged across the bus;
sometimes these have the option of multiple ports (multiport register files) for read and
write. Normally these register files are the densest logic and hardest to fit in a datapath.
For large register files it may be more appropriate to use a multiport memory. We can
add control logic to a register file to create a first-in first-out register ( FIFO ), or last-in
first-out register ( LIFO ).
In Section 2.5 we saw that the standard-cell version and gate-array macro version of the
sequential cells (latches and flip-flops) each contain their own clock buffers. The
reason for this is that (without intelligent placement software) we do not know where a
standard cell or a gate-array macro will be placed on a chip. We also have no idea of
the condition of the clock signal coming into a sequential cell. The ability to place the
clock buffers outside the sequential cells in a datapath gives us more flexibility and
saves space. For example, we can place the clock buffers for all the clocked elements at
the top of the datapath (together with the buffers for the control signals) and river route
(in river routing the interconnect lines all flow in the same direction on the same layer)
the connections to the clock lines. This saves space and allows us to guarantee the
clock skew and timing. It may mean, however, that there is a fixed overhead associated
with a datapath. For example, it might make no sense to build a 4-bit datapath if the
clock and control buffers take up twice the space of the datapath logic. Some tools
allow us to design logic using a portable netlist . After we complete the design we can
decide whether to implement the portable netlist in a datapath, standard cells, or even a
gate array, based on area, speed, or power considerations.
2.7 I/O Cells
Figure 2.33 shows a three-state bidirectional output buffer (Tri-State ® is a
registered trademark of National Semiconductor). When the output enable (OE)
signal is high, the circuit functions as a noninverting buffer driving the value of
DATAin onto the I/O pad. When OE is low, the output transistors or drivers , M1
and M2, are disconnected. This allows multiple drivers to be connected on a bus.
It is up to the designer to make sure that a bus never has two driversa problem
known as contention .
In order to prevent the problem opposite to contentiona bus floating to an
intermediate voltage when there are no bus driverswe can use a bus keeper or
bus-hold cell (TI calls this Bus-Friendly logic). A bus keeper normally acts like
two weak (low drive-strength) cross-coupled inverters that act as a latch to retain
the last logic state on the bus, but the latch is weak enough that it may be driven
easily to the opposite state. Even though bus keepers act like latches, and will
simulate like latches, they should not be used as latches, since their drive strength
is weak.
Transistors M1 and M2 in Figure 2.33 have to drive large off-chip loads. If we
wish to change the voltage on a C = 200 pF load by 5 V in 5 ns (a slew rate of 1
Vns 1 ) we will require a current in the output transistors of I DS = C (d V /d t ) =
(200 ¥ 10 12 ) (5/5 ¥ 10 9 ) = 0.2 A or 200 mA.
Such large currents flowing in the output transistors must also flow in the power
supply bus and can cause problems. There is always some inductance in series
with the power supply, between the point at which the supply enters the ASIC
package and reaches the power bus on the chip. The inductance is due to the bond
wire, lead frame, and package pin. If we have a power-supply inductance of 2 nH
and a current changing from zero to 1 A (32 I/O cells on a bus switching at 30
mA each) in 5 ns, we will have a voltage spike on the power supply (called
power-supply bounce ) of L (d I /d t ) = (2 ¥ 10 9 )(1/(5 ¥ 10 9 )) = 0.4 V.
We do several things to alleviate this problem: We can limit the number of
simultaneously switching outputs (SSOs), we can limit the number of I/O drivers
that can be attached to any one VDD and GND pad, and we can design the output
buffer to limit the slew rate of the output (we call these slew-rate limited I/O
pads). Quiet-I/O cells also use two separate power supplies and two sets of I/O
drivers: an AC supply (clean or quiet supply) with small AC drivers for the I/O
circuits that start and stop the output slewing at the beginning and end of a output
transition, and a DC supply (noisy or dirty supply) for the transistors that handle
large currents as they slew the output.
The three-state buffer allows us to employ the same pad for input and output
bidirectional I/O . When we want to use the pad as an input, we set OE low and
take the data from DATAin. Of course, it is not necessary to have all these
features on every pad: We can build output-only or input-only pads.
FIGURE 2.32 A three-state bidirectional
output buffer. When the output enable,
OE, is '1' the output section is enabled
and drives the I/O pad. When OE is '0'
the output buffer is placed in a
high-impedance state.
We can also use many of these output cell features for input cells that have to
drive large on-chip loads (a clock pad cell, for example). Some gate arrays
simply turn an output buffer around to drive a grid of interconnect that supplies a
clock signal internally. With a typical interconnect capacitance of 0.2pFcm 1 , a
grid of 100 cm (consisting of 10 by 10 lines running all the way across a 1 cm
chip) presents a load of 20 pF to the clock buffer.
Some libraries include I/O cells that have passive pull-ups or pull-downs
(resistors) instead of the transistors, M1 and M2 (the resistors are normally still
constructed from transistors with long gate lengths). We can also omit one of the
driver transistors, M1 or M2, to form open-drain outputs that require an external
pull-up or pull-down. We can design the output driver to produce TTL output
levels rather than CMOS logic levels. We may also add input hysteresis (using a
Schmitt trigger) to the input buffer, I1 in Figure 2.33, to accept input data signals
that contain glitches (from bouncing switch contacts, for example) or that are
slow rising. The input buffer can also include a level shifter to accept TTL input
levels and shift the input signal to CMOS levels.
The gate oxide in CMOS transistors is extremely thin (100 Å or less). This leaves
the gate oxide of the I/O cell input transistors susceptible to breakdown from
static electricity ( electrostatic discharge , or ESD ). ESD arises when we or
machines handle the package leads (like the shock I sometimes get when I touch
a doorknob after walking across the carpet at work). Sometimes this problem is
called electrical overstress (EOS) since most ESD-related failures are caused not
by gate-oxide breakdown, but by the thermal stress (melting) that occurs when
the n -channel transistor in an output driver overheats (melts) due to the large
current that can flow in the drain diffusion connected to a pad during an ESD
event.
To protect the I/O cells from ESD, the input pads are normally tied to device
structures that clamp the input voltage to below the gate breakdown voltage
(which can be as low as 10 V with a 100 Å gate oxide). Some I/O cells use
transistors with a special ESD implant that increases breakdown voltage and
provides protection. I/O driver transistors can also use elongated drain structures
(ladder structures) and large drain-to-gate spacing to help limit current, but in a
salicide process that lowers the drain resistance this is difficult. One solution is to
mask the I/O cells during the salicide step. Another solution is to use pnpn and
npnp diffusion structures called silicon-controlled rectifiers (SCRs) to clamp
voltages and divert current to protect the I/O circuits from ESD.
There are several ways to model the capability of an I/O cell to withstand EOS.
The human-body model ( HBM ) represents ESD by a 100 pF capacitor
discharging through a 1.5 k W resistor (this is an International Electrotechnical
Committee, IEC, specification). Typical voltages generated by the human body
are in the range of 24 kV, and we often see an I/O pad cell rated by the voltage it
can withstand using the HBM. The machine model ( MM ) represents an ESD
event generated by automated machine handlers. Typical MM parameters use a
200 pF capacitor (typically charged to 200 V) discharged through a 25 W
resistor, corresponding to a peak initial current of nearly 10 A. The charge-device
model ( CDM , also called device chargedischarge) represents the problem when
an IC package is charged, in a shipping tube for example, and then grounded. If
the maximum charge on a package is 3 nC (a typical measured figure) and the
package capacitance to ground is 1.5 pF, we can simulate this event by charging a
1.5 pF capacitor to 2 kV and discharging it through a 1 W resistor.
If the diffusion structures in the I/O cells are not designed with care, it is possible
to construct an SCR structure unwittingly, and instead of protecting the
transistors the SCR can enter a mode where it is latched on and conducting large
enough currents to destroy the chip. This failure mode is called latch-up .
Latch-up can occur if the pn -diodes on a chip become forward-biased and inject
minority carriers (electrons in p -type material, holes in n -type material) into the
substrate. The sourcesubstrate and drainsubstrate diodes can become
forward-biased due to power-supply bounce or output undershoot (the cell
outputs fall below V SS ) or overshoot (outputs rise to greater than V DD ) for
example. These injected minority carriers can travel fairly large distances and
interact with nearby transistors causing latch-up. I/O cells normally surround the
I/O transistors with guard rings (a continuous ring of n -diffusion in an n -well
connected to VDD, and a ring of p -diffusion in a p -well connected to VSS) to
collect these minority carriers. This is a problem that can also occur in the logic
core and this is one reason that we normally include substrate and well
connections to the power supplies in every cell.
2.8 Cell Compilers
The process of hand crafting circuits and layout for a full-custom IC is a tedious,
time-consuming, and error-prone task. There are two types of automated layout
assembly tools, often known as a silicon compilers . The first type produces a
specific kind of circuit, a RAM compiler or multiplier compiler , for example.
The second type of compiler is more flexible, usually providing a programming
language that assembles or tiles layout from an input command file, but this is
full-custom IC design.
We can build a register file from latches or flip-flops, but, at 4.56.5 gates (1826
transistors) per bit, this is an expensive way to build memory. Dynamic RAM
(DRAM) can use a cell with only one transistor, storing charge on a capacitor
that has to be periodically refreshed as the charge leaks away. ASIC RAM is
invariably static (SRAM), so we do not need to refresh the bits. When we refer to
RAM in an ASIC environment we almost always mean SRAM. Most ASIC
RAMs use a six-transistor cell (four transistors to form two cross-coupled
inverters that form the storage loop, and two more transistors to allow us to read
from and write to the cell). RAM compilers are available that produce single-port
RAM (a single shared bus for read and write) as well as dual-port RAMs , and
multiport RAMs . In a multi-port RAM the compiler may or may not handle the
problem of address contention (attempts to read and write to the same RAM
address simultaneously). RAM can be asynchronous (the read and write cycles
are triggered by control and/or address transitions asynchronous to a clock) or
synchronous (using the system clock).
In addition to producing layout we also need a model compiler so that we can
verify the circuit at the behavioral level, and we need a netlist from a netlist
compiler so that we can simulate the circuit and verify that it works correctly at
the structural level. Silicon compilers are thus complex pieces of software. We
assume that a silicon compiler will produce working silicon even if every
configuration has not been tested. This is still ASIC design, but now we are
relying on the fact that the tool works correctly and therefore the compiled blocks
are correct by construction .
2.9 Summary
The most important concepts that we covered in this chapter are the following:
● The use of transistors as switches
● The difference between flip-flop and a latch
● The meaning of setup time and hold time
● Pipelines and latency
● The difference between datapath, standard-cell, and gate-array logic cells
● Strong and weak logic levels
● Pushing bubbles
● Ratio of logic
● Resistance per square of layers and their relative values in CMOS
● Design rules and l
2.10 Problems
* = Difficult,** = Very difficult, *** = Extremely difficult
2.1 (Switches, 20 min.) (a) Draw a circuit schematic for a two-way light switch:
flipping the switch at the top or bottom of the stairs reverses the state of two light
bulbs, one at the top and one at the bottom of the stairs. Your schematic should
show and label all the cables, switches, and bulbs. (b) Repeat the problem for
three switches and one light in a warehouse.
2.2 (Logic, 10 min.) The queen wished to choose her successor wisely. She
blindfolded and then placed a crown on each of her three children, explaining that
there were three red and two blue crowns, and they must deduce the color of their
own crown. With blindfolds removed the children could see the two other
crowns, but not their own. After a while Anne said: My crown is red. How did
she know?
2.3 (Minus signs, 20 min.) The channel charge in an n -channel transistor is
negative. (a) Should there not be a minus sign in Eq. 2.5 to account for this? (b)
If so, then where in the derivation of Section 2.1 does the minus sign disappear
to arrive at Eq. 2.9 for the current in an n -channel transistor? (c) The equations
for the current in a p -channel transistor (Eq. 2.15) have the opposite sign to those
for an n -channel transistor. Where in the derivation in Section 2.1 does the extra
minus sign arise?
FIGURE 2.33 Transistor characteristics for a
0.3 m m process (Problem 2.4).
2.4 (Transistor curves, 20 min.) Figure 2.34 shows the measured I DS V DS
characteristics for a 20/20 n -channel transistor in a 0.3 m m (effective gate
length) process from an ASIC foundry. Derive as much information as you can
from this figure.
2.5 (Body effect, 20 min). The equations for the drainsource current (2.9, 2.12,
and 2.15) do not contain V SB , the source voltage with respect to the bulk,
because we assumed that it was zero. This is not true for the n -channel transistor
whose drain is connected to the output in a two-input NAND gate, for example.
A reverse substrate bias (or back-gate bias; V SB > 0 for an n -channel transistor)
makes the bulk act like a second gate (the back gate) and modifies an n -channel
transistor threshold voltage as follows:
V tn = V t0 n + g [ ( f
0
+ V SB ) f
0]
, (2.67)
where V t 0 n is measured with V SB = 0 V; f 0 is called the surface potential; and
g (gamma) is the body-effect coefficient (back-gate bias coefficient),
g = (2q e
Si
N A )/C ox . (2.68)
There are several alternative names and symbols for f 0 (phi, a positive quantity
for an n -channel transistor, typically between 0.60.7 V)you may also see f b (for
bulk potential) or 2 f F (twice the Fermi potential, a negative quantity). In
Eq. 2.68, e Si = e 0 e r = 1.053 ¥ 10 10 Fm 1 is the permittivity of silicon (the
permittivity of a vacuum e 0 = 8.85 ¥ 10 12 Fm 1 and the relative permittivity of
silicon is e r = 11.7); N A is the acceptor doping concentration in the bulk (for p
-type substrate or well N D for the donor concentration in an n -type substrate or
well); and C ox is the gate capacitance per unit area given by
C ox = e ox /T ox . (2.69)
●
a. Calculate the theoretical value of g for N A = 10 16 cm 3 , T ox = 100 Å.
●
●
b. Calculate and plot V t n for V SB ranging from 0 V to 5 V in increments
of 1 V assuming values of g = 0.5 V 0.5 , f 0 = 0.6 V, and V t0 n = 0.5 V
obtained from transistor characteristics.
c. Fit a linear approximation to V t n .
●
d. Recognizing V SB £ 0 V, rewrite Eq. 2.67 for a p -channel device.
●
e. (Harder) What effect does the back-gate bias effect have on CMOS logic
circuits?
Answer: (a) 0.17 V 0.5 (b) 0.50 1.3 V.
2.6 (Sizing layout, 10 min.) Stating clearly whatever assumptions you make and
describing the tools and methods you use, estimate the size (in l ) of the standard
cell shown in Figure 1.3. Estimate the size of each of the transistors, giving their
channel lengths and widths (stating clearly which is which).
2.7 (CMOS process) (20 min.) Table 2.15 shows the major steps involved in a
typical deep submicron CMOS process. There are approximately 100 major steps
in the process.
● a. If each major step has a yield of 0.9, what is the overall process yield?
●
●
●
●
●
b. If the process yield is 90 % (not uncommon), what is the average yield
at each major step?
c. If each of the major steps in Table 2.15 consists of an average of five
other microtasks, what is the average yield of each of the 500 microtasks.
d. Suppose, for example, an operator loads and unloads a furnace five
times a day as a microtask, how many days must the operator work without
making a mistake to achieve this microtask yield?
e. Does this seem reasonable? What is wrong with our model?
f. (**60 min.) Draw the process cross-section showing, in particular, the
poly, FOX, gate oxide, IMOs and metal layers. You may have to make
some assumptions about the meanings and functions of the various steps
and layers. Assume all layers are deposited on top of each other according
to the thicknesses shown (do not attempt to correct for the silicon
consumed during oxidationeven if you understand what this means). The
abbreviations in Table 2.15 are as follows: dep. = deposition; LPCVD =
low-pressure chemical vapor deposition (for growing oxide and poly);
LDD = lightly doped drain (a way to improve transistor characteristics);
SOG = silicon overglass (a deposited quartz to help with step coverage
between metal layers).
TABLE 2.15 CMOS process steps (Problem 2.7). 1
Step
Depth Step
Depth Step
1 substrate
32 resist strip
63 m1 mask
2 oxide 1 dep. 500 33 WSi anneal
64 m1 etch
nitride 1
3
1500 34 nLDD mask
65 resist strip
dep.
base oxide
4 n-well mask
35 nLDD implant
66
dep.
5 n-well etch
36 resist strip
67 SOG coat1/2
n-well
SOG
6
37 pLDD mask
68
implant
cure/etch
cap oxide
7 resist strip
38 pLDD implant
69
dep.
blocking
8
2000 39 resist strip
70 via1 mask
oxide dep.
nitride 1
spacer oxide
9
40
3000 71 via1 etch
strip
dep.
p-well
10
41 WSi anneal
72 resist strip
implant
11 p-well drive
42 SD oxide dep 200 73 TiW dep.
active oxide
AlCu/TiW
12
250 43 n+ mask
74
dep.
dep.
Depth
6000
3000
4000
4000
2500
2000
4000
nitride 2
1500 44 n+ implant
dep.
14 active mask
45 resist strip
15 active etch
46 ESD mask
13
16 resist strip
47 ESD implant
17 field mask
48 resist strip
18 field implant
49 p+ mask
19 resist strip
50 p+ implant
field oxide
dep.
nitride 2
21
strip
sacrificial
22
oxide dep.
Vt adjust
23
implant
gate oxide
24
dep.
LPCVD
25
poly dep.
26 deglaze
27 WSi dep.
LPCVD
28
oxide dep.
29 poly mask
30 oxide etch
polycide
31
etch
20
75 m2 mask
76 m2 etch
77 resist strip
base oxide
78
dep.
79 SOG coat 1/2
SOG
80
cure/etch
cap oxide
81
dep.
5000 51 resist strip
80
LPCVD oxide
dep.
BPSG
54
dep./densify
53
57 resist strip
1500 58 Pt dep.
750
83 via2 etch
4000 85 TiW dep.
86
4000
2500
AlCu/TiW
dep.
2000
4000
2500 87 m3 mask
200
59 Pt sinter
60 Pt strip
61 TiW dep.
4000
1500 84 resist strip
55 contact mask
1500 56 contact etch
3000
82 via2 mask
52 implant anneal
300
6000
88 m3 etch
89 resist strip
90 oxide dep.
92 nitride dep.
2000 93 pad mask
4000
10,000
62 AlCu/TiW dep. 4000 94 pad etch
Answer: (a) Zero. (b) 0.999. (c) 0.9998. (d) 3 years.
2.8 (Stipple patterns, 30 min.)
● a. Check the stipple patterns in Figure 2.9. Using ruled paper draw 8-by-8
stipple patterns for all the combinations of layers shown.
● b. Repeat part a for Figure 2.10.
2.9 (Select, 20 min.) Can you draw a design-rule correct (according to the design
rules in Tables 2.72.9) layout with a piece of select that has a minimum width of
2 l (rule 4.4)?
2.10 (*Inverter layout, 60 min.) Using 1/4-inch ruled paper (or similar) draw a
minimum-size inverter (W/L = 1 for both p -channel and n -channel transistors).
Use a scale of one square to 2 l and the design rules in Table 2.7Table 2.9. Do
not use m2 or m3only m1. Draw the nwell, pwell, ndiff, and pdiff layers, but not
the implant layers or the active layer. Include connections to the input, output,
VDD, and VSS in m1. There must be at least one well connection to each well ( n
-well to VDD, and p -well to VSS). Minimize the size of your cell BB. Draw the
BB outline and write its size in l 2 on your drawing. Use green diagonal stripes
for ndiff, brown diagonal stripes for pdiff, red diagonal stripes for poly, blue
diagonal stripes for m1, solid black for contact). Include a key on your drawing,
and clearly label the input, output, VDD, and VSS contacts.
2.11 (*AOI221 Layout, 120 min.) Layout the AOI221 shown in Figure 2.13 with
the design rules of Tables 2.72.9 and using Figure 1.3 as a guide. Label clearly
the m1 corresponding to the inputs, output, VDD bus, and GND (VSS) bus.
Remember to include substrate contacts. What is the size of your BB in l 2 ?
2.12 (Resistance, 20 min.)
● a. Using the values for sheet resistance shown in Table 2.3, calculate the
resistance of a 200 l long (in the direction of current flow) by 3 l wide
piece of each of the layers.
● b. Estimate the resistance of an 8-inch, 10 W cm, p -type, <100> wafer,
measured (i) from edge to edge across a diameter and (ii) from face center
to the face center on the other side.
2.13 (*Layout graphics, 120 min.) Write a tutorial for capturing layout. As an
example:
To capture EPSF (encapsulated PostScript format) from Tanner Researchs
L-Edit for documentation, Macintosh version... Create a black-and-white
technology file, use Setup, Layers..., in L-Edit. The method described here does
not work well for grayscale or color. Use File, Print..., Destination check button
File to print from L-Edit to an EPS (encapsulated PostScript) file. After you
choose Save, a dialog box appears. Select Format: EPS Enhanced Mac Preview,
ASCII, Level 1 Compatible, Font Inclusion: None. Save the file. Switch to
Frame. Create an Anchored Frame. Use File, Import, File... to bring up a dialog
box. Check button Copy into Document, select Format: EPSF. Import the EPS
file that will appear as a page image. Grab the graphic inside the Anchored
Frame and move the page image around. There will be a footer with text on the
page image that you may want to hide by using the Anchored Frame edges to
crop the image.
Your instructions should be precise, concise, assume nothing, and use the names
of menu items, buttons and so on exactly as they appear to the user. Most of the
layout figures in this book were created using L-Edit running on a Macintosh,
with labels added in FrameMaker. Most of the layouts use the Compass layout
editor.
2.14 (Transistor resistance, 20 min.) Calculate I DS and the resistance (the DC
value V DS / I DS as well as the AC value V DS / I DS as appropriate) of
long-channel transistors with the following parameters, under the specified
conditions. In each case state whether the transistor is in the saturation region,
linear region, or off:
(i) n -channel: V t n = 0.5 V, b n = 40 m AV 2 :
V GS = 3.3V: a. V DS = 3.3 V b. V DS = 0.0 V c. V GS = 0.0 V, V DS = 3.3 V
(ii) p -channel: V t p = 0.6 V, b
p
= 20 m AV 2 :
V GS = 0.0 V: a. V DS = 0.0 V b. V DS = 5.0 V c. V
GS
= 5.0 V, V
DS
= 5.0 V
2.15 (Circuit theory, 15 min.) You accidentally created the inverter shown in
Figure 2.35 on a full-custom ASIC currently being fabricated. Will it work? Your
manager wants a yes or no answer. Your group is a little more understanding:
You are to make a presentation to them to explain the problems ahead. Prepare
two foils as well as a one page list of alternatives and recommendations.
FIGURE 2.34 A CMOS inverter with n -channel and p
-channel transistors swapped (Problem 2.15).
2.16 (Mask resolution, 10 min.) People use LaserWriters to make printed-circuit
boards all the time.
● a. Do you think it is possible to make an IC mask using a 600 dpi (dots per
inch) LaserWriter and a transparency?
● b. What would l be?
● c. (Harder) See if you can use a microscope to look at the dot and the
rectangular bars (serifs) of a letter 'i' from the output of a LaserWriter on
paper (most are 300 dpi or 600 dpi). Estimate l . What is causing the
problem? Why is there no rush to generate 1200 dpi LaserWriters for
paper? Put a page of this textbook under the microscope: can you see the
difference? What are the similar problems printing patterns on a wafer?
2.17 (Lambda, 10 min.) Estimate l
● a. for your TV screen,
● b. for your computer monitor,
● c. (harder) a photograph.
2.18 (Pass-transistor logic, 10 min.)
●
a. In Figure 2.36 suppose we set A = B = C = D = '1', what is the value of
F?
b. What is the logic strength of the signal at F?
c. If V DD = 5 V and V t n = 0.6 V, what would the voltage at the source
and drain terminals of M1, M2, and M3 be?
d. Will this circuit still work if V DD = 3 V?
●
e. At what point does it stop working?
●
●
●
FIGURE 2.35
FIGURE 2.36 A pass transistor chain (Problem
2.18).
2.19 (Transistor parameters, 20 min.) Calculate the (a) electron and (b) hole
mobility for the transistor parameters given in Section 2.1 if k ' n = 80 mA V 2
and k ' p = 40 mA V 2 .
Answer: (a) 0.023 m 2 V 1 s 1 .
2.20 (Quantum behavior, 10 min.) The average thermal energy of an electron is
approximately kT , where k = 1.38 ¥ 10 23 JK 1 is Boltzmanns constant and T is
the absolute temperature in kelvin.
●
●
●
●
a. The kinetic energy of an electron is (1/2) m v 2 , where v is due to
random thermal motion, and m = 9.11 ¥ 10 31 kg is the rest mass. What is
v at 300 K?
b. The electron wavelength l = h / p , where h = 6.62 ¥ 1034 Js is the
Planck constant, and p = m v is the electron momentum. What is l at 25
C?
c. Compare the thermal velocity with the saturation velocity.
d. Compare the electron wavelength with the MOS channel length and
with the gate-oxide thickness in a 0.25 m m process and a 0.1 m m process.
2.21 (Gallium arsenide, 5 min.) The electron mobility in GaAs is about 8500 cm 2
V 1 s 1 ; the hole mobility is about 400 cm 2 V 1 s 1 . If we could make
complementary n -channel and p -channel GaAs transistors (the same way that
we do in a CMOS process) what would the ratio of a GaAs inverter be to equalize
rise and fall times? About how much faster would you expect GaAs transistors to
be than silicon for the same transistor sizes?
2.22 (Margaret of Anjou, 5 min.)
● a. Why is it ones complement but twos complement?
● b. Why Queens University, Belfast but Queens College, Cambridge?
2.23 (Logic cell equations, 5 min.) Show that Eq. 2.31, 2.36, and 2.37 are correct.
2.24 (Carry-lookahead equations, 10 min.)
● a. Derive the carry-lookahead equations for i = 8. Write them in the same
form as Eq. 2.56.
● b. Derive the equations for the BrentKung structure for i = 8.
2.25 (OAI cells, 20 min.) Draw a circuit schematic, including transistor sizes, for
(a) an OAI321 cell, (b) an AOI321 cell. (c) Which do you think will be larger?
2.26 (**Making stipple patterns) Construct a set of black-and-white, transparent,
8-by-8 stipple patterns for a CMOS process in which we draw both well layers,
the active layer, poly, and both diffusion implant layers separately. Consider only
the layers up to m1 (but include m1 and the contact layer). One useful tool is the
Apple Macintosh Control Panel, 'General Controls,' that changes the Mac desktop
pattern.
● a. (60 min.) Create a set of patterns with which you can detect any errors
(for example, n -well and p -well overlap, or n -implant and p -implant
overlap).
● b. (60 min.+) Using a layout of an inverter as an example, find a set of
patterns that allows you to trace transistors and connections (a very
qualitative goal).
● c. (Days+) Find a set of grayscale stipple patterns that allow you to
produce layouts that look nice in a report (much, much harder than it
sounds).
2.27 (AOI and OAI cells, 10 min.). Draw the circuit schematics for an AOI22 and
an OAI22 cell. Clearly label each transistor as on or off for each cell for an input
vector of (A1, A2, B1, B2) = (0101).
2.28 (Flip-flops and latches, 10 min.) In no more than 20 words describe the
difference between a flip-flop and a latch.
2.29 (**An old argument) Should setup and hold times appear under maximum,
minimum, or typical in a data sheet? (From Peter Alfke.)
2.30 (***Setup, 20 min.) There is no such thing as a setup and hold time, just
two setup timesfor a '1' and for a '0'. Comment. (From Clemenz Portmann.)
2.31 (Subtracter, 20 min.) Show that you can rewrite the equations for a full
subtracter (Eqs. 2.652.66) to be the same as a full adderexcept that A is inverted
in the borrow out equation, as follows:
DIFF = A • B • BIN
SUM(A, B, BIN) ,
(2.70)
BOUT = NOT(A) · B + NOT(A) · BIN + B · BIN
MAJ(NOT(A), B, CIN) .
(2.71)
Explain very carefully why we need to connect BIN[0] to VSS. Show that for a
subtracter implemented by inverting the B input of an adder and setting CIN[0] =
'1', the true overflow for ones complement or twos complement representations
is XOR(CIN[MSB], CIN[MSB 1]). Does this hold for the above subtracter?
2.32 (Complex CMOS cells) Logic synthesis has completely changed the nature
of combinational logic design. Synthesis tools like to see a huge selection of cells
from which to choose in order to optimize speed or area.
● a. (20 min.) How many AOI nnnn cells are there, if the maximum value of
n = 4?
● b. (30 min.) Consider cells of the form AOI nnnn where n can be negative
indicating a set of inputs are inverted. Thus, an AOI-22 (where the hyphen
'-' indicates the following input is inverted) is a NOR(NOR(A, B), AND(C,
D)), for example. How many logically different cells of the AOI xxxx
family are there if x can be '-2', '-1', '1', or '2' with no more than four
inputs? Remember the AOI family includes OAI, AO, and OA cells as
well as just AOI. List them using an extension to the notation for a cell
with mixed-sign inputs: for example, an AO(1-1)1 cell is
NOT(NOR(AND(A, NOT(B)), C)). Hint: Be very careful because some
cells with negative inputs are logically equivalent to others with positive
inputs.
● c. (10 min.) If we include NAND and NOR cells with inverting inputs in a
library, how many different cells in the NAND family are there with four
or fewer inputs (the NAND family includes NOR, AND, and OR cells)?
● d. (30 min.) How many cells in the AOI and NAND families are there with
four inputs or less that use fewer than eight transistors? Include cells that
are logically equivalent but have different physical implementations. For
example, a NAND1-1 cell, requiring six transistors, is logically equivalent
to an OR1-1 cell that requires eight transistors. The OR1-1 implementation
may be useful because the output inverter can easily be sized to produce an
OR1-1 cell with higher drive.
● e. (**60 min.) How many cells are there with fewer than four inputs that
do not fit into the AOI or NAND families? Hint: There is an inverter, a
buffer, a half-adder, and the three-input majority function, for example.
● f. (***) Recommend a better, user-friendly, naming system (which is also
CAD tool compatible) for combinational cells.
2.33 (**Design rules, 60 min.) A typical set of deep submicron CMOS design
rules is shown in Table 2.16. Design rules are often confusing and use the
following buzz-words, perhaps to prevent others from understanding them.
● The end cap is the extension of poly gate beyond the active or diffusion.
● Overlap . Normally one material is completely contained within the other,
overlap is then the amount of the surround.
● Extension refers to the extension of diffusion beyond the poly gate.
●
●
●
●
●
●
●
●
●
Same (in a spacing rule) means the space to the same type of diffusion or
implant.
Opposite refers to the space to the opposite type of diffusion or implant.
A dogbone is the area surrounding a contact. Often the spacing to a
dogbone contact is allowed be slightly less than to an isolated line.
Field is the area outside the active regions. The field oxide (sandwiched
between the diffusion layers and the poly or m1 layers) is thicker than the
gate oxide and separates transistors.
Exact refers to contacts that are all the same size to simplify fabrication.
A butting contact consists of two adjacent diffusions of the opposite type
(connected with metal). This occurs when a well contact is placed next to a
source contact.
Fat metal . Some design rules use different spacing for metal lines that are
wider than a certain amount.
a. Draw a copy of the MOSIS rules as shown in Figure 2.11, but using the
rule numbers and values in microns and l from Table 2.16.
b. How compatible are the two sets of rules?
TABLE 2.16 ASIC design rules (Problem 2.33). Absolute values in
microns are given for l = 0.2 m m.
mm l
Layer Rule
mm
l
Layer Rule 2
nwell N.1 width 2
10 implant I.1 width
0.6
3
N.2 sp.
1
5
I.2 sp. (same) 0.6
3
(same)
I.3 sp. to diff
diff D.1 width 0.5 2.5
0.55
2.75
(same)
D.2
I.4 sp. to
transistor 0.6 3
0
0
butting diff
width
D.3 sp.
0.6 3
I.4 ov. of diff 0.25
1.25
(same)
D.4 sp.
I.5 sp. to poly
0.8 4
0.5
2.5
(opposite)
on active
D.5 p+
I.6 sp.
(nwell) to 2.4 12
0.3
1.5
(opposite)
n+ (pwell)
I.7 sp. to
D.6 nwell
0.6 3
butting
0
0
ov. of n+
implant
D.7 nwell
C.1 size
0.6 3 contact
0.4
2
sp. to p+
(exact)
D.8
extension
over gate
D.9 nwell
ov. of p+
D.10 nwell
sp. to n+
poly P.1 width
P.2 gate
P.3 sp.
(over
active)
P.4 sp.
(over field)
P.5 short
sp.
(dogbone)
0.6 3
C.2 sp.
0.6
3
1.2 6
C.3 poly ov.
0.3
1.5
0.4 2
0.4 2
0.6 3
C.7 poly
0.5
contact to diff
0.5 2.5 m1
Mn.1 width
0.45 2.25
P.6 end cap 0.45 2.25
P.7 sp. to
diffusion
C.4 diff ov. (2
0.25/0.35 1.25/1.75
sides/others)
C.5 metal ov. 0.25
1.25
C.6 sp. to poly 0.3
1.5
1.2 6
0.2 1
2.5
0.6/0.7/1.0 3/3.5/4
+
Mn.2 sp. (fat
0.6/0.7/1.0 3/3.5/4
m2/m3 > 25 l is 5 l )
Mn.3 sp.
(dogbone)
Vn.1 size
v1
(exact)
+v2/v3 Vn.2 sp.
Vn.3 metal
ov.
0.5
2.5
0.4
2
0.8
4
0.25
1.25
2.34 (ESD, 10 min.)
● a. Explain carefully why a CMOS device can withstand a 2000 V ESD
event when the gate breakdown voltage is only 510 V, but that shorting a
device pin to a 10 V supply can destroy it.
● b. Explain why an electric shock from a 240 VAC supply can kill you, but
an 3000 VDC shock from a static charge (walking across a nylon carpet
and touching a metal doorknob) only gives you a surprise.
2.35 (*Stacks in CMOS cells, 60 min.)
● a. Given a CMOS cell of the form AOI ijk or OAI ijk ( i, j, k > 0) derive an
equation for the height (the number of transistors in series) and the width
(the number of transistor in parallel) of the n -channel and p -channel
stacks.
● b. Suppose we increase the number of indices to four, i.e. AOI ijkl . How
do your equations change?
● c. If the stack height cannot be greater than three, which three-index AOI
ijk and OAI ijk cells are illegal? Often limiting the stack height to three or
four is a design rule for radiation-hard librariesuseful for satellites.
2.36 (Duals, 20 min.) Draw the n -channel stack (including device sizes,
assuming a ratio of 2) that complements the p -channel stack shown in
Figure 2.37.
FIGURE 2.37 A p -channel stack using a bridge
device, E (Problem 2.36).
2.37 (***FPGA conditional-sum adder, days+) A Xilinx application-note (M.
Klein, Conditional sum adder adds 16 bits in 33 ns, Xilinx Application Brief,
Xilinx data book, 1992, p. 6-26) describes a 16-bit conditional-sum adder using
41 CLBs in three stages of addition; see also [Sklansky, 1960]. A Xilinx XC3000
or XC4000 CLB can perform any logic function of five variables, or two
functions of (the same) four variables. Can you find a solution with fewer CLBs
in three stages? Hint: R. P. Halverson of the University of Hawaii produced a
solution with 36 CLBs.
2.38 (Encoding, 10 min.) Booths algorithm was suggested by a shortcut used by
operators of decimal calculating machines that required turning a handle. To
multiply 5 by 23 you set the levers to 5 and turned the handle three times, change
gears and turn twice more.
● a. What is the equivalent of 1 423 4 3 ?
● b. How many turns do we save using the shortcut?
2.39 (CSD, 20 min.)
● a. Show how to convert 1010111 (decimal 87) to the CSD vector 10 1 0 1
00 1 .
● b. Convert 1000101 to the CSD vector.
● c. How do you know that 1 1 10011 1 (decimal 101) is not the CSD vector
representation of 1100101 (decimal 101)?
1. Depths of layers are in angstroms (negative values are etch depths). For
abbreviations used, see Problem 2.7.
2. sp. = space; ov. = overlap; same = same diffusion or implant type; opposite =
opposite implant or diffusion type;
diff = p+ or n+; p+ = p+ diffusion; n+ = n+ diffusion; implant = p+ or n+ implant
select.
2.11 Bibliography
The topics of this chapter are covered in more detail in Weste and Eshraghian
[1993]. The simulator SPICE was developed at UC Berkeley and now has many
commercial derivatives including Meta Softwares HSPICE and Microsims
PSpice. Mead [1989] gives a description of MOS transistor operation in the
subthreshold region of operation. Muller and Kamins provide an introduction to
device physics [1977 and 1986]. Sze [1988]; Chang and Sze [1996]; and
Campbell [1996] cover process technology in detail at an advanced level. Rabaey
[1996] describes full-custom CMOS datapath circuit design, Chandrakasan and
Brodersen [1995] describe low-power datapath design. Books by Brodersen
[1992] and Gajski [1988] cover silicon compilers. Mukherjee [1986] covers
CMOS process and fabrication issues at an introductory level. Texts on analog
ASIC design include Haskard and May [1988], and Trontelj [1989]. J. Y. Chen
[1990] and Uyemura [1992] provide an analysis of combinational and sequential
logic design. The book by Diaz [1995] contains hard to find material on I/O cell
design for ESD protection. The patent literature is the only source for often
proprietary high-speed and quiet I/O design. Wakerly [1994] and Katz [1994] are
basic references for CMOS logic design (including sequential logic and binary
arithmetic) though they emphasize PLDs rather than ASICs. Advanced material
on computer arithmetic can be found in books by Hwang [1979]; Waser and
Flynn [1982]; Cavanagh [1984]; and C. H. Chen [1992].
A large number of papers on digital arithmetic were published in the 1960s. In
ASIC design we work at the architectural level and not at the transistor level and
so this early work is useful. Many of these early papers appeared in the IRE
Transactions on Computers that changed to IRE Transactions on Electronic
Computers (ISSN 0367-7508, 196367) and then to the IEEE Transactions on
Computers (ISSN 0018-9340, 1967). A series of important papers on multipliers
appeared in Alta Frequenza (ISSN 0002-6557, 193289; ISSN 1120-1908, 1989)
[Dadda, 1965; Dadda and Ferrari, 1968]. Copies of these papers may be obtained
through interlibrary loans (in the United States from Texas A&M library, for
example). The two volumes by Swartzlander [1990] contain reprints of some of
these articles. Ranganathan [1993] contains reprints of more recent articles.
Papers on CMOS logic and arithmetic may be found in the reports of the
following conferences: Proceedings of the Symposium on Computer Arithmetic
(QA76.9.C62.S95a, ISSN 1063-6889), IEEE International Conference on
Computer Design (TK7888.4.I35a, ISSN 1063-6404), and the IEEE International
Solid-State Circuits Conference (TK7870.I58; ISSN 0074-8587, 1960-68; ISSN
0193-6530, 1969). Papers on arithmetic and algorithms that are more theoretical
in nature can be found in the Journal of the Association of Computing Machinery
. Online ACM journal articles can be found at http://www.acm.org .
2.12 References
Page numbers in brackets after a reference indicate its location in the chapter
body.
Bedrij, O. 1962. Carry select adder. IRE Transactions on Electronic Computers ,
vol. 11, pp. 340346. Original reference to carry-select adder. See also [Weste,
1993] p. 532. [p. 84]
Booth, A. 1951. A signed binary multiplication technique. Quarterly Journal of
Mechanics and Applied Mathematics, vol. 4, pt. 2, pp. 236240. Original
reference for the Booth-encoded multiplier. See also Swartzlander [1990] and
Weste [1993, pp. 547554]. [p. 91]
Brent, R., and H. T. Kung. 1982. A regular layout for parallel adders. IEEE
Transactions on Computers, vol. 31, no. 3, pp. 260264. Describes a regular
carry-lookahead adder. [p. 84]
Brodersen, R. (Ed.). 1992. Anatomy of a Silicon Compiler. Boston: Kluwer, 362
p. ISBN 0-7923-9249-3. TK7874.A59.
Campbell, S. 1996. The Science and Engineering of Microelectronic Fabrication.
New York: Oxford University Press, 536 p. ISBN 0-19-510508-7.
TK7871.85.C25. [p. 116]
Cavanagh, J. J. F. 1984. Digital Computer Arithmetic Design and
Implementation . New York: McGraw-Hill, 468 p. QA76.9.C62.C38. ISBN
0070102821.
Chandrakasan A. P., and R. Brodersen. 1995. Low Power Digital CMOS Design .
Boston: Kluwer, 424 p. ISBN 0-7923-9576-X. TK7871.99.M44C43.
Chang, C. Y., and S. M. Sze. 1996. ULSI Technology. New York: McGraw-Hill,
726 p. ISBN 0070630623.
Chen, C. H. (Ed.). 1992. Computer Engineering Handbook. New York:
McGraw-Hill. ISBN 0-07-010924-9. TK7888.3.C652. Chapter 4, Computer
arithmetic, by E. E. Swartzlander, pp. 20, contains descriptions of adder,
multiplier, and divider architectures.
Chen, J. Y. 1990. CMOS Devices and Technology for VLSI. Englewood Cliffs,
NJ: Prentice-Hall, 348 p. ISBN 0-13-138082-6. TK7874.C523.
Dadda, L. 1965. Some schemes for parallel multipliers. Alta Frequenza , vol.
34, pp. 349356. The original reference to the Dadda multiplier. This paper
contains some errors in the diagrams for the multipliers; some remain in the
reprint in Swartzlander [1990, vol. 1]. See also sequel papers: L. Dadda and D.
Ferrari, Digital multipliers: a unified approach, Alta Frequenza, vol. 37, pp.
10791086, 1968; and L. Dadda, On parallel digital multipliers, Alta Frequenza,
vol. 45, pp. 574580, 1976. [p. 92]
Denyer, P. B., and D. Renshaw. 1985. VLSI Signal Processing: A Bit-Serial
Approach. Reading, MA: Addison-Wesley, 312 p. ISBN 0201144042.
TK7874.D46. See also P. B. Denyer and S. G. Smith, Serial-Data Computation.
Boston: Kluwer, 1988, 239 p. ISBN 089838253X. TK7874.S623. [p. 88]
Diaz, C. H., et al. 1995. Modeling of Electrical Overstress in Integrated Circuits.
Norwell, MA: Kluwer Academic, 148 p. ISBN 0-7923-9505-0. TK7874.D498.
Includes 101 references. Introduction to ESD problems and models.
Ferrari, D., and R. Stefanelli. 1969. Some new schemes for parallel multipliers.
Alta Frequenza, vol. 38, pp. 843852. The original reference for the Ferrari
Stefanelli multiplier. Describes the use of 2-bit and 3-bit submultipliers to
generate the product array. Contains tables showing the number of stages and
delay for different configurations. [p. 93]
Gajski, D. D. (Ed.). 1988. Silicon Compilation. Reading, MA: Addison-Wesley,
450 p. ISBN 0-201-109915-2. TK7874.S52.
Goldberg, D. 1990. Computer arithmetic. In D. A. Patterson and J. L. Hennessy,
Computer Architecture: A Quantitative Approach. San Mateo, CA: Morgan
Kaufmann, 2nd ed., 1995. QA76.9.A73. P377. ISBN 1-55860-329-8. See also the
first edition of this book (1990).
Haskard, M. R., and I. C. May. 1988. Analog VLSI Design: nMOS and CMOS.
Englewood Cliffs, NJ: Prentice-Hall, 243 p. ISBN 0-13-032640-2.
TK7874.H392.
Hwang, K. 1979. Computer Arithmetic: Principles, Architecture, and Design.
New York: Wiley, 423 p. ISBN 0471034967. TK7888.3.H9.
Katz, R. H., 1994. Contemporary Logic Design. Reading, MA: Addison-Wesley,
699 p. ISBN 0-8053-2703-7.
Keutzer, K., S. Malik, and A. Saldanha. 1991. Is redundancy necessary to reduce
delay? IEEE Transactions on Computer-Aided Design, vol. 10, no. 4, pp. 427
435. Describes the carry-skip adder. The paper describes the redundant logic that
is added in a carry-skip adder and how to remove it without changing the
function or delay of the circuit. [p. 83]
Lehman, M., and N. Burla. 1961. Skip techniques for high-speed
carry-propagation in binary arithmetic units. IRE Transactions on Electronic
Computers, vol. 10, pp. 691698. Original reference to carry-skip adder. [p. 83]
MacSorley, O. L. 1961. High speed arithmetic in binary computers. IRE
Proceedings, vol. 49, pp. 6791. Early reference to carry-lookahead adder.
Reprinted in Swartzlander [1990, vol. 1]. See also Weste [1993, pp. 526529].
[p. 84]
Mead, C. A. 1989. Analog VLSI and Neural Systems. Reading, MA:
Addison-Wesley, p.371. ISBN 0-201-05992-4. QA76.5.M39. Includes a
description of MOS device operation.
Muller, R. S., and T. I. Kamins. 1977. Device Electronics for Integrated Circuits.
New York: Wiley, p. 404. ISBN 0-471-62364-4. TK7871.85.M86. See also the
second edition of this book (1986).
Mukherjee, A. 1986. Introduction to nMOS and CMOS VLSI Systems Design.
Englewood Cliffs, NJ: Prentice-Hall, 370 p. ISBN 0-13-490947-X. TK7874.M86.
Rabaey, J. 1996. Digital Integrated Circuits: A Design Perspective. Englewood
Cliffs, NJ: Prentice-Hall, pp. 700. ISBN 0-13-178609-1. TK7874.65.R33.
Chapters 4 and 7 describe the design of full-custom CMOS datapath circuits.
Ranganathan, N. (Ed.). 1993. VLSI Algorithms and Architectures: Fundamentals.
New York: IEEE Press, 305 p. ISBN 0-8186-4390-0. TK7874.V5554. See also
N. Ranganathan (Ed.), 1993. VLSI Algorithms and Architectures: Advanced
Concepts. New York: IEEE Press, 303 p. ISBN 0-8186-4400-1. TK7874.V555.
Collections of articles mostly from Computer and IEEE Transactions on
Computers.
Sato, T., et al . 1992. An 8.5 ns 112-b transmission gate adder with a
conflict-free bypass circuit. IEEE Journal of Solid-State Circuits, vol. 27, no. 4,
pp. 657659. Describes an implementation of a carry-bypass adder. [p. 82]
Sklansky, J. 1960. Conditional-sum addition logic. IRE Transactions on
Electronic Computers, vol. 9, pp. 226231. Original reference to conditional-sum
adder. Several texts have propagated an error in the spelling of Sklansky (two k
s). See also [Weste, 1993] pp. 532533; A. Rothermel et al ., Realization of
transmission-gate conditional-sum (TGCS) adders with low latency time, IEEE
Journal of Solid-State Circuits, vol. 24, no. 3, 1989, pp. 558561; each of these
are examples of adders based on Sklanskys design. [p. 86]
Swartzlander, E. E., Jr. 1990. Computer Arithmetic. Los Alamitos, CA: IEEE
Computer Society Press, vols. 1 and 2. ISBN 0818689315 (vol. 1).
QA76.6.C633. Volume 1 is a reprint (originally published: Stroudsberg, PA:
Dowden, Hutchinson & Ross). Volume 2 is a sequel. Contains reprints of many
of the early (19601970) journal articles on adder and multiplier architectures.
Sze, S. (Ed.). 1988. VLSI Technology. New York: McGraw-Hill, 676 p. ISBN
0-07-062735-5. TK7874.V566. Edited book on fabrication technology.
Trontelj, J., et al. 1989. Analog Digital ASIC Design. New York: McGraw-Hill,
249 p. ISBN 0-07-707300-2. TK7874.T76.
Uyemura, J. P. 1992. Circuit Design for CMOS VLSI. Boston: Kluwer, 450 p.
ISBN 0-7923-9184-5. TK7874.U93. See also: J. P. Uyemura, 1988,
Fundamentals of MOS Digital Integrated Circuits, Reading, MA:
Addison-Wesley, 624 p. ISBN 0-201-13318-0. TK7874.U94. Includes basic
circuit equations related to NMOS and CMOS logic design.
Wakerly, J. F. 1994. Digital Design: Principles and Practices . 2nd ed.
Englewood Cliffs, NJ: Prentice-Hall, 840 p. ISBN 0-13-211459-3.
TK7874.65.W34. Undergraduate level introduction to logic design covering:
binary arithmetic, CMOS and TTL, combinational logic, PLDs, sequential logic,
memory, and the IEEE standard logic symbols.
Wallace, C. S. 1960. A suggestion for a fast multiplier. IEEE Transactions on
Electronic Computers, vol. 13, pp. 1417. Original reference to Wallace-tree
multiplier. Reprinted in Swartzlander [1990, vol. 1]. [p. 91]
Waser, S., and M. J. Flynn. 1982. Introduction to Arithmetic for Digital Systems
Designers . New York: Holt, Rinehart, and Winston, 308 p. ISBN 0030605717.
TK7895.A65.W37. [p. 116]
Weste, N. H. E., and K. Eshraghian. 1993. Principles of CMOS VLSI Design: A
Systems Perspective. 2nd ed. Reading, MA: Addison-Wesley, 713 p. ISBN
0-201-53376-6. TK7874.W46. Chapter 5 covers CMOS logic gate design.
Chapter 8 covers datapath elements. See also the first edition of this book. [p. 82]
L ast E d ited by S P 1411 2 0 0 4
ASIC LIBRARY DESIGN
Once we have decided to use an ASIC design styleusing predefined and
precharacterized cells from a librarywe need to design or buy a cell library. Even
though it is not necessary a knowledge of ASIC library design makes it easier to
use library cells effectively.
3.1 Transistors as Resistors
In Section 2.1, CMOS Transistors, we modeled transistors using ideal switches. If this model were
accurate, logic cells would have no delay.
FIGURE 3.1 A model for CMOS logic delay. (a) A CMOS inverter with a load capacitance, C out
. (b) Input, v(in1) , and output, v(out1) , waveforms showing the definition of the falling
propagation delay, t PDf . In this case delay is measured from the input trip point of 0.5. The output
trip points are 0.35 (falling) and 0.65 (rising). The model predicts t PDf ª R pd ( C p + C out ).
(c) The model for the inverter includes: the input capacitance, C ; the pull-up resistance ( R pu )
and pull-down resistance ( R pd ); and the parasitic output capacitance, C p .
The ramp input, v(in1) , to the inverter in Figure 3.1 (a) rises quickly from zero to V DD . In
response the output, v(out1) , falls from V DD to zero. In Figure 3.1 (b) we measure the
propagation delay of the inverter, t PD , using an input trip point of 0.5 and output trip points of
0.35 (falling, t PDf ) and 0.65 (rising, t PDr ). Initially the n -channel transistor, m1 , is off . As the
input rises, m1 turns on in the saturation region ( V DS > V GS V t n ) before entering the linear
region ( V DS < V GS V t n ). We model transistor m1 with a resistor, R pd (Figure 3.1 c); this is
the pull-down resistance . The equivalent resistance of m2 is the pull-up resistance , R pu .
Delay is created by the pull-up and pull-down resistances, R pd and R pu , together with the parasitic
capacitance at the output of the cell, C p (the intrinsic output capacitance ) and the load capacitance
(or extrinsic output capacitance ), C out (Figure 3.1 c). If we assume a constant value for R pd , the
output reaches a lower trip point of 0.35 when (Figure 3.1 b),
t PDf
0.35 V DD = V DD exp
. (3.1)
R pd ( C out + C p )
An output trip point of 0.35 is convenient because ln (1/0.35) = 1.04 ª 1 and thus
t PDf = R pd ( C out + C p ) ln (1/0.35) ª R pd ( C out + C p ) . (3.2)
The expression for the rising delay (with a 0.65 output trip point) is identical in form. Delay thus
increases linearly with the load capacitance. We often measure load capacitance in terms of a
standard load the input capacitance presented by a particular cell (often an inverter or two-input
NAND cell).
We may adjust the delay for different trip points. For example, for output trip points of 0.1/0.9 we
multiply Eq. 3.2 by ln(0.1) = 2.3, because exp (2.3) = 0.100.
Figure 3.2 shows the DC characteristics of a CMOS inverter. To form Figure 3.2 (b) we take the n
-channel transistor surface (Figure 2.4b) and add that for a p -channel transistor (rotated to account
for the connections). Seen from above, the intersection of the two surfaces is the static transfer
curve of Figure 3.2 (a)along this path the transistor currents are equal and there is no output
current to change the output voltage. Seen from one side, the intersection is the curve of Figure 3.2
(c).
(a)
(b)
(c)
FIGURE 3.2 CMOS inverter characteristics. (a) This
static inverter transfer curve is traced as the inverter
switches slowly enough to be in equilibrium at all times
( I DSn = I DSp ). (b) This surface corresponds to the
current flowing in the n -channel transistor (falling
delay) and p -channel transistor (rising delay) for any
trajectory. (c) The current that flows through both
transistors as the inverter switches along the equilibrium
path.
The input waveform, v(in1) , and the output load (which determines the transistor currents) dictate
the path we take on the surface of Figure 3.2 (b) as the inverter switches. We can thus see that the
currents through the transistors (and thus the pull-up and pull-down resistance values) will vary in a
nonlinear way during switching. Deriving theoretical values for the pull-up and pull-down
resistance values is difficultinstead we work the problem backward by picking the trip points,
simulating the propagation delays, and then calculating resistance values that fit the model.
(a)
(c)
(b)
(d)
FIGURE 3.3 Delay. (a) LogicWorks schematic for inverters driving 1, 2, 4, and 8 standard loads
(1 standard load = 0.034 pF in this case). (b) Transient response (falling delay only) from PSpice.
The postprocessor Probe was used to mark each waveform as it crosses its trip point (0.5 for the
input, 0.35 for the outputs). For example v(out1_4) (4 standard loads) crosses 1.0467 V ( ª 0.35 V
1
DD ) at t = 169.93 ps. (c) Falling and rising delays as a function of load. The slopes in pspF
corresponds to the pull-up resistance (1281 W ) and pull-down resistance (817 W ).
(d) Comparison of the delay model (valid for t > 20 ps) and simulation (4 standard loads). Both are
equal at the 0.35 trip point.
Figure 3.3 shows a simulation experiment (using the G5 process SPICE parameters from
Table 2.1). From the results in Figure 3.3 (c) we can see that R pd = 817 W and R pu = 1281 W for
this inverter (with shape factors of 6/0.6 for the n -channel transistor and 12/0.6 for the p -channel)
using 0.5 (input) and 0.35/0.65 (output) trip points. Changing the trip points would give different
resistance values.
We can check that 817 W is a reasonable value for the pull-down resistance. In the saturation
region I DS (sat) is (to first order) independent of V DS . For an n -channel transistor from our
generic 0.5 m m process (G5 from Section 2.1) with shape factor W/L = 6/0.6, I DSn (sat) = 2.5 mA
(at V GS = 3V and V DS = 3V). The pull-down resistance, R 1 , that would give the same drain
source current is
R 1 = 3.0 V / (2.5 ¥ 10 3 A) = 1200 W . (3.3)
This value is greater than, but not too different from, our measured pull-down resistance of 817 W .
We might expect this result since Figure 3.2b shows that the pull-down resistance reaches its
maximum value at V GS = 3V, V DS = 3V. We could adjust the ratio of the logic so that the rising
and falling delays were equal; then R = R pd = R pu is the pull resistance .
Next, we check our model against the simulation results. The model predicts
t'
v(out1) ª V DD exp
for t ' > 0 . (3.4)
R pd ( C out + C p )
( t' is measured from the point at which the input crosses the 0.5 trip point, t' = 0 at t = 20 ps). With
C p = 4 standard loads = 4 ¥ 0.034 pF = 0.136 pF,
R pd ( C out + C p ) = (38 + 817 (0.136)) ps = 149.112 ps . (3.5)
To make a comparison with the simulation we need to use ln (1/0.35) = 1.04 and not approximately
1 as we have assumed, so that (with all times in ps)
t'
v(out1) ª 3.0 exp
V
149.112/1.04
( t 20)
= 3.0 exp
for t > 20 ps . (3.6)
143.4
Equation 3.6 is plotted in Figure 3.3 (d). For v(out1) = 1.05 V (equal to the 0.35 output trip point),
Eq. 3.6 predicts t = 20 + 149.112 ª 169 ps and agrees with Figure 3.3 (b)it should because we
derived the model from these results!
Now we find C p . From Figure 3.3 (c) and Eq. 3.2
t PDr = (52 + 1281 C out ) ps thus C pr = 52/1281 = 0.041 pF (rising) ,
t PDf = (38 + 817 C out ) ps thus C pf = 38/817 = 0.047 pF (falling) . (3.7)
These intrinsic parasitic capacitance values depend on the choice of output trip points, even though
C pf R pdf and C pr R pdr are constant for a given input trip point and waveform, because the pull-up
and pull-down resistances depend on the choice of output trip points. We take a closer look at
parasitic capacitance next.
3.2 Transistor Parasitic
Capacitance
Logic-cell delay results from transistor resistance, transistor (intrinsic) parasitic
capacitance, and load (extrinsic) capacitance. When one logic cell drives another, the
parasitic input capacitance of the driven cell becomes the load capacitance of the driving
cell and this will determine the delay of the driving cell.
Figure 3.4 shows the components of transistor parasitic capacitance. SPICE prints all of
the MOS parameter values for each transistor at the DC operating point. The following
values were printed by PSpice (v5.4) for the simulation of Figure 3.3 :
FIGURE 3.4 Transistor parasitic capacitance. (a) An n -channel MOS transistor with
(drawn) gate length L and width W. (b) The gate capacitance is split into: the constant
overlap capacitances C GSOV , C GDOV , and C GBOV and the variable capacitances C GS
, C GB , and C GD , which depend on the operating region. (c) A view showing how the
different capacitances are approximated by planar components ( T FOX is the field-oxide
thickness). (d) C BS and C BD are the sum of the area ( C BSJ , C BDJ ), sidewall ( C
BSSW , C BDSW ), and channel edge ( C BSJ GATE , C BDJ GATE ) capacitances. (e)(f) The
dimensions of the gate, overlap, and sidewall capacitances (L D is the lateral diffusion).
NAME m1 m2
MODEL CMOSN CMOSP
ID 7.49E-11 -7.49E-11
VGS 0.00E+00 -3.00E+00
VDS 3.00E+00 -4.40E-08
VBS 0.00E+00 0.00E+00
VTH 4.14E-01 -8.96E-01
VDSAT 3.51E-02 -1.78E+00
GM 1.75E-09 2.52E-11
GDS 1.24E-10 1.72E-03
GMB 6.02E-10 7.02E-12
CBD 2.06E-15 1.71E-14
CBS 4.45E-15 1.71E-14
CGSOV 1.80E-15 2.88E-15
CGDOV 1.80E-15 2.88E-15
CGBOV 2.00E-16 2.01E-16
CGS 0.00E+00 1.10E-14
CGD 0.00E+00 1.10E-14
CGB 3.88E-15 0.00E+00
The parameters ID ( I DS ), VGS , VDS , VBS , VTH (V t ), and VDSAT (V DS (sat) ) are
DC parameters. The parameters GM , GDS , and GMB are small-signal conductances
(corresponding to I DS / V GS , I DS / V DS , and I DS / V BS , respectively). The
remaining parameters are the parasitic capacitances. Table 3.1 shows the calculation of
these capacitance values for the n -channel transistor m1 (with W = 6 m m and L = 0.6 m
m) in Figure 3.3 (a).
TABLE 3.1 Calculations of parasitic capacitances for an n-channel MOS transistor.
Values 1 for VGS = 0V, VDS = 3V,
PSpice Equation
VSB = 0V
C BD = 1.855 ¥ 10 13 + 2.04 ¥ 10 16
C BD = C BDJ + C BDSW
CBD
= 2.06 ¥ 10 13 F
C BDJ + A D C J ( 1 + V DB / f B ) mJ ( f C BDJ = (4.032 ¥ 10 15 )(1 + (3/1))
0.56 = 1.86 ¥ 10 15 F
B = PB )
C BDSW = P D C JSW (1 + V DB / f B )
mJSW
(P D may or may not include channel
edge)
C BDSW = (4.2 ¥ 10 16 )(1 + (3/1)) 0.5
= 2.04 ¥ 10 16 F
C BS = 4.032 ¥ 10 15 + 4.2 ¥ 10 16 =
4.45 ¥ 10 15 F
A S C J = (7.2 ¥ 10 15 )(5.6 ¥ 10 4 ) =
C BSJ + A S C J ( 1 + V SB / f B ) mJ
4.03 ¥ 10 15 F
P S C JSW = (8.4 ¥ 10 6 )(5 ¥ 10 11 )
C BSSW = P S C JSW (1 + V SB / f B )
mJSW
= 4.2 ¥ 10 16 F
C GSOV = W EFF C GSO ; W EFF = W
C GSOV = (6 ¥ 10 6 )(3 ¥ 10 10 ) = 1.8
CGSOV
2W D
¥ 10 16 F
C GDOV = (6 ¥ 10 6 )(3 ¥ 10 10 ) =
CGDOV C GDOV = W EFF C GSO
1.8 ¥ 10 15 F
C
= L EFF C GBO ; L EFF = L 2L C GDOV = (0.5 ¥ 10 6 )(4 ¥ 10 10 ) =
CGBOV GBOV
D
2 ¥ 10 16 F
C GS /C O = 0 (off), 0.5 (lin.), 0.66 (sat.) C O = (6 ¥ 10 6 )(0.5 ¥ 10 6
)(0.00345) = 1.03 ¥ 10 14 F
CGS
C O (oxide capacitance) = W EF L EFF e
C GS = 0.0 F
ox / T ox
CBS
C BS = C BSJ + C BSSW
CGD
C GD /C O = 0 (off), 0.5 (lin.), 0 (sat.)
CGB
1
Input
C GD = 0.0 F
C GB = 0 (on), = C O in series with C GS C GB = 3.88 ¥ 10 15 F , C S =
(off)
depletion capacitance
.MODEL CMOSN NMOS LEVEL=3 PHI=0.7 TOX=10E-09 XJ=0.2U TPG=1
VTO=0.65 DELTA=0.7
+ LD=5E-08 KP=2E-04 UO=550 THETA=0.27 RSH=2 GAMMA=0.6
NSUB=1.4E+17 NFS=6E+11
+ VMAX=2E+05 ETA=3.7E-02 KAPPA=2.9E-02 CGDO=3.0E-10
CGSO=3.0E-10 CGBO=4.0E-10
+ CJ=5.6E-04 MJ=0.56 CJSW=5E-11 MJSW=0.52 PB=1
m1 out1 in1 0 0 cmosn W=6U L=0.6U AS=7.2P AD=7.2P PS=8.4U PD=8.4U
3.2.1 Junction Capacitance
The junction capacitances, C BD and C BS , consist of two parts: junction area and
sidewall; both have different physical characteristics with parameters: CJ and MJ for the
junction, CJSW and MJSW for the sidewall, and PB is common. These capacitances
depend on the voltage across the junction ( V DB and V SB ). The calculations in Table
3.1 assume both source and drain regions are 6 m m ¥ 1.2 m m rectangles, so that A D =
A S = 7.2 ( m m) 2 , and the perimeters (excluding the 1.2 m m channel edge) are P D = P
S = 6 + 1.2 + 1.2 = 8.4 m m. We exclude the channel edge because the sidewalls facing
the channel (corresponding to C BSJ GATE and C BDJ GATE in Figure 3.4 ) are different
from the sidewalls that face the field. There is no standard method to allow for this. It is a
mistake to exclude the gate edge assuming it is accounted for in the rest of the modelit is
not. A pessimistic simulation includes the channel edge in P D and P S (but a true
worst-case analysis would use more accurate models and worst-case model parameters).
In HSPICE there is a separate mechanism to account for the channel edge capacitance
(using parameters ACM and CJGATE ). In Table 3.1 we have neglected C J GATE .
For the p -channel transistor m2 (W = 12 m m and L = 0.6 m m) the source and drain
regions are 12 m m ¥ 1.2 m m rectangles, so that A D = A S ª 14 ( m m) 2 , and the
perimeters are P D = P S = 12 + 1.2 + 1.2 ª 14 m m (these parameters are rounded to two
significant figures solely to simplify the figures and tables).
In passing, notice that a 1.2 m m strip of diffusion in a 0.6 m m process ( l = 0.3 m m) is
only 4 l widewide enough to place a contact only with aggressive spacing rules. The
conservative rules in Figure 2.11 would require a diffusion width of at least 2 (rule 6.4a)
+ 2 (rule 6.3a) + 1.5 (rule 6.2a) = 5.5 l .
3.2.2 Overlap Capacitance
The overlap capacitance calculations for C GSOV and C GDOV in Table 3.1 account for
lateral diffusion (the amount the source and drain extend under the gate) using SPICE
parameter LD = 5E-08 or L D = 0.05 m m. Not all versions of SPICE use the equivalent
parameter for width reduction, WD (assumed zero in Table 3.1 ), in calculating C GDOV
and not all versions subtract W D to form W EFF .
3.2.3 Gate Capacitance
The gate capacitance calculations in Table 3.1 depend on the operating region. The gate
source capacitance C GS varies from zero when the transistor is off to 0.5C O (0.5 ¥
1.035 ¥ 10 15 = 5.18 ¥ 10 16 F) in the linear region to (2/3)C O in the saturation region
(6.9 ¥ 10 16 F). The gatedrain capacitance C GD varies from zero (off) to 0.5C O (linear
region) and back to zero (saturation region).
The gatebulk capacitance C GB may be viewed as two capacitors in series: the fixed
gate-oxide capacitance, C O = W EFF L EFF e ox / T ox , and the variable depletion
capacitance, C S = W EFF L EFF e Si / x d , formed by the depletion region that extends
under the gate (with varying depth x d ). As the transistor turns on the conducting channel
appears and shields the bulk from the gateand at this point C GB falls to zero. Even with
V GS = 0 V, the depletion width under the gate is finite and thus C GB ª 4 ¥ 10 15 F is less
than C O ª 10 16 F. In fact, since C GB ª 0.5 C O , we can tell that at V GS = 0 V, C S ª C O
.
Figure 3.5 shows the variation of the parasitic capacitance values.
FIGURE 3.5 The variation of n -channel transistor parasitic capacitance. Values were
obtained from a series of DC simulations using PSpice v5.4, the parameters shown in
Table 3.1 ( LEVEL=3 ), and by varying the input voltage, v(in1) , of the inverter in
Figure 3.3 (a). Data points are joined by straight lines. Note that CGSOV = CGDOV .
3.2.4 Input Slew Rate
Figure 3.6 shows an experiment to monitor the input capacitance of an inverter as it
switches. We have introduced another variablethe delay of the input ramp or the slew
rate of the input.
In Figure 3.6 (b) the input ramp is 40 ps long with a slew rate of 3 V/ 40 ps or 75 GVs 1
as in our previous experimentsand the output of the inverter hardly moves before the
input has changed. The input capacitance varies from 20 to 40 fF with an average value
of approximately 34 fF for both transitionswe can measure the average value in Probe by
plotting AVG(-i(Vin)) .
(a)
(b)
(c)
FIGURE 3.6 The input capacitance of an inverter. (a) Input capacitance is measured by
monitoring the input current to the inverter, i(Vin) . (b) Very fast switching. The current,
i(Vin) , is multiplied by the input ramp delay ( D t = 0.04 ns) and divided by the voltage
swing ( D V = V DD = 3 V) to give the equivalent input capacitance, C = i D t / D V .
Thus an adjusted input current of 40 fA corresponds to an input capacitance of 40 fF.
The current, i(Vin) , is positive for the rising edge of the input and negative for the
falling edge. (c) Very slow switching. The input capacitance is now equal for both
transitions.
In Figure 3.6 (c) the input ramp is slow enough (300 ns) that we are switching under
almost equilibrium conditionsat each voltage we allow the output to find its level on the
static transfer curve of Figure 3.2 (a). The switching waveforms are quite different. The
average input capacitance is now approximately 0.04 pF (a 20 percent difference). The
propagation delay (using an input trip point of 0.5 and an output trip point of 0.35) is
negative and approximately 150 127 = 23 ns. By changing the input slew rate we have
broken our model. For the moment we shall ignore this problem and proceed.
The calculations in Table 3.1 and behavior of Figures 3.5 and 3.6 are very complex.
How can we find the value of the parasitic capacitance, C , to fit the model of Figure 3.1
? Once again, as we did for pull resistance and the intrinsic output capacitance, instead of
trying to derive a theoretical value for C, we adjust the value to fit the model. Before we
formulate another experiment we should bear in mind the following questions that the
experiment of Figure 3.6 raises: Is it valid to replace the nonlinear input capacitance with
a linear component? Is it valid to use a linear input ramp when the normal waveforms are
so nonlinear?
Figure 3.7 shows an experiment crafted to answer these questions. The experiment has
the following two steps:
1. Adjust c2 to model the input capacitance of m5/6 ; then C = c2 = 0.0335 pF.
2. Remove all the parasitic capacitances for inverter m9/10 except for the gate
capacitances C GS , C GD , and C GB and then adjust c3 (0.01 pF) and c4 (0.025
pF) to model the effect of these missing parasitics.
(c)
(a)
(b)
(d)
FIGURE 3.7 Parasitic capacitance. (a) All devices in this circuit include parasitic
capacitance. (b) This circuit uses linear capacitors to model the parasitic
capacitance of m9/10 . The load formed by the inverter ( m5 and m6 ) is modeled
by a 0.0335 pF capacitor ( c2 ); the parasitic capacitance due to the overlap of the
gates of m3 and m4 with their source, drain, and bulk terminals is modeled by a
0.01 pF capacitor ( c3 ); and the effect of the parasitic capacitance at the drain
terminals of m3 and m4 is modeled by a 0.025 pF capacitor ( c4 ). (c) The two
circuits compared. The delay shown (1.22 1.135 = 0.085 ns) is equal to t PDf for
the inverter m3/4 . (d) An exact match would have both waveforms equal at the
0.35 trip point (1.05 V).
We can summarize our findings from this and previous experiments as follows:
1. Since the waveforms in Figure 3.7 match, we can model the input capacitance of a
logic cell with a linear capacitor. However, we know the input capacitance may
vary (by up to 20 percent in our example) with the input slew rate.
2. The input waveform to the inverter m3/m4 in Figure 3.7 is from another inverter
not a linear ramp. The difference in slew rate causes an error. The measured delay
is 85 ps (0.085 ns), whereas our model (Eq. 3.7 ) predicts
t PDr = (38 + 817 C out ) ps = ( 38 + (817)·(0.0355) ) ps = 65 ps . (3.8)
3. The total gate-oxide capacitance in our inverter with T ox = 100Å is
C O = (W n L n + W p L p ) e ox T ox
= (34.5 ¥ 10 4 )·(6)·( (0.6) + (12)·(0.6) ) pF = 0.037 pF . (3.9)
4. All the transistor parasitic capacitances excluding the gate capacitance contribute
0.01 pF of the 0.0335 pF input capacitanceabout 30 percent. The gate capacitances
contribute the rest0.025 pF (about 70 percent).
The last two observations are useful. Since the gate capacitances are nonlinear, we only
see about 0.025/0.037 or 70 percent of the 0.037 pF gate-oxide capacitance, C O , in the
input capacitance, C . This means that it happens by chance that the total gate-oxide
capacitance is also a rough estimate of the gate input capacitance, C ª C O . Using L and
W rather than L EFF and W EFF in Eq. 3.9 helps this estimate. The accuracy of this
estimate depends on the fact that the junction capacitances are approximately one-third of
the gate-oxide capacitancewhich happens to be true for many CMOS processes for the
shapes of transistors that normally occur in logic cells. In the next section we shall use
this estimate to help us design logic cells.
3.3 Logical Effort
In this section we explore a delay model based on logical effort, a term coined by
Ivan Sutherland and Robert Sproull [1991], that has as its basis the time-constant
analysis of Carver Mead, Chuck Seitz, and others.
We add a catch all nonideal component of delay, t q , to Eq. 3.2 that includes:
(1) delay due to internal parasitic capacitance; (2) the time for the input to reach
the switching threshold of the cell; and (3) the dependence of the delay on the
slew rate of the input waveform. With these assumptions we can express the
delay as follows:
t PD = R ( C out + C p ) + t q . (3.10)
(The input capacitance of the logic cell is C , but we do not need it yet.)
We will use a standard-cell library for a 3.3 V, 0.5 m m (0.6 m m drawn)
technology (from Compass) to illustrate our model. We call this technology C5 ;
it is almost identical to the G5 process from Section 2.1 (the Compass library
uses a more accurate and more complicated SPICE model than the generic
process). The equation for the delay of a 1X drive, two-input NAND cell is in the
form of Eq. 3.10 ( C out is in pF):
t PD = (0.07 + 1.46 C out + 0.15) ns . (3.11)
The delay due to the intrinsic output capacitance (0.07 ns, equal to RC p ) and the
nonideal delay ( t q = 0.15 ns) are specified separately. The nonideal delay is a
considerable fraction of the total delay, so we may hardly ignore it. If data books
do not specify these components of delay separately, we have to estimate the
fractions of the constant part of a delay equation to assign to RC p and t q (here
the ratio RC p / t q is approximately 2).
The data book tells us the input trip point is 0.5 and the output trip points are 0.35
and 0.65. We can use Eq. 3.11 to estimate the pull resistance for this cell as R ª
1.46 nspF 1 or about 1.5 k W . Equation 3.11 is for the falling delay; the data
book equation for the rising delay gives slightly different values (but within 10
percent of the falling delay values).
We can scale any logic cell by a scaling factor s (transistor gates become s times
wider, but the gate lengths stay the same), and as a result the pull resistance R
will decrease to R / s and the parasitic capacitance C p will increase to sC p .
Since t q is nonideal, by definition it is hard to predict how it will scale. We shall
assume that t q scales linearly with s for all cells. The total cell delay then scales
as follows:
t PD = ( R / s )·( C out + sC p ) + st q . (3.12)
For example, the delay equation for a 2X drive ( s = 2), two-input NAND cell is
t PD = (0.03 + 0.75 C out + 0.51) ns . (3.13)
Compared to the 1X version (Eq. 3.11 ), the output parasitic delay has decreased
to 0.03 ns (from 0.07 ns), whereas we predicted it would remain constant (the
difference is because of the layout); the pull resistance has decreased by a factor
of 2 from 1.5 k W to 0.75 k W , as we would expect; and the nonideal delay has
increased to 0.51 ns (from 0.15 ns). The differences between our predictions and
the actual values give us a measure of the model accuracy.
We rewrite Eq. 3.12 using the input capacitance of the scaled logic cell, C in = s
C,
C out
t PD = RC
+ RC p + st q . (3.14)
C in
Finally we normalize the delay using the time constant formed from the pull
resistance R inv and the input capacitance C inv of a minimum-size inverter:
( RC ) ( C out / C in ) + RC p + st q
d=
= f + p + q . (3.15)
t
The time constant tau ,
t = R inv C inv , (3.16)
is a basic property of any CMOS technology. We shall measure delays in terms
of t .
The delay equation for a 1X (minimum-size) inverter in the C5 library is
t PDf = R pd ( C out + C p ) ln (1/0.35) ª R pd ( C out + C p ) . (3.17)
Thus tq inv = 0.1 ns and R inv = 1.60 k W . The input capacitance of the 1X
inverter (the standard load for this library) is specified in the data book as C inv =
0.036 pF; thus t = (0.036 pF)(1.60 k W ) = 0.06 ns for the C5 technology.
The use of logical effort consists of rearranging and understanding the meaning
of the various terms in Eq. 3.15 . The delay equation is the sum of three terms,
d = f + p + q . (3.18)
We give these terms special names as follows:
delay = effort delay + parasitic delay + nonideal delay . (3.19)
The effort delay f we write as a product of logical effort, g , and electrical effort,
h:
f = gh . (3.20)
So we can further partition delay into the following terms:
delay = logical effort ¥ electrical effort + parasitic delay + nonideal delay . (3.21)
The logical effort g is a function of the type of logic cell,
g = RC/ t . (3.22)
What size of logic cell do the R and C refer to? It does not matter because the R
and C will change as we scale a logic cell, but the RC product stays the samethe
logical effort is independent of the size of a logic cell. We can find the logical
effort by scaling down the logic cell so that it has the same drive capability as the
1X minimum-size inverter. Then the logical effort, g , is the ratio of the input
capacitance, C in , of the 1X version of the logic cell to C inv (see Figure 3.8 ).
FIGURE 3.8 Logical effort. (a) The input capacitance, C inv , looking into the
input of a minimum-size inverter in terms of the gate capacitance of a
minimum-size device. (b) Sizing a logic cell to have the same drive strength as a
minimum-size inverter (assuming a logic ratio of 2). The input capacitance
looking into one of the logic-cell terminals is then C in . (c) The logical effort of
a cell is C in / C inv . For a two-input NAND cell, the logical effort, g = 4/3.
The electrical effort h depends only on the load capacitance C out connected to
the output of the logic cell and the input capacitance of the logic cell, C in ; thus
h = C out / C in . (3.23)
The parasitic delay p depends on the intrinsic parasitic capacitance C p of the
logic cell, so that
p = RC p / t . (3.24)
Table 3.2 shows the logical efforts for single-stage logic cells. Suppose the
minimum-size inverter has an n -channel transistor with W/L = 1 and a p
-channel transistor with W/L = 2 (logic ratio, r , of 2). Then each two-input
NAND logic cell input is connected to an n -channel transistor with W/L = 2 and
a p -channel transistor with W/L = 2. The input capacitance of the two-input
NAND logic cell divided by that of the inverter is thus 4/3. This is the logical
effort of a two-input NAND when r = 2. Logical effort depends on the ratio of the
logic. For an n -input NAND cell with ratio r , the p -channel transistors are W/L
= r /1, and the n -channel transistors are W/L = n /1. For a NOR cell the n
-channel transistors are 1/1 and the p -channel transistors are nr /1.
TABLE 3.2 Cell effort, parasitic delay, and nonideal delay (in units of t ) for
single-stage CMOS cells.
Cell effort
Cell effort
Nonideal delay/
Parasitic delay/ t
Cell
t
(logic ratio = 2) (logic ratio = r)
inverter
n -input
NAND
n -input
NOR
1 (by definition) 1 (by definition)
p inv (by
definition) 1
q inv (by
definition) 1
( n + 2)/3
( n + r )/( r + 1) n p inv
n q inv
(2 n + 1)/3
( nr + 1)/( r + 1) n p inv
n q inv
The parasitic delay arises from parasitic capacitance at the output node of a
single-stage logic cell and most (but not all) of this is due to the source and drain
capacitance. The parasitic delay of a minimum-size inverter is
p inv = C p / C inv . (3.25)
The parasitic delay is a constant, for any technology. For our C5 technology we
know RC p = 0.06 ns and, using Eq. 3.17 for a minimum-size inverter, we can
calculate p inv = RC p / t = 0.06/0.06 = 1 (this is purely a coincidence). Thus C p
is about equal to C inv and is approximately 0.036 pF. There is a large error in
calculating p inv from extracted delay values that are so small. Often we can
calculate p inv more accurately from estimating the parasitic capacitance from
layout.
Because RC p is constant, the parasitic delay is equal to the ratio of parasitic
capacitance of a logic cell to the parasitic capacitance of a minimum-size
inverter. In practice this ratio is very difficult to calculateit depends on the
layout. We can approximate the parasitic delay by assuming it is proportional to
the sum of the widths of the n -channel and p -channel transistors connected to
the output. Table 3.2 shows the parasitic delay for different cells in terms of p inv
.
The nonideal delay q is hard to predict and depends mainly on the physical size
of the logic cell (proportional to the cell area in general, or width in the case of a
standard cell or a gate-array macro),
q = st q / t . (3.26)
We define q inv in the same way we defined p inv . An n -input cell is
approximately n times larger than an inverter, giving the values for nonideal
delay shown in Table 3.2 . For our C5 technology, from Eq. 3.17 , q inv = t q inv /
t = 0.1 ns/0.06 ns = 1.7.
3.3.1 Predicting Delay
As an example, let us predict the delay of a three-input NOR logic cell with 2X
drive, driving a net with a fanout of four, with a total load capacitance
(comprising the input capacitance of the four cells we are driving plus the
interconnect) of 0.3 pF.
From Table 3.2 we see p = 3 p inv and q = 3 q inv for this cell. We can calculate
C in from the fact that the input gate capacitance of a 1X drive, three-input NOR
logic cell is equal to gC inv , and for a 2X logic cell, C in = 2 gC inv . Thus,
C out
gh = g
C in
g ·(0.3 pF) (0.3 pF)
=
=
. (3.27)
2 g C inv
(2)·(0.036 pF)
(Notice that g cancels out in this equation, we shall discuss this in the next
section.)
The delay of the NOR logic cell, in units of t , is thus
0.3 ¥ 10 12
d = gh + p + q =
+ (3)·(1) + (3)·(1.7)
(2)·(0.036 ¥ 10 12 )
= 4.1666667 + 3 + 5.1
= 12.266667 t .
(3.28)
equivalent to an absolute delay, t PD ª 12.3 ¥ 0.06 ns = 0.74 ns.
The delay for a 2X drive, three-input NOR logic cell in the C5 library is
t PD = (0.03 + 0.72 C out + 0.60) ns . (3.29)
With C out = 0.3 pF,
t PD = 0.03 + (0.72)·(0.3) + 0.60 = 0.846 ns . (3.30)
compared to our prediction of 0.74 ns. Almost all of the error here comes from
the inaccuracy in predicting the nonideal delay. Logical effort gives us a method
to examine relative delays and not accurately calculate absolute delays. More
important is that logical effort gives us an insight into why logic has the delay it
does.
3.3.2 Logical Area and Logical Efficiency
Figure 3.9 shows a single-stage OR-AND-INVERT cell that has different logical
efforts at each input. The logical effort for the OAI221 is the logical-effort vector
g = (7/3, 7/3, 5/3). For example, the first element of this vector, 7/3, is the logical
effort of inputs A and B in Figure 3.9 .
FIGURE 3.9 An OAI221 logic
cell with different logical
efforts at each input. In this
case g = (7/3, 7/3, 5/3). The
logical effort for inputs A and
B is 7/3, the logical effort for
inputs C and D is also 7/3, and
for input E the logical effort is
5/3. The logical area is the sum
of the transistor areas, 33
logical squares.
We can calculate the area of the transistors in a logic cell (ignoring the routing
area, drain area, and source area) in units of a minimum-size n -channel transistor
we call these units logical squares . We call the transistor area the logical area .
For example, the logical area of a 1X drive cell, OAI221X1, is calculated as
follows:
● n -channel transistor sizes: 3/1 + 4 ¥ (3/1)
● p -channel transistor sizes: 2/1 + 4 ¥ (4/1)
● total logical area = 2 + (4 ¥ 4) + (5 ¥ 3) = 33 logical squares
Figure 3.10 shows a single-stage AOI221 cell, with g = (8/3, 8/3, 6/3). The
calculation of the logical area (for a AOI221X1) is as follows:
● n -channel transistor sizes: 1/1 + 4 ¥ (2/1)
●
●
p -channel transistor sizes: 6/1 + 4 ¥ (6/1)
logical area = 1 + (4 ¥ 2) + (5 ¥ 6) = 39 logical squares
FIGURE 3.10 An
AND-OR-INVERT cell,
an AOI221, with
logical-effort vector, g =
(8/3, 8/3, 7/3). The
logical area is 39 logical
squares.
These calculations show us that the single-stage AOI221, with an area of 33
logical squares and logical effort of (7/3, 7/3, 5/3), is more logically efficient than
the single-stage OAI221 logic cell with a larger area of 39 logical squares and
larger logical effort of (8/3, 8/3, 6/3).
3.3.3 Logical Paths
When we calculated the delay of the NOR logic cell in Section 3.3.1, the answer
did not depend on the logical effort of the cell, g (it cancelled out in Eqs. 3.27
and 3.28 ). This is because g is a measure of the input capacitance of a 1X drive
logic cell. Since we were not driving the NOR logic cell with another logic cell,
the input capacitance of the NOR logic cell had no effect on the delay. This is
what we do in a data bookwe measure logic-cell delay using an ideal input
waveform that is the same no matter what the input capacitance of the cell.
Instead let us calculate the delay of a logic cell when it is driven by a
minimum-size inverter. To do this we need to extend the notion of logical effort.
So far we have only considered a single-stage logic cell, but we can extend the
idea of logical effort to a chain of logic cells or logical path . Consider the logic
path when we use a minimum-size inverter ( g 0 = 1, p 0 = 1, q 0 = 1.7) to drive
one input of a 2X drive, three-input NOR logic cell with g 1 = ( nr + 1)/( r + 1), p
1 = 3, q 1 =3, and a load equal to four standard loads. If the logic ratio is r = 1.5,
then g 1 = 5.5/2.5 = 2.2.
The delay of the inverter is
d = g 0 h 0 + p 0 + q 0 = (1) · (2g 1 ) · (C inv /C inv ) +1 + 1.7 (3.31)
= (1)(2)(2.2) + 1 + 1.7
= 7.1 .
Of this 7.1 t delay we can attribute 4.4 t to the loading of the NOR logic cell input
capacitance, which is 2 g 1 C inv . The delay of the NOR logic cell is, as before, d
1 = g 1 h 1 + p 1 + q 1 = 12.3, making the total delay 7.1 + 12.3 = 19.4, so the
absolute delay is (19.4)(0.06 ns) = 1.164 ns, or about 1.2 ns.
We can see that the path delay D is the sum of the logical effort, parasitic delay,
and nonideal delay at each stage. In general, we can write the path delay as
gihi+
D=
i path
( p i + q i ) . (3.32)
i path
3.3.4 Multistage Cells
Consider the following function (a multistage AOI221 logic cell):
ZN(A1, A2, B1, B2, C)
= NOT(NAND(NAND(A1, A2), AOI21(B1, B2, C)))
= (((A1·A2)' · (B1·B2 + C)')')'
= (A1·A2 + B1·B2 + C)'
= AOI221(A1, A2, B1, B2, C) .
(3.33)
Figure 3.11 (a) shows this implementation with each input driven by a
minimum-size inverter so we can measure the effect of the cell input capacitance.
FIGURE 3.11 Logical paths. (a) An AOI221 logic cell constructed as a
multistage cell from smaller cells. (b) A single-stage AOI221 logic cell.
The logical efforts of each of the logic cells in Figure 3.11 (a) are as follows:
g 0 = g 4 = g (NOT) = 1 ,
g 1 = g (AOI21) = (2, (2 r + 1)/( r + 1)) = (2, 4/2.5) = (2, 1.6) ,
g 2 = g 3 = g (NAND2) = ( r + 2)/( r + 1) = (3.5)/(2.5) = 1.4 . (3.34)
Each of the logic cells in Figure 3.11 has a 1X drive strength. This means that
the input capacitance of each logic cell is given, as shown in the figure, by gC inv
.
Using Eq. 3.32 we can calculate the delay from the input of the inverter driving
A1 to the output ZN as
d 1 = (1)·(1.4) + 1 + 1.7 + (1.4)·(1) + 2 + 3.4
+ (1.4)·(0.7) + 2 + 3.4 + (1)· C L + 1 + 1.7
= (20 + C L ) .
(3.35)
In Eq. 3.35 we have normalized the output load, C L , by dividing it by a
standard load (equal to C inv ). We can calculate the delays of the other paths
similarly.
More interesting is to compare the multistage implementation with the
single-stage version. In our C5 technology, with a logic ratio, r = 1.5, we can
calculate the logical effort for a single-stage AOI221 logic cell as
g (AOI221) = ((3 r + 2)/( r + 1), (3 r + 2)/( r + 1), (3 r + 1)/( r + 1))
= (6.5/2.5, 6.5/2.5, 5.5/2.5)
= (2.6, 2.6, 2.2) .
(3.36)
This gives the delay from an inverter driving the A input to the output ZN of the
single-stage logic cell as
d1 = ((1)·(2.6) + 1 + 1.7 + (1)· C L + 5 + 8.5 )
(3.37)
= 18.8 + C L .
The single-stage delay is very close to the delay for the multistage version of this
logic cell. In some ASIC libraries the AOI221 is implemented as a multistage
logic cell instead of using a single stage. It raises the question: Can we make the
multistage logic cell any faster by adjusting the scale of the intermediate logic
cells?
3.3.5 Optimum Delay
Before we can attack the question of how to optimize delay in a logic path, we
shall need some more definitions. The path logical effort G is the product of
logical efforts on a path:
g i . (3.38)
G=
i path
The path electrical effort H is the product of the electrical efforts on the path,
C out
hi
H=
i path
, (3.39)
C in
where C out is the last output capacitance on the path (the load) and C in is the
first input capacitance on the path.
The path effort F is the product of the path electrical effort and logical efforts,
F = GH . (3.40)
The optimum effort delay for each stage is found by minimizing the path delay D
by varying the electrical efforts of each stage h i , while keeping H , the path
electrical effort fixed. The optimum effort delay is achieved when each stage
operates with equal effort,
f^ i = g i h i = F 1/ N . (3.41)
This a useful result. The optimum path delay is then
D^ = NF 1/ N = N ( GH ) 1/ N + P + Q , (3.42)
where P + Q is the sum of path parasitic delay and nonideal delay,
p i + h i . (3.43)
P+Q=
i path
We can use these results to improve the AOI221 multistage implementation of
Figure 3.11 (a). Assume that we need a 1X cell, so the output inverter (cell 4)
must have 1X drive strength. This fixes the capacitance we must drive as C out =
C inv (the capacitance at the input of this inverter). The input inverters are
included to measure the effect of the cell input capacitance, so we cannot cheat
by altering these. This fixes the input capacitance as C in = C inv . In this case H =
1.
The logic cells that we can scale on the path from the A input to the output are
NAND logic cells labeled as 2 and 3. In this case
G = g 0 ¥ g 2 ¥ g 3 = 1 ¥ 1.4 ¥ 1.4 = 1.95 . (3.44)
Thus F = GH = 1.95 and the optimum stage effort is 1.95 (1/3) = 1.25, so that the
optimum delay NF 1/ N = 3.75. From Figure 3.11 (a) we see that
g 0 h 0 + g 2 h 2 + g 3 h 3 = 1.4 + 1.3 + 1 = 3.8 . (3.45)
This means that even if we scale the sizes of the cells to their optimum values, we
only save a fraction of a t (3.8 3.75 = 0.05). This is a useful result (and one that
is true in general)the delay is not very sensitive to the scale of the cells. In this
case it means that we can reduce the size of the two NAND cells in the multicell
implementation of an AOI221 without sacrificing speed. We can use logical
effort to predict what the change in delay will be for any given cell sizes.
We can use logical effort in the design of logic cells and in the design of logic
that uses logic cells. If we do have the flexibility to continuously size each logic
cell (which in ASIC design we normally do not, we usually have to choose from
1X, 2X, 4X drive strengths), each logic stage can be sized using the equation for
the individual stage electrical efforts,
F 1/ N
h^ i =
. (3.46)
gi
For example, even though we know that it will not improve the delay by much,
let us size the cells in Figure 3.11 (a). We shall work backward starting at the
fixed load capacitance at the input of the last inverter.
For NAND cell 3, gh = 1.25; thus (since g = 1.4), h = C out / C in = 0.893. The
output capacitance, C out , for this NAND cell is the input capacitance of the
inverterfixed as 1 standard load, C inv . This fixes the input capacitance, C in , of
NAND cell 3 at 1/0.893 = 1.12 standard loads. Thus, the scale of NAND cell 3 is
1.12/1.4 or 0.8X.
Now for NAND cell 2, gh = 1.25; C out for NAND cell 2 is the C in of NAND
cell 3. Thus C in for NAND cell 2 is 1.12/0.893 = 1.254 standard loads. This
means the scale of NAND cell 2 is 1.254/1.4 or 0.9X.
The optimum sizes of the NAND cells are not very different from 1X in this case
because H = 1 and we are only driving a load no bigger than the input
capacitance. This raises the question: What is the optimum stage effort if we have
to drive a large load, H >> 1? Notice that, so far, we have only calculated the
optimum stage effort when we have a fixed number of stages, N . We have said
nothing about the situation in which we are free to choose, N , the number of
stages.
3.3.6 Optimum Number of Stages
Suppose we have a chain of N inverters each with equal stage effort, f = gh .
Neglecting parasitic and nonideal delay, the total path delay is Nf = Ngh = Nh ,
since g = 1 for an inverter. Suppose we need to drive a path electrical effort H ;
then h N = H , or N ln h = ln H . Thus the delay, Nh = h ln H /ln h . Since ln H is
fixed, we can only vary h /ln ( h ). Figure 3.12 shows that this is a very shallow
function with a minimum at h = e ª 2.718. At this point ln h = 1 and the total
delay is N e = e ln H . This result is particularly useful in driving large loads
either on-chip (the clock, for example) or off-chip (I/O pad drivers, for example).
FIGURE 3.12 Stage effort.
h
1.5
2
2.7
3
4
5
10
h/(ln h)
3.7
2.9
2.7
2.7
2.9
3.1
4.3
Figure 3.12 shows us how to minimize delay regardless of area or power and
neglecting parasitic and nonideal delays. More complicated equations can be
derived, including nonideal effects, when we wish to trade off delay for smaller
area or reduced power.
1. For the Compass 0.5 m m technology (C5): p inv = 1.0, q inv = 1.7, R inv = 1.5
k W , C inv = 0.036 pF.
3.4 Library-Cell Design
The optimum cell layout for each process generation changes because the design
rules for each ASIC vendors process are always slightly differenteven for the
same generation of technology. For example, two companies may have very
similar 0.35 m m CMOS process technologies, but the third-level metal spacing
might be slightly different. If a cell library is to be used with both processes, we
could construct the library by adopting the most stringent rules from each
process. A library constructed in this fashion may not be competitive with one
that is constructed specifically for each process. Even though ASIC vendors prize
their design rules as secret, it turns out that they are similarexcept for a few
details. Unfortunately, it is the details that stop us moving designs from one
process to another. Unless we are a very large customer it is difficult to have an
ASIC vendor change or waive design rules for us. We would like all vendors to
agree on a common set of design rules. This is, in fact, easier than it sounds. The
reason that most vendors have similar rules is because most vendors use the same
manufacturing equipment and a similar process. It is possible to construct a
highest common denominator library that extracts the most from the current
manufacturing capability. Some library companies and the large Japanese ASIC
vendors are adopting this approach.
Layout of library cells is either hand-crafted or uses some form of symbolic
layout . Symbolic layout is usually performed in one of two ways: using either
interactive graphics or a text layout language. Shapes are represented by simple
lines or rectangles, known as sticks or logs , in symbolic layout. The actual
dimensions of the sticks or logs are determined after layout is completed in a
postprocessing step. An alternative to graphical symbolic layout uses a text
layout language, similar to a programming language such as C, that directs a
program to assemble layout. The spacing and dimensions of the layout shapes are
defined in terms of variables rather than constants. These variables can be
changed after symbolic layout is complete to adjust the layout spacing to a
specific process.
Mapping symbolic layout to a specific process technology uses 1020 percent
more area than hand-crafted layout (though this can then be further reduced to 5
10 percent with compaction). Most symbolic layout systems do not allow 45°
layout and this introduces a further area penalty (my experience shows this is
about 515 percent). As libraries get larger, and the capability to quickly move
libraries and ASIC designs between different generations of process technologies
becomes more important, the advantages of symbolic layout may outweigh the
disadvantages.
3.5 Library Architecture
Figure 3.13 (a) shows cell use data from over 150 CMOS gate array designs.
These results are remarkably similar to that from other ASIC designs using
different libraries and different technologies and show that typically 80 percent of
an ASIC uses less than 20 percent of the cell library.
(a)
(b )
(c)
(d)
(e )
FIGURE 3.13 Cell library statistics.
We can use the data in Figure 3.13 (a) to derive some useful conclusions about the
number and types of cells to be included in a library. Before we do this, a few
words of caution are in order. First, the data shown in Figure 3.13 (a) tells us about
cells that are included a library. This data cannot tell us anything about cells that
are not (and perhaps should be) included in a library. Second, the type of design
entry we useand the type of ASIC we are designingcan dramatically affect the
profile of the use of different cell types. For example, if we use a high-level design
language, together with logic synthesis, to enter an ASIC design, this will favor the
use of the complex combinational cells (cells of the AOI family that are
particularly area efficient in CMOS, but are difficult to work with when we design
by hand).
Figure 3.13 (a) tells us which cells we use most often, but does not take into
account the cell area. What we really want to know are which cells are most
important in determining the area of an ASIC. Figure 3.13 (b) shows the area of
the cellsnormalized to the area of a minimum-size inverter. If we take the data in
Figure 3.13 (a) and multiply by the cell areas, we can derive a new measure of the
contribution of each cell in a library (Figure 3.13c). This new measure, cell
importance , is a measure of how much area each cell in a library contributes to a
typical ASIC. For example, we can see from Figure 3.13 (c) that a D flip-flop
(with a cell importance of 3.5) contributes 3.5 times as much area on a typical
ASIC than does an inverter (with a cell importance of 1).
Figure 3.13 (c) shows cell importance ordered by the cell frequency of use and
normalized to an inverter. We can rearrange this data in terms of cell importance,
as shown in Figure 3.13 (d), and normalized so that now the most important cell, a
D flip-flop, has a cell importance of 1. Figure 3.13 (e) includes the cell use data on
the same scale as the cell importance data. Both show roughly the same shape,
reflecting that both measures obey an 8020 rule. Roughly 20 percent of the cells in
a library correspond to 80 percent of the ASIC area and 80 percent of the cells we
use (but not the same 20 percentthat is why cell importance is useful).
Figure 3.13 (e) shows us that the most important cells, measured by their
contribution to the area of an ASIC, are not necessarily the cells that we use most
often. If we wish to build or buy a dense library, we must concentrate on the area
of those cells that have the highest cell importancenot the most common cells.
3.6 Gate-Array Design
Each logic cell or macro in a gate-array library is predesigned using fixed tiles of
transistors known as the gate-array base cell (or just base cell ). We call the
arrangement of base cells across a whole chip in a complete gate array the
gate-array base (or just base ). ASIC vendors offer a selection of bases, with a
different total numbers of transistors on each base. For example, if our ASIC
design uses 48k equivalent gates and the ASIC vendor offers gate arrays bases
with 50k-, 75k-, and 100k-gates, we will probably have to use the 75k-gate base
(because it is unlikely that we can use 48/50 or 96 percent of the transistors on
the 50k-gate base).
We isolate the transistors on a gate array from one another either with thick field
oxide (in the case of oxide-isolated gate arrays) or by using other transistors that
are wired permanently off (in gate-isolated gate arrays). Channeled and
channelless gate arrays may use either gate isolation or oxide isolation.
Figure 3.14 (a) shows a base cell for a gate-isolated gate array . This base cell
has two transistors: one p -channel and one n -channel. When these base cells are
placed next to each other, the n -diffusion and p -diffusion layers form continuous
strips that run across the entire chip broken only at the poly gates that cross at
regularly spaced intervals (Figure 3.14b). The metal interconnect spacing
determines the separation of the transistors. The metal spacing is determined by
the design rules for the metal and contacts. In Figure 3.14 (c) we have shown all
possible locations for a contact in the base cell. There is room for 21 contacts in
this cell and thus room for 21 interconnect lines running in a horizontal direction
(we use m1 running horizontally). We say that there are 21 horizontal tracks in
this cell or that the cell is 21 tracks high. In a similar fashion the space that we
need for a vertical interconnect (m2) is called a vertical track . The horizontal and
vertical track widths are not necessarily equal, because the design rules for m1
and m2 are not always equal.
We isolate logic cells from each other in gate-isolated gate arrays by connecting
transistor gates to the supply bushence the name, gate isolation . If we connect
the gate of an n -channel transistor to V SS , we isolate the regions of n -diffusion
on each side of that transistor (we call this an isolator transistor or device, or just
isolator). Similarly if we connect the gate of a p -channel transistor to V DD , we
isolate adjacent p -diffusion regions.
FIGURE 3.14 The construction of a gate-isolated gate array. (a) The
one-track-wide base cell containing one p -channel and one n -channel transistor.
(b) Three base cells: the center base cell is being used to isolate the base cells on
either side from each other. (c) A base cell including all possible contact
positions (there is room for 21 contacts in the vertical direction, showing the
base cell has a height of 21 tracks).
Oxide-isolated gate arrays often contain four transistors in the base cell: the two n
-channel transistors share an n -diffusion strip and the two p -channel transistors
share a p -diffusion strip. This means that the two n -channel transistors in each
base cell are electrically connected in series, as are the p -channel transistors. The
base cells are isolated from each other using oxide isolation . During the
fabrication process a layer of the thick field oxide is left in place between each
base cell and this separates the p -diffusion and n -diffusion regions of adjacent
base cells.
Figure 3.15 shows an oxide-isolated gate array . This cell contains eight
transistors (which occupy six vertical tracks) plus one-half of a single track that
contains the well contacts and substrate connections that we can consider to be
shared by each base cell.
FIGURE 3.15 An oxide-isolated gate-array base cell. The figure shows two base
cells, each containing eight transistors and two well contacts. The p -channel and
n -channel transistors are each 4 tracks high (corresponding to the width of the
transistor). The leftmost vertical track of the left base cell includes all 12
possible contact positions (the height of the cell is 12 tracks). As outlined here,
the base cell is 7 tracks wide (we could also consider the base cell to be half this
width).
Figure 3.16 shows a base cell in which the gates of the n -channel and p -channel
transistors are connected on the polysilicon layer. Connecting the gates in poly
saves contacts and a metal interconnect in the center of the cell where
interconnect is most congested. The drawback of the preconnected gates is a loss
in flexibility in cell design. Implementing memory and logic based on
transmission gates will be less efficient using this type of base cell, for example.
FIGURE 3.16 This oxide-isolated gate-array base cell is 14 tracks high and 4
tracks wide. VDD (tracks 3 and 4) and GND (tracks 11 and 12) are each 2 tracks
wide. The metal lines to the left of the cell indicate the 10 horizontal routing
tracks (tracks 1, 2, 510, 13, 14). Notice that the p -channel and n -channel
polysilicon gates are tied together in the center of the cell. The well contacts are
short, leaving room for a poly cross-under in each base cell.
Figure 3.17 shows the metal personalization for a D flip-flop macro in a
gate-isolated gate array using a base cell similar to that shown in Figure 3.14 (a).
This macro uses 20 base cells, for a total of 40 transistors, equivalent to 10 gates.
FIGURE 3.17 An example of a flip-flop macro in a gate-isolated gate-array
library. Only the first-level metallization and contact pattern (the
personalization) is shown on the right, but this is enough information to derive
the schematic. The base cell is shown on the left. This macro is 20 tracks wide.
The gates of the base cells shown in Figures 3.14 3.16 are bent. The bent gate
allows contacts to the gates to be placed on the same grid as the contacts to
diffusion. The polysilicon gates run in the space between adjacent metal
interconnect lines. This saves space and also simplifies the routing software.
There are many trade-offs that determine the gate-array base cell height. One
factor is the number of wires that can be run horizontally through the base cell.
This will determine the capacity of the routing channel formed from an unused
row of base cells. The base cell height also determines how easy it is to wire the
logic macros since it determines how much space for wiring is available inside
the macros.
There are other factors that determine the width of the base-cell transistors. The
widths of the p -channel and n -channel transistors are slightly different in Figure
3.14 (a). The p -channel transistors are 6 tracks wide and the n -channel
transistors are 5 tracks wide. The ratio for this gate-array library is thus
approximately 1.2. Most gate-array libraries are approaching a ratio of 1.
ASIC designers are using ever-increasing amounts of RAM on gate arrays. It is
inefficient to use the normal base cell for a static RAM cell and the size of RAM
on an embedded gate array is fixed. As an alternative we can change the design
of the base cell. A base cell designed for use as RAM has extra transistors (either
fourtwo n -channel and two p -channelor two n -channel; usually minimum
width) allowing a six-transistor RAM cell to be built using one base cell instead
of the two or three that we would normally need. This is one of the advantages of
the CBA (cell-based array) base cell shown in Figure 3.18 .
FIGURE 3.18 The SiARC/Synopsys cell-based array (CBA) basic cell.
3.7 Standard-Cell Design
Figure 3.19 shows the components of the standard cell from Figure 1.3. Each
standard cell in a library is rectangular with the same height but different widths. The
bounding box ( BB ) of a logic cell is the smallest rectangle that encloses all of the
geometry of the cell. The cell BB is normally determined by the well layers. Cell
connectors or terminals (the logical connectors ) must be placed on the cell abutment
box ( AB ). The physical connector (the piece of metal to which we connect wires)
must normally overlap the abutment box slightly, usually by at least 1 l , to assure
connection without leaving a tiny space between the ends of two wires. The standard
cells are constructed so they can all be placed next to each other horizontally with the
cell ABs touching (we abut two cells).
(a)
(b)
(c)
(d)
FIGURE 3.19 (a) The standard cell shown in Figure 1.3. (b) Diffusion, poly, and
contact layers. (c) m1 and contact layers. (d) The equivalent schematic.
A standard cell (a D flip-flop with clear) is shown in Figure 3.20 and illustrates the
following features of standard-cell layout:
● Layout using 45° angles. This can save 10%20% in area compared to a cell
that uses only Manhattan or 90° geometry. Some ASIC vendors do not allow
transistors with 45° angles; others do not allow 45° angles at all.
● Connectors are at the top and bottom of the cell on m2 on a routing grid equal
to the vertical (m2) track spacing. This is a double-entry cell intended for a
two-level metal process. A standard cell designed for a three-level metal
process has connectors in the center of the cell.
● Transistor sizes vary to optimize the area and performance but maintain a fixed
ratio to balance rise times and fall times.
● The cell height is 64 l (all cells in the library are the same height) with a
horizontal (m1) track spacing of 8 l . This is close to the minimum height that
can accommodate the most complex cells in a library.
● The power rails are placed at the top and bottom, maintaining a certain width
inside the cell and abut with the power rails in adjacent cells.
● The well contacts (substrate connections) are placed inside the cell at regular
intervals. Additional well contacts may be placed in spacers between cells.
● In this case both wells are drawn. Some libraries minimize the well or moat
area to reduce leakage and parasitic capacitance.
● Most commercial standard cells use m1 for the power rails, m1 for internal
connections, and avoid using m2 where possible except for cell connectors.
FIGURE 3.20 A D flip-flop standard cell. The wide power buses and
transistors show this is a performance-optimized cell. This double-entry cell is
intended for a two-level metal process and channel routing. The five
connectors run vertically through the cell on m2 (the extra short vertical metal
line is an internal crossover).
When a library developer creates a gate-array, standard-cell, or datapath library, there
is a trade-off between using wide, high-drive transistors that result in large cells with
high-speed performance and using smaller transistors that result in smaller cells that
consume less power. A performance-optimized library with large cells might be used
for ASICs in a high-performance workstation, for example. An area-optimized library
might be used in an ASIC for a battery-powered portable computer.
3.8 Datapath-Cell Design
Figure 3.21 shows a datapath flip-flop. The primary, thicker, power buses run
vertically on m2 with thinner, internal power running horizontally on m1. The
control signals (clock in this case) run vertically through the cell on m2. The
control signals that are common to the cells above and below are connected
directly in m2. The other signals (data, q, and qbar in this example) are brought
out to the wiring channel between the rows of datapath cells.
FIGURE 3.21 A datapath D flip-flop cell.
Figure 3.22 is the schematic for Figure 3.21 . This flip-flop uses a pair of
cross-coupled inverters for storage in both the master and slave latches. This
leads to a smaller and potentially faster layout than the flip-flop circuits that we
use in gate-array and standard-cell ASIC libraries. The device sizes of the
inverters in the data-path flip-flops are adjusted so that the state of the latches
may be changed. Normally using this type of circuit is dangerous in an
uncontrolled environment. However, because the datapath structure is regular and
known, the parasitic capacitances that affect the operation of the logic cell are
also known. This is another advantage of the datapath structure.
FIGURE 3.22 The schematic of the datapath D flip-flop cell shown in Figure
3.21 .
Figure 3.23 shows an example of a datapath. Figure 3.23 (a) depicts a two-level
metal version showing the space between rows or slices of the datapath. In this
case there are many connections to be brought out to the right of the datapath,
and this causes the routing channel to be larger than normal and thus easily seen.
Figure 3.23 (b) shows a three-level metal version of the same datapath. In this
case more of the routing is completed over the top of the datapath slices, reducing
the size of the routing channel.
(a)
FIGURE 3.23 A datapath. (a)
Implemented in a two-level
metal process. (b) Implemented
(b)
in a three-level metal process.
3.9 Summary
In this chapter we covered ASIC libraries: cell design, layout, and
characterization. The most important concepts that we covered in this chapter
were
● Tau, logical effort, and the prediction of delay
● Sizes of cells, and their drive strengths
● Cell importance
● The difference between gate-array macros, standard cells, and datapath
cells
3.10 Problems
* = difficult, ** = very difficult, *** = extremely difficult
3.1 (Pull resistance, 10 min.)
● a. Show that, for small V DS , an n -channel transistor looks like a resistor, R =
1/( b n ( V DD V t n )).
●
b. If V GS = V DD , V DS = 0, and k ' n = 200 m AV 2 (equal to the n -channel
transistor SPICE parameter KP in Table 2.1), find the pull resistance, R , for a
6/0.6 transistor in the linear region.
Answer: (b) 213 W .
3.2 (Inversion layer depth, 15 min.) In the absence of surface charge, Gausss law
demands continuity of the electric displacement vector, D = e E , at the silicon surface,
so that e ox E ox = e Si E Si , where e ox = 3.9, e Si = 11.7.
●
a. Assuming the potential at the surface is V GS V t = 2.5 V, calculate E ox and
E Si if T ox = 100 Å.
●
b. Assume that carrier density exp (q f /kT), where f is the potential; calculate
the distance below the surface at which the inversion charge density falls to 10
percent of its value at the surface.
c. Comment on the accuracy of your answers.
●
Answer: (a) 2.5 ¥ 10 8 Vm 1 , 0.833 ¥ 10 8 Vm 1 . (b) 7.16 Å.
3.3 (Depletion layer depth, 15 min.) The depth of the depletion region under the gate is
given by x d = ÷[ (2 e Si f s )/(qN A )], where f s = 2V T ln(N A /n i ) is the surface
potential at strong inversion. Calculate f s and x d assuming: e Si =1.0359 ¥ 10 10 Fm 1
, the substrate doping, N A = 1.4 ¥ 10 17 cm 3 , the intrinsic carrier concentration n i =
1.45 ¥ 10 10 cm 3 (at room temperature), and the thermal voltage V T = kT/q = 25.9
mV.
Answer: 0.833 V, 900 Å.
3.4 (Logical effort, 45 min.) Calculate the logical effort at each input of an AOI122
cell. Find an expression that allows you to calculate the logical effort for each input of
an AOI nnnn cell for n = 1, 2, 3.
3.5 (Gate-array macro design, 120 min.) Draw a 1X drive, two-input NAND cell using
the gate-array base cells shown in Figures 3.14 (a) 3.16 (lay a piece of thin paper over
the figures and draw the contacts and metal personalization only). Label the inputs and
outputs. Lay out a 1X drive, four-input NAND cell using the same base array cells.
Now lay out a 2X drive, four-input NAND cell (think about this one). Make sure that
you size your transistors properly to balance rise times and fall times.
3.6 (Flip-flop library, 20 min.) Suppose we wish to build a library of flip-flops. We
want to have flops with: positive-edge and negative-edge triggering: clear, preset
(either, both, or neither); synchronous or asynchronous reset and preset controls if
present (but not mixed on the same flip-flop); all flip-flops with or without scan as an
option; flip-flops with Q and Qbar (either or both). How many flip-flops is that?
(***) How would you attempt to prioritize which flip-flops to include in a library?
3.7 (AOI and OAI cell ratios, 30 min.) In Figure 2.13(c) we adjusted the sizes of the
transistors assuming that there was only one path through the n -channel and p
-channel stacks. Suppose that p -channel transistors A, B, C, and D are all on and p
-channel transistor E turns on. What is the equivalent resistance of the p -channel stack
in this case?
3.8 (**Eight-input AND, 60 min.) This question is an example in the paper by
Sutherland and Sproull [1991] on logical effort. Figure 3.24 shows three different
ways to design an eight-input AND cell, using NAND and NOR cells.
● a. Find the logical effort at each input for A, B, C. Assume a logic ratio of 2.
● b. Find the parasitic delay for A, B, C. Assume the parasitic delay of an inverter
is 0.6.
● c. Show that the path delays are given by the following equations where H is the
path electrical effort, if we ignore the nonideal delays:
●
(i) 2 (3.33 H ) 0.5 + 5.4 (alternative A)
●
(ii) 2 (3.33 H ) 0.5 + 3.6 (alternative B)
●
(iii) 4 (2.96 H ) 0.25 + 4.2 (alternative C)
d. Use these equations to determine the best alternative for H = 2 and H = 32.
●
FIGURE 3.24
An eight-input
AND cell
(Problem 3.8
).
3.9 (Special logic cells, 30 min.) Many ASIC cell libraries contain special logic cells.
For example the Compass libraries contain a two-input NAND cell with an inverted
input, FN01 = (A + B'). This saves routing area, is faster than using two separate cells,
and is useful because the combination of a two-input NAND gate with one inverted
input is heavily used by synthesis tools. Other special cells include:
● FN02 = MAJ3 = (A·B + A·C + B·C)'
● FN03 = AOI2-2 = ((A'·B') + (C·D))' = (A + B)(C' + D') = OA2-2
● FN04 = OAI2-2
● FN05 = A·B' = (A' + B)'
● a. Draw schematics for these cells.
●
●
b. Calculate the logical effort and logical area for each cell.
c. Can you explain where and why these cells might be useful?
3.10 (Euler paths, 60 min.) There are several ways to arrange the stacks in the AOI211
cell shown in Figure 3.25 . For example, the n -channel transistor A can be below B
without altering the function. Which arrangement would you predict gives a faster
delay from A to Z and why? The p -channel transistors A and B can be above or below
transistors C and D. How many distinct ways of arranging the transistors are there for
this cell? What effect do the different arrangements have on layout? What effects do
these different arrangements have on the cell performance?
FIGURE 3.25 There are several ways to arrange the transistors in this AOI211 cell
(Problem 3.10 ).
3.11 (*AOI and OAI cell efficiency, 60 min.) A standard-cell library data book
contains the following data:
● AOI221: t R = 1.061.15 ns; t F = 1.091.55 ns; C in = 0.210.28 pF; W C = 28.8
mm
● OAI221: t R = 0.771.05 ns; t F = 0.810.96 ns; C in = 0.250.39 pF; W C = 22.4
mm
( W C is the cell width, the cell height is 25.6 m m.) Calculate the (a) logical effort and
(b) logical area for the AOI221 and OAI221 cells.
The implementation of the OAI221 in this library uses a single stage,
OAI221 = OAI221(a1, a2, b1, b2, c),
whereas the AOI221 uses the following multistage implementation:
AOI221 = NOT(NAND(NAND(a1, a2), AOI21(b1, b2, c))).
(c) What are the alternative implementations for these two cells? (d) From your
answers attempt to explain the implementations chosen.
3.12 (**Logical efficiency, 60 min.) Extending Problem 3.11 , let us compare an
AOI33 with an OAI33 cell. (a) Calculate the logical effort and (b) logical areas for
these cells.
The AOI33 uses a single-stage implementation as follows:
AOI33 = aoi33(a1, a2, a3, b1, b2, b3).
The OAI33 uses the following multistage implementation:
OAI33 = not[nor[nor(a1, a2, a3), nor(b1, b2, b3)]].
(c) Calculate the path delay, D , as a function of path electrical effort, H , for both of
these implementations ignoring parasitic and nonideal delays. (d) Use Eq. 3.42 to
calculate the optimum path delay for these cells. (e) Compare and explain the
differences between your answers to parts d and e for H = 1, 2, 4, and 8.
The timing data from the data book is as follows (the cell height is 25.6 m m):
● AOI33: t R = 0.701.06 ns; t F = 0.721.15 ns; C in = 0.210.28 pF; W C = 35.2
mm
● OAI33: t R = 1.061.70 ns; t F = 1.421.98 ns; C in = 0.310.36 pF; W C = 48 m
m
(f) How does this data compare with your theoretical analysis?
3.13 (EXOR cells and logical effort, 60 min.) Show how to implement a two-input
EXOR cell using an AOI22 and two inverters. Using logical effort, compare this with
an implementation using an AOI21 cell and a NOR cell.
3.14 (***XNOR cells, 60 min.) Table 3.3 shows the implementation of XNOR cells
in a standard-cell library. Analyze this data using the concept of logical effort.
TABLE 3.3 Implementations of XNOR cells in CMOS (Problem 3.14 ).
Cell
Implementation
Library 1:
nand[or(a1,a2),nand(a1,a2)]
XNOR2D1
Library 2:
NOT[NOT[MUX[a1, NOT(a1),a2)]]
XNOR2D1
Library 1:
NOT[NOT[MUX(a1,NOT(a1),a2)]]
XNOR2D2
Library 2:
nand[or(a1,a2),nand(a1,a2)]
XNOR2D2
Library 1:
NOT[NOT[MUX(a1, NOT(a1), NOT(MUX(a3, NOT(a3),a2)))]]
XNOR3D1
Library 1:
NOT[NOT[MUX(a1, NOT(a1), NOT(MUX(a3, NOT(a3),a2)))]]
XNOR3D2
3.15 (***Extensions to logical effort, 60 min.) The path branching effort B is the
product of branching efforts:
b i . (3.47)
B=
i path
The branching effort is the ratio of the on-path plus off-path capacitance to the on-path
capacitance. The path effort F becomes the product of the path electrical effort, path
branching effort, and path logical effort:
F = GBH . (3.48)
Show that the path delay D is
gibihi+
D=
i path
p i . (3.49)
i path
(***) Show that the optimum path delay is then
D^ = NF 1/ N = N ( GBH ) 1/ N + P . (3.50)
3.16 (*Circuits from layout, 120 min.) Figure 3.26 shows a D flip-flop with clear
from a 1.0 m m standard-cell library. Figure 3.27 shows two layout views of this D
flip-flop. Construct the circuit diagram for this flip-flop, labeling the nodes and
transistors as shown. Include the transistor sizesuse estimates for transistors with 45°
gatesyou only need W/L values, you can assume the gate lengths are all L = 2 l , equal
to the minimum feature size. Label the inputs and outputs to the cell and identify their
functions.
FIGURE 3.26 A D flip-flop from a 1.0 m m standard-cell library (Problem 3.16 ).
3.17 (Flip-flop circuits, 30 min.) Draw the circuit schematic for a positive-edge
triggered D flip-flop with active-high set and reset (base your schematic on
Figure 2.18a, a negative-edgetriggered D flip-flop). Describe the problem when both
SET and RESET are high.
FIGURE 3.27 (Top) A standard cell showing the diffusion ( n -diffusion and p
-diffusion), poly, and contact layers (the n -well and p -well are not shown).
(Bottom) Shows the m1, contact, m2, and via layers. Problem 3.16 traces this circuit
for this cell.
If we want an active-high set or reset we can: (1) use an inverter on the set or reset
signal or (2) we can substitute NOR cells. Since NOR cells are slower than NAND
cells, which we do depends on whether we want to optimize for speed or area.
Thus, the largest flip-flop would be one with both Q and QN outputs, active high set
and resetrequiring four TX gates, three inverters (four of the seven we normally need
are replaced with NAND cells), four NAND cells, and two inverters to invert the set
and reset, making a total of 34 transistors, or 8.5 gates.
3.18 (Set and reset, 10 min.) Show how to add a synchronous set or a synchronous
reset to the flip-flop of Figure 2.18(a) using a two-input MUX.
3.19 (Clocked inverters, 45 min.) Using PSpice compare the delay of an inverter with
transmission gate with that of a clocked inverter using the G5 process SPICE
parameters from Table 2.1.
3.20 (S-R, T, J-K flip-flops, 30 min.) The characteristic equation for a D flip-flop is Q
t+1 = D. The characteristic equation for a J-K flip-flop is Q t+1 = J(Q t )' + K'Q t .
●
●
●
●
a. Show how you can build a J-K flip-flop using a D flip-flop.
b. The characteristic equation for a T flip-flop (toggle flip-flop) is Q t+1 = (Q t )' .
Show how to build a T flip-flop using a D flip-flop.
c. The characteristic equation does not show the timing behavior of a sequential
elementthe characteristic equation for a D latch is the same as that for a D
flip-flop. The characteristic equation for an S-R latch and an S-R flip-flop is Q
t+1 = S + R'Q t . An S-R flip-flop is sometimes called a pulse-triggered flip-flop.
Find out the behavior of an S-R latch and an S-R flip-flop and describe the
differences between these elements and a D latch and a D flip-flop.
d. Explain why it is probably not a good idea to use an S-R flip-flop in an ASIC
design.
3.21 (**Optimum logic, 60 min.) Suppose we have a fixed logic path of length n 1 .
We want to know how many (if any) buffer stages we should add at the output of this
path to optimize the total path delay given the output load capacitance.
● a. If the total number of stages is N (logic path of length n 1 plus N n 1
inverters), show that the total path delay is
n1
(pi+qi)+(N n
D^ = NF 1/ N +
1
)( p inv + q inv ) . (3.51)
i=1
The optimum number of stages is given by the solution to the following equation:
D^/N = /N ( NF
●
1/ N
+(N n
1
)( p inv + q inv ) ) = 0 . (3.52)
b. Show that the solutions to this equation can be written in terms of F 1/ N^ (the
optimum stage effort) where N^ is the optimum number of stages:
F 1/ N^ (1 ln F
1/ N^
) + ( p inv + q inv ) = 0 . (3.53)
3.22 (XOR and XNOR cells, 60 min.) Table 3.4 shows the implementations of twoand three-input XOR cells in an ASIC standard-cell library (D1 are the 1X drive cells,
and D2 are the 2X drive versions). Can you explain the choices for the two-input XOR
cell and complete the table for the three-input XOR cell?
TABLE 3.4 Implementations of XOR cells (Problem 3.22 ).
Actual implementation 1
Cell
XOR2D1 AOI21[a1, a2, NOR(a1,a2)]
XOR2D2 NOT[MUX(a1, not(a1), a2)]
Alternative implementation(s)
not[mux(a1, not(a1), a2)]
aoi22(a1, a2, not(a1), not(a2))
aoi21[a1, a2, nor(a1, a2)]
aoi22(a1, a2, not(a1), not(a2))
NOT[MUX[a1, not(a1), not(mux(a3, not(a3),
?
a2))]]
NOT[MUX[a1, not(a1), not(mux(a3, not(a3),
XOR3D2
?
a2))]]
XOR3D1
3.23 (Library density, 10 min.) Derive an upper limit on cell density as follows:
Assume a chip consists only of two-input NAND cells with no routing channels
between rows (often achievable in a 3LM process with over-the-cell routing).
● a. Explain how many vertical tracks you need to connect to a two-input NAND
cell, assuming each connection requires a separate track.
● b. If the NAND cell is 64 l high with a vertical track width of 8 l , calculate the
NAND cell area, carefully explaining any assumptions.
●
c. Calculate the cell density (in gate/mil 2 ) for a 0.35 m m process, l = 0.175 m
m.
Answer: 3 tracks, 47 m m 2 , 13.7 gates/mil 2 or 21 ¥ 103 gates/mm 2 .
3.24 (Gate-array density, 20 min.) The LSI Logic 10k and 100k gate arrays use a
four-transistor base cell, equivalent to 1 gate, that is 12 tracks high and 3 tracks wide.
● a. If a metal track is 8l, where l = 0.75 m m for a 1.5 m m technology, calculate
the area of the LSI Logic base cell A L in mil 2 .
●
b. If we could use every base cell in the gate array, the cell density would be D G
= 1/ A L . Assume that, because of routing area and inefficiency of the gate
array, we can use only 50 percent of the base cells for logic. What is D G for the
LSI Logic 1.5 m m array?
●
c. Chip cell density D G is about 1.0 gate/mil 2 for a 1 m m technology (a
two-input NAND cell occupies an area 25 m m on a side in a technology whose
transistors are 1 m m long). This can change by a factor of 2 or more for a
gate-array/standard-cell ASIC or high-density/high-performance library.
Assume that cell density D G scales ideally with technology. If the minimum
feature size of a technology is 2l, then D G 1/ l 2 . Thus, for example, a 1.5 m m
technology should have a cell density of roughly (1/1.5) 2 gates/mil 2 . How does
this agree with your estimate for the LSI Logic array?
3.25 (SiArc RAM, 10 min.) Suppose we need 16 k-bit of SRAM and 20 k-gate of
random logic on a channelless gate array. Assume a base cell with four transistors and
that we can build a RAM cell using two of these base cells. The RAM bits will require
32k base cells and the random logic will require 20k base cells. Suppose the base cell
area is 12 tracks high, 3 tracks wide, and the horizontal and vertical track spacing is
equal at 8 l .
● a. Calculate the total area of the base cells we need. Now suppose we redesign
the gate-array base cell so that we can build a RAM bit cell using a single base
cell that is 20 tracks high, 3 tracks wide, and has 4 logic cell transistors and 4
RAM cell transistors. Assume that since the base cell now contains 8 transistors
we only need 12 k base cells to implement 20 k-gate of random logic (the new
base cell is less efficient than the old cell for implementing random logic).
●
●
b. Calculate the base cell area using the new base cell design.
c. Comment.
Answer: 1.2 ¥ 108 l 2 , 1.1 ¥ 108 l 2 .
3.26 (***Gate-array base cell, 60 min.) Figure 3.28 shows a simple gate-array base
cell. Use the design rules shown in Table 2.16 (Problem 2.33) to calculate the
minimum size of this base cell. Do this by determining which design rules apply to the
labels shown adjacent to each space or width in the figure. In most cases each of the
spaces is determined by a single rule related to the region labeled, for example, the
contact width labeled 'cc' is 2 l determined by rule C.1, the exact contact size. There is
one exception, shown in the figure. Space 'aa' (bounding box, BB, to edge of pdiff) and
width 'bb' (edge of pdiff to edge of contact) are determined by the minimum space
labeled 'xx' (bounding box, BB, to poly edge) and width 'yy' (edge of poly to edge of
contact). Space 'xx' is one half of the poly to poly spacing over field (rule P.4) because
two base cells abut as shown in the figure. Width 'yy' is equal to the minimum poly
overlap of contact (rule C.3). The distance 'aa + bb' is thus determined by the minimum
distance 'xx + yy', as shown. The other distances are more straightforward to
determine.
Answer: 40 l high by 26.25 l wide.
FIGURE 3.28 A simple gate-array base cell (Problem 3.26 ).
3.27 (CIF, 15 min.) Here is the part of the CIF for a standard cell that describes the n
-well (CWN) and p -well (CWP) structure. The statement B length height xCenter,
yCenter is CIF for a box (CIF dimensions are in centimicrons, 0.01 m m):
DS1;LCWN;B6000
1560 13600,3660;B2480 60 11840,2850;B2320 60 15440,2850;LCWP;B680 60
13740,2730;B6000 1380 13600,2010;
● a. Draw the wells and BB. Label the dimensions in microns and l (l = 0.4 m m ) .
● b. This is a double-entry cell with m2 connectors at top and bottom. For this cell
library the cell AB is 3 l (120 centimicrons, determined by the well rules) inside
the cell BB on all sides. What is the size of the cell AB in microns and l ?
● c. The vertical (m2) routing pitch (the distance between centers of adjacent
vertical m2 interconnect lines) is equal to the vertical track spacing and is 8 l
(320 centimicrons). How many vertical tracks are there in this cell?
3.28 (CIF, 60 min.) Figure 3.29 shows an example of CIF that describes a single
rectangle (box) of m1 with an accompanying label.
(CIF written by the Tanner Research layout editor: L-Edit);
(TECHNOLOGY: VLSIcmn6);
(DATE: Thu, Jun 27, 1996);
(FABCELL: NONE);
(SCALING: 1 CIF Unit = 1/120 Lambda, 1 Lambda = 3/10
Microns);
DS1 2 8;
9 Cell0;
94 LabelText 60 180 CM;
LCM;
B 240 120 120 300;
DF;
E
FIGURE 3.29 A simple CIF example (Problem 3.28 ).
The CIF code has the following meaning:
● Lines 15 are CIF comments.
● Line 6 is a definition start for symbol 1 and marks the beginning of a symbol
definition (a symbol is a piece of layout, symbol numbers are unique identifiers).
The integers 2 and 8 define a scaling factor 2/8 (= 0.25) to be applied to distance
measurements (the CIF unit, after scaling, is a centimicron or 0.01 m m).
● Line 7 is a user extension or expansion (all extensions begin with a digit). L-Edit
uses user extension 9 for cell names ( Cell0 in this case).
● Line 8 is a user extension for a cell label located on layer CM (first-level metal
in this technology) located at x = 60 units, y = 180 units (60, 180). Applying the
scaling factor of 0.25, this translates to (15, 45) in centimicrons or (0.5, 1.5) in
lambda.
● Line 9 is a layer specification or command (begins with L ).
● Line 10 is a box command and describes a box with (in order) length, L , of 240
units; width, W , of 120 units; and center at x = 120 units and y = 300 units.
●
●
Applying the DS scaling factor of 0.25 gives L = 60, W = 30, center = (30,
75)(centimicrons) or L = 2, W = 1, center = (1, 2.5) in lambda.
Line 11 is the definition finish ( DS and DF must be paired).
Line 12 is the end command .
You receive a CIF file whose mask-layer names are different from those in the
technology file that you are using. The mapping between layer names is shown in
Table 3.5 .
●
●
a. Write an awk or sed script (or use another automated editing technique) to
change the layer names. At this point you realize that there are several layer
names ( LTRAN , LESD ) in the input file that are not required (or recognized)
by your layout software (these particular examples are for software to recognize
unused transistors in a gate array, and for an ESD implant in I/O devices).
b. (**) Enhance your script to completely remove an unwanted layer from the
CIF file. There are some comments and CIF constructs that are not supported by
your editor. Here is one example:
(BB: 39.2,82.6 72.8,122.5 in lambda);
Comments in this format specify the AB and BB for the cell. Other CIF user
extensions, not recognized by your software, are used for labels for power supplies and
connectors:
4A 1680 3360 2800 4844;
4M a 1 2292 4028 2356 4092 CM2;
4M z 4 2639 4090 2703 4154 CM2;
4X vdd 2 2800 4774 180 * * metal;
● c. (**) Add code to remove all these constructs from the CIF file.
TABLE 3.5
Input mask
label
LCNW
LCPW
none 4
LCP
Mapping CIF layer names (Problem 3.28 ). 2
MOSIS mask Input mask MOSIS mask Input mask
label
label
label
label
LCND 3
CSN
LCM2
CWN
CWP
CSP
LCC2
LCPD 2
LCC 5
CAA
CCA
LCM3
CPG
LCM
CMF
none
MOSIS mask
label
CMS
CVS
CMT
COG
1. MUX(a, b, c) = a·c + b·c'
2. This mapping is for input to a layout editor; the CIF may have to be modified again
when written out from the layout editor.
3. Map the input diffusion layers to the implant select layers. On output from the
layout editor these layers should be sized up to generate the real implant select layers.
4. There is no active layer in the input. Instead use the diffusion layers.
5. There is only one contact layer in the input; map all contacts to CAA.There is no
easy way to generate the MOSIS CCP layer. This prevents handling of poly and
3.11 Bibliography
The first part of this chapter is covered in greater detail in Weste and Eshraghian
[1993]. The experiments presented in this chapter may be reproduced using
PSpice and Probe from MicroSim ( http://www.microsim.com ). A free
CD-ROM is available from MicroSim containing PC versions of their software
together with reference manuals in Adobe Acrobat format that are readable on all
platforms. Other PSpice and Probe versions are available online including the
Apple Macintosh version used in this book (which requires a math coprocessor).
Mukherjee [1986] covers CMOS process and fabrication issues. Analog ASIC
design is covered by Haskard and May [1988] and Trontelj et al. [1989]. Chen
[1990] and Uyemura [1992] provide more depth on analysis of combinational
and sequential logic design. The book by Diaz [1995] includes material on I/O
cell design for ESD protection that is hard to find. The patent literature is the best
reference for high-speed and quiet I/O design. Wakerlys book [1994] on digital
design is an excellent reference for logic design in general (including sequential
logic, metastability, and binary arithmetic), though it emphasizes PLDs rather
than ASICs.
3.12 References
Chen, J. Y. 1990. CMOS Devices and Technology for VLSI. Englewood Cliffs,
NJ: Prentice-Hall, 348 p. ISBN 0-13-138082-6. TK7874.C523.
Diaz, C. H., et al. 1995. Modeling of Electrical Overstress in Integrated Circuits.
Norwell, MA: Kluwer Academic, 148 p. ISBN 0-7923-9505-0. TK7874.D498.
Includes 101 references. Good introduction to ESD problems and models. Most
of the book deals with thermal analysis and thermal stress modeling.
Haskard, M. R., and I. C. May. 1988. Analog VLSI Design: nMOS and CMOS.
Englewood Cliffs, NJ: Prentice-Hall, 243 p. ISBN 0-13-032640-2.
TK7874.H392.
Mukherjee, A. 1986. Introduction to nMOS and CMOS VLSI Systems Design.
Englewood Cliffs, NJ: Prentice-Hall, 370 p. ISBN 0-13-490947-X. TK7874.M86.
Sutherland, I. E., and R. F. Sproull. 1991. Logical effort: designing for speed on
the back of an envelope. In Proceedings of the Advanced Research in VLSI,
Santa Cruz, CA, pp. 116. This reference may be hard to find, but similar
treatments (without the terminology of logical effort) are given in Mead and
Conway, or Weste and Eshraghian.
Trontelj, J., et al. 1989. Analog Digital ASIC Design. New York: McGraw-Hill,
249 p. ISBN 0-07-707300-2. TK7874.T76.
Uyemura, J. P. 1992. Circuit Design for CMOS VLSI. Boston: Kluwer Academic
Publishers, 450 p. ISBN 0-7923-9184-5. TK7874.U93. See also: J. P. Uyemura,
Fundamentals of MOS Digital Integrated Circuits, Reading, MA:
Addison-Wesley, 1988, 624 p. ISBN 0-201-13318-0. TK7874.U94. Reference for
basic circuit equations related to NMOS and CMOS logic design.
Wakerly, J. F. 1994. Digital Design: Principles and Practices. 2nd ed. Englewood
Cliffs, NJ: Prentice-Hall, 840 p. ISBN 0-13-211459-3. TK7874.65.W34.
Introduction to logic design covering: binary arithmetic, CMOS and TTL,
combinational logic, PLDs, sequential logic, memory, and the IEEE standard
logic symbols.
Weste, N. H. E., and K. Eshraghian. 1993. Principles of CMOS VLSI Design: A
Systems Perspective . 2nd ed. Reading, MA: Addison-Wesley, 713 p. ISBN
0-201-53376-6. TK7874.W46. See also the first edition of this book.
L ast E d ited by S P 1411 2 0 0 4
PROGRAMMABLE ASICs
There are two types of programmable ASICs: programmable logic devices
(PLDs) and field-programmable gate arrays (FPGAs). The distinction between
the two is blurred. The only real difference is their heritage. PLDs started as
small devices that could replace a handful of TTL parts, and they have grown to
look very much like their younger relations, the FPGAs. We shall group both
types of programmable ASICs together as FPGAs.
An FPGA is a chip that you, as a systems designer, can program yourself. An IC
foundry produces FPGAs with some connections missing. You perform design
entry and simulation. Next, special software creates a string of bits describing the
extra connections required to make your designthe configuration file . You then
connect a computer to the chip and program the chip to make the necessary
connections according to the configuration file. There is no customization of any
mask level for an FPGA, allowing the FPGA to be manufactured as a standard
part in high volume.
FPGAs are popular with microsystems designers because they fill a gap between
TTL and PLD design and modern, complex, and often expensive ASICs. FPGAs
are ideal for prototyping systems or for low-volume production. FPGA vendors
do not need an IC fabrication facility to produce the chips; instead they contract
IC foundries to produce their parts. Being fabless relieves the FPGA vendors of
the huge burden of building and running a fabrication plant (a new submicron fab
costs hundreds of millions of dollars). Instead FPGA companies put their effort
into the FPGA architecture and the software, where it is much easier to make a
profit than building chips. They often sell the chips through distributors, but sell
design software and any necessary programming hardware directly.
All FPGAs have certain key elements in common. All FPGAs have a regular
array of basic logic cells that are configured using a programming technology .
The chip inputs and outputs use special I/O logic cells that are different from the
basic logic cells. A programmable interconnect scheme forms the wiring between
the two types of logic cells. Finally, the designer uses custom software, tailored
to each programming technology and FPGA architecture, to design and
implement the programmable connections. The programming technology in an
FPGA determines the type of basic logic cell and the interconnect scheme. The
logic cells and interconnection scheme, in turn, determine the design of the input
and output circuits as well as the programming scheme.
The programming technology may or may not be permanent. You cannot undo
the permanent programming in one-time programmable ( OTP ) FPGAs.
Reprogrammable or erasable devices may be reused many times. We shall
discuss the different programming technologies in the following sections.
4.1 The Antifuse
An antifuse is the opposite of a regular fusean antifuse is normally an open
circuit until you force a programming current through it (about 5 mA). In a poly
diffusion antifuse the high current density causes a large power dissipation in a
small area, which melts a thin insulating dielectric between polysilicon and
diffusion electrodes and forms a thin (about 20 nm in diameter), permanent, and
resistive silicon link . The programming process also drives dopant atoms from
the poly and diffusion electrodes into the link, and the final level of doping
determines the resistance value of the link. Actel calls its antifuse a
programmable low-impedance circuit element ( PLICE ).
Figure 4.1 shows a polydiffusion antifuse with an oxidenitrideoxide ( ONO )
dielectric sandwich of: silicon dioxide (SiO 2 ) grown over the n -type antifuse
diffusion, a silicon nitride (Si 3 N 4 ) layer, and another thin SiO 2 layer. The
layered ONO dielectric results in a tighter spread of blown antifuse resistance
values than using a single-oxide dielectric. The effective electrical thickness is
equivalent to 10nm of SiO 2 (Si 3 N 4 has a higher dielectric constant than SiO 2 ,
so the actual thickness is less than 10 nm). Sometimes this device is called a fuse
even though it is an anti fuse, and both terms are often used interchangeably.
FIGURE 4.1 Actel antifuse. (a) A cross section. (b) A simplified drawing. The
ONO (oxidenitrideoxide) dielectric is less than 10 nm thick, so this diagram is
not to scale. (c) From above, an antifuse is approximately the same size as a
contact.
The fabrication process and the programming current control the average
resistance of a blown antifuse, but values vary as shown in Figure 4.2 . In a
particular technology a programming current of 5 mA may result in an average
blown antifuse resistance of about 500 W . Increasing the programming current
to 15 mA might reduce the average antifuse resistance to 100 W . Antifuses
separate interconnect wires on the FPGA chip and the programmer blows an
antifuse to make a permanent connection. Once an antifuse is programmed, the
process cannot be reversed. This is an OTP technology (and radiation hard). An
Actel 1010, for example, contains 112,000 antifuses (see Table 4.1 ), but we
typically only need to program about 2 percent of the fuses on an Actel chip.
TABLE 4.1
Number of
antifuses on Actel
FPGAs.
Device Antifuses
A1010 112,000
A1020 186,000
A1225 250,000
A1240 400,000
A1280 750,000
FIGURE 4.2 The resistance of blown Actel antifuses. The
average antifuse resistance depends on the programming
current. The resistance values shown here are typical for a
programming current of 5 mA.
To design and program an Actel FPGA, designers iterate between design entry
and simulation. When they are satisfied the design is correct they plug the chip
into a socket on a special programming box, called an Activator , that generates
the programming voltage. A PC downloads the configuration file to the Activator
instructing it to blow the necessary antifuses on the chip. When the chip is
programmed it may be removed from the Activator without harming the
configuration data and the chip assembled into a system. One disadvantage of
this procedure is that modern packages with hundreds of thin metal leads are
susceptible to damage when they are inserted and removed from sockets. The
advantage of other programming technologies is that chips may be programmed
after they have been assembled on a printed-circuit boarda feature known as
in-system programming ( ISP ).
The Actel antifuse technology uses a modified CMOS process. A double-metal,
single-poly CMOS process typically uses about 12 masksthe Actel process
requires an additional three masks. The n- type antifuse diffusion and antifuse
polysilicon require an extra two masks and a 40 nm (thicker than normal) gate
oxide (for the high-voltage transistors that handle 18 V to program the antifuses)
uses one more masking step. Actel and Data General performed the initial
experiments to develop the PLICE technology and Actel has licensed the
technology to Texas Instruments (TI).
The programming time for an ACT 1 device is 5 to 10 minutes. Improvements in
programming make the programming time for the ACT 2 and ACT 3 devices
about the same as the ACT 1. A 5-day work week, with 8-hour days, contains
about 2400 minutes. This is enough time to program 240 to 480 Actel parts per
week with 100 percent efficiency and no hardware down time. A production
schedule of more than 1000 parts per month requires multiple or gang
programmers.
4.1.1 MetalMetal Antifuse
Figure 4.3 shows a QuickLogic metalmetal antifuse ( ViaLink ). The link is an
alloy of tungsten, titanium, and silicon with a bulk resistance of about 500 mW
cm.
FIGURE 4.3 Metalmetal antifuse. (a) An idealized (but to scale) cross section
of a QuickLogic metalmetal antifuse in a two-level metal process. (b) A metal
metal antifuse in a three-level metal process that uses contact plugs. The
conductive link usually forms at the corner of the via where the electric field is
highest during programming.
There are two advantages of a metalmetal antifuse over a polydiffusion antifuse.
The first is that connections to a metalmetal antifuse are direct to metalthe
wiring layers. Connections from a polydiffusion antifuse to the wiring layers
require extra space and create additional parasitic capacitance. The second
advantage is that the direct connection to the low-resistance metal layers makes it
easier to use larger programming currents to reduce the antifuse resistance. For
example, the antifuse resistance R • 0.8/ I , with the programming current I in mA
and R in W , for the QuickLogic antifuse. Figure 4.4 shows that the average
QuickLogic metalmetal antifuse resistance is approximately 80 W (with a
standard deviation of about 10 W ) using a programming current of 15 mA as
opposed to an average antifuse resistance of 500 W (with a programming current
of 5 mA) for a polydiffusion antifuse.
FIGURE 4.4 Resistance values for
the QuickLogic metalmetal
antifuse. A higher programming
current (about 15 mA), made
possible partly by the direct
connections to metal, has reduced
the antifuse resistance from the
polydiffusion antifuse resistance
values shown in Figure 4.2 .
The size of an antifuse is limited by the resolution of the lithography equipment
used to makes ICs. The Actel antifuse connects diffusion and polysilicon, and
both these materials are too resistive for use as signal interconnects. To connect
the antifuse to the metal layers requires contacts that take up more space than the
antifuse itself, reducing the advantage of the small antifuse size. However, the
antifuse is so small that it is normally the contact and metal spacing design rules
that limit how closely the antifuses may be packed rather than the size of the
antifuse itself.
An antifuse is resistive and the addition of contacts adds parasitic capacitance.
The intrinsic parasitic capacitance of an antifuse is small (approximately 12 fF in
a 1 m m CMOS process), but to this we must add the extrinsic parasitic
capacitance that includes the capacitance of the diffusion and poly electrodes (in
a polydiffusion antifuse) and connecting metal wires (approximately 10 fF).
These unwanted parasitic elements can add considerable RC interconnect delay if
the number of antifuses connected in series is not kept to an absolute minimum.
Clever routing techniques are therefore crucial to antifuse-based FPGAs.
The long-term reliability of antifuses is an important issue since there is a
tendency for the antifuse properties to change over time. There have been some
problems in this area, but as a result we now know an enormous amount about
this failure mechanism. There are many failure mechanisms in ICs
electromigration is a classic exampleand engineers have learned to deal with
these problems. Engineers design the circuits to keep the failure rate below
acceptable limits and systems designers accept the statistics. All the FPGA
vendors that use antifuse technology have extensive information on long-term
reliability in their data books.
4.2 Static RAM
An example of static RAM ( SRAM ) programming technology is shown in
Figure 4.5 . This Xilinx SRAM configuration cell is constructed from two
cross-coupled inverters and uses a standard CMOS process. The configuration
cell drives the gates of other transistors on the chipeither turning pass transistors
or transmission gates on to make a connection or off to break a connection.
FIGURE 4.5 The Xilinx SRAM
(static RAM) configuration cell.
The outputs of the cross-coupled
inverter (configuration control)
are connected to the gates of
pass transistors or transmission
gates. The cell is programmed
using the WRITE and DATA
lines.
The advantages of SRAM programming technology are that designers can reuse
chips during prototyping and a system can be manufactured using ISP. This
programming technology is also useful for upgradesa customer can be sent a
new configuration file to reprogram a chip, not a new chip. Designers can also
update or change a system on the fly in reconfigurable hardware .
The disadvantage of using SRAM programming technology is that you need to
keep power supplied to the programmable ASIC (at a low level) for the volatile
SRAM to retain the connection information. Alternatively you can load the
configuration data from a permanently programmed memory (typically a
programmable read-only memory or PROM ) every time you turn the system on.
The total size of an SRAM configuration cell plus the transistor switch that the
SRAM cell drives is also larger than the programming devices used in the
antifuse technologies.
4.3 EPROM and EEPROM
Technology
Altera MAX 5000 EPLDs and Xilinx EPLDs both use UV-erasable electrically
programmable read-only memory ( EPROM ) cells as their programming
technology. Altera's EPROM cell is shown in Figure 4.6 . The EPROM cell is
almost as small as an antifuse. An EPROM transistor looks like a normal MOS
transistor except it has a second, floating, gate (gate1 in Figure 4.6 ). Applying a
programming voltage V PP (usually greater than 12 V) to the drain of the nchannel EPROM transistor programs the EPROM cell. A high electric field
causes electrons flowing toward the drain to move so fast they jump across the
insulating gate oxide where they are trapped on the bottom, floating, gate. We say
these energetic electrons are hot and the effect is known as hot-electron injection
or avalanche injection . EPROM technology is sometimes called floating-gate
avalanche MOS ( FAMOS ).
FIGURE 4.6 An EPROM transistor. (a) With a high (> 12 V) programming
voltage, V PP , applied to the drain, electrons gain enough energy to jump onto
the floating gate (gate1). (b) Electrons stuck on gate1 raise the threshold voltage
so that the transistor is always off for normal operating voltages. (c) Ultraviolet
light provides enough energy for the electrons stuck on gate1 to jump back to
the bulk, allowing the transistor to operate normally.
Electrons trapped on the floating gate raise the threshold voltage of the nchannel EPROM transistor ( Figure 4.6 b). Once programmed, an n- channel
EPROM device remains off even with VDD applied to the top gate. An
unprogrammed n- channel device will turn on as normal with a top-gate voltage
of VDD . The programming voltage is applied either from a special programming
box or by using on-chip charge pumps. Exposure to an ultraviolet (UV) lamp will
erase the EPROM cell ( Figure 4.6 c). An absorbed light quantum gives an
electron enough energy to jump from the floating gate. To erase a part we place it
under a UV lamp (Xilinx specifies one hour within 1 inch of a 12,000 m Wcm 2
source for its EPLDs). The manufacturer provides a software program that checks
to see if a part is erased. You can buy an EPLD part in a windowed package for
development, erase it, and use it again, or buy it in a nonwindowed package and
program (or burn) the part once only for production. The packages get hot while
they are being erased, so that windowed option is available with only ceramic
packages, which are more expensive than plastic packages.
Programming an EEPROM transistor is similar to programming an UV-erasable
EPROM transistor, but the erase mechanism is different. In an EEPROM
transistor an electric field is also used to remove electrons from the floating gate
of a programmed transistor. This is faster than using a UV lamp and the chip does
not have to be removed from the system. If the part contains circuits to generate
both program and erase voltages, it may use ISP.
4.4 Practical Issues
System companies often select an ASIC technology first, which narrows the
choice of software design tools. The software then influences the choice of
computer. Most computer-aided engineering ( CAE ) software for FPGA design
uses some type of security. For workstations this usually means floating licenses
(any of n users on a network can use the tools) or node-locked licenses (only n
particular computers can use the tools) using the hostid (or host I.D., a serial
number unique to each computer) in the boot EPROM (a chip containing start-up
instructions). For PCs this is a hardware key, similar to the Viewlogic key
illustrated in Figure 4.7 . Some keys use the serial port (requiring extra cables and
adapters); most now use the parallel port. There are often conflicts between keys
and other hardware/software. For example, for a while some security keys did not
work with the serial-port driver on Intel motherboardsusers had to buy another
serial-port I/O card.
FIGURE 4.7 CAE companies use hardware security keys that fit
at the back of a PC (this one is shown at about one-half the real
size). Each piece of software requires a separate key, so that a
typical design system may have a half dozen or more keys
daisy-chained on one socket. This presents both mechanical and
software conflict problems. Software will not run without a key,
so it is easily possible to have $60,000 worth of keys attached to
a single PC.
Most FPGA vendors offer software on multiple platforms. The performance
difference between workstations and PCs is becoming blurred, but the time taken
for the place-and-route step for Actel and Xilinx designs seems to remain
constanttypically taking tens of minutes to over an hour for a large design
bounded by designers tolerances.
A great deal of time during FPGA design is spent in schematic entry, editing
files, and documentation. This often requires moving between programs and this
is difficult on IBM-compatible PC platforms. Currently most large CAD and
CAE programs completely take over the PC; for example you cannot always run
third-party design entry and the FPGA vendor design systems simultaneously.
There are many other factors to be considered in choosing hardware:
● Software packages are normally less expensive on a PC.
● Peripherals are less expensive and easier to configure on a PC.
●
●
●
Maintenance contracts are usually necessary and expensive for
workstations.
There is a much larger network of users to provide support for PC users.
It is easier to upgrade a PC than a workstation.
4.4.1 FPGAs in Use
I once placed an order for a small number of FPGAs for prototyping and received
a sales receipt with a scheduled shipping date three months away. Apparently,
two customers had recently disrupted the vendors product planning by placing
large orders. Companies buying parts from suppliers often keep an inventory to
cover emergencies such as a defective lot or manufacturing problems. For
example, assume that a company keeps two months of inventory to ensure that it
has parts in case of unforeseen problems. This risk inventory or safety supply, at
a sales volume of 2000 parts per month, is 4000 parts, which, at an ASIC price of
$5 per part, costs the company $20,000. FPGAs are normally sold through
distributors, and, instead of keeping a risk inventory, a company can order parts
as it needs them using a just-in-time ( JIT ) inventory system. This means that the
distributors rather than the customer carry inventory (though the distributors wish
to minimize inventory as well). The downside is that other customers may change
their demands, causing unpredictable supply difficulties.
There are no standards for FPGAs equivalent to those in the TTL and PLD
worlds; there are no standard pin assignments for VDD or GND, and each FPGA
vendor uses different power and signal I/O pin arrangements. Most FPGA
packages are intended for surface-mount printed-circuit boards ( PCBs ).
However, surface mounting requires more expensive PCB test equipment and
vapor soldering rather than bed-of-nails testers and surface-wave soldering. An
alternative is to use socketed parts. Several FPGA vendors publish
socket-reliability tests in their data books.
Using sockets raises its own set of problems. First, it is difficult to find wire-wrap
sockets for surface-mount parts. Second, sockets may change the pin
configuration. For example, when you use an FPGA in a PLCC package and plug
it into a socket that has a PGA footprint, the resulting arrangement of pins is
different from the same FPGA in a PGA package. This means you cannot use the
same board layout for a prototype PCB (which uses the socketed PLCC part) as
for the production PCB (which uses the PGA part). The same problem occurs
when you use through-hole mounted parts for prototyping and surface-mount
parts for production. To deal with this you can add a small piece to your
prototype board that you use as a converter. This can be sawn off on the
production boardssaving a board iteration.
Pin assignment can also cause a problem if you plan to convert an FPGA design
to an MGA or CBIC. In most cases it is desirable to keep the same pin
assignment as the FPGA (this is known as pin locking or I/O locking ), so that the
same PCB can be used in production for both types of devices. There are often
restrictions for custom gate arrays on the number and location of power pads and
package pins. Systems designers must consider these problems before designing
the FPGA and PCB.
4.5 Specifications
All FPGA manufactures are continually improving their products to increase
performance and reduce price. Often this means changing the design of an FPGA
or moving a part from one process generation to the next without changing the
part number (and often without changing the specifications).
FPGA companies usually explain their part history in their data books. 1 The
following history of Actel FPGA ACT 1 part numbers illustrates changes typical
throughout the IC industry as products develop and mature:
● The Actel ACT 1 A1010/A1020 used a 2 m m process.
● The Actel A1010A/A1020A used a 1.2 m m process.
● The Actel A1020B was a die revision (including a shrink to a 1.0 m m
process). At this time the A1020, A1020A, and A1020B all had different
speeds.
● Actel graded parts into three speed bins as they phased in new processes,
dropping the distinction between the different die suffixes.
● At the same time as the transition to die rev. 'B', Actel began specifying
timing at worst-case commercial conditions rather than at typical
conditions.
From this history we can see that it is often possible to have parts from the same
family that use different circuit designs, processes, and die sizes, are
manufactured in different locations, and operate at very different speeds. FPGA
companies ensure that their products always meet the current published
worst-case specifications, but there is no guarantee that the average performance
follows the typical specifications, and there are usually no best-case
specifications.
There are also situations in which two parts with identical part numbers can have
different performancewhen different ASIC foundries produce the same parts.
Since FPGA companies are fabless, second sourcing is very common. For
example, TI began making the TPC1010A/1020A to be equivalent to the original
Actel ACT 1 parts produced elsewhere. The TI timing information for the
TPC1010A/1020A was the same as the 2 m m Actel specifications, but TI used a
faster 1.2 m m process. This meant that equivalent parts with the same part
numbers were much faster than a designer expected. Often this type of
information can only be obtained by large customers in the form of a
qualification kit from FPGA vendors.
A similar situation arises when the FPGA manufacturer adjusts its product mix
by selling fast parts under a slower part number in a procedure known as
down-binning . This is not a problem for synchronous designs that always work
when parts are faster than expected, but is another reason to avoid asynchronous
designs that may not always work when parts are much faster than expected.
1. See, for example, p.1-8 of the Xilinx 1994 data book.
4.6 PREP Benchmarks
Which type of FPGA is best? This is an impossible question to answer. The
Programmable Electronics Performance Company ( PREP ) is a nonprofit
organization that organized a series of benchmarks for programmable ASICs.
The nine PREP benchmark circuits in the version 1.3 suite are:
1. An 8-bit datapath consisting of 4:1 MUX, register, and shift-register
2. An 8-bit timercounter consisting of two registers, a 4:1 MUX, a counter
and a comparator
3. A small state machine (8 states, 8 inputs, and 8 outputs)
4. A larger state machine (16 states, 8 inputs, and 8 outputs)
5. An ALU consisting of a 4 ¥ 4 multiplier, an 8-bit adder, and an 8-bit
register
6. A 16-bit accumulator
7. A 16-bit counter with synchronous load and enable
8. A 16-bit prescaled counter with load and enable
9. A 16-bit address decoder
The data for these benchmarks is archived at http://www.prep.org . PREPs
online information includes Verilog and VHDL source code and test benches
(provided by Synplicity) as well as additional synthesis benchmarks including a
bit-slice processor, multiplier, and R4000 MIPS RISC microprocessor.
One problem with the FPGA benchmark suite is that the examples are small,
allowing FPGA vendors to replicate multiple instances of the same circuit on an
FPGA. This does not reflect the way an FPGA is used in practice. Another
problem is that the FPGA vendors badly misused the results. PREP made the data
available in a spreadsheet form and thus inadvertently challenged the marketing
department of each FPGA vendor to find a way that company could claim to win
the benchmarks (usually by manipulating the data using a complicated weighting
scheme). The PREP benchmarks do demonstrate the large variation in
performance between different FPGA architectures that results from differences
in the type and mix of logic. This shows that designers should be careful in
evaluating others results and performing their own experiments.
4.7 FPGA Economics
FPGA vendors offer a wide variety of packaging, speed, and qualification
(military, industrial, or commercial) options in each family. For example, there
are several hundred possible part combinations for the Xilinx LCA series.
Figure 4.8 shows the Xilinx part-naming convention, which is similar to that used
by other FPGA vendors.
FIGURE 4.8 Xilinx part-naming
convention.
Table 4.2 shows the various codes used by manufacturers in their FPGA part
numbers. Not all possible part combinations are available, not all packaging
combinations are available, and not all I/O options are available in all packages.
For example, it is quite common for an FPGA vendor to offer a chip that has
more I/O cells than pins on the package. This allows the use of cheaper plastic
packages without having to produce separate chip designs for each different
package. Thus a customer can buy an Actel A1020 that has 69 I/O cells in an
inexpensive 44-pin PLCC package but uses only 34 pins for I/Othe other 10 (=
44 34) pins are required for programming and power: three for GND, four for
VDD, one for MODE (a pin that controls four other multifunction pins), and one
for VPP (the programming voltage). A designer who needs all 69 I/Os can buy
the A1020 in a bigger package. Tables in the FPGA manufacturers data books
show the availability, and these matrices change constantly.
TABLE 4.2 Programmable ASIC part codes.
Item
Code
Description
Code
Manufacturers A
Actel
ATT
code
XC
Xilinx
isp
EPM
Altera MAX
M5
EPF
CY7C
Package
Altera FLEX
QL
Cypress
plastic J-leaded
PL or PC
VQ
chip carrier, PLCC
Description
AT&T (Lucent)
Lattice Logic
AMD MACH 5 is on
the device
QuickLogic
very thin quad flatpack,
VQFP
type
Application
plastic quad
flatpack, PQFP
ceramic quad
CQ or CB
flatpack, CQFP
ceramic pin-grid
PG
array, PGA
C
commercial
I
industrial
M
military
PQ
TABLE 4.3 1992 base Actel
FPGA prices.
Actel part
1H92 base price
A1010A-PL44C $23.25
A1020A-PL44C $43.30
A1225-PQ100C $105.00
A1240-PQ144C $175.00
A1280-PQ160C $305.00
TQ
PP
thin plastic flatpack,
TQFP
plastic pin-grid array,
PPGA
WB, PB ball-grid array, BGA
B
E
MIL-STD-883
extended
TABLE 4.4 1992 base Xilinx XC3000
FPGA prices.
Xilinx part
1H92 base price
XC3020-50PC68C $26.00
XC3030-50PC44C $34.20
XC3042-50PC84C $52.00
XC3064-50PC84C $87.00
XC3090-50PC84C $133.30
4.7.1 FPGA Pricing
Asking How much do FPGAs cost? is rather like asking How much does a car
cost? Prices of cars are published, but pricing schemes used by semiconductor
manufactures are closely guarded secrets. Many FPGA companies use a pricing
strategy based on a cost model that uses a series of multipliers or adders for each
part option to calculate the suggested price for their distributors. Although the
FPGA companies will not divulge their methods, it is possible to reverse engineer
these factors to create a pricing matrix.
Many FPGA vendors sell parts through distributors. This can introduce some
problems for the designer. For example, in 1992 the Xilinx XC3000 series
offered the following part options:
TABLE 4.5 Actel price adjustment factors.
Purchase quantity, all types
(19)
(1099)
(100999)
100 %
96 %
84 %
Purchase time, in (100999) quantity
1H92
2H92
93
100 %
8095 %
6080 %
Qualification type, same package
Commercial Industrial
Military
100 %
120 %
150 %
Speed bin 1
ACT 1-Std ACT 1-1
ACT 1-2
100 %
115 %
140 %
Package type
A1010:
PL44, 64, 84 PQ100
100 %
125 %
A1020:
PL44, 64, 84 PQ100
100 %
125 %
A1225:
PQ100
PG100
100 %
175 %
A1240:
PQ144
PG132
100 %
140 %
A1280:
PQ160
PG176
100 %
145 %
●
●
●
●
883-B
230300 %
ACT 2-Std ACT 2-1
100 %
120 %
PG84
400 %
JQ44, 68, 84 PG84
270 %
275 %
CQ84
400 %
CQ172
160 %
Five different size parts: XC30{20, 30, 42, 64, 90}
Three different speed grades or bins: {50, 70, 100}
Ten different packages: {PC68, PC84, PG84, PQ100, CQ100, PP132,
PG132, CQ184, PP175, PG175}
Four application ranges or qualification types: {C, I, M, B}
where {} means Choose one.
This range of options gave a total of 600 possible XC3000 products, of which
127 were actually available from Xilinx, each with a different part code. If a
designer is uncertain as to exact size, speed, or package required, then they might
easily need price information on several dozen different part numbers.
Distributors know the price informationit is given to each distributor by the
FPGA vendors. Sometimes the distributors are reluctant to give pricing
information outfor the same reason car salespeople do not always like to
advertise the pricing scheme for cars. However, pricing of the components of a
microelectronics system is a vital factor in making decisions such as whether to
use FPGAs or some alternative technology. Designers would like to know how
FPGAs are priced and how prices may change.
4.7.2 Pricing Examples
Table 4.3 shows the prices of the least-expensive version of the Actel ACT 1 and
ACT 2 FPGA families, the base prices , in the first half of 1992 (1H92).
Table 4.4 shows the 1H92 base prices for the Xilinx XC3000 FPGA family.
Current FPGA prices are much lower. As an example, the least-expensive
XC3000 part, the XC3020A-7PC68C, was $13.75 in 1996nearly half the 1992
price.
Using historical prices helps prevent accusations of bias or distortion, but still
realistically illustrates the pricing schemes that are used. We shall use these base
prices to illustrate how to estimate the sticker price of an FPGA by adding
optionsas we might for a car. To estimate the price of any part, multiply the base
prices by the adjustment factors (shown in Table 4.5 for the Actel parts).
The adjustment factors in Table 4.5 were calculated by taking averages across a
matrix of prices. Not all combinations of product types are available (for
example, there was no military version of an A1280-1 in 1H92). The dependence
of price over time is especially variable. An example price calculation for an
Actel part is shown in Table 4.6 . Many FPGA vendors use similar pricing
models.
TABLE 4.6 Example Actel part-price calculation using the base prices of
Table 4.3 and the adjustment factors of Table 4.5 .
Example: A1020A-2-PQ100I in (100999) quantity, purchased 1H92.
Factor
Base price
Quantity
Time
Qualification type
Speed bin 2
Package
Estimated price (1H92)
Actual Actel price (1H92)
Example
A1020A
100999
1H92
Industrial (I)
2
Value
$43.30
84 %
100 %
120 %
140 %
PQ100
125 %
$76.38
$75.60
Some distributors now include FPGA prices and availability online (for example,
Marshall at http://marshall.com for Xilinx parts) so that is possible to complete
an up-to-date analysis at any time. Most distributors carry only one FPGA
vendor; not all of the distributors publish prices; and not all FPGA vendors sell
through distributors. Currently Hamilton-Avnet, at http://www.hh.avnet.com ,
carries Xilinx; and Wyle, at http://www.wyle.com , carries Actel and Altera.
1. Actel speed bins are: Std = standard speed grade; 1 = medium speed grade; 2 =
fastest speed grade.
2. The speed bin is a manufacturers code (usually a number) that follows the
family part number and indicates the maximum operating speed of the device.
4.8 Summary
In this chapter we have covered FPGA programming technologies including
antifuse, SRAM, and EPROM technologies; the programming technology is
linked to all the other aspects of a programmable ASIC. Table 4.7 summarizes
the programming technologies and the fabrication processes used by
programmable ASIC vendors.
TABLE 4.7 Programmable ASIC technologies.
Xilinx LCA 1 Altera EPLD
Xilinx EPLD
Actel
Programming
technology
Polydiffusion Erasable
SRAM
antifuse,
PLICE
ISP
Size of
programming
element
Small but
requires
contacts to
metal
Two inverters
plus pass and
switch
devices.
Largest.
Process
Special:
CMOS plus
three extra
masks.
Programming
method
Programming
technology
Size of
programming
element
UV-erasable
EPROM (MAX
UV-erasable
5k)
EPROM
EEPROM
(MAX 7/9k)
One n - channel One n - channel
EPROM
EPROM
device.
device.
Medium.
Medium.
Standard
CMOS
Standard
EPROM and
EEPROM
Standard
EPROM
Special
hardware
PC card,
PROM, or
serial port
ISP (MAX 9k)
EPROM
or EPROM
programmer
programmer
QuickLogic
Crosspoint
Metalmetal
antifuse,
ViaLink
Metal
polysilicon
antifuse
Atmel
Erasable
SRAM.
Altera FLEX
Erasable
SRAM.
Smallest
Small
ISP.
Two inverters
plus pass and
switch devices.
Largest.
ISP.
Two inverters
plus pass and
switch devices.
Largest.
Process
Special,
CMOS plus
ViaLink
Special,
CMOS plus
antifuse
Standard
CMOS
Standard
CMOS
Programming
method
Special
hardware
Special
hardware
PC card,
PROM, or
serial port
PC card,
PROM, or
serial port
All FPGAs have the following key elements:
● The programming technology
● The basic logic cells
● The I/O logic cells
● Programmable interconnect
● Software to design and program the FPGA
1. Lucent (formerly AT&T) FPGAs have almost identical properties to the Xilinx
LCA family.
4.9 Problems
* = Difficult, ** = Very difficult, *** = Extremely difficult
4.1 (Antifuse properties, 20 min.) In this problem we examine some of the
physical and electrical features of the antifuse programming process.
● a. If the programming current of an antifuse is 5 mA and the link diameter
that is formed is 20 nm, what is the current density during programming?
● b. If the average antifuse resistance is 500 W after programming is
complete and the programming current is 5 mA, what is the voltage across
the antifuse at completion of programming?
● c. What power is dissipated in the antifuse link at the end of programming?
● d. Suppose we wish to reduce the antifuse resistance from 500 W to 50 W .
If the antifuse link is a tall, thin cylinder, what is the diameter of a 50 W
antifuse?
● e. Assume we need to keep the power dissipated per unit volume of the
antifuse link the same at the end of the programming process for both 500
W and 50 W antifuses. What current density is required to program a 50 W
antifuse?
● f. With these assumptions what is the required programming current for a
50 W antifuse? Comment on your answer and the assumptions that you
have made.
4.2 (Actel antifuse programming, 20 min.) In this problem we examine the time
taken to program an antifuse-based FPGA.
● a. We have stated that it takes about 5 to 10 minutes to program an Actel
part. Given the number of antifuses on the smallest Actel part, and the
number of antifuses that need to be blown on average, work out the
equivalent time it takes to blow one antifuse. Does this seem reasonable?
● b. Because of a failure process known as electromigration, the current
density in a metal wire on a chip is limited to about 50 k Acm 2 . You can
exceed this current for a short time as long as the time average does not
exceed the limit. Suppose we want to use a minimum metal width to
connect the programming transistors: Would these facts help explain your
answer to part a?
● c. What other factors might be involved in the process of blowing antifuses
that may help explain your answer to part a?
4.3 (*Xilinx cell) Estimate the area components of a Xilinx cell as follows:
●
●
●
a. (30 min.) Assume the two inverters in the cross-coupled SRAM cell are
minimum size (they are not, the p- channelsor n- channelsin one inverter
need to be weaklong and narrowbut ignore this). Assume the readwrite
device is minimum size. Estimate the size of the SRAM cell including an
allowance for wiring (state your assumptions clearly).
b. (15 min.) Assume a single n- channel pass transistor is connected to the
SRAM cell and has an on-resistance of 500 W (equal to the average Actel
ACT 1 antifuse resistance for comparison; the actual Xilinx pass
transistors have closer to 1 k W on-resistance). Estimate the transistor size.
Assume the gate voltage of the pass transistor is at 5 V, and the source and
drain voltages are both at 0 V (the best case). Hint: Use the parameters
from Section 3.1 , Transistors as Resistors .
c. (15min.) Compare your total area estimates of the cell with other FPGA
technologies. Explain why the assumptions you made may be too simple,
and suggest ways to make more accurate estimates.
4.4 (FPGA vendors, 60 min.) Update the information shown in Table 4.7 using
the online information provided by FPGA vendors.
4.5 (Prices) Adjustment factors, calculated from averages across the Xilinx price
matrix, are shown in Table 4.8 (the adjustment factors for the Xilinx military and
MIL-STD parts vary so wildly that it is not possible to use a simple model to
predict these prices).
● a. (5 min.) Estimate the price of a XC3042-70PG132I in 100+ quantity,
purchased in 1H92.
● b. (30min.) Use the 1992 prices in Figure 4.9 to derive as much of the
information shown in Table 4.8 as you can, explaining your methods.
FIGURE 4.9
Xilinx XC3042
prices (1992).
Problem 4.5
reconstructs part
of Table 4.8
from this data.
TABLE 4.8 Xilinx price adjustment factors (1992) for Problem 4.5
Purchase quantity, all types
(124)
(2599)
(100+) (5000+)
100 %
91 %
77 % 70 %
Purchase time, in (100999) quantity
1H92
+18 months
100%
60%
Qualification type, same package
Commercial
Industrial
Military 883-B
100%
130%
varies varies
Speed bin
50
100 %
Package type
3020:
3030:
3042:
3064:
3090:
●
70
100
125
110 %
130 % 220 %
PC68
100 %
PC44
100 %
PC84
100 %
PC84
100 %
PC84
100 %
PC84
106 %
PC68
107 %
PQ100
175 %
PQ160
150 %
PQ160
130 %
PQ100
127 %
PC84
113 %
PP132
240 %
PP132
190 %
PP175
150 %
PG84 CQ100
340 % 490 %
PQ100 PG84
135 % 330 %
PG84 PG132 CQ100
310 % 370 % 375 %
PG132
260 %
PG175 CQ164
230 % 240 %
c. (Hours) Construct a table (using the format of Table 4.8 ) for a current
FPGA family. You may have to be creative in capturing the HTML and
filtering it into a spreadsheet. Hint: In Microsoft Word 5.0 you can select
columns of text by holding down the Option key.
Answer: (a) $211.85 (the actual Xilinx price was $210.20).
4.6 (PREP benchmarks, 60min.) Download the PREP 1.3 benchmark results as
spreadsheets from http://www.prep.org . Split the participating companies among
groups and challenge each group to produce an averaging or analysis scheme that
shows the groups assigned company as a winner. For hints on this problem,
consult advertisements in past issues of EE Times .
4.7 (FPGA patents) Patents are a good place to find information on FPGAs.
● a. Find U.S. Patent 5,440,245, Galbraith et al. Logic module with
configurable combinational and sequential blocks. Find and explain a
method to paste the figures into a report.
● b. Conduct a patent search on FPGAs. Good places to start are the U.S.
Patent and Trademark Office ( PTO ) at http://www.uspto.gov and the IBM
patent resource at http://patent.womplex.ibm.com . Until 1996 the full text
of recent U.S. patents was available at http://www.town.hall.org/patent ;
this is still a good site to visit for references to other locations. Table 4.9
lists the patents awarded to the major FPGA companies up until 1996 (in
the case of Actel and Altera the list includes only patents issued after 1990,
corresponding roughly to patent numbers greater than number 5,000,000,
which was issued in March 1990).
4.8 (**Maskworks, days) If you really want to find out about FPGA technology
you tear chips apart. There is another way. Most U.S. companies register their
chips as a type of copyright called a Maskwork . You will often see a little circle
containing an M on a chip in the same way that a copyright sign is a circle
surrounding the letter C. Companies that require a Maskwork are required to
deposit plots and samples of the chips with a branch of the Library of Congress.
These plots are open for public inspection in Washington, D.C. It is perfectly
legal to use this information. You have to sign a visitors book, and most of the
names in the book are Japanese. Research Maskworks and write a summary of its
implications, the protection it provides, and (if you can find them) the rules for
the materials that must be deposited with the authorities.
TABLE 4.9 FPGA Patents (U.S.).
QuickLogic Xilinx
5,329,181 4,713,557 5,308,795 5,008,855
5,416,367 5,436,575 5,329,174 4,706,216 5,304,871
5,397,939 5,432,719 5,329,181 4,695,740 5,299,150 Altera
5,396,127 5,430,687 5,321,704 4,642,487 5,286,992 5,477,474 5,280,203
5,362,676 5,430,390 5,319,254
5,272,388 5,473,266 5,274,581
5,319,238 5,426,379 5,319,252 Actel
5,272,101 5,463,328 5,272,368
5,302,546 5,426,378 5,302,866 5,479,113 5,266,829 5,444,394 5,268,598
5,220,213 5,422,833 5,295,090 5,477,165 5,254,886 5,438,295 5,260,611
5,196,724 5,414,377 5,291,079 5,469,396 5,223,792 5,436,575 5,260,610
5,410,194 5,245,277 5,464,790 5,208,530 5,436,574 5,258,668
Intel
5,410,189 5,224,056 5,457,644 5,198,705 5,434,514 5,247,478
4,543,594 1 5,399,925 5,166,858 5,451,887 5,194,759 5,432,467 5,247,477
5,399,924 5,155,432 5,449,947 5,191,241 5,414,312 5,243,233
Crosspoint 5,394,104 5,148,390 5,448,185 5,187,393 5,399,922 5,241,224
5,440,453 5,386,154 5,068,603 5,440,245 5,181,096 5,384,499 5,237,219
5,394,103 5,367,207 5,047,710 5,432,441 5,172,014 5,376,844 5,220,533
5,365,125 5,028,821 5,414,364 5,171,715 5,371,422 5,220,214
5,384,481 5,362,999 5,023,606 5,412,244 5,163,180 5,369,314 5,200,920
5,322,812 5,361,229 5,012,135 5,411,917 5,134,457 5,359,243 5,166,604
5,313,119 5,360,747 4,967,107 5,404,029 5,132,571 5,359,242 5,162,680
5,233,217 5,359,536 4,940,909 5,391,942 5,130,777 5,353,248 5,144,167
5,221,865 5,349,691 4,902,910 5,387,812 5,126,282 5,352,940 5,138,576
5,349,250 4,870,302 5,373,169 5,111,262 5,350,954 5,128,565
Concurrent 5,349,249 4,855,669 5,371,414 5,107,146 5,349,255 5,121,006
5,218,240 5,349,248 4,855,619 5,369,054 5,095,228 5,341,308 5,111,423
5,144,166 5,343,406 4,847,612 5,367,208 5,087,958 5,341,048 5,097,208
5,089,973 5,337,255 4,835,418 5,365,165 5,083,083 5,341,044 5,091,661
5,349,248 4,821,233 5,341,092 5,073,729 5,329,487 5,066,873
Plus Logic 5,343,406 4,820,937 5,341,043 5,070,384 5,317,210 5,045,772
5,028,821 5,337,255 4,783,607 5,341,030 5,057,451 5,315,172
5,023,606 5,332,929 4,758,985 5,317,698 5,055,718 5,301,416
5,012,135 5,331,226 4,750,155 5,316,971 5,017,813 5,294,975
4,967,107 5,331,220 4,746,822 5,309,091 5,015,885 5,285,153
4,940,909
1. Mohsens patent on the antifuse structure.
4.10 Bibliography
Books by Ukeiley [ 1993], Chan [ 1994], and Trimberger [ 1994] are dedicated to
FPGAs and their uses. The International Workshop on Field-Programmable
Logic and Applications describes the latest developments and applications of
FPGAs [Grünbacher and Hartenstein, 1992; Hartenstein and Servit, 1994; Moore
and Luk, 1995; Hartenstein and Glesner, 1996]. Many of the FPGA vendors have
Web sites that include white papers and technical documentation. The annual
IEEE International Electron Devices Meeting (IEDM, ISSN 0163-1918, TK
7801.I53) is a forum for presenting new device and IC technology including new
FPGA programming technologies. The IEEE Transaction on Electron Devices
(ISSN 0018-9383) is the archival source for developments in device technology.
There is a large U.S. patent literature on FPGAs (see Table 4.9 ). Sometimes the
FPGA vendors hide the basic low-level structures from the user to simplify their
description or to prevent the competition from understanding their secrets.
Patents have to explain the details of operation (otherwise they will not be
awarded or cannot be enforced), so sometimes it can be useful to at least know
where to look. One place to start is the front or back of the data book, which
often contains a list of the manufacturers patents.
4.11 References
Chan, P. K., and S. Mourad. 1994. Digital Design Using Field Programmable
Gate Arrays. Englewood Cliffs, NJ: Prentice-Hall, 233 p. ISBN 0-13-319021-8.
TK7888.4.C43.
Grünbacher, H., and R. W. Hartenstein. (Eds.). 1993. International Workshop on
Field-Programmable Logic and Applications (2nd: 1992: Vienna). Berlin; New
York: Springer-Verlag. ISBN 0387570918. TK7895.G36.I48.
Hartenstein, R. W., and M. Glesner (Eds.). 1996. International Workshop on
Field-Programmable Logic and Applications (6th: 1996: Darmstadt). Berlin; New
York: Springer-Verlag. ISBN 3540617302. TK7868.L6.I56.
Hartenstein, R. W., and M. Z. Servit. (Eds.). 1994. International Workshop on
Field-Programmable Logic and Applications (4th: 1994: Prague). Berlin; New
York: Springer-Verlag. ISBN 0387584196. TK7868.L6.I56.
Moore, W., and W. Luk. (Eds.). 1995. International Workshop on
Field-Programmable Logic and Applications (5th: 1995: Oxford). Berlin; New
York: Springer-Verlag. ISBN 3540602941. TK7895.G36.I48.
Trimberger, S. M. (Ed.). 1994. Field-Programmable Gate Array Technology .
Boston: Kluwer Academic Publishers. ISBN 0-7923-9419-4. TK7895.G36.F54.
Ukeiley, R. L. 1993. Field Programmable Gate Arrays (FPGAs): The 3000
Series. Englewood Cliffs, NJ: Prentice-Hall, 173 p. ISBN 0-13-319468-X.
TK7895.G36.U44.
L ast E d ited by S P 1411 2 0 0 4
PROGRAMMABLE
ASIC LOGIC
CELLS
All programmable ASICs or FPGAs contain a basic logic cell replicated in a
regular array across the chip (analogous to a base cell in an MGA). There are the
following three different types of basic logic cells: (1) multiplexer based, (2)
look-up table based, and (3) programmable array logic. The choice among these
depends on the programming technology. We shall see examples of each in this
chapter.
5.1 Actel ACT
The basic logic cells in the Actel ACT family of FPGAs are called Logic
Modules . The ACT 1 family uses just one type of Logic Module and the ACT 2
and ACT 3 FPGA families both use two different types of Logic Module.
5.1.1 ACT 1 Logic Module
The functional behavior of the Actel ACT 1 Logic Module is shown in Figure 5.1
(a). Figure 5.1 (b) represents a possible circuit-level implementation. We can
build a logic function using an Actel Logic Module by connecting logic signals to
some or all of the Logic Module inputs, and by connecting any remaining Logic
Module inputs to VDD or GND. As an example, Figure 5.1 (c) shows the
connections to implement the function F = A · B + B' · C + D. How did we know
what connections to make? To understand how the Actel Logic Module works,
we take a detour via multiplexer logic and some theory.
FIGURE 5.1 The Actel ACT architecture. (a) Organization of the basic logic
cells. (b) The ACT 1 Logic Module. (c) An implementation using pass
transistors (without any buffering). (d) An example logic macro. (Source: Actel.)
5.1.2 Shannons Expansion Theorem
In logic design we often have to deal with functions of many variables. We need
a method to break down these large functions into smaller pieces. Using the
Shannon expansion theorem, we can expand a Boolean logic function F in terms
of (or with respect to) a Boolean variable A,
F = A · F (A = '1') + A' · F (A = '0'),(5.1)
where F (A = 1) represents the function F evaluated with A set equal to '1'.
For example, we can expand the following function F with respect to (I shall use
the abbreviation wrt ) A,
F = A' · B + A · B · C' + A' · B' · C
= A · (B · C') + A' · (B + B' · C).(5.2)
We have split F into two smaller functions. We call F (A = '1') = B · C' the
cofactor of F wrt A in Eq. 5.2 . I shall sometimes write the cofactor of F wrt A as
F A (the cofactor of F wrt A' is F A' ). We may expand a function wrt any of its
variables. For example, if we expand F wrt B instead of A,
F = A' · B + A · B · C' + A' · B' · C
= B · (A' + A · C') + B' · (A' · C).(5.3)
We can continue to expand a function as many times as it has variables until we
reach the canonical form (a unique representation for any Boolean function that
uses only minterms. A minterm is a product term that contains all the variables of
Fsuch as A · B' · C). Expanding Eq. 5.3 again, this time wrt C, gives
F = C · (A' · B + A' · B') + C' · (A · B + A' · B).(5.4)
As another example, we will use the Shannon expansion theorem to implement
the following function using the ACT 1 Logic Module:
F = (A · B) + (B' · C) + D.(5.5)
First we expand F wrt B:
F = B · (A + D) + B' · (C + D)
= B · F2 + B' · F1.(5.6)
Equation 5.6 describes a 2:1 MUX, with B selecting between two inputs: F (A =
'1') and F (A = '0'). In fact Eq. 5.6 also describes the output of the ACT 1 Logic
Module in Figure 5.1 ! Now we need to split up F1 and F2 in Eq. 5.6 . Suppose
we expand F2 = F B wrt A, and F1 = F B' wrt C:
F2 = A + D = (A · 1) + (A' · D),(5.7)
F1 = C + D = (C · 1) + (C' · D).(5.8)
From Eqs. 5.6 5.8 we see that we may implement F by arranging for A, B, C to
appear on the select lines and '1' and D to be the data inputs of the MUXes in the
ACT 1 Logic Module. This is the implementation shown in Figure 5.1 (d), with
connections: A0 = D, A1 = '1', B0 = D, B1 = '1', SA = C, SB = A, S0 = '0', and S1
= B.
Now that we know that we can implement Boolean functions using MUXes, how
do we know which functions we can implement and how to implement them?
5.1.3 Multiplexer Logic as Function
Generators
Figure 5.2 illustrates the 16 different ways to arrange 1s on a Karnaugh map
corresponding to the 16 logic functions, F (A, B), of two variables. Two of these
functions are not very interesting (F = '0', and F = '1'). Of the 16 functions,
Table 5.1 shows the 10 that we can implement using just one 2:1 MUX. Of these
10 functions, the following six are useful:
● INV. The MUX acts as an inverter for one input only.
● BUF. The MUX just passes one of the MUX inputs directly to the output.
● AND. A two-input AND.
● OR. A two-input OR.
● AND1-1. A two-input AND gate with inverted input, equivalent to an
NOR-11.
● NOR1-1. A two-input NOR gate with inverted input, equivalent to an
AND-11.
FIGURE 5.2 The
logic functions of two
variables.
TABLE 5.1 Boolean functions using a 2:1 MUX.
Canonical Minterms Minterm Function M1 4
Function, F
F=
1
form
code 2
number 3 A0 A1 SA
1 '0'
'0' '0'
none
0000
0
0 0 0
(A
NOR1-1(A,
2
+ A' · B
B)
B')'
A' · B' +
3 NOT(A)
A'
A' · B
AND1-1(A, A ·
4
A · B'
B)
B'
A' · B' + A
5 NOT(B)
B'
· B'
A' · B + A
6 BUF(B)
B
·B
A·
7 AND(A, B)
A·B
B
A · B' + A
8 BUF(A)
A
·B
A' · B + A
A
9 OR(A, B)
· B' + A ·
+B
B
A' · B' +
A' · B + A
10 '1'
'1'
· B' + A ·
B
1
0010
2
B 0 A
0, 1
0011
3
0 1 A
2
0100
4
A 0 B
0, 2
0101
5
0 1 B
1, 3
1010
6
0 B 1
3
1000
8
0 B A
2, 3
1100
9
0 A 1
1, 2, 3
1110
13
B 1 A
0, 1, 2, 3 1111
15
1 1 1
Figure 5.3 (a) shows how we might view a 2:1 MUX as a function wheel , a
three-input black box that can generate any one of the six functions of two-input
variables: BUF, INV, AND-11, AND1-1, OR, AND. We can write the output of
a function wheel as
F1 = WHEEL1 (A, B).(5.9)
where I define the wheel function as follows:
WHEEL1 (A, B) = MUX (A0, A1, SA).(5.10)
The MUX function is not unique; we shall define it as
MUX (A0, A1, SA) = A0 · SA' + A1 · SA.(5.11)
The inputs (A0, A1, SA) are described using the notation
A0, A1, SA = {A, B, '0', '1'}(5.12)
to mean that each of the inputs (A0, A1, and SA) may be any of the values: A, B,
'0', or '1'. I chose the name of the wheel function because it is rather like a dial
that you set to your choice of function. Figure 5.3 (b) shows that the ACT 1
Logic Module is a function generator built from two function wheels, a 2:1
MUX, and a two-input OR gate.
FIGURE 5.3 The ACT 1 Logic Module as a Boolean function generator. (a) A
2:1 MUX viewed as a function wheel. (b) The ACT 1 Logic Module viewed as
two function wheels, an OR gate, and a 2:1 MUX.
We can describe the ACT 1 Logic Module in terms of two WHEEL functions:
F = MUX [ WHEEL1, WHEEL2, OR (S0, S1) ](5.13)
Now, for example, to implement a two-input NAND gate, F = NAND (A, B) =
(A · B)', using an ACT 1 Logic Module we first express F as the output of a 2:1
MUX. To split up F we expand it wrt A (or wrt B; since F is symmetric in A and
B):
F = A · (B') + A' · ('1')(5.14)
Thus to make a two-input NAND gate we assign WHEEL1 to implement INV
(B), and WHEEL2 to implement '1'. We must also set the select input to the
MUX connecting WHEEL1 and WHEEL2, S0 + S1 = Awe can do this with S0 =
A, S1 = '1'.
Before we get too carried away, we need to realize that we do not have to worry
about how to use Logic Modules to construct combinational logic functionsthis
has already been done for us. For example, if we need a two-input NAND gate,
we just use a NAND gate symbol and software takes care of connecting the
inputs in the right way to the Logic Module.
How did Actel design its Logic Modules? One of Actels engineers wrote a
program that calculates how many functions of two, three, and four variables a
given circuit would provide. The engineers tested many different circuits and
chose the best one: a small, logically efficient circuit that implemented many
functions. For example, the ACT 1 Logic Module can implement all two-input
functions, most functions with three inputs, and many with four inputs.
Apart from being able to implement a wide variety of combinational logic
functions, the ACT 1 module can implement sequential logic cells in a flexible
and efficient manner. For example, you can use one ACT 1 Logic Module for a
transparent latch or two Logic Modules for a flip-flop. The use of latches rather
than flip-flops does require a shift to a two-phase clocking scheme using two
nonoverlapping clocks and two clock trees. Two-phase synchronous design using
latches is efficient and fast but, to handle the timing complexities of two clocks
requires changes to synthesis and simulation software that have not occurred.
This means that most people still use flip-flops in their designs, and these require
two Logic Modules.
5.1.4 ACT 2 and ACT 3 Logic Modules
Using two ACT 1 Logic Modules for a flip-flop also requires added interconnect
and associated parasitic capacitance to connect the two Logic Modules. To
produce an efficient two-module flip-flop macro we could use extra antifuses in
the Logic Module to cut down on the parasitic connections. However, the extra
antifuses would have an adverse impact on the performance of the Logic Module
in other macros. The alternative is to use a separate flip-flop module, reducing
flexibility and increasing layout complexity. In the ACT 1 family Actel chose to
use just one type of Logic Module. The ACT 2 and ACT 3 architectures use two
different types of Logic Modules, and one of them does include the equivalent of
a D flip-flop.
Figure 5.4 shows the ACT 2 and ACT 3 Logic Modules. The ACT 2 C-Module is
similar to the ACT 1 Logic Module but is capable of implementing five-input
logic functions. Actel calls its C-module a combinatorial module even though the
module implements combinational logic. John Wakerly blames MMI for the
introduction of the term combinatorial [Wakerly, 1994, p. 404].
The use of MUXes in the Actel Logic Modules (and in other places) can cause
confusion in using and creating logic macros. For the Actel library, setting S = '0'
selects input A of a two-input MUX. For other libraries setting S = '1' selects
input A. This can lead to some very hard to find errors when moving schematics
between libraries. Similar problems arise in flip-flops and latches with MUX
inputs. A safer way to label the inputs of a two-input MUX is with '0' and '1',
corresponding to the input selected when the select input is '1' or '0'. This notation
can be extended to bigger MUXes, but in Figure 5.4 , does the input combination
S0 = '1' and S1 = '0' select input D10 or input D01? These problems are not
caused by Actel, but by failure to use the IEEE standard symbols in this area.
The S-Module ( sequential module ) contains the same combinational function
capability as the C-Module together with a sequential element that can be
configured as a flip-flop. Figure 5.4 (d) shows the sequential element
implementation in the ACT 2 and ACT 3 architectures.
FIGURE 5.4 The Actel ACT 2 and ACT 3 Logic Modules. (a) The C-Module
for combinational logic. (b) The ACT 2 S-Module. (c) The ACT 3 S-Module.
(d) The equivalent circuit (without buffering) of the SE (sequential element).
(e) The sequential element configured as a positive-edgetriggered D flip-flop.
(Source: Actel.)
5.1.5 Timing Model and Critical Path
Figure 5.5 (a) shows the timing model for the ACT family. 5 This is a simple
timing model since it deals only with logic buried inside a chip and allows us
only to estimate delays. We cannot predict the exact delays on an Actel chip until
we have performed the place-and-route step and know how much delay is
contributed by the interconnect. Since we cannot determine the exact delay
before physical layout is complete, we call the Actel architecture
nondeterministic .
Even though we cannot determine the preroute delays exactly, it is still important
to estimate the delay on a logic path. For example, Figure 5.5 (a) shows a typical
situation deep inside an ASIC. Internal signal I1 may be from the output of a
register (flip-flop). We then pass through some combinational logic, C1, through
a register, S1, and then another register, S2. The register-to-register delay
consists of a clockQ delay, plus any combinational delay between registers, and
the setup time for the next flip-flop. The speed of our system will depend on the
slowest registerregister delay or critical path between registers. We cannot make
our clock period any longer than this or the signal will not reach the second
register in time to be clocked.
Figure 5.5 (a) shows an internal logic signal, I1, that is an input to a C-module,
C1. C1 is drawn in Figure 5.5 (a) as a box with a symbol comprising the
overlapping letters C and L (borrowed from carpenters who use this symbol to
mark the centerline on a piece of wood). We use this symbol to describe
combinational logic. For the standard-speed grade ACT 3 (we shall look at speed
grading in Section 5.1.6 ) the delay between the input of a C-module and the
output is specified in the data book as a parameter, t PD , with a maximum value
of 3.0 ns.
The output of C1 is an input to an S-Module, S1, configured to implement
combinational logic and a D flip-flop. The Actel data book specifies the
minimum setup time for this D flip-flop as t SUD = 0.8 ns. This means we need to
get the data to the input of S1 at least 0.8 ns before the rising clock edge (for a
positive-edgetriggered flip-flop). If we do this, then there is still enough time for
the data to go through the combinational logic inside S1 and reach the input of
the flip-flop inside S1 in time to be clocked. We can guarantee that this will work
because the combinational logic delay inside S1 is fixed.
FIGURE 5.5 The Actel ACT timing model. (a) Timing parameters for a 'Std'
speed grade ACT 3. (Source: Actel.) (b) Flip-flop timing. (c) An example of
flip-flop timing based on ACT 3 parameters.
The S-Module seems like good valuewe get all the combinational logic functions
of a C-module (with delay t PD of 3 ns) as well as the setup time for a flip-flop for
only 0.8 ns? &not really. Next I will explain why not.
Figure 5.5 (b) shows what is happening inside an S-Module. The setup and hold
times, as measured inside (not outside) the S-Module, of the flip-flop are t' SUD
and t' H (a prime denotes parameters that are measured inside the S-Module). The
clockQ propagation delay is t' CO . The parameters t' SUD , t' H , and t' CO are
measured using the internal clock signal CLKi. The propagation delay of the
combinational logic inside the S-Module is t' PD . The delay of the combinational
logic that drives the flip-flop clock signal ( Figure 5.4 d) is t' CLKD .
From outside the S-Module, with reference to the outside clock signal CLK1:
t SUD = t' SUD + (t' PD t'
t H = t' H + (t' PD t'
CLKD
CLKD
),
),
t CO = t' CO + t' CLKD .(5.15)
Figure 5.5 (c) shows an example of flip-flop timing. We have no way of knowing
what the internal flip-flop parameters t' SUD , t' H , and t' CO actually are, but we
can assume some reasonable values (just for illustration purposes):
t' SUD = 0.4 ns, t' H = 0.1 ns, t' CO = 0.4 ns.(5.16)
We do know the delay, t' PD , of the combinational logic inside the S-Module. It
is exactly the same as the C-Module delay, so t' PD = 3 ns for the ACT 3. We do
not know t' CLKD ; we shall assume a reasonable value of t' CLKD = 2.6 ns (the
exact value does not matter in the following argument).
Next we calculate the external S-Module parameters from Eq. 5.15 as follows:
t SUD = 0.8 ns, t H = 0.5 ns, t CO = 3.0 ns.(5.17)
These are the same as the ACT 3 S-Module parameters shown in Figure 5.5 (a),
and I chose t' CLKD and the values in Eq. 5.16 so that they would be the same. So
now we see where the combinational logic delay of 3.0 ns has gone: 0.4 ns went
into increasing the setup time and 2.6 ns went into increasing the clockoutput
delay, t CO .
From the outside we can say that the combinational logic delay is buried in the
flip-flop setup time. FPGA vendors will point this out as an advantage that they
have. Of course, we are not getting something for nothing here. It is like
borrowing moneyyou have to pay it back.
5.1.6 Speed Grading
Most FPGA vendors sort chips according to their speed ( the sorting is known as
speed grading or speed binning , because parts are automatically sorted into
plastic bins by the production tester). You pay more for the faster parts. In the
case of the ACT family of FPGAs, Actel measures performance with a special
binning circuit , included on every chip, that consists of an input buffer driving a
string of buffers or inverters followed by an output buffer. The parts are sorted
from measurements on the binning circuit according to Logic Module
propagation delay. The propagation delay, t PD , is defined as the average of the
rising ( t PLH ) and falling ( t PHL ) propagation delays of a Logic Module
t PD = ( t PLH + t PHL )/2.(5.18)
Since the transistor properties match so well across a chip, measurements on the
binning circuit closely correlate with the speed of the rest of the Logic Modules
on the die. Since the speeds of die on the same wafer also match well, most of the
good die on a wafer fall into the same speed bin. Actel speed grades are: a 'Std'
speed grade, a '1' speed grade that is approximately 15 percent faster, a '2' speed
grade that is approximately 25 percent faster than 'Std', and a '3' speed grade that
is approximately 35 percent faster than 'Std'.
5.1.7 Worst-Case Timing
If you use fully synchronous design techniques you only have to worry about
how slow your circuit may benot how fast. Designers thus need to know the
maximum delays they may encounter, which we call the worst-case timing .
Maximum delays in CMOS logic occur when operating under minimum voltage,
maximum temperature, and slowslow process conditions. (A slowslow process
refers to a process variation, or process corner , which results in slow p -channel
transistors and slow n -channel transistorswe can also have fastfast, slowfast,
and fastslow process corners.)
Electronic equipment has to survive in a variety of environments and ASIC
manufacturers offer several classes of qualification for different applications:
● Commercial. VDD = 5 V ± 5 %, T A (ambient) = 0 to +70 °C.
●
Industrial. VDD = 5 V ± 10 %, T A (ambient) = 40 to +85 °C.
●
Military: VDD = 5 V ± 10 %, T C (case) = 55 to +125 °C.
●
Military: Standard MIL-STD-883C Class B.
Military extended: Unmanned spacecraft.
●
ASICs for commercial application are cheapest; ASICs for the Cruise missile are
very, very expensive. Notice that commercial and industrial application parts are
specified with respect to the ambient temperature T A (room temperature or the
temperature inside the box containing the ASIC). Military specifications are
relative to the package case temperature , T C . What is really important is the
temperature of the transistors on the chip, the junction temperature , T J , which is
always higher than T A (unless we dissipate zero power). For most applications
that dissipate a few hundred mW, T J is only 510 °C higher than T A . To
calculate the value of T J we need to know the power dissipated by the chip and
the thermal properties of the packagewe shall return to this in Section 6.6.1,
Power Dissipation.
Manufacturers have to specify their operating conditions with respect to T J and
not T A , since they have no idea how much power purchasers will dissipate in
their designs or which package they will use. Actel used to specify timing under
nominal operating conditions: VDD = 5.0 V, and T J = 25 °C. Actel and most
other manufacturers now specify parameters under worst-case commercial
conditions: VDD = 4.75 V, and T J = +70 °C.
Table 5.2 shows the ACT 3 commercial worst-case timing. 6 In this table Actel
has included some estimates of the variable routing delay shown in Figure 5.5
(a). These delay estimates depend on the number of gates connected to a gate
output (the fanout).
When you design microelectronic systems (or design anything ) you must use
worst-case figures ( just as you would design a bridge for the worst-case load).
To convert nominal or typical timing figures to the worst case (or best case), we
use measured, or empirically derived, constants called derating factors that are
expressed either as a table or a graph. For example, Table 5.3 shows the ACT 3
derating factors from commercial worst-case to industrial worst-case and military
worst-case conditions (assuming T J = T A ). The ACT 1 and ACT 2 derating
factors are approximately the same. 7
TABLE 5.2 ACT 3 timing parameters. 8
Fanout
Family
Delay 9 1 2 3 4 8
2.9 3.2 3.4 3.7 4.8
ACT 3-3 (data book) t PD
ACT3-2 (calculated) t PD /0.85 3.41 3.76 4.00 4.35 5.65
ACT3-1 (calculated)
t PD /0.75 3.87 4.27 4.53 4.93 6.40
ACT3-Std (calculated) t PD /0.65 4.46 4.92 5.23 5.69 7.38
Source: Actel.
TABLE 5.3 ACT 3 derating factors. 10
Temperature T J ( junction) / °C
V DD / V 55
40 0
25 70 85 125
4.5
0.72 0.76 0.85 0.90 1.04 1.07 1.17
4.75
0.70 0.73 0.82 0.87 1.00 1.03 1.12
5.00
0.68 0.71 0.79 0.84 0.97 1.00 1.09
5.25
0.66 0.69 0.77 0.82 0.94 0.97 1.06
5.5
0.63 0.66 0.74 0.79 0.90 0.93 1.01
Source: Actel.
As an example of a timing calculation, suppose we have a Logic Module on a
'Std' speed grade A1415A (an ACT 3 part) that drives four other Logic Modules
and we wish to estimate the delay under worst-case industrial conditions. From
the data in Table 5.2 we see that the Logic Module delay for an ACT 3 'Std' part
with a fanout of four is t PD = 5.7 ns (commercial worst-case conditions,
assuming T J = T A ).
If this were the slowest path between flip-flops (very unlikely since we have only
one stage of combinational logic in this path), our estimated critical path delay
between registers , t CRIT , would be the combinational logic delay plus the
flip-flop setup time plus the clockoutput delay:
t CRIT (w-c commercial) = t PD + t SUD + t CO
= 5.7 ns + 0.8 ns + 3.0 ns = 9.5 ns .(5.19)
(I use w-c as an abbreviation for worst-case.) Next we need to adjust the timing
to worst-case industrial conditions. The appropriate derating factor is 1.07 (from
Table 5.3 ); so the estimated delay is
t CRIT (w-c industrial) = 1.07 ¥ 9.5 ns = 10.2 ns .(5.20)
Let us jump ahead a little and assume that we can calculate that T J = T A + 20 °C
= 105 °C in our application. To find the derating factor at 105 °C we linearly
interpolate between the values for 85 °C (1.07) and 125 °C (1.17) from Table 5.3
). The interpolated derating factor is 1.12 and thus
t CRIT (w-c industrial, T J = 105 °C) = 1.12 ¥ 9.5 ns = 10.6 ns ,(5.21)
giving us an operating frequency of just less than 100 MHz.
It may seem unfair to calculate the worst-case performance for the slowest speed
grade under the harshest industrial conditionsbut the examples in the data books
are always for the fastest speed grades under less stringent commercial
conditions. If we want to illustrate the use of derating, then the delays can only
get worse than the data book values! The ultimate word on logic delays for all
FPGAs is the timing analysis provided by the FPGA design tools. However, you
should be able to calculate whether or not the answer that you get from such a
tool is reasonable.
5.1.8 Actel Logic Module Analysis
The sizes of the ACT family Logic Modules are close to the size of the base cell
of an MGA. We say that the Actel ACT FPGAs use a fine-grain architecture . An
advantage of a fine-grain architecture is that, whatever the mix of combinational
logic to flip-flops in your application, you can probably still use 90 percent of an
Actel FPGA. Another advantage is that synthesis software has an easier time
mapping logic efficiently to the simple Actel modules.
The physical symmetry of the ACT Logic Modules greatly simplifies the
place-and-route step. In many cases the router can swap equivalent pins on
opposite sides of the module to ease channel routing. The design of the Actel
Logic Modules is a balance between efficiency of implementation and efficiency
of utilization. A simple Logic Module may reduce performance in some areasas I
have pointed outbut allows the use of fast and robust place-and-route software.
Fast, robust routing is an important part of Actel FPGAs (see Section 7.1, Actel
ACT).
1. The minterm numbers are formed from the product terms of the canonical
form. For example, A · B' = 10 = 2.
2. The minterm code is formed from the minterms. A '1' denotes the presence of
that minterm.
3. The function number is the decimal version of the minterm code.
4. Connections to a two-input MUX: A0 and A1 are the data inputs and SA is the
select input (see Eq. 5.11 ).
5. 1994 data book, p. 1-101.
6. ACT 3: May 1995 data sheet, p. 1-173. ACT 2: 1994 data book, p. 1-51.
7. 1994 data book, p. 1-12 (ACT 1), p. 1-52 (ACT 2), May 1995 data sheet,
p. 1-174 (ACT 3).
8. V DD = 4.75 V, T J ( junction) = 70 °C. Logic module plus routing delay. All
propagation delays in nanoseconds.
9. The Actel '1' speed grade is 15 % faster than 'Std'; '2' is 25 % faster than 'Std';
'3' is 35 % faster than 'Std'.
10. Worst-case commercial: V DD = 4.75 V, T A (ambient) = +70 °C.
Commercial: V DD = 5 V ± 5 %, T A (ambient) = 0 to +70 °C. Industrial: V DD =
5 V ± 10 %, T A (ambient) = 40 to +85 °C. Military V DD = 5 V ± 10 %, T C
(case) = 55 to +125 °C.
5.2 Xilinx LCA
Xilinx LCA (a trademark, denoting logic cell array) basic logic cells,
configurable logic blocks or CLBs , are bigger and more complex than the Actel
or QuickLogic cells. The Xilinx LCA basic logic cell is an example of a
coarse-grain architecture . The Xilinx CLBs contain both combinational logic and
flip-flops.
5.2.1 XC3000 CLB
The XC3000 CLB, shown in Figure 5.6 , has five logic inputs (AE), a common
clock input (K), an asynchronous direct-reset input (RD), and an enable (EC).
Using programmable MUXes connected to the SRAM programming cells, you
can independently connect each of the two CLB outputs (X and Y) to the output
of the flip-flops (QX and QY) or to the output of the combinational logic (F and
G).
FIGURE 5.6 The Xilinx XC3000 CLB (configurable logic block). (Source:
Xilinx.)
A 32-bit look-up table ( LUT ), stored in 32 bits of SRAM, provides the ability to
implement combinational logic. Suppose you need to implement the function F =
A · B · C · D · E (a five-input AND). You set the contents of LUT cell number 31
(with address '11111') in the 32-bit SRAM to a '1'; all the other SRAM cells are
set to '0'. When you apply the input variables as an address to the 32-bit SRAM,
only when ABCDE = '11111' will the output F be a '1'. This means that the CLB
propagation delay is fixed, equal to the LUT access time, and independent of the
logic function you implement.
There are seven inputs for the combinational logic in the XC3000 CLB: the five
CLB inputs (AE), and the flip-flop outputs (QX and QY). There are two outputs
from the LUT (F and G). Since a 32-bit LUT requires only five variables to form
a unique address (32 = 2 5 ), there are several ways to use the LUT:
● You can use five of the seven possible inputs (AE, QX, QY) with the
entire 32-bit LUT. The CLB outputs (F and G) are then identical.
● You can split the 32-bit LUT in half to implement two functions of four
variables each. You can choose four input variables from the seven inputs
(AE, QX, QY). You have to choose two of the inputs from the five CLB
inputs (AE); then one function output connects to F and the other output
connects to G.
● You can split the 32-bit LUT in half, using one of the seven input variables
as a select input to a 2:1 MUX that switches between F and G. This allows
you to implement some functions of six and seven variables.
5.2.2 XC4000 Logic Block
Figure 5.7 shows the CLB used in the XC4000 series of Xilinx FPGAs. This is a
fairly complicated basic logic cell containing 2 four-input LUTs that feed a
three-input LUT. The XC4000 CLB also has special fast carry logic hard-wired
between CLBs. MUX control logic maps four control inputs (C1C4) into the
four inputs: LUT input H1, direct in (DIN), enable clock (EC), and a set / reset
control (S/R) for the flip-flops. The control inputs (C1C4) can also be used to
control the use of the F' and G' LUTs as 32 bits of SRAM.
FIGURE 5.7 The Xilinx XC4000 family CLB (configurable logic block). (
Source: Xilinx.)
5.2.3 XC5200 Logic Block
Figure 5.8 shows the basic logic cell, a Logic Cell or LC, used in the XC5200
family of Xilinx LCA FPGAs. 1 The LC is similar to the CLBs in the
XC2000/3000/4000 CLBs, but simpler. Xilinx retained the term CLB in the
XC5200 to mean a group of four LCs (LC0LC3).
The XC5200 LC contains a four-input LUT, a flip-flop, and MUXes to handle
signal switching. The arithmetic carry logic is separate from the LUTs. A limited
capability to cascade functions is provided (using the MUX labeled F5_MUX in
logic cells LC0 and LC2 in Figure 5.8 ) to gang two LCs in parallel to provide the
equivalent of a five-input LUT.
FIGURE 5.8 The Xilinx XC5200 family LC (Logic Cell) and CLB
(configurable logic block). (Source: Xilinx.)
5.2.4 Xilinx CLB Analysis
The use of a LUT in a Xilinx CLB to implement combinational logic is both an
advantage and a disadvantage. It means, for example, that an inverter is as slow
as a five-input NAND. On the other hand a LUT simplifies timing of
synchronous logic, simplifies the basic logic cell, and matches the Xilinx SRAM
programming technology well. A LUT also provides the possibility, used in the
XC4000, of using the LUT directly as SRAM. You can configure the XC4000
CLB as a memoryeither two 16 ¥ 1 SRAMs or a 32 ¥ 1 SRAM, but this is
expensive RAM.
Figure 5.9 shows the timing model for Xilinx LCA FPGAs. 2 Xilinx uses two
speed-grade systems. The first uses the maximum guaranteed toggle rate of a
CLB flip-flop measured in MHz as a suffixso higher is faster. For example a
Xilinx XC3020-125 has a toggle frequency of 125 MHz. The other Xilinx
naming system (which supersedes the old scheme, since toggle frequency is
rather meaningless) uses the approximate delay time of the combinational logic
in a CLB in nanosecondsso lower is faster in this case. Thus, for example, an
XC4010-6 has t ILO = 6.0 ns (the correspondence between speed grade and t ILO
is fairly accurate for the XC2000, XC4000, and XC5200 but is less accurate for
the XC3000).
FIGURE 5.9 The Xilinx
LCA timing model. The
paths show different uses
of CLBs (configurable
logic blocks). The
parameters shown are for
an XC5210-6. ( Source:
Xilinx.)
The inclusion of flip-flops and combinational logic inside the basic logic cell
leads to efficient implementation of state machines, for example. The
coarse-grain architecture of the Xilinx CLBs maximizes performance given the
size of the SRAM programming technology element. As a result of the increased
complexity of the basic logic cell we shall see (in Section 7.2, Xilinx LCA) that
the routing between cells is more complex than other FPGAs that use a simpler
basic logic cell.
1. Xilinx decided to use Logic Cell as a trademark in 1995 rather as if IBM were
to use Computer as a trademark today. Thus we should now only talk of a Xilinx
Logic Cell (with capital letters) and not Xilinx logic cells.
2. October 1995 (Version 3.0) data sheet.
5.3 Altera FLEX
Figure 5.10 shows the basic logic cell, a Logic Element ( LE ), that Altera uses in
its FLEX 8000 series of FPGAs. Apart from the cascade logic (which is slightly
simpler in the FLEX LE) the FLEX cell resembles the XC5200 LC architecture
shown in Figure 5.8 . This is not surprising since both architectures are based on
the same SRAM programming technology. The FLEX LE uses a four-input LUT,
a flip-flop, cascade logic, and carry logic. Eight LEs are stacked to form a Logic
Array Block (the same term as used in the MAX series, but with a different
meaning).
FIGURE 5.10 The Altera FLEX architecture. (a) Chip floorplan. (b) LAB
(Logic Array Block). (c) Details of the LE (Logic Element). ( Source: Altera
(adapted with permission).)
5.4 Altera MAX
Suppose we have a simple two-level logic circuit that implements a sum of products
as shown in Figure 5.11 (a). We may redraw any two-level circuit using a regular
structure ( Figure 5.11 b): a vector of buffers, followed by a vector of AND gates
(which construct the product terms) that feed OR gates (which form the sums of the
product terms). We can simplify this representation still further ( Figure 5.11 c), by
drawing the input lines to a multiple-input AND gate as if they were one horizontal
wire, which we call a product-term line . A structure such as Figure 5.11 (c) is called
programmable array logic , first introduced by Monolithic Memories as the PAL
series of devices.
FIGURE 5.11 Logic arrays. (a) Two-level logic. (b) Organized sum of products.
(c) A programmable-AND plane. (d) EPROM logic array. (e) Wired logic.
Because the arrangement of Figure 5.11 (c) is very similar to a ROM, we sometimes
call a horizontal product-term line, which would be the bit output from a ROM, the bit
line . The vertical input line is the word line . Figure 5.11 (d) and (e) show how to
build the programmable-AND array (or product-term array) from EPROM transistors.
The horizontal product-term lines connect to the vertical input lines using the EPROM
transistors as pull-downs at each possible connection. Applying a '1' to the gate of an
unprogrammed EPROM transistor pulls the product-term line low to a '0'. A
programmed n -channel transistor has a threshold voltage higher than V DD and is
therefore always off . Thus a programmed transistor has no effect on the product-term
line.
Notice that connecting the n -channel EPROM transistors to a pull-up resistor as
shown in Figure 5.11 (e) produces a wired-logic functionthe output is high only if all
of the outputs are high, resulting in a wired-AND function of the outputs. The
product-term line is low when any of the inputs are high. Thus, to convert the
wired-logic array into a programmable-AND array, we need to invert the sense of the
inputs. We often conveniently omit these details when we draw the schematics of
logic arrays, usually implemented as NORNOR arrays (so we need to invert the
outputs as well). They are not minor details when you implement the layout, however.
Figure 5.12 shows how a programmable-AND array can be combined with other logic
into a macrocell that contains a flip-flop. For example, the widely used 22V10 PLD,
also called a registered PAL, essentially contains 10 of the macrocells shown in
Figure 5.12 . The part number, 22V10, denotes that there are 22 inputs (44 vertical
input lines for both true and complement forms of the inputs) to the programmable
AND array and 10 macrocells. The PLD or registered PAL shown in Figure 5.12 has
an 2 i ¥ jk programmable-AND array.
FIGURE 5.12 A registered PAL with i inputs, j product terms, and k macrocells.
5.4.1 Logic Expanders
The basic logic cell for the Altera MAX architecture, a macrocell, is a descendant of
the PAL. Using the logic expander , shown in Figure 5.13 to generate extra logic
terms, it is possible to implement functions that require more product terms than are
available in a simple PAL macrocell. As an example, consider the following function:
F = A' · C · D + B' · C · D + A · B + B · C'.(5.22)
This function has four product terms and thus we cannot implement F using a
macrocell that has only a three-wide OR array (such as the one shown in Figure 5.13
). If we rewrite F as a sum of (products of products) like this:
F = (A' + B') · C · D + (A + C') · B
= (A · B)' (C · D) + (A' · C)' · B ;(5.23)
we can use logic expanders to form the expander terms (A · B)' and (A' · C)' (see
Figure 5.13 ). We can even share these extra product terms with other macrocells if
we need to. We call the extra logic gates that form these shareable product terms a
shared logic expander , or just shared expander .
FIGURE 5.13 Expander logic and programmable inversion. An expander increases
the number of product terms available and programmable inversion allows you to
reduce the number of product terms you need.
The disadvantage of the shared expanders is the extra logic delay incurred because of
the second pass that you need to take through the product-term array. We usually do
not know before the logic tools assign logic to macrocells ( logic assignment )
whether we need to use the logic expanders. Since we cannot predict the exact timing
the Altera MAX architecture is not strictly deterministic . However, once we do know
whether a signal has to go through the array once or twice, we can simply and
accurately predict the delay. This is a very important and useful feature of the Altera
MAX architecture.
The expander terms are sometimes called helper terms when you use a PAL. If you
use helper terms in a 22V10, for example, you have to go out to the chip I/O pad and
then back into the programmable array again, using two-pass logic .
FIGURE 5.14 Use of programmed inversion to simplify logic: (a) The function F =
A · B' + A · C' + A · D' + A' · C · D requires four product terms (P1P4) to implement
while (b) the complement, F ' = A · B · C · D + A' · D' + A' · C' requires only three
product terms (P1P3).
Another common feature in complex PLDs, also used in some PLDs, is shown in
Figure 5.13 . Programming one input of the XOR gate at the macrocell output allows
you to choose whether or not to invert the output (a '1' for inversion or to a '0' for no
inversion). This programmable inversion can reduce the required number of product
terms by using a de Morgan equivalent representation instead of a conventional
sum-of-products form, as shown in Figure 5.14 .
As an example of using programmable inversion, consider the function
F = A · B' + A · C' + A · D' + A' · C · D ,(5.24)
which requires four product termsone too many for a three-wide OR array.
If we generate the complement of F instead,
F ' = A · B · C · D + A' · D' + A' · C' ,(5.25)
this has only three product terms. To create F we invert F ', using programmable
inversion.
Figure 5.15 shows an Altera MAX macrocell and illustrates the architectures of
several different product families. The implementation details vary among the
families, but the basic features: wide programmable-AND array, narrow fixed-OR
array, logic expanders, and programmable inversionare very similar. 1 Each family
has the following individual characteristics:
● A typical MAX 5000 chip has: 8 dedicated inputs (with both true and
complement forms); 24 inputs from the chipwide interconnect (true and
complement); and either 32 or 64 shared expander terms (single polarity). The
MAX 5000 LAB looks like a 32V16 PLD (ignoring the expander terms).
● The MAX 7000 LAB has 36 inputs from the chipwide interconnect and 16
shared expander terms; the MAX 7000 LAB looks like a 36V16 PLD.
● The MAX 9000 LAB has 33 inputs from the chipwide interconnect and 16 local
feedback inputs (as well as 16 shared expander terms); the MAX 9000 LAB
looks like a 49V16 PLD.
FIGURE 5.15 The Altera MAX architecture. (a) Organization of logic and
interconnect. (b) A MAX family LAB (Logic Array Block). (c) A MAX family
macrocell. The macrocell details vary between the MAX familiesthe functions
shown here are closest to those of the MAX 9000 family macrocells.
FIGURE 5.16 The timing model for the Altera MAX architecture. (a) A direct
path through the logic array and a register. (b) Timing for the direct path.
(c) Using a parallel expander. (d) Parallel expander timing. (e) Making two
passes through the logic array to use a shared expander. (f) Timing for the
shared expander (there is no register in this path). All timing values are in
nanoseconds for the MAX 9000 series, '15' speed grade. ( Source: Altera.)
5.4.2 Timing Model
Figure 5.16 shows the Altera MAX timing model for local signals. 2 For example, in
Figure 5.16 (a) an internal signal, I1, enters the local array (the LAB interconnect with
a fixed delay t 1 = t LOCAL = 0.5 ns), passes through the AND array (delay t 2 = t LAD
= 4.0 ns), and to the macrocell flip-flop (with setup time, t 3 = t SU = 3.0 ns, and clock
Q or register delay , t 4 = t RD = 1.0 ns). The path delay is thus: 0.5 + 4 +3 + 1 = 8.5
ns.
Figure 5.16 (c) illustrates the use of a parallel logic expander . This is different from
the case of the shared expander ( Figure 5.13 ), which required two passes in series
through the product-term array. Using a parallel logic expander, the extra product term
is generated in an adjacent macrocell in parallel with other product terms (not in series
as in a shared expander).
We can illustrate the difference between a parallel expander and a shared expander
using an example function that we have used before (Eq. 5.22 ),
F = A' · C · D + B' · C · D + A · B + B · C' .(5.26)
This time we shall use macrocell M1 in Figure 5.16 (d) to implement F1 equal to the
sum of the first three product terms in Eq. 5.26 . We use F1 (using the parallel
expander connection between adjacent macrocells shown in Figure 5.15 ) as an input
to macrocell M2. Now we can form F = F1 + B · C' without using more than three
inputs of an OR gate (the MAX 5000 has a three-wide OR array in the macrocell, the
MAX 9000, as shown in Figure 5.15 , is capable of handling five product terms in one
macrocellbut the principle is the same). The total delay is the same as before, except
that we add the delay of a parallel expander, t PEXP = 1.0 ns. Total delay is then 8.5 +
1 = 9.5 ns.
Figure 5.16 (e) and (f) shows the use of a shared expandersimilar to Figure 5.13 .
The Altera MAX macrocell is more like a PLD than the other FPGA architectures
discussed here; that is why Altera calls the MAX architecture a complex PLD. This
means that the MAX architecture works well in applications for which PLDs are most
useful: simple, fast logic with many inputs or variables.
5.4.3 Power Dissipation in Complex PLDs
A programmable-AND array in any PLD built using EPROM or EEPROM transistors
uses a passive pull-up (a resistor or current source), and these macrocells consume
static power . Altera uses a switch called the Turbo Bit to control the current in the
programmable-AND array in each macrocell. For the MAX 7000, static current varies
between 1.4 mA and 2.2 mA per macrocell in high-power mode (the current depends
on the partgenerally, but not always, the larger 7000 parts have lower operating
currents) and between 0.6 mA and 0.8 mA in low-power mode. For the MAX 9000,
the static current is 0.6 mA per macrocell in high-current mode and 0.3 mA in
low-power mode, independent of the part size. 3 Since there are 16 macrocells in a
LAB and up to 35 LABs on the largest MAX 9000 chip (16 ¥ 35 = 560 macrocells),
just the static power dissipation in low-power mode can be substantial (560 ¥ 0.3 mA
¥ 5 V = 840 mW). If all the macrocells are in high-power mode, the static power will
double. This is the price you pay for having an (up to) 114-wide AND gate delay of a
few nanoseconds (t LAD = 4.0 ns) in the MAX 9000. For any MAX 9000 macrocell in
the low-power mode it is necessary to add a delay of between 15 ns and 20 ns to any
signal path through the local interconnect and logic array (including t LAD and t PEXP
).
1. 1995 data book p. 274 (5000), p. 160 (7000), p. 126 (9000).
2. March 1995 data sheet, v2.
5.5 Summary
Table 5.4 is a look-up table to Tables 5.5 5.9 , which summarize the features of the
logic cells used by the various FPGA vendors.
TABLE 5.4 Logic cell tables.
Programmable ASIC family
Actel (ACT 1)
Programmable ASIC family
Actel (ACT 3)
Table 5.5
Xilinx (XC3000)
Table 5.8 Xilinx LCA (XC5200)
Actel (ACT 2)
Altera FLEX (8000/10k)
Xilinx (XC4000)
Altera MAX (EPM 5000)
AMD MACH 5
Table 5.6 Xilinx EPLD (XC7200/7300) Table 5.9 Actel 3200DX
QuickLogic (pASIC 1)
Crosspoint (CP20K)
Altera MAX (EPM 9000)
Table 5.7 Altera MAX (EPM 7000)
Atmel (AT6000)
TABLE 5.5 Logic cells used by programmable ASICs.
Actel
Xilinx
Actel ACT 2
Xilinx XC4000
ACT 1
XC3000
C-Module
Logic
CLB
CLB
Basic
(combinatorial-module)
module
(Configurable
(Configurable
logic cell
and S-Module
(LM)
Logic Block)
Logic Block)
(sequential module)
32-bit LUT, 2 D
C-Module: 4:1 MUX, flip-flops, 10
2-input OR, 2-input
MUXes,
Three
32-bit LUT, 2 AND
including fast
Logic cell
2:1MUXes
D flip-flops, 9
carry logic
contents
plus OR
S-Module: 4-input
MUXes
gate
MUX, 2-input OR,
E-suffix parts
latch or D flip-flop
Logic path
delay
Fixed
Fixed with
ability to
bypass FF
Fixed
contain dual-port
RAM.
Fixed with
ability to bypass
FF
Two 4-input
LUTs plus
combiner with
ninth input
Most
3-input,
Combinational many
All 5-input
Most 3- and 4-input
logic
4-input
functions plus functions (total 766
functions
functions 2 D flip-flops macros)
(total 702
macros)
CLB as 32-bit
SRAM (except
D-suffix parts)
1 LM
required 2 D-flip-flops
1 S-Module per D
Flip-flop (FF) for latch, 2 per CLB,
LMs
latches can be flip-flop; some FFs
implementation required built from
require 2 modules.
for
pre-FF logic.
flip-flops
LMs:
Basic logic
cells
in each chip
2 D flip-flops
per CLB
64 (XC4002A)
64
(XC3020/A/L,
XC3120/A)
100
(XC4003/A/E/H)
100
A1225:
(XC3030/A/L,
A1010:
451 = 231 S + 220 C
352 (8R XC3130/A)
¥ 44C)
144
144 (XC4004A)
= 295 + (XC3042/A/L, A1240:
XC3142/A)
57 I/O
684 = 348 S + 336 C
224
(XC3064/A/L,
A1020: XC3164/A)
A1280:
616 (14
R ¥ 44C) 320
(XC3090/A/L, 1232 = 624 S + 608 C
= 547 + XC3190/A)
69 I/O
484
(XC3195/A)
256 (XC4006/E)
196
(XC4005/A/E/H)
324 (XC4008/E)
400
(XC4010/D/E)
576
(XC4013/D/E)
784 (XC4020/E)
1024
(XC4025/E)
TABLE 5.6 Logic cells used by programmable ASICs.
Altera MAX 5000
Basic
logic cell
Xilinx XC7200/7300
QuickLogic
pASIC 1
16 macrocells in a LAB
(Logic Array Block)
9 macrocells within a
except EPM5032,
FB (Functional Block),
Logic Cell (LC)
which has 32
fast FBs (FFBs) omit
macrocells in a single ALU
LAB
Logic cell
contents
Macrocell: 64
106-wide AND,
3-wide OR array, 1
flip-flop, 2 MUXes,
programmable
inversion. 3264 shared
logic expander OR
terms.
Macrocell: 21-wide
AND, 16-wide OR
array, 1 flip-flop,
1ALU
Four 2-input and
two 6-input AND,
three 2:1 MUXes
and one D flip-flop
FB looks like 21V9
PLD.
LAB looks like a
32V16 PLD.
Logic path
Fixed (unless using
Fixed
delay
shared logic expanders)
Combinational Wide input functions Wide input functions
logic functions with ability to share
with added 2-input
per logic cell
product terms
ALU
1 D flip-flop or latch
Flip-flop (FF) per macrocell. More
1 D flip-flop or latch
implementation can be constructed in per macrocell
arrays.
FBs:
Fixed
All 3-input
functions
1 D flip-flop per
LC. LCs for other
flip-flops not
specified.
4 (XC7236A)
LABs:
8 (XC7272A)
48 (QL6X8)
32 (EPM5032)
2 (XC7318)
Basic logic cells 64 (EPM5064)
in each chip
128 (EPM5128)
96 (QL8X12)
4 (XC7336)
192 (QL12X16)
6 (XC7354)
384 (QL16X24)
128 (EPM5130)
8 (XC7372)
192 (EPM5192)
12 (XC73108)
16 (XC73144)
TABLE 5.7 Logic cells used by programmable ASICs.
Crosspoint CP20K
Altera MAX 7k
Transistor-pair tile
16 macrocells in a
Basic
(TPT), RAM-logic
LAB (Logic Array
logic cell
Tile (RLT)
Block)
Atmel AT6000
Cell
Logic cell
contents
Logic path
delay
Macrocell: wide
AND, 5-wide OR
array, 1 flip-flop, 3
TPT: 2 transistors
MUXes,
(0.5 gate). RLT: 3
programmable
inverters, two 3-input inversion. 16 shared
NANDs, 2-input
logic expander OR
NAND, 2-input
terms, plus parallel
AND.
logic expander.
Variable
LAB looks like a
36V16 PLD.
Fixed (unless using
shared logic
expanders)
Two 5:1 MUXes, two
4:1 MUXes, 3:1
MUX, three 2:1
MUXes, 6 pass gates,
four 2-input gates, 1
D flip-flop
Variable
1-, 2-, and 3-input
Combinational TPT is smaller than a Wide input functions combinational
functions
gate, approx. 2 TPTs with ability to share configurations:
per logic cell
= 1 gate.
product terms
44 logical states and
72 physical states
1 D flip-flop or latch
D flip-flop requires 2 per macrocell. More
1 D flip-flop per cell
can be constructed in
implementation RLTs and 9 TPTs
arrays.
Macrocells:
TPTs:
32 (EPM7032/V)
1760 (20220)
1024 (AT6002)
64 (EPM7064)
15,876 (22000)
1600 (AT6003)
96 (EPM7096)
Basic logic cells
Flip-flop (FF)
in each chip
128 (EPM70128E) 3136 (AT6005)
RLTs:
160 (EPM70160E) 6400(AT6010)
440 (20220)
192 (EPM70192E)
3969 (22000)
256 (EPM70256E)
TABLE 5.8 Logic cells used by programmable ASICs.
Actel ACT 3
Xilinx XC5200
Altera FLEX
8000/10k
2 types of Logic
Module:
C-Module and
4 Logic Cells (LC)
8 Logic Elements
Basic
in a CLB
(LE) in a Logic Array
logic cell
(Configurable Logic
S-Module
Block (LAB )
(similar but not Block)
identical to
ACT 2)
C-Module: 4:1
MUX, 2-input
16-bit LUT,
OR, 2-input
1 programmable
LC has 16-bit LUT,
Logic cell contents
AND.
flip-flop or latch,
1 flip-flop (or latch),
MUX logic for
(LUT = look-up table) S-Module: 4:1 4 MUXes
control, carry logic,
MUX, 2-input
cascade logic
OR, latch or D
flip-flop.
Fixed with ability to
Logic path delay
Fixed
Fixed
bypass FF
One 4-input LUT
Most 3- and
Combinational
per LC may be
4-input LUT may be
4-input
functions
combined with
cascaded with
functions (total
per logic cell
adjacent LC to form adjacent LE
766 macros)
5-input LUT
1 D flip-flop (or
latch) per
1 D flip-flop (or
Flip-flop (FF)
1 D flip-flop (or latch)
S-Module; some latch) per LC (4 per
per LE
implementation
FFs require 2
CLB)
modules.
LEs:
208 (EPF8282/V/A
/AV)
336 (EPF8452/A)
A1415: 104 S +
96 C
Basic logic cells
in each chip
A1425: 160 S + 64 CLB (XC5202)
150 C
120 CLB (XC5204)
A1440: 288 S +
196 CLB (XC5206)
276 C
324 CLB (XC5210)
A1460: 432 S +
416 C
484 CLB (XC5215)
A14100: 697 S
504 (EPF8636A)
672 (EPF8820/A)
1008 (EPF81188/A)
1296 (EPF81500/A)
576 (EPF10K10)
1152 (EPF10K20)
1728 (EPF10K30)
+ 680 C
2304 (EPF10K40)
2880 (EPF10K50)
3744 (EPF10K70)
4992 (EPF10K100)
TABLE 5.9 Logic cells used by programmable ASICs.
AMD MACH 5
Actel 3200DX
4 PAL Blocks in a Based on ACT 2,
Basic
Segment, 16
plus D-module
logic cell
macrocells in a PAL (decode) and
Block
dual-port SRAM
C-Module: 4:1
MUX, 2-input
OR, 2-input
AND
Logic cell
contents
Combinational
functions per logic
cell
Flip-flop (FF)
implementation
16 macrocells in a
LAB (Logic Array
Block)
Macrocell: 114-wide
AND, 5-wide OR
array, 1 flip-flop, 5
MUXes,
20-bit to 32-bit wide S-Module:
programmable
OR array, switching 4-input MUX,
inversion. 16 shared
logic, XOR gate,
2-input OR, latch
logic expander OR
programmable
or D flip-flop
terms, plus parallel
flip-flop
logic expander.
D-module:
7-input AND,
2-input XOR
Logic path
delay
Altera MAX 9000
Fixed
Fixed
Most 3- and
4-input functions
Wide input functions
(total 766
macros)
1 D flip-flop or
latch per
1 D flip-flop or latch
S-Module; some
per macrocell
FFs require 2
modules.
LAB looks like a
49V16 PLD.
Fixed (unless using
expanders)
Wide input functions
with ability to share
product terms
1 D flip-flop or latch
per macrocell. More
can be constructed in
arrays.
A3265DX: 510 S
+ 475 C + 20 D
Macrocells:
A32100DX: 700
S + 662 C + 20 D 320 (EPM9320) 4
+ 2 kSRAM
¥5
128 (M5-128)
192 (M5-192)
Basic logic cells
in each chip
256 (M5-256)
320 (M5-320)
384 (M5-384)
512 (M5-512)
A32140D): 954 S
+ 912 C + 24 D
A32200DX:
1 230 S + 1 184
C + 24 D + 2.5
kSRAM
A32300DX:
1 888 S + 1 833
C + 28 D +
3kSRAM
A32400DX:
2 526 S + 2 466
C + 28 D + 4
kSRAM
LABs
400 (EPM9400) 5
¥5
LABs
480 (EPM9480) 6
¥5
LABs
560 (EPM9560) 7
¥5
LABs
The key points in this chapter are:
● The use of multiplexers, look-up tables, and programmable logic arrays
● The difference between fine-grain and coarse-grain FPGA architectures
● Worst-case timing design
● Flip-flop timing
● Timing models
● Components of power dissipation in programmable ASICs
● Deterministic and nondeterministic FPGA architectures
Next, in Chapter 6, we shall examine the I/O cells used by the various programmable
ASIC families.
5.6 Problems
* = Difficult, ** = Very difficult, *** = Extremely difficult
5.1 (Using the ACT 1 Logic Module, 30 min.) Consider the Actel ACT 1 Logic
Module shown in Figure 5.1 . Show how to implement: (a) a three-input NOR
gate, (b) a three-input majority function gate, (c) a 2:1 MUX, (d) a half adder,
(e) a three-input XOR gate, and (f) a four-input MUX.
5.2 (Worst-case and best-case timing, 10 min.) Seasoned digital CMOS designers
do not worry too much when their designs stop working when they get too hot or
when they reduce the supply voltage, but an ASIC that stops working either when
increasing the supply voltage above normal or when it gets cold causes panic.
Why?
5.3 (Typical to worst-case variation, 10 min.) The 1994 Actel data book (p. 1-5)
remarks that: the total derating factor from typical to worst-case for a standard
ACT 1 array is only 1.19:1, compared to 2:1 for a masked gate array.
● a. Can you explain why this is when the basic ACT 1 CMOS process is
identical to a CMOS process for masked gate arrays?
● b. There is a price to pay for the reduced spread in timing delays from
typical to worst-case in an ACT 1 array. What is this disadvantage of the
ACT 1 array over a masked gate array?
5.4 (ACT 2/3 sequential element, 30 min.). Show how the Actel ACT 2 and
ACT 3 sequential element of Figure 5.4 (used in the S-Module) can be wired to
implement:
● a. a positive-edgetriggered flip-flop with clear,
● b. a negative-edgetriggered flip-flop with clear,
● c. a transparent-high latch,
● d. a transparent-low latch, and
● e. how it can be made totally transparent.
5.5 (*ACT 1 logic functions, 40 min.+)
● a. How many different combinational functions of four logic variables are
there?
● b. of n variables? Hint: Consider the truth table.
● c. The ACT 1 module can implement 213 of the 256 functions with three
variables. How many of the 43 three-input functions that it cannot
●
implement can you find?
d. (harder) Show that if you have access to both the true and complement
form of the input variables you can implement all 256 logic functions of
three variables with the ACT 1 Logic Module.
5.6 (Actel and Xilinx, 10 min.) The Actel Logic Modules (ACT 1, ACT 2, and
ACT 3) have eight inputs and can implement most three-input logic functions and
a few logic functions with four input variables. In contrast, the Xilinx XC5200
CLB, for example, has only four inputs but can implement all logic functions
with four or fewer variables. Why would Actel choose these logic cell designs
and how can they be competitive with the Xilinx FPGA (which they are)?
5.7 (Actel address decoders, 10 min.) The maximum number of inputs that the
ACT 1 Logic Module can handle is four. The ACT 2/ACT 3 C-module increases
this to five.
● a. How many ACT 1 Logic Modules do you need to implement a 32-bit
wide address decoder (a 32-input AND gate)?
● b. How many ACT 2/ACT 3 C-modules do you need?
5.8 (Altera shared logic expanders, 30 min.) Consider an Altera MAX 5000 logic
array with three product-term lines. You cannot directly implement the function
Z = A · B · C + A · B' · C' + A' · B · C' + A' · B' · C with a programmable array
logic macrocell that has only three product-term lines, since Z has four product
terms.
● a. How many Boolean functions of three variables are there that cannot be
implemented with a programmable array logic macrocell that has only
three product terms? Hint: Use a Karnaugh map to consider how many
Boolean functions of three variables have more than three product terms in
their sum-of-products representation.
● b. Show how to use shared logic expanders that feed terms back into the
product-term array to implement the function Z using a macrocell with
three product terms.
● c. How many shared expander lines do you need to add to be able to
implement all the Boolean functions of three variables?
● d. What is the largest number of product terms that you need to implement
a Boolean function with n variables?
5.9 (Splitting the XC3000 CLB, 20 min.) In Section 5.2.1 we noted You can split
the (XC3000) 32-bit LUT in half, using one of the seven input variables to switch
between the F and G outputs. This technique can implement some functions of
six and seven variables.
● a. Show which functions of six and seven variables can, and
● b. which functions cannot, be implemented using this method.
5.10 (Programmable inversion, 20 min.) Section 5.4 described how the Altera
MAX series logic cells can use programmable inversion to reduce the number of
product terms needed to implement a function. Give another example of a
function of four variables that requires four product terms. Is there a way to tell
how many product terms a function may require?
5.11 (Table look-up mapping, 20 min.) Consider a four-input LUT (used in the
CLB in the Xilinx XC2000, the first generation of Xilinx FPGAs, and in the
XC5200 LE). This CLB can implement any Boolean function of four variables.
Consider the function
Z = (A · (B + C)) + (B · D) + (E · F · G · H · I) .(5.27)
We can use four CLBs to implement Z as follows:
CLB1: Z = Z1 + (B · D) + Z3 ,
CLB2: Z1 = A · (B + C) ,
CLB3: Z3 = E · F · G · Z5 ,
CLB4: Z5 = H · I .(5.28)
What is the length of the critical path? Find a better assignment in terms of area
and critical path.
5.12 (Multiplexer mapping, 10 min.) Consider the function:
F = (A · B) + (B' · C) + D .(5.29)
Use Shannons expansion theorem to expand F wrt B:
F = B · F1 + B' · F2 .(5.30)
In other words express F in terms of B, B', F1, and F2 ( Hint: F1 is a function of
A and D only, F2 is a function of C and D only). Now expand F1 wrt A, and F2
wrt C. Using your answer, implement F using a single ACT 1 Logic Module.
5.13 (*Xilinx hazards, 10 min.) Explain why the outputs of the Xilinx CLBs are
hazard-free for input changes in only one variable. Is this important?
5.14 (**Actel S-Modules, 10 min.) Notice that CLR is tied to the input
corresponding to B0 of the C-module in the ACT 2 S-Module but the CLR input
is separate from the B0 input in the ACT 3 version. Why?
5.15 (**Timing estimates, 60 min.) Using data book values for an FPGA
architecture that you choose, and explaining your calculations carefully, estimate
the (worst-case commercial) delay for the following functions: (a) 16-bit address
decoder, (b) 8-bit ripple-carry adder, (c) 8-bit ripple-carry counter. Give your
answers in terms of the data book symbols, and using actual parameters, for a
speed grade that you specify, give an example calculation with the delay in ns.
5.16 (Actel logic. 30 min.) Table 5.10 shows how to use the Actel ACT 1 Logic
Module to implement some of the 16 functions of two input variables. Complete
this table.
TABLE 5.10 Boolean functions using the ACT 1 Logic Module (Problem 5.16).
M1
M2
OR1
Function, F
F = Canonical form Minterms
A0 A1 SA B0 B1 SB S0 S1
1 0
0
0
0 0 0
2 AND(A, B)
A·BA·B
3
0 B A
A·
3 AND1-1(A, B)
A · B'
2
A 0 B
B'
A+
4 NOR(A, B)
A' · B'
0
B
A+
5 NOR1-1(A, B)
A' · B
1
B 0 A
B'
6 A
A
A · B' + A · B 2, 3
0 A 1
7 B
B
A' · B + A · B 1, 3
0 B 1
8 NOT(A)
A'
A' · B' + A' · B 0, 1
0 1 A
9 NOT(B)
B'
A' · B' + A · B' 0, 2
0 1 B
A•
10 EXOR(A, B)
A' · B + A · B' 1, 2
B
(A •
11 EXNOR(A, B)
A' · B' + A · B 0, 3
B)
A + A' · B + A · B' +
12 OR(A, B)
1, 2, 3
B 1 A
B
A·B
A + A' · B' + A · B'
13 OR1-1(A, B)
0, 2, 3
B'
+A·B
(A · A' · B' + A' · B
14 NAND(A, B)
0, 1, 2
B)' + A · B'
(A · A' · B' + A' · B
15 NAND1-1(A, B)
0, 1, 3
B')' + A · B
A' · B' + A' · B
16 1
1
0, 1, 2, 3 1 1 1
+ A · B' + A · B
5.17 (ACT 1 module implementation, 120 min.)
● a. Show that the circuit shown in Figure 5.17 , with buffered inputs and
outputs, is equivalent to the one shown in Figure 5.1 .
FIGURE 5.17 An alternative
implementation of the ACT 1
Logic Module shown in
Figure 5.1 (Problem 5.17).
●
●
●
b. Show that the circuit for the ACT 1 Logic Module shown in Figure 5.18
is also the same.
c. Convert the circuit of Figure 5.18 to one that uses more efficient CMOS
gates: inverters, AOI, and NAND gates.
d. (harder) Assume that the ACT 1 Logic Module has the equivalent of a
2X drive and the logic ratio is close to one. Compare your answer to part c
against Figure 5.17 in terms of logical efficiency and logical area.
FIGURE 5.18
A schematic
equivalent of
the Actel
ACT 1 Logic
Module
(Problem
5.17).
5.18 (**Xilinx CLB analysis, 60 min.) Table 5.11 shows some information
derived from a die photo in the AT&T ATT3000 series data book that shows the
eight by eight CLB matrix on an ATT3020 (equivalent to a XC3020) clearly. By
measuring the die size in the photo and knowing the actual die size we can
calculate the size of a CLB matrix element ( ME ) that includes a single XC3000
CLB as approximately 277 mil 2 . The ME includes interconnect, SRAM,
programming, and other resources as well as a CLB.
TABLE 5.11 ATT3020 die information (Problem 5.18). 1
Parameter
Data book Die photo
Calculated
3020 die width 183.5 mil 4.1 cm
3020 die height 219.3 mil
3000 ME width
3000 ME height
3000 ME area
3020 pad pitch
●
●
●
4.9 cm
0.325 cm
0.425 cm
14.55 mil = 370 m m
19.02 mil = 483 m m
277 mil 2
1.6 mm / pad 7.21 mil / pad
a. The minimum feature size in the AT&T Holmdel twin-tub V process
used for the ATT3000 family is 0.9 m m. Using a value of l = 0.45 m m,
calculate the Xilinx XC3000 ME size in l 2 .
b. Estimate, explaining your assumptions, the area of the XC4000 ME, and
the XC5200 ME (both in l 2 ).
c. Table 5.12 shows the ATT3000 die information. Using a value of 277
mil 2 for the ATT/XC3000 ME area, complete this table.
TABLE 5.12 ATT3000 die information (Problem 5.18). 2
Die height Die width
Die
mil
3020 219.3
3030 259.8
3042 295.3
3064 270.9
3090 437.0
mil
183.5
215.0
242.5
366.5
299.2
Die
Die area mil 2 area
40,242
55,857
71,610
99,285
130,750
cm2
0.26
0.36
0.46
0.64
0.84
ME
CLBs area
mil 2
ME
area
cm2
8¥8
10 ¥ 10
12 ¥ 12
16 ¥ 14
16 ¥ 20
1. Data from AT&T data book, July 1992, p. 3-76, MN92-024FPGA
2. Data from AT&T data book, July 1992, p. 3-75, MN92-024FPGA. 1 mil 2 = 10
6 in 2 = 2.54 2 ¥ 10 6 cm 2 = 6.452 ¥ 10 6 cm 2
5.7 Bibliography
The book by Brown et al. [ 1992] on FPGAs deals with commercially available
FPGAs and logic block architecture. There are several easily readable articles on
FPGAs in the July 1993 issue of the IEEE Proceedings including articles by Rose
et al. [ 1993] and Greene et al. [ 1993]. Greenes article is a good place to start
digging deeper into the Actel FPGA architecture and gives an idea of the very
complex problem of programming antifuses, something we have not discussed.
Trimberger, who works at Xilinx, has edited a book on FPGAs [ 1994]. For those
wishing to understand even more about the trade-offs in the different
programmable ASIC architectures, a student of Stanford Professor Abbas El
Gamal (one of the cofounders of Actel) has completed a Ph.D. on this topic
[Kouloheris, 1993]. The best resources for information on FPGAs and their logic
cells are the manufacturers data sheets, data books, and application notes. The
data books change every year or so as new products are released, so it is difficult
to give specific references, but Xilinx, Actel, and Altera currently produce huge
volumes complete with excellent design guides and application notesyou should
obtain each of these even if you are not currently using that particular technology.
Many of these are also online in Adobe Acrobat and PostScript format as well as
in CD-ROM format (see also the bibliography in Chapter 4).
5.8 References
Brown, S. D., et al. 1992. Field-Programmable Gate Arrays. Norwell, MA:
Kluwer Academic. 206 p. ISBN 0-7923-9248-5. TK7872.L64F54. Introduction
to FPGAs, Commercially Available FPGAs, Technology Mapping for FPGAs,
Logic Block Architecture, Routing for FPGAs, Flexibility of FPGA Routing
Resources, A Theoretical Model for FPGA Routing. Includes an introduction to
commercially available FPGAs. The rest of the book covers research on logic
synthesis for FPGAs and FPGA architectures, concentrating on LUT-based
architectures.
Greene, J., et al. 1993. Antifuse field programmable gate arrays. Proceedings of
the IEEE, vol. 81, no. 7, pp. 10421056. Review article describing the Actel
FPGAs. (Included in the Actel 1994 data book.)
Kouloheris, J. L. 1993. Empirical study of the effect of cell granularity on FPGA
density and performance. Ph.D. Thesis, Stanford, CA. 114 p. Detailed research
study of the different FPGA architectures concentrating on structures similar to
the Actel and Altera FPGAs.
Rose, J., et al. 1993. A classification and survey of field-programmable gate
array architectures. Proceedings of the IEEE, vol. 81, no. 7.
Trimberger, S. M. (Ed.). 1994. Field-Programmable Gate Array Technology.
Boston: Kluwer Academic Publishers. ISBN 0-7923-9419-4. TK7895.G36.F54.
L ast E d ited by S P 141 1 2 0 0 4
PROGRAMMABLE
ASIC I/O CELLS
All programmable ASICs contain some type of input/output cell ( I/O cell ).
These I/O cells handle driving logic signals off-chip, receiving and conditioning
external inputs, as well as handling such things as electrostatic protection. This
chapter explains the different types of I/O cells that are used in programmable
ASICs and their functions.
The following are different types of I/O requirements.
● DC output. Driving a resistive load at DC or low frequency (less than 1
MHz). Example loads are light-emitting diodes (LEDs), relays, small
motors, and such. Can we supply an output signal with enough voltage,
current, power, or energy?
● AC output. Driving a capacitive load with a high-speed (greater than 1
MHz) logic signal off-chip. Example loads are other logic chips, a data or
address bus, ribbon cable. Can we supply a valid signal fast enough?
● DC input. Example sources are a switch, sensor, or another logic chip. Can
we correctly interpret the digital value of the input?
● AC input. Example sources are high-speed logic signals (higher than 1
MHz) from another chip. Can we correctly interpret the input quickly
enough?
● Clock input. Examples are system clocks or signals on a synchronous bus.
Can we transfer the timing information from the input to the appropriate
places on the chip correctly and quickly enough?
● Power input. We need to supply power to the I/O cells and the logic in the
core, without introducing voltage drops or noise. We may also need a
separate power supply to program the chip.
These issues are common to all FPGAs (and all ICs) so that the design of FPGA
I/O cells is driven by the I/O requirements as well as the programming
technology.
6.1 DC Output
Figure 6.1 shows a robot arm driven by three small motors together with switches
to control the motors. The motor armature current varies between 50 mA and
nearly 0.5 A when the motor is stalled. Can we replace the switches with an
FPGA and drive the motors directly?
FIGURE 6.1 A robot arm.
(a) Three small DC motors drive
the arm. (b) Switches control
each motor.
Figure 6.2 shows a CMOS complementary output buffer used in many FPGA I/O
cells and its DC characteristics. Data books typically specify the output
characteristics at two points, A (V OHmin , I OHmax ) and B ( V OLmax , I OLmax ),
as shown in Figure 6.2 (d). As an example, values for the Xilinx XC5200 are as
follows 1 :
● V OLmax = 0.4 V, low-level output voltage at I OLmax = 8.0 mA.
●
V OHmin = 4.0 V, high-level output voltage at I OHmax = 8.0 mA.
By convention the output current , I O , is positive if it flows into the output.
Input currents, if there are any, are positive if they flow into the inputs. The
Xilinx XC5200 specifications show that the output buffer can force the output
pad to 0.4 V or lower and sink no more than 8 mA if the load requires it. CMOS
logic inputs that may be connected to the pad draw minute amounts of current,
but bipolar TTL inputs can require several milliamperes. Similarly, when the
output is 4 V, the buffer can source 8 mA. It is common to say that V OLmax = 0.4
V and V OHmin = 4.0 V for a technologywithout referring to the current values at
which these are measuredstrictly this is incorrect.
FIGURE 6.2 (a) A CMOS complementary output buffer. (b) Pull-down
transistor M2 (M1 is off) sinks (to GND) a current I OL through a pull-up
resistor, R 1 . (c) Pull-up transistor M1 (M2 is off) sources (from VDD) current
I OH ( I OH is negative) through a pull-down resistor, R 2 . (d) Output
characteristics.
If we force the output voltage , V O , of an output buffer, using a voltage supply,
and measure the output current, IO , that results, we find that a buffer is capable
of sourcing and sinking far more than the specified I OHmax and I OLmax values.
Most vendors do not specify output characteristics because they are difficult to
measure in production. Thus we normally do not know the value of I OLpeak or I
OHpeak ; typical values range from 50 to 200 mA.
Can we drive the motors by connecting several output buffers in parallel to reach
a peak drive current of 0.5 A? Some FPGA vendors do specifically allow you to
connect adjacent output cells in parallel to increase the output drive. If the output
cells are not adjacent or are on different chips, there is a risk of contention.
Contention will occur if, due to delays in the signal arriving at two output cells,
one output buffer tries to drive an output high while the other output buffer is
trying to drive the same output low. If this happens we essentially short VDD to
GND for a brief period. Although contention for short periods may not be
destructive, it increases power dissipation and should be avoided. 2
It is thus possible to parallel outputs to increase the DC drive capability, but it is
not a good idea to do so because we may damage or destroy the chip (by
exceeding the maximum metal electromigration limits). Figure 6.3 shows an
alternativea simple circuit to boost the drive capability of the output buffers. If
we need more power we could use two operational amplifiers ( op-amps )
connected as voltage followers in a bridge configuration. For even more power
we could use discrete power MOSFETs or power op-amps.
FIGURE 6.3 A circuit to drive
a small electric motor (0.5 A)
using ASIC I/O buffers. Any
npn transistors with a
reasonable gain ( b ª 100) that
are capable of handling the
peak current (0.5 A) will work
with an output buffer that is
capable of sourcing more than
5 mA. The 470 W resistors
drop up to 5 V if an output
buffer current approaches 10
mA, reducing the drive to the
output transistors.
6.1.1 Totem-Pole Output
Figure 6.4 (a) and (b) shows a totem-pole output buffer and its DC
characteristics. It is similar to the TTL totem-pole output from which it gets its
name (the totem-pole circuit has two stacked transistors of the same type,
whereas a complementary output uses transistors of opposite types). The
high-level voltage, V OHmin , for a totem pole is lower than VDD . Typically V
OHmin is in the range of 3.5 V to 4.0 V (with VDD = 5 V), which makes rising
and falling delays more symmetrical and more closely matches TTL voltage
levels. The disadvantage is that the totem pole will typically only drive the output
as high as 34 V; so this would not be a good choice of FPGA output buffer to
work with the circuit shown in Figure 6.3 .
FIGURE 6.4 Output buffer characteristics. (a) A CMOS totem-pole output stage
(both M1 and M2 are n -channel transistors). (b) Totem-pole output
characteristics. (c) Clamp diodes, D1 and D2, in an output buffer (these diodes
are present in all output bufferstotem-pole or complementary). (d) The clamp
diodes start to conduct as the output voltage exceeds the supply voltage bounds.
6.1.2 Clamp Diodes
Figure 6.4 (c) show the connection of clamp diodes (D1 and D2) that prevent the
I/O pad from voltage excursions greater than V DD and less than V SS . Figure 6.4
(d) shows the resulting characteristics.
1. XC5200 data sheet, October 1995 (v. 3.0).
2. Actel specifies a maximum I/O current of ± 20 mA for ACT3 family (1994
data book, p. 1-93) and its ES family. Altera specifies the maximum DC output
current per pin, for example ± 25 mA for the FLEX 10k (July 1995, v. 1 data
sheet, p. 42).
6.2 AC Output
Figure 6.5 shows an example of an off-chip three-state bus. Chips that have inputs and
outputs connected to a bus are called bus transceivers . Can we use FPGAs to perform
the role of bus transceivers? We will focus on one bit, B1, on bus BUSA, and we shall
call it BUSA.B1. We need unique names to refer to signals on each chip; thus
CHIP1.OE means the signal OE inside CHIP1. Notice that CHIP1.OE is not
connected to CHIP2.OE.
FIGURE 6.5 A three-state bus. (a) Bus parasitic capacitance. (b) The output buffers
in each chip. The ASIC CHIP1 contains a bus keeper, BK1.
Figure 6.6 shows the timing of part of a bus transaction (a sequence of signals on a
bus):
1. Initially CHIP2 drives BUSA.B1 high (CHIP2.D1 is '1' and CHIP2.OE is '1').
2. The buffer output enable on CHIP2 (CHIP2.OE) goes low, floating the bus. The
bus will stay high because we have a bus keeper, BK1.
3. The buffer output enable on CHIP3 (CHIP3.OE) goes high and the buffer drives
a low onto the bus (CHIP3.D1 is '0').
We wish to calculate the delays involved in driving the off-chip bus in Figure 6.6 . In
order to find t float , we need to understand how Actel specifies the delays for its I/O
cells. Figure 6.7 (a) shows the circuit used for measuring I/O delays for the ACT
FPGAs. These measurements do not use the same trip points that are used to
characterize the internal logic (Actel uses input and output trip points of 0.5 for
internal logic delays).
FIGURE 6.6 Three-state bus timing for
Figure 6.5 . The on-chip delays, t 2OE
and t 3OE , for the logic that generates
signals CHIP2.E1 and CHIP3.E1 are
derived from the timing models
described in Chapter 5 (the minimum
values for each chip would be the
clock-to-Q delay times).
FIGURE 6.7 (a) The test circuit for characterizing the ACT 2 and ACT 3 I/O delay
parameters. (b) Output buffer propagation delays from the data input to PAD (output
enable, E, is high). (c) Three-state delay with D low. (d) Three-state delay with D
high. Delays are shown for ACT 2 'Std' speed grade, worst-case commercial
conditions ( R L = 1 k W , C L = 50 pF, V OHmin = 2.4 V, V OLmax = 0.5 V). (The
Actel three-state buffer is named TRIBUFF, an input buffer INBUF, and the output
buffer, OUTBUF.)
Notice in Figure 6.7 (a) that when the output enable E is '0' the output is three-stated (
high-impedance or hi-Z ). Different companies use different polarity and naming
conventions for the output enable signal on a three-state buffer. To measure the
buffer delay (measured from the change in the enable signal, E) Actel uses a resistor
load ( R L = 1 k W for ACT 2). The resistor pulls the buffer output high or low
depending on whether we are measuring:
● t ENZL , when the output switches from hi-Z to '0'.
●
t ENLZ , when the output switches from '0' to hi-Z.
●
t ENZH , when the output switches from hi-Z to '1'.
●
t ENHZ , when the output switches from '1' to hi-Z.
Other vendors specify the time to float a three-state output buffer directly (t fr and t ff
in Figure 6.7 c and d). This delay time has different names (and definitions): disable
time , time to begin hi-Z , or time to turn off .
Actel does not specify the time to float but, since R L C L = 50 ns, we know t RC = R
L C L ln 0.9 or approximately 5.3 ns. Now we can estimate that
t fr = t ENLZ t RC = 11.1 5.3 = 5.8 ns, and t ff = 9.4 5.3 = 4.1 ns,
and thus the Actel buffer can float the bus in t float = 4.1 ns ( Figure 6.6 ).
The Xilinx FPGA is responsible for the second part of the bus transaction. The time to
make the buffer CHIP2.B1 active is t active . Once the buffer is active, the output
transistors turn on, conducting a current I peak . The output voltage V O across the load
capacitance, C BUS , will slew or change at a steady rate, d V O / d t = I peak / C BUS ;
thus t slew = C BUS D V O / I peak , where D V O is the change in output voltage.
Vendors do not always provide enough information to calculate t active and t slew
separately, but we can usually estimate their sum. Xilinx specifies the time from the
three-state input switching to the time the pad is active and valid for an XC3000-125
switching with a 50 pF load, to be t active = t TSON = 11 ns (fast option), and 27 ns
(slew-rate limited option). 1 If we need to drive the bus in less than one clock cycle
(30 ns), we will definitely need to use the fast option.
A supplement to the XC3000 timing data specifies the additional fall delay for
switching large capacitive loads (above 50 pF) as R fall = 0.06 nspF 1 (falling) and R
1
2
rise = 0.12 nspF (rising) using the fast output option. We can thus estimate that
I peak ª (5 V)/(0.06 ¥ 10 3 sF 1 ) ª 84 mA (falling)
and I peak ª (5 V)/(0.12 ¥ 10 3 sF 1 ) ª 42 mA (rising).
Now we can calculate,
t slew = R fall ( C BUS 50 pF) = (90 pF 50 pF) (0.06 nspF 1 ) or 2.4 ns ,
for a total falling delay of 11 + 2.4 = 13.4 ns. The rising delay is slower at 11 + (40
pF)(0.12 nspF 1 ) or 15.8 ns. This leaves (30 15.8) ns, or about 14 ns worst-case, to
generate the output enable signal CHIP2.OE (t 3OE in Figure 6.6 ) and still leave time t
spare before the bus data is latched on the next clock edge. We can thus probably use a
XC3000 part for a 30 MHz bus transceiver, but only if we use the fast slew-rate
option.
An aside: Our example looks a little like the PCI bus used on Pentium and PowerPC
systems, but the bus transactions are simplified. PCI buses use a sustained three-state
system ( s / t / s ). On the PCI bus an s / t / s driver must drive the bus high for at least
one clock cycle before letting it float. A new driver may not start driving the bus until
a clock edge after the previous driver floats it. After such a turnaround cycle a new
driver will always find the bus parked high.
6.2.1 Supply Bounce
Figure 6.8 (a) shows an n -channel transistor, M1, that is part of an output buffer
driving an output pad, OUT1; M2 and M3 form an inverter connected to an input pad,
IN1; and M4 and M5 are part of another output buffer connected to an output pad,
OUT2. As M1 sinks current pulling OUT1 low ( V o 1 in Figure 6.8 b), a substantial
current I OL may flow in the resistance, R S , and inductance, L S , that are between the
on-chip GND net and the off-chip, external ground connection.
FIGURE 6.8 Supply bounce. (a) As the pull-down device, M1, switches, it causes
the GND net (value V SS ) to bounce. (b) The supply bounce is dependent on the
output slew rate. (c) Ground bounce can cause other output buffers to generate a logic
glitch. (d) Bounce can also cause errors on other inputs.
The voltage drop across R S and L S causes a spike (or transient) on the GND net,
changing the value of V SS , leading to a problem known as supply bounce . The
situation is illustrated in Figure 6.8 (a), with V SS bouncing to a maximum of V OLP .
This ground bounce causes the voltage at the output, V o 2 , to bounce also. If the
threshold of the gate that OUT2 is driving is a TTL level at 1.4 V, for example, a
ground bounce of more than 1.4 V will cause a logic high glitch (a momentary
transition from one logic level to the opposite logic level and back again).
Ground bounce may also cause problems at chip inputs. Suppose the inverter M2/M3
is set to have a TTL threshold of 1.4 V and the input, IN1, is at a fixed voltage equal
to 3 V (a respectable logic high for bipolar TTL). In this case a ground bounce of
greater than 1.6 V will cause the input, IN1, to see a logic low instead of a high and a
glitch will be generated on the inverter output, I1. Supply bounce can also occur on
the VDD net, but this is usually less severe because the pull-up transistors in an output
buffer are usually weaker than the pull-down transistors. The risk of generating a
glitch is also greater at the low logic level for TTL-threshold inputs and TTL-level
outputs because the low-level noise margins are smaller than the high-level noise
margins in TTL.
Sixteen SSOs, with each output driving 150 pF on a bus, can generate a ground
bounce of 1.5 V or more. We cannot simulate this problem easily with FPGAs
because we are not normally given the characteristics of the output devices. As a rule
of thumb we wish to keep ground bounce below 1 V. To help do this we can limit the
maximum number of SSOs, and we can limit the number of I/O buffers that share
GND and VDD pads.
To further reduce the problem, FPGAs now provide options to limit the current
flowing in the output buffers, reducing the slew rate and slowing them down. Some
FPGAs also have quiet I/O circuits that sense when the input to an output buffer
changes. The quiet I/O then starts to change the output using small transistors; shortly
afterwards the large output transistors drop-in. As the output approaches its final
value, the large transistors kick-out, reducing the supply bounce.
6.2.2 Transmission Lines
Most of the problems with driving large capacitive loads at high speed occur on a bus,
and in this case we may have to consider the bus as a transmission line. Figure 6.9 (a)
shows how a transmission line appears to a driver, D1, and receiver, R1, as a constant
impedance, the characteristic impedance of the line, Z 0 . For a typical PCB trace, Z 0
is between 50 W and 100 W .
FIGURE 6.9 Transmission lines. (a) A printed-circuit board (PCB) trace is a
transmission (TX) line. (b) A driver launches an incident wave, which is reflected at
the end of the line. (c) A connection starts to look like a transmission line when the
signal rise time is about equal to twice the line delay (2 t f ).
The voltages on a transmission line are determined by the value of the driver source
resistance, R 0 , and the way that we terminate the end of the transmission line. In
Figure 6.9 (a) the termination is just the capacitance of the receiver, C in . As the
driver switches between 5 V and 0 V, it launches a voltage wave down the line, as
shown in Figure 6.9 (b). The wave will be Z 0 / ( R 0 + Z 0 ) times 5 V in magnitude,
so that if R 0 is equal to Z 0 , the wave will be 2.5 V.
Notice that it does not matter what is at the far end of the line. The bus driver sees
only Z 0 and not C in . Imagine the transmission line as a tunnel; all the bus driver can
see at the entrance is a little way into the tunnelit could be 500 m or 5 km long. To
find out, we have to go with the wave to the end, turn around, come back, and tell the
bus driver. The final result will be the same whether the transmission line is there or
not, but with a transmission line it takes a little longer for the voltages and currents to
settle down. This is rather like the difference between having a conversation by
telephone or by post.
The propagation delay (or time of flight), t f , for a typical PCB trace is approximately
1 ns for every 15 cm of trace (the signal velocity is about one-half the speed of light).
A voltage wave launched on a transmission line takes a time t f to get to the end of the
line, where it finds the load capacitance, C in . Since no current can flow at this point,
there must be a reflection that exactly cancels the incident wave so that the voltage at
the input to the receiver, at V 2 , becomes exactly zero at time t f . The reflected wave
travels back down the line and finally causes the voltage at the output of the driver, at
V 1 , to be exactly zero at time 2 t f . In practice the nonidealities of the driver and the
line cause the waves to have finite rise times. We start to see transmission line
behavior if the rise time of the driver is less than 2 t f , as shown in Figure 6.9 (c).
There are several ways to terminate a transmission line. Figure 6.10 illustrates the
following methods:
● Open-circuit or capacitive termination. The bus termination is the input
capacitance of the receivers (usually less than 20 pF). The PCI bus uses this
method.
● Parallel resistive termination. This requires substantial DC current (5 V / 100 W
= 50 mA for a 100 W line). It is used by bipolar logic, for example
emitter-coupled logic (ECL), where we typically do not care how much power
we use.
● Thévenin termination. Connecting 300 W in parallel with 150 W across a 5 V
supply is equivalent to a 100 W termination connected to a 1.6 V source. This
reduces the DC current drain on the drivers but adds a resistance directly across
the supply.
● Series termination at the source. Adding a resistor in series with the driver so
that the sum of the driver source resistance (which is usually 50 W or even less)
and the termination resistor matches the line impedance (usually around 100 W
). The disadvantage is that it generates reflections that may be close to the
switching threshold.
● Parallel termination with a voltage bias. This is awkward because it requires a
●
third supply and is normally used only for a specialized high-speed bus.
Parallel termination with a series capacitance. This removes the requirement for
DC current but introduces other problems.
FIGURE 6.10 Transmission line termination. (a) Open-circuit or capacitive
termination. (b) Parallel resistive termination. (c) Thévenin termination.
(d) Series termination at the source. (e) Parallel termination using a voltage
bias. (f) Parallel termination with a series capacitor.
Until recently most bus protocols required strong bipolar or BiCMOS output buffers
capable of driving all the way between logic levels. The PCI standard uses weaker
CMOS drivers that rely on reflection from the end of the bus to allow the intermediate
receivers to see the full logic value. Many FPGA vendors now offer complete PCI
functions that the ASIC designer can drop in to an FPGA [PCI, 1995].
An alternative to using a transmission line that operates across the full swing of the
supply voltage is to use current-mode signaling or differential signals with
low-voltage swings. These and other techniques are used in specialized bus structures
and in high-speed DRAM. Examples are Rambus, and Gunning transistor logic ( GTL
). These are analog rather than digital circuits, but ASIC methods apply if the interface
circuits are available as cells, hiding some of the complexity from the designer. For
example, Rambus offers a Rambus access cell ( RAC ) for standard-cell design (but
not yet for an FPGA). Directions to more information on these topics are in the
bibliography at the end of this chapter.
1. 1994 data book, p. 2-159.
2. Application Note XAPP 024.000, Additional XC3000 Data, 1994 data book
p. 8-15.
6.3 DC Input
Suppose we have a pushbutton switch connected to the input of an FPGA as shown in
Figure 6.11 (a). Most FPGA input pads are directly connected to a buffer. We need to
ensure that the input of this buffer never floats to a voltage between valid logic levels
(which could cause both n -channel and p -channel transistors in the buffer to turn on,
leading to oscillation or excessive power dissipation) and so we use the optional pull-up
resistor (usually about 100 k W ) that is available on many FPGAs (we could also
connect a 1 k W pull-up or pull-down resistor externally).
Contacts may bounce as a switch is operated ( Figure 6.11 b). In the case of a Xilinx
XC4000 the effective pull-up resistance is 550 k W (since the specified pull-up current is
between 0.2 and 2.0 mA) and forms an RC time constant with the parasitic capacitance of
the input pad and the external circuit. This time constant (typically hundreds of
nanoseconds) will normally be much less than the time over which the contacts bounce
(typically many milliseconds). The buffer output may thus be a series of pulses extending
for several milliseconds. It is up to you to deal with this in your logic. For example, you
may want to debounce the waveform in Figure 6.11 (b) using an SR flip-flop.
FIGURE 6.11 A switch input. (a) A
pushbutton switch connected to an
input buffer with a pull-up resistor.
(b) As the switch bounces several
pulses may be generated.
A bouncing switch may create a noisy waveform in the time domain, we may also have
noise in the voltage level of our input signal. The Schmitt-trigger inverter in Figure 6.12
(a) has a lower switching threshold of 2 V and an upper switching threshold of 3 V. The
difference between these thresholds is the hysteresis , equal to 1 V in this case. If we
apply the noisy waveform shown in Figure 6.12 (b) to an inverter with no hysteresis,
there will be a glitch at the output, as shown in Figure 6.12 (c). As long as the noise on
the waveform does not exceed the hysteresis, the Schmitt-trigger inverter will produce
the glitch-free output of Figure 6.12 (d).
Most FPGA input buffers have a small hysteresis (the 200 mV that Xilinx uses is a
typical figure) centered around 1.4 V (for compatibility with TTL), as shown in
Figure 6.12 (e). Notice that the drawing inside the symbol for a Schmitt trigger looks like
the transfer characteristic for a buffer, but is backward for an inverter. Hysteresis in the
input buffer also helps prevent oscillation and noise problems with inputs that have slow
rise times, though most FPGA manufacturers still have a restriction that input signals
must have a rise time faster than several hundred nanoseconds.
FIGURE 6.12 DC input. (a) A Schmitt-trigger inverter. (b) A noisy input signal.
(c) Output from an inverter with no hysteresis. (d) Hysteresis helps prevent glitches.
(e) A typical FPGA input buffer with a hysteresis of 200 mV centered around a threshold
of 1.4 V.
6.3.1 Noise Margins
Figure 6.13 (a) and (b) show the worst-case DC transfer characteristics of a CMOS
inverter. Figure 6.13 (a) shows a situation in which the process and device sizes create
the lowest possible switching threshold. We define the maximum voltage that will be
recognized as a '0' as the point at which the gain ( V out / V in ) of the inverter is 1. This
point is V ILmax = 1V in the example shown in Figure 6.13 (a). This means that any input
voltage that is lower than 1V will definitely be recognized as a '0', even with the most
unfavorable inverter characteristics. At the other worst-case extreme we define the
minimum voltage that will be recognized as a '1' as V IHmin = 3.5V (for the example in
Figure 6.13 b).
FIGURE 6.13 Noise margins. (a) Transfer characteristics of a CMOS inverter with the
lowest switching threshold. (b) The highest switching threshold. (c) A graphical
representation of CMOS logic thresholds. (d) Logic thresholds at the inputs and outputs
of a logic gate or an ASIC. (e) The switching thresholds viewed as a plug and socket.
(f) CMOS plugs fit CMOS sockets and the clearances are the noise margins.
Figure 6.13 (c) depicts the following relationships between the various voltage levels at
the inputs and outputs of a logic gate:
● A logic '1' output must be between V OHmin and V DD .
●
A logic '0' output must be between V SS and V OLmax .
●
A logic '1' input must be above the high-level input voltage , V IHmin .
●
A logic '0' input must be below the low-level input voltage , V ILmax .
●
Clamp diodes prevent an input exceeding V DD or going lower than V SS .
The voltages, V OHmin , V OLmax , V IHmin , and V ILmax , are the logic thresholds for a
technology. A logic signal outside the areas bounded by these logic thresholds is badan
unrecognizable logic level in an electronic no-mans land. Figure 6.13 (d) shows typical
logic thresholds for a CMOS-compatible FPGA. The V IHmin and V ILmax logic
thresholds come from measurements in Figure 6.13 (a) and (b) and V OHmin and V OLmax
come from the measurements shown in Figure 6.2 (c).
Figure 6.13 (d) illustrates how logic thresholds form a plug and socket for any gate,
group of gates, or even a chip. If a plug fits a socket, we can connect the two components
together and they will have compatible logic levels. For example, Figure 6.13 (e) shows
that we can connect two CMOS gates or chips together.
FIGURE 6.14 TTL and CMOS logic thresholds. (a) TTL logic thresholds. (b) Typical
CMOS logic thresholds. (c) A TTL plug will not fit in a CMOS socket. (d) Raising V
OHmin solves the problem.
Figure 6.13 (f) shows that we can even add some noise that shifts the input levels and the
plug will still fit into the socket. In fact, we can shift the plug down by exactly V OHmin
V IHmin (4.5 3.5 = 1 V) and still maintain a valid '1'. We can shift the plug up by V ILmax
V OLmax (1.0 0.5 = 0.5 V) and still maintain a valid '0'. These clearances between plug
and socket are the noise margins :
V NMH = V OHmin V
IHmin
and V NML = V ILmax V
OLmax
. (6.1)
For two logic systems to be compatible, the plug must fit the socket. This requires both
the high-level noise margin (V NMH ) and the low-level noise margin (V NML ) to be
positive. We also want both noise margins to be as large as possible to give us maximum
immunity from noise and other problems at an interface.
Figure 6.14 (a) and (b) show the logic thresholds for TTL together with typical CMOS
logic thresholds. Figure 6.14 (c) shows the problem with trying to plug a TTL chip into a
CMOS input levelthe lowest permissible TTL output level, V OHmin = 2.7 V, is too low
to be recognized as a logic '1' by the CMOS input. This is fixed by most FPGA
manufacturers by raising V OHmin to around 3.84.0 V ( Figure 6.14 d). Table 6.1 lists the
logic thresholds for several FPGAs.
6.3.2 Mixed-Voltage Systems
To reduce power consumption and allow CMOS logic to be scaled below 0.5 m m it is
necessary to reduce the power supply voltage below 5 V. The JEDEC 8 [ JEDEC I/O]
series of standards sets the next lower supply voltage as 3.3 ± 0.3 V. Figure 6.15 (a) and
(b) shows that the 3 V CMOS I/O logic-thresholds can be made compatible with 5 V
systems. Some FPGAs can operate on both 3 V and 5 V supplies, typically using one
voltage for internal (or core) logic, V DDint and another for the I/O circuits, V DDI/O (
Figure 6.15 c).
TABLE 6.1 FPGA logic thresholds.
I/O options
Input Output
Input levels
V IH V IL
Output levels (high
Output levels (low
current)
current)
V OH I OH V OL I OL V OH I OH VOL I OL
(min) (max) (min) (max) (max) (max) (min) (max) (max) (max)
XC3000 1 TTL
CMOS
2.0
0.8
3.86 4.0
0.40 4.0
3.85
0.9 3 3.86 4.0
0.40 4.0
2
XC3000L
2.0
0.8
2.40 4.0
0.40 4.0
XC4000 5
XC4000H
TTL
6
2.0
0.8
2.40 4.0
0.40 12.0
2.0
0.8
2.40 4.0
0.50 24.0
4.00 1.0
CMOS CMOS 3.85
0.9 3 7
2
0.50 24.0
XC8100 8 TTL
TTL
R
ACT 2/3
FLEX10k
9
4
0.1
2.0
0.8
3.85
0.9 3 3.86 4.0
0.40 4.0
2.0
0.8
2.4
8.0
0.50 12.0 3.84 4.0
3V/5V 2.0
0.8
2.4
4.0
0.45 12.0
CMOS C
2
3.86 4.0
2.80
0.2
0.1
0.50 24.0
0.33 6.0
There is one problem when we mix 3 V and 5 V supplies that is shown in Figure 6.15 (d).
If we apply a voltage to a chip input that exceeds the power supply of a chip, it is possible
to power a chip inadvertently through the clamp diodes. In the worst case this may cause
a voltage as high as 2.5 V (= 5.5 V 3.0 V) to appear across the clamp diode, which will
cause a very large current (several hundred milliamperes) to flow. One way to prevent
damage is to include a series resistor between the chips, typically around 1 k W . This
solution does not work for all chips in all systems. A difficult problem in ASIC I/O
design is constructing 5 V-tolerant I/O . Most solutions may never surface (there is little
point in patenting a solution to a problem that will go away before the patent is granted).
Similar problems can arise in several other situations:
● when you connect two ASICs with different 5 V supplies;
● when you power down one ASIC in a system but not another, or one ASIC powers
down faster than another;
● on system power-up or system reset.
FIGURE 6.15
Mixed-voltage systems.
(a) TTL levels.
(b) Low-voltage CMOS
levels. (c) A
mixed-voltage ASIC.
(d) A problem when
connecting two chips
with different supply
voltagescaused by the
input clamp diodes.
1. XC2000, XC3000/A have identical thresholds. XC3100/A thresholds are identical to
XC3000 except for ±8 mA sourcesink current. XC5200 thresholds are identical to
XC3100A.
2. Defined as 0.7 V DD , calculated with V DD max = 5.5 V.
3. Defined as 0.2 V DD , calculated with V DD min = 4.5 V.
4. Defined as V DD 0.2 V, calculated with V
DD min
= 3.0 V.
5. XC4000, XC4000A have identical I/O thresholds except XC4000A has 24 mA sink
current.
6. XC4000H/E have identical I/O thresholds except XC4000E has 12 mA sink current.
Options are independent.
7. Defined as VDD 0.5 V, calculated with VDD
min
= 4.5 V.
8. Input and output options are independent.
9. MAX 9000 has identical thresholds to FLEX 10k.
Note: All voltages in volts, all currents in milliamperes.
6.4 AC Input
Suppose we wish to connect an input bus containing sampled data from an
analog-to-digital converter ( A/D ) that is running at a clock frequency of 100 kHz
to an FPGA that is running from a system clock on a bus at 10 MHz (a NuBus).
We are to perform some filtering and calculations on the sampled data before
placing it on the NuBus. We cannot just connect the A/D output bus to our FPGA,
because we have no idea when the A/D data will change. Even though the A/D
data rate (a sample every 10 m s or every 100 NuBus clock cycles) is much lower
than the NuBus clock, if the data happens to arrive just before we are due to place
an output on the NuBus, we have no time to perform any calculations. Instead we
want to register the data at the input to give us a whole NuBus clock cycle (100
ns) to perform the calculations. We know that we should have the A/D data at the
flip-flop input for at least the flip-flop setup time before the NuBus clock edge.
Unfortunately there is no way to guarantee this; the A/D converter clock and the
NuBus clock are completely independent. Thus it is entirely possible that every
now and again the A/D data will change just before the NuBus clock edge.
6.4.1 Metastability
If we change the data input to a flip-flop (or a latch) too close to the clock edge
(called a setup or hold-time violation ), we run into a problem called metastability
, illustrated in Figure 6.16. In this situation the flip-flop cannot decide whether its
output should be a '1' or a '0' for a long time. If the flip-flop makes a decision, at a
time t r after the clock edge, as to whether its output is a '1' or a '0', there is a
small, but finite, probability that the flip-flop will decide the output is a '1' when it
should have been a '0' or vice versa. This situation, called an upset , can happen
when the data is coming from the outside world and the flip-flop cant determine
when it will arrive; this is an asynchronous signal , because it is not synchronized
to the chip clock.
FIGURE 6.16 Metastability.
(a) Data coming from one
system is an asynchronous
input to another. (b) A
flip-flop has a very narrow
decision window bounded
by the setup and hold times.
If the data input changes
inside this decision window,
the output may be
metastableneither '1' or '0'.
Experimentally we find that the probability of upset , p , is
p = T 0 exp t
r
/ t c , (6.2)
(per data event, per clock edge, in one second, with units Hz 1 ·Hz 1 ·s 1 ) where t
r is the time a sampler (flip-flop or latch) has to resolve the sampler output; T 0
and t c are constants of the sampler circuit design. Let us see how serious this
problem is in practice. If t r = 5 ns, t c = 0.1 ns, and T 0 = 0.1 s, Eq. 6.2 gives the
upset probability as
5 ¥ 10
19
= 2 ¥ 10 23 s , (6.3)
p = 0.1 exp
0.1 ¥ 10 9
which is very small, but the data and clock may be running at several MHz,
causing the sampler plenty of opportunities for upset.
The mean time between upsets ( MTBU , similar to MTBFmean time between
failures) is
1
MTBU =
exp t r / t c
= ,
(6.4)
pf clock f data f clock f data
where f clock is the clock frequency and f data is the data frequency.
If t r = 5 ns, t c = 0.1 ns, T 0 = 0.1 s (as in the previous example), f clock = 100
MHz, and f data = 1 MHz, then
exp (5 ¥ 10 9 /0.1 ¥ 10 9)
= 5.2 ¥ 10 8 seconds , (6.5)
MTBU =
(100 ¥ 10 6 )(1 ¥ 10 6 )(0.1)
or about 16 years (10 8 seconds is three years, and a day is 10 5 seconds). An
MTBU of 16 years may seem safe, but suppose we have a 64-bit input bus using
64 flip-flops. If each flip-flop has an MTBU of 16 years, our system-level MTBF
is three months. If we ship 1000 systems we would have an average of 10 systems
failing every day. What can we do?
The parameter t c is the inverse of the gainbandwidth product , GB , of the
sampler at the instant of sampling. It is a constant that is independent of whether
we are sampling a positive or negative data edge. It may be determined by a
small-signal analysis of the sampler at the sampling instant or by measurement. It
cannot be determined by simulating the transient response of the flip-flop to a
metastable event since the gain and bandwidth both normally change as a function
of time. We cannot change t c .
The parameter T 0 (units of time) is a function of the process technology and the
circuit design. It may be different for sampling a positive or negative data edge,
but normally only one value of T 0 is given. Attempts have been made to calculate
T 0 and to relate it to a physical quantity. The best method is by measurement or
simulation of metastable events. We cannot change T 0 .
Given a good flip-flop or latch design, t c and T 0 should be similar for
comparable CMOS processes (so, for example, all 0.5 m m processes should have
approximately the same t c and T 0 ). The only parameter we can change when
using a flip-flop or latch from a cell library is t r , and we should allow as much
resolution time as we can after the output of a latch before the signal is clocked
again. If we use a flip-flop constructed from two latches in series (a masterslave
design), then we are sampling the data twice. The resolution time for the first
sample t r is fixed, it is half the clock cycle (if the clock is high and low for equal
timeswe say the clock has a 50 percent duty cycle , or equal markspace ratio ).
Using such a flip-flop we need to allow as much time as we can before we clock
the second sample by connecting two flip-flops in series, without any
combinational logic between them, if possible. If you are really in trouble, the
next step is to divide the clock so you can extend the resolution time even further.
TABLE 6.2 Metastability parameters for FPGA flip-flops. These figures are not
guaranteed by the vendors.
T0/s tc/s
FPGA
Actel ACT 1
1.0E09 2.17E10
Xilinx XC3020-70
1.5E10 2.71E10
QuickLogic QL12x16-0
2.94E11 2.91E10
QuickLogic QL12x16-1
8.38E11 2.09E10
QuickLogic QL12x16-2
1.23E10 1.85E10
Xilinx XC8100
2.15E-12 4.65E10
Xilinx XC8100 synchronizer
1.59E-17 2.07E10
Altera MAX 7000
2.98E17 2.00E10
Altera FLEX 8000
1.01E13 7.89E11
Sources: Actel April 1992 data book, p. 5-1, gives C1 = T 0 = 10 9 Hz 1 , C2 = 1/
t c = 4.6052 ns 1 , or t c = 2.17E10 s and T 0 = 1.0E09 s. Xilinx gives K1 = T 0 =
1.5E10 s and K2 = 1/ t c = 3.69E9 s1, t c = 2.71E10 s, for the XC3020-70
(p. 8-20 of 1994 data book). QuickLogic pASIC 1 QL12X16: t c = 0.2 ns to 0.3
ns, T 0 = 0.3E10 s to 1.2E10 s (1994 data book, p. 5-25, Fig. 2). Xilinx XC8100
data, t c = 4.65E10 s and T 0 = 2.15E12 s, is from October 1995 (v. 1.0) data
sheet, Fig.17 (the XC8100 was discontinued in August 1996). Altera 1995 data
book p. 437, Table 1.
Table 6.2 shows flip-flop metastability parameters and Figure 6.17 graphs the
metastability data for f clock = 10 MHz and f data = 1 MHz. From this graph we
can see the enormous variation in MTBF caused by small variations in t c . For
example, in the QuickLogic pASIC 1 series the range of T 0 from 0.3 to 1.2 ¥ 10
10 s is 4:1, but it is the range of t = 0.2 0.3 ns (a variation of only 1:1.5) that is
c
responsible for the enormous variation in MTBF (nearly four orders of magnitude
at t r = 5 ns). The variation in t c is caused by the variation in GB between the
QuickLogic speed grades. Variation in the other vendors parts will be similar, but
most vendors do not show this information. To be safe, build a large safety
margin for MTBF into any designit is not unreasonable to use a margin of four
orders of magnitude.
FIGURE 6.17 Mean time between failures (MTBF) as a function of resolution
time. The data is from FPGA vendors data books for a single flip-flop with clock
frequency of 10 MHz and a data input frequency of 1 MHz (see Table 6.2 ).
Some cell libraries include a synchronizer , built from two flip-flops in cascade,
that greatly reduces the effective values of t c and T 0 over a single flip-flop. The
penalty is an extra clock cycle of latency.
To compare discrete TTL parts with ASIC flip-flops, the 74AS4374 TTL
metastable-hardened dual flip-flops , from TI, have t c = 0.42 ns and T 0 = 4 ns.
The parameter T 0 ranges from about 10 s for the 74LS74 (a regular flip-flop) to 4
ns for the 74AS4374 (over nine orders of magnitude different); t c only varies
from 0.42 ns (74AS374) to 1.3 ns (74LS74), but this small variation in t c is just
as important.
6.5 Clock Input
When we bring the clock signal onto a chip, we may need to adjust the logic level
(clock signals are often driven by TTL drivers with a high current output
capability) and then we need to distribute the clock signal around the chip as it is
needed. FPGAs normally provide special clock buffers and clock networks. We
need to minimize the clock delay (or latency), but we also need to minimize the
clock skew.
6.5.1 Registered Inputs
Some FPGAs provide a flip-flop or latch that you can use as part of the I/O
circuit (registered I/O). For other FPGAs you have to use a flip-flop or latch
using the basic logic cell in the core. In either case the important parameter is the
input setup time. We can measure the setup with respect to the clock signal at the
flip-flop or the clock signal at the clock input pad. The difference between these
two parameters is the clock delay.
FIGURE 6.18 Clock input. (a) Timing model with values for a Xilinx
XC4005-6. (b) A simplified view of clock distribution. (c) Timing diagram.
Xilinx eliminates the variable internal delay t PG , by specifying a pin-to-pin
setup time, t PSUFmin = 2 ns.
Figure 6.18 shows part of the I/O timing model for a Xilinx XC40005-6. 1
●
t PICK is the fixed setup time for a flip-flop relative to the flip-flop clock.
●
t skew is the variable clock skew , the signed delay between two clock
edges.
t PG is the variable clock delay or latency .
●
To calculate the flip-flop setup time ( t PSUFmin ) relative to the clock pad (which
is the parameter system designers need to know), we subtract the clock delay, so
that
t PSUF = t PICK t
PG
. (6.6)
The problem is that we cannot easily calculate t PG , since it depends on the clock
distribution scheme and where the flip-flop is on the chip. Instead Xilinx
specifies t PSUFmin directly, measured from the data pad to the clock pad; this
time is called a pin-to-pin timing parameter . Notice t PSUF min = 2 ns ` t PICK t
PG max = 1 ns.
Figure 6.19 shows that the hold time for a XC4005-6 flip-flop ( t CKI ) with
respect to the flip-flop clock is zero. However, the pin-to-pin hold time including
the clock delay is t PHF = 5.5 ns. We can remove this inconvenient hold-time
restriction by delaying the input signal. Including a programmable delay allows
Xilinx to guarantee the pin-to-pin hold time ( t PH ) as zero. The penalty is an
increase in the pin-to-pin setup time ( t PSU ) to 21 ns (from 2 ns) for the
XC4005-6, for example.
FIGURE 6.19 Programmable input delay. (a) Pin-to-pin timing model with
values from an XC4005-6. (b) Timing diagrams with and without programmable
delay.
We also have to account for clock delay when we register an output. Figure 6.20
shows the timing model diagram for the clock-to-output delay.
FIGURE 6.20
Registered output.
(a) Timing model with
values for an XC4005-6
programmed with the
fast slew-rate option.
(b) Timing diagram.
1. The Xilinx XC4005-6 timing parameters are from the 1994 data book p. 2-50
to p. 2-53.
6.6 Power Input
The last item that we need to bring onto an FPGA is the power. We may need
multiple VDD and GND power pads to reduce supply bounce or separate VDD
pads for mixed-voltage supplies. We may also need to provide power for on-chip
programming (in the case of antifuse or EPROM programming technology). The
package type and number of pins will determine the number of power pins,
which, in turn, affects the number of SSOs you can have in a design.
6.6.1 Power Dissipation
As a general rule a plastic package can dissipate about 1 W, and more expensive
ceramic packages can dissipate up to about 2 W. Table 6.3 shows the thermal
characteristics of common packages. In a high-speed (high-power) design the
ASIC power consumption may dictate your choice of packages. Actel provides a
formula for calculating typical dynamic chip power consumption of their FPGAs.
The formula for the ACT 2 and ACT 3 FPGAs are complex; therefore we shall
use the simpler formula for the ACT 1 FPGAs as an example 1 :
TABLE 6.3 Thermal characteristics of ASIC packages.
q JA /°CW 1 q JA /°CW 1
Package 2 Pin count Max. power P max /W
(still air) 3 , 4 (still air) 5
CPGA
84
33
3238
CPGA
100
35
CPGA
132
30
CPGA
175
25
16
CPGA
207
22
CPGA
257
15
CQFP
84
40
CQFP
172
25
PQFP
100
1.0
55
5675
PQFP
160
1.75
33
3033
PQFP
208
2.0
33
27-32
VQFP
80
68
PLCC
44
52
44
PLCC
68
45
2835
PLCC
PPGA
84
132
1.5
44
3334
Total chip power = 0.2 (N ¥ F1) + 0.085 (M ¥ F2) + 0.8 ( P ¥ F3) mW (6.7)
where
F1 = average logic module switching rate in MHz
F2 = average clock pin switching rate in MHz
F3 = average I/O switching rate in MHz
M = number of logic modules connected to the clock pin
N = number of logic modules used on the chip
P = number of I/O pairs used (input + output), with 50 pF load
As an example of a power-dissipation calculation, consider an Actel 1020B-2
with a 20 MHz clock. We shall initially assume 100 percent utilization of the 547
Logic Modules and assume that each switches at an average speed of 5 MHz. We
shall also initially assume that we use all of the 69 I/O Modules and that each
switches at an average speed of 5 MHz. Using Eq. 6.7 , the Logic Modules
dissipate
P LM = (0.2)(547)(5) = 547 mW , (6.8)
and the I/O Module dissipation is
P IO = (0.8)(69)(5) = 276 mW . (6.9)
If we assume the clock buffer drives 20 percent of the Logic Modules, then the
additional power dissipation due to the clock buffer is
P CLK = (0.085)(547)(0.2)(5) = 46.495 mW . (6.10)
The total power dissipation is thus
P D = (547 + 276 + 46.5) = 869.5 mW , (6.11)
or about 900 mW (with an accuracy of certainly no better than ± 100 mW).
Suppose we intend to use a very thin quad flatpack ( VQFP ) with no cooling
(because we are trying to save area and board height). From Table 6.3 the thermal
resistance, q JA , is approximately 68 °CW 1 for an 80-pin VQFP. Thus the
maximum junction temperature under industrial worst-case conditions (T A = 85
°C) will be
T J = (85 + (0.87)(68)) = 144.16 °C , (6.12)
(with an accuracy of no better than 10 °C). Actel specifies the maximum junction
temperature for its devices as T Jmax = 150 °C (T Jmax for Altera is also 150 °C,
for Xilinx T Jmax = 125°C). Our calculated value is much too close to the rated
maximum for comfort; therefore we need to go back and check our assumptions
for power dissipation. At or near 100 percent module utilization is not
unreasonable for an Actel device, but more questionable is that all nodes and I/Os
switch at 5 MHz.
Our real mistake is trying to use a VQFP package with a high q JA for a
high-speed design. Suppose we use an 84-pin PLCC package instead. From
Table 6.3 the thermal resistance, q JA , for this alternative package is
approximately 44 °CW 1 . Now the worst-case junction temperature will be a
more reasonable
T J = (85 + (0.87)(44)) = 123.28 °C , (6.13)
It is possible to estimate the power dissipation of the Actel architecture because
the routing is regular and the interconnect capacitance is well controlled (it has to
be since we must minimize the number of series antifuses we use). For most
other architectures it is much more difficult to estimate power dissipation. The
exception, as we saw in Section 5.4 Altera MAX, are the programmable ASICs
based on programmable logic arrays with passive pull-ups where a substantial
part of the power dissipation is static.
6.6.2 Power-On Reset
Each FPGA has its own power-on reset sequence. For example, a Xilinx FPGA
configures all flip-flops (in either the CLBs or IOBs) as either SET or RESET.
After chip programming is complete, the global SET/RESET signal forces all
flip-flops on the chip to a known state. This is important since it may determine
the initial state of a state machine, for example.
1. 1994 data book, p.1-9
2. CPGA = ceramic pin-grid array; CQFP = ceramic quad flatpack; PQFP =
plastic quad flatpack; VQFP = very thin quad flatpack; PLCC = plastic leaded
chip carrier; PPGA = plastic pin-grid array.
3. q JA varies with die size.
4. Data from Actel 1994 data book p. 1-9, p. 1-45, and p. 1-94.
5. Data from Xilinx 1994 data book p. 4-26 and p. 4-27.
6.7 Xilinx I/O Block
The Xilinx I/O cell is the input/output block ( IOB ) . Figure 6.21 shows the Xilinx
XC4000 IOB, which is similar to the IOB in the XC2000, XC3000, and XC5200 but
performs a superset of the options in these other Xilinx FPGAs.
FIGURE 6.21 The Xilinx XC4000 family IOB (input/output block). ( Source:
Xilinx.)
The outputs contain features that allow you to do the following:
● Switch between a totem-pole and a complementary output (XC4000H).
● Include a passive pull-up or pull-down (both n -channel devices) with a typical
resistance of about 50 k W .
● Invert the three-state control (output enable OE or three-state, TS).
● Include a flip-flop, or latch, or a direct connection in the output path.
● Control the slew rate of the output.
The features on the inputs allow you to do the following:
● Configure the input buffer with TTL or CMOS thresholds.
● Include a flip-flop, or latch, or a direct connection in the input path.
● Switch in a delay to eliminate an input hold time.
FIGURE 6.22 The Xilinx LCA (Logic Cell Array) timing model. The paths
show different uses of CLBs (Configurable Logic Blocks) and IOBs
(Input/Output Blocks). The parameters shown are for an XC5210-6. (Source:
Xilinx.)
Figure 6.22 shows the timing model for the XC5200 family. 1 It is similar to the
timing model for all the other Xilinx LCA FPGAs with one exceptionthe XC5200
does not have registers in the I/O cell; you go directly to the core CLBs to include a
flip-flop or latch on an input or output.
6.7.1 Boundary Scan
Testing PCBs can be done using a bed-of-nails tester. This approach becomes very
difficult with closer IC pin spacing and more sophisticated assembly methods using
surface-mount technology and multilayer boards. The IEEE implemented
boundary-scan standard 1149.1 to simplify the problem of testing at the board level.
The Joint Test Action Group (JTAG) developed the standard; thus the terms JTAG
boundary scan or just JTAG are commonly used.
Many FPGAs contain a standard boundary-scan test logic structure with a four-pin
interface. By using these four signals, you can program the chip using ISP, as well as
serially load commands and data into the chips to control the outputs and check the
inputs. This is a great improvement over bed-of-nails testing. We shall cover
boundary scan in detail in Section 14.6, Scan Test.
1. October 1995 (v. 3.0) data sheet.
6.8 Other I/O Cells
The Altera MAX 5000 and 7000 use the I/O Control Block ( IOC ) shown in
Figure 6.23 . In the MAX 5000, all inputs pass through the chipwide
interconnect. The MAX 7000E has special fast inputs that are connected directly
to macrocell registers in order to reduce the setup time for registered inputs.
FIGURE 6.23 A simplified
block diagram of the Altera
I/O Control Block (IOC)
used in the MAX 5000 and
MAX 7000 series. The I/O
pin feedback allows the I/O
pad to be isolated from the
macrocell. It is thus
possible to use a LAB
without using up an I/O pad
(as you often have to do
using a PLD such as a
22V10). The PIA is the
chipwide interconnect.
The FLEX 8000 and 10k use the I/O Element ( IOE ) shown in Figure 6.24 (the
MAX 9000 IOC is similar). The interface to the IOE is directly to the chipwide
interconnect rather than the core logic. There is a separate bus, the Peripheral
Control Bus , for the IOE control signals: clock, preset, clear, and output enable.
FIGURE 6.24 A simplified
block diagram of the Altera I/O
Element (IOE), used in the
FLEX 8000 and 10k series. The
MAX 9000 IOC (I/O Cell) is
similar. The FastTrack
Interconnect bus is the chipwide
interconnect. The PCB is used
for control signals common to
each IOE.
The AMD MACH 5 family has some I/O features not currently found on other
programmable ASICs. The MACH 5 family has 3.3 V and 5 V versions that are
both suitable for mixed-voltage designs. The 3 V versions accept 5 V inputs, and
the outputs of the 3 V versions do not drive above 3.3 V. You can apply a voltage
up to 5.5 V to device inputs before you connect VDD (this is known as hot
insertion or hot switching, allowing you to swap cards with power still applied
without causing latch-up). During power-up and power-down, all I/Os are
three-state, and there is no I/O current during power-down, allowing power-down
while connected to an active bus. All MACH 5 devices in the same package have
the same pin configuration, so you can increase or reduce the size of device after
completing the board layout.
6.9 Summary
Among the options available in I/O cells are: different drive strengths,
TTL-compatibility, registered or direct inputs, registered or direct outputs,
pull-up resistors, over-voltage protection, slew-rate control, and boundary-scan.
Table 6.4 shows a list of features. Interfacing an ASIC with a system starts at the
outputs where you check the voltage levels first, then the current levels. Table 6.5
is a look-up table for Tables 6.6 and 6.7 , which show the I/O resources present in
each type of programmable ASIC (using the abbreviations of Table 6.4 ).
TABLE 6.4 I/O options for programmable ASICs.
Function
Code 1 I/O Option
IT/C TTL/CMOS input Programmable input buffer threshold
OT/C TTL/CMOS output Complementary or totem-pole output
Maximum current sink ability (e.g., 12SNK is I 0 =
nSNK Sink capability
12 mA sink)
Maximum current source ability (e.g., 12SRC is I 0
nSRC Source capability
= 12 mA source)
5/3
5V/3V
Separate I/O and core voltage supplies
OD
Open drain/collector Programmable open-drain at the output buffer
TS
Three-state
Output buffer with three-state control
Fast or slew-rate limited output buffer to reduce
SR
Slew-rate control
ground bounce
Programmable pull-down device or resistor at the
PD
Pull-down
I/O pad
Programmable pull-up device or resistor at the I/O
PU
Pull-up
pad
Driver control can be positive (three-state) or
EP
Enable polarity
negative (enable).
RI
Registered input
Inputs may be registered in I/O cell.
RO
Registered output Outputs may be registered in I/O cell.
Both inputs and outputs may be registered in I/O
RIO Registered I/O
cell.
ID
Input delay
Input delay to eliminate input hold time
JTAG JTAG
Boundary-scan test
SCH Schmitt trigger
Schmitt trigger or input hysteresis
HOT Hot insertion
PCI
PCI compliant
Inputs protected from hot insertion
Output buffer characteristics comply with PCI
specifications.
Important points that we covered in this chapter are the following:
● Outputs can typically source or sink 510 mA continuously into a DC load,
and 50200 mA transiently into an AC load.
● Input buffers can be CMOS (threshold at 0.5 V DD ) or TTL (1.4 V).
●
●
●
●
●
●
Input buffers normally have a small hysteresis (100200 mV).
CMOS inputs must never be left floating.
Clamp diodes to GND and VDD are present on every pin.
Inputs and outputs can be registered or direct.
I/O registers can be in the I/O cell or in the core.
Metastability is a problem when working with asynchronous inputs.
1. These codes are used in Tables 6.6 and 6.7 .
6.10 Problems
* = Difficult, ** = Very difficult, *** = Extremely difficult
6.1 (I/O resources, 60 min.) Obtain the specifications for the latest version of your
choice of FPGA vendor from a data book or online data sheet and complete a
table in the same format as Tables 6.6 and 6.7 .
TABLE 6.5 I/O Cell Tables.
Programmable ASIC family Table
Actel (ACT 1)
Programmable ASIC family Table
Actel (ACT 3)
Xilinx (XC3000)
Xilinx LCA (XC5200)
Actel (ACT 2)
Altera FLEX (8000/10k)
Altera MAX (EPM 5k)
Table 6.6
AMD MACH 5
Table 6.7
Xilinx EPLD (XC7200/7300)
Actel 3200DX
QuickLogic (pASIC 1)
Altera MAX (EPM 9000)
Crosspoint (CP20K)
Xilinx (XC8100)
Altera MAX (EPM 7000)
AT&T ORCA (2C)
Atmel (AT6000)
Xilinx (XC4000)
6.2 (I/O timing, 60 min.) On-chip delays are only half the battle in a typical
design. Using data book parameters for an FPGA that you choose, estimate
(worst-case commercial) how long it takes to bring a signal on-chip; through an
input register (a flip-flop); through a combinational function (assume an inverter);
and back off chip again through another (flip-flop) register. Give your answer in
three parts:
TABLE 6.6 Programmable ASIC I/O logic resources.
Actel (ACT 1)
Xilinx (XC3000)
IOB (Input/Output
I/O cell name I/O module
Block)
TS, RIO, IT/C, PU,
I/O cell
TS, 10SRC,
4SRC, 4SNK, 8SRC
10SNK
functions 1
(3100), 8SNK (3100)
Actel (ACT 2)
I/O module
TS, (RIO) 2 , 10SRC,
10SNK
Max. I/O:
Number of I/O
57 (1010)
cells
69 (1020)
Max. I/O:
Max. I/O:
64 (3020)
83 (1225)
144 (3090)
140 (1280)
Altera MAX 5000 Xilinx EPLD
I/O cell name
I/O control block I/O block
I/O cell
functions
TS, 4SRC, 8SNK
Number of I/O 8 (5016)
cells
64 (5192)
Crosspoint
(CP20K)
I/O cell name
I/O cell
I/O cell
functions
TS, SR, IC/T ,
JTAG, SCH
Number of I/O 91 (20220)
cells
270 (22000)
QuickLogic
(pASIC 1)
Bidirectional
input/output cell &
dedicated input cell
(TS), (RI) 3 , 5/3,
TS
4SRC, 12SNK
38 (7336)156 (73144)
32 (QL6X8) 4
36 (7236)
104 (QL16X24)
72 (7272)
Altera MAX 7000
Atmel (AT6000)
IOC (I/O Control
Block)
TS, SR, 5/3, PCI,
4SRC, 12SNK
36 (7032)
Entrance and exit
cells
TS, SR, PU, OD,
IT/C, 16SRC, 16SNK
96 (6002)
164 (7256)
160 (6010)
TABLE 6.7 Programmable ASIC I/O logic resources (contd.).
Altera FLEX
Actel (ACT 3) Xilinx LCA (XC5200)
(8000/10k)
I/O cell name I/O Module
IOB (I/O Block)
IOE (I/O Element)
TS, SR, RI or RO,
I/O cell
TS, SR, (RIO) 6 ,
TS, PU, PD, JTAG
JTAG, PCI(8k),
functions 5
8SRC, 12SNK
4SRC, 12SNK
78 (8282)208
84 (5202)
80 (1415)
(81500)
Number of I/O
244 (5215)
228 (14100)
150 (10K10)
cells
406 (10K100)
AMD MACH 5 Actel 3200DX
I/O cell name
I/O Cell
I/O Module
Altera MAX
(EPM 9000)
IOE (I/O Element)
I/O cell
functions
TS, 3.2SRC,
16SNK, PCI
Number of I/O 120 (M5-128)
cells
256 (M5-512)
Xilinx
(XC8100) 7
126 (A3265DX)
TS, SR, 5/3, PCI,
JTAG, 4SRC, 8SNK
168 (9320)
292 (A32400DX)
216 (9560)
AT&T ORCA 2C
Xilinx (XC4000)
Same as ACT 2
PIC (Programmable
input/output cells)
TS, PU, IT/C
TS, IT/C, ID, PU, PD,
(global), JTAG, OD, JTAG, PCI, (6SRC
I/O cell
PCI, 4SRC,
and 12SNK) or (3SRC
functions
8
and 6SNK), SCH
4/24SNK
160 (2C04)
Number of I/O 32 (8100)
cells
208 (8109)
480 (2C40)
I/O cell name
●
●
●
I/O Cell
IOB (I/O Block)
TS, RIO, JTAG, ID,
IT/C, OT/C, PU,
PD, 4SRC, 12SNK,
24SNK (4000A/H)
80 (4003)
256 (4025)
a. The delay from a CMOS-level pad input (trip-point of 0.5) to the D input
of the input register plus the flip-flop setup time.
b. The delay (measured from the clock, so include the clock-to-Q delay)
through the inverter to the output register plus the setup time.
c. The delay from the output register (measured from the clock edge) to the
output pad (trip point of 0.5) with a 50 pF load.
In each case give your answers: (i) Using data book symbols (specify which
symbols and where in the data books you found them); and (ii) as calculated
values, in nanoseconds, using a speed grade that you specify. State and explain
very clearly any assumptions that you need to make about the clock to determine
the setup times.
6.3 (Clock timing, 30 min.) When we calculate FPGA timing we need to include
the time it takes to bring the clock onto the chip. For an FPGA you choose,
estimate (worst-case commercial) the delay from the clock pad (0.5 trip-point) to
the clock pin of an internal flip-flop
● a. in terms of data book symbols (specify which and where you found them
t AB on p. 2-32 of the ABC 1994 data book, for example), and
●
b. as calculated values in nanoseconds.
6.4 (**Bipolar drivers, 60 min.) The circuit in Figure 6.3 uses npn transistors.
●
●
●
●
●
a. Design a similar circuit that uses pnp transistors.
b. The pnp circuit may work better, why?
c. Design an even better circuit that uses npn and pnp transistors.
d. Explain why your circuit is even better.
e. Draw a diagram for a controller using op-amps instead of bipolar
transistors.
6.5 (Xilinx output buffers, 15 min.) For the Xilinx XC2000 and XC3000 series 9 :
I OLpeak = 120 mA and I OHpeak = 80 mA; for the XC4000 family: I OLpeak = 160
mA and I OHpeak = 130 mA; and for the XC7300 series: I OLpeak = 100 mA and I
OHpeak = 65 mA. For a typical 0.81.0 m m process:
p -channel (20/1): I DS = 3.05.0 mA with V DS = 5 V, V GS = 5 V
n -channel (20/1): I DS = 7.510.0 mA with V DS = 5 V, V GS = 5 V
● a. Calculate the effective sizes of the transistors in the Xilinx output buffer.
● b. Why might these only be effective sizes?
● c. The Xilinx data book gives values for source current and output high
impedance shown in Table 6.8 . Graph the buffer characteristics when
sourcing current.
● d. Explain which parts in Table 6.8 use complementary output buffers and
which use totem-pole outputs and explain how you can tell.
● e. Can you explain how Xilinx arrived at the figures for impedance?
● f. Comment on the method that Xilinx used.
● g. Suggest and calculate a better measure of impedance.
TABLE 6.8 Xilinx output buffer characteristics.
V O (output voltage) 10 / V
Part
IO (2018)
IO (3020)
IO (4005)
IO (73108)
4
30
35
0
0
3
52
60
12
10
2
60
75
50
26
Impedance/ W
30
30
25
40
6.6 (Xilinx logic levels, 10 min.) Most manufacturers measure V OLmax with V
DD set to its minimum value, Xilinx measures V OLmax at V DDmax . For example,
for the Xilinx XC4000 11 : V OLmax = 0.4 V at I OLmax = 12 mA and V DDmax . A
footnote also explains that V OLmax is measured with 50 % of the outputs
simultaneously sinking 12 mA.
● a. Can you explain why Xilinx measures V OLmax this way?
●
b. What information do you need to know to estimate V OLmax if all the
other outputs were not sourcing or sinking any current.
6.7 (Output levels, 10 min.) In Figure 6.7 (bd) the PAD signal is labeled with
different levels: In Figure 6.7 (b) the PAD high and low levels are V OHmin and V
OLmax respectively, in Figure 6.7 (c) they are V DD and V OLmax , and in
Figure 6.7 (c) they are V OHmin and V SS .
●
●
a. Explain why this is.
b. In no more than 20 words explain the difference between V DD and V
OHmin as well as the difference between V OLmax and V SS .
6.8 (TTL and CMOS outputs, 10 min.) The ACT 2 figures for t DLH and t DHL in
Figure 6.7 are for the CMOS levels. For TTL levels the figures are (with the
CMOS figures in parentheses): t DLH = 10.6 ns (13.5 ns), and t DHL = 13.4 ns
(11.2 ns). The output buffer is the same in both cases, but the delays are measured
using different levels. Explain the differences in these delays quantitatively.
6.9 (Bus-keeper contention, 30 min.) Figure 6.25 shows a three-state bus, similar
to Figure 6.5 , that has a bus keeper on CHIP1 and a pull-up resistor that is part of
a Xilinx IOB on CHIP2we have a type of bus-keeper contention. For the XC3000
the pull-up current is 0.020.17 mA and thus RL1 is between 5 and 50 k W (1994
data book, p. 2-155).
● a. Explain what might happen when both the bus drivers turn off.
● b. Have you considered all possibilities?
● c. Is bus-keeper contention a problem?
● d. In the PCI specification control signals are required to be sustained
three-state. A driver must deassert a control signal to the inactive state
(high for the PCI control signals) for at least one clock cycle before
three-stating the line. This means that a driver has to put the signal back
where it found it. Does this affect your answers?
● e. Suggest a fix that stops you having to worry about any potential
problems.
FIGURE 6.25
A bus keeper,
BK1, and
pull-up
resistor, RL1,
on the same
bus.
6.10 (Short-circuit, 10 min.) What happens if you short-circuit the output of a
complementary output buffer to (a) GND and (b) VDD? (c) What difference
does it make if the output buffer is complementary or a totem-pole?
6.11 (Transmission line bias, 10 min.)
● a. Why do we adjust the resistors in Figure 6.10 (c) so that the Thévenin
equivalent voltage source is 1.6 V?
● b. What current does a driver have to sink if we want V OLmax = 0.4 V?
●
c. What current does a driver have to source if we want V OHmin = 2.4 V?
6.12 (Ground resistance, 10 min.) Calculate the resistance of an aluminum GND
net that is 0.5 mm long and 10 m m wide.
6.13 (*Temperature) (a) (30 min.) You are about to ship a product and you have
a problem with an FPGA. A high case temperature is causing it to be slower than
you thought. You calculated the power dissipation, but you forgot that the InLet
microprocessor is toasting the next door FPGA. You have no easy way to
calculate T J now, so we need to measure it in order to redesign the FPGA with
fixed I/O locations. You remember that a diode forward voltage has a temperature
coefficient of about 2 mV°C 1 and there are clamp diodes on the FPGA I/O.
Explain, using circuit diagrams, how to measure the T J of an FPGA in-circuit
using: a voltage supply, DVM, thermometer, resistors, spoon, and a coffee maker.
(b) (**120 min.) Try it.
6.14 (Delay measurement, 10 min.) Sumo Silicon has a new process ready before
we do and Sumos data book timing figures are much better than ours. Explain
how to reduce our logic delays by changing our measurement circuits and trip
points.
6.15 (Data sheets, 10 min.) In the 1994 data book Xilinx specifies V ILmin = 0.3 V
(and V ILmax = 0.8 V) for the XC2000L. Why does this surprise you and what do
you think the value for VILmin really is? FPGA vendors produce thousands of
pages of data every year with virtually no errors. It is important to have the
confidence to question a potential error.
6.16 (GTL, 60 min.) Find the original reference to Gunning transistor logic. Write
a one-page summary of its uses and how it works.
6.17 (Thresholds, 10 min.) With some FPGAs it is possible to configure an output
at TTL thresholds and an input (on the same pad) at CMOS thresholds. Can you
think of a reason why you might want to do this?
6.18 (Input levels, 10 min.) When we define V IHmin = 0.7 V DD , why do we
calculate the minimum value of V IH using V DDmax = 5.5 V?
6.19 (Metastability equations, 30 min.)
● a. From Eq. 6.4 show that if we make two measurements of t r and MTBF
then:
tr1 t r2
tc= ,
(6.14)
ln MTBF 1 ln MTBF 2
exp t r 1 / t c
T0= .
(6.15)
ln MTBF 1 f c f d
●
b. MTBU is extremely sensitive to variations in t c , show that:
d MTBU t r
=
. (6.16)
dtc
tc2
●
c. Show that the variation in MTBU is related to the variation in t c by the
following expression:
D MTBU t r Dt c
=
. (6.17)
tc2
MTBU
6.20 (***Alternative metastability solutions, 120 min.) Write a minitutorial on
metastability solutions. The best sources for this type of information are usually
application notes written by FPGA and TTL manufacturers, many of which are
available on the Web (TI is a good source on this topic).
6.21 (Altera 8000 I/O, 10 min) Figure 6.26 shows the Altera FLEX 8000 I/O
characteristics. Determine as much as you are able to from these figures.
FIGURE 6.26 (a) Altera FLEX 8000 I/O characteristics operating at 5 V.
(b) EPF8282V I/O operating at 3.3 V. (c) Characteristics with mixed 5V and 3.3
V I/O operation.
6.22 (Power calculation, 60 min.) Suppose we wish to limit power dissipation on
an ACT 1 A1020 chip to below 1 W for a 44-pin PLCC package.
● a. Derive an equation for the number of logic modules, number of I/O
modules, number of modules connected to the clock and system clock
frequency in terms of the package parameters and the worst-case T A .
●
b. Assume:
100 percent utilization of I/Os,
50 percent are outputs connected to a 50 pF load,
100 percent utilization of logic modules,
10 percent of the logic modules are connected to the clock,
20 percent of the logic modules toggle every clock cycle,
20 percent of the I/Os toggle every clock cycle.
Determine an upper limit on clock frequency.
● c. Next vary each of the assumptions you made in part b. Draw graphs
showing the variation of clock frequency as you vary each of the above
parameters, including the power dissipation limit (a spreadsheet will help).
● d. Can you draw any conclusions from this exercise?
6.23 (Switch debounce, 30 min) Design a logic circuit to debounce the output
from a buffer whose input is connected to a bounce-prone switch. Your system
operates at a clock frequency of 1 MHz.
6.24 (Plugs and sockets, 30 min.) Draw the plugs and sockets (to scale) for the
technologies in Table 6.9 .
TABLE 6.9 TTL-compatible CMOS logic thresholds (Problems 6.24 and 6.25 ).
12
Input levels Output levels driving TTL
Family V
V
74HCT 2.0
74HC 3.85
74ACT 2.0
74AC 3.85
0.8
1.35
0.8
1.35
V
I
V
I
Output levels driving CMOS
13
V
I
V
I
IHmin ILmax OHmin OHmax OLmax OLmax OHmin OHmax OLmax OLmax
3.84
3.84
3.76
3.76
4.0
4.0
24.0
24.0
0.33
0.33
0.37
0.37
4.0
4.0
24.0
24.0
4.4
4.4
4.4
4.4
0.02
0.02
0.05
0.05
0.1
0.1
0.1
0.1
0.02
0.02
0.05
0.05
6.25 (TTL compatibility, 30 min.) Explain very carefully, giving an example
using actual figures from the tables, how you would determine the compatibility
between the TTL and CMOS logic thresholds shown in Table 6.9 and Table 6.10
and the FPGA logic thresholds in Table 6.1 .
TABLE 6.10 TTL logic thresholds (Problem 6.25 ). 14
TTL Family 15 V IHmin V ILmax V OHmin I OHmax V OLmax I OLmax I IHmax I ILmax
74S
2.0
0.8
2.7
1.0
0.5
20.0 0.05 2.0
74LS
2.0
0.8
2.7
0.4
0.5
8.0
0.02 0.4
74ALS
2.0
0.8
2.7
0.4
0.5
8.0
0.02 0.2
74AS
2.0
0.8
2.7
2.0
0.5
20.0 0.02 0.5
74F
2.0
0.8
2.7
1.0
0.5
20.0 0.02 0.6
74FCT
2.0
0.8
2.4
15.0
0.5
48.0 ±0.005 ±0.005
74FCT-T
2.0
0.8
2.4
8.0
0.5
48.0 ±0.005 ±0.005
6.26 (ECL, 30 min.) Emitter-coupled logic (ECL) uses a positive supply, V CC =
0 V, and a negative supply, V EE = 5.2 V. The highest logic voltage allowed is
0.81 V and the lowest is 1.85 V. Table 6.11 shows the ECL 10K thresholds.
●
●
●
a. Calculate the high-level and low-level noise margins.
b. Find out the 100K thresholds and
c. calculate the 100K noise margins.
TABLE 6.11 ECL logic thresholds (Problem 6.26 ).
V IHmin / V V ILmax / V V OHmin / V V OLmax / V
ECL10K 1.105
ECL100K
1.475
0.980
1.630
6.27 (Schmitt trigger, 30 min.) Find out the typical hysteresis for a TTL Schmitt
trigger. What are the advantages and disadvantages of changing the hysteresis?
6.28 (Hysteresis, 20 min.)
● a. Draw the transfer curve for an inverting buffer with very high gain that
has a switching threshold centered at 2.2 V and 300 mV hysteresis.
● b. If the center of the characteristic shifts by 0.3 V and +0.4 V and the
hysteresis varies from 260 mV to 350 mV, calculate V IHmin and V ILmax .
6.29 (Driving an LED, 30 min.) Find out the typical current and voltage drive
required by an LED and design a circuit to drive it. List your sources of
information.
6.30 (**Driving TTL, 60 min.) Find out the input current requirements of
different TTL families and write a minitutorial on the I/O requirements (in
particular the current) when driving high and low levels onto a bus.
1. Code definitions are listed in Table 6.4 .
2. ACT 2 I/O Module is separate from the I/O Pad Driver.
3. Xilinx EPLD uses a mixture of I/O blocks, input-only blocks, and output-only
blocks. The I/O blocks and input only blocks contain the equivalent of a D
flip-flop (configured to be a flip-flop or latch).
4. 8 I/O are dedicated inputs on all parts.
5. Code definitions are listed in Table 6.4 .
6. ACT 3 I/O Module is separate from the I/O Pad Driver.
7. Discontinued August 1986.
8. Two output modes: Capacitive (4SNK) and Resistive (24SNK).
9. 1994 databook, p. 8-15 and p. 9-23.
10. Currents in milliamperes.
11. Xilinx 1994 data book, p. 2-48.
12. All voltages in volts, all currents in milliamperes.
13. I IHmax = ±0.001 mA, I ILmax = ±0.001 mA for all families.
14. All voltages in volts, all currents in milliamperes
15. Other (older) TTL and CMOS logic families include 4000, 74, 74H, and 74L
6.11 Bibliography
Wakerlys [1994] book describes TTL and CMOS logic thresholds as well as
noise margins. The specification of digital I/O interfaces (voltage and current
levels) is defined by the JEDEC (part of the Electronic Industries Association,
EIA) JC-16 committee standards [JEDEC I/O]. Standards for ESD measurement
are not as well defined; companies use a range of specifications: MIL-STD-883,
EIAJ, a published model used by AT&T (see, for example, p. 5-13 to p. 5-19 in
the AT&T 1995 FPGA data book) as well as JEDEC and ANSI/IEEE standards
[JEDEC I/O, JEDEC ESD, ANSI/IEEE ESD]. You are not likely to find any of
these standards at the library, but they are available through specialist technical
document distributors (typical 1996 costs were about $25 for the JEDEC
documents; catalogs are generally free of charge). These standards are not
technical reports, most only contain a few pages, but they are the source of the
parameters that you see in data sheets.
6.12 References
Page numbers in brackets after a reference indicate its location in the chapter
body.
[JEDEC I/O] [ reference location ] In numerical (not chronological) order the
relevant JEDEC standards for I/O are:
JESD8-A. Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated
Circuits (June 1994). This standard replaces JEDEC Standards 8, 8-1, and 8-1-A
and defines the DC interface parameters for digital circuits operating from a
power supply of nominal 3 V/3.3 V.
JESD8-2. Standard for Operating Voltages and Interface Levels for Low Voltage
Emitter-Coupled Logic (ECL) Integrated Circuits (March 1993). Describes 300K
ECL (voltage and temperature compensated, with threshold levels compatible
with 100K ECL).
JESD8-3. Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits (Nov. 1993). Defines the DC input and
output specifications for a low-level, high-speed interface for integrated circuits.
JESD8-4. Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits (Nov. 1993). Defines the DC I/O
specifications for a low-level, high-speed interface for integrated circuits that can
be a superset of LVCMOS and LVTTL.
JESD8-5. 2.5 V +/ 0.2 V (Normal Range), and 1.8 V2.7 V (Wide Range) Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated
Circuit (Oct. 1995). Defines power supply voltage ranges, DC interface
parameters for a high-speed, low-voltage family of nonterminated digital circuits.
JESD8-6. High Speed Transceiver Logic (HSTL): A 1.5 V Output Buffer Supply
Voltage Based Interface Standard for Digital Integrated Circuits (Aug. 1995).
Describes a 1.5 V high-performance CMOS interface suitable for high I/O count
CMOS and BiCMOS devices operating at over 200 MHz.
JESD12-6. Interface Standard for Semicustom Integrated Circuits (March 1991).
Defines logic interface levels for CMOS, TTL, and ECL inputs and outputs for 5
V operation.
[JEDEC ESD, ANSI/IEEE ESD] The JEDEC and IEEE standards for ESD are:
JESD22-C101. Field Induced Charged Device Model Test Method for
Electrostatic Discharge Withstand Thresholds of Microelectronic Components
(May 1995). Describes Charged Device Model that simulates
charging/discharging events that occur in production equipment and processes.
Potential for CDM ESD events occur with metal-to-metal contact in
manufacturing.
ANSI/EOS/ESD S5.1-1993. Electrostatic Discharge (ESD) Sensitivity Testing,
Human Body Model (HBM), Component Level.
ANSI/IEEE C62.47-1992. Guide on Electrostatic Discharge (ESD):
Characterization of the ESD Environment.
ANSI/IEEE 1181-1991. Latchup Test Methods for CMOS and BiCMOS
Integrated Circuit Process Characterization.
PCI Local Bus Specification, Revision 2.1, June 1, 1995. Available from PCI
Special Interest Group, PO Box 14070, Portland OR 97214. (800) 433-5177
(U.S.), (503)797-4207 (International). 282 p. Detailed description of the electrical
and mechanical requirements for the PCI Bus written for engineers who already
understand the basic operation of the bus protocol. [ reference location ]
Wakerly, J. F. 1994. Digital Design: Principles and Practices. 2nd ed. Englewood
Cliffs, NJ: Prentice-Hall, 840 p. ISBN 0-13-211459-3. TK7874.65.W34. [
reference location ]
L ast E d ited by S P 1411 2 0 0 4
PROGRAMMABLE
ASIC
INTERCONNECT
All FPGAs contain some type of programmable interconnect . The structure and
complexity of the interconnect is largely determined by the programming
technology and the architecture of the basic logic cell. The raw material that we
have to work with in building the interconnect is aluminum-based metallization,
which has a sheet resistance of approximately 50 m W /square and a line
capacitance of 0.2 pFcm 1 . The first programmable ASICs were constructed
using two layers of metal; newer programmable ASICs use three or more layers
of metal interconnect.
7.1 Actel ACT
The Actel ACT family interconnect scheme shown in Figure 7.1 is similar to a
channeled gate array. The channel routing uses dedicated rectangular areas of
fixed size within the chip called wiring channels (or just channels ). The
horizontal channels run across the chip in the horizontal direction. In the vertical
direction there are similar vertical channels that run over the top of the basic logic
cells, the Logic Modules. Within the horizontal or vertical channels wires run
horizontally or vertically, respectively, within tracks . Each track holds one wire.
The capacity of a fixed wiring channel is equal to the number of tracks it
contains. Figure 7.2 shows a detailed view of the channel and the connections to
each Logic Modulethe input stubs and output stubs .
FIGURE 7.1 The interconnect architecture used in an Actel ACT family FPGA.
( Source: Actel.)
FIGURE 7.2 ACT 1 horizontal and vertical channel architecture. (Source:
Actel.)
In a channeled gate array the designer decides the location and length of the
interconnect within a channel. In an FPGA the interconnect is fixed at the time of
manufacture. To allow programming of the interconnect, Actel divides the fixed
interconnect wires within each channel into various lengths or wire segments. We
call this segmented channel routing, a variation on channel routing. Antifuses
join the wire segments. The designer then programs the interconnections by
blowing antifuses and making connections between wire segments; unwanted
connections are left unprogrammed. A statistical analysis of many different
layouts determines the optimum number and the lengths of the wire segments.
7.1.1 Routing Resources
The ACT 1 interconnection architecture uses 22 horizontal tracks per channel for
signal routing with three tracks dedicated to VDD, GND, and the global clock
(GCLK), making a total of 25 tracks per channel. Horizontal segments vary in
length from four columns of Logic Modules to the entire row of modules (Actel
calls these long segments long lines ).
Four Logic Module inputs are available to the channel below the Logic Module
and four inputs to the channel above the Logic Module. Thus eight vertical tracks
per Logic Module are available for inputs (four from the Logic Module above the
channel and four from the Logic Module below). These connections are the input
stubs.
The single Logic Module output connects to a vertical track that extends across
the two channels above the module and across the two channels below the
module. This is the output stub. Thus module outputs use four vertical tracks per
module (counting two tracks from the modules below, and two tracks from the
modules above each channel). One vertical track per column is a long vertical
track ( LVT ) that spans the entire height of the chip (the 1020 contains some
segmented LVTs). There are thus a total of 13 vertical tracks per column in the
ACT 1 architecture (eight for inputs, four for outputs, and one for an LVT).
Table 7.1 shows the routing resources for both the ACT 1 and ACT 2 families.
The last two columns show the total number of antifuses (including antifuses in
the I/O cells) on each chip and the total number of antifuses assuming the wiring
channels are fully populated with antifuses (an antifuse at every horizontal and
vertical interconnect intersection). The ACT 1 devices are very nearly fully
populated.
TABLE 7.1 Actel FPGA routing resources.
Total
Horizontal
tracks per
channel, H
A1010 22
A1020 22
A1225A 36
A1240A 36
A1280A 36
Vertical
antifuses
tracks per Rows, R Columns, C
column, V
on each
chip
13
8
44
112,000
13
14
44
186,000
15
13
46
250,000
15
14
62
400,000
15
18
82
750,000
H¥V¥R
¥C
100,672
176,176
322,920
468,720
797,040
If the Logic Module at the end of a net is less than two rows away from the driver
module, a connection requires two antifuses, a vertical track, and two horizontal
segments. If the modules are more than two rows apart, a connection between
them will require a long vertical track together with another vertical track (the
output stub) and two horizontal tracks. To connect these tracks will require a total
of four antifuses in series and this will add delay due to the resistance of the
antifuses. To examine the extent of this delay problem we need some help from
the analysis of RC networks.
7.1.2 Elmores Constant
Figure 7.3 shows an RC tree representing a net with a fanout of two. We shall
assume that all nodes are initially charged to V DD = 1 V, and that we short node
0 to ground, so V 0 = 0 V, at time t = 0 sec. We need to find the node voltages, V
1 to V 4 , as a function of time. A similar problem arose in the design of
wideband vacuum tube distributed amplifiers in the 1940s. Elmore found a
measure of delay that we can use today [ Rubenstein, Penfield, and Horowitz,
1983].
FIGURE 7.3 Measuring the delay of a net. (a) An RC tree. (b) The waveforms
as a result of closing the switch at t = 0.
The current in branch k of the network is
dVk
ik= C
. (7.1)
k
dt
The linear superposition of the branch currents gives the voltage at node i as
dVk
n
V i = S R ki C k
k=1
dt
, (7.2)
where R ki is the resistance of the path to V 0 (ground in this case) shared by node
k and node i . So, for example, R 24 = R 1 , R 22 = R 1 + R 2 , and R 31 = R 1 .
Unfortunately, Eq. 7.2 is a complicated set of coupled equations that we cannot
easily solve. We know the node voltages have different values at each point in
time, but, since the waveforms are similar, let us assume the slopes (the time
derivatives) of the waveforms are related to each other. Suppose we express the
slope of node voltage V k as a constant, a k , times the slope of V i ,
dVi
dVk
=ak
dt
. (7.3)
dt
Consider the following measure of the error, E , of our approximation:
n
E = S R ki C k . (7.4)
k=1
The error, E , is a minimum when a k = 1 since initially V i ( t = 0) = V k ( t = 0)
= 1 V (we normalized the voltages) and V i ( t = " ) = V k ( t = " ) = 0.
Now we can rewrite Eq. 7.2 , setting a k = 1, as follows:
n
dVi
V i = S R ki C k
k=1
dt
, (7.5)
This is a linear first-order differential equation with the following solution:
n
V i ( t ) = exp ( t / t Di ) ; t Di = S
R ki C k . (7.6)
k=1
The time constant t D i is often called the Elmore delay and is different for each
node. We shall refer to t D i as the Elmore time constant to remind us that, if we
approximate V i by an exponential waveform, the delay of the RC tree using
0.35/0.65 trip points is approximately t Di seconds.
7.1.3 RC Delay in Antifuse Connections
Suppose a single antifuse, with resistance R 1 , connects to a wire segment with
parasitic capacitance C 1 . Then a connection employing a single antifuse will
delay the signal passing along that connection by approximately one time
constant, or R 1 C 1 seconds. If we have more than one antifuse, we need to use
the Elmore time constant to estimate the interconnect delay.
FIGURE 7.4 Actel routing model. (a) A four-antifuse connection. L0 is an
output stub, L1 and L3 are horizontal tracks, L2 is a long vertical track (LVT),
and L4 is an input stub. (b) An RC-tree model. Each antifuse is modeled by a
resistance and each interconnect segment is modeled by a capacitance.
For example, suppose we have the four-antifuse connection shown in Figure 7.4 .
Then, from Eq. 7.6 ,
t D 4 = R 14 C 1 + R 24 C 2 + R 14 C 1 + R 44 C 4
=
(R 1 + R 2 + R 3 + R 4 ) C 4 + (R 1 + R 2 + R 3 ) C 3 + (R 1 + R 2 ) C 2 +
R1C1
If all the antifuse resistances are approximately equal (a reasonably good
assumption) and the antifuse resistance is much larger than the resistance of any
of the metal lines, L1L5, shown in Figure 7.4 (a very good assumption) then R 1
= R 2 = R 3 = R 4 = R , and the Elmore time constant is
t D 4 = 4 RC 4 + 3 RC 3 + 2 RC 2 + RC 1 (7.7)
Suppose now that the capacitance of each interconnect segment (including all the
antifuses and programming transistors that may be attached) is approximately
constant, and equal to C . A connection with two antifuses will generate a 3 RC
time constant, a connection with three antifuses a 6 RC time constant, and a
connection with four antifuses gives a 10 RC time constant. This analysis is
disturbingit says that the interconnect delay grows quadratically ( n 2 ) as we
increase the interconnect length and the number of antifuses, n . The situation is
worse when the intermediate wire segments have larger capacitance than that of
the short input stubs and output stubs. Unfortunately, this is the situation in an
Actel FPGA where the horizontal and vertical segments in a connection may be
quite long.
7.1.4 Antifuse Parasitic Capacitance
We can determine the number of antifuses connected to the horizontal and
vertical lines for the Actel architecture. Each column contains 13 vertical signal
tracks and each channel contains 25 horizontal tracks (22 of these are used for
signals). Thus, assuming the channels are fully populated with antifuses,
● An input stub (1 channel) connects to 25 antifuses.
● An output stub (4 channels) connects to 100 (25 ¥ 4) antifuses.
● An LVT (1010, 8 channels) connects to 200 (25 ¥ 8) antifuses.
● An LVT (1020, 14 channels) connects to 350 (25 ¥ 14) antifuses.
● A four-column horizontal track connects to 52 (13 ¥ 4) antifuses.
● A 44-column horizontal track connects to 572 (13 ¥ 44) antifuses.
A connection to the diffusion of an Actel antifuse has a parasitic capacitance due
to the diffusion junction. The polysilicon of the antifuse has a parasitic
capacitance due to the thin oxide. These capacitances are approximately equal.
For a 2 m m CMOS process the capacitance to ground of the diffusion is 200 to
300 aF m m 2 (area component) and 400 to 550 aF m m 1 (perimeter
component). Thus, including both area and perimeter effects, a 16 m m 2
diffusion contact (consisting of a 2 m m by 2 m m opening plus the required
overlap) has a parasitic capacitance of 1014 f F. If we assume an antifuse has a
parasitic capacitance of approximately 10 fF in a 1.0 or 1.2 m m process, we can
calculate the parasitic capacitances shown in Table 7.2 .
TABLE 7.2 Actel interconnect parameters.
Parameter
A1010/A1020
Technology
2.0 m m, l = 1.0 m m
Die height (A1010) 240 mil
Die width (A1010) 360 mil
Die area (A1010)
86,400 mil 2 = 56 M l 2
Logic Module (LM)
180 m m = 180 l
height (Y1)
LM width (X)
150 m m = 150 l
LM area (X ¥ Y1)
27,000 m m 2 = 27 k l 2
Channel height (Y2) 25 tracks = 287 m m
Channel area per LM
43,050 m m 2 = 43 k l 2
(X ¥ Y2)
LM and routing area
70,000 m m 2 = 70 k l 2
(X ¥ Y1 + X ¥ Y2)
Antifuse capacitance
Metal capacitance
0.2 pFmm 1
Output stub length
4 channels = 1688 m m
(spans 3 LMs + 4
channels)
Output stub metal
0.34 pF
capacitance
Output stub antifuse
100
connections
Output stub antifuse
capacitance
444 cols. = 6006600 m
Horiz. track length
m
Horiz. track metal
0.11.3 pF
capacitance
Horiz. track antifuse
52572 antifuses
connections
Horiz. track antifuse
capacitance
A1010B/A1020B
1.2 m m, l = 0.6 m m
144 mil
216 mil
31,104 mil 2 = 56 M l 2
108 m m = 180 l
90 m m = 150 l
9,720 m m 2 = 27 k l 2
25 tracks = 170 m m
15,300 m m 2 = 43 k l 2
25,000 m m 2 = 70 k l 2
10 fF
0.2 pFmm 1
4 channels = 1012 m m
0.20 pF
100
1.0 pF
444 cols. = 3603960 m m
0.070.8 pF
52572 antifuses
0.525.72 pF
Long vertical track
(LVT)
LVT metal
capacitance
LVT track antifuse
connections
LVT track antifuse
capacitance
Antifuse resistance
(ACT 1)
814 channels = 3760
6580 m m
814 channels = 22403920 m m
0.080.13 pF
0.450.8 pF
200350 antifuses
200350 antifuses
23.5 pF
0.5 k W (typ.), 0.7 k W (max.)
We can use the figures from Table 7.2 to estimate the interconnect delays. First
we calculate the following resistance and capacitance values:
1. The antifuse resistance is assumed to be R = 0.5 k W .
2. C 0 = 1.2 pF is the sum of the gate output capacitance (which we shall
neglect) and the output stub capacitance (1.0 pF due to antifuses, 0.2 pF
due to metal). The contribution from this term is zero in our calculation
because we have neglected the pull resistance of the driving gate.
3. C 1 = C 3 = 0.59 pF (0.52 pF due to antifuses, 0.07 pF due to metal)
corresponding to a minimum-length horizontal track.
4. C 2 = 4.3 pF (3.5 pF due to antifuses, 0.8 pF due to metal) corresponding to
a LVT in a 1020B.
5. The estimated input capacitance of a gate is C 4 = 0.02 pF (the exact value
will depend on which input of a Logic Module we connect to).
From Eq. 7.7 , the Elmore time constant for a four-antifuse connection is
t D 4 = 4(0.5)(0.02) + 3(0.5)(0.59) + 2(0.5)(4.3) + (0.5)(0.59) (7.8)
= 5.52 ns .
This matches delays obtained from the Actel delay calculator. For example, an
LVT adds between 510 ns delay in an ACT 1 FPGA (612 ns for ACT 2, and 4
14 ns for ACT 3). The LVT connection is about the slowest connection that we
can make in an ACT array. Normally less than 10 percent of all connections need
to use an LVT and we see why Actel takes great care to make sure that this is the
case.
7.1.5 ACT 2 and ACT 3 Interconnect
The ACT 1 architecture uses two antifuses for routing nearby modules, three
antifuses to join horizontal segments, and four antifuses to use a horizontal or
vertical long track. The ACT 2 and ACT 3 architectures use increased
interconnect resources over the ACT 1 device that we have described. This
reduces further the number of connections that need more than two antifuses.
Delay is also reduced by decreasing the population of antifuses in the channels,
and by decreasing the antifuse resistance of certain critical antifuses (by
increasing the programming current).
The channel density is the absolute minimum number of tracks needed in a
channel to make a given set of connections (see Section 17.2.2, Measurement of
Channel Density ). Software to route connections using channeled routing is so
efficient that, given complete freedom in location of wires, a channel router can
usually complete the connections with the number of tracks equal or close to the
theoretical minimum, the channel density. Actels studies on segmented channel
routing have shown that increasing the number of horizontal tracks slightly (by
approximately 10 percent) above density can lead to very high routing
completion rates.
The ACT 2 devices have 36 horizontal tracks per channel rather than the 22
available in the ACT 1 architecture. Horizontal track segments in an ACT 3
device range from a module pair to the full channel length. Vertical tracks are:
input (with a two channel span: one up, one down); output (with a four-channel
span: two up, two down); and long (LVT). Four LVTs are shared by each column
pair. The ACT 2/3 Logic Modules can accept five inputs, rather than four inputs
for the ACT 1 modules, and thus the ACT 2/3 Logic Modules need an extra two
vertical tracks per channel. The number of tracks per column thus increases from
13 to 15 in the ACT 2/3 architecture.
The greatest challenge facing the Actel FPGA architects is the resistance of the
polysilicon-diffusion antifuse. The nominal antifuse resistance in the ACT 12 12
m m processes (with a 5 mA programming current) is approximately 500 W and,
in the worst case, may be as high as 700 W . The high resistance severely limits
the number of antifuses in a connection. The ACT 2/3 devices assign a special
antifuse to each output allowing a direct connection to an LVT. This reduces the
number of antifuses in a connection using an LVT to three. This type of antifuse
(a fast fuse) is blown at a higher current than the other antifuses to give them
about half the nominal resistance (about 0.25 k W for AC T 2) of a normal
antifuse. The nominal antifuse resistance is reduced further in the ACT 3 (using a
0.8 m m process) to 200 W (Actel does not state whether this value is for a
normal or fast fuse). However, it is the worst-case antifuse resistance that will
determine the worst-case performance.
7.2 Xilinx LCA
Figure 7.5 shows the hierarchical Xilinx LCA interconnect architecture.
●
●
●
●
●
●
The vertical lines and horizontal lines run between CLBs.
The general-purpose interconnect joins switch boxes (also known as magic
boxes or switching matrices).
The long lines run across the entire chip. It is possible to form internal buses
using long lines and the three-state buffers that are next to each CLB.
The direct connections (not used on the XC4000) bypass the switch matrices and
directly connect adjacent CLBs.
The Programmable Interconnection Points ( PIP s) are programmable pass
transistors that connect the CLB inputs and outputs to the routing network.
The bidirectional ( BIDI ) interconnect buffers restore the logic level and logic
strength on long interconnect paths.
FIGURE 7.5 Xilinx LCA interconnect. (a) The LCA architecture (notice the
matrix element size is larger than a CLB). (b) A simplified representation of the
interconnect resources. Each of the lines is a bus.
Table 7.3 shows the interconnect data for an XC3020, a typical Xilinx LCA FPGA,
that uses two-level metal interconnect. Figure 7.6 shows the switching matrix.
Programming a switch matrix allows a number of different connections between the
general-purpose interconnect.
TABLE 7.3 XC3000 interconnect parameters.
Parameter
XC3020
Technology
1.0 m m, l = 0.5 m m
Die height
220 mil
Die width
180 mil
Die area
39,600 mil 2 = 102 M l 2
CLB matrix height (Y)
480 m m = 960 l
CLB matrix width (X)
370 m m = 740 l
CLB matrix area (X ¥ Y)
17,600 m m 2 = 710 k l 2
Matrix transistor resistance, R P1
0.51k W
Matrix transistor parasitic capacitance, C P1 0.010.02 pF
PIP transistor resistance, R P2
PIP transistor parasitic capacitance, C P2
0.51k W
0.010.02 pF
Single-length line (X, Y)
370 m m, 480 m m
Single-length line capacitance: C LX , C LY 0.075 pF, 0.1 pF
Horizontal Longline (8X)
8 cols. = 2960 m m
Horizontal Longline metal capacitance, C LL 0.6 pF
In Figure 7.6 (d), (g), and (h):
FIGURE 7.6 Components of interconnect delay in a Xilinx LCA array. (a) A portion
of the interconnect around the CLBs. (b) A switching matrix. (c) A detailed view
inside the switching matrix showing the pass-transistor arrangement. (d) The
equivalent circuit for the connection between nets 6 and 20 using the matrix. (e) A
view of the interconnect at a Programmable Interconnection Point (PIP). (f) and
(g) The equivalent schematic of a PIP connection. (h) The complete RC delay path.
●
●
●
●
●
●
C1 = 3CP1 + 3CP2 + 0. 5C LX is the parasitic capacitance due to the switch
matrix and PIPs (F4, C4, G4) for CLB1, and half of the line capacitance for the
double-length line adjacent to CLB1.
C P1 and R P1 are the switching-matrix parasitic capacitance and resistance.
C P2 and R P2 are the parasitic capacitance and resistance for the PIP connecting
YQ of CLB1 and F4 of CLB3.
C2 = 0. 5CLX + CLX accounts for half of the line adjacent to CLB1 and the line
adjacent to CLB2.
C 3 = 0. 5C LX accounts for half of the line adjacent to CLB3.
C 4 = 0. 5C LX + 3C P2 + C LX + 3C P1 accounts for half of the line adjacent to
CLB3, the PIPs of CLB3 (C4, G4, YQ), and the rest of the line and switch
matrix capacitance following CLB3.
We can determine Elmores time constant for the connection shown in Figure 7.6 as
t D = R P2 (C P2 + C 2 + 3C P1 ) + (R P2 + R P1 )(3C P1 + C 3 + C P2 ) (7.9)
+ (2R P2 + R P1 )(C P2 + C 4 ) .
If RP1 = RP2 , and CP1 = CP2 , then
t D = (15 + 21)R P C P + (1.5 + 1 + 4.5)R P C LX . (7.10)
We need to know the pass-transistor resistance RP . For example, suppose RP = 1k W .
If
k ' n = 50 m AV 2 , then (with Vt n = 0.65 V and V DD = 3.3 V)
1
1
W/L =
=
k ' n R p ( V DD V
tn
= 7.5
. (7.11)
) (50 ¥ 10 6 )(1 ¥ 10 3 )(3.3 0.65)
If L = 1 m m, both source and drain areas are 7.5 m m long and approximately 3 m m
wide (determined by diffusion overlap of contact, contact width, and contact-to-gate
spacing, rules 6.1a + 6.2a + 6.4a = 5.5 l in Table 2.7 ). Both drain and source areas are
thus 23 m m 2 and the sidewall perimeters are 14 m m (excluding the sidewall facing
the channel). If we have a diffusion capacitance of 140 aF m m 2 (area) and 500 aF m
m 1 (perimeter), typical values for a 1.0 m m process, the parasitic source and drain
capacitance is
C P = (140 ¥ 10 18 )(23) + (500 ¥ 10 18 )(14) (7.12)
= 1.022 ¥ 10 14 F .
If we assume CP = 0.01 pF and CLX = 0.075 pF ( Table 7.3 ),
t D = (36)(1)(0.01) + (7)(1)(0.075) (7.13)
= 0.885 ns .
A delay of approximately 1 ns agrees with the typical values from the XACT delay
calculator and is about the fastest connection we can make between two CLBs.
FIGURE 7.7 The Xilinx EPLD UIM (Universal Interconnection Module). (a) A
simplified block diagram of the UIM. The UIM bus width, n , varies from 68
(XC7236) to 198 (XC73108). (b) The UIM is actually a large programmable AND
array. (c) The parasitic capacitance of the EPROM cell.
7.3 Xilinx EPLD
The Xilinx EPLD family uses an interconnect bus known as Universal
Interconnection Module ( UIM ) to distribute signals within the FPGA. The UIM,
shown in Figure 7.7 , is a programmable AND array with constant delay from
any input to any output. In Figure 7.7 :
●
C G is the fixed gate capacitance of the EPROM device.
●
C D is the fixed drain parasitic capacitance of the EPROM device.
●
C B is the variable horizontal bus (bit line) capacitance.
●
C W is the variable vertical bus (word line) capacitance.
Figure 7.7 shows the UIM has 21 output connections to each FB. 1 Thus the
XC7272 UIM (with a 4 ¥ 2 array of eight FBs as shown in Figure 7.7 ) has 168 (8
¥ 21) output connections. Most (but not all) of the nine I/O cells attached to each
FB have two input connections to the UIM, one from a chip input and one
feedback from the macrocell output. For example, the XC7272 has 18 I/O cells
that are outputs only and thus have only one connection to the UIM, so n = (18 ¥
8) 18 = 126 input connections. Now we can calculate the number of tracks in the
UIM: the XC7272, for example, has H = 126 tracks and V = 168/2 = 84 tracks.
The actual physical height, V , of the UIM is determined by the size of the FBs,
and is close to the die height.
The UIM ranges in size with the number of FBs. For the smallest XC7236 (with a
2 ¥ 2 array of four FBs), the UIM has n = 68 inputs and 84 outputs. For the
XC73108 (with a 6 ¥ 2 array of 12 FBs), the UIM has n = 198 inputs. The UIM is
a large array with large parasitic capacitance; it employs a highly optimized
structure that uses EPROM devices and a sense amplifier at each output. The
signal swing on the UIM uses less than the full V DD = 5 V to reduce the
interconnect delay.
1. 1994 data book p. 3-62 and p. 3-78.
7.4 Altera MAX 5000 and 7000
Altera MAX 5000 devices (except the EPM5032, which has only one LAB) and
all MAX 7000 devices use a Programmable Interconnect Array ( PIA ), shown in
Figure 7.8 . The PIA is a cross-point switch for logic signals traveling between
LABs. The advantages of this architecture (which uses a fixed number of
connections) over programmable interconnection schemes (which use a variable
number of connections) is the fixed routing delay. An additional benefit of the
simpler nature of a large regular interconnect structure is the simplification and
improved speed of the placement and routing software.
FIGURE 7.8 A simplified block diagram of the Altera MAX interconnect
scheme. (a) The PIA (Programmable Interconnect Array) is deterministicdelay
is independent of the path length. (b) Each LAB (Logic Array Block) contains a
programmable AND array. (c) Interconnect timing within a LAB is also fixed.
Figure 7.8 (a) illustrates that the delay between any two LABs, t PIA , is fixed.
The delay between LAB1 and LAB2 (which are adjacent) is the same as the
delay between LAB1 and LAB6 (on opposite corners of the die). It may seem
rather strange to slow down all connections to the speed of the longest possible
connectiona large penalty to pay to achieve a deterministic architecture.
However, it gives Altera the opportunity to highly optimize all of the connections
since they are completely fixed.
7.5 Altera MAX 9000
Figure 7.9 shows the Altera MAX 9000 interconnect architecture. The size of the
MAX 9000 LAB arrays varies between 4 ¥ 5 (rows ¥ columns) for the EPM9320
and 7 ¥ 5 for the EPM9560. The MAX 9000 is an extremely coarse-grained
architecture, typical of complex PLDs, but the LABs themselves have a finer
structure. Sometimes we say that complex PLDs with arrays (LABs in the Altera
MAX family) that are themselves arrays (of macrocells) have a dual-grain
architecture .
FIGURE 7.9 The Altera
MAX 9000 interconnect
scheme. (a) A 4 ¥ 5
array of Logic Array
Blocks (LABs), the same
size as the EMP9400
chip. (b) A simplified
block diagram of the
interconnect architecture
showing the connection
of the FastTrack buses to
a LAB.
In Figure 7.9 (b), boxes A, B, and C represent the interconnection between the
FastTrack buses and the 16 macrocells in each LAB:
● Box A connects a macrocell to one row channel.
● Box B connects three column channels to two row channels.
● Box C connects a macrocell to three column channels.
7.6 Altera FLEX
Figure 7.10 shows the interconnect used in the Altera FLEX family of complex
PLDs. Altera refers to the FLEX interconnect and MAX 9000 interconnect by the
same name, FastTrack, but the two are different because the granularity of the
logic cell arrays is different. The FLEX architecture is of finer grain than the
MAX arraysbecause of the difference in programming technology. The FLEX
horizontal interconnect is much denser (at 168 channels per row) than the vertical
interconnect (16 channels per column), creating an aspect ratio for the
interconnect of over 10:1 (168:16). This imbalance is partly due to the aspect
ratio of the die, the array, and the aspect ratio of the basic logic cell, the LAB.
FIGURE 7.10 The Altera FLEX interconnect scheme. (a) The row and column
FastTrack interconnect. The chip shown, with 4 rows ¥ 21 columns, is the same
size as the EPF8820. (b) A simplified diagram of the interconnect architecture
showing the connections between the FastTrack buses and a LAB. Boxes A, B,
and C represent the bus-to-bus connections.
As an example, the EPF8820 has 4 rows and 21 columns of LABs ( Figure 7.10
a). Ignoring, for simplicitys sake, what happens at the edge of the die we can
total the routing channels as follows:
● Horizontal channels = 4 rows ¥ 168 channels/row = 672 channels.
● Vertical channels = 21 rows ¥ 16 channels/row = 336 channels.
It appears that there is still approximately twice (672:336) as much interconnect
capacity in the horizontal direction as the vertical. If we look inside the boxes A,
B, and C in Figure 7.10 (b) we see that for individual lines on each bus:
●
●
●
Box A connects an LE to two row channels.
Box B connects two column channels to a row channel.
Box C connects an LE to two column channels.
There is some dependence between boxes A and B since they contain MUXes
rather than direct connections, but essentially there are twice as many
connections to the column FastTrack as the row FastTrack, thus restoring the
balance in interconnect capacity.
7.7 Summary
The RC product of the parasitic elements of an antifuse and a pass transistor are not
too different. However, an SRAM cell is much larger than an antifuse which leads to
coarser interconnect architectures for SRAM-based programmable ASICs. The
EPROM device lends itself to large wired-logic structures. These differences in
programming technology lead to different architectures:
● The antifuse FPGA architectures are dense and regular.
● The SRAM architectures contain nested structures of interconnect resources.
● The complex PLD architectures use long interconnect lines but achieve
deterministic routing.
Table 7.4 is a look-up table for Tables 7.5 and 7.6 , which summarize the features of
the logic cells used by the various FPGA vendors.
TABLE 7.4 I/O Cell Tables.
Table
Programmable ASIC family
Actel (ACT 1)
Table
Programmable ASIC family
Xilinx (XC3000)
Actel (ACT 2)
Table 7.5
Xilinx (XC4000)
Xilinx (XC8100)
Altera MAX (EPM 5000)
Lucent ORCA (2C)
Xilinx EPLD (XC7200/7300)
Table 7.6
Altera FLEX (8000/10k)
Actel (ACT 3)
AMD MACH 5
QuickLogic (pASIC 1)
Actel 3200DX
Crosspoint (CP20K)
Altera MAX (EPM 9000)
Altera MAX (EPM 7000)
Atmel (AT6000)
Xilinx LCA (XC5200)
TABLE 7.5 Programmable ASIC interconnect.
Actel (ACT 1)
Xilinx (XC3000)
Actel (ACT 2)
Xilinx
(XC4000)
Channeled array
Interconnect with segmented
routing, long lines:
between
logic cells
25 trks/ch. (horiz.);
(tracks =
13 trks/ch. (vert.);
trks)
< 4 antifuses/path
Switch box, PIPs
(Programmable
Interconnect
Points), 3-state
internal bus, and
long lines
Channeled
array with
segmented
routing, long Switch box,
PIPs
lines:
(Programmable
36 trks/ch.
Interconnect
(horiz.); 15
Points), 3-state
trks/ch.
internal bus,
(vert.);
and long lines
<4
antifuses/path
Interconnect
Variable
delay
Interconnect
Polydiffusion
inside logic
antifuse
cells
Variable
Variable
32-bit SRAM LUT
Polydiffusion 32-bit SRAM
antifuse
LUT
Altera (MAX 5000) Xilinx EPLD
QuickLogic
(pASIC 1)
Variable
Actel (ACT 3)
Cross-bar PIA
Programmable Channeled
UIM
(Universal
(Programmable
array with
Interconnect Interconnect
Interconnect Matrix) fully
segmented
between
populated
Architecture) using using EPROM
routing, long
logic cells EPROM
programmable-AND
lines: <4
antifuse
programmable-AND array
antifuses/path
matrix
array
Interconnect
Fixed
Fixed
Variable
Variable
delay
Interconnect
Metalmetal
Polydiffusion
inside logic EPROM
EPROM
antifuse
antifuse
cells
Altera MAX
Crosspoint (CP20K)
(MAX 7000)
Atmel
(AT6000)
Xilinx LCA
(XC5200)
Programmable
Interconnect highly
between
logic cells interconnected
matrix
Interconnect
Variable
delay
Interconnect Metalmetal
inside logic
antifuse
cells
Switch box,
Programmable
PIPs
Fixed cross-bar PIA regular, local,
(Programmable
(Programmable
and express
Interconnect
Interconnect
bus scheme
Points), 3-state
Architecture)
with line
internal bus,
repeaters
and long lines
Fixed
Variable
EEPROM
SRAM
Variable
16-bit SRAM
LUT
TABLE 7.6 Programmable ASIC interconnect (continued).
Xilinx (XC8100)
Lucent ORCA 2C
Altera FLEX
8000/10k
Channeled array with
Interconnect
between logic
cells
segmented routing,
long lines.
Programmable fully
populated antifuse
matrix.
Switch box, SRAM
programmable
Row and column
interconnect, 3-state FastTrack between
internal bus, and long LABs
lines
Interconnect delay Variable
Variable
Interconnect
inside logic cells
SRAM LUTs and
MUXs
Antifuse
Fixed with small
variation in delay in
row FastTrack
LAB local
interconnect between
LEs. 16-bit SRAM
LUT in LE.
AMD MACH 5
Actel 3200DX
Altera MAX 9000
Channeled gate array Row and column
Interconnect
EPROM
between logic
FastTrack between
programmable array with segmented
cells
LABs
routing, long lines
Interconnect delay Fixed
Variable
Fixed
Programmable AND
Interconnect
Polydiffusion
EPROM
array inside LAB,
inside logic cells
antifuse
EEPROM MUXes
The key points covered in this chapter are:
● The difference between deterministic and nondeterministic interconnect
● Estimating interconnect delay
● Elmores constant
Next, in Chapter 8, we shall cover the software you need to design with the various
7.8 Problems
* = Difficult, ** = Very difficult, *** = Extremely difficult
7.1 (*Xilinx interconnect, 120 min.)
● a. Write a minitutorial (one or two pages) explaining what you need to
know to run and use the XACT delay calculator. Explain how to choose
the part, set the display preferences, make connections to CLBs and the
interconnect, and obtain timing figures.
● b. Use the XACT editor to determine typical delays using the longlines, a
switch matrix, the PIPs, and BIDI buffers (see the Xilinx data book for
more detailed explanations of the interconnect structure). Draw six
different typical paths using these elements and show the components of
delay. Include screen shots showing the layout of the paths and cells with
detailed explanations of the figures.
● c. Construct a path using the TBUFs, the three-state buffers, driving a
longline (do not forget the pull-up). Show the XACT calculated delay for
your path and explain the number from data book parameters (list them
and the page number from the data book).
● d. Extend one simple path to the I/O and explain the input and output
timing, again using the data book.
● e. Include screen shots from the layout editor showing you example paths.
● f. Bury all the ASCII (but not binary) files you used and the tools produced
inside your report using Hidden Text. Include explanations as to what
these files are and which parts of the report they go with. This includes any
schematic files, netlist files, and all files produced by the Xilinx tools. Use
a separate directory for this problem and make a list in your report of all
files (binary and ASCII) with explanations of what each file is.
7.2 (*Actel interconnect, 120 min.) Use the Actel chip editor to explore the
properties of the interconnect scheme in a similar fashion to Problem 7.1 with
the following changes: in part b make at least six different paths using various
antifuse connections and explain the numbers from the delay calculator. Omit
part c.
7.3 (*Altera MAX interconnect, 120 min.) Use the Altera tools to determine the
properties of the MAX or FLEX interconnect in a similar fashion to Problem 7.1
with the following changes: In parts b and c construct at least six example circuits
that show the various paths through the FastTrack or PIA chip-level interconnect,
the local LAB array, the LAB, and the macrocells.
7.4 (**Custom ASICs, 120 min.)
● a. Write a minitutorial (one or two pages) explaining how to run an ASIC
tool (Compass/Mentor/Cadence/Tanner). Enter a simple circuit (using
schematic entry or synthesis and cells from a cell library) and obtain a
delay estimate.
● b. Construct at least six example circuits that show various logic paths
using various logic cells (for example: an inverter, a full adder).
● c. Perform a timing simulation (either using a static timing verifier or using
a logic simulator). Compare your results with those from a data book.
● d. Extract the circuit to include the parasitic capacitances from layout in
your circuit netlist and run a simulation to predict the delays.
● e. Compare the results that include routing capacitance with the data book
values for the logic cell delays and with the values predicted before
routing.
● f. Extend one simple path to the outputs of the chip by including I/O pads
in your circuit and explain the input and output timing predictions.
● g. Bury the ASCII files you used and the tools produced inside your report.
7.5 (**Actel stubs, 60 min.)
● a. Which metal layers do you think Actel assigns to the horizontal and
vertical interconnect in the ACT 13 architectures and why?
● b. Why do the ACT 13 input stubs not extend over more than two
channels above and below the Logic Modules, since this would reduce the
need for LVTs?
● c. The ACT 2 data sheet describes the output stubs as twisted (or
interwoven) so that they occupy only four tracks. Show that the stubs
occupy four vertical tracks whether they are twisted or not.
● d. Suggest the real reason for the twisted stubs.
7.6 (A three-input NAND in ACT 1, 30 min.) The macros that require two
ACT 1 modules include the three-input NAND (others include four-input NAND,
AND, NOR).
● a. What is the problem with trying to implement a three-input NAND gate
using the Actel ACT 1 Logic Module?
● b. Suggest a modification to the ACT 1 Logic Module that would allow the
implementation of a three-input NAND using one of your new Logic
Modules.
● c. Can you think of a reason why Actel did not use your modification to its
Logic Module design? Hi nt: The modification has to do with routing, and
not the logic itself.
7.7 (*Actel architecture, 60 min.) This is a long but relatively straightforward
problem that reverse-engineers the Actel architecture. If you measured the chip
photo on the front of the April 1990 Actel data book, you would find the
following:
1. Die height (scribe to scribe) = 170 mm.
2. Channel height = 8 mm (there are 7 full-height and 2 half-height channels).
3. Logic Module height = 5 mm (there are 8 rows of Logic Modules).
4. Column (Logic Module) width = 4.2 mm.
(The scribe line is an area at the edge of a die where a cut is made by a diamond
saw when the dice are separated.) An Actel 1010 die in 2 m m technology is 240
mil high by 360 mil wide (p. 4-17 in the 1990 data book). Assuming these data
book dimensions are scribe to scribe, calculate (a) the Logic Module height, (b)
the channel height, and (c) the column (Logic Module) width.
Given that there are 25 tracks per horizontal channel, and 13 tracks per column in
the vertical direction, calculate (d) the horizontal channel track spacing and (e)
the vertical channel track spacing. (f) Using the fact that each output stub spans
two channels above and below the Logic Module, calculate the height of the
output stub.
We can now estimate the capacitance of the Logic Module stubs and
interconnect. Assume the interconnect capacitance is 0.2 pFmm 1 . (g) Calculate
the capacitance of an output stub and an input stub. (h) Calculate the width and
thus the capacitance of the horizontal tracks that are from four columns to 44
columns long.
You should not have to make any other assumptions to calculate these figures,
but if you do, state them clearly. The figures you have calculated are summarized
in Table 7.2 .
7.8 (Xilinx bank shots, 20 min.) Figure 7.11 shows a magic box. Explain how to
use a bank shot to enter one side of the box, bounce off another, and exit on a
third side. What is the delay involved in this maneuver?
FIGURE 7.11 A Xilinx magic box showing one set of
connections from connection 1 (Problem 7.8).
7.9 Bibliography
The paper by Greene et al. [1993] (reprinted in the 1994 Actel data book) is a
good description of the Actel interconnect. The 1995 AT&T data book contains a
very detailed account of the routing for the ORCA series of FPGAs, which is
similar to the Xilinx LCA interconnect. You can learn a great deal about the
details of the Lucent and Xilinx interconnect architecture from the AT&T data
book. The Xilinx data book gives a good high-level overview of SRAM-based
FPGA interconnect. The best way to learn about any FPGA interconnect is to use
the software tools provided by the vendor. The Xilinx XACT editor that shows
point-to-point routing delays on a graphical representation of the chip layout is an
easy way to become familiar with the interconnect properties. The book by
Brown et al. [ 1992] covers FPGA interconnect from a theoretical point of view,
concentrating on routing for LUT based FPGAs, and also describes specialized
routing algorithms for FPGAs.
7.10 References
Brown, S. D., et al. 1992. Field-Programmable Gate Arrays. Norwell, MA:
Kluwer Academic, 206 p. ISBN 0-7923-9248-5. TK7872.L64F54. Contents:
Introduction to FPGAs, Commercially Available FPGAs, Technology Mapping
for FPGAs, Logic Block Architecture, Routing for FPGAs, Flexibility of FPGA
Routing Resources, A Theoretical Model for FPGA Routing. Includes an
introduction to commercially available FPGAs. The rest of the book covers
research on logic synthesis for FPGAs and FPGA architectures, concentrating on
LUT-based architectures.
Greene, J., et al. 1993. Antifuse field programmable gate arrays. Proceedings of
the IEEE, vol. 81, no. 7, pp. 10421056, 1993. Review article describing the Actel
FPGAs. (Included in the Actel 1994 data book.)
Rubenstein, J., P. Penfield, and M. A. Horowitz. 1983. Signal delay in RC tree
networks. IEEE Transactions on CAD, vol. CAD-2, no. 3, July 1983, pp. 202
211. Derives bounds for the response of RC networks excited by an input step
voltage.
L ast E d ited by S P 1411 2 0 0 4
PROGRAMMABLE
ASIC DESIGN
SOFTWARE
There are five components of a programmable ASIC or FPGA: (1) the
programming technology, (2) the basic logic cell, (3) the I/O cell, (4) the
interconnect, and (5) the design software that allows you to program the ASIC.
The design software is much more closely tied to the FPGA architecture than is
the case for other types of ASICs.
8.1 Design Systems
The sequence of steps for FPGA design is similar to the sequence discussed in
Section 1.2 , Design Flow . As for any ASIC a designer needs design-entry
software, a cell library, and physical-design software. Each of the FPGA vendors
sells design kits that include all the software and hardware that a designer needs.
Many of these kits use design-entry software produced by a different company.
Often designers buy that software from the FPGA vendor. This is called an
original equipment manufacturer ( OEM ) arrangementsimilar to buying a car
with a stereo manufactured by an electronics company but labeled with the
automobile companys name. Design entry uses cell libraries that are unique to
each FPGA vendor. All of the FPGA vendors produce their own physical-design
software so they can tune the algorithms to their own architecture.
Unfortunately, there are no standards in FPGA design. Thus, for example, Xilinx
calls its 2:1 MUX an M2_1 with inputs labeled D0 , D1 , and S0 with output O .
Actel calls a 2:1 MUX an MX2 with inputs A , B , and S with output Y . This
problem is not peculiar to Xilinx and Actel; each ASIC vendor names its logic
cells, buffers, pads, and so on in a different manner. Consequently designers may
not be able to transfer a netlist using one ASIC vendor library to another. Worse
than this, designers may not even be able to transfer a design between two FPGA
families made by the same FPGA vendor!
One solution to the lack of standards for cell libraries is to use a generic cell
library, independent from any particular FPGA vendor. For example, most of the
FPGA libraries include symbols that are equivalent to TTL 7400 logic series
parts. The FPGA vendors own software automatically handles the conversion
from schematic symbols to the logic cells of the FPGA.
Schematic entry is not the only method of design entry for FPGAs. Some
designers are happier describing control logic and state machines in terms of state
diagrams and logic equations. A solution to some of the problems with schematic
entry for FPGA design is to use one of several hardware description languages (
HDL s) for which there are some standards. There are two sets of languages in
common use. One set has evolved from the design of programmable logic
devices (PLDs). The ABEL (pronounced able), CUPL (cupple), and PALASM
(pal-azzam) languages are simple and easy to learn. These languages are useful
for describing state machines and combinational logic. The other set of HDLs
includes VHDL and Verilog, which are higher-level and are more complex but
are capable of describing complete ASICs and systems.
After completing design entry and generating a netlist, the next step is simulation.
Two types of simulators are normally used for FPGA design. The first is a logic
simulator for behavioral, functional, and timing simulation. This tool can catch
any design errors. The designer provides input waveforms to the simulator and
checks to see that the outputs are as expected. At this point, using a
nondeterministic architecture, logic path delays are only estimates, since the
wiring delays will not be known until after physical design (place-and-route) is
complete. Designers then add or back-annotate the postlayout timing information
to the postlayout netlist (also called a back-annotated netlist). This is followed by
a postlayout timing simulation.
The second type of simulator, the type most often used in FPGA design, is a
timing-analysis tool. A timing analyzer is a static simulator and removes the need
for input waveforms. Instead the timing analyzer checks for critical paths that
limit the speed of operationsignal paths that have large delays caused, say, by a
high fanout net. Designers can set a certain delay restriction on a net or path as a
timing constraint; if the actual delay is longer, this is a timing violation. In most
design systems we can return to design entry and tag critical paths with attributes
before completing the place-and-route step again. The next time we use the
place-and-route software it will pay special attention to those signals we have
labeled as critical in order to minimize the routing delays associated with those
signals. The problem is that this iterative process can be lengthy and sometimes
nonconvergent. Each time timing violations are fixed, others appear. This is
especially a problem with place-and-route software that uses random algorithms
(and forms a chaotic system). More complex (and expensive) logic synthesizers
can automate this iterative stage of the design process. The critical path
information is calculated in the logic synthesizer, and timing constraints are
created in a feedforward path (this is called forward-annotation ) to direct the
place-and-route software.
Although some FPGAs are reprogrammable, it is not a good idea to rely on this
fact. It is very tempting to program the FPGA, test it, make changes to the netlist,
and then keep programming the device until it works. This process is much more
time consuming and much less reliable than performing thorough simulation. It is
quite possible, for example, to get a chip working in an experimental fashion
without really knowing why. The danger here is that the design may fail under
some other set of operating conditions or circumstances. Simulation is the proper
way to catch and correct these potential disasters.
8.1.1 Xilinx
Figure 8.1 shows the Xilinx design system. Using third-party design-entry
software, the designer creates a netlist that forms the input to the Xilinx software.
Utility software ( pin2xnf for FutureNet DASH and wir2xnf for Viewlogic, for
example) translate the netlist into a Xilinx netlist format ( XNF ) file. In the next
step the Xilinx program xnfmap takes the XNF netlist and maps the logic into the
Xilinx Logic Cell Array ( LCA ) architecture. The output from the mapping step
is a MAP file. The schematic MAP file may then be merged with other MAP files
using xnfmerge . This technique is useful to merge different pieces of a design,
some created using schematic entry and others created, for example, using logic
synthesis. A translator program map2lca translates from the logic gates (NAND
gates, NOR gates, and so on) to the required CLB configurations and produces an
unrouted LCA file. The Xilinx place-and-route software ( apr or ppr ) takes the
unrouted LCA file and performs the allocation of CLBs and completes the
routing. The result is a routed LCA file. A control program xmake (that works
like the make program in C) can automatically handle the mapping, merging, and
place-and-route steps. Following the place-and-route step, the logic and wiring
delays are known and the postlayout netlist may be generated. After a postlayout
simulation the download file or BIT file used to program the FPGA (or a PROM
that will load the FPGA) is generated using the Xilinx makebits program.
FIGURE 8.1 The Xilinx FPGA design flow. The numbers next to the steps in
the flow correspond to those in the general ASIC design flow of Figure 1.10 .
Xilinx also provides a software program (Xilinx design editor, XDE) that permits
manual control over the placement and routing of a Xilinx FPGA. The designer
views a graphical representation of the FPGA, showing all the CLBs and
interconnect, and can make or alter connections by pointing and clicking. This
program is useful to check an automatically generated layout, or to explore
critical routing paths, or to change and hand tune a critical connection, for
example.
Xilinx uses a system called X-BLOX for creating regular structures such as
vectored instances and datapaths. This system works with the Xilinx XNF netlist
format. Other vendors, notably Actel and Altera, use a standard called
Relationally Placed Modules ( RPM ), based on the EDIF standard, that ensures
that the pieces of an 8-bit adder, for example, are treated as a macro and stay
together during placement.
8.1.2 Actel
Actel FPGA design uses third-party design entry and simulators. After creating a
netlist, a designer uses the Actel software for the place-and-route step. The Actel
design software, like other FPGA and ASIC design systems, employs a large
number of file formats with associated filename extensions. Table 8.1 shows
some of the Actel file extensions and their meanings.
TABLE 8.1 File types used by Actel design software.
ADL
Main design netlist
IPF
Partial or complete pin assignment for the design
CRT
Net criticality
VALIDATED Audit information
COB
List of macros removed from design
VLD
Information, warning, and error messages
PIN
Complete pin assignment for the design
DFR
Information about routability and I/O assignment quality
Placement of non-I/O macros, pin swapping, and freeway
LOC
assignment
PLI
Feedback from placement step
SEG
Assignment of horizontal routing segments
STF
Back-annotation timing
RTI
Feedback from routing step
FUS
Fuse coordinates (column-track, row-track)
DEL
Delays for input pins, nets, and I/O modules
AVI
Fuse programming times and currents for last chip programmed
Actel software can also map hardware description files from other programmable
logic design software into the Actel FPGA architecture. As an example, Table 8.2
shows a text description of a state machine using an HDL from a company called
LOG/iC. You can then convert the LOG/iC code to the PALASM code shown in
Table 8.2 . The Actel software can take the PALASM code and merge it with
other PALASM files or netlists.
TABLE 8.2 FPGA state-machine language.
LOG/iC state-machine language
PALASM version
*IDENTIFICATION
sequence detector
LOG/iC code
*X-NAMES
X; !input
*Y-NAMES
D; !output, D = 1 when three 1's appear on X
*FLOW-TABLE
TITLE sequence detector
;State, X input, Y output, next state
CHIP MEALY USER
S1, X1, Y0, F2;
CLK Z QQ2 QQ1 X
S1, X0, Y0, F1;
EQUATIONS
S2, X1, Y0, F3;
Z = X * QQ2 * QQ1
S2, X0, Y0, F1;
QQ2 := X * QQ1 + X * QQ2
S3, X1, Y0, F4;
QQ1 := X * QQ2 + X * /QQ1
S3, X0, Y0, F1;
S4, X1, Y1, F4;
S4, X0, Y0, F1;
*STATE-ASSIGNMENT
BINARY;
*RUN-CONTROL
PROGFORMAT = P-EQUATIONS;
*END
8.1.3 Altera
Altera uses a self-contained design system for its complex PLDs that performs
design entry, simulation, and programming of the parts. Altera also provides an
input and output interface to EDIF so that designers may use third-party
schematic entry or a logic synthesizer. We have seen that the interconnect
scheme in the Altera complex PLDs is nearly deterministic, simplifying the
physical-design software as well as eliminating the need for back-annotation and
a postlayout simulation. As Altera FPGAs become larger and more complex,
there are some exceptions to this rule. Some special cases require signals to make
more than one pass through the routing structures or travel large distances across
the Altera FastTrack interconnect. It is possible to tell if this will be the case only
by trying to place and route an Altera device.
8.2 Logic Synthesis
Designers are increasingly using logic synthesis as a replacement for schematic
entry. As microelectronic systems and their ASICs become more complex, the
use of schematics becomes less practical. For example, a complex ASIC that
contains over 10,000 gates might require hundreds of pages of schematics at the
gate level. As another example, it is easier to write A = B + C than to draw a
schematic for a 32-bit adder at the gate level.
The term logic synthesis is used to cover a broad range of software and software
capabilities. Many logic synthesizers are based on logic minimization. Logic
minimization is usually performed in one of two ways, either using a set of rules
or using algorithms. Early logic-minimization software was designed using
algorithms for two-level logic minimization and developed into multilevel
logic-optimization software. Two-level and multilevel logic minimization is well
suited to random logic that is to be implemented using a CBIC, MGA, or PLD. In
these technologies, two-level logic can be implemented very efficiently. Logic
minimization for FPGAs, including complex PLDs, is more difficult than other
types of ASICs, because of the complex basic logic cells in FPGAs.
There are two ways to use logic synthesis in the design of FPGAs. The first and
simplest method takes a hardware description, optimizes the logic, and then
produces a netlist. The netlist is then passed to software that maps the netlist to an
FPGA architecture. The disadvantage of this method is the inefficiency of
decoupling the logic optimization from the mapping step. The second, more
complicated, but more efficient method, takes the hardware description and
directly optimizes the logic for a specific FPGA architecture.
Some logic synthesizers produce files in PALASM, ABEL, or CUPL formats.
Software provided by the FPGA vendor then take these files and maps the logic
to the FPGA architecture. The FPGA mapping software requires detailed
knowledge of the FPGA architecture. This makes it difficult for third-party
companies to create logic synthesis software that can map directly to the FPGA.
A problem with design-entry systems is the difficulty of moving netlists between
different FPGA vendors. Once you have completed a design using an FPGA cell
library, for example, you are committed to using that type of FPGA unless you
repeat design entry using a different cell library. ASIC designers do not like this
approach since it exposes them to the mercy of a single ASIC vendor. Logic
synthesizers offer a degree of independence from FPGA vendors (universally
referred to vendor independence, but this should, perhaps, be designer
independence) by delaying the point in the design cycle at which designers need
to make a decision on which FPGA to use. Of course, now designers become
dependent on the synthesis software company.
8.2.1 FPGA Synthesis
For low-level logic synthesis, PALASM is a de facto standard as the
lowest-common-denominator interchange format. Most FPGA design systems are
capable of converting their own native formats into a PALASM file. The most
common programmable logic design systems are ABEL from Data I/O, CUPL
from P-CAD, LOG/iC from IsData, PALASM2 from AMD, and PGA-Designer
from Minc. At a higher level, CAD companies (Cadence, Compass, Mentor, and
Synopsys are examples) support most FPGA cell libraries. This allows you to
map from a VHDL or Verilog description to an EDIF netlist that is compatible
with FPGA design software. Sometimes you have to buy the cell library from the
software company, sometimes from the FPGA vendor.
TABLE 8.3 The VHDL code for the sequence detector of Table 8.2 .
entity detector is port (X, CLK: in BIT; Z : out BIT); end;
architecture behave of SEQDET is
type STATES is (S1, S2, S3, S4);
signal current, next: STATES;
begin
combinational: process begin
case current is
when S1 =>
if X = '1' then Z <= '0'; next <= S3; else Z <= '0'; next <= S1; end if;
when S2 =>
if X = '1' then Z <= '0'; next <= S2; else Z <= '0'; next <= S1; end if;
when S3 =>
if X = '1' then Z <= '0'; next <= S2; else Z <= '0'; next <= S1; end if;
when S4 =>
if X = '1' then Z <= '1'; next <= S4; else Z <= '0'; next <= S1; end if
end case;
end process
sequential: process begin
wait until CLK'event and CLK = '1'; current <= next ;
end process;
end behave;
As an example, Table 8.3 shows a VHDL model for a pattern detector to check
for a sequence of three '1's (excluding the code for the I/O pads). Table 8.4 shows
a script or command file that runs the Synopsys software to generate an EDIF
netlist from this VHDL that targets the TI version of the Actel FPGA parts. A
script is a recipe that tells the software what to do. If we wanted to retarget this
design to another type of FPGA or an MGA or CBIC ASIC, for example, we may
only need a new set of cell libraries and to change the script (if we are lucky). In
practice, we shall probably find we need to make a few changes in the VHDL
code (in the areas of I/O pads, for example, that are different for each kind of
ASIC). We now have a portable design and a measure of vendor independence.
We have also introduced some dependence on the Synopsys software since the
code in Table 8.3 might be portable, but the script (which is just as important a
part of the design) in Table 8.4 may only be used with the Synopsys software.
Nevertheless, using logic synthesis results in a more portable design than using
schematic entry.
TABLE 8.4 The Synopsys script for the VHDL code of Table 8.3 .
report_design > detector.rpt
/design checking/
search_path = .
/optimize for area/
/use the TI cell libraries/
max_area 0.0
link_library = tpc10.db
compile
target_library = tpc10.db
write -h -f db -o detector_opt.db
symbol_library = tpc10.sdb
report -area -cell -timing > detector.rpt
read -f vhdl detector.vhd
free -all
current_design = detector
/write EDIF netlist/
write -n -f db -hierarchy -0 detector.db write -h -f edif -0
check_design > detector.rpt
exit
8.3 The Halfgate ASIC
This section illustrates FPGA design using a very simple ASICa single inverter. The hidden details of the design
and construction of this halfgate FPGA are quite complicated. Fortunately, most of the inner workings of the
design software are normally hidden from the designer. However, when software breaks, as it sometimes does, it is
important to know how things work in order to fix the problem. The formats, filenames, and flow will change, but
the information needed at each stage and the order in which it is conveyed will stay much the same.
8.3.1 Xilinx
Table 8.5 shows an FPGA design flow using Compass and Xilinx software. On the left of Table 8.5 is a script for
the Compass programsscripts for Cadence, Mentor, and Synopsys software are similar, but not all design software
has the capability to be run on autopilot using scripts and a command language. The diagrams in Table 8.5
illustrate what is happening at each of the design steps. The following numbered comments, corresponding to the
labels in Table 8.5 , highlight the important steps:
TABLE 8.5 Design flow for the Xilinx implementation of the halfgate ASIC.
Script
Design flow
#
halfgate.xilinx.inp
shell setdef
path working
xc4000d xblox
cmosch000x
quit
asic
open [v]halfgate
synthesize
save
[nls]halfgate_p
quit
fpga
set tag xc4000
set opt area
optimize
[nls]halfgate_p
quit
qtv
open
[nls]halfgate_p
trace critical
print trace
[txt]halfgate_p
quit
shell vuterm
exec xnfmerge -p
4003PC84
halfgate_p >
/dev/null
exec xnfprep
halfgate_p >
/dev/null
exec ppr
halfgate_p >
/dev/null
exec makebits -w
halfgate_p >
/dev/null
exec lca2xnf -g -v
halfgate_p
halfgate_b >
/dev/null
quit
manager notice
utility netlist
open
[xnf]halfgate_b
save
[nls]halfgate_b
save
[edf]halfgate_b
quit
qtv
open
[nls]halfgate_b
trace critical
print trace
[txt]halfgate_b
quit
TABLE 8.6 The Xilinx files for the halfgate ASIC.
Verilog file (halfgate.v)
Preroute XNF file (halfgate_p.xnf)
LCA file (halfgate_p.lca)
Postroute XNF file (halfgate_b.xnf)
1. The Verilog code, in halfgate.v , describes a single inverter.
2. The script runs the logic synthesizer that converts the Verilog description to an inverter (using elements
from the Xilinx XC4000 library) and saves the result in a netlist, halfgate_p.nls (a Compass internal format).
3. The script next runs the logic optimizer for FPGAs. This program also adds the I/O pads. In this case, logic
optimization implements the inverter by using an inverting output pad. The software writes out the netlist as
halfgate_p.xnf .
4. A timing simulation is run on the netlist halfgate_p.nls (the Compass format netlist). This netlist uses the
default delaysevery gate has a delay of 1 ns.
5. At this point the script has run all of the Xilinx programs required to complete the place-and-route step. The
Xilinx programs have created several files, the most important of which is halfgate_p.lca , which describes
the FPGA layout. This postroute netlist is converted to halfgate_b.nls (the added suffix 'b' stands for
back-annotation). Next a timing simulation is performed on the postroute netlist, which now includes
delays, to find the delay from the input ( myInput ) to the output ( myOutput ). This is the criticaland only
path. The simulation (not shown) reveals that the delay is 2.8 ns (for the input buffer) plus 11.6 ns (for the
output buffer), for a total delay of 14.4 ns (this is for a XC4003 in a PC84 package, and default speed grade
'4').
Table 8.6 shows the key Xilinx files that are created. The preroute file, halfgate_p.xnf , describes the IBUF and
OBUF library cells but does not contain any delays. The LCA file, halfgate_p.lca , contains all the physical design
information, including the locations of the pads and I/O cells on the FPGA ( PAD61 for myInput and PAD1 for
myOutput ), as well as the details of the programmable connections between these I/O Cells. The postroute file,
halfgate_b.xnf , is similar to the preroute version except that now the delays are included. Xilinx assigns delays to
a pin (connector or terminal of a cell). In this case 2.8 ns is assigned to the output of the input buffer, 8.6 ns is
assigned to the input of the output buffer, and finally 3.0 ns is assigned to the output of the output buffer.
8.3.2 Actel
The key Actel files for the halfgate design are the netlist file, halfgate_io.adl, and the STF delay file for
back-annotation, halfgate_io.stf. Both of these files are shown in Table 8.7 (the STF file is large and only the last
few lines, which contain the delay information, are shown in the table).
TABLE 8.7 The Actel files for the halfgate ASIC.
ADL file
STF file
; HEADER
; FILEID STF ./halfgate_io.stf c96ef4d8
... lines omitted ... (126 lines total)
; HEADER
; FILEID ADL ./halfgate_io.adl 85e8053b
DEF halfgate_io.
; CHECKSUM 85e8053b
USE ; INBUF_2/U0;
; PROGRAM certify
TPADH:'11:26:37',
; VERSION 23/1
TPADL:'13:30:41',
; ALSMAJORREV 2
TPADE:'12:29:41',
; ALSMINORREV 3
TPADD:'20:48:70',
; ALSPATCHREV .1
TYH:'8:20:27',
; NODEID 72705192
TYL:'12:28:39'.
; VAR FAMILY 1400
PIN u2:A;
; ENDHEADER
RDEL:'13:31:42',
DEF halfgate_io; myInput, myOutput.
FDEL:'11:26:37'.
USE ADLIB:INBUF; INBUF_2.
USE ; OUTBUF_3/U0;
USE ADLIB:OUTBUF; OUTBUF_3.
TPADH:'11:26:37',
USE ADLIB:INV; u2.
TPADL:'13:30:41',
NET DEF_NET_8; u2:A, INBUF_2:Y.
TPADE:'12:29:41',
NET DEF_NET_9; myInput, INBUF_2:PAD.
TPADD:'20:48:70',
NET DEF_NET_11; OUTBUF_3:D, u2:Y.
TYH:'8:20:27',
NET DEF_NET_12; myOutput, OUTBUF_3:PAD.
TYL:'12:28:39'.
END.
PIN OUTBUF_3/U0:D;
RDEL:'14:32:45',
FDEL:'11:26:37'.
END.
8.3.3 Altera
Because Altera complex PLDs use a deterministic routing structure, they can be designed more easily using a
self-contained software packagean all-in-one software package using a single interface. We shall assume that we
can generate a netlist that the Altera software can accept using Cadence, Mentor, or Compass software with an
Altera design kit (the most convenient format is EDIF).
Table 8.8 shows the EDIF preroute netlist in a format that the Altera software can accept. This netlist file describes
a single inverter (the line 'cellRef not'). The majority of the EDIF code in Table 8.8 is a standard template to pass
information about how the VDD and VSS nodes are named, which libraries are used, the name of the design, and
so on. We shall cover EDIF in Chapter 9 .
TABLE 8.8 EDIF netlist in Altera format for the halfgate ASIC.
Table 8.9 shows a small part of the reports generated by the Altera software after completion of the
place-and-route step. This report tells us how the software has used the basic logic cells, interconnect, and I/O
cells to implement our design. With practice it is possible to read the information from reports such as Table 8.9
directly, but it is a little easier if we also look at the netlist. The EDIF version of postroute netlist for this example
is large. Fortunately, the Altera software can also generate a Verilog version of the postroute netlist. Here is the
generated Verilog postroute netlist, halfgate_p.vo (not '.v' ), for the halfgate design:
TABLE 8.9 Report for the halfgate ASIC fitted to an Altera MAX 7000 complex PLD.
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT 0 0 0 0 0 0 1 myInput
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
41 17 B OUTPUT t 0 0 0 1 0 0 0 myOutput
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
+- LC17 myOutput
|
LC | | A B | Name
Pin
43 -> * | - * | myInput
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
// halfgate_p (EPM7032LC44) MAX+plus II Version 5.1 RC6 10/03/94
// Wed Jul 17 04:07:10 1996
`timescale 100 ps / 100 ps
module TRI_halfgate_p( IN, OE, OUT ); input IN; input OE; output OUT;
bufif1 ( OUT, IN, OE );
specify
specparam TTRI = 40; specparam TTXZ = 60; specparam TTZX = 60;
(IN => OUT) = (TTRI,TTRI);
(OE => OUT) = (0,0, TTXZ, TTZX, TTXZ, TTZX);
endspecify
endmodule
module halfgate_p (myInput, myOutput);
input myInput; output myOutput; supply0 gnd; supply1 vcc;
wire B1_i1, myInput, myOutput, N_8, N_10, N_11, N_12, N_14;
TRI_halfgate_p tri_2 ( .OUT(myOutput), .IN(N_8), .OE(vcc) );
TRANSPORT transport_3 ( N_8, N_8_A );
defparam transport_3.DELAY = 10;
and delay_3 ( N_8_A, B1_i1 );
xor xor2_4 ( B1_i1, N_10, N_14 );
or or1_5 ( N_10, N_11 );
TRANSPORT transport_6 ( N_11, N_11_A );
defparam transport_6.DELAY = 60;
and and1_6 ( N_11_A, N_12 );
TRANSPORT transport_7 ( N_12, N_12_A );
defparam transport_7.DELAY = 40;
not not_7 ( N_12_A, myInput );
TRANSPORT transport_8 ( N_14, N_14_A );
defparam transport_8.DELAY = 60;
and and1_8 ( N_14_A, gnd );
endmodule
The Verilog model for our ASIC, halfgate_p , is written in terms of other models: and , xor , or , not ,
TRI_halfgate_p , TRANSPORT . The first four of these are primitive models for basic logic cells and are built into
the Verilog simulator. The model for TRI_halfgate_p is generated together with the rest of the code. We also need
the following model for TRANSPORT, which contains the delay information for the Altera MAX complex PLD.
This code is part of a file ( alt_max2.vo ) that is generated automatically.
// MAX+plus II Version 5.1 RC6 10/03/94 Wed Jul 17 04:07:10 1996
`timescale 100 ps / 100 ps
module TRANSPORT( OUT, IN ); input IN; output OUT; reg OUTR;
wire OUT = OUTR; parameter DELAY = 0;
`ifdef ZeroDelaySim
always @IN OUTR <= IN;
`else
always @IN OUTR <= #DELAY IN;
`endif
`ifdef Silos
initial #0 OUTR = IN;
`endif
endmodule
The Altera software can also write the following VHDL postroute netlist:
-- halfgate_p (EPM7032LC44) MAX+plus II Version 5.1 RC6 10/03/94
-- Wed Jul 17 04:07:10 1996
LIBRARY IEEE; USE IEEE.std_logic_1164.all;
ENTITY n_tri_halfgate_p IS
GENERIC (ttri: TIME := 1 ns; ttxz: TIME := 1 ns; ttzx: TIME := 1 ns);
PORT (in0 : IN X01Z; oe : IN X01Z; out0: OUT X01Z);
END n_tri_halfgate_p;
ARCHITECTURE behavior OF n_tri_halfgate_p IS
BEGIN
PROCESS (in0, oe) BEGIN
IF oe'EVENT THEN
IF oe = '0' THEN out0 <= TRANSPORT 'Z' AFTER ttxz;
ELSIF oe = '1' THEN out0 <= TRANSPORT in0 AFTER ttzx;
END IF;
ELSIF oe = '1' THEN out0 <= TRANSPORT in0 AFTER ttri;
END IF;
END PROCESS;
END behavior;
LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.n_tri_halfgate_p;
ENTITY n_halfgate_p IS
PORT ( myInput : IN X01Z; myOutput : OUT X01Z);
END n_halfgate_p;
ARCHITECTURE EPM7032LC44 OF n_halfgate_p IS
SIGNAL gnd : X01Z := '0'; SIGNAL vcc : X01Z := '1';
SIGNAL n_8, B1_i1, n_10, n_11, n_12, n_14 : X01Z;
COMPONENT n_tri_halfgate_p
GENERIC (ttri, ttxz, ttzx: TIME);
PORT (in0, oe : IN X01Z; out0 : OUT X01Z);
END COMPONENT;
BEGIN
PROCESS(myInput) BEGIN ASSERT myInput /= 'X' OR Now = 0 ns
REPORT "Unknown value on myInput" SEVERITY Warning;
END PROCESS;
n_tri_2: n_tri_halfgate_p
GENERIC MAP (ttri => 4 ns, ttxz => 6 ns, ttzx => 6 ns)
PORT MAP (in0 => n_8, oe => vcc, out0 => myOutput);
n_delay_3: n_8 <= TRANSPORT B1_i1 AFTER 1 ns;
n_xor_4: B1_i1 <= n_10 XOR n_14;
n_or_5: n_10 <= n_11;
n_and_6: n_11 <= TRANSPORT n_12 AFTER 6 ns;
n_not_7: n_12 <= TRANSPORT NOT myInput AFTER 4 ns;
n_and_8: n_14 <= TRANSPORT gnd AFTER 6 ns;
END EPM7032LC44;
LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.n_halfgate_p;
ENTITY halfgate_p IS
PORT ( myInput : IN std_logic; myOutput : OUT std_logic);
END halfgate_p;
ARCHITECTURE EPM7032LC44 OF halfgate_p IS
COMPONENT n_halfgate_p PORT (myInput : IN X01Z; myOutput : OUT X01Z);
END COMPONENT;
BEGIN
n_0: n_halfgate_p
PORT MAP ( myInput => TO_X01Z(myInput), myOutput => myOutput);
END EPM7032LC44;
The VHDL is a little harder to decipher than the Verilog, so the schematic for the VHDL postroute netlist is shown
in Figure 8.2 . This VHDL netlist is identical in function to the Verilog netlist, but the net names and component
names are different. Compare Figure 8.2 with Figure 5.15 (c) in Section 5.4 , Altera MAX , which shows the
Altera basic logic cell and Figure 6.23 in Section 6.8, Other I/O Cells, which describes the Altera I/O cell. The
software has fixed the inputs to the various elements in the Altera MAX device to implement a single inverter.
FIGURE 8.2 The VHDL version of the postroute Altera MAX 7000 schematic for the halfgate ASIC. Compare
this with Figure 5.15(c) and Figure 6.23.
8.3.4 Comparison
The halfgate ASIC design illustrates the differences between a nondeterministic coarse-grained FPGA (Xilinx
XC4000), a nondeterministic fine-grained FPGA (Actel ACT 3), and a deterministic complex PLD (Altera MAX
7000). These differences, summarized as follows, were apparent even in the halfgate design:
1. The Xilinx LCA architecture does not permit an accurate timing analysis until after place and route. This is
because of the coarse-grained nondeterministic architecture.
2. The Actel ACT architecture is nondeterministic, but the fine-grained structure allows fairly accurate
preroute timing prediction.
3. The Altera MAX complex PLD requires logic to be fitted to the product steering and programmable array
logic. The Altera MAX 7000 has an almost deterministic architecture, which allows accurate preroute
timing.
8.4 Summary
The important concepts covered in this chapter are:
● FPGA design flow: design entry, simulation, physical design, and
programming
● Schematic entry, hardware design languages, logic synthesis
● PALASM as a common low-level hardware description
● EDIF, Verilog, and VHDL as vendor-independent netlist standards
8.5 Problems
* = Difficult, ** = Very difficult, *** = Extremely difficult
8.1 (Files, 60 min.) Create a version of Table 8.1 for your design system.
8.2 (Scripts, 60 min.) Create a version of Table 8.5 for your design system.
8.3 (Halfgate, 60 min.)
● a. Using an FPGA of your choice, estimate the preroute delay of a single
inverter (including I/O delays).
● b. Complete a halfgate design and explain the postroute delays (make sure
you know what conditions are being usedworst-case commercial, for
example).
8.4 (***Xilinx die analysis, 120 min.) The data in Table 8.10 shows some
information derived from a die photo of an ATT3020 (equivalent to a Xilinx
3020) in the AT&T data book. The die photo shows the CLBs clearly enough that
we can measure their size. Then, knowing the actual die size, we can calculate
the CLB size and other parameters. From your knowledge of the contents of the
XC3020 CLB, as well as the programming and interconnect structures, make an
estimate (showing all of your approximations and explaining all of your
assumptions) of the CLB area and compare this to the value of 277 mils 2 shown
in Table 8.10 . You will need to calculate the number of logic gates in each CLB
including the LUT resources. Estimate how many pass transistors and memory
elements are required as well as calculate how many routing resources are
assigned to each CLB. Hint: You may need to use the Xilinx software, look at the
Xilinx data books, or even the AT&T (Lucent) Orca documentation.
TABLE 8.10 ATT3020 die information (Problem 8.4).
Specified in data Measured on die
Calculated from die
Parameter
book
photo
photo
3020 die width 183.5 mil
4.1 cm
3020 die height 219.3 mil
4.9 cm
3000 CLB width
0.325 cm
14.55 mil = 370 m m
3000 CLB height
0.425 cm
19.02 mil = 483 m m
3000 CLB area
277 mils 2
3020 pad pitch
1.61 mm/pad
7.21 mil/pad
Source: AT&T Data Book, July 1992, p. 3-76, MN92-024FPGA.
8.5 (***FPGA process, 120 min.) Table 8.11 describes AT&Ts 0.9 m m
twin-tub V CMOS process, with 0.75 m m minimum design rules and 0.6 m m
effective channel length and silicided (TiS 2 ) poly, source, and drain. This is the
process used by AT&T to second-source the Xilinx XC3000 family of FPGAs.
Calculate the parasitic resistance and capacitance parameters for the interconnect.
TABLE 8.11 ATT3000 0.9 m m twin-tub V CMOS process (Problem 8.5).
Parameter
Value
Die thickness, t die
21 mil
Wafer diameter, W D
5 inch
Wafer thickness, W t
25 mil
Minimum feature size, 2 l
0.75 m m
Effective gate length, L eff ( n -channel and p -channel)
0.6 m m
First-level metal, m1
Ti/AlCuSi
Second-level metal, m2
AlCuSi
m1 width
0.9 m m
m2 width
1.2 m m
m1 thickness
0.5 m m
m2 thickness
1.0 m m
m1 spacing
1.0 m m
m2 spacing
1.3 m m
D1 dielectric thickness, boron/phosphorus doped glass
3500 Å
D2 dielectric thickness, undoped glass
9000 Å
Minimum contact size
1.0 m m
Minimum via size
1.2 m m
Isolation oxide, FOX
3500 Å
Gate oxide
150 Å
Source: AT&T Data Book, July 1992, p. 2-37 and p. 3-76, MN92-024FPGA.
8.6 (Xilinx die costs, 10 min.) Table 8.12 shows the AT&T ATT3000 series die
information. Assume a 6-inch wafer that costs $2000 to fabricate and has a 90
percent yield. (a) What are the die costs? (b) Compare these figures to the costs
of XC3020 parts in 1992 and comment.
TABLE 8.12 ATT3000 die information (Problem 8.6).
Die
Die
Die
Die area
Die height
area
CLBs
width
/mils 2
/mils
/cm2
/mils
3020 219.3
183.5
40,242
0.26
8¥8
3030 259.8
215.0
55,857
0.36
10 ¥ 10
3042 295.3
242.5
71,610
0.46
12 ¥ 12
Die perimeter I/O
/mils
pads
806
950
1076
74
98
118
3064 270.9
366.5
99,285
0.64
16 ¥ 14 1275
142
3090 437.0
299.2
130,750
0.84
16 ¥ 20 1472
166
Source: AT&T Data Book, July 1992, p. 3-75, MN92-024FPGA. 1 mil 2 = 2.54 2
¥ 10 6 cm 2 = 6.452 ¥ 10 6 cm 2 .
8.7 (Pad density) Table 8.12 shows the number of pads on each of the
AT&T 3000 (equivalent to the Xilinx XC3000) die. Calculate the pad densities in
mil/pad for each part and compare with the figure for the ATT3020 in Table 8.10
.
8.8 (Xilinx HardWire, 10 min.) Xilinx manufactures nonprogrammable versions
of its LCA family of FPGAs. These HardWire chips are useful when a customer
wishes to convert to high-volume production. The Xilinx 1996 Product overview
(p. 16) shows two die photographs: one, an XC3090 (with the four quadrants of 8
¥ 10 CLB matrices visible), which is 32 mm ¥ 47 mm; the other shows the
HardWire version (24 mm ¥ 29 mm). Estimate the die size of the HardWire
version from the data in Table 8.12 and estimate the percentage of a Xilinx LCA
that is taken up by SRAM.
Answer: 60,500 mils 2 ; 50 %.
8.9 (Xilinx XDE, 10 min.) During his yearly appraisal Dewey explains to you
how he improved three Xilinx designs last year and managed to use 100 percent
of the CLBs on these LCA chips by means of the XDE manual place-and-route
program. As Deweys boss, rank Dewey from 1 (bad) to 5 (outstanding) and
explain your ranking in a space that has room for no more than 20 words.
8.10 (Clocks, 60 min) (From a discussion on an Internet newsgroup including
comments from Peter Alfke of Xilinx) Xilinx guarantees that the minimum value
for any delay parameter is always more than 25 % of the maximum value for that
same parameter, as published for the fastest speed grade offered at any time.
Many parameters have been reduced significantly over the years, but the clock
delay has not. For example, comparing the fastest available XC3020-70 in 1988
with the fastest available XC3020A-6 (1996):
● logic delay ( t ILO ) decreased from 9 ns to 4.1 ns
●
●
output-to-pad delay decreased from 10 ns to 5 ns
internal-clock-to-output pad delay decreased from 13 ns to 7 ns
The internal speed has more than doubled, but the worst-case clock distribution
delay specification has only changed from 6.0 ns (1988) to 5.7 ns (1996).
Comment on the reasons for these changes and their repercussions.
8.11 (State-machine design)
● a. (10 min.) Draw the state diagram for the LOG/iC code in Table 8.2 .
●
b. (10 min.) Show, using an example input sequence, that the detector
●
●
●
works.
c. (10 min.) Show that the state equations and the encoding for the
PALASM code in Table 8.2 correctly describe the sequence detector state
machine.
d. (30 min.) Convert this design to a different format of your choice:
schematic, low-level design language, or HDL.
e. (30 min.) Simulate and test your design.
8.12 (FPGA software, 60 min.) Write a minitutorial (less than 2 pages) on using
your FPGA design system. An example set of instructions for the Altera
MAX PLUS II software on a Unix system are shown below:
Setup:
1. Copy ~altera/M+2/maxplus2.ini into ~you/yourDirectory (call this the
working directory).
2. Edit maxplus2.ini and point the DESIGN_NAME to your design
3. Copy ~altera/M+2/compass.lmf and ~altera/M+2/compass.edc into your
working directory.
4. Copy ~altera/M+2/foo.acf into your working directory and rename it
mydesign.acf if your design name is mydesign.edf .
5. Set the environment as follows:
setenv LM_LICENSE_FILE ~altera/maxplus2/adm/license.altera
set path=($path ~altera/maxplus5.1/bin)
and run the programs in batch mode: maxplus2 -c mydesign.edf . Add to this
information on any peculiarities of the system you are using (handling of
overwriting of files, filename extensions and when they are created, arguments
required to run the programs, and so on).
8.13 (Help, 20 min.) Print the help for the key programs in your FPGA system
and form it into a condensed cheat-sheet. Most programs echo help instruction
when called with a '-help' or '?' argument (this ought to be a standard). For
example, in the Actel system the key programs are edn2adl, adl2edn, and als (in
newer versions adl2edn is now an option to als). Hint: Actel does not use '-help'
argument, but you can get instructions on the syntax for each option individually.
Table 8.13 shows an example for the Xilinx xdelay program.
TABLE 8.13 Xilinx xdelay arguments.
usage: xdelay [<options>] [<lcafile> ..]
where <options> are:
-help Print this help.
-timespec Do timespec based delay analysis.
-s Write short xdelay report.
-x Write long xdelay report.
-t <template file> Read <template file>.
-r Use two letter style block names in output.
-o <file> Send output to file.
-w Write design file, after retiming net delays.
-u <speed> Use the <speed> speed grade.
-d Don't trace delay paths.
-convert <input .lca file> <new part type> <output .lca file>
Convert the input design to a new part type.
Specify no arguments to run xdelay in interactive mode.
To Select Report Specify Option
------------------------- --------------------------TimeSpec summary -timespec
Short path details -s
Long path details -x
Analyze summary none of -s, -x or -timespec
A template file can be specified with the -t option to further filter the selected
report. Only those template commands relevant to the selected report will be
used.
Using -w and -d options together will insert delay information into the design
file(s), without tracing any paths.
The -convert option may not be used with any other options.
8.6 Bibliography
There are few books on FPGA design software. Skahills book [1996] covers
PLD and FPGA design with Cypress FPGAs and the Cypress Warp design
system. Connor has written two articles in EDN describing a complete FPGA
design project [1992]. Most of the information on design software is available
from the software companies themselvesincreasingly in online form. There is
still some material that is only available through the BBS or from a file-transfer
protocol (ftp) site. There is also a great deal of valuable material available in data
books printed between 1990 and 1995, prior to the explosion of the use of the
Internet in the late-1990s. I have included pointers to these sources in the
following sections.
8.6.1 FPGA Vendors
Actel ( http://www.actel.com ) has a Frequently Asked Questions ( FAQ ) guide
that is an indication of the most common problems with FPGA design:
● Software versions, installation, and security, and not having enough
computer memory
● X11, Motif, and OpenWindowsproblems with paths and fonts.
Compatibility problems with Windows 95 and NT
● Including I/O pads in a design using schematic entry and logic synthesis
problems with the commands and the exact syntax to use
● Using third-party software for schematic entry or logic synthesis and
librariesproblems with versions and paths
● EDIF netlist issues
It seems most of these problems never go awaythey just keep resurfacing. If you
design a halfgate ASIC, an inverter, start-to-finish, as soon as you get a new set
of software, this will alert you to most of the problems you are likely to
encounter.
The May 1989 Actel data book contains details of the early antifuse experiments.
The Actel April 1990 data book has a chip photo of the Actel 1010 on the cover
(from which some useful information may be derived). Reliability reports and
article reprints are now included in the data books (see, for example, [Actel,
1996]). There is PowerPoint presentation on FPGAs ( architec.exe ) and the Actel
FPGA architecture at its Web site.
The Xilinx data book (see, for example, [Xilinx, 1996]) contains several hundred
pages of information on LCA parts. Xilinx produced a separate User Guide and
Tutorials book that contains over 600 pages of application notes, guides, and
tutorials on designing with FPGAs and Xilinx FPGAs in particular. XCELL is
the quarterly Xilinx Newsletter, first published in 1988. It is available online and
contains useful tips and pointers to new application notes. There is an extensive
set of Xilinx Application Notes at http://www.xilinx.com/apps . A 250 -page
guide to using the Synopsys software ( hdl_dg.pdf ) covers many of the problems
users experience in using any logic synthesizer for FPGA design.
Xilinx provides design kits for its EPLD FPGAs for third-party software such as
the Viewlogic design entry and simulation programs. The interconnect
architecture in the Xilinx EPLD FPGA is deterministic and so postlayout timing
results are close to prelayout estimates.
AMD, before it sold its stake in Xilinx, published the 1989/1990 Programmable
Data Array Book, which was distinct from the Xilinx data book. The AMD data
book contains useful information and code for programs to download
configuration files to Xilinx FPGAs from a PC that are still useful.
Altera publishes a series of loose-leaf application notes on a variety of topics,
some of them are in the data book (see, for example [Altera, 1996]), but some are
not. Most of these application notes are available as the AN series of documents
at http://www.altera.com/html/literature . This includes guides on using Cadence,
Mentor, Viewlogic, and Synopsys software. The 100-page Synopsys guide (
as_sig.pdf ) explains many of the limitations of logic synthesizers for FPGA
design and includes the complete VHDL source code for a voice-mail machine as
an example.
Atmel has a series of data sheets and application notes for its PLD logic at
http://www.atmel.com . Some of the data sheets (for the ATV2500, for example,
available as doc156.pdf ) also include examples of the use of CUPL and ABEL.
An application note in Atmels data book (available as doc168.pdf ) includes the
ABEL source code for a video frame grabber and a description of the NTSC
video format. Atmel offers a review of its links to third-party software in a
section PLD Software Tools Overview in its data book (available online as
doc150.pdf at http://www.atmel.com/atmel/products ). Atmel uses an
IBM-compatible PC-based system based on the Viewlogic software. Schematic
entry uses Viewdraw and simulation uses Viewsim. Atmel provides a separate
program, a fitter, to optimize a schematic for its FPGA architecture. The output
from this software generates an optimized schematic. The place-and-route
software then works with this new schematic. Atmel provides an interactive
editor similar to the Xilinx design editor that allows the designer to perform
placement manually. Atmel also supports PLD design software such as Synario
from Data I/O.
The QuickLogic design kit uses the ECS ( Engineering Capture System)
developed by the CAD/CAM Group and now part of DATA I/O. Simulation uses
X-SIM, a product of Silicon Automation Systems.
Cypress has a low-cost design system (for QuickLogic and its own series of
complex PLDs) called Warp that uses VHDL for design entry.
8.6.2 Third-Party Software
There is a bewildering array of software and software companies that make, sell,
and develop products for PLD and FPGA design. These are referred to as
third-party vendors . In the remainder of this section we shall describe (in
alphabetical order) some of the available third-party software. This list changes
frequently and for more information you might search the EE sites from the
Bibliography in Chapter 1.
Accel ( http://www.edac.org/EDAC/Companies ) produces Tango and P-CAD
(which used to belong to Personal CAD Systems) that are a low-cost and popular
schematic-entry and PCB layout software for PCs. Currently there are no FPGA
vendors that support P-CAD or Tango directly. The missing ingredient is a set of
libraries with the appropriate schematic symbols for the logic macros and cells
used by the FPGA vendor.
AMD ( http://www.amd.com ) produces the Mach series of PLDs and is also the
owner of PALASM. All of the FPGA vendors use the PALASM and PALASM2
languages as interchange formats. Using PALASM is an easy way to incorporate
a PLD into an FPGA.
Antares ( http://www.anteresco.com ) is a spin-off from Mentor Corporation
formed from Exemplar Logic, a company specializing in synthesis software for
PLDs and FPGAs, and Model Technology, who produce a VHDL and Verilog
simulator using a common kernel.
Cadence ( http://www.cadence.com ) is one of the largest EDA companies. They
offer design kits for PLD and FPGA design with its schematic-entry (Composer)
and logic-synthesis (Concept) software. The Cadence Web site has some pictures
of ASIC and FPGA design flow in its third-party support area. To find these,
search for FPGA from the main menu.
Compass Design Automation ( http://www.compass-da.com ) is a spin-off from
VLSI Technology that specializes in ASIC design software and cell libraries. As
part of its system design software, this vendor includes compilers and libraries
for Xilinx, Actel, and Altera FPGAs.
Data I/O ( http://www.data-io.com ) makes the FutureNet DASH schematic-entry
program primarily for IBM-compatible PCs. Version 5 also has an EDIF 2 0 0
netlist writer, and an optional program PLDlinx to convert designs to ABEL.
Data I/O's ABEL is a very widely used PLD design standard. Most FPGA
software allows the merging of ABEL files with netlists from schematic-entry
programs. Usually you have to translate ABEL to PALASM first and then merge
the PALASM file with any netlists that you created from schematics. ABEL is
available on SUN workstations, IBM-compatible PC-DOS, and Macintosh
platforms. The Macintosh version is available through Capilano Computing,
using its DesignWorks program. Data I/O has extended its ABEL language for
use with FPGA design. ABEL-FPGA is a set of software that can accept
hardware descriptions in ABEL-HDL. ABEL-HDL is an extension of the ABEL
language which is optimized for programmable logic. One of the features of
ABEL-HDL is a set of naming extensions, dot extensions, which allow the
designer to specify how certain signals will be mapped into an FPGA.
Data I/O also makes a number of programmers. For example, the Unisite PROM
programmer can be used to program Actel, Altera MAX, and Xilinx EPLD
devices.
Data I/O has recently launched a separate division called Synario Design
Automation ( http://www.synario.com ) that has taken over ABEL and produces
a new series of PLD and FPGA design software under the Synario banner.
Exemplar, now part of Antares, writes many of the software modules for logic
synthesis used by other companies in their FPGA synthesis software. Exemplar
provides a software package that allows you to enter hardware descriptions in
ABEL, PALASM, CUPL, or Minc formats.
ISDATA produces a system called LOG/iC that can be used for FPGA design.
LOG/iC produces JEDEC fusemap files, which can be converted and merged
with netlists created with other vendors software. An evaluation diskette contains
LOG/iC software that programs the Lattice GAL16V8. ISDATA also makes a
program called STATE/view for design using state diagrams and flow charts and
works with LOG/iC and ABEL. HINT is a program that accepts a subset of
VHDL and compiles to the LOG/iC language.
Logical Devices ( http://www.logicaldevices.com ) acquired CUPL, a widely
used programming language for PLDs, from Personal CAD Systems in 1987.
Most FPGA vendors allow you to use files in CUPL format indirectly. Usually
you translate to the PALASM format first in order to incorporate any logic you
design with CUPL. Logical Devices also sells EPROM programming hardware.
They manufacture programmers for FPGAs.
Mentor Graphics Corporation ( http://www.mentorg.com ) is a large EDA
company. Mentor produces schematic-entry and logic-synthesis software, IDEA
Station and FPGA Station, that interface to the major FPGA vendors (see also
Antares).
Mincs PLDesigner software allows the entry of PLD designs using a mixture of
truth tables, waveforms, Minc's Design Synthesis Language ( DSL), schematic
entry, or a netlist (in EDIF format). Another Minc program PGADesigner
includes the ability to target FPGAs as well as PLDs. This program is compatible
with the OrCAD, P-CAD, and FutureNet DASH schematic-entry programs.
OrCAD ( http://www.orcad.com ) is a popular low-cost PC schematic-entry
program supported directly by a number of FPGA vendors.
Simucad ( http://www.simucad.com ) produces PC-SILOS, a low-cost
logic-simulation program for PCs machines. Xilinx used to bundle Simucad with
FutureNet DASH in its least expensive, entry-level design kit.
Synopsys ( http://www.synopsys.com ) sells logic-synthesis software. There are
two main products: the Design Compiler for ASIC design and the FPGA
Compiler for FPGA design. FPGA Express is a PC-based FPGA logic
synthesizer. There is an extensive on-line help system available for Synopsys
customers.
Tanner Research ( http://www.tanner.com ) offers a variety of ASIC design
software and a burning service; you send them the download files to program
the FPGAs and Tanner Research programs the parts and ships them to you.
Tanner Research also offers an Actel schematic library for its schematic-entry
program S-Edit.
Texas Instruments (TI) and Minc produces mapping software between TI's gate
arrays and FPGAs (TIs relationship with Actel is somewhere between a
second-source and a partner). Mapping software allows designers to design for a
TI gate array, for example, but prototype in FPGAs. Alternatively you could take
an existing FPGA design and map it into a TI gate array. This type of design flow
is popular with vendors such as AT&T (Lucent), TI, and Motorola who would
like you to prototype with their FPGAs before transferring any high-volume
products to their ASICs.
Viewlogic ( http://www.viewlogic.com ) produces the Workview and
PRODesigner systems that are sets of ASIC design programs available on a
variety of platforms. The Workview software consists of a schematic-entry
program Viewdraw; two simulators: Viewsim and Viewfault; a synthesis tool,
Viewgen; Viewplace for layout interface; Viewtrace for simulation analysis; and
Viewwave for graphical display. There is also a package, Viewbase, that is a set
of software routines enabling programmers to access Viewlogic's database in
order to create EDIF, VHDL, and CFI ( CAD Framework Initiative) interfaces.
Most of the FPGA vendors have a means to incorporate Viewlogics schematic
netlists using Viewlogics WIR netlist format. Viewlogic provides a number of
applications notes (TECHniques) and includes a list of bug fixes, software
limitations, and workarounds online.
8.7 References
Page numbers in brackets after a reference indicate its location in the chapter
body.
Actel. 1996. FPGA Data Book and Design Guide. No catalog information.
Available from Actel Corporation, 955 East Arques Avenue, Sunnyvale, CA
94086-4533, (408) 739-1010. Contains design guides and applications notes,
including: Estimating Capacity and Performance for ACT 2 FPGA Designs
(describes circuits to connect FPGAs to PALs); Binning Circuit of Actel FPGAs
(describes circuits and data for performance measurement); Global Clock
Networks (describes clock distribution schemes); Fast On and Off Chip Delays
with ACT 2 I/O Latches (describes techniques to improve I/O performance);
Board Level Considerations for Actel FPGAs (describes ground bounce and SSO
problems); A Power-On Reset (POR) Circuit for Actel Devices (describes
problems caused by slowly rising supply voltage); Implementing Load ( sic )
Latency Fast Counters with ACT 2 FPGAs; Oscillators for Actel FPGAs
(describes crystal and RC oscillators); Designing a DRAM Controller Using
Language-Based Synthesis (a detailed Verilog description of a 4 MB DRAM
controller including refresh). See also the Actel Web site. [ reference location ]
Altera. 1996. Data Book. No catalog information. Available from Altera
Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020, (408) 944-0952.
Contains information on the FLEX 10k and 8000 complex PLDs; MAX 9000,
7000, and 5000 complex PLDs; FLASHlogic; and EPLDs. A limited number of
application notes are also included. More information may be found at the Altera
Web site. [ reference location ]
Connor, D. 1992. Taking the first steps. EDN, April 9, p. 98. ISSN 0012-7515.
The second part of this article, Migrating to FPGAs: Any designer can do it, was
published in EDN, April 23, 1992, p. 120. See also http://www.ednmag.com .
Both articles are reprinted in the 1994 Actel Data Book. A description of
designing, simulating, and testing a voicemail system using Viewlogic software. [
reference location ]
Skahill, K. 1996. VHDL for Programmable Logic. Menlo Park, CA:
Addison-Wesley, 593 p. ISBN 0-201-89573-0. TK7885.7.S55. Covers VHDL
design for PLDs using Cypress Warp design system. [ reference location ]
Xilinx. 1996. The Programmable Logic Data Book. No catalog information.
Available from Xilinx Corporation, 2100 Logic Drive, San Jose, CA 95124-3400,
(408) 559-7778. Contains details of XC9500, XC7300, and XC7200 CPLDs;
XC5200, XC4000, XC3000 LCA FPGAs; and XC6200 sea-of-gates FPGAs.
Earlier editions of this data book (the 1994 edition, for example) contained a
section titled Best of XCELL that contained extremely useful design
information. Much of this design material is now only available online, at the
Xilinx Web site. [ reference location ]
L ast E d ited by S P 1411 2 0 0 4
LOW-LEVEL
DESIGN ENTRY
The purpose of design entry is to describe a microelectronic system to a set of
electronic-design automation ( EDA ) tools. Electronic systems used to be, and
many still are, constructed from off-the-shelf components, such as TTL ICs.
Design entry for these systems now usually consists of drawing a picture, a
schematic . The schematic shows how all the components are connected together,
the connectivity of an ASIC. This type of design-entry process is called
schematic entry , or schematic capture . A circuit schematic describes an ASIC in
the same way an architects plan describes a building.
The circuit schematic is a picture, an easy format for us to understand and use,
but computers need to work with an ASCII or binary version of the schematic
that we call a netlist . The output of a schematic-entry tool is thus a netlist file
that contains a description of all the components in a design and their
interconnections.
Not all the design information may be conveyed in a circuit schematic or netlist,
because not all of the functions of an ASIC are described by the connectivity
information. For example, suppose we use a programmable ASIC for some
random logic functions. Part of the ASIC might be designed using a text
language. In this case design entry also includes writing the code. What if an
ASIC in our system contains a programmable memory (PROM)? Is the PROM
microcode, the '1's and '0's, part of design entry? The operation of our system is
certainly dependent on the correct programming of the PROM. So perhaps the
PROM code ought to be considered part of design entry. On the other hand
nobody would consider the operating-system code that is loaded into a RAM on
an ASIC to be a part of design entry. Obviously, then, there are several different
forms of design entry. In each case it is important to make sure that you have
completely specified the systemnot only so that it can be correctly constructed,
but so that someone else can understand how the system is put together. Design
entry is thus an important part of documentation .
Until recently most ASIC design entry used schematic entry. As ASICs have
become more complex, other design-entry methods are becoming common.
Alternative design-entry methods can use graphical methods, such as a
schematic, or text files, such as a programming language. Using a hardware
description language ( HDL ) for design entry allows us to generate netlists
directly using logic synthesis . We will concentrate on low-level design-entry
methods together with their advantages and disadvantages in this chapter.
9.1 Schematic Entry
Schematic entry is the most common method of design entry for ASICs and is
likely to be useful in one form or another for some time. HDLs are replacing
conventional gate-level schematic entry, but new graphical tools based on
schematic entry are now being used to create large amounts of HDL code.
Circuit schematics are drawn on schematic sheets . Standard schematic sheet
sizes ( Table 9.1 ) are ANSI AE (more common in the United States) and ISO
A4A0 (more common in Europe). Usually a frame or border is drawn around the
schematic containing boxes that list the name and number of the schematic page,
the designer, the date of the drawing, and a list of any modifications or changes.
TABLE 9.1 ANSI (American National Standards Institute) and ISO
(International Standards Organization) schematic sheet sizes.
ANSI sheet
Size (inches)
ISO sheet
Size (cm)
A
8.5 ¥ 11
A5
21.0 ¥ 14.8
B
11 ¥ 17
A4
29.7 ¥ 21.0
C
17 ¥ 22
A3
42.0 ¥ 29.7
D
22 ¥ 34
A2
59.4 ¥ 42.0
E
34 ¥ 44
A1
84.0 ¥ 59.4
A0
118.9 ¥ 84.0
Figure 9.1 shows the spades and shovels, the recognized symbols for AND,
NAND, OR, and NOR gates. One of the problems with these recommendations is
that the corner points of the shapes do not always lie on a grid point (using a
reasonable grid size).
FIGURE 9.1 IEEE-recommended dimensions and their construction for
logic-gate symbols. (a) NAND gate (b) exclusive-OR gate (an OR gate is a
subset).
Figure 9.2 shows some pictorial definitions of objects you can use in a simple
schematic. We shall discuss the different types of objects that might appear in an
ASIC schematic first and then discuss the different types of connections.
FIGURE 9.2 Terms used in circuit schematics.
Schematic-entry tools for ASIC design are similar to those for printed-circuit
board (PCB) design. The basic object on a PCB schematic is a component or
device a TTL IC or resistor, for example. There may be several hundred
components on a typical PCB. If we think of a logic gate on an ASIC as being
equivalent to a component on a PCB, then a large ASIC contains hundreds of
thousands of components. We can normally draw every component on a few
schematic sheets for a PCB, but drawing every component on an ASIC schematic
is impractical.
9.1.1 Hierarchical Design
Hierarchy reduces the size and complexity of a schematic. Suppose a building
has 10 floors and contains several hundred offices but only three different basic
office plans. Furthermore, suppose each of the floors above the ground floor that
contains the lobby is identical. Then the plans for the whole building need only
show detailed plans for the ground floor and one of the upper floors. The plans
for the upper floor need only show the locations of each office and the office
type. We can then use a separate set of three detailed plans for each of the
different office types. All these different plans together form a nested structure
that is a hierarchical design . The plan for the whole building is the top-level
plan. The plans for the individual offices are the lowest level. To clarify the
relationship between different levels of hierarchy we say that a subschematic (an
office) is a child of the parent schematic (the floor containing offices). An
electrical schematic can contain subschematics. The subschematic, in turn, may
contain other subschematics. Figure 9.3 illustrates the principles of schematic
hierarchical design.
FIGURE 9.3 Schematic example showing hierarchical design. (a) The
schematic of a half-adder, the subschematic of cell HADD. (b) A schematic
symbol for the half adder. (c) A schematic that uses the half-adder cell. (d) The
hierarchy of cell HADD.
The alternative to hierarchical design is to draw all of the ASIC components on
one giant schematic, with no hierarchy, in a flat design . For a modern ASIC
containing thousands or more logic gates using a flat design or a flat schematic
would be hopelessly impractical. Sometimes we do use flat netlists though.
9.1.2 The Cell Library
Components in an ASIC schematic are chosen from a library of cells. Library
elements for all types of ASICs are sometimes also known as modules .
Unfortunately the term module will have a very specific meaning when we come
to discuss hardware description languages. To avoid any chance of confusion I
use the term cell to mean either a cell, a module, a macro, or a book from an
ASIC library. Library cells are equivalent to the offices in our office building.
Most ASIC companies provide a schematic library of primitive gates to be used
for schematic entry. The first problem with ASIC schematic libraries is that there
are no naming conventions. For example, a primitive two-input NAND gate in a
Xilinx FPGA library does not have the same name as the two-input NAND gate
in an LSI Logic gate-array library. This means that you cannot take a schematic
that you used to create a prototype product using a Xilinx FPGA and use that
schematic to create an LSI Logic gate array for production (something you might
very likely want to do). As soon as you start entering a schematic using a library
from an ASIC vendor, you are, to some extent, making a commitment to use that
vendors ASIC. Most ASIC designers are much happier maintaining a large
degree of vendor independence.
A second problem with ASIC schematic libraries is that there are no standards for
cell behavior. For example, a two-input MUX in an Actel library operates so that
the input labeled A is selected when the MUX select input S = '0'. A two-input
MUX in a VLSI Technology library operates in the reverse fashion, so that the
input labeled B is selected when S = '0'. These types of differences can cause
hard-to-find problems when trying to convert a schematic from one vendor to
another by hand. These problems make changing or retargeting schematics from
one vendor to another difficult. This process is sometimes known as porting a
design.
Library cells that represent basic logic gates, such as a NAND gate, are known as
primitive cells , usually referred to just as cells. In a hierarchical ASIC design a
cell may be a NAND gate, a flip-flop, a multiplier, or even a microprocessor, for
example. To use the office building analogy again, each of the three basic office
types is a primitive cell. However, the plan for the second floor is also a cell. The
second-floor cell is a subschematic of the schematic for the whole building. Now
we see why the commonly accepted use of the term cell in schematic entry can be
so confusing. The term cell is used to represent both primitive cells and
subschematics. These are two different, but closely related, things.
There are two types of macros for MGAs and programmable ASICs. The most
common type of macro is a hard macro that includes placement information. A
hard macro can change in position and orientation, but the relative location of the
transistors, other layout, and wiring inside the macro is fixed. A soft macro
contains only connection information (between transistors for a gate array or
between logic cells for a programmable ASIC). Thus the placement and wiring
for a soft macro can vary. This means that the timing parameters for a soft macro
can only be determined after you complete the place-and-route step. For this
reason the basic library elements for MGAs and programmable ASICs, such as
NAND gates, flip-flops, and so on, are hard macros.
A standard cell contains layout information on all mask levels. An MGA hard
macro contains layout information on just the metal, contact, and via layers. An
MGA soft macro or programmable ASIC macro does not contain any layout
information at all, just the details of connections to be made inside the macro.
We can stretch the office building analogy to explain the difference between hard
and soft macros. A hard macro would be an office with fixed walls in which you
are not allowed to move the furniture. A soft macro would be an office with
partitions in which you can move the furniture around and you can also change
the shape of your office by moving the partitions.
9.1.3 Names
Each of the cells, primitive or not, that you place on an ASIC schematic has a cell
name . Each use of a cell is a different instance of that cell, and we give each
instance a unique instance name . A cell instance is somewhere between a copy
and a reference to a cell in a library. An analogy would be the pictures of
hamburgers on the wall in a fast-food restaurant. The pictures are somewhere
between a copy and a reference to a real hamburger.
We represent each cell instance by a picture or icon , also known as a symbol .
We can represent primitive cells, such as NAND and NOR gates, with familiar
icons that look like spades and shovels. Some schematic editors offer the option
of switching between these familiar icons and using the rectangular IEEE
standard symbols for logic gates. Unfortunately the term icon is also often used to
refer to any of the pictures on a schematic, including those that represent
subschematics. There is no accepted way to differentiate between an icon that
represents a primitive cell and one that represents a subschematic that may be in
turn a collection of primitive cells. In fact, there is usually no easy way to tell by
looking at a schematic which icons represent primitive cells and which represent
subschematics.
We will have three different icons for each of the three different primitive offices
in the imaginary office building example of Section 9.1.1 . We also will have
icons to represent the ground floor and the plan for the other floors. We shall call
the common plan for the second through tenth floors, Floor . Then we say that the
second floor is an instance of the cell name Floor . The third through tenth floors
are also instances of the cell name Floor . The same icon will be used to represent
the second through tenth floors, but each will have a unique instance name. We
shall give them instance names: FloorTwo , FloorThree , ... , FloorTen . We say
that FloorTwo through FloorTen are unique instance names of the cell name
Floor .
At the risk of further confusion I should point out that, strictly speaking, the
definition of a primitive cell depends on the type of library being used.
Schematic-entry libraries for the ASIC designer stop at the level of NAND gates
and other similar low-level logic gates. Then, as far as the ASIC designer is
concerned, the primitive cells are these logic gates. However, from the view of
the library designer there is another level of hierarchy below the level of logic
gates. The library designer needs to work with libraries that contain schematics of
the gates themselves, and so at this level the primitive cells are transistors.
Let us look at the building analogy again to understand the subtleties of primitive
cells. A building contractor need only concern himself with the plans for our
office building down to the level of the offices. To the building contractor the
primitive cells are the offices. Suppose that the first of the three different office
types is a corner office, the second office type has a window, and a third office
type is without a window. We shall call these office cells: CornerOffice ,
WindowOffice , and NoWindowOffice . These cells are primitive cells as far as
the contractor is concerned. However, when discussing the plans with a client,
the architect of our building will also need to see how each offices is furnished.
The architect needs to see a level of detail of each office that is more complicated
than needed by the building contractor. The architect needs to see the cells that
represent the tables, chairs, and desks that make up each type of office. To the
architect the primitive cells are a library containing cells such as chair , table ,
and desk .
9.1.4 Schematic Icons and Symbols
Most schematic-entry programs allow the designer to draw special or custom
icons. In addition, the schematic-entry tool will also usually create an icon
automatically for a subschematic that is used in a higher-level schematic. This is
a derived icon , or derived symbol . The external connections of the subschematic
are automatically attached to the icon, usually a rectangle.
Figure 9.4 (c) shows what a derived icon for a cell, DLAT , might look like (we
could also have drawn this by hand). The subschematic for DLAT is shown in
Figure 9.4 (b). We say that the inverter with the instance name inv1 in the
subschematic is a subcell (or submodule) of the cell DLAT . Alternatively we say
that cell instance inv1 is a child of the cell DLAT , and cell DLAT is a parent of
cell instance inv1 .
FIGURE 9.4 A cell and its subschematic. (a) A schematic library containing
icons for the primitive cells. (b) A subschematic for a cell, DLAT, showing the
instance names for the primitive cells. (c) A symbol for cell DLAT.
Figure 9.5 (a) shows a more complex subschematic for a 4-bit latch. Each
primitive cell instance in this schematic must have a unique name. This can get
very tiresome for large circuits. Instead of creating complex, but repetitive,
subschematics for complex cells we can use hierarchy.
FIGURE 9.5 A 4-bit latch: (a) drawn as a flat schematic from gate-level
primitives, (b) drawn as four instances of the cell symbol DLAT, (c) drawn
using a vectored instance of the DLAT cell symbol with cardinality of 4,
(d) drawn using a new cell symbol with cell name FourBit.
Figure 9.5 (b) shows a hierarchical subschematic for a cell FourBit , which in
turn uses four instances of the cell DLAT . The four instances of DLAT in
Figure 9.5 (b) have different instance names: L1 , L2 , L3 , and L4 . Notice that
we cannot use just one name for the four instances of DLAT to indicate that they
are all the same cell. If we did, we could not differentiate between L1 and L2 , for
example.
The vertical row of instances in Figure 9.5 (b) looks like a vector of elements.
Figure 9.5 (c) shows a vectored instance representing four copies of the DLAT
cell. We say the cardinality of this instance is 4. Tools normally use bold lines or
some other distinguishing feature to represent a vectored instance. The
cardinality information is often shown as a vector. Thus L[1:4] represents four
instances: L[1] , L[2] , L[3] , L[4] . This is convenient because now we can see
that all subcells are identical copies of L , but we have a unique name for each.
Finally, as shown in Figure 9.5 (d) we can create a new symbol for the 4-bit
latch, FourBit . The symbol for FourBit has a 4-bit-wide input bus for the four D
inputs, and a 4-bit wide output bus for the four Q outputs. The subschematic for
FourBit could be either Figure 9.5 (a), (b), or (c) (though the exact naming of the
inputs and outputs and their attachment to the buses may be different in each
case).
We need a convention to distinguish, for example, between the inverter subcells,
inv1 , which are children of the cell DLAT , which are in turn children of the cell
FourBit . Most schematic-entry tools do this by combining the instance names of
the subcells in a hierarchical manner using a special character as a delimiter. For
example, if we drew the subschematic as in Figure 9.5 (b), the four inverters in
FourBit might be named L1.inv1 , L2.inv1 , L3.inv1 , and L4.inv1 . Once again
this makes it clear that the inverters, inv1 , are identical in all four subcells.
In our office building example, the offices are subcells of the cell Floor . Suppose
you and I both have corner offices. Mine is on the second floor and yours is
above mine on the third floor. My office is 211 and your office is 311. Another
way to name our offices on a building plan might be FloorTwo.11 for my office
and FloorThree.11 for your office. This shows that FloorTwo.11 is a subcell of
FloorTwo and also makes it clear that, apart from being on different floors, your
office and mine are identical. Both our offices have instance names 11 and are
instances of cell name Corner .
9.1.5 Nets
The schematics shown in Figure 9.4 contain both local nets and external nets . An
example of a local net in Figure 9.4 (b) is n1 , the connection between the output
terminal of the AND cell and1 to the OR cell or1 . When the four copies of this
circuit are placed in the parent cell FourBit in Figure 9.5 (d), four copies of net n1
are created. Since the four nets named n1 are not actually electrically connected,
even though they have the same name at the lowest hierarchical level, we must
somehow find a way to uniquely identify each net.
The usual convention for naming nets in a hierarchical schematic uses the parent
cell instance name as a prefix to the local net name. A special character ( ':' '/' '$'
'#' for example) that is not allowed to appear in names is used as a delimiter to
separate the net name from the cell instance name. Supposing that we drew the
subschematic for cell FourBit as shown in Figure 9.5 (b), the four different nets
labeled n1 might then become:
FourBit .L1:n1 FourBit .L2:n1 FourBit .L3:n1 FourBit .L4:n1
This naming is usually done automatically by the schematic-entry tool.
The schematic DLAT also contains three external nets: D, EN, and Q . The
terminals on the symbol DLAT connect these nets to other nets in the hierarchical
level above. For example, the signal Trigger:flag in Figure 9.4 (c) is also
Trigger.DLAT:Q . Each schematic tool handles this situation differently, and life
becomes especially difficult when we need to refer to these nodes from a
simulator outside the schematic tool, for example. HDLs such as VHDL and
Verilog have a very precise and well-defined standard for naming nets in
hierarchical structures.
9.1.6 Schematic Entry for ASICs and PCBs
A symbol on a schematic may represent a component, which may contain
component parts. You are more likely to come across the use of components in a
PCB schematic. A component is slightly different from an ASIC library cell. A
simple example of a component would be a TTL gate, an SN74LS00N, that
contains four 2-input NAND gates. We call an SN74LS00N a component and
each of the individual NAND gates inside is a component part. Another common
example of a component would be a resistor packa single package that contains
several identical resistors.
In PCB design language a component label or name is a reference designator . A
reference designator is a unique name attribute, such as R99 , attached to each
component. A reference designator, such as R99 , has two pieces: an alpha prefix
R and a numerical suffix 99 . To understand the difference between reference
designators and instance names, we need to look at the special requirements of
PCB design.
PCBs usually contain packaged ASICs and other ICs that have pins that are
soldered to a board. For rectangular, dual-in-line (DIP) packages the pins are
numbered counterclockwise from the upper-left corner looking down on the
package.
IC symbols have a pin number for each part in the package. For example, the
TTL 74174 hex D flip-flop with clear, contains six parts: six identical D
flip-flops. The IC symbol representing this device has six PinNumber attribute
entries for the D input corresponding to the six possible input pins. They are pins
3, 4, 6, 11, 13, and 14.
When we need a flip-flop in our design, we use a symbol for a 74174 from a
schematic library, suppose the symbol name is dffClr . We shall assign a unique
instance name to the symbol, CarryFF . Now suppose we need another, identical,
flip-flop and we call this BitFF . We do not mind which of the six flip-flop parts
in a 74174 we use for CarryFF and BitFF . In fact they do not even have to be in
the same package. We shall delay the choice of assigning CarryFF and BitFF to
specific packages until we get to the PCB routing step. So at this point on our
schematic we do not even know the pin numbers for CarryFF and BitFF . For
example the D input to CarryFF could be pin 3, 4, 6, 11, 13, or 14.
The number of wire crossings on a PCB is minimized by careful assignment of
components to packages and choice of parts within a package. So the
placement-and-routing software may decide which part of which package to use
for CarryFF and BitFF depending on which is easier to route. Then, only after the
placement and routing is complete, are unique reference designators assigned to
the component parts. Only at this point do we know where CarryFF is actually
located on the PCB by referring to the reference designator, which points to a
specific part in a specific package. Thus CarryFF might be located in IC4 on our
PCB. At this point we also know which pins are used for each symbol. So we
now know, for example, that the D-input to CarryFF is pin 3 of IC4 .
There is no process in ASIC design directly equivalent to the process of part
assignment described above and thus no need to use reference designators. The
reference-designator naming convention quickly becomes unwieldy if there are a
large number of components in a design. For example, how will we find a NAND
gate named X3146 in an ASIC schematic with 100 pages? Instead, for ASICs, we
use a naming scheme based on hierarchy.
In large hierarchical ASIC designs it is difficult to provide a unique reference
designator to each element. For this reason ASIC designs use instance names to
identify the individual components. Meaningful names can be assigned to
low-level components and also the symbols that represent hierarchy. We derive
the component names by joining all of the higher level cell names together. A
special character is used as a delimiter and separates each level.
Examples of hierarchical instance names are:
cpu.alu.adder.and01
MotherBoard:Cache:RAM4:ReadBit4:Inverter2
9.1.7 Connections
Cell instances have terminals that are the inputs and outputs of the cell. Terminals
are also known as pins , connectors , or signals . The term pin is widely used, but
we shall try to use terminal, and reserve the term pin for the metal leads on an
ASIC package. The term pin is used in schematic entry and routing programs that
are primarily intended for PCB design.
FIGURE 9.6 An example of the use of a bus to simplify a schematic. (a) An
address decoder without using a bus. (b) A bus with bus rippers simplifies the
schematic and reduces the possibility of making a mistake in creating and
reading the schematic.
Electrical connections between cell instances use wire segments or nets . We can
group closely related nets, such as the 32 bits of a 32-bit digital word, together
into a bus or into buses (not busses). If signals on a bus are not closely related,
we usually use the term bundle or array instead of bus. An example of a bundle
might be a bus for a SCSI disk system, containing not only data bits but
handshake and control signals too. Figure 9.6 shows an example of a bus in a
schematic. If we need to access individual nets in a bus or a bundle, we use a
breakout (also known as a ripper , an EDIF term, or extractor ). For example, a
breakout is used to access bits 07 of a 32-bit bus. If we need to rearrange bits on
a bus, some schematic editors offer something called a swizzle . For example, we
might use a swizzle to reorder the bits on an 8-bit bus so that the MSB becomes
the LSB and so on down to the LSB, which now becomes the MSB. Swizzles can
be useful. For example, we can multiply or divide a number by 2 by swizzling all
the bits up or down one place on a bus.
9.1.8 Vectored Instances and Buses
So far the naming conventions are fairly standard and easy to follow. However,
when we start to use vectored instances and buses (as is now common in large
ASICs), there are potential areas of difficulty and confusion. Figure 9.7 (a) shows
a schematic for a 16-bit latch that uses multiple copies of the cell FourBit . The
buses are labeled with the appropriate bits. Figure 9.7 (b) shows a new cell
symbol for the 16-bit latch with 16-bit wide buses for the inputs, D, and outputs,
Q.
FIGURE 9.7 A 16-bit latch: (a) drawn as four instances of cell FourBit; (b)
drawn as a cell named SixteenBit; (c) drawn as four multiple instances of cell
FourBit.
Figure 9.7 (c) shows an alternative representation of the 16-bit latch using a
vectored instance of FourBit with cardinality 4. Suppose we wish to make a
connection to expressly one bit, D1 (we have used D1 as the first bit rather than
the more conventional D0 so that numbering is easier to follow). We also wish to
make a connection to bits D9D12, represented as D[9:12]. We do this using a
bus ripper. Now we have the rather awkward situation of bus naming shown in
Figure 9.7 (c). Problems arise when we have buses of buses because the
numbers for the bus widths do not match on either side of a ripper. For this
reason it is best to use the single-bus approach shown in Figure 9.7 (b) rather than
the vectored-bus approach of Figure 9.7 (c).
9.1.9 Edit-in-Place
Figure 9.7 (b) shows a symbol SixteenBit , which uses the subschematic shown
in Figure 9.7 (a) containing four copies of FourBit , named NB1 , NB2 , NB3 ,
and NB4 (the NB stands for nibble, which is half of a word; a nibble is 4 bits for
8-bit words). Suppose we use the schematic-entry program to edit the subcell
NB1.L1 , which is an instance of DLAT inside NB1 . Perhaps we wish to change
the D latch to a D latch with a reset, for example. If the schematic editor supports
edit-in-place , we can edit a cell instance directly. After we edit the cell, the
program will update all the DLAT subcells in the cell that is currently loaded to
reflect the changes that have been made.
To see how edit-in-place works, consider our office building again. Suppose we
wish to change some of the offices on each floor from offices without windows to
offices with windows. We select the cell instance FloorTwo that is, an instance
of cell Floor . Now we choose the edit mode in the schematic-entry program. But
wait! Do we want to edit the cell Floor , or do we want to edit the cell instance
FloorTwo ? If we edit the cell Floor , we will be making changes to all of the
floors that use cell name Floor that is, instances FloorTwo through FloorTen . If
we edit the cell instance FloorTwo , then the second floor will become different
from all the other floors. It will no longer be an instance of cell name Floor and
we will have to create another cell name for the cell used by instance FloorTwo .
This is like the difference between ordering just one hamburger without pickles
and changing the picture on the wall that will change all future hamburgers.
Using edit-in-place we can edit the cell Floor . Suppose we change some of the
cell instances of cell name NoWindowOffice to instances of cell name
WindowOffice . When we finish editing and save the cell Floor , we have
effectively changed all of the floors that contain instances of this cell.
Instead of editing a cell in place, you may really want to edit just one instance of
a cell and leave any other instances unchanged. In this case you must create a
new cell with a new symbol and new, unique cell name. It might also be wise to
change the instance name of the new cell to avoid any confusion.
For example, we might change the third-floor plan of our office to be different
from the other upper floors. Suppose the third floor is now an instance of cell
name FloorVIP instead of Floor . We could continue to call the third floor cell
instance FloorThree , but it would be better to rename the instance differently,
FloorSpecial for example, to make it clear that it is different from all the other
floors.
Some tools have the ability to alias nets. Aliasing creates a net name from the
highest level in the design. Local names are net names at the lowest level such as
D , and Q in a flip-flop cell. These local names are automatically replaced by the
appropriate top-level names such as Clock1 , or Data2 , using a dictionary . This
greatly speeds tracing of signals through a design containing many levels of
hierarchy.
9.1.10 Attributes
You can attach a name , also known as an identifier or label , to a component, cell
instance, net, terminal, or connector. You can also attach an attribute , or property
, which describes some aspect of the component, cell instance, net, or connector.
Each attribute has a name, and some attributes also have values. The most
common problems in working with schematics and netlists, especially when you
try to exchange schematic information between different tools, are problems in
naming.
Since cells and their contents have to be stored in a database, a cell name
frequently corresponds (or is mapped to) a filename. This then raises the
problems of naming conventions including: case sensitivity, name-collision
resolution, dictionaries, handling of common special characters (such as
embedded blanks or underscores), other special characters (such as characters in
foreign alphabets), first-character restrictions, name-length problems (only 28
characters are permitted on an NFS compatible filename), and so on.
9.1.11 Netlist Screener
A surprising number of problems can be found by checking a schematic for
obviously fatal errors. A program that analyzes a schematic netlist for simple
errors is sometimes called a schematic screener or netlist screener . Errors that
can be found by a netlist screener include:
● unconnected cell inputs,
● unconnected cell outputs,
● nets not driven by any cells,
● too many nets driven by one cell,
● nets driven by more than one cell.
The screener can work continuously as the designer is creating the schematic or
can be run as a separate program independently from schematic entry. Usually
the designer provides attributes that give the screener the information necessary
to perform the checks. A few of the typical attributes that schematic-entry
programs use are described next.
A screener usually generates a list of errors together with the locations of the
problem on the schematic where appropriate. Some editors associate an identifier,
or handle , to every piece of a schematic, including comments and every net.
Normally there is some convention to the assigned names such as a grid on a
schematic. This works like the locator codes on a map, so that a net with A1 as
part of the name is in the upper-left-hand corner, for example. This allows you to
quickly and uniquely find any problems found by a screener. The term handle is a
computer programming term that is used in referring to a location in memory.
Each piece of information on a schematic is stored in lists in memory. This
technique breaks down completely when we move to HDLs.
Most schematic-entry programs work on a grid. The designer can control the size
of the grid and whether it is visible or not. When you place components or wires
you can instruct the editor to force your drawing to snap to grid . This means that
drawing a schematic is like drawing on graph paper. You can only locate
symbols, wires, and connections on grid points. This simplifies the internal
mechanics of the schematic-entry program. It also makes the transfer of
schematics between different EDA systems more manageable. Finally, it allows
the designer to produce schematic diagrams that are cleaner in appearance and
thus easier to read.
Most schematic-entry programs allow you to find components by instance name
or cell name. The editor may either jump to the component location and center
the graphic window on the component or highlight the component. More
sophisticated options allow more complex searches, perhaps using wildcard
matching. For example, to find all three-input NAND gates (primitive cell name
ND3) or three-input NOR gates (primitive cell name NO3), you could search for
cell name N*3, where * is a wildcard symbol standing for any character. The
editor may generate a list of components, perhaps with page number and
coordinate locations. Extensive find features are useful for large schematics
where it quickly becomes impossible to find individual components.
Some schematic editors can complete automatic naming of reference designators
or instance names to the schematic symbols either as the editor is running or as a
postprocessing step. A component attribute, called a prefix, defines the prefix for
the name for each type of component. For example, the prefix for all resistor
component types may be R . Each time a prefix is found or a new instance is
placed, the number in the reference designator or name is automatically
incremented. Thus if the last resistor component type you placed was R99 , the
next time you place a resistor it would automatically be named R100 .
For large schematics it is useful to be able to generate a report on the used and
unused reference designators. An example would be:
Reference designator prefix: R
Unused reference designator numbers: 153, 154
Last used reference designator number: 180
If you need this feature, you probably are not using enough hierarchy to simplify
your design.
During schematic entry of an ASIC design you will frequently need multiple
copies of components. This often occurs during datapath design, where
operations are carried out across multiple signals on a bus. A common example
would be multiple copies of a latch, one for each signal on a bus. It is tedious and
inefficient to have to draw and label the same cell many times on a schematic. To
simplify this task, most editors allow you to place a special vectored cell instance
of a cell. A vectored cell instance, or vectored instance for short, uses the same
icon for a single instance but with a special attribute, the cell cardinality , that
denotes the number of copies of the cell. Connections between signals on a bus
and vectored instances should be handled automatically. The width or cardinality
of the bus and the cell cardinality must match, and the design-entry tool should
issue a warning if this is not the case.
A schematic-entry program can use a terminal attribute to determine which cell
terminals are output terminals and which terminals are input terminals. This
attribute is usually called terminal polarity or terminal direction . Possible values
for terminal polarity might be: input , output , and bidirectional . Checking the
terminal polarity of the terminals on a net can help find problems such as a net
with all input terminals or all output terminals.
The fanout of a cell measures the driving capability of an output terminal. The
fanin of a cell measures the number of input terminals. Fanout is normally
measured using a standard load. A standard load is the load presented by one
input of a primitive cell, usually a two-input NAND. For example, a library cell
Counter may have an input terminal, Clock , that is connected to the input
terminals of five primitive cells. The loading at this terminal is then five standard
loads. We say that the fanout of Clock is five. In a similar fashion, we say that if
a cell Buffer is capable of driving the inputs of three primitive cells, the fanout of
Buffer is three. Using the fanin and fanout attributes a netlist screener can check
to see if the fanout driving a net is greater than the sum of all loads on that net.
(See Figure 9.2 on page 329.)
9.1.12 Schematic-Entry tools
Some editors offer icon edit-in-place in a similar fashion as schematic
edit-in-place for cells. Often you have to toggle editing modes in the
schematic-entry program to switch between editing cells and editing cell icons. A
schematic-entry program must keep track of when cells are edited. Normally this
is done by using a timestamp or datestamp for each cell. This is a text field within
the data file for each cell that holds the date and time that the cell was last
modified. When a new schematic or cell is loaded, the program needs to compare
its timestamp with the timestamps of any subcells. If any of the subcell
timestamps are more recent, then the designer needs to be alerted. Usually a
message appears to inform you that changes have been made to subcells since the
last time the cell currently loaded was saved. This may be what you expect or it
may be a warning that somehow a subcell has been changed inadvertently
(perhaps someone else changed it) since you last loaded that cell.
Normally the primitive cells in a library are locked and cannot be edited. If you
can edit a primitive cell, you have to make a copy, edit the copy, and rename it.
Normally the ASIC designer cannot do this and does not want to. For example, to
edit a primitive NAND gate stored in an ASIC schematic library would require
that the subschematic of the primitive cell be available (usually not the case) and
also that the next lower level primitives (symbols for the transistors making up
the NAND gate) also be available to the designer (also usually not the case).
What do you do if somehow changes were made to a cell by mistake, perhaps by
someone else, and you dont want the new cell, you want the old version? Most
schematic-entry and other EDA tools keep old versions of files as a back-up in
case this kind of problem occurs. Most EDA software automatically keeps track
of the different versions of a file by appending a version number to each file.
Usually this is transparent to the designer. Thus when you edit a cell named Floor
, the file on disk might be called Floor.6 . When you save the changes, the
software will not overwrite Floor.6 , but write out a new file and automatically
name it Floor.7 .
Some design-entry tools are more sophisticated and allow users to create their
own libraries as they complete an ASIC design. Designers can then control
access to libraries and the cells that they build during a design. This normally
requires that a schematic editor, for example, be part of a larger EDA system or
framework rather than work as a stand-alone tool. Sometimes the process of
library control operates as a separate tool, as a design manager or library manager
. Often there is a program similar to the UNIX make command that keeps track of
all files, their dependencies, and the tools that are necessary to create and update
each file.
You can normally set the number of back-up versions of files that EDA software
keeps. The version history controls the number of files the software will keep. If
you accidentally update, overwrite, or delete a file, there is usually an option to
select and revert to an earlier version. More advanced systems have check-out
services (which work just as in source control systems in computer programming
databases) that prevent these kinds of problems when many people are working
on the same design. Whenever possible, the management of design files and
different versions should be left under software control because the process can
become very complicated. Reverting to an earlier version of a cell can have
drastic consequences for other cells that reference the cell you are working with.
Attempts to manually edit files by changing version numbers and timestamps can
quickly lead to chaos.
Most schematic-entry programs allow you to undo commands. This feature may
be restricted to simply undoing the last command that you entered, or may be an
unlimited undo and redo, allowing you to back up as many commands as you
want in the current editing session.
You can spend a lot of time in a schematic editor placing components and
drawing the connections between them. Features that simplify initial entry and
allow modifications to be made easily can make an enormous difference to the
efficiency of the schematic-entry process.
Most schematic editors allow you to make connections by dragging the cursor
with the wire following behind, in a process known as rubber banding . The
connection snaps to a right angle when the connection is completed. For wire
connections that require more than two line segments, an automatic wiring
feature is useful. This allows you to define the wire path roughly using mouse
clicks and have the editor complete the connection.
It is exceedingly painful to move components if you have to rewire connections
each time. Most schematic editors allow you to move the components and drag
any wires along with them.
One of the most annoying problems that can arise in schematic entry is to think
that you have joined two wires on a schematic but find that in reality they do not
quite meet. This error can be almost impossible to find. A good editing program
will have a way of avoiding this problem. Some editors provide a visual (flash) or
audible (beep) feedback when the designer draws a wire that makes an electrical
connection with another. Some editors will also automatically insert a dot at a T
connection to show that an electrical connection is present. Other editors refuse
to allow four-way connections to be made, so there can be no ambiguity when
wires cross each other if an electrical connection is present or not.
A cell library or a collection of libraries is a key part of the schematic-entry
process. The ability to handle and control these libraries is an important feature of
any schematic editor. It should be easy to select components from the library to
be placed on a schematic.
In large schematics it is necessary to continue large nets and signals across
several pages of schematics. Signals such as power and ground, VDD and GND,
can be connected using global nets or special connectors . Global nets allow the
designer to label a net with the same name at different places on a schematic page
or on different pages without having to draw a connection explicitly. The
schematic editor treats these nets as though they were electrically connected.
Special connector symbols can be used for connections that cross schematic
pages. An off-page connector or multipage connector is a special symbol that will
show and label a connection to different schematic pages. More sophisticated
editors can automatically label these connectors with the page numbers of the
destination connectors.
9.1.13 Back-Annotation
After you enter a schematic you simulate the design to make sure it works as
expected. This completes the logical design. Next you move to ASIC physical
design and complete the layout. Only after you complete the layout do you know
the parasitic capacitance and therefore the delay associated with the interconnect.
This postroute delay information must be returned to the schematic in a process
known as back-annotation . Then you can complete a final, postlayout simulation
to make sure that the specifications for the ASIC are met. Chapter 13 covers
simulation, and the physical design steps are covered in Chapters 15 to 17.
9.2 Low-Level Design
Languages
Schematics can be a very effective way to convey design information because
pictures are such a powerful medium. There are two major problems with
schematic entry, however. The first problem is that making changes to a
schematic can be difficult. When you need to include an extra few gates in the
middle of a schematic sheet, you may have to redraw the whole sheet. The
second problem is that for many years there were no standards on how symbols
should be drawn or how the schematic information should be stored in a netlist.
These problems led to the development of design-entry tools based on text rather
than graphics. As TTL gave way to PLDs, these text-based design tools became
increasingly popular as de facto standards began to emerge for the format of the
design files.
PLDs are closely related to FPGAs. The major advantage of PLD tools is their
low cost, their ease of use, and the tremendous amount of knowledge and number
of designs, application notes, textbooks, and examples that have been built up
over years of their use. It is natural then that designers would want to use PLD
development systems and languages to design FPGAs and other ASICs. For
example, there is a tremendous amount of PLD design expertise and working
designs that can be reused.
In the case of ASIC design it is important to use the right tool for the job. This
may mean that you need to convert from a low-level design medium you have
used for PLD design to one more appropriate for ASIC design. Often this is
because you are merging several PLDs into a single, much larger, ASIC. The
reason for covering the PLD design languages here is not to try and teach you
how to use them, but to allow you to read and understand a PLD language and, if
necessary, convert it to a form that you can use in another ASIC design system.
9.2.1 ABEL
ABEL is a PLD programming language from Data I/O. Table 9.2 shows some
examples of the ABEL statements. The following example code describes a 4:1
MUX (equivalent to the LS153 TTL part):
TABLE 9.2 ABEL.
Statement
Example
Module
module MyModule
Comment
You can have multiple modules.
A string is a character series between
quotes.
MYDEV is Device ID for
MYDEV device '22V10' documentation.
Device
;
22V10 is checked by the compiler.
"comments go between
The end of a line signifies the end of
double quotes"
Comment
a comment; there is no need for an
"end of line is end of
end quote.
comment
@ALTERNATE "use
@ALTERNATE
operator
alternate
default
alternate symbols
&
*
AND
Title
title 'Title in a String'
OR
+
#
NOT
/
!
XOR
:+:
$
!$
:*:
XNOR
Pin 22 is the IO for input on pin 2 for
MYINPUT pin 2; I3, I4 a 22V10.
pin 3, 4 ;
Pin declaration
MYOUTPUT is active-low at the
/MYOUTPUT pin 22;
chip pin.
IO3,IO4 pin 21,20 ;
Signal names must start with a letter.
Equations
equations
Defines combinational logic.
IO4 = HELPER ;
Two-pass logic
HELPER = /I4 ;
MYOUTPUT =
Assignments
Equals '=' is unlocked assignment.
/MYINPUT ;
Clocked assignment operator
IO3 := I4 ;
(registered IO)
D = [D0, D1, D2, D3] ;
Signal sets
A signal set, an ABEL bus
Q = [Q0, Q1, Q2, Q3];
Q := D ;
4-bit-wide register
MYOUTPUT.RE = CLR
Suffix
Register reset
;
MYOUTPUT.PR = PRE
Register preset
;
COUNT = [D0, D1, D2]; Cant use @ALTERNATE
Addition
COUNT := COUNT + 1; if you use '+' to add.
ENABLE IO3 = IO2;
Enable
IO3 = MYINPUT;
Constants
Relational
End
K = [1, 0, 1] ;
IO# = D == K5 ;
end MyModule
Three-state enable (ENABLE is a
keyword).
IO3 must be a three-state pin.
K is 5.
Operators: == != < > <=
Last statement in module
module MUX4
title '4:1 MUX'
MyDevice device 'P16L8' ;
@ALTERNATE
"inputs
A, B, /P1G1, /P1G2 pin 17,18,1,6 "LS153 pins 14,2,1,15
P1C0, P1C1, P1C2, P1C3 pin 2,3,4,5 "LS153 pins 6,5,4,3
P2C0, P2C1, P2C2, P2C3 pin 7,8,9,11 "LS153 pins 10,11,12,13
"outputs
P1Y, P2Y pin 19, 12 "LS153 pins 7,9
equations
P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);
P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);
end MUX4
9.2.2 CUPL
CUPL is a PLD design language from Logical Devices. We shall review the
CUPL 4.0 language here. The following code is a simple CUPL example
describing sequential logic:
SEQUENCE BayBridgeTollPlaza {
PRESENT red
IF car NEXT green OUT go; /* conditional synchronous output */
DEFAULT NEXT red; /* default next state */
PRESENT green
NEXT red; } /* unconditional next state */
>=
This code describes a state machine with two states. Table 9.3 shows the different
state machine assignment statements.
TABLE 9.3 CUPL statements for state-machine entry.
Statement
Description
IF
NEXT
Conditional next state transition
Conditional next state transition with synchronous
IF
NEXT OUT
output
NEXT
Unconditional next state transition
Unconditional next state transition with asynchronous
NEXT OUT
output
OUT Unconditional asynchronous output
IF
OUT Conditional asynchronous output
DEFAULT NEXT
Default next state transition
DEFAULT
OUT Default asynchronous output
DEFAULT NEXT OUT Default next state transition with synchronous output
You may also encode state machines as truth tables in CUPL. Here is another
simple example:
FIELD input = [in1..0];
FIELD output = [out3..0];
TABLE input => output {00 => 01; 01 => 02; 10 => 04; 11 => 08; }
The advantage of the CUPL language, and text-based PLD languages in general,
is now apparent. First, we do not have to enter the detailed logic for the state
decoding ourselvesthe software does it for us. Second, to make changes only
requires simple text editingfast and convenient.
Table 9.4 shows some examples of CUPL statements. In CUPL Boolean
equations may use variables that contain a suffix, or an extension , as in the
following example:
output.ext = (Boolean expression);
TABLE 9.4 CUPL.
Statement
Example
Boolean
A = !B;
expression
A = B & C;
A = B # C;
A = B $ C;
Comment
A = B & C /* comment */
Pin declaration
PIN 1 = CLK;
Comment
Logical negation
Logical AND
Logical OR
Logical exclusive-OR
Device dependent
PIN = CLK;
Device independent
Node declaration NODE A;
Number automatically assigned
NODE [B0..7];
Array of buried nodes
Pinnode
PINNODE 99 = A;
Node assigned by designer
declaration
PINNODE [10..17] = [B0..7]; Array of pinnodes
Bit-field
FIELD Address = [B0..7];
8-bit address field
declaration
Bit-field
add_one = Address:FF;
True if Address = OxFF
operations
add_zero = !(Address:&);
True if Address = Ox00
add_range =
True if 0F.LE.Address.LE.FF
Address:[0F..FF];
The extensions steer the software, known as a fitter , in assigning the logic. For
example, a signal-name suffix of .OE marks that signal as an output enable.
Here is an example of a CUPL file for a 4-bit counter placed in an ATMEL PLD
part that illustrates the use of some common extensions:
Name 4BIT; Device V2500B;
/* inputs */
pin 1 = CLK; pin 3 = LD_; pin 17 = RST_;
pin [18,19,20,21] = [I0,I1,I2,I3];
/* outputs */
pin [4,5,6,7] = [Q0,Q1,Q2,Q3];
field CNT = [Q3,Q2,Q1,Q0];
/* equations */
Q3.T = (!Q2 & !Q1 & !Q0) & LD_ & RST_ /* count down */
# Q3 & !RST_ /* ReSeT */
# (Q3 $ I3) & !LD_; /* LoaD*/
Q2.T = (!Q1 & !Q0) & LD_ & RST_ # Q2 & !RST_ # (Q2 $ I2) & !LD_;
Q1.T = !Q0 & LD_ & RST_ # Q1 & !RST_ # (Q1 $ I1) & !LD_;
Q0.T = LD_ & RST_ # Q0 & !RST_ # (Q0 $ I0) & !LD_;
CNT.CK = CLK; CNT.OE = 'h'F; CNT.AR = 'h'0; CNT.SP = 'h'0;
In this example the suffix extensions have the following effects: .CK marks the
clock; .T configures sequential logic as T flip-flops; .OE (wired high) is the
output enable; .AR (wired low) is the asynchronous reset; and .SP (wired low) is
the synchronous preset. Table 9.5 shows the different CUPL extensions.
TABLE 9.5 CUPL 4.0 extensions.
Extension 1 Explanation
Extension
D
L
J, K
S, R
T
DQ
LQ
AP, AR
SP, SR
CK
OE
CA
PR
CE
LE
OBS
D input to a D
register
DFB
L L input to a latch
LFB
L
L
J-K-input to a J-K
register
S-R input to an
S-R register
T input to a T
L
register
D output of an
R
input D register
L
Explanation
D register feedback of
R
combinational output
Latched feedback of
R
combinational output
T register feedback of
TFB
R
combinational output
INT
R Internal feedback
Pin feedback of registered
output
D/T register on pin feedback
IOD/T
R
path selection
Latch on pin feedback path
Q output of an
R
IOL
R
input latch
selection
Asynchronous preset/reset of
Asynchronous
IOAP,
L
L
preset/reset
IOAR
register on feedback path
Synchronous preset/reset of
Synchronous
L
IOSP, IOSR L
preset/reset
register on feedback path
Product clock term
Clock for pin feedback
L
IOCK
L
(async.)
register
Asynchronous preset/reset
Product-term
APMUX,
L
L
output enable
ARMUX
multiplexor selection
L Complement array CKMUX
L Clock multiplexor selector
Programmable
Latch enable multiplexor
L
LEMUX
L
preload
selector
Output enable multiplexor
CE input of a
L
OEMUX
L
D-CE register
selector
Input multiplexor selector of
Product-term latch
L
IMUX
L
enable
two pins
Programmable
Technology-dependent fuse
L observability of
TEC
L
selection
buried nodes
IO
R
BYP
L
Programmable
register bypass
T1
L T1 input of 2-T register
The 4-bit counter is a very simple example of the use of the Atmel ATV2500B.
This PLD is quite complex and has many extra buried features. In order to use
these features in CUPL (and ABEL) you need to refer to special pin numbers and
node numbers that are given in tables in the manufacturers data sheets. You may
need the pin-number tables to reverse engineer or convert a complicated CUPL
(or ABEL) design from one format to another.
Atmel also gives skeleton headers and pin declarations for their parts in their data
sheets. Table 9.6 shows the headers and pin declarations in ABEL and CUPL
format for the ATMEL ATV2500B.
TABLE 9.6 ABEL and CUPL pin declarations for an ATMEL ATV2500B.
ABEL
CUPL
device_id device 'P2500B';
"device_id used for JEDEC filename
I1,I2,I3,I17,I18 pin 1,2,3,17,18;
O4,O5 pin 4,5 istype 'reg_d,buffer';
O6,O7 pin 6,7 istype 'com';
O4Q2,O7Q2 node 41,44 istype
'reg_d';
O6F2 node 43 istype 'com';
device V2500B;
pin [1,2,3,17,18] = [I1,I2,I3,I17,I18];
pin [7,6,5,4] = [O7,O6,O5,O4];
pinnode [41,65,44] = [O4Q2,O4Q1,O7Q2];
pinnode [43,68] = [O6Q2,O7Q1];
O7Q1 node 220 istype 'reg_d';
9.2.3 PALASM
PALASM is a PLD design language from AMD/MMI. Table 9.7 shows the
format of PALASM statements. The following simple example (a video shift
register) shows the most basic features of the PALASM 2 language:
TABLE 9.7 PALASM 2.
Statement
Example
Chip
CHIP abc 22V10
CHIP xyz USER
CLK /LD D0 D1 D2 D3 D4
Pinlist
GND NC Q4 Q3 Q2 Q1 Q0
/RST VCC
Comment
Specific PAL type
Free-form equation entry
Part of CHIP statement; PAL
pins in numerical order starting
with pin 1
String
STRING string_name 'text'
Equations
EQUATIONS
A = /B
A=B*C
A=B+C
A = B :+: C
A = B :*: C
Polarity inversion /A = /(B + C)
Assignment
A=B+C
A := B + C
Comment
A = B + C ; comment
Functional equation name.TRST
name.CLKF
name.RSTF
name.SETF
Before EQUATIONS
statement
After CHIP statement
Logical negation
Logical AND
Logical OR
Logical exclusive-OR
Logical exclusive-NOR
Same as A = B + C
Combinational assignment
Registered assignment
Comment
Output enable control
Register clock control
Register reset control
Register set control
TITLE video ; shift register
CHIP video PAL20X8
CK /LD D0 D1 D2 D3 D4 D5 D6 D7 CURS GND NC REV Q7 Q6 Q5 Q4 Q3
Q2 Q1 Q0 /RST VCC
STRING Load 'LD*/REV*/CURS*RST' ; load data
STRING LoadInv 'LD*REV*/CURS*RST' ; load inverted of data
STRING Shift '/LD*/CURS*/RST' ; shift data from MSB to LSB
EQUATIONS
/Q0 := /D0*Load+D0*LoadInv:+:/Q1*Shift+RST
/Q1 := /D1*Load+D1*LoadInv:+:/Q2*Shift+RST
/Q2 := /D2*Load+D2*LoadInv:+:/Q3*Shift+RST
/Q3 := /D3*Load+D3*LoadInv:+:/Q4*Shift+RST
/Q4 := /D4*Load+D4*LoadInv:+:/Q5*Shift+RST
/Q5 := /D5*Load+D5*LoadInv:+:/Q6*Shift+RST
/Q6 := /D6*Load+D6*LoadInv:+:/Q7*Shift+RST
/Q7 := /D7*Load+D7*LoadInv:+:Shift+RST;
The order of the pin numbers in the previous example is important; the order
must correspond to the order of pins for the DEVICE . This means that you
probably need the device data sheet in order to be able to translate a design from
PALASM to another format by hand. The alternative is to use utilities that many
PLD and FPGA companies offer that automatically translate from PALASM to
their own formats.
1. L means that the extension is used only on the LHS of an equation; R means
that the extension is used only on the RHS of an equation.
9.3 PLA Tools
We shall use the Berkeley PLA tools to illustrate logic minimization using an
example to minimize the logic required to implement the following three logic
functions:
F1 = A|B|!C; F2 = !B&C; F3 = A&B|C;
These equations are in eqntott input format. The eqntott (for equation to truth
table) program converts the input equations into a tabular format. Table 9.8
shows the truth table and eqntott output for functions F1 , F2 , and F3 that use the
six minterms: A , B , !C , !B&C , A&B , C .
TABLE 9.8 A PLA tools example.
Input (6 minterms): F1 = A|B|!C; F2 = !B&C; F3 = A&B|C;
A B C F1 F2 F3 eqntott output
espresso output
.i 3
.i 3
0 001 0 0
.o 3
.o 3
0 010 1 1
.p 6
.p 6
0 101 0 0
1-- 100
--0 100
0 111 0 1
--1 001
11- 001
1 001 0 0
-01 010
--0 100
-1- 100
-01 011
1-- 100
-11 101
11- 001
.e
1 011 1 1
1 101 0 1
1 111 0 1
.e
Output (5 minterms): F1 = A|!C|(B&C); F2 = !B&C; F3 = A&B|(!B&C)|(B&C);
This eqntott output is not really a truth table since each line corresponds to a
minterm. The output forms the input to the espresso logic-minimization program.
Table 9.9 shows the format for espresso input and output files. Table 9.10
explains the format of the input and output planes of the espresso input and
output files. The espresso output in Table 9.8 corresponds to the eqntott logic
equations on the next page.
TABLE 9.9 The format of the input and output files used by the PLA design
tool espresso.
Expression
Explanation
# comment
# must be first character on a line.
[d]
Decimal number
[s]
Character string
.i [d]
Number of input variables
.o [d]
Number of output variables
.p [d]
Number of product terms
Names of the binary-valued variables must be after .i
.ilb [s1] [s2]... [sn]
and .o .
.ob [s1] [s2]... [sn]
Names of the output functions must be after .i and .o .
.type f
Following table describes the ON set; DC set is empty.
.type fd
Following table describes the ON set and DC set.
.type fr
Following table describes the ON set and OFF set.
Following table describes the ON set, OFF set, and DC
.type fdr
set.
.e
Optional, marks the end of the PLA description.
TABLE 9.10 The format of the plane part of the input and output files for
espresso.
Plane Character Explanation
I
1
The input literal appears in the product term.
I
0
The input literal appears complemented in the product term.
I
The input literal does not appear in the product term.
O
1 or 4
This product term appears in the ON set.
O
0
This product term appears in the OFF set.
O
2 or This product term appears in the dont care set.
O
3 or ~
No meaning for the value of this function.
F1 = A|!C|(B&C); F2 = !B&C; F3 = A&B|(!B&C)|(B&C);
We see that espresso reduced the original six minterms to these five: A , A&B ,
!C , !B&C , B&C .
The Berkeley PLA tools were widely used in the 1980s. They were important
stepping stones to modern logic synthesis tools. There are so many testbenches,
examples, and old designs that used these tools that we occasionally need to
convert files in the Berkeley PLA format to formats used in new tools.
9.4 EDIF
An ASIC designer spends an increasing amount of time forcing different tools to
communicate. One standard for exchanging information between EDA tools is
the electronic design interchange format ( EDIF ). We will describe EDIF version
2 0 0. The most important features added in EDIF 3 0 0 were to handle buses, bus
rippers, and buses across schematic pages. EDIF 4 0 0 includes new extensions
for PCB and multichip module (MCM) data. The Library of Parameterized
Modules ( LPM ) standard is also based on EDIF. The newer versions of EDIF
have a richer feature set, but the ASIC industry seems to have standardized on
EDIF 2 0 0. Most EDA companies now support EDIF. The FPGA companies
Altera and Actel use EDIF as their netlist format, and Xilinx has announced its
intention to switch from its own XNF format to EDIF. We only have room for a
brief description of the EDIF format here. A complete description of the EDIF
standard is contained in the Electronic Industries Association ( EIA ) publication,
Electronic Design Interchange Format Version 2 0 0 ( ANSI/EIA Standard
548-1988) [ EDIF, 1988].
9.4.1 EDIF Syntax
The structure of EDIF is similar to the Lisp programming language or the
Postscript printer language. This makes EDIF a very hard language to read and
almost impossible to write by hand. EDIF is intended as an exchange format
between tools, not as a design-entry language. Since EDIF is so flexible each
company reads and writes different flavors of EDIF. Inevitably EDIF from one
company does not quite work when we try and use it with a tool from another
company, though this situation is improving with the gradual adoption of
EDIF 3 0 0. We need to know just enough about EDIF to be able to fix these
problems.
FIGURE 9.8 The hierarchical nature of an EDIF
file.
Figure 9.8 illustrates the hierarchy of the EDIF file. Within an EDIF file are one
or more libraries of cell descriptions. Each library contains technology
information that is used in describing the characteristics of the cells it contains.
Each cell description contains one or more user-named views of the cell. Each
view is defined as a particular viewType and contains an interface description
that identifies where the cell may be connected to and, possibly, a contents
description that identifies the components and related interconnections that make
up the cell.
The EDIF syntax consists of a series of statements in the following format:
(keywordName {form})
A left parenthesis (round bracket) is always followed by a keyword name ,
followed by one or more EDIF forms (a form is a sequence of identifiers,
primitive data, symbolic constants, or EDIF statements), ending with a right
parenthesis. If you have programmed in Lisp or Postscript, you may understand
that EDIF uses a define it before you use it approach and why there are so many
parentheses in an EDIF file.
The semantics of EDIF are defined by the EDIF keywords . Keywords are the
only types of name that can immediately follow a left parenthesis. Case is not
significant in keywords.
An EDIF identifier represents the name of an object or group of data. Identifiers
are used for name definition, name reference, keywords, and symbolic constants.
Valid EDIF identifiers consist of alphanumeric or underscore characters and must
be preceded by an ampersand ( &) if the first character is not alphabetic. The
ampersand is not considered part of the name. The length of an identifier is from
1 to 255 characters and case is not significant. Thus &clock , Clock , and clock
all represent the same EDIF name (very confusing).
Numbers in EDIF are 32-bit signed integers. Real numbers use a special EDIF
format. For example, the real number 1.4 is represented as (e 14 -1) . The e form
requires a mantissa ( 14 ) and an exponent ( -1 ). Reals are restricted to the range
± 1 ¥ 10 ± 35 . Numbers in EDIF are dimensionless and the units are determined
according to where the number occurs in the file. Coordinates and line widths are
units of distance and must be related to meters. Each coordinate value is
converted to meters by applying a scale factor . Each EDIF library has a
technology section that contains a required numberDefinition . The scale
keyword is used with the numberDefinition to relate EDIF numbers to physical
units.
Valid EDIF strings consist of sequences of ASCII characters enclosed in double
quotes. Any alphanumeric character is allowed as well as any of the following
characters: ! # $ & ' () * + , - . / : ; < = > ? @ [ \ ] ^ _ ` { | } ~ . Special
characters, such as " and % are entered as escape sequences: %number% , where
number is the integer value of the ASCII character. For example, "A quote is %
34 %" is a string with an embedded double-quote character. Blank, tab, line feed,
and carriage-return characters (white space) are used as delimiters in EDIF.
Blank and tab characters are also significant when they appear in strings.
The rename keyword can be used to create a new EDIF identifier as follows:
(cell (rename TEST_1 "test$1") ...
In this example the EDIF string contains the original name, test$1, and a new
name, TEST_1 , is created as an EDIF identifier.
9.4.2 An EDIF Netlist Example
Table 9.11 shows an EDIF netlist. This EDIF description corresponds to the
halfgate example in Chapter 8 and describes an inverter. We shall explain the
functions of the EDIF in Table 9.11 by showing a piece of the code at a time
followed by an explanation.
TABLE 9.11 EDIF file for the halfgate netlist from Chapter 8.
(edif halfgate_p
(edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 1996 7 10 22 5 10)
(program "COMPASS Design Automation -- EDIF Interface"
(version "v9r1.2 last updated 26-Mar-96")) (author "mikes")))
Every EDIF file must have an edif form. The edif form must have a name , an
edifVersion , an edifLevel , and a keywordMap . The edifVersion consists of
three integers describing the major (first number) and minor version of EDIF.
The keywordMap must have a keywordLevel . The optional status can contain a
written form that must have a timeStamp and, optionally, author or program
forms.
(library xc4000d (edifLevel 0) (technology
(The unbalanced parentheses are deliberate since we are showing segments of the
EDIF code.) The library form must have a name , edifLevel and technology . The
edifLevel is normally 0. The xc4000d library contains the cells we are using in
our schematic.
(numberDefinition ) (simulationInfo (logicValue H) (logicValue L)))
The simulationInfo form is used by simulation tools; we do not need that
information for netlist purposes for this cell. We shall discuss numberDefinition
in the next example. It is not needed in a netlist.
(cell (rename INV "inv") (cellType GENERIC)
This cell form defines the name and type of a cell inv that we are going to use in
the schematic.
(view COMPASS_mde_view (viewType NETLIST)
(interface (port I (direction INPUT)) (port O (direction OUTPUT))
(designator "@@Label")))))
The NETLIST view of this inverter cell has an input port I and an output port O .
There is also a place holder "@@Label" for the instance name of the cell.
(library working...
This begins the description of our schematic that is in our library working. The
lines that follow this library form are similar to the preamble for the cell library
xc4000d that we just explained.
(cell (rename HALFGATE_P "halfgate_p")(cellType GENERIC)
(view COMPASS_nls_view (viewType NETLIST)
This cell form is for our schematic named halfgate_p.
(interface (port myInput (direction INPUT))
(port myOutput (direction OUTPUT))
The interface form defines the names of the ports that were used in our
schematic, myInput and myOutput. At this point we have not associated these
ports with the ports of the cell INV in the cell library.
(designator "@@Label")) (contents (instance B1_i1
This gives an instance name B1_i1 to the cell in our schematic.
(viewRef COMPASS_mde_view (cellRef INV (libraryRef xc4000d))))
The cellRef form links the cell instance name B1_i1 in our schematic to the cell
INV in the library xc4000d.
(net myInput (joined (portRef myInput)
(portRef I (instanceRef B1_i1))))
The net form for myInput (and the one that follows it for myOutput) ties the net
names in our schematic to the ports I and O of the library cell INV .
(net VDD (joined )) (net VSS (joined ))))))
These forms for the global VDD and VSS nets are often handled differently by
different tools (one company might call the negative supply GND instead of VSS
, for example). This section is where you most often have to edit the EDIF.
(design HALFGATE_P (cellRef HALFGATE_P (libraryRef working))))
The design form names and places our design in library working, and completes
the EDIF description.
9.4.3 An EDIF Schematic Icon
EDIF is capable of handling many different representations. The next EDIF
example is another view of an inverter that describes how to draw the icon (the
picture that appears on the printed schematic or on the screen) shown in
Figure 9.9 . We shall examine the EDIF created by the CAD/CAM Groups
Engineering Capture System ( ECS) schematic editor.
FIGURE 9.9 An EDIF view of an inverter icon. The coordinates shown are in
EDIF units. The crosses that show the text location origins and the dotted
bounding box do not print as part of the icon.
This time we shall give more detailed explanations after each piece of EDIF
code. We shall also maintain balanced parentheses to make the structure easier to
follow. To shorten the often lengthy EDIF code, we shall use an ellipsis ( ... ) to
indicate any code that has been left out.
(edif ECS
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 1987 8 20 0 50 23)
(program "CAD/CAM Group, Inc. ECS" (Version "1"))))
(library USER ...
)
...
)
This preamble is virtually identical to the previous netlist example (and
demonstrates that EDIF is useful to store design information as software tools
come and go over many years). The first line of the file defines the name of the
file. This is followed by lines that identify the version of EDIF being used and the
highest EDIF level used in the file (each library may use its own level up to this
maximum). EDIF level 0 supports only literal constants and basic constructs.
Higher EDIF levels support parameters, expressions, and flow control constructs.
EDIF keywords may be mapped to aliases, and keyword macros may be defined
within the keywordMap form. These features are not often used in ASIC design
because of a lack of standardization. The keywordLevel 0 indicates these
capabilities are not used here. The status construct is used for administration:
when the file was created, the software used to create the file, and so on.
Following this preamble is the main section of the file, which contains design
information.
(library USER (edifLevel 0)
(technology
(numberDefinition
(scale 4 (e 254 -5) (unit distance)))
(figureGroup NORMAL
(pathWidth 0) (borderWidth 0)
(textHeight 5))
(figureGroup WIDE
(pathWidth 1) (borderWidth 1)
(textHeight 5)))
(cell 7404 ...
)
)
The technology form has a numberDefinition that defines the scaling information
(we did not use this form for a netlist, but the form must be present). The first
numberValue after scale represents EDIF numbers and the second numberValue
represents the units specified by the unit form. The EDIF unit for distance is the
meter. The numberValue can be an integer or an exponential number. The e form
has a mantissa and an exponent. In this example, within the USER library, a
distance of 4 EDIF units equals 254 ¥ 10 5 meters (or 4 EDIF units equals 0.1
inch).
After the numberDefinition in the technology form there are one or more
figureGroup definitions. A figureGroup defines drawing information such as
pathWidth , borderWidth , color , fillPattern , borderPattern , and textHeight .
The figureGroup form must have a name, which will be used later in the library
to refer back to these definitions. In this example the USER library has one
figureGroup (NORMAL) for lines and paths of zero width (the actual width will
be implementation dependent) and another figureGroup (WIDE) that will be used
for buses with a wider width (for bold lines). The borderWidth is used for
drawing filled areas such as rectangles, circles, and polygons. The pathWidth is
used for open figures such as lines (paths) and open arcs.
Following the technology section the cell forms each represent a symbol. The cell
form has a name that will appear in the names of any files produced. The
cellType form GENERIC type is required by this schematic editor. The property
form is used to list properties of the cell.
(cell 7404 (cellType GENERIC)
(property SymbolType (string "GATE"))
(view PCB_Symbol (viewType SCHEMATIC)
(interface ...
)
)
)
The SymbolType property is used to distinguish between purely graphical
symbols that do not occur in the parts list (a ground connection, for example),
gate or component symbols, and block or cell symbols (for hierarchical
schematics). The SymbolType property is a string that may be COMPONENT ,
GATE , CELL , BLOCK , or GRAPHIC . Each cell may contain view forms and
each view must have a name. Following the name of the view must be a
viewType that is either GRAPHIC or SCHEMATIC . Following the viewType is
the interface form, which contains the symbol and terminal information. The
interface form contains the actual symbol data.
(interface
(port Pin_1
(designator "2")
(direction OUTPUT)
(dcMaxFanout 50))
(port Pin_2
(designator "1")
(direction INPUT)
(dcFanoutLoad 8)
(property Cap
(string "22")))
(property Value
(string "45"))
(symbol ...
)
If the symbol has terminals, they are listed before the symbol form. The port form
defines each terminal. The required port name is used later in the symbol form to
refer back to the port. Since this example is from a PCB design, the terminals
have pin numbers that correspond to the IC package leads. The pin numbers are
defined in the designator form with the pin number as a string. The polarity of the
pin is indicated by the direction form, which may be INPUT , OUTPUT , or
INOUT . If the pin is an output pin, its Drive can be represented by dcMaxFanout
and if it is an input pin its Load can be represented by dcFanoutLoad . The port
form can also contain forms unused , dcMaxFanin , dcFaninLoad , acLoad , and
portDelay . All other attributes for pins besides PinNumber , Polarity , Load , and
Drive are contained in the property form.
An attribute string follows the name of the property in the string form. In this
example port Pin_2 has a property Cap whose value is 22. This is the input
capacitance of the inverter, but the interpretation and use of this value depends on
the tools. In ASIC design pins do not have pin numbers, so designator is not used.
Instead, the pin names use the property form. So (property NetName (string "1"))
would replace the (designator "1") in this example on Pin_2 . The interface form
may also contain attributes of the symbol.
Symbol attributes are similar to pin attributes. In this example the property name
Value has an attribute string "45" . The names occurring in the property form
may be referenced later in the interface under the symbol form to refer back to
the property .
(symbol
(boundingBox (rectangle (pt 0 0) (pt 76 -32)))
(portImplementation Pin_1
(connectLocation (figure NORMAL (dot (pt 60 -16)))))
(keywordDisplay designator
(display NORMAL
(justify LOWERCENTER) (origin (pt 60 -14)))))
(portImplementation Pin_2
(connectLocation (figure NORMAL (dot (pt 0 -16)))))
(keywordDisplay designator
(display NORMAL
(justify LOWERCENTER) (origin (pt 0 -14)))))
(keywordDisplay cell
(display NORMAL (justify CENTERLEFT) (origin (pt 25 -5))))
(keywordDisplay instance
(display NORMAL
(justify CENTERLEFT) (origin (pt 36 -28))))
(keywordDisplay designator
(display (figureGroupOverride NORMAL (textHeight 7))
(justify CENTERLEFT) (origin (pt 13 -16))))
(propertyDisplay Value
(display (figureGroupOverride NORMAL (textHeight 9))
(justify CENTERRIGHT) (origin (pt 76 -24))))
(figure ... )
)
The interface contains a symbol that contains the pin locations and graphical
information about the icon. The optional boundingBox form encloses all the
graphical data. The x- and y-locations of two opposite corners of the bounding
rectangle use the pt form. The scale section of the numberDefinition from the
technology section of the library determines the units of these coordinates. The pt
construct is used to specify coordinate locations in EDIF. The keyword pt must
be followed by the x-location and the y-location. For example: (pt 100 200) is at
x = 100, y = 200.
● Each pin in the symbol is given a location using a portImplementation .
●
●
●
The portImplementation refers back to the port defined in the
interface .
The connectLocation defines the point to connect to the pin.
The connectLocation is specified as a figure , a dot with a single pt for its
location.
(symbol
( ...
(figure WIDE
(path (pointList (pt 12 0) (pt 12 -32)))
(path (pointList (pt 12 -32) (pt 44 -16)))
(path (pointList (pt 12 0) (pt 44 -16))))
(figure NORMAL
(path (pointList (pt 48 -16) (pt 60 -16)))
(circle (pt 44 -16) (pt 48 -16))
(path (pointList (pt 0 -16) (pt 12 -16))))
(annotate
(stringDisplay "INV"
(display NORMAL
(justify CENTERLEFT) (origin (pt 12 -12)))))
)
The figure form has either a name, previously defined as a figureGroup in the
technology section, or a figureGroupOverride form. The figure has all the
attributes ( pathWidth , borderWidth , and so on) that were defined in the
figureGroup unless they are specifically overridden with a figureGroupOverride .
Other objects that may appear in a figure are: circle , openShape , path , polygon ,
rectangle , and shape . Most schematic editors use a grid, and the pins are only
allowed to occur on grid .
A portImplementation can contain a keywordDisplay or a propertyDisplay for the
location to display the pin number or pin name. For a GATE or COMPONENT ,
keywordDisplay will display the designator (pin number), and designator is the
only keyword that can be displayed. For a BLOCK or CELL , propertyDisplay
will display the NetName . The display form displays text in the same way that
the figure displays graphics. The display must have either a name previously
defined as a figureGroup in the technology section or a figureGroupOverride
form. The display will have all the attributes ( textHeight for example) defined in
the figureGroup unless they are overridden with a figureGroupOverride .
A symbolic constant is an EDIF name with a predefined meaning. For example,
LOWERLEFT is used to specify text justification. The display form can contain
a justify to override the default LOWERLEFT . The display can also contain an
orientation that overrides the default R0 (zero rotation). The choices for
orientation are rotations ( R0, R90, R180, R270 ), mirror about axis ( MX, MY ),
and mirror with rotation ( MXR90, MYR90 ). The display can contain an origin
to override the default (pt 0 0) .
The symbol itself can have either keywordDisplay or propertyDisplay forms such
as the ones in the portImplementation . The choices for keywordDisplay are: cell
for attribute Type , instance for attribute InstName , and designator for attribute
RefDes . In the preceding example an attribute window currently mapped to
attribute Value is displayed at location (76, 24) using right-justified text, and a
font size is set with (textHeight 9) .
The graphical data in the symbol are contained in figure forms. The path form
must contain pointList with two or more points. The figure may also contain a
rectangle or circle . Two points in a rectangle define the opposite corners. Two
points in a circle represent opposite ends of the diameter. In this example a figure
from figureGroup WIDE has three lines representing the triangle of the inverter
symbol.
Arcs use the openShape form. The openShape must contain a curve that contains
an arc with three points. The three points in an arc correspond to the starting
point, any point on the arc, and the end point. For example, (openShape (curve
(arc (pt - 5 0) (pt 0 5 ) (pt 5 0)))) is an arc with a radius of 5, centered at the
origin. Arcs and lines use the pathWidth from the figureGroup or
figureGroupOverride ; circles and rectangles use borderWidth .
The fixed text for a symbol uses annotate forms. The stringDisplay in annotate
contains the text as a string. The stringDisplay contains a display with the
textHeight , justification , and location . The symbol form can contain multiple
figure and annotate forms.
9.4.4 An EDIF Example
In this section we shall illustrate the use of EDIF in translating a cell library from
one set of tools to anotherfrom a Compass Design Automation cell library to the
Cadence schematic-entry tools. The code in Table 9.12 shows the EDIF
description of the symbol for a two-input AND gate, an02d1, from the Compass
cell library.
TABLE 9.12 EDIF file for a Compass standard-cell schematic icon.
The Cadence schematic tools do contain a procedure, EDIFIN, that reads the
Compass EDIF files. This procedure works, but, as we shall see, results in some
problems when you use the icons in the Cadence schematic-entry tool. Instead we
shall make some changes to the original files before we use EDIFIN to transfer
the information to the Cadence database, cdba .
The original Compass EDIF file contains a figureGroup for each of the following
four EDIF cell symbols:
connector_FG icon_FG instance_FG net_FG bus_FG
The EDIFIN application translates each figureGroup to a Cadence layerpurpose
pair definition that must be defined in the Cadence technology file associated
with the library. If we use the original EDIF file with EDIFIN this results in the
automatic modification of the Cadence technology file to define layer names,
purposes, and the required properties to enable use of the figureGroup names.
This results in non-Cadence layer names in the Cadence database.
First then, we need to modify the EDIF file to use the standard Cadence layer
names shown in Table 9.13 . These layer names and their associated purposes
and properties are defined in the default Cadence technology file, default.tf .
There is one more layer name in the Compass files ( bus_FG figureGroup ), but
since this is not used in the library we can remove this definition from the EDIF
input file.
TABLE 9.13 Compass and corresponding Cadence figureGroup names.
Compass name
Cadence name Compass name Cadence name
connector_FG
pin
net_FG
wire
icon_FG
device
bus_FG
not used
instance_FG
instance
Internal scaling differences lead to giant characters in the Cadence tools if we use
the textHeight of 30 defined in the EDIF file. Reducing the textHeight to 5 results
in a reasonable text height.
The EDIF numberDefinition construct, together with the scale construct, defines
measurement scaling in an EDIF file. In a Cadence schematic EDIF file the
numberDefinition and scale construct is determined by an entry in the associated
library technology file that defines the edifUnit to userUnit ratio. This ratio
affects the printed size of an icon.
For example, the distance defined by the following path construct is 10 EDIF
units:
(path (pointlist (pt 0 0) (pt 0 10)))
What is the length of 10 EDIF units? The numberDefinition and scale construct
associates EDIF units with a physical dimension. The following construct
(numberDefinition (scale 100 (e 25400 -6) unit DISTANCE))
specifies that 100 EDIF units equal 25400 ¥ 10 6 m or approximately 1 inch.
Cadence defines schematic measurements in inches by defining the userUnit
property of the affected viewType or viewName as inch in the Cadence
technology file. The Compass EDIF files do not provide values for the
numberDefinition and scale construct, and the Cadence tools default to a value of
160 EDIF units to 1 user unit. We thus need to add a numberDefinition and scale
construct to the Compass EDIF file to control the printed size of icons.
The EDIF file defines blank label placeholders for each cell using the EDIF
property construct. Cadence EDIFIN does recognize and translate EDIF
properties, but to attach a label property to a cellview object it must be defined
(not blank) and identified as a property using the EDIF owner construct in the
EDIF file. Since the intent of a placeholder is to hold an empty spot for later use
and since Cadence Composer (the schematic-entry tool) supports label additions
to instantiated icons, we can remove the EDIF label property construct in each
cell and the associated propertyDisplay construct from the Compass file.
There is a problem that we need to resolve with naming. This is a problem that
sooner or later everyone must tackle in ASIC design case sensitivity .
In EDIF, input and output pins are called ports and they are identified using
portImplementation constructs. In order that the ports of a particular cell
icon_view are correctly associated with the ports in the related functional, layout,
and abstract views, they must all have the same name. The Cadence tools are case
sensitive in this respect. The Verilog and CIF files corresponding to each cell in
the Compass library use lowercase names for each port of a given cell, whereas
the EDIF file uses uppercase. The EDIFIN translator allows the case of cell,
view, and port names to be automatically changed on translation. Thus pin names
such as ' A1 ' become ' a1 ' and the original view name ' Icon_view ' becomes '
icon_view '.
The boundingBox construct defines a bounding box around a symbol (icon).
Schematic-capture tools use this to implement various functions. The Cadence
Composer tool, for example, uses the bounding box to control the wiring between
cells and as a highlight box when selecting components of a schematic. Compass
uses a large boundingBox definition for the cells to allow space for long
hierarchical names. Figure 9.10 (a) shows the original an02d1 cell bounding box
that is larger than the cell icon.
FIGURE 9.10 The bounding box problem. (a) The original bounding box for the
an02d1 icon. (b) Problems in Cadence Composer due to overlapping bounding
boxes. (c) A shrink-wrapped bounding box created using SKILL.
Icons with large bounding boxes create two problems in Composer. Highlighting
all or part of a complex design consisting of many closely spaced cells results in
a confusion of overlapped highlight boxes. Also, large boxes force strange wiring
patterns between cells that are placed too closely together when Composer's
automatic routing algorithm is used. Figure 9.10 (b) shows an example of this
problem.
There are two solutions to the bounding-box problem. We could modify each
boundingBox definition in the original EDIF file before translation to conform to
the outline of the icon. This involves identifying the outline of each icon in the
EDIF file and is difficult. A simpler approach is to use the Cadence tool
programming language, SKILL. SKILL provides direct access to the Cadence
database, cdba , in order to modify and create objects. Using SKILL you can use
a batch file to call functions normally accessed interactively. The solution to the
bounding box problem is:
1. Use EDIFIN to create the views in the Cadence database, cdba .
2. Use the schCreateInstBox() command on each icon_view object to
eliminate the original bounding box and create a new, minimum-sized,
bounding box that is shrink-wrapped to each icon.
Figure 9.10 (c) shows the results of this process. This modification fixes the
problems with highlighting and wiring in Cadence Composer.
This completes the steps required to translate the schematic icons from one set of
tools to another. The process can be automated in three ways:
● Write UNIX sed and awk scripts to make the changes to the EDIF file
before using EDIFIN and SKILL.
● Write custom C programs to make the changes to the EDIF file and then
proceed as in the first option.
● Perform all the work using SKILL.
The last approach is the most elegant and most easily maintained but is the most
difficult to implement (mostly because of the time required to learn SKILL). The
whole project took several weeks (including the time it took to learn how to use
each of the tools). This is typical of the problems you face when trying to convert
data from one system to another.
9.5 CFI Design Representation
The CAD Framework Initiative ( CFI ) is an independent nonprofit organization
working on the creation of standards for the electronic CAD industry. One of the
areas in which CFI is working is the definition of standards for design
representation ( DR ). The CFI 1.0 standard [ CFI, 1992] has tackled the
problems of ambiguity in the area of definitions and terms for schematics by
defining an information model ( IM ) for electrical connectivity information.
What this means is that a group of engineers got together and proposed a standard
way of using the terms and definitions that we have discussed. There are good
things and bad things about standards, and one aspect of the CFI 1.0 DR standard
illustrates this point. A good thing about the CFI 1.0 DR standard is that it
precisely defines what we mean by terms and definitions in schematics, for
example. A bad thing about the CFI DR standard is that in order to be precise it
introduces yet more terms that are difficult to understand. A very brief discussion
of the CFI 1.0 DR standard is included here, at the end of this chapter, for several
reasons:
● It helps to solidify the concepts of the terms and definitions such as cell,
net, and instance that we have already discussed. However, there are
additional new concepts and terms to define in order to present the
standard model, so this is not a good way to introduce schematic
terminology.
● The ASIC design engineer is becoming more of a programmer and less of
a circuit designer. This trend shows no sign of stopping as ASICs grow
larger and systems more complex. A precise understanding of how tools
operate and interact is becoming increasingly important.
9.5.1 CFI Connectivity Model
The CFI connectivity model is defined using the EXPRESS language and its
graphical equivalent EXPRESS-G . EXPRESS is an International Standards
Organization (ISO) standard [ EXPRESS, 1991]. EDIF 3 0 0 and higher also use
EXPRESS as the internal formal description of the language. EXPRESS is used
to define objects and their relationships. Figure 9.11 shows some simple
examples of the EXPRESS-G notation.
FIGURE 9.11 Examples of EXPRESS-G. (a) Each day in January has a number
from 1 to 31. (b) A shopping list may contain a list of items. (c) An EXPRESS-G
model for a family.
The following EXPRESS code (a schema ) is equivalent to the EXPRESS-G
family model shown in Figure 9.11 (c):
SCHEMA family_model;
ENTITY person
ABSTRACT SUPERTYPE OF (ONEOF (man, woman, child));
name: STRING;
date of birth: STRING;
END_ENTITY;
ENTITY man
SUBTYPE OF (person);
wife: SET[0:1] OF woman;
children: SET[0:?] OF child;
END_ENTITY;
ENTITY woman
SUBTYPE OF (person);
husband: SET[0:1] OF man;
children: SET[0:?] OF child;
END_ENTITY;
ENTITY child
SUBTYPE OF (person);
father: man;
mother: woman;
END_ENTITY;
END_SCHEMA;
This EXPRESS description is a formal way of saying the following:
● Men, women, and children are people.
● A man can have one woman as a wife, but does not have to.
● A wife can have one man as a husband, but does not have to.
● A man or a woman can have several children.
● A child has one father and one mother.
Computers can deal more easily with the formal language version of these
statements. The formal language and graphical forms are more precise for very
complex models.
Figure 9.12 shows the basic structure of the CFI 1.0.0 Base Connectivity Model (
BCM ). The actual EXPRESS-G diagram for the BCM defined in the CFI 1.0.0
standard is only a little more complicated than Figure 9.12 (containing 21 boxes
or types rather than just six). The extra types are used for bundles (a group of
nets) and different views of cells (other than the netlist view).
FIGURE 9.12 The original five-box model of electrical connectivity. There are
actually six boxes or types in this figure; the Library type was added later.
Figure 9.12 says the following (presents as used in Figure 9.12 is the Express
jargon for have):
● A library contains cells.
● Cells have ports, contain nets, and can contain other cells.
● Cell instances are copies of a cell and have port instances.
● A port instance is a copy of the port in the library cell.
● You connect to a port using a net.
● Nets connect port instances together.
Once you understand Figure 9.12 you will see that it replaces the first half of this
chapter. Unfortunately you have to read the first half of this chapter to understand
Figure 9.12 .
9.6 Summary
The important concepts that we covered in this chapter are:
● Schematic entry using a cell library
● Cells and cell instances, nets and ports
● Bus naming, vectored instances in datapath
● Hierarchy
● Editing cells
● PLD languages: ABEL, PALASM, and CUPL
● Logic minimization
● The functions of EDIF
● CFI representation of design information
9.7 Problems
9.1 (EDIF description)
● a. (5 min.) Write an EDIF description for an icon for an inverter (just the
input and output wires, a triangle, and a bubble). What problems do you
face and what assumptions did you make?
● b. (30 min.+) Try and import your symbol into your schematic-entry tool.
If you fail (as you might) explain what the problem is and suggest a
direction of attack. Hint: If you can, try Problem 9.2 first.
9.2 (EDIF inverter, 15 min.) If you have access to a tool that generates EDIF for
the icons, write out the EDIF for an inverter icon. Explain the code.
9.3 (EDIF netlist, 20 min.) Starting with an empty directory and using a
schematic editor (such as Viewlogic) draw a schematic with a single inverter
(from any cell library).
● a. List the files that are created in the directory.
● b. Print each one (check first to make sure it is ASCII, not binary).
● c. Try and explain the contents.
9.4 (Minitutorial, 60 min.) Write a minitutorial (no more than five pages) that
explains how to set up your system (location and nature of any start-up files such
as .ini files for Viewlogic and so on); how to choose or change a library (for cell
icons); how to choose cells, instantiate, label, and connect them; how to select,
copy and delete symbols; and how to save a schematic. Use a single inverter
connected to an input and output pad as an example.
9.5 (Icons, 30 min.) With an example show how to edit and create a symbol icon.
Make a triangular icon (the same size as an inverter in your library but without a
bubble) for a series connection of two inverters and call it myBuffer .
9.6 (Buses, 30 min.)
● a. Create an example of a 16-bit bus: connect 8 inverters to bit zero (the
MSB or leftmost bit) and bits 1016 (as if we were taking the sign bit, bit
zero, and the seven least-significant bits from a 16-bit signed number).
Name the inverter connected to the sign bit, SIGN . Name the other
inverters BIT0 through BIT7 .
● b. Write the netlist as an EDIF file, number the lines, and explain the
contents by referencing line numbers.
9.7 (VDD and VSS, 30 min.) Using a simple example of two inverters (one with
input connected to VDD, the other with input connected to VSS or GND) explain
how your schematic-entry system handles global power and ground nets and their
connection to cell pins. Can you connect VDD or VSS to an output pin in your
system? If your schematic software has a netlist screener, try it on this example.
9.8 (Hierarchy, 30 min.) Create a very simple hierarchical cell. The lowest level,
named bottom , contains a single inverter (named invB ). The highest level,
called top , contains another inverter, invT , whose input is connected to the
output of cell bottom . Write out the netlist (in internal and EDIF format) and
explain how the tool labels a hierarchical cell.
9.9 (Vectored instances, 30 min.) Create a vectored instance of eight inverters,
inv0 through inv7 . Write the netlist in internal and EDIF form and explain the
contents.
9.10 (Dangling wires, 30 min.) Create a cell, dangle1 , containing two inverters,
inv1 and inv2 . Connect the input of inv1 to an external connector, in1 , and the
output of inv2 to an external connector out2 . Write the netlist and explain what
happens to the unlabeled and unused nets. If you have a netlist screener, run it on
this example.
9.11 (PLD languages, 60 min.) Conduct a Web search on ABEL, CUPL, or
PALASM (start by searching for Logical Devices not ABEL). Try and find
examples of these files and write an explanation of their function using the
descriptions of these languages in this chapter.
9.12 (EDIF 3 0 0, 10 min.) Download the EDIF 3 0 0 example schematic file
from http://www.edif.org/edif/workshop.edf and see if your EDIF reader will
accept it. What is it?
9.13 (EXPRESS-G, 15 min.) Draw an EXPRESS-G diagram for the government
of your country. For example, in the United States you would start with the
president and the White House and work down through the House and Senate,
showing the senators and congressional representatives. In the United Kingdom
you would draw the prime minister, the House of Commons, and House of Lords
with the various MPs.
9.14 (ABEL PCI Target) (10 min.) Download the Xilinx Application Note,
Designing Flexible PCI Interfaces with Xilinx EPLDs, January 1995 (
pci_epld.pdf at www.xilinx.com ). The Appendix of this App. Note contains the
ABEL source code for a PCI Bus Interface Target. The code is long but
straightforward; most of it describes the next-state transitions for the
bus-controller state machine. Extract the ABEL source code using Adobe
Acrobat. Hint: This is not easy; Acrobat does a poor job of selecting text; you
will lose many semicolons at the end of lines that you will have to add by hand.
Use Replace... to search for end-of-line, "^p" , and replace by " ; ^p" in Word. (60
min.+) Try to convert this code to a system where you can compile it. You may
need conversion utilities to do this. For example Altera ( www.altera.com ) has
utilities ( EAU018.EXE and EAU019.EXE located at ftp.altera.com/pub ) to
convert from ABEL 4.0 to AHDL.
9.15 (CUPL, 60 min.) Download and install the CUPL demonstration package
from http://www.protel.com/download.htm . Write a two-page help sheet on what
you did, where the software is installed, and how to run it.
9.16 (PALASM) (30 min.) Download and install PALASM4 v1.5 from the AMD
Web site at ftp://ftp.amd.com/pub/pld/software/palasm .
9.17 (CUPL)
● a. (15 min.) Check the equations in the CUPL code for the 4-bit counter in
Section 9.2 .
●
●
b. (10 min.) Add a count-enable signal to the code.
c. (30 min.) If you have access to CUPL, compile your answer.
9.18 (EDIF)
● a. (30 min.) Using the syntax definitions below and the example schematic
icon shown in Table 9.12 to help you, stitch back together the EDIF
definition for the 7404 inverter symbol used as an example in Section 9.4.3
.
● b. (60 min.+) Try to import the EDIF into your schematic entry system.
Comment on any problems and how you attempted to resolve them
(including failures).
The EDIF Reference Manual [ EDIF, 1988] uses the following metasyntax rules:
[optional] <at most once> {may be repeated zero or more times}
{this|that} indicates any number of this or that in any order
syntactic names are italic
literal words are bold
SYMBOLIC constants are uppercase
IdentifierNameDef means the name is being defined
IdentifierNameRef means the name is being referenced
The syntax definitions of the most common EDIF constructs for schematics are
as follows:
(edif edifFileNameDef
edifVersion
edifLevel
keywordMap
{<status>|external|library|design|comment|userdata} )
(library libraryNameDef
edifLevel
technology
{<status>|cell|comment|userdata} )
(technology numberDefinition
{figureGroup|fabricate|
<simulationInfos>|<physicalDesignRule>|comment|userdata} )
(cell cellNameDef
cellType
{<status>|view|<viewMap>|property|comment|userdata} )
(view viewNameDef
viewType
interface
{<status>|<contents>|comment|property|userdata} )
(interface
{port|portBundle|<symbol>|<protectionFrame>|
<arrayRelatedInfo>|parameter|joined|mustJoin|weakJoined|
permutable|timing|simulate|<designator>|property|comment|userdata} )
(contents
{instance|offPageConnector|figure|section|
net|netBundle|page|commentGraphics|portImplementation|
timing|simulate|when|follow|logicPort|<boundingBox>|
comment|userdata} )
(viewMap
{portMap|portBackAnnotate|instanceMap|instanceBackAnnotate|
netMap|netBackAnnotate|comment|userdata} )
9.8 Bibliography
The data books from AMD, Atmel, and other PLD manufacturers are excellent
sources of tutorials, examples, and information on PLD design. The EDIF
tutorials produced by the EIA [ EDIF, 1988, 1989] are hard to find, but there are
few other texts or sources that explain EDIF. EDIF does have a World Wide Web
site at http://www.edif.org . The EDIF Technical Centre at the University of
Manchester ( http://www.cs.man.ac.uk/cad , I shall refer to this as ~EDIF ) serves
as a resource center for EDIF, including the formal information models of the
EDIF language in EXPRESS format and the BNF definitions of the language
syntax. There is a hypertext version of an EDIF 3 0 0 schematic file with
hypertext links at ~EDIF/EDIFTechnicalCenter/software . CFI has a home page
and links to other sites at http://www.cfi.org .
PALASM4 v1.5 is available as freeware from AMD at
ftp://ftp.amd.com/pub/pld/software/palasm . The Data I/O home page at
http://www.data-io.com is devoted mainly to Synario. The Viewlogic home page
is http://www.viewlogic.com . Capilano Computing has a Web page at
http://www.capilano.com with DesignWorks and MacABEL software. Protel (
http://www.protel.com/download.htm ) has Windows-based schematic-entry
tools for FPGAs and a CUPL demonstration package. Logical Devices has a site
at http://www.logicaldevices.com . Atmel has several demonstration and code
examples for ABEL and CUPL at ftp://www.atmel.com/pub/atmel .
9.9 References
Page numbers in brackets after a reference indicate its location in the chapter
body.
CFI Standards for Electronic Design Automation Release 1.0. 1992. CFI
published a four-volume set in 1992, ISBN 1-882750-00-4 (set). The first
volume, ISBN 1-882750-01-2, is approximately 300 pages and contains a brief
introduction (approximately 10 pages) and the Electrical Connectivity model.
Unfortunately two of the volumes were labeled as volume three. The (first) third
volume is the Tool Encapsulation Specification, ISBN 1-882750-03-09
(approximately 100 pages). The (second) third volume, ISBN 1-882750-02-0,
covers the Inter-Tool Communication Programming Interface (approximately
150 pages). The fourth volume, ISBN 1-882750-04-7, is approximately 100
pages long and covers the Computing Environment Services requirement [
reference location ].
EDIF is maintained by the EIA, EIA Standards Sales Office, 2001 Pennsylvania
Ave., N.W., Washington, DC 20006, (202) 457-4966 [ reference location ]:
EDIF Steering Committee. 1988. EDIF Reference Manual Version 2.0.0.
Washington, DC: Electronic Industries Association. ISBN 0-7908-0000-4.
EDIF Steering Committee. 1988. Introduction to EDIF. Washington, DC:
Electronic Industries Association. ISBN 0-7908-0001-2.
EDIF Steering Committee. 1989. EDIF Connectivity. Washington, DC:
Electronic Industries Association. ISBN 0-7908-0002-0.
EDIF Schematic Technical Subcommittee. 1989. Using EDIF 2.0.0 for
Schematic Transfer. Washington, DC: Electronic Industries Association.
EXPRESS Language Reference Manual. ISO TC184/SC4/WG5 Document N14,
March 29, 1991 [ reference location ].
L ast E d ited by S P 14112 0 0 4
CHAPTER 10
VHDL
The U.S. Department of Defense (DoD) supported the development of VHDL
(VHSIC hardware description language) as part of the VHSIC (very high-speed
IC) program in the early 1980s. The companies in the VHSIC program found
they needed something more than schematic entry to describe large ASICs, and
proposed the creation of a hardware description language. VHDL was then
handed over to the Institute of Electrical and Electronics Engineers (IEEE) in
order to develop and approve the IEEE Standard 1076-1987. 1 As part of its
standardization process the DoD has specified the use of VHDL as the
documentation, simulation, and verification medium for ASICs (MIL-STD-454).
Partly for this reason VHDL has gained rapid acceptance, initially for description
and documentation, and then for design entry, simulation, and synthesis as well.
The first revision of the 1076 standard was approved in 1993. References to the
VHDL Language Reference Manual (LRM) in this chapter--[VHDL 87LRM2.1,
93LRM2.2] for example--point to the 1987 and 1993 versions of the LRM [IEEE,
1076-1987 and 1076-1993]. The prefixes 87 and 93 are omitted if the references
are the same in both editions. Technically 1076-1987 (known as VHDL-87) is
now obsolete and replaced by 1076-1993 (known as VHDL-93). Except for code
that is marked 'VHDL-93 only' the examples in this chapter can be analyzed
(the VHDL word for "compiled") and simulated using both VHDL-87 and
VHDL-93 systems.
1. Some of the material in this chapter is reprinted with permission from IEEE
Std 1076-1993, © 1993 IEEE. All rights reserved.
10.1 A Counter
The following VHDL model describes an electrical "black box" that contains a 50 MHz clock generator and a
counter. The counter increments on the negative edge of the clock, counting from zero to seven, and then begins
at zero again. The model contains separate processes that execute at the same time as each other. Modeling
concurrent execution is the major difference between HDLs and computer programming languages such as C.
entity Counter_1 is end; -- declare a "black box" called Counter_1
library STD; use STD.TEXTIO.all; -- we need this library to print
architecture Behave_1 of Counter_1 is -- describe the "black box"
-- declare a signal for the clock, type BIT, initial value '0'
signal Clock : BIT := '0';
-- declare a signal for the count, type INTEGER, initial value 0
signal Count : INTEGER := 0;
begin
process begin -- process to generate the clock
wait for 10 ns; -- a delay of 10 ns is half the clock cycle
Clock <= not Clock;
if (now > 340 ns) then wait; end if; -- stop after 340 ns
end process;
-- process to do the counting, runs concurrently with other processes
process begin
-- wait here until the clock goes from 1 to 0
wait until (Clock = '0');
-- now handle the counting
if (Count = 7) then Count <= 0;
else Count <= Count + 1;
end if;
end process;
process (Count) variable L: LINE; begin -- process to print
write(L, now); write(L, STRING'(" Count="));
write(L, Count); writeline(output, L);
end process;
end;
Throughout this book VHDL keywords (reserved words that are part of the language) are shown in bold type in
code examples (but not in the text). The code examples use the bold keywords to improve readability. VHDL
code is often lengthy and the code in this book is always complete wherever possible. In order to save space
many of the code examples do not use the conventional spacing and formatting that is normally considered
good practice. So "Do as I say and not as I do."
The steps to simulate the model and the printed results for Counter_1 using the Model Technology
V-System/Plus common-kernel simulator are as follows:
> vlib work
> vcom Counter_1.vhd
Model Technology VCOM V-System VHDL/Verilog 4.5b
-- Loading package standard
-- Compiling entity counter_1
-- Loading package textio
-- Compiling architecture behave_1 of counter_1
> vsim -c counter_1
# Loading /../std.standard
# Loading /../std.textio(body)
# Loading work.counter_1(behave_1)
VSIM 1> run 500
# 0 ns Count=0
# 20 ns Count=1
(...15 lines omitted...)
# 340 ns Count=1
VSIM 2> quit
10.2 A 4-bit Multiplier
This section presents a more complex VHDL example to motivate the study of the syntax and semantics of VHDL in the rest of this chapter.
10.2.1 An 8-bit Adder
Table 10.1 shows a VHDL model for the full adder that we described in Section 2.6, "Datapath Logic Cells." Table 10.2 shows a VHDL
model for an 8-bit ripple-carry adder that uses eight instances of the full adder.
TABLE 10.1 A full adder.
entity Full_Adder is
generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns);
port (X, Y, Cin: in BIT; Cout, Sum: out BIT);
end Full_Adder;
architecture Behave of Full_Adder is
Timing:
begin
Sum <= X xor Y xor Cin after TS;
TS (Input to Sum) = 0.1 1 ns
Cout <= (X and Y) or (X and Cin) or (Y and Cin) after TC;
TC (Input to Cout) = 0.1 ns
end;
TABLE 10.2 An 8-bit ripple-carry adder.
entity Adder8 is
port (A, B: in BIT_VECTOR(7 downto 0);
Cin: in BIT; Cout: out BIT;
Sum: out BIT_VECTOR(7 downto 0));
end Adder8;
architecture Structure of Adder8 is
component Full_Adder
port (X, Y, Cin: in BIT; Cout, Sum: out BIT);
end component;
signal C: BIT_VECTOR(7 downto 0);
begin
Stages: for i in 7 downto 0 generate
LowBit: if i = 0 generate
FA:Full_Adder port map (A(0),B(0),Cin,C(0),Sum(0));
end generate;
OtherBits: if i /= 0 generate
FA:Full_Adder port map
(A(i),B(i),C(i-1),C(i),Sum(i));
end generate;
end generate;
Cout <= C(7);
end;
10.2.2 A Register Accumulator
Table 10.3 shows a VHDL model for a positive-edge-triggered D flip-flop with an active-high asynchronous clear. Table 10.4 shows an 8-bit
register that uses this D flip-flop model (this model only provides the Q output from the register and leaves the QN flip-flop outputs
unconnected).
TABLE 10.3 Positive-edge-triggered D flip-flop with asynchronous clear.
entity DFFClr is
generic(TRQ : TIME := 2 ns; TCQ : TIME := 2 ns);
port (CLR, CLK, D : in BIT; Q, QB : out BIT);
end;
architecture Behave of DFFClr is
signal Qi : BIT;
begin QB <= not Qi; Q <= Qi;
process (CLR, CLK) begin
if CLR = '1' then Qi <= '0' after TRQ;
elsif CLK'EVENT and CLK = '1'
Timing:
then Qi <= D after TCQ;
TRQ (CLR to Q/QN) = 2 ns
end if;
end process;
TCQ (CLK to Q/QN) = 2 ns
end;
TABLE 10.4 An 8-bit register.
entity Register8 is
port (D : in BIT_VECTOR(7 downto 0);
Clk, Clr: in BIT ; Q : out BIT_VECTOR(7 downto 0));
end;
architecture Structure of Register8 is
component DFFClr
port (Clr, Clk, D : in BIT; Q, QB : out BIT);
end component;
begin
STAGES: for i in 7 downto 0 generate
8-bit register. Uses
FF: DFFClr port map (Clr, Clk, D(i), Q(i), open);
DFFClr positive edge-triggered flip-flop
end generate;
model.
end;
Table 10.5 shows a model for a datapath multiplexer that consists of eight 2:1 multiplexers with a common select input (this select signal
would normally be a control signal in a datapath). The multiplier will use the register and multiplexer components to implement a register
accumulator.
TABLE 10.5
An 8-bit multiplexer.
entity Mux8 is
generic (TPD : TIME := 1 ns);
port (A, B : in BIT_VECTOR (7 downto 0);
Sel : in BIT := '0'; Y : out BIT_VECTOR (7 downto 0));
end;
Eight 2:1 MUXs with
architecture Behave of Mux8 is
single select input.
begin
Y <= A after TPD when Sel = '1' else B after TPD;
Timing:
end;
TPD (input to Y) = 1 ns
10.2.3 Zero Detector
Table 10.6 shows a model for a variable-width zero detector that accepts a bus of any width and will produce a single-bit output of '1' if all
input bits are zero.
TABLE 10.6
A zero detector.
entity AllZero is
generic (TPD : TIME := 1 ns);
port (X : BIT_VECTOR; F : out BIT );
end;
architecture Behave of AllZero is
begin process (X) begin F <= '1' after TPD;
for j in X'RANGE loop
Variable-width zero detector.
if X(j) = '1' then F <= '0' after TPD; end if;
Timing:
end loop;
end process;
TPD (X to F) = 1 ns
end;
10.2.4 A Shift Register
Table 10.7 shows a variable-width shift register that shifts (left or right under input control, DIR ) on the positive edge of the clock, CLK ,
gated by a shift enable, SH . The parallel load, LD , is synchronous and aligns the input LSB to the LSB of the output, filling unused MSBs
with zero. Bits vacated during shifts are zero filled. The clear, CLR , is asynchronous.
TABLE 10.7
A variable-width shift register.
entity ShiftN is
generic (TCQ : TIME := 0.3 ns; TLQ : TIME := 0.5 ns;
TSQ : TIME := 0.7 ns);
port(CLK, CLR, LD, SH, DIR: in BIT;
D: in BIT_VECTOR; Q: out BIT_VECTOR);
begin assert (D'LENGTH <= Q'LENGTH)
report "D wider than output Q" severity Failure;
end ShiftN;
architecture Behave of ShiftN is
begin Shift: process (CLR, CLK)
subtype InB is NATURAL range D'LENGTH-1 downto 0;
subtype OutB is NATURAL range Q'LENGTH-1 downto 0;
variable St: BIT_VECTOR(OutB);
begin
if CLR = '1' then
St := (others => '0'); Q <= St after TCQ;
elsif CLK'EVENT and CLK='1' then
if LD = '1' then
St := (others => '0');
St(InB) := D;
Q <= St after TLQ;
elsif SH = '1' then
case DIR is
when '0' => St := '0' & St(St'LEFT downto 1);
when '1' => St := St(St'LEFT-1 downto 0) & '0';
end case;
Q <= St after TSQ;
end if;
end if;
end process;
end;
CLK Clock
CLR Clear, active
high
LD Load, active
high
SH Shift, active
high
DIR Direction, 1 =
left
D Data in
Q Data out
Variable-width
shift register. Input
width must be less
than output width.
Output is
left-shifted or
right-shifted under
control of DIR.
Unused MSBs are
zero-padded during
load. Clear is
asynchronous. Load
is synchronous.
Timing:
TCQ (CLR to Q) =
0.3 ns
TLQ (LD to Q) =
0.5 ns
TSQ (SH to Q) = 0.
7 ns
10.2.5 A State Machine
To multiply two binary numbers A and B , we can use the following algorithm:
If the LSB of A is '1', then add B into an accumulator.
Shift A one bit to the right and B one bit to the left.
Stop when all bits of A are zero.
Table 10.8 shows the VHDL model for a Moore (outputs depend only on the state) finite-state machine for the multiplier, together with its
state diagram.
TABLE 10.8
A Moore state machine for the multiplier.
entity SM_1 is
generic (TPD : TIME := 1 ns);
port(Start, Clk, LSB, Stop, Reset: in BIT;
Init, Shift, Add, Done : out BIT);
end;
architecture Moore of SM_1 is
type STATETYPE is (I, C, A, S, E);
signal State: STATETYPE;
begin
Init <= '1' after TPD when State = I
else '0' after TPD;
Add <= '1' after TPD when State = A
else '0' after TPD;
Shift <= '1' after TPD when State = S
else '0' after TPD;
Done <= '1' after TPD when State = E
else '0' after TPD;
process (CLK, Reset) begin
if Reset = '1' then State <= E;
elsif CLK'EVENT and CLK = '1' then
case State is
when I => State <= C;
when C =>
if LSB = '1' then State <= A;
elsif Stop = '0' then State <= S;
else State <= E;
end if;
when A => State <= S;
when S => State <= C;
when E =>
if Start = '1' then State <= I; end if;
end case;
end if;
end process;
end;
State Function
E End of multiply cycle.
I Initialize: clear output
register and load input
registers.
C Check if LSB of register A
is zero.
A Add shift register B to
accumulator.
S Shift input register A right
and input register B left.
10.2.6 A Multiplier
Table 10.9 shows a schematic and the VHDL code that describes the interconnection of all the components for the multiplier. Notice that the
schematic comprises two halves: an 8-bit-wide datapath section (consisting of the registers, adder, multiplexer, and zero detector) and a
control section (the finite-state machine). The arrows in the schematic denote the inputs and outputs of each component. As we shall see in
Section 10.7, VHDL has strict rules about the direction of connections.
TABLE 10.9
A 4-bit by 4-bit multiplier.
entity Mult8 is
port (A, B: in BIT_VECTOR(3 downto 0); Start, CLK, Reset: in BIT;
Result: out BIT_VECTOR(7 downto 0); Done: out BIT); end Mult8;
architecture Structure of Mult8 is use work.Mult_Components.all;
signal SRA, SRB, ADDout, MUXout, REGout: BIT_VECTOR(7 downto 0);
signal Zero, Init, Shift, Add, Low: BIT := '0'; signal High: BIT := '1';
signal F, OFL, REGclr: BIT;
begin
REGclr <= Init or Reset; Result <= REGout;
SR1 : ShiftN port map(CLK=>CLK,CLR=>Reset,LD=>Init,SH=>Shift,DIR=>Low ,D=>A,Q=>SRA);
SR2 : ShiftN port map(CLK=>CLK,CLR=>Reset,LD=>Init,SH=>Shift,DIR=>High,D=>B,Q=>SRB);
Z1 : AllZero port map(X=>SRA,F=>Zero);
A1 : Adder8 port map(A=>SRB,B=>REGout,Cin=>Low,Cout=>OFL,Sum=>ADDout);
M1 : Mux8
port map(A=>ADDout,B=>REGout,Sel=>Add,Y=>MUXout);
R1 : Register8 port map(D=>MUXout,Q=>REGout,Clk=>CLK,Clr=>REGclr);
F1 : SM_1
port map(Start,CLK,SRA(0),Zero,Reset,Init,Shift,Add,Done);
end;
10.2.7 Packages and Testbench
To complete and test the multiplier design we need a few more items. First we need the following "components list" for the items in
Table 10.9:
package Mult_Components is
component Mux8 port (A,B:BIT_VECTOR(7 downto 0);
Sel:BIT;Y:out BIT_VECTOR(7 downto 0));end component;
component AllZero port (X : BIT_VECTOR;
F:out BIT );end component;
component Adder8 port (A,B:BIT_VECTOR(7 downto 0);Cin:BIT;
Cout:out BIT;Sum:out BIT_VECTOR(7 downto 0));end component;
component Register8 port (D:BIT_VECTOR(7 downto 0);
Clk,Clr:BIT; Q:out BIT_VECTOR(7 downto 0));end component;
component ShiftN port (CLK,CLR,LD,SH,DIR:BIT;D:BIT_VECTOR;
Q:out BIT_VECTOR);end component;
component SM_1 port (Start,CLK,LSB,Stop,Reset:BIT;
Init,Shift,Add,Done:out BIT);end component;
end;
Next we need some utility code to help test the multiplier. The following VHDL generates a clock with programmable "high" time ( HT )
and "low" time ( LT ):
package Clock_Utils is
procedure Clock (signal C: out Bit; HT, LT:TIME);
end Clock_Utils;
package body Clock_Utils is
procedure Clock (signal C: out Bit; HT, LT:TIME) is
begin
loop C<='1' after LT, '0' after LT + HT; wait for LT + HT;
end loop;
end;
end Clock_Utils;
Finally, the following code defines two functions that we shall also use for testing--the functions convert an array of bits to a number and vice
versa:
package Utils is
function Convert (N,L: NATURAL) return BIT_VECTOR;
function Convert (B: BIT_VECTOR) return NATURAL;
end Utils;
package body Utils is
function Convert (N,L: NATURAL) return BIT_VECTOR is
variable T:BIT_VECTOR(L-1 downto 0);
variable V:NATURAL:= N;
begin for i in T'RIGHT to T'LEFT loop
T(i) := BIT'VAL(V mod 2); V:= V/2;
end loop; return T;
end;
function Convert (B: BIT_VECTOR) return NATURAL is
variable T:BIT_VECTOR(B'LENGTH-1 downto 0) := B;
variable V:NATURAL:= 0;
begin for i in T'RIGHT to T'LEFT loop
if T(i) = '1' then V:= V + (2**i); end if;
end loop; return V;
end;
end Utils;
The following code tests the multiplier model. This is a testbench (this simple example is not a comprehensive test). First we reset the logic
(line 17) and then apply a series of values to the inputs, A and B . The clock generator (line 14) supplies a clock with a 20 ns period. The
inputs are changed 1 ns after a positive clock edge, and remain stable for 20 ns through the next positive clock edge.
entity Test_Mult8_1 is end; -- runs forever, use break!!
architecture Structure of Test_Mult8_1 is
use Work.Utils.all; use Work.Clock_Utils.all;
component Mult8 port
(A, B : BIT_VECTOR(3 downto 0); Start, CLK, Reset : BIT;
Result : out BIT_VECTOR(7 downto 0); Done : out BIT);
end component;
signal A, B : BIT_VECTOR(3 downto 0);
signal Start, Done : BIT := '0';
signal CLK, Reset : BIT;
signal Result : BIT_VECTOR(7 downto 0);
signal DA, DB, DR : INTEGER range 0 to 255;
begin
C: Clock(CLK, 10 ns, 10 ns);
UUT: Mult8 port map (A, B, Start, CLK, Reset, Result, Done);
DR <= Convert(Result);
Reset <= '1', '0' after 1 ns;
process begin
for i in 1 to 3 loop for j in 4 to 7 loop
DA <= i; DB <= j;
A<=Convert(i,A'Length);B<=Convert(j,B'Length);
wait until CLK'EVENT and CLK='1'; wait for 1 ns;
Start <= '1', '0' after 20 ns; wait until Done = '1';
wait until CLK'EVENT and CLK='1';
end loop; end loop;
for i in 0 to 1 loop for j in 0 to 15 loop
DA <= i; DB <= j;
A<=Convert(i,A'Length);B<=Convert(j,B'Length);
wait until CLK'EVENT and CLK='1'; wait for 1 ns;
Start <= '1', '0' after 20 ns; wait until Done = '1';
wait until CLK'EVENT and CLK='1';
end loop; end loop;
wait;
end process;
end;
Here is the signal trace output from the Compass Scout simulator:
Time(fs) + Cycle
da
db
---------------------- ------------ -----------0+ 0:
0
0
0+ 1: *
1 *
4
...
92000000+ 3:
1
4
...
150000000+ 1: *
1 *
5
...
193000000+ 3:
1
5
...
252000000+ 3:
1
5
...
310000000+ 1: *
1 *
6
...
353000000+ 3:
1
6
...
412000000+ 3:
1
6
dr
-----------0
*
0
*
4
4
*
0
*
5
5
*
0
*
6
Positive clock edges occur at 10, 30, 50, 70, 90, ... ns. You can see that the output (dr) changes from '0' to '4' at 92 ns, after five clock
edges (with a 2 ns delay due to the output register, R1).
10.3 Syntax and Semantics of VHDL
We might define the syntax of a very small subset of the English language in Backus-Naur form
(BNF) using constructs as follows:
sentence
subject
object
article
noun
verb
::=
|
[]
{}
::=
::=
::=
::=
::=
::=
means
means
means
means
subject verb object.
The|A noun
[article] noun {, and article noun}
the|a
man|shark|house|food
eats|paints
"can be replaced by"
"or"
"contents optional"
"contents can be left out, used once, or repeated"
The following two English sentences are correct according to these syntax rules:
A shark eats food.
The house paints the shark, and the house, and a man.
We need semantic rules to tell us that the second sentence does not make much sense. Most of the
VHDL LRM is dedicated to the definition of the language semantics. Appendix A of the LRM
(which is not officially part of the standard) explains the complete VHDL syntax using BNF.
The rules that determine the characters you can use (the "alphabet" of VHDL), where you can put
spaces, and so on are lexical rules [VHDL LRM13]. Any VHDL description may be written using
a subset of the VHDL character set:
basic_character ::= upper_case_letter|digit|special_character
|space_character|format_effector
The two space characters are: space ( SP ) and the nonbreaking space ( NBSP ). The five format
effectors are: horizontal tabulation ( HT ), vertical tabulation ( VT ), carriage return ( CR ), line
feed ( LF ), and form feed ( FF ). The characters that are legal in VHDL constructs are defined
as the following subsets of the complete character set:
graphic_character ::=
upper_case_letter|digit|special_character|space_character
|lower_case_letter|other_special_character
special_character ::= " # & ' () * + , - . / : ; < = > [ ] _ |
The 11 other special characters are: ! $ % @ ? \ ^ ` { } ~ , and (in VHDL-93 only) 34
other characters from the ISO Latin-1 set [ISO, 1987]. If you edit code using a word processor,
you either need to turn smart quotes off or override this feature (use Tools... Preferences... General
in MS Word; and use CTRL-' and CTRL-" in Frame).
When you learn a language it is difficult to understand how to use a noun without using it in a
sentence. Strictly this means that we ought to define a sentence before we define a noun and so on.
In this chapter I shall often break the "Define it before you use it" rule and use code examples and
BNF definitions that contain VHDL constructs that we have not yet defined. This is often
frustrating. You can use the book index and the table of important VHDL constructs at the end of
this chapter (Table 10.28) to help find definitions if you need them.
We shall occasionally refer to the VHDL BNF syntax definitions in this chapter using
references--BNF [10.1], for example. Only the most important BNF constructs for VHDL are
included here in this chapter, but a complete description of the VHDL language syntax is
contained in Appendix A.
10.4 Identifiers and Literals
Names (the "nouns" of VHDL) are known as identifiers [VHDL LRM13.3]. The correct "spelling" of an identifier is defined
in BNF as follows:
identifier ::=
letter {[underline] letter_or_digit}
|\graphic_character{graphic_character}\
In this book an underline in VHDL BNF marks items that are new or that have changed in VHDL-93 from VHDL-87. The
following are examples of identifiers:
s -- A simple name.
S -- A simple name, the same as s. VHDL is not case sensitive.
a_name -- Imbedded underscores are OK.
-- Successive underscores are illegal in names: Ill__egal
-- Names can't start with underscore: _Illegal
-- Names can't end with underscore: Illegal_
Too_Good -- Names must start with a letter.
-- Names can't start with a number: 2_Bad
\74LS00\ -- Extended identifier to break rules (VHDL-93 only).
VHDL \vhdl\ \VHDL\ -- Three different names (VHDL-93 only).
s_array(0) -- A static indexed name (known at analysis time).
s_array(i) -- A non-static indexed name, if i is a variable.
You may not use a reserved word as a declared identifier, and it is wise not to use units, special characters, and function
names: ns , ms , FF , read , write, and so on. You may attach qualifiers to names as follows [VHDL LRM6]:
CMOS.all -- A selected or expanded name, all units in library CMOS.
Data'LEFT(1) -- An attribute name, LEFT is the attribute designator.
Data(24 downto 1) -- A slice name, part of an array: Data(31 downto 0)
Data(1) -- An indexed name, one element of an array.
Comments follow two hyphens '--' and instruct the analyzer to ignore the rest of the line. There are no multiline comments
in VHDL. Tabs improve readability, but it is best not to rely on a tab as a space in case the tabs are lost or deleted in
conversion. You should thus write code that is still legal if all tabs are deleted.
There are various forms of literals (fixed-value items) in VHDL [VHDL LRM13.4-13.7]. The following code shows some
examples:
entity Literals_1 is end;
architecture Behave of Literals_1 is
begin process
variable I1 : integer; variable Rl : real;
variable C1 : CHARACTER; variable S16 : STRING(1 to 16);
variable BV4: BIT_VECTOR(0 to 3);
variable BV12 : BIT_VECTOR(0 to 11);
variable BV16 : BIT_VECTOR(0 to 15);
begin
-- Abstract literals are decimal or based literals.
-- Decimal literals are integer or real literals.
-- Integer literal examples (each of these is the same):
I1 := 120000; Int := 12e4; Int := 120_000;
-- Based literal examples (each of these is the same):
I1 := 2#1111_1111#; I1 := 16#FFFF#;
-- Base must be an integer from 2 to 16:
I1 := 16:FFFF:; -- you may use a : if you don't have #
-- Real literal examples (each of these is the same):
Rl := 120000.0; Rl := 1.2e5; Rl := 12.0E4;
-- Character literal must be one of the 191 graphic characters.
-- 65 of the 256 ISO Latin-1 set are non-printing control characters
C1 := 'A'; C1 := 'a'; -- different from each other
-- String literal examples:
S16 := " string" & " literal";
-- concatenate long strings
S16 := """Hello,"" I said!";
-- doubled quotes
S16 := % string literal%;
-- can use % instead of "
S16 := %Sale: 50%% off!!!%;
-- doubled %
-- Bit-string literal examples:
BV4 := B"1100";
-- binary bit-string literal
BV12 := O"7777";
-- octal
BV16 := X"FFFF";
-- hex
wait; end process; -- the wait prevents an endless loop
end;
bit-string literal
bit-string literal
10.5 Entities and Architectures
The highest-level VHDL construct is the design file [VHDL LRM11.1]. A design file contains design units that contain one or
more library units. Library units in turn contain: entity, configuration, and package declarations (primary units); and
architecture and package bodies (secondary units).
design_file ::=
{library_clause|use_clause} library_unit
{{library_clause|use_clause} library_unit}
library_unit ::= primary_unit|secondary_unit
primary_unit ::=
entity_declaration|configuration_declaration|package_declaration
secondary_unit ::= architecture_body|package_body
Using the written language analogy: a VHDL library unit is a "book," a VHDL design file is a "bookshelf," and a VHDL
library is a collection of bookshelves. A VHDL primary unit is a little like the chapter title and contents that appear on the first
page of each chapter in this book and a VHDL secondary unit is like the chapter contents (though this is stretching our analogy
a little far).
I shall describe the very important concepts of entities and architectures in this section and then cover libraries, packages, and
package bodies. You define an entity, a black box, using an entity declaration [VHDL LRM1.1]. This is the BNF definition:
entity_declaration ::=
entity identifier is
[generic (formal_generic_interface_list);]
[port (formal_port_interface_list);]
{entity_declarative_item}
[begin
{[label:] [postponed] assertion ;
|[label:] [postponed] passive_procedure_call ;
|passive_process_statement}]
end [entity] [entity_identifier] ;
The following is an example of an entity declaration for a black box with two inputs and an output:
entity Half_Adder is
port (X, Y : in BIT := '0'; Sum, Cout : out BIT); -- formals
end;
Matching the parts of this code with the constructs in BNF [10.7] you can see that the identifier is Half_Adder and
that (X, Y: in BIT := '0'; Sum, Cout: out BIT) corresponds to (port_interface_list) in the BNF.
The ports X, Y, Sum, and Cout are formal ports or formals. This particular entity Half_Adder does not use any of the other
optional constructs that are legal in an entity declaration.
The architecture body [VHDL LRM1.2] describes what an entity does, or the contents of the black box (it is architecture body
and not architecture declaration).
architecture_body ::=
architecture identifier of entity_name is
{block_declarative_item}
begin
{concurrent_statement}
end [architecture] [architecture_identifier] ;
For example, the following architecture body (I shall just call it an architecture from now on) describes the contents of the
entity Half_Adder :
architecture Behave of Half_Adder is
begin Sum <= X xor Y; Cout <= X and Y;
end Behave;
We use the same signal names (the formals: Sum , X , Y , and Cout ) in the architecture as we use in the entity (we say the
signals of the "parent" entity are visible inside the architecture "child"). An architecture can refer to other entity-architecture
pairs--so we can nest black boxes. We shall often refer to an entity-architecture pair as entity(architecture). For
example, the architecture Behave of the entity Half_Adder is Half_Adder(Behave).
Why would we want to describe the outside of a black box (an entity) separately from the description of its contents (its
architecture)? Separating the two makes it easier to move between different architectures for an entity (there must be at least
one). For example, one architecture may model an entity at a behavioral level, while another architecture may be a structural
model.
A structural model that uses an entity in an architecture must declare that entity and its interface using a component declaration
as follows [VHDL LRM4.5]:
component_declaration ::=
component identifier [is]
[generic (local_generic_interface_list);]
[port (local_port_interface_list);]
end component [component_identifier];
For example, the following architecture, Netlist , is a structural version of the behavioral architecture, Behave :
architecture Netlist of Half_Adder is
component MyXor port (A_Xor,B_Xor : in BIT; Z_Xor : out BIT);
end component; -- component with locals
component MyAnd port (A_And,B_And : in BIT; Z_And : out BIT);
end component; -- component with locals
begin
Xor1: MyXor port map (X, Y, Sum);
-- instance with actuals
And1 : MyAnd port map (X, Y, Cout);
-- instance with actuals
end;
Notice that:
● We declare the components: MyAnd, MyXor and their local ports (or locals): A_Xor, B_Xor, Z_Xor, A_And,
B_And, Z_And.
● We instantiate the components with instance names: And1 and Xor1.
● We connect instances using actual ports (or actuals): X, Y , Sum , Cout.
Next we define the entities and architectures that we shall use for the components MyAnd and MyXor . You can think of an
entity-architecture pair (and its formal ports) as a data-book specification for a logic cell; the component (and its local ports)
corresponds to a software model for the logic cell; and an instance (and its actual ports) is the logic cell.
We do not need to write VHDL code for MyAnd and MyXor ; the code is provided as a technology library (also called an
ASIC vendor library because it is often sold or distributed by the ASIC company that will manufacture the chip--the ASIC
vendor--and not the software company):
-- These definitions are part of a technology library:
entity AndGate is
port (And_in_1, And_in_2 : in BIT; And_out : out BIT); -- formals
end;
architecture Simple of AndGate is
begin And_out <= And_in_1 and And_in_2;
end;
entity XorGate is
port (Xor_in_1, Xor_in_2 : in BIT; Xor_out : out BIT); -- formals
end;
architecture Simple of XorGate is
begin Xor_out <= Xor_in_1 xor Xor_in_2;
end;
If we keep the description of a circuit's interface (the entity ) separate from its contents (the architecture ), we need a
way to link or bind them together. A configuration declaration [VHDL LRM1.3] binds entities and architectures.
configuration_declaration ::=
configuration identifier of entity_name is
{use_clause|attribute_specification|group_declaration}
block_configuration
end [configuration] [configuration_identifier] ;
An entity-architecture pair is a design entity. The following configuration declaration defines which design entities we wish to
use and associates the formal ports (from the entity declaration) with the local ports (from the component declaration):
configuration Simplest of Half_Adder is
use work.all;
for Netlist
for And1 : MyAnd use entity AndGate(Simple)
port map -- association: formals => locals
(And_in_1 => A_And, And_in_2 => B_And, And_out =>
Z_And);
end for;
for Xor1 : MyXor use entity XorGate(Simple)
port map
(Xor_in_1 => A_Xor, Xor_in_2 => B_Xor, Xor_out => Z_Xor);
end for;
end for;
end;
Figure 10.1 diagrams the use of entities, architectures, components, and configurations. This figure seems very complicated,
but there are two reasons that VHDL works this way:
● Separating the entity, architecture, component, and configuration makes it easier to reuse code and change libraries. All
we have to do is change names in the port maps and configuration declaration.
● We only have to alter and reanalyze the configuration declaration to change which architectures we use in a
model--giving us a fast debug cycle.
FIGURE 10.1 Entities, architectures, components, ports, port maps, and configurations.
You can think of design units, the analyzed entity-architecture pairs, as compiled object-code modules. The configuration then
determines which object-code modules are linked together to form executable binary code.
You may also think of an entity as a block diagram, an architecture for an entity a more detailed circuit schematic for the block
diagram, and a configuration as a parts list of the circuit components with their part numbers and manufacturers (also known as
a BOM for bill of materials, rather like a shopping list). Most manufacturers (including the U.S. DoD) use schematics and
BOMs as control documents for electronic systems. This is part of the rationale behind the structure of VHDL.
10.6 Packages and Libraries
After the VHDL tool has analyzed entities, architectures, and configurations, it stores the resulting design units in a
library. Much of the power of VHDL comes from the use of predefined libraries and packages. A VHDL design library
[VHDL LRM11.2] is either the current working library (things we are currently analyzing) or a predefined resource
library (something we did yesterday, or we bought, or that came with the tool). The working library is named work and
is the place where the code currently being analyzed is stored. Architectures must be in the same library (but they do not
have to be in the same physical file on disk) as their parent entities.
You can use a VHDL package [VHDL LRM2.5-2.6] to define subprograms (procedures and functions), declare special
types, modify the behavior of operators, or to hide complex code. Here is the BNF for a package declaration:
package_declaration ::=
package identifier is
{subprogram_declaration
| type_declaration
| subtype_declaration
| constant_declaration | signal_declaration
| file_declaration
| alias_declaration
| component_declaration
| attribute_declaration | attribute_specification
| disconnection_specification | use_clause
| shared_variable_declaration | group_declaration
| group_template_declaration}
end [package] [package_identifier] ;
You need a package body if you declare any subprograms in the package declaration (a package declaration and its body
do not have to be in the same file):
package_body ::=
package body package_identifier is
{subprogram_declaration
| subprogram_body
| type_declaration
| subtype_declaration
| constant_declaration | file_declaration
| alias_declaration
| use_clause
| shared_variable_declaration | group_declaration
| group_template_declaration}
end [package body] [package_identifier] ;
To make a package visible [VHDL LRM10.3] (or accessible, so you can see and use the package and its contents), you
must include a library clause before a design unit and a use clause either before a design unit or inside a unit, like this:
library MyLib; -- library clause
use MyLib.MyPackage.all; -- use clause
-- design unit (entity + architecture, etc.) follows:
The STD and WORK libraries and the STANDARD package are always visible. Things that are visible to an entity are
visible to its architecture bodies.
10.6.1 Standard Package
The VHDL STANDARD package [VHDL LRM14.2] is defined in the LRM and implicitly declares the following
implementation dependent types: TIME , INTEGER , REAL . We shall use uppercase for types defined in an IEEE
standard package. Here is part of the STANDARD package showing the explicit type and subtype declarations:
package Part_STANDARD is
type BOOLEAN
is (FALSE, TRUE); type BIT
is ('0', '1');
type SEVERITY_LEVEL
is (NOTE, WARNING, ERROR, FAILURE);
subtype NATURAL
is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE
is INTEGER range 1 to INTEGER'HIGH;
type BIT_VECTOR
is array (NATURAL range <>) of BIT;
type STRING
is array (POSITIVE range <>) of CHARACTER;
-- the following declarations are VHDL-93 only:
attribute FOREIGN: STRING; -- for links to other languages
subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
type FILE_OPEN_KIND is (READ_MODE,WRITE_MODE,APPEND_MODE);
type FILE_OPEN_STATUS is
(OPEN_OK,STATUS_ERROR,NAME_ERROR,MODE_ERROR);
end Part_STANDARD;
Notice that a STRING array must have a positive index. The type TIME is declared in the STANDARD package as
follows:
type TIME is range implementation_defined -- and varies with software
units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us;
sec = 1000 ms; min = 60 sec; hr = 60 min; end units;
The STANDARD package also declares the function now that returns the current simulation time (with type TIME in
VHDL-87 and subtype DELAY_LENGTH in VHDL-93).
In VHDL-93 the CHARACTER type declaration extends the VHDL-87 declaration (the 128 ASCII characters):
type Part_CHARACTER is ( -- 128 ASCII characters in VHDL-87
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, -- 33 control characters
BS, HT, LF, VT, FF, CR, SO, SI, -- including:
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, -- format effectors:
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, -- horizontal tab = HT
' ', '!', '"', '#', '$', '%', '&', ''', -- line feed = LF
'(', ')', '*', '+', ',', '-', '.', '/', -- vertical tab = VT
'0', '1', '2', '3', '4', '5', '6', '7', -- form feed = FF
'8', '9', ':', ';', '<', '=', '>', '?', -- carriage return = CR
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', -- and others:
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', -- FSP, GSP, RSP, USP use P
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', -- suffix to avoid conflict
'X', 'Y', 'Z', '[', '\', ']', '^', '_', -- with TIME units
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL -- delete = DEL
-- VHDL-93 includes 96 more Latin-1 characters, like ¥ (Yen) and
-- 32 more control characters, better not to use any of them.
);
The VHDL-87 character set is the 7-bit coded ISO 646-1983 standard known as the ASCII character set. Each of the
printable ASCII graphic character codes (there are 33 nonprintable control codes, like DEL for delete) is represented by a
graphic symbol (the shapes of letters on the keyboard, on the display, and that actually print). VHDL-93 uses the 8-bit
coded character set ISO 8859-1:1987(E), known as ISO Latin-1. The first 128 characters of the 256 characters in ISO
Latin-1 correspond to the 128-character ASCII code. The graphic symbols for the printable ASCII characters are well
defined, but not part of the standard (for example, the shape of the graphic symbol that represents 'lowercase a' is
recognizable on every keyboard, display, and font). However, the graphic symbols that represent the printable characters
from other 128-character codes of the ISO 8-bit character set are different in various fonts, languages, and computer
systems. For example, a pound sterling sign in a U.K. character set looks like this-'£', but in some fonts the same
character code prints as '#' (known as number sign, hash, or pound). If you use such characters and want to share your
models with people in different countries, this can cause problems (you can see all 256 characters in a character set by
using Insert... Symbol in MS Word).
10.6.2 Std_logic_1164 Package
VHDL does not have a built-in logic-value system. The STANDARD package predefines the type BIT with two logic
values, '0' and '1' , but we normally need at least two more values: 'X' (unknown) and 'Z' (high-impedance).
Unknown is a metalogical value because it does not exist in real hardware but is needed for simulation purposes. We
could define our own logic-value system with four logic values:
type MVL4 is ('X', '0', '1', 'Z'); -- a four-value logic system
The proliferation of VHDL logic-value systems prompted the creation of the Std_logic_1164 package (defined in IEEE
Std 1164-1993) that includes functions to perform logical, shift, resolution, and conversion functions for types defined in
the Std_logic_1164 system. To use this package in a design unit, you must include the following library clause
(before each design unit) and a use clause (either before or inside the unit):
library IEEE; use IEEE.std_logic_1164.all;
This Std_Logic_1164 package contains definitions for a nine-value logic system. The following code and comments
show the definitions and use of the most important parts of the package 1:
package Part_STD_LOGIC_1164 is
type STD_ULOGIC is
(
'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't Care);
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
subtype STD_LOGIC is resolved STD_ULOGIC;
type STD_LOGIC_VECTOR is array (NATURAL range <>) of STD_LOGIC;
subtype X01
is resolved STD_ULOGIC range 'X' to '1';
subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z';
subtype UX01 is resolved STD_ULOGIC range 'U' to '1';
subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z';
-- Vectorized overloaded logical operators:
function "and" (L : STD_ULOGIC; R : STD_ULOGIC) return UX01;
-- Logical operators not, and, nand, or, nor, xor, xnor (VHDL-93),
-- overloaded for STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC_VECTOR.
-- Strength strippers and type conversion functions:
-- function To_T (X : F) return T;
-- defined for types, T and F, where
-- F=BIT BIT_VECTOR STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC_VECTOR
-- T=types F plus types X01 X01Z UX01 (but not type UX01Z)
-- Exclude _'s in T in name: TO_STDULOGIC not TO_STD_ULOGIC
-- To_XO1 : L->0, H->1 others->X
-- To_XO1Z: Z->Z, others as To_X01
-- To_UX01: U->U, others as To_X01
-- Edge detection functions:
function rising_edge (signal s: STD_ULOGIC) return BOOLEAN;
function falling_edge (signal s: STD_ULOGIC) return BOOLEAN;
-- Unknown detection (returns true if s = U, X, Z, W):
-- function Is_X (s : T) return BOOLEAN;
-- defined for T = STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC_VECTOR.
end Part_STD_LOGIC_1164;
Notice:
● The type STD_ULOGIC has nine logic values. For this reason IEEE Std 1164 is sometimes referred to as
MVL9--multivalued logic nine. There are simpler, but nonstandard, MVL4 and MVL7 packages, as well as
packages with more than nine logic values, available. Values 'U' , 'X' , and 'W' are all metalogical values.
● There are weak and forcing logic-value strengths. If more than one logic gate drives a node (there is more than one
driver) as in wired-OR logic or a three-state bus, for example, the simulator checks the driver strengths to resolve
the actual logic value of the node using the resolution function, resolved , defined in the package.
● The subtype STD_LOGIC is the resolved version of the unresolved type STD_ULOGIC. Since subtypes are
compatible with types (you can assign one to the other) you can use either STD_LOGIC or STD_ULOGIC for a
signal with a single driver, but it is generally safer to use STD_LOGIC.
● The type STD_LOGIC_VECTOR is the resolved version of unresolved type STD_ULOGIC_VECTOR. Since these
are two different types and are not compatible, you should use STD_LOGIC_VECTOR. That way you will not run
into a problem when you try to connect a STD_LOGIC_VECTOR to a STD_ULOGIC_VECTOR.
● The don't care logic value '-' (hyphen), is principally for use by synthesis tools. The value '-' is almost always
treated the same as 'X'.
● The 1164 standard defines (or overloads) the logical operators for the STD_LOGIC types but not the arithmetic
operators (see Section 10.12).
10.6.3 Textio Package
You can use the textio package, which is part of the library STD , for text input and output [VHDL LRM14.3]. The
following code is a part of the TEXTIO package header and, together with the comments, shows the declarations of
types, subtypes, and the use of the procedures in the package:
package Part_TEXTIO is -- VHDL-93 version.
type LINE is access STRING; -- LINE is a pointer to a STRING value.
type TEXT is file of STRING; -- File of ASCII records.
type SIDE is (RIGHT, LEFT); -- for justifying output data.
subtype WIDTH is NATURAL; -- for specifying widths of output fields.
file INPUT : TEXT open READ_MODE is "STD_INPUT"; -- Default input file.
file OUTPUT : TEXT open WRITE_MODE is "STD_OUTPUT"; -- Default output.
-- The following procedures are defined for types, T, where
-- T = BIT BIT_VECTOR BOOLEAN CHARACTER INTEGER REAL TIME STRING
-procedure READLINE(file F : TEXT; L : out LINE);
-procedure READ(L : inout LINE; VALUE : out T);
-procedure READ(L : inout LINE; VALUE : out T; GOOD: out BOOLEAN);
-procedure WRITELINE(F : out TEXT; L : inout LINE);
-procedure WRITE(
-L : inout LINE;
-VALUE : in T;
-JUSTIFIED : in SIDE:= RIGHT;
-FIELD:in WIDTH := 0;
-DIGITS:in NATURAL := 0; -- for T = REAL only
-UNIT:in TIME:= ns); -- for T = TIME only
-- function ENDFILE(F : in TEXT) return BOOLEAN;
end Part_TEXTIO;
Here is an example that illustrates how to write to the screen (STD_OUTPUT ):
library std; use std.textio.all; entity Text is end;
architecture Behave of Text is signal count : INTEGER := 0;
begin count <= 1 after 10 ns, 2 after 20 ns, 3 after 30 ns;
process (count) variable L: LINE; begin
if (count > 0) then
write(L, now); -- Write time.
write(L, STRING'(" count=")); -- STRING' is a type qualification.
write(L, count); writeline(output, L);
end if; end process; end;
10 ns count=1
20 ns count=2
30 ns count=3
10.6.4 Other Packages
VHDL does not predefine arithmetic operators on types that hold bits. Many VHDL simulators provide one or more
arithmetic packages that allow you to perform arithmetic operations on std_logic_1164 types. Some companies also
provide one or more math packages that contain functions for floating-point algebra, trigonometry, complex algebra,
queueing, and statistics (see also [IEEE 1076.2, 1996]).
Synthesis tool companies often provide a special version of an arithmetic package, a synthesis package, that allows you
to synthesize VHDL that includes arithmetic operators. This type of package may contain special instructions (normally
comments that are recognized by the synthesis software) that map common functions (adders, subtracters, multipliers,
shift registers, counters, and so on) to ASIC library cells. I shall introduce the IEEE synthesis package in Section 10.12.
Synthesis companies may also provide component packages for such cells as power and ground pads, I/O buffers, clock
drivers, three-state pads, and bus keepers. These components may be technology-independent (generic) and are mapped
to primitives from technology-dependent libraries after synthesis.
10.6.5 Creating Packages
It is often useful to define constants in one central place rather than using literals wherever you need a specific value in
your code. One way to do this is by using VHDL packaged constants [VHDL LRM4.3.1.1] that you define in a package.
Packages that you define are initially part of the working library, work . Here are two example packages [VHDL
LRM2.5-2.7]:
package Adder_Pkg is -- a package declaration
constant BUSWIDTH : INTEGER := 16;
end Adder_Pkg;
use work.Adder_Pkg.all; -- a use clause
entity Adder is end Adder;
architecture Flexible of Adder is -- work.Adder_Pkg is visible here
begin process begin
MyLoop : for j in 0 to BUSWIDTH loop -- adder code goes here
end loop; wait; -- the wait prevents an endless cycle
end process;
end Flexible;
package GLOBALS is
constant HI : BIT := '1'; constant LO: BIT := '0';
end GLOBALS;
Here is a package that declares a function and thus requires a package body:
package Add_Pkg_Fn is
function add(a, b, c : BIT_VECTOR(3 downto 0)) return BIT_VECTOR;
end Add_Pkg_Fn;
package body Add_Pkg_Fn is
function add(a, b, c : BIT_VECTOR(3 downto 0)) return BIT_VECTOR is
begin return a xor b xor c; end;
end Add_Pkg_Fn;
The following example is similar to the VITAL (VHDL Initiative Toward ASIC Libraries) package that provides two
alternative methods (procedures or functions) to model primitive gates (I shall describe functions and procedures in more
detail in Section 10.9.2):
package And_Pkg is
procedure V_And(a, b : BIT; signal c : out BIT);
function V_And(a, b : BIT) return BIT;
end;
package body And_Pkg is
procedure V_And(a, b : BIT; signal c : out BIT) is
begin c <= a and b; end;
function V_And(a, b : BIT) return BIT is
begin return a and b; end;
end And_Pkg;
The software determines where it stores the design units that we analyze. Suppose the package Add_Pkg_Fn is in
library MyLib . Then we need a library clause (before each design unit) and use clause with a selected name to use the
package:
library MyLib; -- use MyLib.Add_Pkg.all; -- use all the package
use MyLib.Add_Pkg_Fn.add; -- just function 'add' from the package
entity Lib_1 is port (s : out BIT_VECTOR(3 downto 0) := "0000"); end;
architecture Behave of Lib_1 is begin process
begin s <= add ("0001", "0010", "1000"); wait; end process; end;
The VHDL software dictates how you create the library MyLib from the library work and the actual name and directory
location for the physical file or directory on the disk that holds the library. The mechanism to create the links between
the file and directory names in the computer world and the library names in the VHDL world depends on the software.
There are three common methods:
● Use a UNIX environment variable (SETENV MyLib ~/MyDirectory/
MyLibFile , for example).
● Create a separate file that establishes the links between the filename known to the operating system and the library
name known to the VHDL software.
● Include the links in an initialization file (often with an '.ini' suffix).
1. The code in this section is adapted with permission from IEEE Std 1164-1993, © Copyright IEEE. All rights reserved.
10.7 Interface Declarations
An interface declaration declares interface objects that may be interface constants, signals, variables, or files [VHDL 87LRM4.3.3,
93LRM4.3.2]. Interface constants are generics of a design entity, a component, or a block, or parameters of subprograms. Interface
signals are ports of a design entity, component, or block, and parameters of subprograms. Interface variables and interface files are
parameters of subprograms.
Each interface object has a mode that indicates the direction of information flow. The most common modes are in (the default), out ,
inout , and buffer (a fifth mode, linkage , is used to communicate with other languages and is infrequently used in ASIC
design). The restrictions on the use of objects with these modes are listed in Table 10.10. An interface object is read when you use it
on the RHS of an assignment statement, for example, or when the object is associated with another interface object of modes in ,
inout (or linkage ). An interface object is updated when you use it on the LHS side of an assignment statement or when the object
is associated with another interface object of mode out , buffer , inout (or linkage ). The restrictions on reading and updating
objects generate the diagram at the bottom of Table 10.10 that shows the 10 allowed types of interconnections (these rules for modes
buffer and inout are the same). The interface objects ( Inside and Outside ) in the example in this table are ports (and thus
interface signals), but remember that interface objects may also be interface constants, variables, and files.
TABLE 10.10
Modes of interface objects and their properties.
entity E1 is port (Inside : in BIT); end; architecture Behave of E1 is begin end;
entity E2 is port (Outside : inout BIT := '1'); end; architecture Behave of E2 is
component E1 port (Inside: in BIT); end component; signal UpdateMe : BIT; begin
I1 : E1 port map (Inside => Outside); -- formal/local (mode in) => actual (mode
inout)
UpdateMe <= Outside; -- OK to read Outside (mode inout)
Outside <= '0' after 10 ns; -- and OK to update Outside (mode inout)
end;
Possible modes of interface object, Outside
in (default)
out inout buffer
Can you read Outside (RHS of assignment)?
Yes
No
Yes
Yes
Can you update Outside (LHS of assignment)?
No
Yes
Yes
Yes
Modes of Inside that Outside may connect to (see below) 1
in
out any
any
There are other special-case rules for reading and updating interface signals, constants, variables, and files that I shall cover in the
following sections. The situation is like the spelling rule, "i before e except after c." Table 10.10 corresponds to the rule "i before e."
10.7.1 Port Declaration
Interface objects that are signals are called ports [VHDL 93LRM1.1.1.2]. You may think of ports as "connectors" and you must
declare them as follows:
port (port_interface_list)
interface_list ::=
port_interface_declaration {; port_interface_declaration}
A port interface declaration is a list of ports that are the inputs and outputs of an entity, a block, or a component declaration:
interface_declaration ::=
[signal]
identifier {, identifier}:[in|out|inout|buffer|linkage]
subtype_indication [bus] [:= static_expression]
Each port forms an implicit signal declaration and has a port mode. I shall discuss bus , which is a signal kind, in Section 10.13.1.
Here is an example of an entity declaration that has five ports:
entity Association_1 is
port (signal X, Y : in BIT := '0'; Z1, Z2, Z3 : out BIT);
end;
In the preceding declaration the keyword signal is redundant (because all ports are signals) and may be omitted. You may also omit
the port mode in because it is the default mode. In this example, the input ports X and Y are driven by a default value (in general a
default expression) of '0' if (and only if ) the ports are left unconnected or open. If you do leave an input port open, the port must
have a default expression.
You use a port map and either positional association or named association to connect the formals of an entity with the locals of a
component. Port maps also associate (connect) the locals of a component with the actuals of an instance. For an example of formal,
local, and actual ports, and explanation of their function, see Section 10.5, where we declared an entity AndGate. The following
example shows how to bind a component to the entity AndGate (in this case we use the default binding) and associate the ports.
Notice that if we mix positional and named association then all positional associations must come first.
use work.all; -- makes analyzed design entity AndGate(Simple) visible.
architecture Netlist of Association_1 is
-- The formal port clause for entity AndGate looks like this:
-- port (And_in_1, And_in_2: in BIT; And_out : out BIT); -- Formals.
component AndGate port
(And_in_1, And_in_2 : in BIT; And_out : out BIT); -- Locals.
end component;
begin
-- The component and entity have the same names: AndGate.
-- The port names are also the same: And_in_1, And_in_2, And_out,
-- so we can use default binding without a configuration.
-- The last (and only) architecture for AndGate will be used: Simple.
A1:AndGate port map (X, Y, Z1); -- positional association
A2:AndGate port map (And_in_2=>Y, And_out=>Z2, And_in_1=>X);
-- named
A3:AndGate port map (X, And_out => Z3, And_in_2 => Y);
-- both
end;
The interface object rules of Table 10.10 apply to ports. The rule that forbids updating an interface object of mode in prevents
modifying an input port (by placing the input signal on the left-hand side of an assignment statement, for example). Less obviously,
you cannot read a port of mode out (that is you cannot place an output signal on the right-hand side of an assignment statement). This
stops you from accidentally reading an output signal that may be connected to a net with multiple drivers. In this case the value you
would read (the unresolved output signal) might not be the same as the resolved signal value. For example, in the following code, since
Clock is a port of mode out , you cannot read Clock directly. Instead you can transfer Clock to an intermediate variable and read
the intermediate variable instead:
entity ClockGen_1 is port (Clock : out BIT); end;
architecture Behave of ClockGen_1 is
begin process variable Temp : BIT := '1';
begin
-Clock <= not Clock; -- Illegal, you cannot read Clock (mode out),
Temp := not Temp; -- use a temporary variable instead.
Clock <= Temp after 10 ns; wait for 10 ns;
if (now > 100 ns) then wait; end if; end process;
end;
TABLE 10.11
Properties of ports.
Example entity declaration:
entity E is port (F_1:BIT; F_2:out BIT; F_3:inout BIT; F_4:buffer BIT); end;
formals
--
Example component declaration:
component C port (L_1:BIT; L_2:out BIT; L_3:inout BIT; L_4:buffer BIT); -- locals
end component;
Example component instantiation:
I1 : C port map
(L_1 => A_1, L_2 => A_2, L_3 => A_3, L_4 => A_4); -- locals => actuals
Example configuration:
for I1 : C use entity E(Behave) port map
(F_1 => L_1, F_2 => L_2, F_3 => L_3, F_4 => L_4); -- formals => locals
Interface object, port F
Mode of F
F_1
in (default)
F_2
out
F_3
F_4
inout
buffer
Yes, but not the attributes:
'STABLE 'QUIET
Yes, but not the attributes:
Yes, but not the attributes:
'DELAYED
Can you read attributes of F?
[VHDL LRM4.3.2]
'STABLE
'STABLE
'TRANSACTION
'QUIET
'QUIET
Yes
'EVENT 'ACTIVE
'DELAYED
'DELAYED
'LAST_EVENT
'TRANSACTION
'TRANSACTION
'LAST_ACTIVE
'LAST_VALUE
Table 10.10 lists the restrictions on reading and updating interface objects including interface signals that form ports. Table 10.11 lists
additional special rules for reading and updating the attributes of interface signals.
There is one more set of rules that apply to port connections [VHDL LRM 1.1.1.2]. If design entity E2 contains an instance, I1 , of
design entity E1 , then the formals (of design entity E1 ) are associated with actuals (of instance I1 ). The actuals (of instance I1 ) are
themselves formal ports (of design entity E2 ). The restrictions illustrated in Table 10.12 apply to the modes of the port connections
from E1 to E2 (looking from the inside to the outside).
Notice that the allowed connections diagrammed in Table 10.12 (looking from inside to the outside) are a superset of those of
Table 10.10 (looking from the outside to the inside). Only the seven types of connections shown in Table 10.12 are allowed between
the ports of nested design entities. The additional rule that ports of mode buffer may only have one source, together with the
restrictions on port mode interconnections, limits the use of ports of mode buffer .
TABLE 10.12
Connection rules for port modes.
entity E1 is port (Inside : in BIT); end; architecture Behave of E1 is begin end;
entity E2 is port (Outside : inout BIT := '1'); end; architecture Behave of E2 is
component E1 port (Inside : in BIT); end component; begin
I1 : E1 port map (Inside => Outside);
-- formal/local (mode in) => actual (mode inout)
end;
Possible modes of interface object, Inside
in (default)
Modes of Outside that Inside may connect to (see below)
in inout buffer out inout inout 2 buffer 3
out
inout
buffer
10.7.2 Generics
Ports are signals that carry changing information between entities. A generic is similar to a port, except generics carry constant, static
information [VHDL LRM1.1.1.1]. A generic is an interface constant that, unlike normal VHDL constants, may be given a value in a
component instantiation statement or in a configuration specification. You declare generics in an entity declaration and you use
generics in a similar fashion to ports. The following example uses a generic parameter to alter the size of a gate:
entity AndGateNWide is
generic (N : NATURAL := 2);
port (Inputs : BIT_VECTOR(1 to N); Result : out BIT);
end;
Notice that the generic interface list precedes the port interface list. Generics are useful to carry timing (delay) information, as in the
next example:
entity AndT is
generic (TPD : TIME := 1 ns);
port (a, b : BIT := '0'; q: out BIT);
end;
architecture Behave of AndT is
begin q <= a and b after TPD;
end;
entity AndT_Test_1 is end;
architecture Netlist_1 of AndT_Test_1 is
component MyAnd
port (a, b : BIT; q : out BIT);
end component;
signal a1, b1, q1 : BIT := '1';
begin
And1 : MyAnd port map (a1, b1, q1);
end Netlist_1;
configuration Simplest_1 of AndT_Test_1 is use work.all;
for Netlist_1 for And1 : MyAnd
use entity AndT(Behave) generic map (2 ns);
end for; end for;
end Simplest_1;
The configuration declaration, Simplest_1, changes the default delay (equal to 1 ns, declared as a default expression in the entity)
to 2 ns. Techniques based on this method are useful in ASIC design. Prelayout simulation uses the default timing values.
Back-annotation alters the delay in the configuration for postlayout simulation. When we change the delay we only need to reanalyze
the configuration, not the rest of the ASIC model.
There was initially no standard in VHDL for how timing generics should be used, and the lack of a standard was a major problem for
ASIC designers. The IEEE 1076.4 VITAL standard addresses this problem (see Section 13.5.5).
1. There are additional rules for interface objects that are signals (ports)--see Tables 10.11 and 10.12.
2. A signal of mode inout can be updated by any number of sources [VHDL 87LRM4.3.3, 93LRM4.3.2].
3. A signal of mode buffer can be updated by at most one source [VHDL LRM1.1.1.2].
10.8 Type Declarations
In some programming languages you must declare objects to be integer, real, Boolean, and so on.
VHDL (and ADA, the DoD programming language to which VHDL is related) goes further: You must
declare the type of an object, and there are strict rules on mixing objects of different types. We say
VHDL is strongly typed. For example, you can use one type for temperatures in Centigrade and a
different type for Fahrenheit, even though both types are real numbers. If you try to add a temperature
in Centigrade to a temperature in Fahrenheit, VHDL catches your error and tells you that you have a
type mismatch.
This is the formal (expanded) BNF definition of a type declaration:
type_declaration ::=
type identifier ;
| type identifier is
(identifier|'graphic_character' {, identifier|'graphic_character'}) ;
| range_constraint ;
| physical_type_definition ;
| record_type_definition ;
| access subtype_indication ;
| file of type_name ;
| file of subtype_name ;
| array index_constraint of element_subtype_indication ;
| array
(type_name|subtype_name range <>
{, type_name|subtype_name range <>}) of
element_subtype_indication ;
There are four type classes in VHDL [VHDL LRM3]: scalar types, composite types, access types, and
file types. The scalar types are: integer type, floating-point type, physical type, and enumeration type.
Integer and enumeration types are discrete types. Integer, floating-point, and physical types are
numeric types. The range of an integer is implementation dependent but is guaranteed to include
-2147483647 to +2147483647. Notice the integer range is symmetric and equal to -(231- 1) to (231- 1).
Floating-point size is implementation dependent, but the range includes the bounds -1.0E38 and
+1.0E38, and must include a minimum of six decimal digits of precision. Physical types correspond to
time, voltage, current, and so on and have dimensions--a unit of measure (seconds, for example).
Access types are pointers, useful in abstract data structures, but less so in ASIC design. File types are
used for file I/O.
You may also declare a subset of an existing type, known as a subtype, in a subtype declaration. We
shall discuss the different treatment of types and subtypes in expressions in Section 10.12.
Here are some examples of scalar type [VHDL LRM4.1] and subtype declarations [VHDL LRM4.2]:
entity Declaration_1 is end; architecture Behave of Declaration_1 is
type F is range 32 to 212; -- Integer type, ascending range.
type C is range 0 to 100; -- Range 0 to 100 is the range constraint.
subtype G is INTEGER range 9 to 0; -- Base type INTEGER, descending.
-- This is illegal: type Bad100 is INTEGER range 0 to 100;
-- don't use INTEGER in declaration of type (but OK in subtype).
type Rainbow is (R, O, Y, G, B, I, V); -- An enumeration type.
-- Enumeration types always have an ascending range.
type MVL4 is ('X', '0', '1', 'Z');
-- Note that 'X' and 'x' are different character literals.
-- The default initial value is MVL4'LEFT = 'X'.
-- We say '0' and '1' (already enumeration literals
-- for predefined type BIT) are overloaded.
-- Illegal enumeration type: type Bad4 is ("X", "0", "1", "Z");
-- Enumeration literals must be character literals or identifiers.
begin end;
The most common composite type is the array type [VHDL LRM3.2.1]. The following examples
illustrate the semantics of array declarations:
entity Arrays_1 is end; architecture Behave of Arrays_1 is
type Word is array (0 to 31) of BIT; -- a 32-bit array, ascending
type Byte is array (NATURAL range 7 downto 0) of BIT; -- descending
type BigBit is array (NATURAL range <>) of BIT;
-- We call <> a box, it means the range is undefined for now.
-- We call BigBit an unconstrained array.
-- This is OK, we constrain the range of an object that uses
-- type BigBit when we declare the object, like this:
subtype Nibble is BigBit(3 downto 0);
type T1 is array (POSITIVE range 1 to 32) of BIT;
-- T1, a constrained array declaration, is equivalent to a type T2
-- with the following three declarations:
subtype index_subtype is POSITIVE range 1 to 32;
type array_type is array (index_subtype range <>) of BIT;
subtype T2 is array_type (index_subtype);
-- We refer to index_subtype and array_type as being
-- anonymous subtypes of T1 (since they don't really exist).
begin end;
You can assign values to an array using aggregate notation [VHDL LRM7.3.2]:
entity Aggregate_1 is end; architecture Behave of Aggregate_1 is
type D is array (0 to 3) of BIT; type Mask is array (1 to 2) of BIT;
signal MyData : D := ('0', others => '1'); -- positional aggregate
signal MyMask : Mask := (2 => '0', 1 => '1'); -- named aggregate
begin end;
The other composite type is the record type that groups elements together:
entity Record_2 is end; architecture Behave of Record_2 is
type Complex is record real : INTEGER; imag : INTEGER; end record;
signal s1 : Complex := (0, others => 1); signal s2: Complex;
begin s2 <= (imag => 2, real => 1); end;
10.9 Other Declarations
A declaration is one of the following [VHDL LRM4]:
declaration ::=
type_declaration
| subtype_declaration
| object_declaration
| interface_declaration
| alias_declaration
| attribute_declaration
| component_declaration
| entity_declaration
| configuration_declaration | subprogram_declaration
| package_declaration
| group_template_declaration | group_declaration
I discussed entity, configuration, component, package, interface, type, and subtype declarations in Sections 10.5-10.8. Next I shall
discuss the other types of declarations (except for groups or group templates [VHDL 93LRM4.6-4.7], new to VHDL-93, that are
not often used in ASIC design).
10.9.1 Object Declarations
There are four object classes in VHDL: constant, variable, signal, and file [VHDL LRM 4.3.1.1-4.3.1.3]. You use a constant
declaration, signal declaration, variable declaration, or file declaration together with a type. Signals can only be declared in the
declarative region (before the first begin ) of an architecture or block, or in a package (not in a package body). Variables can
only be declared in the declarative region of a process or subprogram (before the first begin ). You can think of signals as
representing real wires in hardware. You can think of variables as memory locations in the computer. Variables are more efficient
than signals because they require less overhead.
You may assign an (explicit) initial value when you declare a type. If you do not provide initial values, the (implicit) default initial
value of a type or subtype T is T'LEFT (the leftmost item in the range of the type). For example:
entity Initial_1 is end; architecture Behave of Initial_1 is
type Fahrenheit is range 32 to 212;
-- Default initial value is 32.
type Rainbow is (R, O, Y, G, B, I, V);
-- Default initial value is R.
type MVL4 is ('X', '0', '1', 'Z');
-- MVL4'LEFT = 'X'.
begin end;
The details of initialization and assignment of initial values are important--it is difficult to implement the assignment of initial
values in hardware--instead it is better to mimic the hardware and use explicit reset signals.
Here are the formal definitions of constant and signal declarations:
constant_declaration ::= constant
identifier {, identifier}:subtype_indication [:= expression] ;
signal_declaration ::= signal
identifier {, identifier}:subtype_indication [register|bus] [:=expression];
I shall explain the use of signals of kind register or bus in Section 10.13.1. Signal declarations are explicit signal declarations
(ports declared in an interface declaration are implicit signal declarations). Here is an example that uses a constant and several
signal declarations:
entity Constant_2 is end;
library IEEE; use IEEE.STD_LOGIC_1164.all;
architecture Behave of Constant_2 is
constant Pi : REAL := 3.14159;
-- A constant declaration.
signal B : BOOLEAN; signal s1, s2: BIT;
signal sum : INTEGER range 0 to 15;
-- Not a new type.
signal SmallBus : BIT_VECTOR (15 downto 0);
-- 16-bit bus.
signal GBus : STD_LOGIC_VECTOR (31 downto 0); bus; -- A guarded signal.
begin end;
Here is the formal definition of a variable declaration:
variable_declaration ::= [shared] variable
identifier {, identifier}:subtype_indication [:= expression] ;
A shared variable can be used to model a varying quantity that is common across several parts of a model, temperature, for
example, but shared variables are rarely used in ASIC design. The following examples show that variable declarations belong
inside a process statement, after the keyword process and before the first appearance of the keyword begin inside a
process:
library IEEE; use IEEE.STD_LOGIC_1164.all; entity Variables_1 is end;
architecture Behave of Variables_1 is begin process
variable i : INTEGER range 1 to 10 := 10; -- Initial value = 10.
variable v : STD_LOGIC_VECTOR (0 to 31) := (others => '0');
begin wait; end process; -- The wait stops an endless cycle.
end;
10.9.2 Subprogram Declarations
VHDL code that you use several times can be declared and specified as subprograms (functions or procedures) [VHDL LRM2.1].
A function is a form of expression, may only use parameters of mode in , and may not contain delays or sequence events during
simulation (no wait statements, for example). Functions are useful to model combinational logic. A procedure is a form of
statement and allows you to control the scheduling of simulation events without incurring the overhead of defining several
separate design entities. There are thus two forms of subprogram declaration: a function declaration or a procedure declaration.
subprogram_declaration ::= subprogram_specification ; ::=
procedure
identifier|string_literal [(parameter_interface_list)]
| [pure|impure] function
identifier|string_literal [(parameter_interface_list)]
return type_name|subtype_name;
Here are a function and a procedure declaration that illustrate the difference:
function add(a, b, c : BIT_VECTOR(3 downto 0)) return BIT_VECTOR is
-- A function declaration, a function can't modify a, b, or c.
procedure Is_A_Eq_B (signal A, B : BIT; signal Y : out BIT);
-- A procedure declaration, a procedure can change Y.
Parameter names in subprogram declarations are called formal parameters (or formals). During a call to a subprogram, known as
subprogram invocation, the passed values are actual parameters (or actuals). An impure function, such as the function now or a
function that writes to or reads from a file, may return different values each time it is called (even with the same actuals). A pure
function (the default) returns the same value if it is given the same actuals. You may call subprograms recursively. Table 10.13
shows the properties of subprogram parameters.
TABLE 10.13
Properties of subprogram parameters.
Example subprogram declarations:
function my_function(Ff) return BIT is -- Formal function parameter, Ff.
procedure my_procedure(Fp);
-- Formal procedure parameter, Fp.
Example subprogram calls:
my_result := my_function(Af); -- Calling a function with an actual parameter, Af.
MY_LABEL:my_procedure(Ap);
-- Using a procedure with an actual parameter, Ap.
out
inout
No mode
Not allowed
Not allowed
file
Permissible classes for Ap
constant (default) constant
constant
(procedure actual parameter)
variable
variable (default) variable (default) file
signal
signal
Mode of Ff or Fp (formals)
in
Permissible classes for Af
constant (default)
(function actual parameter)
signal
signal
Yes, except:
'STABLE 'QUIET
Yes, except:
Yes, except:
'DELAYED
'STABLE
'STABLE
'TRANSACTION
Can you read attributes of
'QUIET
'QUIET
'EVENT 'ACTIVE
Ff or Fp (formals)?
'DELAYED
'DELAYED
'LAST_EVENT
'TRANSACTION
'TRANSACTION
'LAST_ACTIVE
of a signal
of a signal
'LAST_VALUE
of a signal
A subprogram declaration is optional, but a subprogram specification must be included in the subprogram body (and must be
identical in syntax to the subprogram declaration--see BNF [10.19]):
subprogram_body ::=
subprogram_specification is
{subprogram_declaration|subprogram_body
|type_declaration|subtype_declaration
|constant_declaration|variable_declaration|file_declaration
|alias_declaration|attribute_declaration|attribute_specification
|use_clause|group_template_declaration|group_declaration}
begin
{sequential_statement}
end [procedure|function] [identifier|string_literal] ;
You can include a subprogram declaration or subprogram body in a package or package body (see Section 10.6) or in the
declarative region of an entity or process statement. The following is an example of a function declaration and its body:
function subset0(sout0 : in BIT) return BIT_VECTOR -- declaration
-- Declaration can be separate from the body.
function subset0(sout0 : in BIT) return BIT_VECTOR is -- body
variable y : BIT_VECTOR(2 downto 0);
begin
if (sout0 = '0') then y := "000"; else y := "100"; end if;
return result;
end;
procedure clockGen (clk : out BIT)
-- Declaration
procedure clockGen (clk : out BIT) is
-- Specification
begin -- Careful this process runs forever:
process begin wait for 10 ns; clk <= not clk; end process;
end;
One reason for having the optional (and seemingly redundant) subprogram declaration is to allow companies to show the
subprogram declarations (to document the interface) in a package declaration, but to hide the subprogram bodies (the actual code)
in the package body. If a separate subprogram declaration is present, it must conform to the specification in the subprogram body
[VHDL 93LRM2.7]. This means the specification and declaration must be almost identical; the safest method is to copy and paste.
If you define common procedures and functions in packages (instead of in each entity or architecture, for example), it will be
easier to reuse subprograms. In order to make a subprogram included in a package body visible outside the package, you must
declare the subprogram in the package declaration (otherwise the subprogram is private).
You may call a function from any expression, as follows:
entity F_1 is port (s : out BIT_VECTOR(3 downto 0) := "0000"); end;
architecture Behave of F_1 is begin process
function add(a, b, c : BIT_VECTOR(3 downto 0)) return BIT_VECTOR is
begin return a xor b xor c; end;
begin s <= add("0001", "0010", "1000"); wait; end process; end;
package And_Pkg is
procedure V_And(a, b : BIT; signal c : out BIT);
function V_And(a, b : BIT) return BIT;
end;
package body And_Pkg is
procedure V_And(a,b : BIT; signal c : out BIT) is
begin c <= a and b; end;
function V_And(a,b : BIT) return BIT is
begin return a and b; end;
end And_Pkg;
entity F_2 is port (s: out BIT := '0'); end;
use work.And_Pkg.all; -- use package already analyzed
architecture Behave of F_2 is begin process begin
s <= V_And('1', '1'); wait; end process; end;
I shall discuss the two different ways to call a procedure in Sections 10.10.4 and 10.13.3.
10.9.3 Alias and Attribute Declarations
An alias declaration [VHDL 87LRM4.3.4, 93LRM4.3.3] names parts of a type:
alias_declaration ::=
alias
identifier|character_literal|operator_symbol
is name [signature] ;
[ :subtype_indication]
(the subtype indication is required in VHDL-87, but not in VHDL-93).
Here is an example of alias declarations for parts of a floating-point number:
entity Alias_1 is end; architecture Behave of Alias_1 is
begin process variable Nmbr: BIT_VECTOR (31 downto 0);
-- alias declarations to split Nmbr into 3 pieces :
alias Sign : BIT is Nmbr(31);
alias Mantissa : BIT_VECTOR (23 downto 0) is Nmbr (30 downto 7);
alias Exponent : BIT_VECTOR ( 6 downto 0) is Nmbr ( 6 downto 0);
begin wait; end process; end; -- the wait prevents an endless cycle
An attribute declaration [VHDL LRM4.4] defines attribute properties:
attribute_declaration ::=
attribute identifier:type_name ; | attribute identifier:subtype_name ;
Here is an example:
entity Attribute_1 is end; architecture Behave of Attribute_1 is
begin process type COORD is record X, Y : INTEGER; end record;
attribute LOCATION : COORD; -- the attribute declaration
begin wait ; -- the wait prevents an endless cycle
end process; end;
You define the attribute properties in an attribute specification (the following example specifies an attribute of a component label).
You probably will not need to use your own attributes very much in ASIC design.
attribute LOCATION of adder1 : label is (10,15);
You can then refer to your attribute as follows:
positionOfComponent := adder1'LOCATION;
10.9.4 Predefined Attributes
The predefined attributes for scalar and array types in VHDL-93 are shown in Table 10.14 [VHDL 93LRM14.1]. There are two
attributes, 'STRUCTURE and 'BEHAVIOR , that are present in VHDL-87, but removed in VHDL-93. Both of these attributes
apply to architecture bodies. The attribute name A'BEHAVIOR is TRUE if the architecture A does not contain component
instantiations. The attribute name A'STRUCTURE is TRUE if the architecture A contains only passive processes (those with no
assignments to signals) and component instantiations. These two attributes were not widely used. The attributes shown in
Table 10.14, however, are used extensively to create packages and functions for type conversion and overloading operators, but
should not be needed by an ASIC designer. Many of the attributes do not correspond to "real" hardware and cannot be
implemented by a synthesis tool.
TABLE 10.14 Predefined attributes for scalar and array types.
Prefix
Attribute
Kind 1
Parameter X or N 3 Result type 3
Result
T, A, E 2
T'BASE
T
any
base(T)
base(T), use only with other attribute
T'LEFT
V
scalar
T
Left bound of T
T'RIGHT
V
scalar
T
Right bound of T
T'HIGH
V
scalar
T
Upper bound of T
T'LOW
V
scalar
T
Lower bound of T
T'ASCENDING
V
scalar
BOOLEAN
True if range of T is ascending 4
T'IMAGE(X)
F
scalar
base(T)
STRING
String representation of X in T 4
T'VALUE(X)
F
scalar
STRING
base(T)
Value in T with representation X 4
T'POS(X)
F
discrete
base(T)
UI
Position number of X in T (starts at 0)
T'VAL(X)
F
discrete
UI
base(T)
Value of position X in T
T'SUCC(X)
F
discrete
base(T)
base(T)
Value of position X in T plus one
T'PRED(X)
F
discrete
base(T)
base(T)
Value of position X in T minus one
T'LEFTOF(X)
F
discrete
base(T)
base(T)
Value to the left of X in T
T'RIGHTOF(X)
F
discrete
base(T)
base(T)
Value to the right of X in T
A'LEFT[(N)]
F
array
UI
T(Result)
Left bound of index N of array A
A'RIGHT[(N)]
F
array
UI
T(Result)
Right bound of index N of array A
A'HIGH[(N)]
F
array
UI
T(Result)
Upper bound of index N of array A
A'LOW[(N)]
F
array
UI
T(Result)
Lower bound of index N of array A
A'RANGE[(N)]
R
array
UI
T(Result)
Range A'LEFT(N) to A'RIGHT(N) 5
A'REVERSE_RANGE[(N)] R
array
UI
T(Result)
Opposite range to A'RANGE[(N)]
A'LENGTH[(N)]
V
array
UI
UI
Number of values in index N of array
A
A'ASCENDING[(N)]
V
array
UI
BOOLEAN
True if index N of A is ascending 4
E'SIMPLE_NAME
V
name
STRING
Simple name of E 4
E'INSTANCE_NAME
V
name
STRING
Path includes instantiated entities 4
E'PATH_NAME
V
name
STRING
Path excludes instantiated entities 4
The attribute 'LEFT is important because it determines the default initial value of a type. For example, the default initial value
for type BIT is BIT'LEFT , which is '0' . The predefined attributes of signals are listed in Table 10.15. The most important
signal attribute is 'EVENT , which is frequently used to detect a clock edge. Notice that Clock'EVENT , for example, is a
function that returns a value of type BOOLEAN , whereas the otherwise equivalent not(Clock'STABLE) , is a signal. The
difference is subtle but important when these attributes are used in the wait statement that treats signals and values differently.
TABLE 10.15
Predefined attributes for signals.
Attribute
Kind 6 Parameter T 7 Result type 8 Result/restrictions
S'DELAYED [(T)] S
TIME
base(S)
S delayed by time T
S'STABLE [(T)]
S
TIME
BOOLEAN
TRUE if no event on S for time T
S'QUIET [(T)]
S
TIME
BOOLEAN
TRUE if S is quiet for time T
S'TRANSACTION
S
BIT
Toggles each cycle if S becomes active
S'EVENT
F
BOOLEAN
TRUE when event occurs on S
S'ACTIVE
F
BOOLEAN
TRUE if S is active
S'LAST_EVENT
F
TIME
Elapsed time since the last event on S
S'LAST_ACTIVE
F
TIME
Elapsed time since S was active
S'LAST_VALUE
F
base(S)
Previous value of S, before last event 9
S'DRIVING
F
BOOLEAN
TRUE if every element of S is driven 10
base(S)
Value of the driver for S in the current process 10
S'DRIVING_VALUE F
1. T = Type, F = Function, V = Value, R = Range.
2. any = any type or subtype, scalar = scalar type or subtype, discrete = discrete or physical type or subtype, name = entity name =
identifier, character literal, or operator symbol.
3. base(T) = base type of T, T = type of T, UI = universal_integer, T(Result) = type of object described in result column.
4. Only available in VHDL-93. For 'ASCENDING all enumeration types are ascending.
5. Or reverse for descending ranges.
6. F = function, S = signal.
7. Time T >= 0 ns. The default, if T is not present, is T = 0 ns.
8. base(S) = base type of S.
9. VHDL-93 returns last value of each signal in array separately as an aggregate, VHDL-87 returns the last value of the composite
signal.
10. VHDL-93 only.
10.10 Sequential Statements
A sequential statement [VHDL LRM8] is defined as follows:
sequential_statement ::=
wait_statement
| assertion_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement | case_statement | loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement | report_statement
Sequential statements may only appear in processes and subprograms. In the following sections I shall describe each of these different types of sequential statements in turn.
10.10.1 Wait Statement
The wait statement is central to VHDL, here are the BNF definitions [VHDL 93LRM8.1]:
wait_statement ::= [label:] wait [sensitivity_clause]
[condition_clause] [timeout_clause] ;
sensitivity_clause ::= on sensitivity_list
sensitivity_list ::= signal_name { , signal_name }
condition_clause ::= until condition
condition ::= boolean_expression
timeout_clause ::= for time_expression
A wait statement suspends (stops) a process or procedure (you cannot use a wait statement in a function). The wait statement may be made sensitive to events (changes) on static signals (the value of the signal must be
known at analysis time) that appear in the sensitivity list after the keyword on . These signals form the sensitivity set of a wait statement. The process will resume (restart) when an event occurs on any signal (and only signals)
in the sensitivity set.
A wait statement may also contain a condition to be met before the process resumes. If there is no sensitivity clause (there is no keyword on ) the sensitivity set is made from signals (and only signals) from the condition
clause that appears after the keyword until (the rules are quite complicated [VHDL 93LRM8.1]).
Finally a wait statement may also contain a timeout (following the keyword for ) after which the process will resume. Here is the expanded BNF definition, which makes the structure of the wait statement easier to see (but
we lose the definitions of the clauses and the sensitivity list):
wait_statement ::= [label:]
wait
[on signal_name {, signal_name}]
[until boolean_expression]
[for time_expression] ;
For example, the statement, wait on light , makes you wait until a traffic light changes (any change). The statement, wait until light = green , makes you wait (even at a green light) until the traffic signal
changes to green. The statement,
if light = (red or yellow) then wait
until light = green;
end
if;
accurately describes the basic rules at a traffic intersection.
The most common use of the wait statement is to describe synchronous logic, as in the following model of a D flip-flop:
entity DFF is port (CLK, D : BIT; Q : out BIT); end;
architecture Behave of DFF is
process begin wait
until C
lk = '1'; Q <= D ; end process;
end;
Notice that the statement in line 3 above, wait until C lk = '1', is equivalent to wait on Clk until C lk = '1', and detects a clock edge and not the clock level. Here are some more complex examples of the use of the
wait statement:
entity Wait_1 is port (Clk, s1, s2 :in BIT); end;
architecture Behave of Wait_1 is
signal x : BIT_VECTOR (0 to 15);
begin process variable v : BIT; begin
wait;
-- Wait forever, stops simulation.
wait on s1 until s2 = '1'; -- Legal, but s1, s2 are signals so
-- s1 is in sensitivity list, and s2 is not in the sensitivity set.
-- Sensitivity set is s1 and process will not resume at event on s2.
wait on s1, s2; -- resumes at event on signal s1 or s2.
wait on s1 for 10 ns; -- resumes at event on s1 or after 10 ns.
wait on x; -- resumes when any element of array x has an event.
-- wait on x(1 to v); -- Illegal, nonstatic name, since v is a variable.
end process;
end;
entity Wait_2 is port (Clk, s1, s2:in BIT); end;
architecture Behave of Wait_2 is
begin process variable v : BIT; begin
wait on Clk; -- resumes when Clk has an event: rising or falling.
wait until Clk = '1'; -- resumes on rising edge.
wait on Clk until Clk = '1'; -- equivalent to the last statement.
wait on Clk until v = '1';
-- The above is legal, but v is a variable so
-- Clk is in sensitivity list, v is not in the sensitivity set.
-- Sensitivity set is Clk and process will not resume at event on v.
wait on Clk until s1 = '1';
-- The above is legal, but s1 is a signal so
-- Clk is in sensitivity list, s1 is not in the sensitivity set.
-- Sensitivity set is Clk, process will not resume at event on s1.
end process;
end;
You may only use interface signals that may be read (port modes in , inout , and buffer --see Section 10.7) in the sensitivity list of a wait statement.
10.10.2 Assertion and Report Statements
You can use an assertion statement to conditionally issue warnings. The report statement (VHDL-93 only) prints an expression and is useful for debugging.
assertion_statement ::= [label:] assert
boolean_expression [report expression] [severity expression] ;
report_statement
::= [label:] report expression [severity expression] ;
Here is an example of an assertion statement:
entity Assert_1 is port (I:INTEGER:=0); end;
architecture Behave of Assert_1 is
begin process begin
assert (I > 0) report "I is negative or zero"; wait;
end process;
end;
The expression after the keyword report must be of type STRING (the default is "Assertion violation" for the assertion statement), and the expression after the keyword severity must be of type
SEVERITY_LEVEL (default ERROR for the assertion statement, and NOTE for the report statement) defined in the STANDARD package. The assertion statement prints if the assertion condition (after the keyword
assert ) is FALSE . Simulation normally halts for severity of ERROR or FAILURE (you can normally control this threshold in the simulator).
10.10.3 Assignment Statements
There are two sorts of VHDL assignment statements: one for signals and one for variables [VHDL 93LRM8.4-8.5]. The difference is in the timing of the update of the LHS. A variable assignment statement is the closest
equivalent to the assignment statement in a computer programming language. Variable assignment statements are always sequential statements and the LHS of a variable assignment statement is always updated immediately.
Here is the definition and an example:
variable_assignment_statement ::=
[label:] name|aggregate := expression ;
entity Var_Assignment is end;
architecture Behave of Var_Assignment is
signal s1 : INTEGER := 0;
begin process variable v1,v2 : INTEGER := 0; begin
assert (v1/=0) report "v1 is 0" severity note ; -- this prints
v1 := v1 + 1; -- after this statement v1 is 1
assert (v1=0) report "v1 isn't 0" severity note ; -- this prints
v2 := v2 + s1; -- signal and variable types must match
wait;
end process;
end;
This is the output from Cadence Leapfrog for the preceding example:
ASSERT/NOTE (time 0 FS) from :$PROCESS_000 (design unit WORK.VAR_ASSIGNMENT:BEHAVE)
v1 is 0
ASSERT/NOTE (time 0 FS) from :$PROCESS_000 (design unit WORK.VAR_ASSIGNMENT:BEHAVE)
v1 isn't 0
A signal assignment statement schedules a future assignment to a signal:
signal_assignment_statement::=
[label:] target <=
[transport | [ reject time_expression ] inertial ] waveform ;
The following example shows that, even with no delay, a signal is updated at the end of a simulation cycle after all the other assignments have been scheduled, just before simulation time is advanced:
entity Sig_Assignment_1 is end;
architecture Behave of Sig_Assignment_1 is
signal s1,s2,s3 : INTEGER := 0;
begin process variable v1 : INTEGER := 1; begin
assert (s1 /= 0) report "s1 is 0" severity note ; -- this prints.
s1 <= s1 + 1; -- after this statement s1 is still 0.
assert (s1 /= 0) report "s1 still 0" severity note ; -- this prints.
wait;
end process;
end;
ASSERT/NOTE (time 0 FS) from :$PROCESS_000 (design unit WORK.SIG_ASSIGNMENT_1:BEHAVE)
s1 is 0
ASSERT/NOTE (time 0 FS) from :$PROCESS_000 (design unit WORK.SIG_ASSIGNMENT_1:BEHAVE)
s1 still 0
Here is an another example to illustrate how time is handled:
entity Sig_Assignment_2 is end;
architecture Behave of Sig_Assignment_2 is
signal s1, s2, s3 : INTEGER := 0;
begin process variable v1 : INTEGER := 1; begin
-- s1, s2, s3 are initially 0; now consider the following:
s1 <= 1 ; -- schedules updates to s1 at end of 0 ns cycle.
s2 <= s1; -- s2 is 0, not 1.
wait for 1 ns;
s3 <= s1; -- now s3 will be 1 at 1 ns.
wait;
end process;
end;
The Compass simulator produces the following trace file for this example:
Time(fs) + Cycle
s1
s2
s3
---------------------- ------------ ------------ -----------0+ 0:
0
0
0
0+ 1: *
1 *
0
0
...
1000000+ 1:
1
0 *
1
Time is indicated in femtoseconds for each simulation cycle plus the number of delta cycles (we call this delta time, measured in units of delta) needed to calculate all transactions on signals. A transaction consists of a new
value for a signal (which may be the same as the old value) and the time delay for the value to take effect. An asterisk '*' before a value in the preceding trace indicates that a transaction has occurred and the corresponding
signal updated at that time. A transaction that does result in a change in value is an event. In the preceding simulation trace for Sig_Assignment_2:Behave
At 0 ns + 0 delta: all signals are 0 .
At 0 ns + 1 delta: s1 is updated to 1 , s2 is updated to 0 (not to 1 ).
At 1 ns + 1 delta: s3 is updated to a 1 .
The following example shows the behavior of the different delay models: transport and inertial (the default):
entity Transport_1 is end;
architecture Behave of Transport_1 is
signal s1, SLOW, FAST, WIRE : BIT := '0';
begin process begin
s1 <= '1' after 1 ns, '0' after 2 ns, '1' after 3 ns ;
-- schedules s1 to be '1' at t+1 ns, '0' at t+2 ns,'1' at t+3 ns
wait; end process;
-- inertial delay: SLOW rejects pulsewidths less than 5ns:
process (s1) begin SLOW <= s1 after 5 ns ; end process;
-- inertial delay: FAST rejects pulsewidths less than 0.5ns:
process (s1) begin FAST <= s1 after 0.5 ns ; end process;
-- transport delay: WIRE passes all pulsewidths...
process (s1) begin WIRE <= transport s1 after 5 ns ; end process;
end;
Here is the trace file from the Compass simulator:
Time(fs) + Cycle
---------------------0+ 0:
500000+ 0:
1000000+ 0:
1500000+ 0:
2000000+ 0:
2500000+ 0:
3000000+ 0:
3500000+ 0:
5000000+ 0:
6000000+ 0:
7000000+ 0:
8000000+ 0:
s1 slow fast wire
---- ---- ---- ---'0' '0' '0' '0'
'0' '0' *'0' '0'
*'1' '0' '0' '0'
'1' '0' *'1' '0'
*'0' '0' '1' '0'
'0' '0' *'0' '0'
*'1' '0' '0' '0'
'1' '0' *'1' '0'
'1' '0' '1' *'0'
'1' '0' '1' *'1'
'1' '0' '1' *'0'
'1' *'1' '1' *'1'
Inertial delay mimics the behavior of real logic gates, whereas transport delay more closely models the behavior of wires. In VHDL-93 you can also add a separate pulse rejection limit for the inertial delay model as in the
following example:
process (s1) begin RJCT <= reject 2 ns s1 after 5 ns ; end process;
10.10.4 Procedure Call
A procedure call in VHDL corresponds to calling a subroutine in a conventional programming language [VHDL LRM8.6]. The parameters in a procedure call statement are the actual procedure parameters (or actuals); the
parameters in the procedure definition are the formal procedure parameters (or formals). The two are linked using an association list, which may use either positional or named association (association works just as it does for
ports--see Section 10.7.1):
procedure_call_statement ::=
[label:] procedure_name [(parameter_association_list)];
Here is an example:
package And_Pkg is
procedure V_And(a, b : BIT; signal c : out BIT);
function V_And(a, b : BIT) return BIT;
end;
package body And_Pkg is
procedure V_And(a, b : BIT; signal c: out BIT) is
begin c <= a and b; end;
function V_And(a, b: BIT) return BIT is
begin return a and b; end;
end And_Pkg;
use work.And_Pkg.all; entity Proc_Call_1 is end;
architecture Behave of Proc_Call_1 is signal A, B, Y: BIT := '0';
begin process begin V_And (A, B, Y); wait; end process;
end;
Table 10.13 on page 416 explains the rules for formal procedure parameters. There is one other way to call procedures, which we shall cover in Section 10.13.3.
10.10.5 If Statement
An if statement evaluates one or more Boolean expressions and conditionally executes a corresponding sequence of statements [VHDL LRM8.7].
if_statement ::=
[if_label:] if boolean_expression then {sequential_statement}
{elsif boolean_expression then {sequential_statement}}
[else {sequential_statement}]
end if [if_label];
The simplest form of an if statement is thus:
if boolean_expression then {sequential_statement} end if;
Here are some examples of the if statement:
entity If_Then_Else_1 is end;
architecture Behave of If_Then_Else_1 is signal a, b, c: BIT :='1';
begin process begin
if c = '1' then c <= a ; else c <= b; end if; wait;
end process;
end;
entity If_Then_1 is end;
architecture Behave of If_Then_1 is signal A, B, Y : BIT :='1';
begin process begin
if A = B then Y <= A; end if; wait;
end process;
end;
10.10.6 Case Statement
A case statement [VHDL LRM8.8] is a multiway decision statement that selects a sequence of statements by matching an expression with a list of (locally static [VHDL LRM7.4.1]) choices.
case_statement ::=
[case_label:] case expression is
when choice {| choice} => {sequential_statement}
{when choice {| choice} => {sequential_statement}}
end case [case_label];
Case statements are useful to model state machines. Here is an example of a Mealy state machine with an asynchronous reset:
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity sm_mealy is
port (reset, clock, i1, i2 : STD_LOGIC; o1, o2 : out STD_LOGIC);
end sm_mealy;
architecture Behave of sm_mealy is
type STATES is (s0, s1, s2, s3); signal current, new : STATES;
begin
synchronous : process (clock, reset) begin
if To_X01(reset) = '0' then current <= s0;
elsif rising_edge(clock) then current <= new; end if;
end process;
combinational : process (current, i1, i2) begin
case current is
when s0 =>
if To_X01(i1) = '1' then o2 <='0'; o1 <='0'; new <= s2;
else o2 <= '1'; o1 <= '1'; new <= s1; end if;
when s1 =>
if To_X01(i2) = '1' then o2 <='1'; o1 <='0'; new <= s1;
else o2 <='0'; o1 <='1'; new <= s3; end if;
when s2 =>
if To_X01(i2) = '1' then o2 <='0'; o1 <='1'; new <= s2;
else o2 <= '1'; o1 <= '0'; new <= s0; end if;
when s3 => o2 <= '0'; o1 <= '0'; new <= s0;
when others => o2 <= '0'; o1 <= '0'; new <= s0;
end case;
end process;
end Behave;
Each possible value of the case expression must be present once, and once only, in the list of choices (or arms) of the case statement (the list must be exhaustive). You can use '|' (that means 'or') or 'to' to denote a range in
the expression for choice . You may also use the keyword others as the last, default choice (even if the list is already exhaustive, as in the preceding example).
10.10.7 Other Sequential Control Statements
A loop statement repeats execution of a series of sequential statements [VHDL LRM8.9]:
loop_statement ::=
[loop_label:]
[while boolean_expression|for identifier in discrete_range]
loop
{sequential_statement}
end loop [loop_label];
If the loop variable (after the keyword for ) is used, it is only visible inside the loop. A while loop evaluates the Boolean expression before each execution of the sequence of statements; if the expression is TRUE , the
statements are executed. In a for loop the sequence of statements is executed once for each value of the discrete range.
package And_Pkg is function V_And(a, b : BIT) return BIT; end;
package body And_Pkg is function V_And(a, b : BIT) return BIT is
begin return a and b; end; end And_Pkg;
entity Loop_1 is port (x, y : in BIT := '1'; s : out BIT := '0'); end;
use work.And_Pkg.all;
architecture Behave of Loop_1 is
begin loop
s <= V_And(x, y); wait on x, y;
end loop;
end;
The next statement [VHDL LRM8.10] forces completion of the current iteration of a loop (the containing loop unless another loop label is specified). Completion is forced if the condition following the keyword then is TRUE
(or if there is no condition).
next_statement ::=
[label:] next [loop_label] [when boolean_expression];
An exit statement [VHDL LRM8.11] forces an exit from a loop.
exit_statement ::=
[label:] exit [loop_label] [when condition] ;
As an example:
loop wait on Clk; exit when Clk = '0'; end loop;
-- equivalent to: wait until Clk = '0';
The return statement [VHDL LRM8.12] completes execution of a procedure or function.
return_statement ::= [label:] return [expression];
A null statement [VHDL LRM8.13] does nothing (but is useful in a case statement where all choices must be covered, but for some of the choices you do not want to do anything).
null_statement ::= [label:] null;
10.11 Operators
Table 10.16 shows the predefined VHDL operators, listed by their (increasing) order of precedence
[VHDL 93LRM7.2]. The shift operators and the xnor operator were added in VHDL-93.
TABLE 10.16
VHDL predefined operators (listed by increasing order of precedence). 1
logical_operator 2 ::=
and | or | nand | nor | xor | xnor
relational_operator ::=
= | /= | < | <= | > | >=
shift_operator 2 ::=
sll | srl | sla | sra | rol | ror
adding_operator ::=
+|-|&
sign ::=
+|-
multiplying_operator ::=
* | / | mod | rem
miscellaneous_operator ::=
** | abs | not
The binary logical operators (and , or , nand , nor , xor , xnor) and the unary not logical operator
are predefined for types BIT or BOOLEAN and one-dimensional arrays whose element type is BIT or
BOOLEAN . The operands must be of the same base type for the binary logical operators and the same
length if they are arrays. Both operands of relational operators must be of the same type and the result
type is BOOLEAN . The equality operator and inequality operator ('=' and '/=') are defined for all
types (other than file types). The remaining relational operators, ordering operators, are predefined for any
scalar type, and for any one-dimensional array whose elements are of a discrete type (enumeration or
integer type).
The left operand of the shift operators (VHDL-93 only) is a one-dimensional array with element type of
BIT or BOOLEAN ; the right operand must be INTEGER .
The adding operators ('+' and '-') are predefined for any numeric type. You cannot use the adding
operators on BIT or BIT_VECTOR without overloading. The concatenation operator '&' is predefined
for any one-dimensional array type. The signs ('+' and '-') are defined for any numeric type.
The multiplying operators are: '*' , '/' , mod , and rem . The operators '*' and '/' are predefined
for any integer or floating-point type, and the operands and the result are of the same type. The operators
mod and rem are predefined for any integer type, and the operands and the result are of the same type. In
addition, you can multiply an INTEGER or REAL by any physical type and the result is the physical type.
You can also divide a physical type by REAL or INTEGER and the result is the physical type. If you
divide a physical type by the same physical type, the result is an INTEGER (actually type
UNIVERSAL_INTEGER , which is a predefined anonymous type [VHDL LRM7.5]). Once again--you
cannot use the multiplying operators on BIT or BIT_VECTOR types without overloading the operators.
The exponentiating operator, '**' , is predefined for integer and floating-point types. The right operand,
the exponent, is type INTEGER . You can only use a negative exponent with a left operand that is a
floating-point type, and the result is the same type as the left operand. The unary operator abs (absolute
value) is predefined for any numeric type and the result is the same type. The operators abs , '**' , and
not are grouped as miscellaneous operators.
Here are some examples of the use of VHDL operators:
entity Operator_1 is end; architecture Behave of Operator_1 is
begin process
variable b : BOOLEAN; variable bt : BIT := '1'; variable i : INTEGER;
variable pi : REAL := 3.14; variable epsilon : REAL := 0.01;
variable bv4 : BIT_VECTOR (3 downto 0) := "0001";
variable bv8 : BIT_VECTOR (0 to 7);
begin
b
b
bt
bv4
i
i
i
i
:=
:=
:=
:=
:=
:=
:=
:=
"0000" < bv4;
'f' > 'g';
'0' and bt;
not bv4;
1 + 2;
2 ** 3;
7/3;
12 rem 7;
-- b is TRUE, "0000" treated as BIT_VECTOR.
-- b is FALSE, 'dictionary' comparison.
-- bt is '0', analyzer knows '0' is BIT.
-- bv4 is now "1110".
-- Addition, must be compatible types.
-- Exponentiation, exponent must be integer.
-- Division, L/R rounded towards zero, i=2.
-- Remainder, i=5. In general:
-- L rem R = L-((L/R)*R).
i
:= 12 mod 7;
-- modulus, i=5. In general:
-- L mod R = L-(R*N) for an integer N.
-- shift := sll | srl | sla | sra | rol | ror (VHDL-93 only)
bv4 := "1001" srl 2; -- Shift right logical, now bv4="0100".
-- Logical shift fills with T'LEFT.
bv4 := "1001" sra 2; -- Shift right arithmetic, now bv4="0111".
-- Arithmetic shift fills with element at end being vacated.
bv4 := "1001" ror 2; -- Rotate right, now bv4="0110".
-- Rotate wraps around.
-- Integer argument to any shift operator may be negative or zero.
if (pi*2.718)/2.718 = 3.14 then wait; end if; -- This is unreliable.
if (abs(((pi*2.718)/2.718)-3.14)<epsilon) then wait; end if; -- Better.
bv8 := bv8(1 to 7) & bv8(0); -- Concatenation, a left rotation.
wait; end process;
end;
1. The not operator is a logical operator but has the precedence of a miscellaneous operator. 2. Underline
means "new to VHDL-93."
10.12 Arithmetic
The following example illustrates type checking and type conversion in VHDL arithmetic operations [VHDL 93LRM7.3.4-7.3.5]:
entity Arithmetic_1 is end; architecture Behave of Arithmetic_1 is
begin process
variable i : INTEGER := 1; variable r : REAL := 3.33;
variable b : BIT := '1';
variable bv4 : BIT_VECTOR (3 downto 0) := "0001";
variable bv8 : BIT_VECTOR (7 downto 0) := B"1000_0000";
begin
-i := r;
-- you can't assign REAL to INTEGER.
-bv4 := bv4 + 2;
-- you can't add BIT_VECTOR and INTEGER.
-bv4 := '1';
-- you can't assign BIT to BIT_VECTOR.
-bv8 := bv4;
-- an error, the arrays are different sizes.
r
:= REAL(i);
-- OK, uses a type conversion.
i
:= INTEGER(r);
-- OK (0.5 rounds up or down).
bv4
:= "001" & '1';
-- OK, you can mix an array and a scalar.
bv8
:= "0001" & bv4;
-- OK, if arguments are the correct lengths.
wait; end process; end;
The next example shows arithmetic operations between types and subtypes, and also illustrates range checking during analysis and simulation:
entity Arithmetic_2 is end; architecture Behave of Arithmetic_2 is
type TC is range 0 to
100;
-- Type INTEGER.
type TF is range 32 to
212;
-- Type INTEGER.
subtype STC is INTEGER range 0 to
100;
-- Subtype of type INTEGER.
subtype STF is INTEGER range 32 to
212;
-- Base type is INTEGER.
begin process
variable t1 : TC := 25;
variable t2 : TF := 32;
variable st1 : STC := 25; variable st2 : STF := 32;
begin
-t1
:= t2;
-- Illegal, different types.
-t1
:= st1;
-- Illegal, different types and
subtypes.
st2
:= st1;
-- OK to use same base types.
st2
:= st1 + 1;
-- OK to use subtype and base type.
-st2
:= 213;
-- Error, outside range at analysis
time.
-st2
:= 212 + 1;
-- Error, outside range at analysis
time.
st1
:= st1 + 100;
-- Error, outside range at
initialization.
wait; end process; end;
The MTI simulator, for example, gives the following informative error message during simulation of the preceding model:
# ** Fatal: Value 25 is out of range 32 to 212
#
Time: 0 ns Iteration: 0 Instance:/
# Stopped at Arithmetic_2.vhd line 12
# Fatal error at Arithmetic_2.vhd line 12
The assignment st2 := st1 causes this error (since st1 is initialized to 25).
Operations between array types and subtypes are a little more complicated as the following example illustrates:
entity Arithmetic_3 is end; architecture Behave of Arithmetic_3 is
type TYPE_1 is array (INTEGER range 3 downto 0) of BIT;
type TYPE_2 is array (INTEGER range 3 downto 0) of BIT;
subtype SUBTYPE_1 is BIT_VECTOR (3 downto 0);
subtype SUBTYPE_2 is BIT_VECTOR (3 downto 0);
begin process
variable bv4 : BIT_VECTOR (3 downto 0) := "0001";
variable st1 : SUBTYPE_1 := "0001"; variable t1 : TYPE_1 := "0001";
variable st2 : SUBTYPE_2 := "0001"; variable t2 : TYPE_2 := "0001";
begin
bv4 := st1;
-- OK, compatible type and subtype.
-bv4 := t1;
-- Illegal, different types.
bv4 := BIT_VECTOR(t1);
-- OK, type conversion.
st1 := bv4;
-- OK, compatible subtype and base type.
-st1 := t1;
-- Illegal, different types.
st1 := SUBTYPE_1(t1);
-- OK, type conversion.
-t1 := st1;
-- Illegal, different types.
-t1 := bv4;
-- Illegal, different types.
t1 := TYPE_1(bv4);
-- OK, type conversion.
-t1 := t2;
-- Illegal, different types.
t1 := TYPE_1(t2);
-- OK, type conversion.
st1 := st2;
-- OK, compatible subtypes.
wait; end process; end;
The preceding example uses BIT and BIT_VECTOR types, but exactly the same considerations apply to STD_LOGIC and STD_LOGIC_VECTOR types or other arrays. Notice the use of type
conversion, written as type_mark'(expression), to convert between closely related types. Two types are closely related if they are abstract numeric types (integer or floating-point) or arrays with the
same dimension, each index type is the same (or are themselves closely related), and each element has the same type [VHDL 93LRM7.3.5].
10.12.1 IEEE Synthesis Packages
The IEEE 1076.3 standard synthesis packages allow you to perform arithmetic on arrays of the type BIT and STD_LOGIC . 1 The NUMERIC_BIT package defines all of the operators in
Table 10.16 (except for the exponentiating operator '**' ) for arrays of type BIT . Here is part of the package header, showing the declaration of the two types UNSIGNED and SIGNED , and an
example of one of the function declarations that overloads the addition operator '+' for UNSIGNED arguments:
package Part_NUMERIC_BIT is
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
function "+" (L, R : UNSIGNED) return UNSIGNED;
-- other function definitions that overload +, -, = , >, and so on.
end Part_NUMERIC_BIT;
The package bodies included in the 1076.3 standard define the functionality of the packages. Companies may implement the functions in any way they wish--as long as the results are the same as
those defined by the standard. Here is an example of the parts of the NUMERIC_BIT package body that overload the addition operator '+' for two arguments of type UNSIGNED (even with my
added comments the code is rather dense and terse, but remember this is code that we normally never see or need to understand):
package body Part_NUMERIC_BIT is
constant NAU : UNSIGNED(0 downto 1) := (others =>'0'); -- Null array.
constant NAS : SIGNED(0 downto 1):=(others => '0'); -- Null array.
constant NO_WARNING : BOOLEAN := FALSE; -- Default to emit warnings.
function MAX (LEFT, RIGHT : INTEGER) return INTEGER is
begin -- Internal function used to find longest of two inputs.
if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end MAX;
function ADD_UNSIGNED (L, R : UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT : INTEGER := L'LENGTH-1; -- L, R must be same length.
alias XL : UNSIGNED(L_LEFT downto 0) is L; -- Descending alias,
alias XR : UNSIGNED(L_LEFT downto 0) is R; -- aligns left ends.
variable RESULT : UNSIGNED(L_LEFT downto 0); variable CBIT : BIT := C;
begin for I in 0 to L_LEFT loop -- Descending alias allows loop.
RESULT(I) := CBIT xor XL(I) xor XR(I); -- CBIT = carry, initially = C.
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop; return RESULT; end ADD_UNSIGNED;
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is
constant ARG_LEFT : INTEGER := ARG'LENGTH-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; -- Descending range.
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin -- resize the input ARG to length NEW_SIZE
if (NEW_SIZE < 1) then return NAU; end if; -- Return null array.
if XARG'LENGTH = 0 then return RESULT; end if; -- Null to empty.
if (RESULT'LENGTH < ARG'LENGTH) then -- Check lengths.
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else -- Need to pad the result with some '0's.
RESULT(RESULT'LEFT downto XARG'LEFT + 1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if; return RESULT;
end RESIZE;
function "+" (L, R : UNSIGNED) return UNSIGNED is -- Overloaded '+'.
constant SIZE : NATURAL := MAX(L'LENGTH, R'LENGTH);
begin -- If length of L or R < 1 return a null array.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0'); end "+";
end Part_NUMERIC_BIT;
The following conversion functions are also part of the NUMERIC_BIT package:
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
function TO_INTEGER (ARG : SIGNED) return INTEGER;
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED;
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED;
-- set XMAP to convert unknown values, default is 'X'->'0'
function TO_01(S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED;
function TO_01(S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED;
The NUMERIC_STD package is almost identical to the NUMERIC_BIT package except that the UNSIGNED and SIGNED types are declared in terms of the STD_LOGIC type from the
Std_Logic_1164 package as follows:
library IEEE; use IEEE.STD_LOGIC_1164.all;
package Part_NUMERIC_STD is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
end Part_NUMERIC_STD;
The NUMERIC_STD package body is similar to NUMERIC_BIT with the addition of a comparison function called STD_MATCH , illustrated by the following:
-- function STD_MATCH (L, R: T) return BOOLEAN;
-- T = STD_ULOGIC UNSIGNED SIGNED STD_LOGIC_VECTOR STD_ULOGIC_VECTOR
The STD_MATCH function uses the following table to compare logic values:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE : BOOLEAN_TABLE := (
---------------------------------------------------------------------- U
X
0
1
Z
W
L
H
--------------------------------------------------------------------(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | U |
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | X |
(FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE,FALSE, TRUE), -- | 0 |
(FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE, TRUE), -- | 1 |
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | Z |
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | W |
(FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE,FALSE, TRUE), -- | L |
(FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE, TRUE), -- | H |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE));-- | - |
Thus, for example (notice we need type conversions):
IM_TRUE = STD_MATCH(STD_LOGIC_VECTOR
STD_LOGIC_VECTOR
("10HLXWZ-"),
("HL10----"))
-- is TRUE
The following code is similar to the first simple example of Section 10.1, but illustrates the use of the Std_Logic_1164 and NUMERIC_STD packages:
entity Counter_1 is end;
library STD; use STD.TEXTIO.all;
library IEEE; use IEEE.STD_LOGIC_1164.all;
use work.NUMERIC_STD.all;
architecture Behave_2 of Counter_1 is
signal Clock : STD_LOGIC := '0';
signal Count : UNSIGNED (2 downto 0) := "000";
begin
process begin
wait for 10 ns; Clock <= not Clock;
if (now > 340 ns) then wait;
end if;
end process;
process begin
wait until (Clock = '0');
if (Count = 7)
then Count <= "000";
else Count <= Count + 1;
end if;
end process;
process (Count) variable L: LINE; begin write(L, now);
write(L, STRING'(" Count=")); write(L, TO_INTEGER(Count));
writeline(output, L);
end process;
end;
The preceding code looks similar to the code in Section 10.1 (and the output is identical), but there is more going on here:
● Line 3 is a library clause and a use clause for the std_logic_1164 package, so you can use the STD_LOGIC type and the NUMERIC_BIT package.
● Line 4 is a use clause for NUMERIC_BIT package that was previously analyzed into the library work . If the package is instead analyzed into the library IEEE , you would use the name
IEEE.NUMERIC_BIT.all here. The NUMERIC_BIT package allows you to use the type UNSIGNED .
● Line 6 declares Clock to be type STD_LOGIC and initializes it to '0' , instead of the default initial value STD_LOGIC'LEFT (which is 'U' ).
● Line 7 declares Count to be a 3-bit array of type UNSIGNED from NUMERIC_BIT and initializes it using a bit-string literal.
● Line 10 uses the overloaded 'not' operator from std_logic_1164 .
● Line 15 uses the overloaded '=' operator from std_logic_1164 .
● Line 16 uses the overloaded '=' operator from NUMERIC_BIT .
● Line 17 requires a bit-string literal, you cannot use Count <= 0 here.
● Line 18 uses the overloaded '+' operator from NUMERIC_BIT .
● Line 22 converts Count , type UNSIGNED , to type INTEGER .
1. IEEE Std 1076.3-1997 was approved by the IEEE Standards Board on 20 March 1997. The synthesis package code on the following pages is reprinted with permission from IEEE Std
1076.3-1997, Copyright © 1997 IEEE. All rights reserved.
10.13 Concurrent Statements
A concurrent statement [VHDL LRM9] is one of the following statements:
concurrent_statement ::=
block_statement
| process_statement
| [ label : ] [ postponed ] procedure_call ;
| [ label : ] [ postponed ] assertion ;
| [ label : ] [ postponed ] conditional_signal_assignment
| [ label : ] [ postponed ] selected_signal_assignment
| component_instantiation_statement
| generate_statement
The following sections describe each of these statements in turn.
10.13.1 Block Statement
A block statement has the following format [VHDL LRM9.1]:
block_statement ::=
block_label: block [(guard_expression)] [is]
[generic (generic_interface_list);
[generic map (generic_association_list);]]
[port (port_interface_list);
[port map (port_association_list);]]
{block_declarative_item}
begin
{concurrent_statement}
end block [block_label] ;
Blocks may have their own ports and generics and may be used to split an architecture into several hierarchical parts
(blocks can also be nested). As a very general rule, for the same reason that it is better to split a computer program
into separate small modules, it is usually better to split a large architecture into smaller separate entity-architecture
pairs rather than several nested blocks.
A block does have a unique feature: It is possible to specify a guard expression for a block. This creates a special
signal, GUARD , that you can use within the block to control execution [VHDL LRM9.5]. It also allows you to
model three-state buses by declaring guarded signals (signal kinds register and bus).
When you make an assignment statement to a signal, you define a driver for that signal. If you make assignments to
guarded signals in a block, the driver for that signal is turned off, or disconnected, when the GUARD signal is FALSE
. The use of guarded signals and guarded blocks can become quite complicated, and not all synthesis tools support
these VHDL features.
The following example shows two drivers, A and B , on a three-state bus TSTATE , enabled by signals OEA and OEB
. The drivers are enabled by declaring a guard expression after the block declaration and using the keyword
guarded in the assignment statements. A disconnect statement [VHDL LRM5.3] models the driver delay from
driving the bus to the high-impedance state (time to "float").
library ieee; use ieee.std_logic_1164.all;
entity bus_drivers is end;
architecture Structure_1 of bus_drivers is
signal TSTATE: STD_LOGIC bus; signal A, B, OEA, OEB : STD_LOGIC:= '0';
begin
process begin OEA <= '1' after 100 ns, '0' after 200 ns;
OEB <= '1' after 300 ns; wait; end process;
B1 : block (OEA = '1')
disconnect all : STD_LOGIC after 5 ns; -- Only needed for float time.
begin TSTATE <= guarded not A after 3 ns; end block;
B2 : block (OEB = '1')
disconnect all : STD_LOGIC after 5 ns; -- Float time = 5 ns.
begin TSTATE <= guarded not B after 3 ns; end block;
end;
Time(fs) + Cycle
---------------------0+ 0:
0+ 1:
100000000+ 0:
103000000+ 0:
200000000+ 0:
200000000+ 1:
300000000+ 0:
303000000+ 0:
1
2
3
4
5
tstate
a
b oea oeb
------ ---- ---- ---- ---'U' '0' '0' '0' '0'
* 'Z' '0' '0' '0' '0'
'Z' '0' '0' *'1' '0'
* '1' '0' '0' '1' '0'
'1' '0' '0' *'0' '0'
* 'Z' '0' '0' '0' '0'
'Z' '0' '0' '0' *'1'
* '1' '0' '0' '0' '1'
6
7
b1.GUARD b2.GUARD
-------- -------FALSE
FALSE
FALSE
FALSE
*
TRUE
FALSE
TRUE
FALSE
* FALSE
FALSE
FALSE
FALSE
FALSE *
TRUE
FALSE
TRUE
Notice the creation of implicit guard signals b1.GUARD and b2.GUARD for each guarded block. There is another,
equivalent, method that uses the high-impedance value explicitly as in the following example:
architecture Structure_2 of bus_drivers is
signal TSTATE : STD_LOGIC; signal A, B, OEA, OEB : STD_LOGIC := '0';
begin
process begin
OEA <= '1' after 100 ns, '0' after 200 ns; OEB <= '1' after 300 ns; wait; end
process;
process(OEA, OEB, A, B) begin
if
(OEA = '1') then TSTATE <= not A after 3 ns;
elsif (OEB = '1') then TSTATE <= not B after 3 ns;
else TSTATE <= 'Z' after 5 ns;
end if;
end process;
end;
This last method is more widely used than the first, and what is more important, more widely accepted by synthesis
tools. Most synthesis tools are capable of recognizing the value 'Z' on the RHS of an assignment statement as a
cue to synthesize a three-state driver. It is up to you to make sure that multiple drivers are never enabled
simultaneously to cause contention.
10.13.2 Process Statement
A process statement has the following format [VHDL LRM9.2]:
process_statement ::=
[process_label:]
[postponed] process [(signal_name {, signal_name})]
[is] {subprogram_declaration
| subprogram_body
| type_declaration | subtype_declaration
| constant_declaration
| variable_declaration
| file_declaration | alias_declaration
| attribute_declaration
| attribute_specification
| use_clause
| group_declaration
| group_template_declaration}
begin
{sequential_statement}
end [postponed] process [process_label];
The following process models a 2:1 MUX (combinational logic):
entity Mux_1 is port (i0, i1, sel : in BIT := '0'; y : out BIT); end;
architecture Behave of Mux_1 is
begin process (i0, i1, sel) begin -- i0, i1, sel = sensitivity set
case sel is when '0' => y <= i0; when '1' => y <= i1; end case;
end process; end;
This process executes whenever an event occurs on any of the signals in the process sensitivity set (i0, i1, sel). The
execution of a process occurs during a simulation cycle--a delta cycle. Assignment statements to signals may trigger
further delta cycles. Time advances when all transactions for the current time step are complete and all signals
updated.
The following code models a two-input AND gate (combinational logic):
entity And_1 is port (a, b : in BIT := '0'; y : out BIT); end;
architecture Behave of And_1 is
begin process (a, b) begin y <= a and b; end process; end;
The next example models a D flip-flop (sequential logic). The process statement is executed whenever there is
an event on clk . The if statement updates the output q with the input d on the rising edge of the signal clk . If
the if statement condition is false (as it is on the falling edge of clk ), then the assignment statement q <= d will
not be executed, and q will keep its previous value. The process thus requires the value of q to be stored between
successive process executions, and this implies sequential logic.
entity FF_1 is port (clk, d: in BIT := '0'; q : out BIT); end;
architecture Behave of FF_1 is
begin process (clk) begin
if clk'EVENT and clk = '1' then q <= d; end if;
end process; end;
The behavior of the next example is identical to the previous model. Notice that the wait statement is at the end of
the equivalent process with the signals in the sensitivity set (in this case just one signal, clk ) included in the
sensitivity list (that follows the keyword on ).
entity FF_2 is port (clk, d: in BIT := '0'; q : out BIT); end;
architecture Behave of FF_2 is
begin process begin -- The equivalent process has a wait at the end:
if clk'event and clk = '1' then q <= d; end if; wait on clk;
end process; end;
If we use a wait statement in a process statement, then we may not use a process sensitivity set (the reverse is
true: If we do not have a sensitivity set for a process, we must include a wait statement or the process will execute
endlessly):
entity FF_3 is port (clk, d: in BIT := '0'; q : out BIT); end;
architecture Behave of FF_3 is
begin process begin -- No sensitivity set with a wait statement.
wait until clk = '1'; q <= d;
end process; end;
If you include ports (interface signals) in the sensitivity set of a process statement, they must be ports that can be
read (they must be of mode in , inout , or buffer , see Section 10.7).
10.13.3 Concurrent Procedure Call
A concurrent procedure call appears outside a process statement [VHDL LRM9.3]. The concurrent procedure call
is a shorthand way of writing an equivalent process statement that contains a procedure call (Section 10.10.4):
package And_Pkg is procedure V_And(a,b:BIT; signal c:out BIT); end;
package body And_Pkg is procedure V_And(a,b:BIT; signal c:out BIT) is
begin c <= a and b; end; end And_Pkg;
use work.And_Pkg.all; entity Proc_Call_2 is end;
architecture Behave of Proc_Call_2 is signal A, B, Y : BIT := '0';
begin V_And (A, B, Y); -- Concurrent procedure call.
process begin wait; end process; -- Extra process to stop.
end;
10.13.4 Concurrent Signal Assignment
There are two forms of concurrent signal assignment statement. A selected signal assignment statement is equivalent
to a case statement inside a process statement [VHDL LRM9.5.2]:
selected_signal_assignment ::=
with expression select
name|aggregate <= [guarded]
[transport|[reject time_expression] inertial]
waveform when choice {| choice}
{, waveform when choice {| choice} } ;
The following design unit, Selected_1, uses a selected signal assignment. The equivalent unit, Selected_2, uses a
case statement inside a process statement.
entity Selected_1 is end; architecture Behave of Selected_1 is
signal y,i1,i2 : INTEGER; signal sel : INTEGER range 0 to 1;
begin with sel select y <= i1 when 0, i2 when 1; end;
entity Selected_2 is end; architecture Behave of Selected_2 is
signal i1,i2,y : INTEGER; signal sel : INTEGER range 0 to 1;
begin process begin
case sel is when 0 => y <= i1; when 1 => y <= i2; end case;
wait on i1, i2;
end process; end;
The other form of concurrent signal assignment is a conditional signal assignment statement that, in its most general
form, is equivalent to an if statement inside a process statement [VHDL LRM9.5.1]:
conditional_signal_assignment ::=
name|aggregate <= [guarded]
[transport|[reject time_expression] inertial]
{waveform when boolean_expression else}
waveform [when boolean_expression];
Notice that in VHDL-93 the else clause is optional. Here is an example of a conditional signal assignment,
followed by a model using the equivalent process with an if statement:
entity Conditional_1 is end; architecture Behave of Conditional_1 is
signal y,i,j : INTEGER; signal clk : BIT;
begin y <= i when clk = '1' else j; -- conditional signal assignment
end;
entity Conditional_2 is end; architecture Behave of Conditional_2 is
signal y,i : INTEGER; signal clk : BIT;
begin process begin
if clk = '1' then y <= i; else y <= y ; end if; wait on clk;
end process; end;
A concurrent signal assignment statement can look just like a sequential signal assignment statement, as in the
following example:
entity Assign_1 is end; architecture Behave of Assign_1 is
signal Target, Source : INTEGER;
begin Target <= Source after 1 ns; -- looks like signal assignment
end;
However, outside a process statement, this statement is a concurrent signal assignment and has its own equivalent
process statement. Here is the equivalent process for the example:
entity Assign_2 is end; architecture Behave of Assign_2 is
signal Target, Source : INTEGER;
begin process begin
Target <= Source after 1 ns; wait on Source;
end process; end;
Every process is executed once during initialization. In the previous example, an initial value will be scheduled to be
assigned to Target even though there is no event on Source . If, for some reason, you do not want this to
happen, you need to rewrite the concurrent assignment statement as a process statement with a wait statement
before the assignment statement:
entity Assign_3 is end; architecture Behave of Assign_3 is
signal Target, Source : INTEGER; begin process begin
wait on Source; Target <= Source after 1 ns;
end process; end;
10.13.5 Concurrent Assertion Statement
A concurrent assertion statement is equivalent to a passive process statement (without a sensitivity list) that
contains an assertion statement followed by a wait statement [VHDL LRM9.4].
concurrent_assertion_statement
::= [ label : ] [ postponed ] assertion ;
If the assertion condition contains a signal, then the equivalent process statement will include a final wait
statement with a sensitivity clause. A concurrent assertion statement with a condition that is static expression is
equivalent to a process statement that ends in a wait statement that has no sensitivity clause. The equivalent
process will execute once, at the beginning of simulation, and then wait indefinitely.
10.13.6 Component Instantiation
A component instantiation statement in VHDL is similar to placement of a component in a schematic--an
instantiated component is somewhere between a copy of the component and a reference to the component. Here is
the definition [VHDL LRM9.6]:
component_instantiation_statement ::=
instantiation_label:
[component] component_name
|entity entity_name [(architecture_identifier)]
|configuration configuration_name
[generic map (generic_association_list)]
[port map (port_association_list)] ;
We examined component instantiation using a component_name in Section 10.5. If we instantiate a component in
this way we must declare the component (see BNF [10.9]). To bind a component to an entity-architecture pair we
can use a configuration, as illustrated in Figure 10.1, or we can use the default binding as described in Section 10.7.
In VHDL-93 we have another alternative--we can directly instantiate an entity or configuration. For example:
entity And_2 is port (i1, i2 : in BIT; y : out BIT); end;
architecture Behave of And_2 is begin y <= i1 and i2; end;
entity Xor_2 is port (i1, i2 : in BIT; y : out BIT); end;
architecture Behave of Xor_2 is begin y <= i1 xor i2; end;
entity Half_Adder_2 is port (a,b : BIT := '0'; sum, cry : out BIT); end;
architecture Netlist_2 of Half_Adder_2 is
use work.all; -- need this to see the entities Xor_2 and And_2
begin
X1 : entity Xor_2(Behave) port map (a, b, sum); -- VHDL-93 only
A1 : entity And_2(Behave) port map (a, b, cry); -- VHDL-93 only
end;
10.13.7 Generate Statement
A generate statement [VHDL LRM9.7] simplifies repetitive code:
generate_statement ::=
generate_label:
for generate_parameter_specification
|if boolean_expression
generate [{block_declarative_item} begin]
{concurrent_statement}
end generate [generate_label] ;
Here is an example (notice the labels are required):
entity Full_Adder is port (X, Y, Cin : BIT; Cout, Sum: out BIT); end;
architecture Behave of Full_Adder is begin Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin); end;
entity Adder_1 is
port (A, B : in BIT_VECTOR (7 downto 0) := (others => '0');
Cin : in BIT := '0'; Sum : out BIT_VECTOR (7 downto 0);
Cout : out BIT); end;
architecture Structure of Adder_1 is use work.all;
component Full_Adder port (X, Y, Cin: BIT; Cout, Sum: out BIT);
end component;
signal C : BIT_VECTOR(7 downto 0);
begin AllBits : for i in 7 downto 0 generate
LowBit : if i = 0 generate
FA : Full_Adder port map (A(0), B(0), Cin, C(0), Sum(0));
end generate;
OtherBits : if i /= 0 generate
FA : Full_Adder port map (A(i), B(i), C(i-1), C(i), Sum(i));
end generate;
end generate;
Cout <= C(7);
end;
The instance names within a generate loop include the generate parameter. For example for i=6 ,
FA'INSTANCE_NAME is
:adder_1(structure):allbits(6):otherbits:fa:
10.14 Execution
Two successive statements may execute in either a concurrent or sequential fashion depending on where the statements appear.
statement_1; statement_2;
In sequential execution, statement_1 in this sequence is always evaluated before statement 2 . In concurrent execution, statement_1 and
statement_2 are evaluated at the same time (as far as we are concerned--obviously on most computers exactly parallel execution is not possible).
Concurrent execution is the most important difference between VHDL and a computer programming language. Suppose we have two signal assignment
statements inside a process statement. In this case statement_1 and statement_2 are sequential assignment statements:
entity Sequential_1 is end; architecture Behave of Sequential_1 is
signal s1, s2 : INTEGER := 0;
begin
process begin
s1 <= 1;
-- sequential signal assignment 1
s2 <= s1 + 1; -- sequential signal assignment 2
wait on s1, s2 ;
end process;
end;
Time(fs) + Cycle
s1
s2
---------------------- ------------ -----------0+ 0:
0
0
0+ 1: *
1 *
1
0+ 2: *
1 *
2
0+ 3: *
1 *
2
If the two statements are outside a process statement they are concurrent assignment statements, as in the following example:
entity Concurrent_1 is end; architecture Behave of Concurrent_1 is
signal s1, s2 : INTEGER := 0; begin
L1 : s1 <= 1;
-- concurrent signal assignment 1
L2 : s2 <= s1 + 1; -- concurrent signal assignment 2
end;
Time(fs) + Cycle
s1
s2
---------------------- ------------ -----------0+ 0:
0
0
0+ 1: *
1 *
1
0+ 2:
1 *
2
The two concurrent signal assignment statements in the previous example are equivalent to the two processes, labeled as P1 and P2 , in the following
model.
entity Concurrent_2 is end; architecture Behave of Concurrent_2 is
signal s1, s2 : INTEGER := 0; begin
P1 : process begin s1 <= 1;
wait on s2 ; end process;
P2 : process begin s2 <= s1 + 1; wait on s1 ; end process;
end;
Time(fs) + Cycle
s1
s2
---------------------- ------------ -----------0+ 0:
0
0
0+ 1: *
1 *
1
0+ 2: *
1 *
2
0+ 3: *
1
2
Notice that the results are the same (though the trace files are slightly different) for the architectures Sequential_1, Concurrent_1, and
Concurrent_2. Updates to signals occur at the end of the simulation cycle, so the values used will always be the old values. So far things seem fairly
simple: We have sequential execution or concurrent execution. However, variables are updated immediately, so the variable values that are used are always
the new values. The examples in Table 10.17 illustrate this very important difference.
TABLE 10.17 Variables and signals in VHDL.
Variables
Signals
entity Execute_1 is end;
entity Execute_2 is end;
architecture Behave of Execute_1 is
architecture Behave of Execute_2 is
begin
signal s1 : INTEGER := 1;
process
signal s2 : INTEGER := 2;
variable v1 : INTEGER := 1;
begin
variable v2 : INTEGER := 2;
process
begin
begin
v1 := v2; -- before: v1 = 1, v2 = 2
s1 <= s2; -- before: s1 = 1, s2 = 2
v2 := v1; -- after: v1 = 2, v2 = 2
s2 <= s1; -- after: s1 = 2, s2 = 1
wait;
wait;
end process;
end process;
end;
end;
The various concurrent and sequential statements in VHDL are summarized in Table 10.18.
TABLE 10.18 Concurrent and sequential statements in VHDL.
Concurrent [VHDL LRM9]
Sequential [VHDL LRM8]
block
wait
case
assertion
loop
signal_assignment
next
variable_assignment
exit
procedure_call
return
if
null
process
concurrent_procedure_call
concurrent_assertion
concurrent_signal_assignment
component_instantiation
generate
10.15 Configurations and Specifications
The difference between, the interaction, and the use of component/configuration declarations and specifications is probably the most
confusing aspect of VHDL. Fortunately this aspect of VHDL is not normally important for ASIC design. The syntax of
component/configuration declarations and specifications is shown in Table 10.19.
TABLE 10.19 VHDL binding.
configuration
declaration 1
[VHDL LRM1.3]
configuration identifier of entity_name is
{use_clause|attribute_specification|group_declaration}
block_configuration
end [configuration] [configuration_identifier];
block
for architecture_name
configuration
|block_statement_label
[VHDL LRM1.3.1]
|generate_statement_label [(index_specification)]
{use selected_name {, selected_name};}
{block_configuration|component_configuration}
end for ;
configuration
for
specification 1
instantiation_label{,instantiation_label}:component_name
|others:component_name
[VHDL LRM5.2]
|all:component_name
[use
entity entity_name [(architecture_identifier)]
|configuration configuration_name
|open]
[generic map (generic_association_list)]
[port map (port_association_list)];
component
declaration 1
[VHDL LRM4.5]
component identifier [is]
[generic (local_generic_interface_list);]
[port (local_port_interface_list);]
end component [component_identifier];
component
for
configuration 1 instantiation_label {, instantiation_label}:component_name
[VHDL LRM1.3.2] |others:component_name
|all:component_name
[[use
entity entity_name [(architecture_identifier)]
|configuration configuration_name
|open]
[generic map (generic_association_list)]
[port map (port_association_list)];]
[block_configuration]
end for;
●
●
●
●
●
A configuration declaration defines a configuration--it is a library unit and is one of the basic units of VHDL code.
A block configuration defines the configuration of a block statement or a design entity. A block configuration appears inside a
configuration declaration, a component configuration, or nested in another block configuration.
A configuration specification may appear in the declarative region of a generate statement, block statement, or architecture body.
A component declaration may appear in the declarative region of a generate statement, block statement, architecture body, or
package.
A component configuration defines the configuration of a component and appears in a block configuration.
Table 10.20 shows a simple example (identical in structure to the example of Section 10.5) that illustrates the use of each of the preceding
constructs.
TABLE 10.20 VHDL binding examples.
entity AD2 is port (A1, A2: in
architecture B of AD2 is begin
entity XR2 is port (X1, X2: in
architecture B of XR2 is begin
BIT;
Y <=
BIT;
Y <=
Y:
A1
Y:
X1
out
and
out
xor
BIT); end;
A2; end;
BIT); end;
X2; end;
component
declaration
configuration
specification
entity Half_Adder is port (X, Y: BIT; Sum, Cout: out BIT); end;
architecture Netlist of Half_Adder is use work.all;
component MX port (A, B: BIT; Z :out BIT);end component;
component MA port (A, B: BIT; Z :out BIT);end component;
for G1:MX use entity XR2(B) port map(X1 => A,X2 => B,Y => Z);
begin
G1:MX port map(X, Y, Sum); G2:MA port map(X, Y, Cout);
end;
configuration C1 of Half_Adder is
configuration
use work.all;
declaration
for Netlist
block
for G2:MA
configuration
use entity AD2(B) port map(A1 => A,A2 => B,Y => Z);
component
end for;
configuration
end for;
end;
1. Underline means "new to VHDL-93".
10.16 An Engine Controller
This section describes part of a controller for an automobile engine. Table 10.21 shows a temperature converter that converts
digitized temperature readings from a sensor from degrees Centigrade to degrees Fahrenheit.
TABLE 10.21 A temperature converter.
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- type STD_LOGIC, rising_edge
use IEEE.NUMERIC_STD.all ; -- type UNSIGNED, "+", "/"
entity tconv is generic TPD : TIME:= 1 ns;
port (T_in : in UNSIGNED(11 downto 0);
clk, rst : in STD_LOGIC; T_out : out UNSIGNED(11 downto 0));
end;
architecture rtl of tconv is
signal T : UNSIGNED(7 downto 0);
constant T2 : UNSIGNED(1 downto 0) := "10" ;
constant T4 : UNSIGNED(2 downto 0) := "100" ;
constant T32 : UNSIGNED(5 downto 0) := "100000" ;
begin
process(T) begin T_out <= T + T/T2 + T/T4 + T32 after TPD;
end process;
end rtl;
T_in = temperature in
degC
T_out = temperature in
degF
The conversion formula
from Centigrade to
Fahrenheit is:
T(degF) = (9/5) x
T(degC) + 32
This converter uses the
approximation:
9/5 = 1.75 = 1 + 0.5 +
0.25
To save area the temperature conversion is approximate. Instead of multiplying by 9/5 and adding 32 (so 0 degC becomes 32 degF
and 100 degC becomes 212 degF) we multiply by 1.75 and add 32 (so 100 degC becomes 207 degF). Since 1.75 = 1 + 0.5 + 0.25,
we can multiply by 1.75 using shifts (for divide by 2, and divide by 4) together with a very simple constant addition (since 32 =
"100000"). Using shift to multiply and divide by powers of 2 is free in hardware (we just change connections to a bus). For large
temperatures the error approaches 0.05/1.8 or approximately 3 percent. We play these kinds of tricks often in hardware
computation. Notice also that temperatures measured in degC and degF are defined as unsigned integers of the same width. We
could have defined these as separate types to take advantage of VHDL's type checking.
Table 10.22 describes a digital filter to compute a "moving average" over four successive samples in time (i(0), i(1), i(2), and i(3),
with i(0) being the first sample).
TABLE 10.22 A digital filter.
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- STD_LOGIC type, rising_edge
use IEEE.NUMERIC_STD.all; -- UNSIGNED type, "+" and "/"
entity filter is
generic TPD : TIME := 1 ns;
port (T_in : in UNSIGNED(11 downto 0);
rst, clk : in STD_LOGIC;
T_out: out UNSIGNED(11 downto 0));
end;
architecture rtl of filter is
type arr is array (0 to 3) of UNSIGNED(11 downto 0);
signal i : arr ;
constant T4 : UNSIGNED(2 downto 0) := "100";
begin
process(rst, clk) begin
if (rst = '1') then
for n in 0 to 3 loop i(n) <= (others =>'0') after TPD;
end loop;
else
if(rising_edge(clk)) then
i(0) <= T_in after TPD;i(1) <= i(0) after TPD;
i(2) <= i(1) after TPD;i(3) <= i(2) after TPD;
end if;
end if;
end process;
process(i) begin
T_out <= ( i(0) + i(1) + i(2) + i(3) )/T4 after TPD;
end process;
The filter
computes
a moving
average
over four
successive
samples
in time.
Notice
i(0) i(1)
i(2) i(3)
are each
12 bits
wide.
Then the
sum
i(0) + i(1)
+ i(2) +
i(3)
is 14 bits
wide, and
end rtl;
the
average
( i(0) +
i(1) + i(2)
+ i(3)
)/T4
is 12 bits
wide.
All delays
are
generic
TPD .
The filter uses the following formula:
T_out <= ( i(0) + i(1) + i(2) + i(3) )/T4
Division by T4 = "100" is free in hardware. If instead, we performed the divisions before the additions, this would reduce the
number of bits to be added for two of the additions and saves us worrying about overflow. The drawback to this approach is
round-off errors. We can use the register shown in Table 10.23 to register the inputs.
TABLE 10.23 The input register.
12-bit-wide
register for the
temperature
input
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- type STD_LOGIC, rising_edge
signals.
use IEEE.NUMERIC_STD.all ; -- type UNSIGNED
entity register_in is
generic ( TPD : TIME := 1 ns);
If the input is
port (T_in : in UNSIGNED(11 downto 0);
asynchronous
clk, rst : in STD_LOGIC; T_out : out UNSIGNED(11 downto 0)); end;
(from an A/D
architecture rtl of register_in is
begin
converter with a
process(clk, rst) begin
separate clock,
if (rst = '1') then T_out <= (others => '0') after TPD;
for example),
else
if (rising_edge(clk)) then T_out <= T_in after TPD; end if; we would need
to worry about
end if;
metastability.
end process;
end rtl ;
All delays are
generic TPD .
Table 10.24 shows a first-in, first-out stack (FIFO). This allows us to buffer the signals coming from the sensor until the
microprocessor has a chance to read them. The depth of the FIFO will depend on the maximum amount of time that can pass
without the microcontroller being able to read from the bus. We have to determine this with statistical simulations taking into
account other traffic on the bus.
TABLE 10.24 A first-in, first-out stack (FIFO).
library IEEE; use IEEE.NUMERIC_STD.all ; -- UNSIGNED type
use ieee.std_logic_1164.all; -- STD_LOGIC type, rising_edge
entity fifo is
generic (width : INTEGER := 12; depth : INTEGER := 16);
port (clk, rst, push, pop : STD_LOGIC;
Di : in UNSIGNED (width-1 downto 0);
Do : out UNSIGNED (width-1 downto 0);
empty, full : out STD_LOGIC);
end fifo;
architecture rtl of fifo is
subtype ptype is INTEGER range 0 to (depth-1);
signal diff, Ai, Ao : ptype; signal f, e : STD_LOGIC;
type a is array (ptype) of UNSIGNED(width-1 downto 0);
signal mem : a ;
function bump(signal ptr : INTEGER range 0 to (depth-1))
return INTEGER is begin
if (ptr = (depth-1)) then return 0;
else return (ptr + 1);
end if;
end;
begin
process(f,e) begin full <= f ; empty <= e; end process;
process(diff) begin
if (diff = depth -1) then f <= '1'; else f <= '0'; end if;
if (diff = 0) then e <= '1'; else e <= '0'; end if;
end process;
process(clk, Ai, Ao, Di, mem, push, pop, e, f) begin
if(rising_edge(clk)) then
if(push='0')and(pop='1')and(e = '0') then Do <= mem(Ao); end if;
if(push='1')and(pop='0')and(f = '0') then mem(Ai) <= Di; end if;
end if ;
end process;
process(rst, clk) begin
if(rst = '1') then Ai <= 0; Ao <= 0; diff <= 0;
else if(rising_edge(clk)) then
if (push = '1') and (f = '0') and (pop = '0') then
Ai <= bump(Ai); diff <= diff + 1;
elsif (pop = '1') and (e = '0') and (push = '0') then
Ao <= bump(Ao); diff <= diff - 1;
end if;
end if;
end if;
end process;
end;
FIFO
(first-in,
first-out)
register
Reads (pop =
1) and writes
(push = 1)
are
synchronous
to the rising
edge of the
clock.
Read and
write should
not occur at
the same
time. The
width
(number of
bits in each
word) and
depth
(number of
words) are
generics.
External
signals:
clk , clock
rst , reset
active-high
push , write
to FIFO
pop , read
from FIFO
Di , data in
Do , data out
empty ,
FIFO flag
full , FIFO
flag
Internal
signals:
diff ,
difference
pointer
Ai , input
address
Ao , output
address
f , full flag
e , empty
flag
No delays in
this model.
The FIFO has flags, empty and full , that signify its state. It uses a function to increment two circular pointers. One pointer
keeps track of the address to write to next, the other pointer tracks the address to read from. The FIFO memory may be implemented
in a number of ways in hardware. We shall assume for the moment that it will be synthesized as a bank of flip-flops.
Table 10.25 shows a controller for the two FIFOs. The controller handles the reading and writing to the FIFO. The microcontroller
attached to the bus signals which of the FIFOs it wishes to read from. The controller then places the appropriate data on the bus. The
microcontroller can also ask for the FIFO flags to be placed in the low-order bits of the bus on a read cycle. If none of these actions
are requested by the microcontroller, the FIFO controller three-states its output drivers.
Table 10.25 shows the top level of the controller. To complete our model we shall use a package for the component declarations:
TABLE 10.25 A FIFO controller.
library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.NUMERIC_STD.all;
entity fifo_control is generic TPD : TIME := 1 ns;
port(D_1, D_2 : in UNSIGNED(11 downto 0);
sel : in UNSIGNED(1 downto 0) ;
read , f1, f2, e1, e2 : in STD_LOGIC;
r1, r2, w12 : out STD_LOGIC; D : out UNSIGNED(11 downto 0)) ;
end;
architecture rtl of fifo_control is
begin process
(read, sel, D_1, D_2, f1, f2, e1, e2)
begin
r1 <= '0' after TPD; r2 <= '0' after TPD;
if (read = '1') then
w12 <= '0' after TPD;
case sel is
when "01" => D <= D_1 after TPD; r1 <= '1' after TPD;
when "10" => D <= D_2 after TPD; r2 <= '1' after TPD;
when "00" => D(3) <= f1 after TPD; D(2) <= f2 after TPD;
D(1) <= e1 after TPD; D(0) <= e2 after TPD;
when others => D <= "ZZZZZZZZZZZZ" after TPD;
end case;
elsif (read = '0') then
D <= "ZZZZZZZZZZZZ" after TPD; w12 <= '1' after TPD;
else D <= "ZZZZZZZZZZZZ" after TPD;
end if;
end process;
end rtl;
This handles the
reading and writing
to the FIFOs under
control of the
processor (mpu).
The mpu can ask for
data from either
FIFO or for status
flags to be placed on
the bus.
Inputs:
D_1
data in from
FIFO1
D_2
data in from
FIFO2
sel
FIFO select from
mpu
read
FIFO read from
mpu
f1,f2,e1,e2
flags from FIFOs
Outputs:
r1, r2
read enables for
FIFOs
w12
write enable for
FIFOs
D
data out to mpu
bus
TABLE 10.26 Top level of temperature controller.
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
entity T_Control is port (T_in1, T_in2 : in UNSIGNED (11 downto 0);
sensor: in UNSIGNED(1 downto 0);
clk, RD, rst : in STD_LOGIC; D : out UNSIGNED(11 downto 0));
end;
architecture structure of T_Control is use work.TC_Components.all;
signal F, E : UNSIGNED (2 downto 1);
signal T_out1, T_out2, R_out1, R_out2, F1, F2, FIFO1, FIFO2 : UNSIGNED(11 downto 0);
signal RD1, RD2, WR: STD_LOGIC ;
begin
RG1 : register_in generic map (1ns) port map (T_in1,clk,rst,R_out1);
RG2 : register_in generic map (1ns) port map (T_in2,clk,rst,R_out2);
TC1 : tconv generic map (1ns) port map (R_out1, T_out1);
TC2 : tconv generic map (1ns) port map (R_out2, T_out2);
TF1 : filter generic map (1ns) port map (T_out1, rst, clk, F1);
TF2 : filter generic map (1ns) port map (T_out2, rst, clk, F2);
FI1 : fifo generic map (12,16) port map (clk, rst, WR, RD1, F1, FIFO1, E(1), F(1));
FI2 : fifo generic map (12,16) port map (clk, rst, WR, RD2, F2, FIFO2, E(2), F(2));
FC1 : fifo_control port map
(FIFO1, FIFO2, sensor, RD, F(1), F(2), E(1), E(2), RD1, RD2, WR, D);
end structure;
package TC_Components is
component register_in generic (TPD : TIME := 1 ns);
port (T_in : in UNSIGNED(11 downto 0);
clk, rst : in STD_LOGIC; T_out : out UNSIGNED(11 downto 0));
end component;
component tconv generic (TPD : TIME := 1 ns);
port (T_in : in UNSIGNED (7 downto 0);
clk, rst : in STD_LOGIC; T_out : out UNSIGNED(7 downto 0));
end component;
component filter generic (TPD : TIME := 1 ns);
port (T_in : in UNSIGNED (7 downto 0);
rst, clk : in STD_LOGIC; T_out : out UNSIGNED(7 downto 0));
end component;
component fifo generic (width:INTEGER := 12; depth : INTEGER := 16);
port (clk, rst, push, pop : STD_LOGIC;
Di : UNSIGNED (width-1 downto 0);
Do : out UNSIGNED (width-1 downto 0);
empty, full : out STD_LOGIC);
end component;
component fifo_control generic (TPD:TIME := 1 ns);
port (D_1, D_2 : in UNSIGNED(7 downto 0);
select : in UNSIGNED(1 downto 0); read, f1, f2, e1, e2 : in STD_LOGIC;
r1, r2, w12 : out STD_LOGIC; D : out UNSIGNED(7 downto 0)) ;
end component;
end;
The following testbench completes a set of reads and writes to the FIFOs:
library IEEE;
use IEEE.std_logic_1164.all; -- type STD_LOGIC
use IEEE.numeric_std.all; -- type UNSIGNED
entity test_TC is end;
architecture testbench of test_TC is
component T_Control port (T_1, T_2 : in UNSIGNED(11 downto 0);
clk : in STD_LOGIC; sensor: in UNSIGNED( 1 downto 0) ;
read : in STD_LOGIC; rst : in STD_LOGIC;
D : out UNSIGNED(7 downto 0)); end component;
signal T_1, T_2 : UNSIGNED(11 downto 0);
signal clk, read, rst : STD_LOGIC;
signal sensor : UNSIGNED(1 downto 0);
signal D : UNSIGNED(7 downto 0);
begin TT1 : T_Control port map (T_1, T_2, clk, sensor, read, rst, D);
process begin
rst <= '0'; clk <= '0';
wait for 5 ns; rst <= '1'; wait for 5 ns; rst <= '0';
T_in1 <= "000000000011"; T_in2 <= "000000000111"; read <= '0';
for i in 0 to 15 loop -- fill the FIFOs
clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns;
end loop;
assert (false) report "FIFOs full" severity NOTE;
clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns;
read <= '1'; sensor <= "01";
for i in 0 to 15 loop -- empty the FIFOs
clk <= '0'; wait for 5ns; clk <= '1'; wait for 5 ns;
end loop;
assert (false) report "FIFOs empty" severity NOTE;
clk <= '0'; wait for 5ns; clk <= '1'; wait;
end process;
end;
10.17 Summary
Table 10.27 shows the essential elements of the VHDL language. Table 10.28 shows the most
important BNF definitions and their locations in this chapter. The key points covered in this chapter
are as follows:
● The use of an entity and an architecture
● The use of a configuration to bind entities and their architectures
● The compile, elaboration, initialization, and simulation steps
● Types, subtypes, and their use in expressions
● The logic systems based on BIT and Std_Logic_1164 types
● The use of the IEEE synthesis packages for BIT arithmetic
● Ports and port modes
● Initial values and the difference between simulation and hardware
● The difference between a signal and a variable
● The different assignment statements and the timing of updates
● The process and wait statements
VHDL is a "wordy" language. The examples in this chapter are complete rather than code
fragments. To write VHDL "nicely," with indentation and nesting of constructs, requires a large
amount of space. Some of the VHDL code examples in this chapter are deliberately dense (with
reduced indentation and nesting), but the bold keywords help you to see the code structure. Most of
the time, of course, we do not have the luxury of bold fonts (or color) to highlight code. In this case,
you should add additional space, indentation, nesting, and comments.
TABLE 10.27
VHDL summary.
VHDL feature
Example
Book
93LRM
Comments
-- this is a comment
10.3
13.8
10.4
13.4
10.4
13.3
10.5
1.1-1.3
Literals
(fixed-value
items)
Identifiers
12 1.0E6 '1' "110" 'Z'
2#1111_1111#
"Hello world"
STRING'("110")
a_good_name Same same
(case-insensitive,
2_Bad bad_ _bad very__bad
start with letter)
Several basic
units of code
entity
Connections
made through
ports
port ( signal in i : BIT; out o : BIT);
10.7
4.3
Default
expression
port (i : BIT := '1');
-- i='1' if left open
10.7
4.3
architecture configuration
No built-in
logic-value
system.
BIT and
BIT_VECTOR
(STD).
Arrays
type BIT is ('0', '1'); -- predefined
10.8
signal myArray: BIT_VECTOR (7 downto 0);
14.2
myArray(1 downto 0) <= ('0', '1');
3.2.1
10.8
4.3.1.2
Two basic types a signal corresponds to a real wire
of logic signals a variable is a memory location in RAM
10.9
Types and
explicit
initial/default
value
signal ONE : BIT := '1' ;
10.9
4.3.2
Implicit
initial/default
value
BIT'LEFT = '0'
10.9
4.3.2
Predefined
attributes
clk'EVENT, clk'STABLE
10.9.4
14.1
10.10
8
4.3.1.3
Sequential
statements inside process begin
processes model wait until alarm = ring;
things that
eat; work; sleep;
happen one after
end process;
another and
repeat
Timing with
wait statement
wait for 1 ns; -- not wait 1 ns
10.10.1 8.1
wait on light until light = green;
Update to
signals occurs at signal <= 1; -- delta time delay
the end of a
signal <= variable1 after 2 ns;
simulation cycle
10.10.3 8.3
Update to
variables is
immediate
10.10.3 8.4
Processes and
concurrent
statements
model things
that happen at
the same time
variable := 1; -- immediate update
process begin rain ; end process ;
process begin sing ; end process ;
process begin dance; end process ;
10.13
9.2
STD_ULOGIC
IEEE
, STD_LOGIC
Std_Logic_1164 , STD_ULOGIC_VECTOR
, and STD_LOGIC_VECTOR
(defines logic
operators on
type STD_ULOGIC is
1164 types)
('U','X','0','1','Z','W','L','H','-');
IEEE
Numeric_Bit
and
Numeric_Std
10.6
--
10.12
--
UNSIGNED and SIGNED
X <= "10" * "01"
(defines
-- OK with numeric pkgs.
arithmetic
operators on BIT
and 1164 types)
TABLE 10.28 VHDL definitions.
Structure
Page BNF
Structure
Page BNF
alias declaration
418
10.21
next statement
429
10.32
architecture body
394
10.8
null statement
430
10.35
assertion statement
423
10.25
package declaration
398
10.11
attribute declaration
418
10.22
port interface declaration
406
10.13
block statement
438
10.37
port interface list
406
10.12
case statement
428
10.30
primary unit
393
10.5
component declaration
395
10.9
procedure call statement
427
10.28
component instantiation
444
10.42
process statement
440
10.38
concurrent statement
438
10.36
return statement
430
10.34
conditional signal assignment 442
10.40
secondary unit
393
10.6
configuration declaration
396
10.10
selected signal assignment
442
10.39
constant declaration
414
10.16
sequential statement
419
10.23
declaration
413
10.15
signal assignment statement
424
10.27
design file
393
10.4
signal declaration
414
10.17
entity declaration
394
10.7
special character
391
10.2
exit statement
430
10.33
subprogram body
416
10.20
generate statement
444
10.43
subprogram declaration
415
10.19
graphic character
391
10.1
type declaration
411
10.14
identifier
392
10.3
variable assignment statement 424
10.26
if statement
427
10.29
variable declaration
415
10.18
loop statement
429
10.31
wait statement
421
10.24
Appendix A contains more detailed definitions and technical reference material.
10.18 Problems
* = Difficult ** = Very difficult *** = Extremely difficult
10.1 (Hello World, 10 min.) Set up a new, empty, directory (use mkdir VHDL , for example) to run your VHDL simulator
(the exact details will depend on your computer and simulator). Copy the code below to a file called hw_1.vhd in your
VHDL directory (leave out comments to save typing). Hint: Use the vi editor ( i inserts text, x deletes text, dd deletes a
line, ESC :w writes the file, ESC :q quits) or use cat > hw_1.vhd and type in the code (use CTRL-D to end typing) on
a UNIX machine. Remember to save in 'Text Only' mode (Frame or MS Word) on an IBM PC or Apple Macintosh.
Analyze, elaborate, and simulate your model (include the output in your answer). Comment on how easy or hard it was to
follow the instructions to use the software and suggest improvements.
entity HW_1 is end; architecture Behave of HW_1 is
constant M : STRING := "hello, world"; signal Ch : CHARACTER := ' ';
begin process begin
for i in M'RANGE loop Ch <= M(i); wait for 1 ns; end loop; wait;
end process; end;
10.2 (Running a VHDL simulation, 20 min.) Copy the example from Section 10.1 into a file called Counter1.vhd in your
VHDL directory (leave out the comments to save typing). Complete the compile (analyze), elaborate (build), and execute
(initialize and simulate) or other equivalent steps for your simulator. After each step list the contents of your directory VHDL
and any subdirectories and files that are created (use ls -alR on a UNIX system).
10.3 (Simulator commands, 10 min.) Make a "cheat sheet" for your simulator, listing the commands that can be used to control
simulation.
10.4 (BNF addresses, 10 min.) Create a BNF description of a name including: optional title (Prof., Dr., Mrs., Mr., Miss, or
Ms.), optional first name and middle initials (allow up to two), and last name (including unusual hyphenated and foreign
names, such as Miss A-S. de La Salle, and Prof. John T. P. McTavish-f Fiennes). The lowest level constructs are
letter ::= a-Z , '.' (period) and '-' (hyphen). Add BNF productions for a postal address in the form: company name,
mail stop, street address, address lines (1 to 4), and country.
10.5 (BNF e-mail, 10 min.) Create a BNF description of a valid internet e-mail address in terms of letters, '@' , '.' , 'gov'
, 'com ', 'org ', and 'edu' . Create a state diagram that "parses" an e-mail address for validity.
10.6 (BNF equivalence) Are the following BNF productions exactly equivalent? If they are not, produce a counterexample that
shows a difference.
term ::= factor { multiplying_operator factor }
term ::= factor | term multiplying_operator factor
10.7 (Environment, 20 min.) Write a simple VHDL model to check and demonstrate that you can get to the IEEE library and
have the environment variables, library statements, and such correctly set up for your simulator.
10.8 (Work, 20 min.) Write simple VHDL models to demonstrate that you can retrieve and use previously analyzed design
units from the library work and that you can also remove design units from work . Explain how your models prove that
access to work is functioning correctly.
10.9 (Packages, 60 min.) Write a simple package (use filename PackH.vhd ) and package body (filename PackB.vhd ).
Demonstrate that you can store your package (call it MyPackage ) in the library work . Then store, move, or rename (the
details will depend on your software) your package to a library called MyLibrary in a directory called MyDir , and use its
contents with a library clause ( library MyLibrary ) and a use clause ( use MyLibrary.MyPackage.all ) in a
testbench called PackTest (filename PackT.vhd ) in another directory MyWork . You may or may not be amazed at how
complicated this can be and how poorly most software companies document this process.
10.10 (***IEEE Std 1164, 60 min.) Prior to VHDL-93 the xnor function was not available, and therefore older versions of
the std_logic_1164 library did not provide the xnor function for STD_LOGIC types either (it was actually included but
commented out). Write a simple model that checks to see if you have the newer version of std_logic_1164 . Can you do
this without crashing the simulator?
You are an engineer on a very large project and find that your design fails to compile because your design must use the xnor
function and the library setup on your company's system still points to the old IEEE std_logic_1164 library, even though
the new library was installed. You are apparently the first person to realize the problem. Your company has a policy that any
time a library is changed all design units that use that library must be rebuilt from source. This might require days or weeks of
work. Explain in detail, using code, the alternative solutions. What will you recommend to your manager?
10.11 (**VHDL-93 test, 20 min.) Write a simple test to check if your simulator is a VHDL-87 or VHDL-93
environment--without crashing the simulator.
10.12 (Declarations, 10 min.) Analyze the following changes to the code in Section 10.8 and include the simulator output in
your answers:
Uncomment the declarations for Bad100 and Bad4 in Declaration _1 .
Add the following to Constant_2:
signal wacky : wackytype (31 downto 0); -- wacky
Remove the library and use clause in Constant_2.
10.13 ( STRING type, 10 min.) Replace the write statement that prints the string " count=" in Text(Behave) in
Section 10.6.3 with the following, compile it, and explain the result:
write(L, " count=" ); -- No type qualification.
10.14 (Sequential statements, 10 min.) Uncomment the following line in Wait_1(Behave) in Section 10.10, analyze the code,
and explain the result:
wait on x(1 to v); -- v is a variable.
10.15 (VHDL logical operators, 10 min.)
Explain the problem with the following VHDL statement:
Z <= A nand B nand C;
Explain why this problem does not occur with this statement:
Z <= A and B and C;
What can you say about the logical operators: and , or , nand , nor , xnor , xor ?
Is the following code legal?
Z <= A and B or C;
10.16 (*Initialization, 45 min.) Consider the following code:
entity DFF_Plain is port (Clk, D : in BIT; Q : out BIT); end;
architecture Bad of DFF_Plain is begin process (Clk) begin
if Clk = '0' and Clk'EVENT then Q <= D after 1 ns; end if;
end process; end;
Analyze and simulate this model using a testbench.
Rewrite architecture Bad using an equivalent process including a wait statement. Simulate this equivalent model and
confirm the behaviors are identical.
What is the behavior of the output Q during initial execution of the process?
Why does this happen?
Why does this not happen with the following code:
architecture Good of DFF_Plain is
begin process begin wait until Clk = '0'; Q <= D after 1 ns;
end process; end;
10.17 (Initial and default values, 20 min.) Use code examples to explain the difference between: default expression, default
value, implicit default value, initial value, initial value expression, and default initial value.
10.18 (Enumeration types, 20 min.) Explain the analysis results for the following:
type MVL4 is ('X', '0', '1', 'Z'); signal test : MVL4;
process begin
test <= 1; test <= Z; test <= z; test <= '1'; test <= 'Z';
end process;
Alter the type declaration to the following, analyze your code again, and comment:
type Mixed4 is (X , '0', '1', Z);
10.19 (Type declarations, 10 min.) Correct these declarations:
type BadArray is array (0 to 7) of BIT_VECTOR;
type Byte is array (NATURAL range 7 downto 0) of BIT;
subtype BadNibble is Byte(3 downto 0);
type BadByte is array (range 7 downto 0) of BIT;
10.20 (Procedure parameters, 10 min.) Analyze the following package; explain and correct the error. Finally, build a testbench
to check your solution.
package And_Pkg_Bad is procedure V_And(a, b : BIT; c: out BIT); end;
package body And_Pkg_Bad is
procedure V_And(a,b : BIT;c : out BIT) is begin c <= a and b;end;
end And_Pkg_Bad;
10.21 (Type checking, 20 min.) Test the following code and explain the results:
type T is INTEGER range 0 to 32; variable a: T;
a := (16 + 17) - 12; a := 16 - 12 + 17; a := 16 + (17 - 12);
10.22 (Debugging VHDL code, 30 min.) Find and correct the errors in the following code. Create a testbench for your code to
check that it works correctly.
entity UpDownCount_Bad is
port(clock, reset, up: STD_LOGIC; D: STD_LOGIC_VECTOR (7 to 0));
end UpDownCount_Bad;
architecture Behave of UpDownCount_Bad is
begin process (clock, reset, up); begin
if (reset = '0') then D <= '0000000';
elseif (rising_edge(clock)) then
if (up = 1) D <= D+1; else D <= D-1; end if;
end if; end process; end Behave;
10.23 (Subprograms, 20 min.) Write and test subprograms for these declarations:
function Is_X_Zero (signal X : in BIT) return BIT;
procedure Is_A_Eq_B (signal A, B : BIT; signal Y : out BIT);
10.24 (Simulator error messages, 10 min.) Analyze and attempt to simulate Arithmetic_2(Behave) from Section 10.12 and
compare the error message you receive with that from the MTI simulator (not all simulators are as informative). There are no
standards for error messages.
10.25 (Exhaustive property of case statement, 30 min.) Write and simulate a testbench for the state machine of Table 10.8 and
include your results. Is every state transition tested by your program and is every transition covered by an assignment
statement in the code? (Hint: Think very carefully.) Repeat this exercise for the state machine in Section 10.10.6.
10.26 (Default values for inputs, 20 min.) Replace the interface declaration for entity Half_Adder in Section 10.5 with the
following (to remove the default values):
port (X, Y: in BIT ; Sum, Cout: out BIT);
Attempt to compile, elaborate, and simulate configuration Simplest (the other entities needed, AndGate and XorGate , must
already be in work or in the same file). You should get an error at some stage (different systems find this error at different
points--just because an entity compiles, that does not mean it is error-free).
The LRM says "... A port of mode in may be unconnected ...only if its declaration includes a default expression..." [VHDL
93LRM1.1.1.2].
We face a dilemma here. If we do not drive inputs with test signals and leave an input port unconnected, we can compile the
model (since it is syntactically correct) but the model is not semantically correct. On the other hand, if we give the inputs
default values, we might accidentally forget to make a connection and not notice.
10.27 (Adder generation, 10 min.) Draw the schematic for Adder_1(Structure) of Section 10.13.7, labeling each instance with
the VHDL instance name.
10.28 (Generate statement, 20 min.) Draw a schematic corresponding to the following code (label the cells with their instance
names):
B1: block begin L1 : C port map (T, B, A(0), B(0)) ;
L2: for i in 1 to 3 generate L3 : for j in 1 to 3 generate
L4: if i+j > 4 generate L5: C port map (A(i-1), B(j-1), A(i), B(j)) ;
end generate; end generate; end generate;
L6: for i in 1 to 3 generate L7: for j in 1 to 3 generate
L8: if i+j < 4 generate L9: C port map (A(i+1), B(j+1), A(i), B(j)) ;
end generate; end generate; end generate;
end block B1;
Rewrite the code without generate statements. How would you prove that your code really is exactly equivalent to the
original?
10.29 (Case statement, 20 min.) Create a package ( my_equal ) that overloads the equality operator so that 'X' = '0'
and 'X' = '1' are both TRUE . Test your package. Simulate the following design unit and explain the result.
entity Case_1 is end; architecture Behave of Case_1 is
signal r : BIT; use work.my_equal.all;
begin process variable twobit:STD_LOGIC_VECTOR(1 to 2); begin
twobit := "X0";
case twobit is
when "10" => r <= '1';
when "00" => r <= '1';
when others => r <= '0';
end case; wait;
end process; end;
10.30 (State machine) Create a testbench for the state machine of Section 10.2.5.
10.31 (Mealy state machine, 60 min.) Rewrite the state machine of Section 10.2.5 as a Mealy state machine (the outputs
depend on the inputs and on the current state).
10.32 (Gate-level D flip-flop, 30 min.) Draw the schematic for the following D flip-flop model. Create a testbench (check for
correct operation with combinations of Clear , Preset , Clock , and Data ). Have you covered all possible modes of
operation? Justify your answer of yes or no.
architecture RTL of DFF_To_Test is
signal A, B, C, D, QI, QBarI : BIT; begin
A <= not (Preset and D and B) after 1 ns;
B <= not (A and Clear and Clock) after 1 ns;
C <= not (B and Clock and D) after 1 ns;
D <= not (C and Clear and Data) after 1 ns;
QI <= not (Preset and B and QBarI) after 1 ns;
QBarI <= not (QI and Clear and C) after 1 ns;
Q <= QI; QBar <= QBarI;
end;
10.33 (Flip-flop model, 20 min.) Add an asynchronous active-low preset to the D flip-flop model of Table 10.3. Generate a
testbench that includes interaction of the preset and clear inputs. What issue do you face and how did you solve it?
10.34 (Register, 45 min.) Design a testbench for the register of Table 10.4. Adapt the 8-bit register design to a 4-bit version
with the following interface declaration:
entity Reg4 is port (D : in STD_LOGIC_VECTOR(7 downto 0);
Clk,Pre,Clr : in STD_LOGIC;Q,QB : out STD_LOGIC_VECTOR(7 downto 0));
end Reg8;
Create a testbench for your 4-bit register with the following component declaration:
component DFF
port(Preset,Clear,Clock,Data:STD_LOGIC;Q,QBar:out STD_LOGIC_VECTOR);
end component;
10.35 (*Conversion functions, 30 min.) Write a conversion function from
NATURAL to STD_LOGIC_VECTOR using the following declaration:
function Convert (N, L: NATURAL) return STD_LOGIC_VECTOR;
-- N is NATURAL, L is length of STD_LOGIC_VECTOR
Write a similar conversion function from STD_LOGIC_VECTOR to NATURAL:
function Convert (B: STD_LOGIC_VECTOR) return NATURAL;
Create a testbench to test your functions by including them in a package.
10.36 (Clock procedure, 20 min.) Design a clock procedure for a two-phase clock (C1, C2) with variable high times ( HT1 ,
HT2 ) and low times ( LT1 , LT2 ) and the following interface. Include your procedure in a package and write a model to test
it.
procedure Clock (C1, C2 : out STD_LOGIC; HT1, HT2, LT1, LT2 : TIME);
10.37 (Random number, 20 min.) Design a testbench for the following procedure:
procedure uniform (seed : inout INTEGER range 0 to 15) is
variable x : INTEGER;
begin x := (seed*11) + 7; seed := x mod 16;
end uniform;
10.38 (Full-adder, 30 min.) Design and test a behavioral model of a full adder with the following interface:
entity FA is port (X, Y, Cin : STD_LOGIC; Cout, Sum : out STD_LOGIC);
end;
Repeat the exercise for inputs and outputs of type UNSIGNED .
10.39 (8-bit adder testbench, 60 min.) Write out the code corresponding to the generate statements of Adder_1 ( Structure
) in Section 10.13.7. Write a testbench to check your adder. What problems do you encounter? How thorough do you believe
your tests are?
10.40 (Shift-register testbench, 60 min.) Design a testbench for the shift register of Table 10.4. Convert this model to use
STD_LOGIC types with the following interface:
entity ShiftN is
port (CLK, CLR, LD, SH, DIR : STD_LOGIC;
D : STD_LOGIC_VECTOR; Q : out STD_LOGIC_VECTOR);
end;
10.41 (Multiplier, 60 min.) Design and test a multiplier with the following interface:
entity Mult8 is
port (A, B : STD_LOGIC_VECTOR(3 downto 0);
Start, CLK, Reset : in STD_LOGIC;
Result : out STD_LOGIC_VECTOR(7 downto 0); Done : out BIT);
end;
Create testbench code to check your model.
Catalog each compile step with the syntax errors as you debug your code.
Include a listing of the first code you write together with the final version.
An interesting class project is to collect statistics from other students working on this problem and create a table showing the
types and frequency of syntax errors made with each compile step, and the number of compile steps required. Does this
information suggest ways that you could improve the compiler, or suggest a new type of tool to use when writing VHDL?
10.42 (Port maps, 5 min.) What is wrong with this VHDL statement?
U1 : nand2 port map (a <= set, b <= qb, c <= q);
10.43 (DRIVING_VALUE, 15 min.) Use the VHDL-93 attribute Clock'DRIVING_VALUE to rewrite the following clock
generator model without using a temporary variable.
entity ClockGen_2 is port (Clock : out BIT); end;
architecture Behave of ClockGen_2 is
begin process variable Temp : BIT := '1'; begin
Temp := not Temp ; Clock <= Temp after 10 ns; wait for 10 ns;
if (now > 100 ns) then wait; end if; end process;
end;
10.44 (Records, 15 min.) Write an architecture (based on the following skeleton) that uses the record structure shown:
entity Test_Record_1 is end; architecture Behave of Test_Record_1 is
begin process type Coordinate is record X, Y : INTEGER; end record;
-- a record declaration for an attribute declaration:
attribute Location:Coordinate; -- an attribute declaration
begin wait; end process; end Behave;
10.45 (**Communication between processes, 30 min.) Explain and correct the problem with the following skeleton code:
variable v1 : INTEGER := 1; process begin v1 := v1+3; wait; end process;
process variable v2 : INTEGER := 2; begin v2 := v1 ; wait; end process;
10.46 (*Resolution, 30 min.) Explain and correct the problems with the following:
entity R_Bad_1 is port (i : in BIT; o out BIT); end;
architecture Behave of R_Bad_1 is
begin o <= not i after 1 ns; o <= i after 2 ns; end;
10.47 (*Inputs, 30 min.) Analyze the following and explain the result:
entity And2 is port (A1, A2: in BIT; ZN: out BIT); end;
architecture Simple of And2 is begin ZN <= A1 and A2; end;
entity Input_Bad_1 is end; architecture Netlist of Input_Bad_1 is
component And2 port (A1, A2 : in BIT; ZN : out BIT); end component;
signal X, Z : BIT begin G1 : And2 port map (X, X, Z); end;
10.48 (Association, 15 min.) Analyze the following and explain the problem:
entity And2 is port (A1, A2 : in BIT; ZN : out BIT); end;
architecture Simple of And2 is begin ZN <= A1 and A2; end;
entity Assoc_Bad_1 is port (signal X, Y : in BIT; Z : out BIT); end;
architecture Netlist of Assoc_Bad_1 is
component And2 port (A1, A2 : in BIT; ZN : out BIT); end component;
begin
G1: And2 port map (X, Y, Z);
G2: And2 port map (A2 => Y, ZN => Z, A1 => X);
G3: And2 port map (X, ZN => Z, A2 => Y);
end;
10.49 (Modes, 30 min.) Analyze and explain the errors in the following:
entity And2 is port (A1, A2 : in BIT; ZN : out BIT); end;
architecture Simple of And2 is begin ZN <= A1 and A2; end;
entity Mode_Bad_1 is port (X : in BIT; Y : out BIT; Z : inout BIT); end;
architecture Netlist of Mode_Bad_1 is
component And2 port (A1, A2 : in BIT; ZN : out BIT); end component;
begin G1 : And2 port map (X, Y, Z); end;
entity Mode_Bad_2 is port (X : in BIT; Y : out BIT; Z : inout BIT); end;
architecture Netlist of Mode_Bad_1 is
component And2 port (A1, A2 : in BIT; ZN : inout BIT); end component;
begin G1 : And2 port map (X, Y, Z); end;
10.50 (*Mode association, 60 min.) Analyze and explain the errors in the following code. The number of errors, types of error,
and the information in the error messages given by different simulators vary tremendously in this area.
entity Allmode is port
(I : in BIT; O : out BIT; IO : inout BIT; B : buffer BIT);
end;
architecture Simple of Allmode is begin O<=I; IO<=I; B<=I; end;
entity Mode_1 is port
(I : in BIT; O : out BIT; IO : inout BIT; B : buffer BIT);
end;
architecture Netlist of Mode_1 is
component Allmode port
(I : in BIT; O : out BIT; IO : inout BIT; B : buffer BIT); end component;
begin
G1:Allmode port map (I , O , IO, B );
G2:Allmode port map (O , IO, B , I );
G3:Allmode port map (IO, B , I , O );
G4:Allmode port map (B , I , O , IO);
end;
10.51 (**Declarations, 60 min.) Write a tutorial (approximately two pages of text, five pages with code) with examples
explaining the difference between: a component declaration, a component configuration, a configuration declaration, a
configuration specification, and a block configuration.
10.52 (**Guards and guarded signals, 60 min.) Write some simple models to illustrate the use of guards, guarded signals, and
the disconnect statement. Include an experiment that shows and explains the use of the implicit signal GUARD in assignment
statements.
10.53 (** Std_logic_1164 , 120 min.) Write a short (two pages of text) tutorial, with (tested) code examples, explaining
the std_logic_1164 types, their default values, the difference between the 'ulogic' and 'logic' types, and their
vector forms. Include an example that shows and explains the problem of connecting a std_logic_vector to a
std_ulogic_vector.
10.54 (Data swap, 20 min.) Consider the following code:
library ieee; use ieee.std_logic_1164.all;
package config is
type type1 is record
f1 : std_logic_vector(31 downto 0); f2 : std_logic_vector(3 downto 0);
end record;
type type2 is record
f1 : std_logic_vector(31 downto 0); f2 : std_logic_vector(3 downto 0);
end record;
end config;
library ieee; use ieee.STD_LOGIC_1164.all; use work.config.all;
entity Swap_1 is
port (Data1 : type1; Data2 : type2; sel : STD_LOGIC;
Data1Swap : out type1; Data2Swap : out type2); end Swap_1;
architecture Behave of Swap_1 is begin
Swap: process (Data1, Data2, sel) begin case sel is
when '0' => Data1Swap <= Data1; Data2Swap <= Data2;
when others => Data1Swap <= Data2; Data2Swap <= Data1;
end case; end process Swap; end Behave;
Compile this code. What is the problem? Suggest a fix. Now write a testbench and test your code. Have you considered all
possibilities?
10.55 (***RTL, 30 min.) "RTL stands for register-transfer level. ...when referencing VHDL, the term means that the
description includes only concurrent signal assignment statements and possibly block statements. In particular, VHDL data
flow descriptions explicitly do not contain either process statements (which describe behavior) or component instantiation
statements (which describe structure)" (Dr. VHDL from VHDL International).
With your knowledge of process statements and components, comment on Dr. VHDL's explanation.
In less than 100 words offer your own definition of the difference between RTL, data flow, behavioral, and structural models.
10.56 (*Operators mod and rem , 20 min.) Confirm and explain the following:
i1 := (-12)
rem
7;
-- i1 = -5
i2
-- i2 = 5
i3
-- i3 = -5
i4
-- i4 = 5
i5
-- i5 = 2
i6
-- i6 = -2
i7
-- i7 = -5
:= 12
rem
(-7);
:= (12)
rem
(-7);
:= 12
mod
7;
:= (-12)
mod
7;
:= 12
mod
(-7);
:= (12)
mod
(-7);
Evaluate -5 rem 2 and explain the result.
10.57 (***Event and stable, 60 min.) Investigate the differences between clk'EVENT and clk'STABLE . Write a
minitutorial (in the form of a "cheat sheet") with examples showing the differences and potential dangers of using
clk'STABLE .
10.58 (PREP benchmark #2, 60 min.) The following code models a benchmark circuit used by PREP to measure the capacity
of FPGAs. Rewrite the concurrent signal assignment statements (labeled mux and comparator) as equivalent processes. Draw a
datapath schematic corresponding to PREP2(Behave_1). Write a testbench for the model. Finally (for extra credit) rewrite the
model and testbench to use STD_LOGIC instead of BIT types.
library ieee; use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_BIT.all; use ieee.NUMERIC_STD.all;
entity PREP2 is
port(CLK,Reset,Sel,Ldli,Ldhi : BIT; D1,D2 : STD_LOGIC_VECTOR(7 downto 0);
DQ:out STD_LOGIC_VECTOR(7 downto 0));
end;
architecture Behave_1 of PREP2 is
signal EQ : BIT; signal y,lo,hi,Q_i : STD_LOGIC_VECTOR(7 downto 0);
begin
outputDriver: Q <= Q_i;
mux: with Sel select y <= hi when '0', D1 when '1';
comparator: EQ <= '1' when Q_i = lo else '0';
register: process(Reset, CLK) begin
if Reset = '1' then hi <= "00000000"; lo <= "00000000";
elsif CLK = '1' and CLK'EVENT then
if Ldhi='1' then hi<=D2;end if;if Ldlo='1' then lo<=D2;end
if;
end if;
end process register;
counter: process(Reset, CLK) begin
if Reset = '1' then Q_i <= "00000000";
elsif CLK = '1' and CLK'EVENT then
if EQ = '1' then Q_i <= y;
elsif EQ = '0' then Q_i <= Q_i + "00000001";
end if;
end if;
end process counter;
end;
10.59 (PREP #3, state machine) Draw the state diagram for the following PREP benchmark (see Problem 10.58). Is this a
Mealy or Moore machine? Write a testbench and test this code.
library ieee; use ieee.STD_LOGIC_1164.all;
entity prep3_1 is port(Clk, Reset: STD_LOGIC;
I : STD_LOGIC_VECTOR(7 downto 0); O : out STD_LOGIC_VECTOR(7 downto 0));
end prep3_1;
architecture Behave of prep3_1 is
type STATE_TYPE is (sX,s0,sa,sb,sc,sd,se,sf,sg);
signal state : STATE_TYPE; signal Oi : STD_LOGIC_VECTOR(7 downto 0);
begin
O <= Oi;
process (Reset, Clk) begin
if (Reset = '1') then state <= s0; Oi <= (others => '0');
elsif rising_edge(Clk) then
case state is
when s0 =>
if (I = X"3c") then state <= sa; Oi <= X"82";
else state <= s0; Oi <= (others => '0');
end if;
when sa =>
if (I = X"2A") then state <= sc; Oi <= X"40";
elsif (I = X"1F") then state <= sb; Oi <=
X"20";
when
when
when
when
when
when
when
end case;
else state <= sa; Oi <= X"04";
end if;
sb =>
if (I = X"AA") then state <= se; Oi <= X"11";
else state <= sf; Oi <= X"30";
end if;
sc => state <= sd; Oi <= X"08";
sd => state <= sg; Oi <= X"80";
se => state <= s0; Oi <= X"40";
sf => state <= sg; Oi <= X"02";
sg => state <= s0; Oi <= X"01";
others => state <= sX; Oi <= (others => 'X');
end if;
end process;
end;
10.60 (Edge detection, 30 min) Explain the construction of the IEEE 1164 function to detect the rising edge of a signal,
rising_edge(s) . List all the changes in signal s that correspond to a rising edge.
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin return
(s'EVENT and (To_X01(s) = '1') and (To_X01(s'LAST_VALUE) = '0')); end;
10.61 (*Real, 10 min.) Determine the smallest real in your VHDL environment.
10.62 (*Stop, 30 min.) How many ways are there to stop a VHDL simulator?
10.63 (*Arithmetic package, 60 min.) Write a function for an arithmetic package to subtract two's complement numbers.
Create a test bench to check your function. Your declarations in the package header should look like this:
type TC is array (INTEGER range <>) of STD_LOGIC;
function "-"(L : TC; R : TC) return TC;
10.64 (***Reading documentation, hours) There are a few gray areas in the interpretation of the VHDL-87 LRM some of
which were clarified in the VHDL-93 revision. One VHDL system has a "compatibility mode" that allows alternative
interpretations. For each of the following "issues" taken from the actual tool documentation try to interpret what was meant,
determine the interpretation taken by your own software, and then rewrite the explanation clearly using examples.
* "Unassociated variable and signal parameters. Compatibility mode allows variable and signal parameters to subprograms to
be unassociated if they have a default value. Otherwise, an error is generated."
Example answer: Consider the following code:
package Util_2 is
procedure C(signal Clk : out BIT; signal P : TIME := 10 ns);
end Util_2;
package body Util_2 is
procedure C(signal Clk : out BIT; signal P : TIME := 10 ns) is
begin loop Clk <= '1' after P/2, '0' after P;
wait for P; end loop; end; end Util_2;
entity Test_Compatibility_1 is end; use work.Util_2.all;
architecture Behave of Test_Compatibility_1 is
signal v,w,x,y,z : BIT; signal s : TIME := 5 ns;
begin process variable v : TIME := 5 ns; begin
C(v, s);
since P is declared as signal
-- C(w, v);
is declared as variable instead
-- C(x, 5 ns);
is declared as constant instead
-- C(y);
error if P is signal or variable
-- C(z,open);
P is signal or variable
end process; end;
-- parameter s is OK
-- would be OK if P
-- would be OK if P
-- unassociated, an
-- open, an error if
The Compass Scout simulator (which does not have a compatibility mode) generates an error during analysis if a signal or
variable subprogram parameter is open or unassociated (a constant subprogram parameter may be unassociated or open).
* "Allow others in an aggregate within a record aggregate. The LRM [7.3.2.2] defines nine situations where others may
appear in an aggregate. In compatibility mode, a tenth case is added. In this case, others is allowed in an aggregate that
appears as an element association in a record element."
* " BIT'('1') parsed as BIT ' ('1') . The tick ( ' ) character is being used twice in this example. In the first case as
an attribute indicator, in the second case, to form a character literal. Without the compatibility option, the analyzer adopts a
strict interpretation of the LRM, and without white space around the first tick, the fragment is parsed as BIT '('1') , that
is, the left parenthesis ( '(' ) is the character literal."
** "Generate statement declarative region. Generate statements form their own declarative region. In compatibility mode,
configuration specifications will apply to items being instantiated within a generate statement."
** "Allow type conversion functions on open parameters. If a parameter is specified as open, it indicates a parameter without
an explicit association. In such cases, the presence of a type conversion function is meaningless. Compatibility mode allows
the type conversion functions."
*** "Entity class flexibility. Section [3.1.2] of the LRM defines the process of creating a new integer type. The type name
given is actually assigned to a subtype name, related to an anonymous base type. This implies that the entity class used during
an attribute specification [LRM 5.1] should indicate subtype, rather than type. Because the supplied declaration was type rather
than subtype, compatibility mode allows type."
*** "Allowing declarations beyond an all/others specification. Section [5.1] of the LRM states that the first occurrence of the
reserved word all or others in an attribute specification terminates the declaration of the related entity class. The LRM
declares that the entity/architecture and package/package body library units form single declaration regions [LRM 10.1] that
are the concatenation of the two individual library declarative regions. For example, if a signal attribute specification with all
or others was specified in the entity, it would be impossible to declare a signal in the architecture. In compatibility mode,
this LRM limitation is removed."
*** "User-defined attributes on overloaded functions. In compatibility mode, user-defined attributes are allowed to be
associated with overloaded functions. Note: Even in compatibility mode, there is no way to retrieve the different attributes."
10.65 (*1076 interpretations, 30 min.) In a DAC paper, the author writes: `It was experienced that (company R) might have
interpreted IEEE 1076 differently than (company S) did, e.g. concatenations (&) are not allowed in "case selector" expressions
for (company S).' Can you use concatenation in your VHDL tool for either the expression or choices for a case
statement?
10.66 (**Interface declarations, 15 min.) Analyze the following and comment:
entity Interface_1 is
generic (I : INTEGER; J : INTEGER := I; K, L : INTEGER);
port (A : BIT_VECTOR; B : BIT_VECTOR(A'RANGE); C : BIT_VECTOR (K to L));
procedure X(P, Q : INTEGER; R : INTEGER range P to Q);
procedure Y(S : INTEGER range K to L);
end Interface_1;
10.67 (**Wait statement, 10 min.) Construct the sensitivity set and thus the sensitivity list for the following wait statement
(that is, rewrite the wait statement in the form wait on sensitivity_list until condition ).
entity Complex_Wait is end;
architecture Behave of Complex_Wait is
type A is array (1 to 5) of BOOLEAN;
function F (P : BOOLEAN) return BOOLEAN;
signal S : A; signal i, j : INTEGER range 1 to 5;
begin process begin
wait until F(S(3)) and (S(i) or S(j));
end process;
end;
10.68 (**Shared variables, 20 min.) Investigate the following code and comment:
architecture Behave of Shared_1 is
subtype S is INTEGER range 0 to 1; shared variable C : S := 0; begin
process begin C := C + 1; wait; end process;
process begin C := C - 1; wait; end process;
end;
10.69 (Undocumented code and ranges, 20 min.) Explain the purpose of the following function (part of a package from a
well-known synthesis company) with a parameter of type SIGNED. Write a testbench to check your explanation. Investigate
what happens when you call this function with a string-literal argument, for example with the statement X <= IM("11100").
What is the problem and why does it happen? Rewrite the code, including documentation, to avoid this problem.
type SIGNED is array (NATURAL range <> ) of BIT;
function IM (L : SIGNED) return INTEGER is variable M : INTEGER;
begin M := L'RIGHT-1;
for i in L'LEFT-1 downto L'RIGHT loop
if (L(i) = (not L(L'LEFT))) then M := i; exit; end if;
end loop; return M;
end;
10.70 (Timing parameters, 20 min.) Write a model and a testbench for a two-input AND gate with separate rising (tpLH) and
falling (tpHL) delays using the following interface:
entity And_Process is
generic (tpLH, tpHL : TIME); port (a, b : BIT; z : out BIT) end;
10.71 (Passive code in entities, 30 min.) Write a procedure (CheckTiming, part of a package Timing_Pkg ) to check that two
timing parameters (tPLH and tPHL) are both greater than zero. Include this procedure in a two-input AND gate model (
And_Process ). Write a testbench to show your procedure and gate model both work. Rewrite the entity for
And_Process to include the timing check as part of the entity declaration. You are allowed to include passive code (no
assignments to signals and so on) directly in each entity. This avoids having to include the timing checks in each architecture.
10.72 (Buried code, 30 min.) Some companies bury instructions to the software within their packages. Here is an example of
part of the arithmetic package from an imaginary company called SissyN:
function UN_plus(A, B : UN) return UN is
variable CRY : STD_ULOGIC; variable X,SUM : UN (A'LEFT downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UN_ARG
-- pragma return_port_name Z
begin
-- sissyn synthesis_off
if (A(A'LEFT) = 'X' or B(B'LEFT) = 'X') then SUM := (others => 'X');
return(SUM);
end if;
-- sissyn synthesis_on
CRY := '0'; X := B;
for i in 0 to A'LEFT loop
SUM(i) := A(i) xor X(i) xor carry;
CRY := (A(i) and X(i)) or (A(i) and CRY) or (CRY and X(i));
end loop; return SUM;
end;
Explain what this function does. Can you now hazard a guess at what each of the comments means? What are the
repercussions of using comments in this fashion?
10.73 (*Deferred constants, 15 min.) "If the assignment symbol ':=' followed by an expression is not present in a constant
declaration, then the declaration declares a deferred constant. Such a constant declaration may only appear in a package
declaration. The corresponding full constant declaration, which defines the value of the constant, must appear in the body of
the package" [VHDL 93LRM4.3.1.1].
package Constant is constant s1, s2 : BIT_VECTOR; end Constant;
package body Constant is
constant s0 : BIT_VECTOR := "00"; constant s1 : BIT_VECTOR := "01";
end Constant;
It is tempting to use deferred constants to hide information. However, there are problems with this approach. Analyze the
following code, explain the results, and correct the problems:
entity Deferred_1 is end; architecture Behave of Deferred_1 is
use work.all; signal y,i1,i2 : INTEGER; signal sel : INTEGER range 0 to 1;
begin with sel select y <= i1 when s0, i2 when s1; end;
10.74 (***Viterbi code, days) Convert the Verilog model of the Viterbi decoder in Chapter 11 to VHDL. This problem is
tedious without the help of some sort of Verilog to VHDL conversion process. There are two main approaches to this problem.
The first uses a synthesis tool to read the behavioral Verilog and write structural VHDL (the Compass ASIC Synthesizer can
do this, for example). The second approach uses conversion programs (Alternative System Concepts Inc. at
http://www.ascinc.com is one source). Some of these companies allow you to e-mail code to them and they will
automatically return a translated version.
10.75 (*Wait statement, 30 min.) Rewrite the code below using a single wait statement and write a testbench to prove that
both approaches are exactly equivalent:
entity Wait_Exit is port (Clk : in BIT); end;
architecture Behave of Wait_Exit is
begin process begin
loop wait on Clk; exit when Clk = '1'; end loop;
end process;
end;
10.76 (Expressions, 10 min.) Explain and correct the problems with the following:
variable b : BOOLEAN; b := "00" < "11";
variable bv8 : BIT_VECTOR (7 downto 0) := "1000_0000";
10.77 (Combinational logic using case statement, 10 min.) A Verilog user suggests the following method to model
combinational logic. What are the problems with this approach? Can you get it to work?
entity AndCase is port (a, b : BIT; y : out BIT); end;
architecture Behave of AndCase is begin process (a , b) begin
case a & b is
when '1'&'1' => y <= '1'; when others => y <= '0';
end case;
end process; end;
10.78 (*Generics and back-annotation, 60 min.)
Construct design entities And_3(Behave), a two-input AND gate, and Xor_3(Behave) , a two-input XOR gate. Include
generic constants to model the propagation delay from each input to the output separately. Use the following entity declaration
for And_3:
entity And_3 is port (I1, I2 : BIT; O : out BIT);
generic (I1toO, I2toO : DELAY_LENGTH := 0.4 ns); end;
Create and test a package, P_1, that contains And_3 and Xor_3 as components.
Create and test a design entity Half_Adder_3 (Structure_3) that uses P_1, with the following interface:
entity Half_Adder_3 is port (X, Y : BIT; Sum, Carry : out BIT); end;
Modify and test the architecture Structure_3 for Half_Adder_3 so that you can use the following configuration:
configuration Structure_3 of Half_Adder_3 is
for Structure_3
for L1 : XOR generic map (0.66 ns,0.69 ns); end for;
for L2 : AND generic map (0.5 ns, 0.6 ns) port map (I2 => HI); end for;
end for; end;
10.79 (SNUG'95, *60 min.) In 1995 John Cooley organized a contest between VHDL and Verilog for ASIC designers. The
goal was to design the fastest 9-bit counter in under one hour using Synopsys synthesis tools and an LSI Logic vendor
technology library. The VHDL interface is as follows:
library ieee; use ieee.std_logic_1164.all;
-- use ieee.std_logic_arith.all; -- substitute your package here
entity counter is port (
data_in
: in std_logic_vector(8 downto 0);
up
: in std_logic;
down
: in std_logic;
clock
: in std_logic;
count_out : inout std_logic_vector(8 downto 0);
carry_out : out std_logic;
borrow_out : out std_logic;
parity_out : out std_logic ); end counter;
architecture example of counter is begin
-- insert your design here
end example;
The counter is positive-edge triggered, counts up with up = '1' and down with down = '1' . The contestants had the
advantage of a predefined testbench with a set of test vectors, you do not. Design a model for the counter and a testbench. How
confident are you that you have thoroughly tested your model? (In the real contest none of the VHDL contestants managed to
even complete a working design in under one hour. In addition, the VHDL experts that had designed the testbench omitted a
test case for one of the design specifications.)
10.80 (*A test procedure, 45 min.) Write a procedure all (for a package test ) that serially generates all possible input
values for a signal spaced in time by a delay, dly . Use the following interface:
library ieee; use ieee.std_logic_1164.all; package test is
procedure all (signal SLV : out STD_LOGIC_VECTOR; dly : in TIME);
end package test ;
10.81 (Direct instantiation, 20 min.) Write an architecture for a full-adder, entity Full_Adder_2, that directly instantiates units
And_2(Behave) and Xor_2(Behave). This is only possible in a VHDL-93 environment.
entity And_2 is port (i1, i2 : BIT; y : out BIT); end;
entity Xor_2 is port (i1, i2 : BIT; y : out BIT); end;
entity Full_Adder_2 is port (a, b, c : BIT ; sum, cout : out BIT); end;
10.82 (**Shift operators for 1164, 60 min.) Write a package body to implement the VHDL-93 shift operators, sll and srl, for
the type STD_LOGIC_VECTOR. Use the following package header:
package 1164_shift is
function "sll"(x : STD_LOGIC_VECTOR; n : INTEGER)
return STD_LOGIC_VECTOR;
function "srl"(x : STD_LOGIC_VECTOR; n : INTEGER)
return STD_LOGIC_VECTOR;
end package 1164_shift;
10.83 (**VHDL wait statement, 60 min.) What is the problem with the following VHDL code? Hint: You may need to
consult the VHDL LRM.
procedure p is begin wait on b; end;
process (a) is begin procedure p; end process;
10.84 (**Null range, 45 min.) A range such as 1 to -1 or 0 downto 1 is a null range ( 0 to 0 is a legal range). Write
a one-page summary on null ranges, including code examples. Is a null range treated as an ascending or descending range?
10.85 (**Loops, 45 min.) Investigate the following issues with loops, including code examples and the results of analysis and
simulation:
Try to alter the loop parameter within a loop. What happens?
What is the type of the loop parameter?
Can the condition inside a loop depend on a loop parameter?
What happens in a for loop if the range is null?
Can you pass a loop parameter out of a procedure as a procedure parameter?
10.86 (Signals and variables, 30 min.) Write a summary on signals and variables, including code examples.
10.87 (Type conversion, 60 min.) There are some very subtle rules involving type conversion, [VHDL 93LRM7.3.5]. Does the
following work? Explain the type conversion rules.
BV <= BIT_VECTOR("1111");
10.19 Bibliography
The definitive reference guide to VHDL is the IEEE VHDL LRM [IEEE,
1076-1993]. The LRM is initially difficult to read because it is concise and
precise (the LRM is intended for tool builders and experienced tool users, not as
a tutorial). The LRM does form a useful reference--as does a dictionary for
serious users of any language. You might think of the LRM as a legal contract
between you and the company that sells you software that is compliant with the
standard. VHDL software uses the terminology of the LRM for error messages,
so it is necessary to understand the terms and definitions of the LRM. The
WAVES standard [IEEE 1029.1-1991] deals with the problems of interfacing
VHDL testbenches to testers.
VHDL International maintains VIUF (VHDL International Users' Forum)
Internet Services ( http:/www.vhdl.org ) and links to other groups
working on VHDL including the IEEE synthesis packages, IEEE WAVES
packages, and IEEE VITAL packages (see also Appendix A).
The frequently asked questions (FAQ) list for the VHDL newsgroup
comp.lang.vhdl is a useful starting point (the list is archived at
gopher://kona.ee.pitt.edu/h0/NewsGroupArchives ).
Information on character sets and the problems of exchanging information across
national boundaries can be found at
ftp://watsun.cc.columbia.edu/kermit/charsets .
10.20 References
Page numbers in brackets after the reference indicate the location in the chapter
body.
IEEE 1029.1-1991. IEEE Standard for Waveform and Vector Exchange
(WAVES). IEEE Std 1029.1-1991. The Institute of Electrical and Electronics
Engineers, Inc., New York. Available from The Institute of Electrical and
Electronics Engineers, Inc., 345 East 47th Street, New York, NY 10017 USA.
IEEE 1076-1993. IEEE Standard VHDL Language Reference Manual (ANSI).
IEEE Std. 1076-1993. The Institute of Electrical and Electronics Engineers, Inc.,
New York. Available from The Institute of Electrical and Electronics Engineers,
Inc., 345 East 47th Street, New York, NY 10017 USA. [p. 380]
IEEE 1076.2-1996. Standard VHDL Language Mathematical Packages. IEEE
Ref. AD129-NYF. Approved by IEEE Standards Board on 19 September 1996.
[p. 404].
ISO 8859-1. 1987 (E). Information Processing--8-bit single-byte coded graphic
character sets--Part 1: Latin Alphabet No. 1. American National Standards
Institute, Hackensack, NJ; 1987. Available from Sales Department, American
National Standards Institute, 105-111 South State Street, Hackensack, NJ 07601
USA. [p. 391]
IEEE Language Reference Manual project
This material is an experimental project to link ASICs... the book with the IEEE
VHDL Language Reference Manual. The VHDL-93 LRM was published on
CD-ROM in 1997, but contained errors. The VHDL LRM and the CD-ROM are
both copyright material, and vigorously protected by the IEEE. This project is not
intended for public distribution and access is therefore protected.
1. The first part of the project was to find/eliminate the errors in the
CD-ROM version of VHDL-93 LRM (these have been found and
corrected).
2. The second part was to link the LRM with the text (this is complete, see
the index of chapters in HTML format)
3. The third part is to merge educational material developed by the US
Department of Defence (DoD) DARPA sponsored RASSP project with the
LRM and ASICs... the book. Without the support of the IEEE or DARPA,
and with no easy resolution to copyright problems, it is currently
impossible to complete this project.
● LRM Table of Contents
●
LRM Section 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
●
LRM Annex A B C D E
●
LRM Index
Some notes for people working on and with this
project material
References to the IEEE LRM in my HTML pages are of the form:
<A HREF="../LRM/HTML/1076_2.HTM#2.2">93LRM2.2]</A>
to turn these off (so that people cannot access the LRM, for example) you need to
insert comment tags around the HTML reference tags:
<!----> and <!---->
Search and replace for HTML (grep format for BBEdit)
search for: </PRE>/r<PRE CLASS="Computer[a-zA-z]+"><A NAME="[^"]+">
</A>
replace with: null
search for: (<PRE CLASS="Computer[^"]+">)<A NAME="[^"]+"> </A>
replace with: \1
search for: </B>/r
replace with: </B>
search for: <TABLE>
replace with: <TABLE BORDER="1" CELLSPACING="2"
CELLPADDING="2">
search for: <SUB CLASS="Subscript">
replace with: <SUB>
search for: <P CLASS="Symbol">([a-zA-z])</P>
replace with: <FONT FACE="symbol">\1</FONT>
search for: <P CLASS="Symbol">&yen;</P>
replace with: <FONT FACE="symbol">&yen;</FONT>
Some of the material in this website is protected using access control.
The IEEE VHDL LRM material on which the LRM project is based is copyright
and therefore access is protected with the following .htaccess file:
<Limit GET>
order deny,allow
deny from all
allow from .eng.hawaii.edu
allow from 128.171.61
</Limit>
Web-page access control
In order to control access to Web pages, NCSA and Apache servers (and many
others) look for a file named .htaccess in each directory along the path to a
Web page. The lowest level .htaccess file (i.e. that closest to the Web page)
determines access. There are two styles of access control.
Domain-name based access control
The first and simplest type of access control restricts access to machines which
have a hostname that match a pattern. For example placing these lines in a file
named .htaccess in a directory
Options All
<Limit GET>
order deny,allow
deny from all
allow from .edu
</Limit>
restricts access to that directory to those hostnames whose domain names end in
.edu.
Password-based access control
To implement password access control, an .htaccess file looks like this
Options All
AuthType Basic
AuthName [message]
AuthUserFile .passwd
<Limit GET>
require valid-user
</Limit>
You need a copy of the htpasswd program to establish user names and assign
passwords.
The message in the square brackets is a text string that will be displayed to the
user when they are prompted for the password. The password file does not have
to located in the same directory as the .htaccess file.
For more information, see the NCSA HTTPd access configuration
documentation.
Errors in IEEE VHDL CD-ROM
Document titles
The documents all have titles:
VHDL LRM- Introduction
(sometimes this is repeated multiple times) except 1076_TOC.HTM which has the
title:
1076 -- Table of Contents
Broken links
20 missing or broken links (from Adobe PageMill 2.0):
Broken links:
Problem: In 3.1.4 and 3.1.4.1 (see below) there are four bad links attached to
the number '1.0'.
Fix: remove the links.
3.1.4 Floating point types
...
An implementation may restrict the bounds of the range constraint of floating point
types other than type universal_real. However, an implementation must allow the
declaration of any floating point type whose range is wholly contained within the
bounds - 1.0 E38 and + 1.0 E38 inclusive. The representation of floating point
types must include a minimum of six decimal digits of precision.
NOTE--An implementation is not required to detect errors in the execution of a
predefined floating point arithmetic operation, since the detection of overflow
conditions resulting from such operations may not be easily accomplished on many
host systems.
3.1.4.1 Predefined floating point types
The only predefined floating point type is the type REAL. The range of REAL is
host-dependent, but it is guaranteed to include the range - 1.0 E38 to + 1.0 E38
inclusive. It is defined with an ascending range.
Problem: Bad link <A HREF="1076_14.HTM#PED_NUM_SUBT"> in
Index (1076_INA.HTM)
Fix: change to <A HREF="1076_14.HTM#14.2">
Note: Reference to object is quite far into Section 14.2. It would be better to
add another anchor, but this is the simplext fix.
Problem: Bad link <A HREF="1076_14.HTM#14.1:NOTES"> in Index
(1076_INA.HTM)
Fix: Line 2189 in 1076_14.HTM change
NOTES
to
<A NAME="14.1:NOTES"></A>NOTES
Problem: Line 1670 in Index (1076_INA.HTM) <A
HREF="1076_14.HTM#S'OUIET">
Fix: change to <A HREF="1076_14.HTM#S'QUIET">
Problem: bad link in Index (1076_INA.HTM) <A
HREF="1076_8.HTM#8.1.3">
Fix: change to <A HREF="1076_8.HTM#8.13">
Problem: bad link in Index (1076_INA.HTM) <A
HREF="1076_AXA.HTM#BIT_STRING_LITERAL">
Fix: change to <A HREF="1076_AXA.HTM#bit_string_literal">
Problem: bad link in Index (1076_INA.HTM) <A
HREF="1076_AXA.HTM#BIT_VALUE">
Fix: change to <A HREF="1076_AXA.HTM#bit_value">
Problem: multiple bad links in Index (1076_INA.HTM) <A
HREF="1076_AXC.HTM#ANNEXC">
Fix: change all to <A HREF="1076_AXC.HTM#AnnexC">
Problem: bad link in Index (1076_INA.HTM) <A
HREF="1076_AXC.HTM#ANNEX C">
Fix: change to <A HREF="1076_AXC.HTM#AnnexC">
Problem: multiple bad links in Index (1076_INA.HTM) <A
HREF="1076_AXE.HTM#ANNEX E">
Fix: change all to <A HREF="1076_AXE.HTM#Annex E">
Problem: bad link in Index (1076_INA.HTM) <A
HREF="1076_AXE.HTM#ANNEX E">
Fix: change to <A HREF="1076_AXE.HTM#Annex E">
Problem: bad link in Index (1076_INA.HTM) <A
HREF="#./1076_0.HTM0.2.3">
Fix: change to <A HREF="1076_0.HTM#0.2.3">
Problem: bad link in Index (1076_INA.HTM) <A HREF="#12.3.1.1">
Fix: change to <A HREF="1076_12.HTM#12.3.1.1">
Problem: bad link in Index (1076_INA.HTM) <A HREF="#12.6.2">
Fix: change to <A HREF="1076_12.HTM#12.6.2">
Problem: bad link in Index (1076_INA.HTM) <A HREF="#4.3.1.3">
Fix: change to <A HREF="1076_4.HTM#4.3.1.3">
Problem: in 1076_9.HTM (see <A HREF="1076_2.HTM#2.6.4">2.6.4
Fix: change to (see <A HREF="1076_12.HTM#12.6.4">12.6.4
Problem: in 1076_AXD.HTM <A HREF="1076_4.HTM#4.3.4">4.3.4
</A>
Fix: change to 4.3.4
Note: There is a Section 4.3.4 Alias Declaration in 1076-87 there is no
Section 4.3.4 in 1076-93. There is a Section 4.3.3 Alias declarations in
1076-93.
Problem: in 1076_AXB.HTM <A HREF="1076_7.HTM#7.5.2">7.5.2
Fix: change to <A HREF="1076_7.HTM#7.4.2">7.4.2
Note: There is no Section 7.5.2. Section 7.4.2 Globally static primaries parts
g and h deal with aggregates.
Problem: in 1076_2.HTM <A HREF="1076_8.HTM#8.1.4">8.1.4
Fix: Until I can find out what this is supposed to be, I'll leave it alone.
Note: There is no Section 8.1.4.
Problem: in 1076_AXD.HTM <A HREF="1076_8.HTM#8.3.1">8.3.1
</A>
Fix: change to 8.3.1
Note: There is no Section 8.3.1 in 1076-93. There is a Section 8.3.1 Updating
a Projected Output Waveform in 1076-87.
Error in formatting and content in Section 8.
What it currently looks like:
What it should look like:
Minor errors in formatting and content in the Index
L ast E d ited by S P 1411 2 0 0 4
CHAPTER 11
VERILOG HDL
In this chapter we look at the Verilog hardware description language. Gateway
Design Automation developed Verilog as a simulation language. The use of the
Verilog-XL simulator is discussed in more detail in Chapter 13. Cadence
purchased Gateway in 1989 and, after some study, placed the Verilog language in
the public domain. Open Verilog International (OVI) was created to develop the
Verilog language as an IEEE standard. The definitive reference guide to the
Verilog language is now the Verilog LRM, IEEE Std 1364-1995 [1995]. 1 This
does not mean that all Verilog simulators and tools adhere strictly to the IEEE
Standard--we must abide by the reference manual for the software we are using.
Verilog is a fairly simple language to learn, especially if you are familiar with the
C programming language. In this chapter we shall concentrate on the features of
Verilog applied to high-level design entry and synthesis for ASICs.
1. Some of the material in this chapter is reprinted with permission from IEEE
Std 1364-1995, © Copyright 1995 IEEE. All rights reserved.
11.1 A Counter
The following Verilog code models a "black box" that contains a 50 MHz clock (period 20 ns), counts from 0 to 7, resets,
and then begins counting at 0 again:
`timescale 1ns/1ns // Set the units of time to be nanoseconds.
module counter;
reg clock; // Declare a reg data type for the clock.
integer count; // Declare an integer data type for the count.
initial // Initialize things; this executes once at t=0.
begin
clock = 0; count = 0; // Initialize signals.
#340 $finish; // Finish after 340 time ticks.
end
/* An always statement to generate the clock; only one statement follows the always
so we don't need a begin and an end. */
always #10 clock = ~ clock; // Delay (10ns) is set to half the clock cycle.
/* An always statement to do the counting; this executes at the same time
(concurrently) as the preceding always statement. */
always
begin
// Wait here until the clock goes from 1 to 0.
@ (negedge clock);
// Now handle the counting.
if (count == 7)
count = 0;
else
count = count + 1;
$display("time = ",$time," count = ", count);
end
endmodule
Verilog keywords (reserved words that are part of the Verilog language) are shown in bold type in the code listings (but not
in the text). References in this chapter such as [Verilog LRM 1.1] refer you to the IEEE Verilog LRM.
The following output is from the Cadence Verilog-XL simulator. This example includes the system input so you can see
how the tool is run and when it is finished. Some of the banner information is omitted in the listing that follows to save
space (we can use "quiet" mode using a '-q' flag, but then the version and other useful information is also suppressed):
> verilog counter.v
VERILOG-XL 2.2.1
Apr 17, 1996 11:48:18
... Banner information omitted here...
Compiling source file "counter.v"
Highest level modules:
counter
time =
20 count =
1
time =
40 count =
2
(... 12 lines omitted...)
time =
300 count =
7
time =
320 count =
0
L10 "counter.v": $finish at simulation time 340
223 simulation events
CPU time: 0.6 secs to compile + 0.2 secs to link + 0.0 secs in simulation
End of VERILOG-XL 2.2.1
Apr 17, 1996 11:48:20
>
Here is the output of the VeriWell simulator from the console window (future examples do not show all of the compiler
output-- just the model output):
Veriwell -k VeriWell.key -l VeriWell.log -s :counter.v
... banner information omitted ....
Memory Available: 0
Entering Phase I...
Compiling source file : :counter.v
The size of this model is [1%, 1%] of the capacity of the free version
Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
counter
C1> .
time =
20 count =
1
time =
40 count =
2
(... 12 lines omitted...)
time =
300 count =
7
time =
320 count =
0
Exiting VeriWell for Macintosh at time 340
0 Errors, 0 Warnings, Memory Used: 29468
Compile time = 0.6, Load time = 0.7, Simulation time = 4.7
Normal exit
Thank you for using VeriWell for Macintosh
11.2 Basics of the Verilog Language
A Verilog identifier [Verilog LRM2.7], including the names of variables, may contain any sequence of letters, digits, a
dollar sign '$' , and the underscore '_' symbol. The first character of an identifier must be a letter or underscore; it
cannot be a dollar sign '$' , for example. We cannot use characters such as '-' (hyphen), brackets, or '#' (for
active-low signals) in Verilog names (escaped identifiers are an exception). The following is a shorthand way of saying
the same thing:
identifier ::= simple_identifier | escaped_identifier
simple_identifier ::= [a-zA-Z][a-zA-Z_$]
escaped_identifier ::=
\ {Any_ASCII_character_except_white_space} white_space
white_space ::= space | tab | newline
If we think of '::=' as an equal sign, then the preceding "equation" defines the syntax of an identifier. Usually we use
the Backus-Naur form (BNF) to write these equations. We also use the BNF to describe the syntax of VHDL. There is an
explanation of the BNF in Appendix A. Verilog syntax definitions are given in Appendix B. In Verilog all names,
including keywords and identifiers, are case-sensitive. Special commands for the simulator (a system task or a system
function) begin with a dollar sign '$' [Verilog LRM 2.7]. Here are some examples of Verilog identifiers:
module identifiers;
/* Multiline comments in Verilog
look like C comments and // is OK in here. */
// Single-line comment in Verilog.
reg legal_identifier,two__underscores;
reg _OK,OK_,OK_$,OK_123,CASE_SENSITIVE, case_sensitive;
reg \/clock ,\a*b ; // Add white_space after escaped identifier.
//reg $_BAD,123_BAD; // Bad names even if we declare them!
initial begin
legal_identifier = 0; // Embedded underscores are OK,
two__underscores = 0; // even two underscores in a row.
_OK = 0; // Identifiers can start with underscore
OK_ = 0; // and end with underscore.
OK$ = 0; // $ sign is OK, but beware foreign keyboards.
OK_123 =0; // Embedded digits are OK.
CASE_SENSITIVE = 0; // Verilog is case-sensitive (unlike VHDL).
case_sensitive = 1;
\/clock = 0; // An escaped identifier with \ breaks rules,
\a*b = 0; // but be careful to watch the spaces!
$display("Variable CASE_SENSITIVE= %d",CASE_SENSITIVE);
$display("Variable case_sensitive= %d",case_sensitive);
$display("Variable \/clock = %d",\/clock );
$display("Variable \\a*b = %d",\a*b );
end endmodule
The following is the output from this model (future examples in this chapter list the simulator output directly after the
Verilog code).
Variable
Variable
Variable
Variable
CASE_SENSITIVE= 0
case_sensitive= 1
/clock = 0
\a*b = 0
11.2.1 Verilog Logic Values
Verilog has a predefined logic-value system or value set [Verilog LRM 3.1] that uses four logic values: '0' , '1' ,
'x' , and 'z' (lowercase 'x' and lowercase 'z' ). The value 'x' represents an uninitialized or an unknown logic
value--an unknown value is either '1' , '0' , 'z' , or a value that is in a state of change. The logic value 'z'
represents a high-impedance value, which is usually treated as an 'x' value. Verilog uses a more complicated internal
logic-value system in order to resolve conflicts between different drivers on the same node. This hidden logic-value
system is useful for switch-level simulation, but for most ASIC simulation and synthesis purposes we do not need to
worry about the internal logic-value system.
11.2.2 Verilog Data Types
There are several data types in Verilog--all except one need to be declared before we can use them. The two main data
types are nets and registers [Verilog LRM 3.2]. Nets are further divided into several net types. The most common and
important net types are: wire and tri (which are identical); supply1 and supply0 (which are equivalent to the positive
and negative power supplies respectively). The wire data type (which we shall refer to as just wire from now on) is
analogous to a wire in an ASIC. A wire cannot store or hold a value. A wire must be continuously driven by an
assignment statement (see Section 11.5). The default initial value for a wire is 'z' [Verilog LRM3.6]. There are also
integer, time, event, and real data types.
module declarations_1;
wire pwr_good, pwr_on, pwr_stable; // Explicitly declare wires.
integer i; // 32-bit, signed (2's complement).
time t; // 64-bit, unsigned, behaves like a 64-bit reg.
event e; // Declare an event data type.
real r; // Real data type of implementation defined size.
// An assign statement continuously drives a wire:
assign pwr_stable = 1'b1; assign pwr_on = 1; // 1 or 1'b1
assign pwr_good = pwr_on & pwr_stable;
initial begin
i = 123.456; // There must be a digit on either side
r = 123456e-3; // of the decimal point if it is present.
t = 123456e-3; // Time is rounded to 1 second by default.
$display("i=%0g",i," t=%6.2f",t," r=%f",r);
#2 $display("TIME=%0d",$time," ON=",pwr_on,
" STABLE=",pwr_stable," GOOD=",pwr_good);
$finish; end
endmodule
i=123 t=123.00 r=123.456000
TIME=2 ON=1 STABLE=1 GOOD=1
A register data type is declared using the keyword reg and is comparable to a variable in a programming language. On
the LHS of an assignment a register data type (which we shall refer to as just reg from now on) is updated immediately
and holds its value until changed again. The default initial value for a reg is 'x' . We can transfer information directly
from a wire to a reg as shown in the following code:
module declarations_2;
reg Q, Clk; wire D;
// Drive the wire (D):
assign D = 1;
// At a +ve clock edge assign the value of wire D to the reg Q:
always @(posedge Clk) Q = D;
initial Clk = 0; always #10 Clk = ~ Clk;
initial begin #50; $finish; end
always begin
$display("T=%2g", $time," D=",D," Clk=",Clk," Q=",Q); #10; end
endmodule
T= 0 D=z Clk=0 Q=x
T=10 D=1 Clk=1 Q=x
T=20 D=1 Clk=0 Q=1
T=30 D=1 Clk=1 Q=1
T=40 D=1 Clk=0 Q=1
We shall discuss assignment statements in Section 11.5. For now, it is important to recognize that a reg is not always
equivalent to a hardware register, flip-flop, or latch. For example, the following code describes purely combinational
logic:
module declarations_3;
reg a,b,c,d,e;
initial begin
#10; a = 0;b = 0;c = 0;d = 0; #10; a = 0;b = 1;c = 1;d = 0;
#10; a = 0;b = 0;c = 1;d = 1; #10; $stop;
end
always begin
@(a or b or c or d) e = (a|b)&(c|d);
$display("T=%0g",$time," e=",e);
end
endmodule
T=10 e=0
T=20 e=1
T=30 e=0
A single-bit wire or reg is a scalar (the default). We may also declare a wire or reg as a vector with a range of
bits [Verilog LRM 3.3]. In some situations we may use implicit declaration for a scalar wire ; it is the only data type we
do not always need to declare. We must use explicit declaration for a vector wire or any reg . We may access (or
expand) the range of bits in a vector one at a time, using a bit-select, or as a contiguous subgroup of bits (a continuous
sequence of numbers--like a straight in poker) using a part-select [Verilog LRM 4.2]. The following code shows some
examples:
module declarations_4;
wire Data; // A scalar net of type wire.
wire [31:0] ABus, DBus; // Two 32-bit-wide vector wires:
// DBus[31] = leftmost = most-significant bit = msb
// DBus[0] = rightmost = least-significant bit = lsb
// Notice the size declaration precedes the names.
// wire [31:0] TheBus, [15:0] BigBus; // This is illegal.
reg [3:0] vector; // A 4-bit vector register.
reg [4:7] nibble; // msb index < lsb index is OK.
integer i;
initial begin
i = 1;
vector = 'b1010; // Vector without an index.
nibble = vector; // This is OK too.
#1; $display("T=%0g",$time," vector=", vector," nibble=", nibble);
#2; $display("T=%0g",$time," Bus=%b",DBus[15:0]);
end
assign DBus [1] = 1; // This is a bit-select.
assign DBus [3:0] = 'b1111; // This is a part-select.
// assign DBus [0:3] = 'b1111; // Illegal : wrong direction.
endmodule
T=1 vector=10 nibble=10
T=3 Bus=zzzzzzzzzzzz1111
There are no multidimensional arrays in Verilog, but we may declare a memory data type as an array of registers
[Verilog LRM 3.8]:
module declarations_5;
reg [31:0] VideoRam [7:0]; // An 8-word by 32-bit wide memory.
initial begin
VideoRam[1] = 'bxz; // We must specify an index for a memory.
VideoRam[2] = 1;
VideoRam[7] = VideoRam[VideoRam[2]]; // Need 2 clock cycles for this.
VideoRam[8] = 1; // Careful! the compiler won't complain about this!
// Verify what we entered:
$display("VideoRam[0] is %b",VideoRam[0]);
$display("VideoRam[1] is %b",VideoRam[1]);
$display("VideoRam[2] is %b",VideoRam[2]);
$display("VideoRam[7] is %b",VideoRam[7]);
end
endmodule
VideoRam[0] is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
VideoRam[1] is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxz
VideoRam[2] is 00000000000000000000000000000001
VideoRam[7] is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxz
We may also declare an integer array or time array in the same way as an array of reg , but there are no real arrays
[Verilog LRM 3.9]:
module declarations_6;
integer Number [1:100]; // Notice that size follows name
time Time_Log [1:1000]; // - as in an array of reg.
// real Illegal [1:10]; // Illegal. There are no real arrays.
endmodule
11.2.3 Other Wire Types
There are the following other Verilog wire types (rarely used in ASIC design) [Verilog LRM 3.7]:
●
●
●
wand , wor , triand , and trior model wired logic. Wiring, or dotting, the outputs of two gates generates a
logic function (in emitter-coupled logic, ECL, or in an EPROM, for example). This is one area in which the logic
values 'z' and 'x' are treated differently.
tri0 and tri1 model resistive connections to VSS or VDD.
trireg is like a wire but associates some capacitance with the net, so it can model charge storage.
There are also other keywords that may appear in declarations:
● scalared and vectored are properties of vectors [Verilog LRM 3.3].
●
small , medium , and large model the charge strength of trireg connections [Verilog LRM 7].
11.2.4 Numbers
Constant numbers are integer or real constants [Verilog LRM 2.5]. Integer constants are written as
width'radix value
where width and radix are optional. The radix (or base) indicates the type of number: decimal ( d or D ), hex ( h
or H ), octal ( o or O ), or binary ( b or B ). A number may be sized or unsized. The length of an unsized number is
implementation dependent. We can use '1' and '0' as numbers since they cannot be identifiers, but we must write
1'bx and 1'bz for 'x' and 'z' . A number may be declared as a parameter [Verilog LRM 3.10]. A parameter
assignment belongs inside a module declaration and has local scope [Verilog LRM3.11]. Real constants are written
using decimal (100.0) or scientific notation (1e2) and follow IEEE Std 754-1985 for double-precision floating-point
numbers. Reals are rounded to the nearest integer, ties (numbers that end in .5) round away from zero [Verilog LRM
3.9], but not all implementations follow this rule (the output from the following code is from VeriWell, which rounds
ties toward zero for negative integers).
module constants;
parameter H12_UNSIZED = 'h 12; // Unsized hex 12 = decimal 18.
parameter H12_SIZED = 6'h 12; // Sized hex 12 = decimal 18.
// Note: a space between base and value is OK.
// Note: `' (single apostrophes) are not the same as the ' character.
parameter D42 = 8'B0010_1010; // bin 101010 = dec 42
// OK to use underscores to increase readability.
parameter D123 = 123; // Unsized decimal (the default).
parameter D63 = 8'o 77; // Sized octal, decimal 63.
// parameter ILLEGAL = 1'o9; // No 9's in octal numbers!
// A = 'hx and B = 'ox assume a 32 bit width.
parameter A = 'h x, B = 'o x, C = 8'b x, D = 'h z, E = 16'h ????;
// Note the use of ? instead of z, 16'h ???? is the same as 16'h zzzz.
// Also note the automatic extension to a width of 16 bits.
reg [3:0] B0011,Bxxx1,Bzzz1; real R1,R2,R3; integer I1,I3,I_3;
parameter BXZ = 8'b1x0x1z0z;
initial begin
B0011 = 4'b11; Bxxx1 = 4'bx1; Bzzz1 = 4'bz1; // Left padded.
R1 = 0.1e1; R2 = 2.0; R3 = 30E-01; // Real numbers.
I1 = 1.1; I3 = 2.5; I_3 = -2.5; // IEEE rounds away from 0.
end initial begin #1;
$display
("H12_UNSIZED, H12_SIZED (hex) = %h, %h",H12_UNSIZED, H12_SIZED);
$display("D42 (bin) = %b",D42," (dec) = %d",D42);
$display("D123 (hex) = %h",D123," (dec) = %d",D123);
$display("D63 (oct) = %o",D63);
$display("A (hex) = %h",A," B (hex) = %h",B);
$display("C (hex) = %h",C," D (hex) = %h",D," E (hex) = %h",E);
$display("BXZ (bin) = %b",BXZ," (hex) = %h",BXZ);
$display("B0011, Bxxx1, Bzzz1 (bin) = %b, %b, %b",B0011,Bxxx1,Bzzz1);
$display("R1, R2, R3 (e, f, g) = %e, %f, %g", R1, R2, R3);
$display("I1, I3, I_3 (d) = %d, %d, %d", I1, I3, I_3);
end
endmodule
H12_UNSIZED, H12_SIZED (hex) = 00000012, 12
D42 (bin) = 00101010 (dec) = 42
D123 (hex) = 0000007b (dec) =
123
D63 (oct) = 077
A (hex) = xxxxxxxx B (hex) = xxxxxxxx
C (hex) = xx D (hex) = zzzzzzzz E (hex) = zzzz
BXZ (bin) = 1x0x1z0z (hex) = XZ
B0011, Bxxx1, Bzzz1 (bin) = 0011, xxx1, zzz1
R1, R2, R3 (e, f, g) = 1.000000e+00, 2.000000, 3
I1, I3, I_3 (d) =
1,
3,
-2
11.2.5 Negative Numbers
Integer numbers are signed (two's complement) or unsigned. The following example illustrates the handling of negative
constants [Verilog LRM 3.2 , 4.1]:
module negative_numbers;
parameter PA = -12, PB = -'d12, PC = -32'd12, PD = -4'd12;
integer IA , IB , IC , ID ; reg [31:0] RA , RB , RC , RD ;
initial begin #1;
IA = -12; IB = -'d12; IC = -32'd12; ID = -4'd12;
RA = -12; RB = -'d12; RC = -32'd12; RD = -4'd12; #1;
$display("
parameter
integer
reg[31:0]");
$display ("-12
=",PA,IA,,,RA);
$displayh("
",,,,PA,,,,IA,,,,,RA);
$display ("-'d12
=",,PB,IB,,,RB);
$displayh("
",,,,PB,,,,IB,,,,,RB);
$display ("-32'd12 =",,PC,IC,,,RC);
$displayh("
",,,,PC,,,,IC,,,,,RC);
$display ("-4'd12 =",,,,,,,,,,PD,ID,,,RD);
$displayh("
",,,,,,,,,,,PD,,,,ID,,,,,RD);
end
endmodule
parameter
integer
reg[31:0]
-12
=
-12
-12 4294967284
fffffff4
fffffff4
fffffff4
-'d12
= 4294967284
-12 4294967284
fffffff4
fffffff4
fffffff4
-32'd12 = 4294967284
fffffff4
-4'd12 =
4
4
-12
fffffff4
-12
fffffff4
4294967284
fffffff4
4294967284
fffffff4
Verilog only "keeps track" of the sign of a negative constant if it is (1) assigned to an integer or (2) assigned to a
parameter without using a base (essentially the same thing). In other cases (even though the bit representations may
be identical to the signed number--hexadecimal fffffff4 in the previous example), a negative constant is treated as an
unsigned number. Once Verilog "loses" the sign, keeping track of signed numbers becomes your responsibility (see also
Section 11.3.1).
11.2.6 Strings
The code listings in this book use Courier font. The ISO/ANSI standard for the ASCII code defines the characters, but
not the appearance of the graphic symbol in any particular font. The confusing characters are the quote and accent
characters:
module characters; /*
" is ASCII 34 (hex 22), double quote.
' is ASCII 39 (hex 27), tick or apostrophe.
/ is ASCII 47 (hex 2F), forward slash.
\ is ASCII 92 (hex 5C), back slash.
` is ASCII 96 (hex 60), accent grave.
| is ASCII 124 (hex 7C), vertical bar.
There are no standards for the graphic symbols for codes above 128.
´ is 171 (hex AB), accent acute in almost all fonts.
" is 210 (hex D2), open double quote, like 66 (in some fonts).
" is 211 (hex D3), close double quote, like 99 (in some fonts).
` is 212 (hex D4), open single quote, like 6 (in some fonts).
' is 213 (hex D5), close single quote, like 9 (in some fonts).
*/ endmodule
Here is an example showing the use of string constants [Verilog LRM 2.6]:
module text;
parameter A_String = "abc"; // string constant, must be on one line
parameter Say = "Say \"Hey!\"";
// use escape quote \" for an embedded quote
parameter Tab = "\t"; // tab character
parameter NewLine = "\n"; // newline character
parameter BackSlash = "\\"; // back slash
parameter Tick = "\047"; // ASCII code for tick in octal
// parameter Illegal = "\500"; // illegal - no such ASCII code
initial begin$display("A_String(str) = %s ",A_String," (hex) = %h ",A_String);
$display("Say = %s ",Say," Say \"Hey!\"");
$display("NewLine(str) = %s ",NewLine," (hex) = %h ",NewLine);
$display("\\(str) = %s ",BackSlash," (hex) = %h ",BackSlash);
$display("Tab(str) = %s ",Tab," (hex) = %h ",Tab,"1 newline...");
$display("\n");
$display("Tick(str) = %s ",Tick," (hex) = %h ",Tick);
#1.23; $display("Time is %t", $time);
end
endmodule
A_String(str) = abc (hex) = 616263
Say = Say \"Hey!\" Say "Hey!"
NewLine(str) = \n (hex) = 0a
\(str) = \\ (hex) = 5c
Tab(str) = \t (hex) = 09 1 newline...
Tick(str) = '
Time is
(hex) = 27
1
Instead of parameters you may use a define directive that is a compiler directive, and not a statement [Verilog
LRM 16]. The define directive has global scope:
module define;
define G_BUSWIDTH 32 // Bus width parameter (G_ for global).
/* Note: there is no semicolon at end of a compiler directive. The character ` is
ASCII 96 (hex 60), accent grave, it slopes down from left to right. It is not the
tick or apostrophe character ' (ASCII 39 or hex 27)*/
wire [`G_BUSWIDTH:0]MyBus; // A 32-bit bus.
endmodule
11.3 Operators
An expression uses any of the three types of operators: unary operators, binary operators, and a single
ternary operator [Verilog LRM 4.1]. The Verilog operators are similar to those in the C programming
language--except there is no autoincrement ( ++ ) or autodecrement ( -- ) in Verilog. Table 11.1 shows
the operators in their (increasing) order of precedence and Table 11.2 shows the unary operators. Here is
an example that illustrates the use of the Verilog operators:
TABLE 11.1
Verilog operators (in increasing order of precedence).
?: (conditional) [legal for real; associates right to left (others associate left to right)]
|| (logical or) [A smaller operand is zero-filled from its msb (0-fill); legal for real]
&& (logical and)[0-fill, legal for real]
| (bitwise or) ~| (bitwise nor) [0-fill]
^ (bitwise xor) ^~ ~^ (bitwise xnor, equivalence) [0-fill]
& (bitwise and) ~& (bitwise nand) [0-fill]
== (logical) != (logical) === (case) !== (case) [0-fill, logical versions are legal for real]
< (lt) <= (lt or equal) > (gt) >= (gt or equal) [0-fill, all arelegal for real]
<< (shift left) >> (shift right) [zero fill; no -ve shifts; shift by x or z results in unknown]
+ (addition) - (subtraction) [if any bit is x or z for + - * / % then entire result is unknown]
* (multiply) / (divide) % (modulus) [integer divide truncates fraction; + - * / legal for real]
Unary operators: ! ~ & ~& | ~| ^ ~^ ^~ + - [see Table 11.2 for precedence]
TABLE 11.2
Verilog unary operators.
Operator Name
Examples
!
logical negation
!123 is 'b0 [0, 1, or x for ambiguous; legal for real]
~
bitwise unary negation ~1'b10xz is 1'b01xx
&
unary reduction and
& 4'b1111 is 1'b1, & 2'bx1 is 1'bx, & 2'bz1 is 1'bx
~&
unary reduction nand
~& 4'b1111 is 1'b0, ~& 2'bx1 is 1'bx
|
unary reduction or
Note:
~|
unary reduction nor
Reduction is performed left (first bit) to right
^
unary reduction xor
Beware of the non-associative reduction operators
~^ ^~
unary reduction xnor
z is treated as x for all unary operators
+
unary plus
+2'bxz is +2'bxz [+m is the same as m; legal for real]
-
unary minus
-2'bxz is x [-m is unary minus m; legal for real]
module operators;
parameter A10xz = {1'b1,1'b0,1'bx,1'bz}; // Concatenation and
parameter A01010101 = {4{2'b01}}; // replication, illegal for real.
// Arithmetic operators: +, -, *, /, and modulus %
parameter A1 = (3+2) %2; // The sign of a % b is the same as sign of a.
// Logical shift operators: << (left), >> (right)
parameter A2 = 4 >> 1; parameter A4 = 1 << 2; // Note: zero fill.
// Relational operators: <, <=, >, >=
initial if (1 > 2) $stop;
// Logical operators: ! (negation), && (and), || (or)
parameter B0 = !12; parameter B1 = 1 && 2;
reg [2:0] A00x; initial begin A00x = 'b111; A00x = !2'bx1; end
parameter C1 = 1 || (1/0); /* This may or may not cause an
error: the short-circuit behavior of && and || is undefined. An
evaluation including && or || may stop when an expression is known
to be true or false. */
// == (logical equality), != (logical inequality)
parameter Ax = (1==1'bx); parameter Bx = (1'bx!=1'bz);
parameter D0 = (1==0); parameter D1 = (1==1);
// === case equality, !== (case inequality)
// The case operators only return true (1) or false (0).
parameter E0 = (1===1'bx); parameter E1 = 4'b01xz === 4'b01xz;
parameter F1 = (4'bxxxx === 4'bxxxx);
// Bitwise logical operators:
// ~ (negation), & (and), | (inclusive or),
// ^ (exclusive or), ~^ or ^~ (equivalence)
parameter A00 = 2'b01 & 2'b10;
// Unary logical reduction operators:
// & (and), ~& (nand), | (or), ~| (nor),
// ^ (xor), ~^ or ^~ (xnor)
parameter G1= & 4'b1111;
// Conditional expression f = a ? b : c [if (a) then f=b else f=c]
// if a=(x or z), then (bitwise) f=0 if b=c=0, f=1 if b=c=1, else f=x
reg H0, a, b, c; initial begin a=1; b=0; c=1; H0=a?b:c; end
reg[2:0] J01x, Jxxx, J01z, J011;
initial begin Jxxx = 3'bxxx; J01z = 3'b01z; J011 = 3'b011;
J01x = Jxxx ? J01z : J011; end // A bitwise result.
initial begin #1;
$display("A10xz=%b",A10xz," A01010101=%b",A01010101);
$display("A1=%0d",A1," A2=%0d",A2," A4=%0d",A4);
$display("B1=%b",B1," B0=%b",B0," A00x=%b",A00x);
$display("C1=%b",C1," Ax=%b",Ax," Bx=%b",Bx);
$display("D0=%b",D0," D1=%b",D1);
$display("E0=%b",E0," E1=%b",E1," F1=%b",F1);
$display("A00=%b",A00," G1=%b",G1," H0=%b",H0);
$display("J01x=%b",J01x); end
endmodule
A10xz=10xz A01010101=01010101
A1=1 A2=2 A4=4
B1=1 B0=0 A00x=00x
C1=1 Ax=x Bx=x
D0=0 D1=1
E0=0 E1=1 F1=1
A00=00 G1=1 H0=0
J01x=01x
11.3.1 Arithmetic
Arithmetic operations on n-bit objects are performed modulo 2n in Verilog,
module modulo; reg [2:0] Seven;
initial begin
#1 Seven = 7; #1 $display("Before=", Seven);
#1 Seven = Seven + 1; #1 $display("After =", Seven);
end
endmodule
Before=7
After =0
Arithmetic operations in Verilog (addition, subtraction, comparison, and so on) on vectors ( reg or
wire ) are predefined (Tables 11.1 and 11.2 show which operators are legal for real ). This is a very
important difference for ASIC designers from the situation in VHDL. However, there are some subtleties
with Verilog arithmetic and negative numbers that are illustrated by the following example (based on an
example in the LRM [Verilog LRM4.1]):
module LRM_arithmetic;
integer IA, IB, IC, ID, IE; reg [15:0] RA, RB, RC;
initial begin
IA = -4'd12;
RA = IA / 3; // reg is treated as unsigned.
RB = -4'd12;
IB = RB / 3; //
IC = -4'd12 / 3; RC = -12 / 3; // real is treated as signed
ID =
-12 / 3; IE = IA / 3; // (two's complement).
end
initial begin #1;
$display("
hex
default");
$display("IA = -4'd12
= %h%d",IA,IA);
$display("RA = IA / 3
=
%h
%d",RA,RA);
$display("RB = -4'd12
=
%h
%d",RB,RB);
$display("IB = RB / 3
= %h%d",IB,IB);
$display("IC = -4'd12 / 3 = %h%d",IC,IC);
$display("RC = -12 / 3
=
%h
%d",RC,RC);
$display("ID = -12 / 3
= %h%d",ID,ID);
$display("IE = IA / 3
= %h%d",IE,IE);
end
endmodule
hex
default
IA = -4'd12
= fffffff4
-12
RA = IA / 3
=
fffc
65532
RB = -4'd12
=
fff4
65524
IB = RB / 3
= 00005551
21841
IC = -4'd12 / 3 = 55555551 1431655761
RC = -12 / 3
=
fffc
65532
ID = -12 / 3
= fffffffc
-4
IE = IA / 3
= fffffffc
-4
We might expect the results of all these divisions to be - 4 = -12/3. For integer assignments, the results are
correctly signed ( ID and IE ). Hex fffc (decimal 65532) is the 16-bit two's complement of - 4, so RA
and RC are also correct if we keep track of the signs ourselves. The integer result IB is incorrect because
Verilog treats RB as an unsigned number. Verilog also treats -4'd12 as an unsigned number in the
calculation of IC . Once Verilog "loses" a sign, it cannot get it back (see also Section 11.2.5).
11.4 Hierarchy
The module is the basic unit of code in the Verilog language [Verilog LRM 12.1],
module holiday_1(sat, sun, weekend);
input sat, sun; output weekend;
assign weekend = sat | sun;
endmodule
We do not have to explicitly declare the scalar wires: saturday , sunday , weekend
because, since these wires appear in the module interface, they must be declared in an input ,
output , or inout statement and are thus implicitly declared. The module interface provides
the means to interconnect two Verilog modules using ports [Verilog LRM 12.3]. Each port must
be explicitly declared as one of input, output, or inout. Table 11.3 shows the characteristics of
ports. Notice that a reg cannot be an input port or an inout port. This is to stop us trying to
connect a reg to another reg that may hold a different value.
TABLE 11.3
Verilog port
Verilog ports.
input
output
inout
reg or wire (or other net)
Characteristics wire (or other net) We can read an output port inside a
module
wire (or other net)
Within a module we may instantiate other modules, but we cannot declare other modules. Ports
are linked using named association or positional association,
`timescale 100s/1s // Units are 100 seconds with precision of 1s.
module life; wire [3:0] n; integer days;
wire wake_7am, wake_8am; // Wake at 7 on weekdays else at 8.
assign n = 1 + (days % 7); // n is day of the week (1-7)
[email protected](wake_8am or wake_7am)
$display("Day=",n," hours=%0d ",($time/36)%24," 8am = ",
wake_8am," 7am = ",wake_7am," m2.weekday = ", m2.weekday);
initial days = 0;
initial begin #(24*36*10);$finish; end // Run for 10 days.
always #(24*36) days = days + 1; // Bump day every 24hrs.
rest m1(n, wake_8am); // Module instantiation.
// Creates a copy of module rest with instance name m1,
// ports are linked using positional notation.
work m2(.weekday(wake_7am), .day(n));
// Creates a copy of module work with instance name m2,
// Ports are linked using named association.
endmodule
module rest(day, weekend); // Module definition.
// Notice the port names are different from the parent.
input [3:0] day; output weekend; reg weekend;
always begin #36 weekend = day > 5; end // Need a delay here.
endmodule
module work(day, weekday);
input [3:0] day; output weekday; reg weekday;
always begin #36 weekday = day < 6; end // Need a delay here.
endmodule
Day= 1 hours=0
8am = 0 7am = 0 m2.weekday = 0
Day= 1 hours=1
8am = 0 7am = 1 m2.weekday = 1
Day= 6 hours=1
8am = 1 7am = 0 m2.weekday = 0
Day= 1 hours=1
8am = 0 7am = 1 m2.weekday = 1
The port names in a module definition and the port names in the parent module may be different.
We can associate (link or map) ports using the same order in the instantiating statement as we
use in the module definition--such as instance m1 in module life . Alternatively we can
associate the ports by naming them--such as instance m2 in module life (using a period '.'
before the port name that we declared in the module definition). Identifiers in a module have
local scope. If we want to refer to an identifier outside a module, we use a hierarchical name
[Verilog LRM12.4] such as m1.weekend or m2.weekday (as in module life ), for
example. The compiler will first search downward (or inward) then upward (outward) to resolve
a hierarchical name [Verilog LRM 12.4-12.5].
11.5 Procedures and Assignments
A Verilog procedure [Verilog LRM 9.9] is an always or initial statement, a task , or a function . The
statements within a sequential block (statements that appear between a begin and an end ) that is part of a
procedure execute sequentially in the order in which they appear, but the procedure executes concurrently with other
procedures. This is a fundamental difference from computer programming languages. Think of each procedure as a
microprocessor running on its own and at the same time as all the other microprocessors (procedures). Before I
discuss procedures in more detail, I shall discuss the two different types of assignment statements:
● continuous assignments that appear outside procedures
● procedural assignments that appear inside procedures
To illustrate the difference between these two types of assignments, consider again the example used in Section 11.4:
module holiday_1(sat, sun, weekend);
input sat, sun; output weekend;
assign weekend = sat | sun; // Assignment outside a procedure.
endmodule
We can change weekend to a reg instead of a wire , but then we must declare weekend and use a procedural
assignment (inside a procedure--an always statement, for example) instead of a continuous assignment. We also
need to add some delay (one time tick in the example that follows); otherwise the computer will never be able to get
out of the always procedure to execute any other procedures:
module holiday_2(sat, sun, weekend);
input sat, sun; output weekend; reg weekend;
always #1 weekend = sat | sun; // Assignment inside a procedure.
endmodule
We shall cover the continuous assignment statement in the next section, which is followed by an explanation of
sequential blocks and procedural assignment statements. Here is some skeleton code that illustrates where we may use
these assignment statements:
module assignments
//... Continuous assignments go here.
always // beginning of a procedure
begin // beginning of sequential block
//... Procedural assignments go here.
end
endmodule
Table 11.4 at the end of Section 11.6 summarizes assignment statements, including two more forms of
assignment--you may want to look at this table now.
11.5.1 Continuous Assignment Statement
A continuous assignment statement [Verilog LRM 6.1] assigns a value to a wire in a similar way that a real
logic gate drives a real wire,
module assignment_1();
wire pwr_good, pwr_on, pwr_stable; reg Ok, Fire;
assign pwr_stable = Ok & (!Fire);
assign pwr_on = 1;
assign pwr_good = pwr_on & pwr_stable;
initial begin Ok = 0; Fire = 0; #1 Ok = 1; #5 Fire = 1; end
initial begin $monitor("TIME=%0d",$time," ON=",pwr_on, " STABLE=",
pwr_stable," OK=",Ok," FIRE=",Fire," GOOD=",pwr_good);
#10 $finish; end
endmodule
TIME=0 ON=1 STABLE=0 OK=0 FIRE=0 GOOD=0
TIME=1 ON=1 STABLE=1 OK=1 FIRE=0 GOOD=1
TIME=6 ON=1 STABLE=0 OK=1 FIRE=1 GOOD=0
The assignment statement in this next example models a three-state bus:
module assignment_2; reg Enable; wire [31:0] Data;
/* The following single statement is equivalent to a declaration and continuous
assignment. */
wire [31:0] DataBus = Enable ? Data : 32'bz;
assign Data = 32'b10101101101011101111000010100001;
initial begin
$monitor("Enable=%b DataBus=%b ", Enable, DataBus);
Enable = 0; #1; Enable = 1; #1; end
endmodule
Enable = 0 DataBus =zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
Enable = 1 DataBus =10101101101011101111000010100001
11.5.2 Sequential Block
A sequential block [Verilog LRM 9.8] is a group of statements between a begin and an end. We may declare new
variables within a sequential block, but then we must name the block. A sequential block is considered a statement, so
that we may nest sequential blocks.
A sequential block may appear in an always statement [Verilog LRM9.9.2], in which case the block executes
repeatedly. In contrast, an initial statement [Verilog LRM9.9.1] executes only once, so a sequential block within an
initial statement only executes once--at the beginning of a simulation. It does not matter where the initial
statement appears--it still executes first. Here is an example:
module always_1; reg Y, Clk;
always // Statements in an always statement execute repeatedly:
begin: my_block // Start of sequential block.
@(posedge Clk) #5 Y = 1; // At +ve edge set Y=1,
@(posedge Clk) #5 Y = 0; // at the NEXT +ve edge set Y=0.
end // End of sequential block.
always #10 Clk = ~ Clk; // We need a clock.
initial Y = 0; // These initial statements execute
initial Clk = 0; // only once, but first.
initial $monitor("T=%2g",$time," Clk=",Clk," Y=",Y);
initial #70 $finish;
endmodule
T= 0 Clk=0 Y=0
T=10 Clk=1 Y=0
T=15 Clk=1 Y=1
T=20 Clk=0 Y=1
T=30 Clk=1 Y=1
T=35 Clk=1 Y=0
T=40 Clk=0 Y=0
T=50 Clk=1 Y=0
T=55 Clk=1 Y=1
T=60 Clk=0 Y=1
11.5.3 Procedural Assignments
A procedural assignment [Verilog LRM 9.2] is similar to an assignment statement in a computer programming
language such as C. In Verilog the value of an expression on the RHS of an assignment within a procedure (a
procedural assignment) updates a reg (or memory element) on the LHS. In the absence of any timing controls (see
Section 11.6), the reg is updated immediately when the statement executes. The reg holds its value until changed
by another procedural assignment. Here is the BNF definition:
blocking_assignment ::= reg-lvalue = [delay_or_event_control] expression
(Notice this BNF definition is for a blocking assignment--a type of procedural assignment--see Section 11.6.4.) Here
is an example of a procedural assignment (notice that a wire can only appear on the RHS of a procedural
assignment):
module procedural_assign; reg Y, A;
always @(A)
Y = A; // Procedural assignment.
initial begin A=0; #5; A=1; #5; A=0; #5; $finish; end
initial $monitor("T=%2g",$time,,"A=",A,,,"Y=",Y);
endmodule
T= 0 A=0 Y=0
T= 5 A=1 Y=1
T=10 A=0 Y=0
11.6 Timing Controls and Delay
The statements within a sequential block are executed in order, but, in the absence of any delay, they all execute at the same
simulation time--the current time step. In reality there are delays that are modeled using a timing control.
11.6.1 Timing Control
A timing control is either a delay control or an event control [Verilog LRM 9.7]. A delay control delays an assignment by a
specified amount of time. A timescale compiler directive is used to specify the units of time followed by the precision used
to calculate time expressions,
`timescale 1ns/10ps // Units of time are ns. Round times to 10 ps.
Time units may only be s , ns , ps , or fs and the multiplier must be 1, 10, or 100. We can delay an assignment in two
different ways:
● Sample the RHS immediately and then delay the assignment to the LHS.
● Wait for a specified time and then assign the value of the LHS to the RHS.
Here is an example of the first alternative (an intra-assignment delay):
x = #1 y; // intra-assignment delay
The second alternative is delayed assignment:
#1 x = y; // delayed assignment
These two alternatives are not the same. The intra-assignment delay is equivalent to the following code:
begin // Equivalent to intra-assignment delay.
hold = y; // Sample and hold y immediately.
#1; // Delay.
x = hold; // Assignment to x. Overall same as x = #1 y.
end
In contrast, the delayed assignment is equivalent to a delay followed by an assignment as follows:
begin // Equivalent to delayed assignment.
#1; // Delay.
x = y; // Assign y to x. Overall same as #1 x = y.
end
The other type of timing control, an event control, delays an assignment until a specified event occurs. Here is the formal
definition:
event_control ::= @ event_identifier | @ (event_expression)
event_expression ::= expression | event_identifier
| posedge expression | negedge expression
| event_expression or event_expression
(Notice there are two different uses of 'or' in this simplified BNF definition--the last one, in bold, is part of the Verilog
language, a keyword.) A positive edge (denoted by the keyword posedge ) is a transition from '0' to '1' or 'x' , or a
transition from 'x' to '1 '. A negative edge ( negedge ) is a transition from '1' to '0' or 'x' , or a transition from
'x' to '0'. Transitions to or from 'z' do not count. Here are examples of event controls:
module delay_controls; reg X, Y, Clk, Dummy;
always #1 Dummy=!Dummy; // Dummy clock, just for graphics.
// Examples of delay controls:
always begin #25 X=1;#10 X=0;#5; end
// An event control:
always @(posedge Clk) Y=X; // Wait for +ve clock edge.
always #10 Clk = !Clk; // The real clock.
initial begin Clk = 0;
$display("T
Clk X Y");
$monitor("%2g",$time,,,Clk,,,,X,,Y);
$dumpvars;#100 $finish; end
endmodule
T
Clk X Y
0 0
x x
10 1
x x
20 0
x x
25 0
1 x
30 1
1 1
35 1
0 1
40 0
0 1
50 1
0 0
60 0
0 0
65 0
1 0
70 1
1 1
75 1
0 1
80 0
0 1
90 1
0 0
The dummy clock in delay_controls helps in the graphical waveform display of the results (it provides a one-time-tick timing
grid when we zoom in, for example). Figure 11.1 shows the graphical output from the Waves viewer in VeriWell (white is
used to represent the initial unknown values). The assignment statements to 'X' in the always statement repeat (every 25 +
10 + 5 = 40 time ticks).
FIGURE 11.1 Output from the module delay_controls
.
Events can be declared (as named events), triggered, and detected as follows:
module show_event;
reg clock;
event event_1, event_2; // Declare two named events.
always @(posedge clock) -> event_1; // Trigger event_1.
always @ event_1
begin $display("Strike 1!!"); -> event_2; end // Trigger event_2.
always @ event_2 begin $display("Strike 2!!");
$finish; end // Stop on detection of event_2.
always #10 clock = ~ clock; // We need a clock.
initial clock = 0;
endmodule
Strike 1!!
Strike 2!!
11.6.2 Data Slip
Consider this model for a shift register and the simulation output that follows:
module data_slip_1 (); reg Clk, D, Q1, Q2;
/************* bad sequential logic below ***************/
always @(posedge Clk) Q1 = D;
always @(posedge Clk) Q2 = Q1; // Data slips here!
/************* bad sequential logic above ***************/
initial begin Clk = 0; D = 1; end always #50 Clk = ~Clk;
initial begin $display("t
Clk D Q1 Q2");
$monitor("%3g",$time,,Clk,,,,D,,Q1,,,Q2); end
initial #400 $finish; // Run for 8 cycles.
initial $dumpvars;
endmodule
t
Clk D Q1 Q2
0 0
1 x x
50 1
1 1 1
100 0
1 1 1
150 1
1 1 1
200 0
1 1 1
250 1
300 0
350 1
1 1
1 1
1 1
1
1
1
The first clock edge at t = 50 causes Q1 to be updated to the value of D at the clock edge (a '1' ), and at the same time Q2
is updated to this new value of Q1 . The data, D , has passed through both always statements. We call this problem data
slip.
If we include delays in the always statements (labeled 3 and 4) in the preceding example, like this-always @(posedge Clk)
always @(posedge Clk)
Q1 = #1 D; // The delays in the assignments
Q2 = #1 Q1; // fix the data slip.
--we obtain the correct output:
t
0
50
51
100
150
151
200
250
300
350
Clk
0
1
1
0
1
1
0
1
0
1
D
1
1
1
1
1
1
1
1
1
1
Q1
x
x
1
1
1
1
1
1
1
1
Q2
x
x
x
x
x
1
1
1
1
1
11.6.3 Wait Statement
The wait statement [Verilog LRM9.7.5] suspends a procedure until a condition becomes true. There must be another
concurrent procedure that alters the condition (in this case the variable Done --in general the condition is an expression) in
the following wait statement; otherwise we are placed on "infinite hold":
wait (Done) $stop; // Wait until Done = 1 then stop.
Notice that the Verilog wait statement does not look for an event or a change in the condition; instead it is level-sensitive--it
only cares that the condition is true.
module test_dff_wait;
reg D, Clock, Reset; dff_wait u1(D, Q, Clock, Reset);
initial begin D=1; Clock=0;Reset=1'b1; #15 Reset=1'b0; #20 D=0; end
always #10 Clock = !Clock;
initial begin $display("T Clk D Q Reset");
$monitor("%2g",$time,,Clock,,,,D,,Q,,Reset); #50 $finish; end
endmodule
module dff_wait(D, Q, Clock, Reset);
output Q; input D, Clock, Reset; reg Q; wire D;
always @(posedge Clock) if (Reset !== 1) Q = D;
always begin wait (Reset == 1) Q = 0; wait (Reset !== 1); end
endmodule
T Clk D Q Reset
0 0
1 0 1
10 1
1 0 1
15 1
1 0 0
20 0
1 0 0
30 1
1 1 0
35 1
0 1 0
40 0
0 1 0
We must include wait statements in module dff_wait above to wait for both Reset==1 and Reset==0 . If we were to
omit the wait statement for Reset==0 , as in the following code:
module dff_wait(D,Q,Clock,Reset);
output Q; input D,Clock,Reset; reg Q; wire D;
always @(posedge Clock) if (Reset !== 1) Q = D;
// We need another wait statement here or we shall spin forever.
always begin wait (Reset == 1) Q = 0; end
endmodule
the simulator would cycle endlessly, and we would need to press the 'Stop' button or 'CTRL-C' to halt the simulator.
Here is the console window in VeriWell:
C1> .
T Clk D Q Reset
Interrupt at time 0
C1>
<- at this point nothing happens, so press CTRL-C
11.6.4 Blocking and Nonblocking Assignments
If a procedural assignment in a sequential block contains a timing control, then the execution of the following statement is
delayed or blocked. For this reason a procedural assignment statement is also known as a blocking procedural assignment
statement [Verilog LRM 9.2]. We covered this type of statement in Section 11.5.3. The nonblocking procedural
assignment statement allows execution in a sequential block to continue and registers are all updated together at the end of
the current time step. Both types of procedural assignment may contain timing controls. Here is an artificially complicated
example that illustrates the different types of assignment:
module delay;
reg a,b,c,d,e,f,g,bds,bsd;
initial begin
a = 1; b = 0; // No delay control.
#1 b = 1;
// Delayed assignment.
c = #1 1;
// Intra-assignment delay.
#1;
// Delay control.
d = 1;
//
e <= #1 1;
// Intra-assignment delay, nonblocking assignment
#1 f <= 1;
// Delayed nonblocking assignment.
g <= 1;
// Nonblocking assignment.
end
initial begin #1 bds = b; end // Delay then sample (ds).
initial begin bsd = #1 b; end // Sample then delay (sd).
initial begin $display("t a b c d e f g bds bsd");
$monitor("%g",$time,,a,,b,,c,,d,,e,,f,,g,,bds,,,,bsd); end
endmodule
t a b c d e f g bds bsd
0 1 0 x x x x x x
x
1 1 1 x x x x x 1
0
2 1 1 1 x x x x 1
0
3 1 1 1 1 x x x 1
0
4 1 1 1 1 1 1 1 1
0
Many synthesis tools will not allow us to use blocking and nonblocking procedural assignments to the same reg within the
same sequential block.
11.6.5 Procedural Continuous Assignment
A procedural continuous assignment statement [Verilog LRM 9.3] (sometimes called a quasicontinuous assignment
statement) is a special form of the assign statement that we use within a sequential block. For example, the following
flip-flop model assigns to q depending on the clear, clr_, and preset, pre_, inputs (in general it is considered very bad form to
use a trailing underscore to signify active-low signals as I have done to save space; you might use " _n " instead).
module dff_procedural_assign;
reg d,clr_,pre_,clk; wire q; dff_clr_pre dff_1(q,d,clr_,pre_,clk);
always #10 clk = ~clk;
initial begin clk = 0; clr_ = 1; pre_ = 1; d = 1;
#20; d = 0; #20; pre_ = 0; #20; pre_ = 1; #20; clr_ = 0;
#20; clr_ = 1; #20; d = 1; #20; $finish; end
initial begin
$display("T CLK PRE_ CLR_ D Q");
$monitor("%3g",$time,,,clk,,,,pre_,,,,clr_,,,,d,,q); end
endmodule
module dff_clr_pre(q,d,clear_,preset_,clock);
output q; input d,clear_,preset_,clock; reg q;
always @(clear_ or preset_)
if (!clear_) assign q = 0; // active-low clear
else if(!preset_) assign q = 1; // active-low preset
else deassign q;
always @(posedge clock) q = d;
endmodule
T CLK PRE_ CLR_ D Q
0 0
1
1
1 x
10 1
1
1
1 1
20 0
1
1
0 1
30 1
1
1
0 0
40 0
0
1
0 1
50 1
0
1
0 1
60 0
1
1
0 1
70 1
1
1
0 0
80 0
1
0
0 0
90 1
1
0
0 0
100 0
1
1
0 0
110 1
1
1
0 0
120 0
1
1
1 0
130 1
1
1
1 1
We have now seen all of the different forms of Verilog assignment statements. The following skeleton code shows where
each type of statement belongs:
module all_assignments
//... continuous assignments.
always // beginning of procedure
begin // beginning of sequential block
//... blocking procedural assignments.
//... nonblocking procedural assignments.
//... procedural continuous assignments.
end
endmodule
Table 11.4 summarizes the different types of assignments.
TABLE 11.4
Verilog assignment statements.
Nonblocking
procedural
assignment
statement
Procedural
continuous
assignment
statement
inside an always or
initial statement,
task, or function
always or initial
statement, task, or
function
Type of Verilog
assignment
Procedural
Continuous assignment statement assignment
statement
Where it can
occur
outside an always or initial
statement, task, or function
inside an always or
initial statement,
task, or function
Example
wire [31:0] DataBus;
assign DataBus =
Enable ? Data : 32'bz
reg Y;
reg Y;
always
always Y <=
@(posedge
1;
clock) Y = 1;
always
@(Enable)
if(Enable)
assign Q = D;
else deassign
Q;
Valid LHS of
assignment
net
register or memory
element
register or memory
element
net
<expression>
<expression>
<expression>
Valid RHS of
assignment
<expression>
net, reg or memory element
net, reg or memory
element
net, reg or memory
element
net, reg or memory
element
Book
11.5.1
11.5.3
11.6.4
11.6.5
Verilog LRM
6.1
9.2
9.2.2
9.3
11.7 Tasks and Functions
A task [Verilog LRM 10.2] is a type of procedure, called from another procedure. A task has both
inputs and outputs but does not return a value. A task may call other tasks and functions. A
function [Verilog LRM 10.3] is a procedure used in any expression, has at least one input, no
outputs, and returns a single value. A function may not call a task. In Section 11.5 we covered all
of the different Verilog procedures except for tasks and functions. Now that we have covered
timing controls, we can explain the difference between tasks and functions: Tasks may contain
timing controls but functions may not. The following two statements help illustrate the difference
between a function and a task:
Call_A_Task_And_Wait (Input1, Input2, Output);
Result_Immediate = Call_A_Function (All_Inputs);
Functions are useful to model combinational logic (rather like a subroutine):
module F_subset_decode; reg [2:0]A, B, C, D, E, F;
initial begin A = 1; B = 0; D = 2; E = 3;
C = subset_decode(A, B); F = subset_decode(D,E);
$display("A B C D E F"); $display(A,,B,,C,,D,,E,,F); end
function [2:0] subset_decode; input [2:0] a, b;
begin if (a <= b) subset_decode = a; else subset_decode = b; end
endfunction
endmodule
A B C D E F
1 0 0 2 3 2
11.8 Control Statements
In this section we shall discuss the Verilog if , case , loop , disable , fork , and join statements that control the
flow of code execution.
11.8.1 Case and If Statement
An if statement [Verilog LRM 9.4] represents a two-way branch. In the following example, switch has to be true to
execute 'Y = 1' ; otherwise 'Y = 0' is executed:
if(switch) Y = 1; else Y = 0;
The case statement [Verilog LRM 9.5] represents a multiway branch. A controlling expression is matched with case
expressions in each of the case items (or arms) to determine a match,
module test_mux; reg a, b, select; wire out;
mux mux_1(a, b, out, select);
initial begin #2; select = 0; a = 0; b = 1;
#2; select = 1'bx; #2; select = 1'bz; #2; select = 1; end
initial $monitor("T=%2g",$time," Select=",select," Out=",out);
initial #10 $finish;
endmodule
module mux(a, b, mux_output, mux_select); input a, b, mux_select;
output mux_output; reg mux_output;
always begin
case(mux_select)
0: mux_output = a;
1: mux_output = b;
default mux_output = 1'bx; // If select = x or z set output to x.
endcase
#1; // Need some delay, otherwise we'll spin forever.
end
endmodule
T= 0 Select=x Out=x
T= 2 Select=0 Out=x
T= 3 Select=0 Out=0
T= 4 Select=x Out=0
T= 5 Select=x Out=x
T= 6 Select=z Out=x
T= 8 Select=1 Out=x
T= 9 Select=1 Out=1
Notice that the case statement must be inside a sequential block (inside an always statement). Because the case
statement is inside an always statement, it needs some delay; otherwise the simulation runs forever without advancing
simulation time. The casex statement handles both 'z' and 'x' as don't care (so that they match any bit value), the casez
statement handles 'z' bits, and only 'z' bits, as don't care. Bits in case expressions may be set to '?' representing don't
care values, as follows:
casex (instruction_register[31:29])
3b'??1 : add;
3b'?1? : subtract;
3b'1?? : branch;
endcase
11.8.2 Loop Statement
A loop statement [Verilog LRM 9.6] is a for, while, repeat, or forever statement. Here are four examples, one for each
different type of loop statement, each of which performs the same function. The comments with each type of loop statement
illustrate how the controls work:
module loop_1;
integer i; reg [31:0] DataBus; initial DataBus = 0;
initial begin
/************** Insert loop code after here. ******************/
/* for(Execute this assignment once before starting loop; exit loop if this
expression is false; execute this assignment at end of loop before the check for end
of loop.) */
for(i = 0; i <= 15; i = i+1) DataBus[i] = 1;
/*************** Insert loop code before here. ****************/
end
initial begin
$display("DataBus = %b",DataBus);
#2; $display("DataBus = %b",DataBus); $finish;
end
endmodule
Here is the while statement code (to replace line 4 in module loop_1 ):
i = 0;
/* while(Execute next statement while this expression is true.) */
while(i <= 15) begin DataBus[i] = 1; i = i+1; end
Here is the repeat statement code (to replace line 4 in module loop_1 ):
i = 0;
/* repeat(Execute next statement the number of times corresponding to the evaluation
of this expression at the beginning of the loop.) */
repeat(16) begin DataBus[i] = 1; i = i+1; end
Here is the forever statement code (to replace line 4 in module loop_1 ):
i = 0;
/* A forever statement loops continuously. */
forever begin : my_loop
DataBus[i] = 1;
if (i == 15) #1 disable my_loop; // Need to let time advance to exit.
i = i+1;
end
The output for all four forms of looping statement is the same:
DataBus = 00000000000000000000000000000000
DataBus = 00000000000000001111111111111111
11.8.3 Disable
The disable statement [Verilog LRM 11] stops the execution of a labeled sequential block and skips to the end of the block:
forever
begin: microprocessor_block // Labeled sequential block.
@(posedge clock)
if (reset) disable microprocessor_block; // Skip to end of block.
else Execute_code;
end
Use the disable statement with caution in ASIC design. It is difficult to implement directly in hardware.
11.8.4 Fork and Join
The fork statement and join statement [Verilog LRM 9.8.2] allows the execution of two or more parallel threads in a
parallel block:
module fork_1
event eat_breakfast, read_paper;
initial begin
fork
@eat_breakfast; @read_paper;
join
end
endmodule
This is another Verilog language feature that should be used with care in ASIC design, because it is difficult to implement in
hardware.
11.9 Logic-Gate Modeling
Verilog has a set of built-in logic models and you may also define your own models.
11.9.1 Built-in Logic Models
Verilog's built-in logic models are the following primitives [Verilog LRM7]:
● and, nand, nor, or, xor, xnor
You may use these primitives as you use modules. For example:
module primitive;
nand (strong0, strong1) #2.2
Nand_1(n001, n004, n005),
Nand_2(n003, n001, n005, n002);
nand (n006, n005, n002);
endmodule
This module models three NAND gates (Figure 11.2). The first gate (line 3) is a two-input gate
named Nand_1 ; the second gate (line 4) is a three-input gate named Nand_2 ; the third gate
(line 5) is unnamed. The first two gates have strong drive strengths [Verilog LRM3.4] (these
are the defaults anyway) and 2.2 ns delay; the third gate takes the default values for drive
strength (strong) and delay (zero). The first port of a primitive gate is always the output port.
The remaining ports for a primitive gate (any number of them) are the input ports.
FIGURE 11.2 An example schematic (drawn with Capilano's DesignWorks) to illustrate the
use of Verilog primitive gates.
Table 11.5 shows the definition of the and gate primitive (I use lowercase 'and' as the name
of the Verilog primitive, rather than 'AND' , since Verilog is case-sensitive). Notice that if one
input to the primitive 'and' gate is zero, the output is zero, no matter what the other input is.
TABLE 11.5
'and'
Definition of the Verilog primitive 'and' gate.
0
1
x
z
0
0
0
0
0
1
0
1
x
x
x
0
x
x
x
z
0
x
x
x
11.9.2 User-Defined Primitives
We can define primitive gates (a user-defined primitive or UDP) using a truth-table
specification [Verilog LRM8]. The first port of a UDP must be an output port, and this must
be the only o utput port (we may not use vector or inout ports):
primitive Adder(Sum, InA, InB);
output Sum; input Ina, InB;
table
// inputs : output
00 : 0;
01 : 1;
10 : 1;
11 : 0;
endtable
endprimitive
We may only specify the values '0' , '1' , and 'x' as inputs in a UDP truth table. Any
'z' input is treated as an 'x' . If there is no entry in a UDP truth table that exactly matches a
set of inputs, the output is 'x' (unknown).
We can construct a UDP model for sequential logic by including a state in the UDP truth-table
definition. The state goes between an input and an output in the table and the output then
represents the next state. The following sequential UDP model also illustrates the use of
shorthand notation in a UDP truth table:
primitive DLatch(Q, Clock, Data);
output Q; reg Q; input Clock, Data;
table
//inputs : present state : output (next state)
1 0 : ? : 0; // ? represents 0,1, or x (input or present state).
1 1 : b : 1; // b represents 0 or 1 (input or present state).
1 1 : x : 1; // Could have combined this with previous line.
0 ? : ? : -; // - represents no change in an output.
endtable
endprimitive
Be careful not to confuse the '?' in a UDP table (shorthand for '0' , '1' , or 'x' ) with the
'?' in a constant that represents an extension to 'z' (Section 11.2.4) or the '?' in a case
statement that represents don't care values (Section 11.8.1).
For sequential UDP models that need to detect edge transitions on inputs, there is another
special truth-table notation (ab) that represents a change in logic value from a to b . For
example, (01) represents a rising edge. There are also shorthand notations for various edges:
● * is (??)
●
●
●
●
r
f
p
n
is
is
is
is
(01)
(10)
(01), (0x), or (x1)
(10), (1x), or (x0)
primitive DFlipFlop(Q, Clock, Data);
output Q; reg Q; input Clock, Data;
table
//inputs : present state : output (next state)
r
0 : ? : 0 ; // rising edge, next state = output =
r
1 : ? : 1 ; // rising edge, next state = output =
(0x) 0 : 0 : 0 ; // rising edge, next state = output =
(0x) 1 : 1 : 1 ; // rising edge, next state = output =
(?0) ? : ? : - ; // falling edge, no change in output
? (??) : ? : - ; // no clock edge, no change in output
endtable
endprimitive
0
1
0
1
11.10 Modeling Delay
Verilog has a set of built-in methods to define delays. This is very important in ASIC physical
design. Before we start layout, we can use ASIC cell library models written in Verilog that include
logic delays as a function of fanout and estimated wiring loads. After we have completed layout,
we can extract the wiring capacitance, allowing us to calculate the exact delay values. Using the
techniques described in this section, we can then back-annotate our Verilog netlist with postlayout
delays and complete a postlayout simulation.
We can complete this back-annotation process in a standard fashion since delay specification is
part of the Verilog language. This makes working with an ASIC cell library and the ASIC foundry
that will fabricate our ASIC much easier. Typically an ASIC library company might sell us a cell
library complete with Verilog models that include all the minimum, typical, and maximum delays
as well as the different values for rising and falling transitions. The ASIC foundry will provide us
with a delay calculator that calculates the net delays (this is usually proprietary technology) from
the layout. These delays are held in a separate file (the Standard Delay Format, SDF, is widely
used) and then mapped to parameters in the Verilog models. If we complete back-annotation and a
postlayout simulation using an approved cell library, the ASIC foundry will "sign off" on our
design. This is basically a guarantee that our chip will work according to the simulation. This
ability to design sign-off quality ASIC cell libraries is very important in the ASIC design process.
11.10.1 Net and Gate Delay
We saw how to specify a delay control for any statement in Section 11.6. In fact, Verilog allows
us to specify minimum, typical, and maximum values for the delay as follows [Verilog LRM7.15]:
#(1.1:1.3:1.7) assign delay_a = a; // min:typ:max
We can also specify the delay properties of a wire in a similar fashion:
wire #(1.1:1.3:1.7) a_delay; // min:typ:max
We can specify delay in a wire declaration together with a continuous assignment as in the
following example:
wire #(1.1:1.3:1.7) a_delay = a; // min:typ:max
but in this case the delay is associated with the driver and not with the wire .
In Section 11.9.1 we explained that we can specify a delay for a logic primitive. We can also
specify minimum, typical, and maximum delays as well as separate delays for rising and falling
transitions for primitives as follows [Verilog LRM4.3]:
nand #3.0 nd01(c, a, b);
nand #(2.6:3.0:3.4) nd02(d, a, b); // min:typ:max
nand #(2.8:3.2:3.4, 2.6:2.8:2.9) nd03(e, a, b);
// #(rising, falling) delay
The first NAND gate, nd01 , has a delay of 3 ns (assuming we specified nanoseconds as the
timescale) for both rising and falling delays. The NAND gate nd02 has a triplet for the delay; this
corresponds to a minimum (2.6 ns), typical (3.0 ns), and a maximum delay (3.4 ns). The NAND
gate nd03 has two triplets for the delay: The first triplet specifies the min/typ/max rising delay (
'0' or 'x' or 'z' to '1' ), and the second triplet specifies the min/typ/max falling delay (
'1' or 'x' or 'z' to '0' ).
Some primitives can produce a high-impedance output, 'z' . In this case we can specify a triplet
of delay values corresponding to rising transition, falling transition, and the delay to transition to
'z' (from '0' or '1' to 'z' --this is usually the delay for a three-state driver to turn off or
float). We can do the same thing for net types,
wire #(0.5,0.6,0.7) a_z = a; // rise/fall/float delays
11.10.2 Pin-to-Pin Delay
The specify block [Verilog LRM 13] is a special construct in Verilog that allows the definition of
pin-to-pin delays across a module. The use of a specify block can include the use of built-in
system functions to check setup and hold times, for example. The following example illustrates
how to specify pin-to-pin timing for a D flip-flop. We declare the timing parameters first followed
by the paths. This example uses the UDP from Section 11.9.2, which does not include preset and
clear (so only part of the flip-flop function is modeled), but includes the timing for preset and clear
for illustration purposes.
module DFF_Spec; reg D, clk;
DFF_Part DFF1 (Q, clk, D, pre, clr);
initial begin D = 0; clk = 0; #1; clk = 1; end
initial $monitor("T=%2g", $time," clk=", clk," Q=", Q);
endmodule
module DFF_Part(Q, clk, D, pre, clr);
input clk, D, pre, clr; output Q;
DFlipFlop(Q, clk, D); // No preset or clear in this UDP.
specify
specparam
tPLH_clk_Q = 3, tPHL_clk_Q = 2.9,
tPLH_set_Q = 1.2, tPHL_set_Q = 1.1;
(clk => Q) = (tPLH_clk_Q, tPHL_clk_Q);
(pre, clr *> Q) = (tPLH_set_Q, tPHL_set_Q);
endspecify
endmodule
T= 0 clk=0 Q=x
T= 1 clk=1 Q=x
T= 4 clk=1 Q=0
There are the following two ways to specify paths (module DFF_part above uses both) [Verilog
LRM13.3]:
● x => y specifies a parallel connection (or parallel path) between x and y ( x and y must
have the same number of bits).
● x *> y specifies a full connection (or full path) between x and y (every bit in x is
connected to y) . In this case x and y may be different sizes.
The delay of some logic cells depends on the state of the inputs. This can be modeled using a
state-dependent path delay. Here is an example:
`timescale 1 ns / 100 fs
module M_Spec; reg A1, A2, B; M M1 (Z, A1, A2, B);
initial begin A1=0;A2=1;B=1;#5;B=0;#5;A1=1;A2=0;B=1;#5;B=0; end
initial
$monitor("T=%4g",$realtime," A1=",A1," A2=",A2," B=",B," Z=",Z);
endmodule
`timescale 100 ps / 10 fs
module M(Z, A1, A2, B); input A1, A2, B; output Z;
or (Z1, A1, A2); nand (Z, Z1, B); // OAI21
/*A1 A2 B Z Delay=10*100 ps unless indicated in the table below.
0 0 0 1
0 0 1 1
0 1 0 1 B:0->1 Z:1->0 delay=t2
0 1 1 0 B:1->0 Z:0->1 delay=t1
1 0 0 1 B:0->1 Z:1->0 delay=t4
1 0 1 0 B:1->0 Z:0->1 delay=t3
1 1 0 1
1 1 1 0 */
specify specparam t1 = 11, t2 = 12; specparam t3 = 13, t4 = 14;
(A1 => Z) = 10; (A2 => Z) = 10;
if (~A1) (B => Z) = (t1, t2); if (A1) (B => Z) = (t3, t4);
endspecify
endmodule
T=
0 A1=0 A2=1 B=1 Z=x
T=
1 A1=0 A2=1 B=1 Z=0
T=
5 A1=0 A2=1 B=0 Z=0
T= 6.1 A1=0 A2=1 B=0 Z=1
T= 10 A1=1 A2=0 B=1 Z=1
T= 11 A1=1 A2=0 B=1 Z=0
T= 15 A1=1 A2=0 B=0 Z=0
T=16.3 A1=1 A2=0 B=0 Z=1
11.11 Altering Parameters
Here is an example of a module that uses a parameter [Verilog LRM3.10, 12.2]:
module Vector_And(Z, A, B);
parameter CARDINALITY = 1;
input [CARDINALITY-1:0] A, B;
output [CARDINALITY-1:0] Z;
wire [CARDINALITY-1:0] Z = A & B;
endmodule
We can override this parameter when we instantiate the module as follows:
module Four_And_Gates(OutBus, InBusA, InBusB);
input [3:0] InBusA, InBusB; output [3:0] OutBus;
Vector_And #(4) My_AND(OutBus, InBusA, InBusB); // 4 AND gates
endmodule
The parameters of a module have local scope, but we may override them using a defparam
statement and a hierarchical name, as in the following example:
module And_Gates(OutBus, InBusA, InBusB);
parameter WIDTH = 1;
input [WIDTH-1:0] InBusA, InBusB; output [WIDTH-1:0] OutBus;
Vector_And #(WIDTH) My_And(OutBus, InBusA, InBusB);
endmodule
module Super_Size; defparam And_Gates.WIDTH = 4; endmodule
11.12 A Viterbi Decoder
This section describes an ASIC design for a Viterbi decoder using Verilog. Christeen Gray completed the
original design as her MS thesis at the University of Hawaii (UH) working with VLSI Technology, using
the Compass ASIC Synthesizer and a VLSI Technology cell library. The design was mapped from VLSI
Technology design rules to Hewlett-Packard design rules; prototypes were fabricated by Hewlett-Packard
(through Mosis) and tested at UH.
11.12.1 Viterbi Encoder
Viterbi encoding is widely used for satellite and other noisy communications channels. There are two
important components of a channel using Viterbi encoding: the Viterbi encoder (at the transmitter) and
the Viterbi decoder (at the receiver). A Viterbi encoder includes extra information in the transmitted
signal to reduce the probability of errors in the received signal that may be corrupted by noise.
I shall describe an encoder in which every two bits of a data stream are encoded into three bits for
transmission. The ratio of input to output information in an encoder is the rate of the encoder; this is a
rate 2/3 encoder. The following equations relate the three encoder output bits (Yn2 , Yn1 , and Yn0 ) to the
two encoder input bits (Xn2 and Xn1 ) at a time nT:
Yn2 = Xn2
Yn1 = Xn1 xor Xn-21
Yn0 = Xn-11
We can write the input bits as a single number. Thus, for example, if Xn2 = 1 and Xn2 = 0 , we can write
Xn = 2 . Equation 11.1 defines a state machine with two memory elements for the two last input values for
Xn1 : Xn-11 and Xn-21 . These two state variables define four states: {Xn-11, Xn-21 } , with S0 = { 0, 0}, S1
= {1, 0}, S2 = {0, 1}, and S3 = {1, 1}. The 3-bit output Yn is a function of the state and current 2-bit input
Xn .
The following Verilog code describes the rate 2/3 encoder. This model uses two D flip-flops as the state
register. When reset (using active-high input signal res ) the encoder starts in state S0 . In Verilog I
represent Yn2 by Y2N , for example.
/******************************************************/
/* module viterbi_encode
*/
/******************************************************/
/* This is the encoder. X2N (msb) and X1N form the 2-bit input
message, XN. Example: if X2N=1, X1N=0, then XN=2. Y2N (msb), Y1N, and
Y0N form the 3-bit encoded signal, YN (for a total constellation of 8
PSK signals that will be transmitted). The encoder uses a state
machine with four states to generate the 3-bit output, YN, from the
2-bit input, XN. Example: the repeated input sequence XN = (X2N, X1N)
= 0, 1, 2, 3 produces the repeated output sequence YN = (Y2N, Y1N,
Y0N) = 1, 0, 5, 4. */
module viterbi_encode(X2N,X1N,Y2N,Y1N,Y0N,clk,res);
input X2N,X1N,clk,res; output Y2N,Y1N,Y0N;
wire X1N_1,X1N_2,Y2N,Y1N,Y0N;
dff dff_1(X1N,X1N_1,clk,res); dff dff_2(X1N_1,X1N_2,clk,res);
assign Y2N=X2N; assign Y1N=X1N ^ X1N_2; assign Y0N=X1N_1;
endmodule
Figure 11.3 shows the state diagram for this encoder. The first four rows of Table 11.6 show the four
different transitions that can be made from state S0 . For example, if we reset the encoder and the input is
Xn = 3 (Xn2 = 1 and Xn1 = 1), then the output will be Yn = 6 (Yn2 = 1 , Yn1 = 1 , Yn0 = 0 ) and the next
state will be S1 .
FIGURE 11.3 A state diagram for a rate 2/3 Viterbi encoder. The inputs and outputs are shown in
binary as Xn2 Xn1 / Yn2Yn1Yn0 , and in decimal as Xn/ Yn .
TABLE 11.6
State table for the rate 2/3 Viterbi encoder.
Outputs
Inputs
State variables
Yn2
Yn1
Yn0
Next state
Xn2 Xn1
Xn-11
Xn-21
Xn2
= Xn1 xor Xn-21
= Xn-11
{Xn-11, Xn-21}
S0
0
0
0
0
0
0
0
00
S0
S0
0
1
0
0
0
1
0
10
S1
S0
1
0
0
0
1
0
0
00
S0
S0
1
1
0
0
1
1
0
10
S1
S1
0
0
1
0
0
0
1
01
S2
S1
0
1
1
0
0
1
1
11
S3
S1
1
0
1
0
1
0
1
01
S2
S1
1
1
1
0
1
1
1
11
S3
S2
0
0
0
1
0
1
0
00
S0
S2
0
1
0
1
0
0
0
10
S1
S2
1
0
0
1
1
1
0
00
S0
S2
1
1
0
1
1
0
0
10
S1
Present state
S3
0
0
1
1
0
1
1
01
S2
S3
0
1
1
1
0
0
1
11
S3
S3
1
0
1
1
1
1
1
01
S2
S3
1
1
1
1
1
0
1
11
S3
As an example, the repeated encoder input sequence Xn = 0, 1, 2, 3, ... produces the encoder output
sequence Yn = 1, 0, 5, 4, ... repeated. Table 11.7 shows the state transitions for this sequence, including
the initialization steps.
FIGURE 11.4 The signal constellation for an 8 PSK (phase-shift keyed)
code.
TABLE 11.7
A sequence of transmitted signals for the rate 2/3 Viterbi encoder
Time Inputs
State variables
Outputs
Present state
Next state
x
S?
S?
1
0
S0
S1
0
0
1
S1
S2
1
0
0
0
S2
S1
1
0
1
0
1
S1
S2
1
0
1
1
0
0
S2
S1
0
0
1
0
0
0
1
S1
S2
550
0
1
0
1
0
0
0
S2
S1
650
1
0
1
0
1
0
1
S1
S2
750
1
1
0
1
1
0
0
S2
S1
850
0
0
1
0
0
0
1
S1
S2
950
0
1
0
1
0
0
0
S2
S1
ns
Xn2
Xn1
Xn-11 Xn-21
Yn2
Yn1
Yn0
0
1
1
x
x
1
x
10
1
1
0
0
1
50
0
0
1
0
150
0
1
0
250
1
0
350
1
450
Next we transmit the eight possible encoder outputs (Yn = 0-7 ) as signals over our noisy communications
channel (perhaps a microwave signal to a satellite) using the signal constellation shown in Figure 11.4.
Typically this is done using phase-shift keying ( PSK) with each signal position corresponding to a
different phase shift in the transmitted carrier signal.
11.12.2 The Received Signal
The noisy signal enters the receiver. It is now our task to discover which of the eight possible signals were
transmitted at each time step. First we calculate the distance of each received signal from each of the
known eight positions in the signal constellation. Table 11.8 shows the distances between signals in the
8PSK constellation. We are going to assume that there is no noise in the channel to illustrate the operation
of the Viterbi decoder, so that the distances in Table 11.8 represent the possible distance measures of our
received signal from the 8PSK signals.
The distances, X, in the first column of Table 11.8 are the geometric or algebraic distances. We measure
the Euclidean distance, E = X2 shown as B (the binary quantized value of E) in Table 11.8. The
rounding errors that result from conversion to fixed-width binary are quantization errors and are
important in any practical implementation of the Viterbi decoder. The effect of the quantization error is to
add a form of noise to the received signal.
The following code models the receiver section that digitizes the noisy analog received signal and
computes the binary distance measures. Eight binary-distance measures, in0-in7 , are generated each
time a signal is received. Since each of the distance measures is 3 bits wide, there are a total of 24 bits (8
∞ 3) that form the digital inputs to the Viterbi decoder.
TABLE 11.8
Distance measures for Viterbi encoding (8PSK).
Algebraic
Signal distance from
signal 0
Euclidean
X = Distance distance
from signal 0
E = X2
B = binary
quantized
value of E
D=
decimal
value of B
Quantization error
Q = D - 1.75 E
0
2 sin (0 &pi; /
8)
0.00
0.00
000
0
0
1
2 sin (1 &pi; /
8)
0.77
0.59
001
1
-0.0325
2
2 sin (2 &pi; /
8)
1.41
2.00
100
4
0.5
3
2 sin (3 &pi; /
8)
1.85
3.41
110
6
0.0325
4
2 sin (4 &pi; /
8)
2.00
4.00
111
7
0
5
2 sin (5 &pi; /
8)
1.85
3.41
110
6
0.0325
6
2 sin (6 &pi; /
8)
1.41
2.00
100
4
0.5
7
2 sin (7 &pi; /
8)
0.77
0.59
001
1
-0.0325
/******************************************************/
/* module viterbi_distances
*/
/******************************************************/
/* This module simulates the front end of a receiver. Normally the
received analog signal (with noise) is converted into a series of
distance measures from the known eight possible transmitted PSK
signals: s0,...,s7. We are not simulating the analog part or noise in
this version, so we just take the digitally encoded 3-bit signal, Y,
from the encoder and convert it directly to the distance measures.
d[N] is the distance from signal = N to signal = 0
d[N] = (2*sin(N*PI/8))**2 in 3-bit binary (on the scale 2=100)
Example: d[3] = 1.85**2 = 3.41 = 110
inN is the distance from signal = N to encoder signal.
Example: in3 is the distance from signal = 3 to encoder signal.
d[N] is the distance from signal = N to encoder signal = 0.
If encoder signal = J, shift the distances by 8-J positions.
Example: if signal = 2, in0 is d[6], in1 is D[7], in2 is D[0], etc. */
module viterbi_distances
(Y2N,Y1N,Y0N,clk,res,in0,in1,in2,in3,in4,in5,in6,in7);
input clk,res,Y2N,Y1N,Y0N; output in0,in1,in2,in3,in4,in5,in6,in7;
reg [2:0] J,in0,in1,in2,in3,in4,in5,in6,in7; reg [2:0] d [7:0];
initial begin d[0]='b000;d[1]='b001;d[2]='b100;d[3]='b110;
d[4]='b111;d[5]='b110;d[6]='b100;d[7]='b001; end
always @(Y2N or Y1N or Y0N) begin
J[0]=Y0N;J[1]=Y1N;J[2]=Y2N;
J=8-J;in0=d[J];J=J+1;in1=d[J];J=J+1;in2=d[J];J=J+1;in3=d[J];
J=J+1;in4=d[J];J=J+1;in5=d[J];J=J+1;in6=d[J];J=J+1;in7=d[J];
end endmodule
As an example, Table 11.9 shows the distance measures for the transmitted encoder output sequence Yn =
1, 0, 5, 4, ... (repeated) corresponding to an encoder input of Xn = 0, 1, 2, 3, ... (repeated).
TABLE 11.9
Receiver distance measures for an example transmission sequence.
Time Input
Output Yn
Present state
Next state
in0 in1 in2 in3 in4 in5 in6 in7
3
x
S?
S?
x
x
x
x
x
x
x
x
10
3
6
S0
S1
4
6
7
6
4
1
0
1
50
0
1
S1
S2
1
0
1
4
6
7
6
4
150
1
0
S2
S1
0
1
4
6
7
6
4
1
250
2
5
S1
S2
6
7
6
4
1
0
1
4
350
3
4
S2
S1
7
6
4
1
0
1
4
6
450
0
1
S1
S2
1
0
1
4
6
7
6
4
550
1
0
S2
S1
0
1
4
6
7
6
4
1
650
2
5
S1
S2
6
7
6
4
1
0
1
4
750
3
4
S2
S1
7
6
4
1
0
1
4
6
850
0
1
S1
S2
1
0
1
4
6
7
6
4
950
1
0
S2
S1
0
1
4
6
7
6
4
1
ns
Xn
0
11.12.3 Testing the System
Here is a testbench for the entire system: encoder, receiver front end, and decoder:
/*****************************************************/
/* module viterbi_test_CDD
*/
/*****************************************************/
/* This is the top-level module, viterbi_test_CDD, that models the
communications link. It contains three modules: viterbi_encode,
viterbi_distances, and viterbi. There is no analog and no noise in
this version. The 2-bit message, X, is encoded to a 3-bit signal, Y.
In this module the message X is generated using a simple counter.
The digital 3-bit signal Y is transmitted, received with noise as an
analog signal (not modeled here), and converted to a set of eight
3-bit distance measures, in0, ..., in7. The distance measures form
the input to the Viterbi decoder that reconstructs the transmitted
signal Y, with an error signal if the measures are inconsistent.
CDD = counter input, digital transmission, digital reception */
module viterbi_test_CDD;
wire Error;
// decoder out
wire [2:0] Y, Out; // encoder out, decoder out
reg [1:0] X;
// encoder inputs
reg Clk, Res;
// clock and reset
wire [2:0] in0,in1,in2,in3,in4,in5,in6,in7;
always #500 $display("t
Clk X Y Out Error");
initial $monitor("%4g",$time,,Clk,,,,X,,Y,,Out,,,,Error);
initial $dumpvars; initial #3000 $finish;
always #50 Clk = ~Clk; initial begin Clk = 0;
X = 3; // No special reason to start at 3.
#60 Res = 1;#10 Res = 0; end // Hit reset after inputs are stable.
always @(posedge Clk) #1 X = X + 1; // Drive the input with a counter.
viterbi_encode v_1
(X[1],X[0],Y[2],Y[1],Y[0],Clk,Res);