An Overview of the QorIQ T1040 Communications Processor

An Overview of the QorIQ T1040 Communications Processor
An Overview of the QorIQ T1040
Processor
FTF-NET-F0163
Chun Chang | Application Engineer
APR.2014
TM
External Use
Agenda
•
Introduction
− Block
Diagram
− Market
•
Trend
QorIQ T1040 processor features
− Ethernet
Switch
− Serdes
− Clocking
− Power
Management
•
Collaterals
•
Summary
TM
External Use
1
QorIQ T1040 Processor
Power Architecture®
e5500
256 KB
Backside
L2 Cache
32 KB
32 KB
D-Cache
I-Cache
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory Controller
Controller
Memory
Security Fuse Processor
CoreNet™ Coherency Fabric
Security Monitor
PAMU
IFC
DIU
1G 1G 1G 1G
SATA 2.0
8 Port
Switch
SATA 2.0
Buffer
Mgr.
TDM/HDLC
TDM/HDLC
2x USB 2.0 w/PHY
Pattern
Match
Engine
2.0
2xDMA
1G 1G 1G 1G
PCIe
2x I2C
SPI, GPIO
QUICC
Engine
Parse, Classify,
Distribute
PCIe
2x DUART
5.0
(XoR,
CRC)
Queue
Mgr.
PCIe
eSDHC
Security
PCIe
Power Management
Peripheral
Access Mgmt Unit
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
1G 1G 1G 1G
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Enable Convection cooled
system design
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
2
Processor
• 4x e5500, 64b, up to 1.4GHz
• Each with 256KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory Subsystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4x PCIe Gen2 (5Gbps) Controllers
• 2x SATA 2.0, 3Gbps
• 2x USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• Up to 4x 10/100/1000 Ethernet Controllers
• 8-Port Gigabit Ethernet Switch
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation quad-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
QorIQ T1020 Processor
2 CORES
Power Architecture®
e5500
256 KB
Backside
L2 Cache
32 KB
32 KB
D-Cache
I-Cache
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory Controller
Controller
Memory
Security Fuse Processor
CoreNet™ Coherency Fabric
Security Monitor
PAMU
IFC
DIU
8 Port
Switch
Buffer
Mgr. 1G 1G 1G 1G
TDM/HDLC
TDM/HDLC
2x USB 2.0 w/PHY
Pattern
Match
Engine
2.0
SATA 2.0
SPI, GPIO
1G 1G 1G 1G
SATA 2.0
2x I2C
2xDMA
PCIe
Queue
Mgr.
PCIe
2x DUART
5.0
(XoR,
CRC)
QUICC
Engine
Parse, Classify,
Distribute
PCIe
eSDHC
Security
PCIe
Power Management
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
1G 1G 1G 1G
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Enable Convection cooled
system design
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
3
Processor
• 2x e5500, 64b, up to 1.4GHz
• Each with 256KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory Subsystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4 PCIe Gen2 Controllers
• SATA 2.0, 3Gbps
• 2 USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• Up to 4x 10/100/1000 Ethernet Controllers
• 8-Port Gigabit Ethernet Switch
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation dual-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
QorIQ T1042 Processor
Power Architecture®
e5500
256 KB
Backside
L2
Cache
32 KB
D-Cache
32 KB
I-Cache
Security Fuse
Processor
Security Monitor
CoreNet™ Coherency Fabric
PAMU
2x USB 2.0 w/PHY
DIU
1G 1G 1G
8 Port
Switch
Buffer
Mgr. 1G 1G 1G 1G
SATA 2.0
Pattern
Match
Engine
2.0
2xDMA
1G 1G 1G 1G
SATA 2.0
2.5G
2x I2C
SPI, GPIO
QUICC
Engine
Parse, Classify,
Distribute
Queue
Mgr. 2.5G
PCIe
PCIe
5.0
(XoR,
CRC)
PCIe
2x DUART
Security
PCIe
eSDHC
TDM/HDLC
TDM/HDLC
IFC
Power Management
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory
Memory
Controller
Controller
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Target Deep Sleep 150mW
on special Part Numbers
(1/2W AC System)
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
4
Processor
• 4x e5500, 64b, up to 1.4GHz
• Each with 256 KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory Subsystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4 PCIe Gen2 Controllers
• SATA 2.0, 3Gbps
• 2 USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• 5x 10/100/1000 Ethernet Controllers
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation quad-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
QorIQ T1022 Processor
2 CORES
Power Architecture®
e5500
256 KB
Backside
L2
Cache
32 KB
D-Cache
32 KB
I-Cache
Security Fuse
Processor
Security Monitor
CoreNet™ Coherency Fabric
PAMU
2x USB 2.0 w/PHY
DIU
1G 1G 1G
8 Port
Switch
Buffer
Mgr. 1G 1G 1G 1G
SATA 2.0
Pattern
Match
Engine
2.0
2xDMA
1G 1G 1G 1G
SATA 2.0
2.5G
2x I2C
SPI, GPIO
QUICC
Engine
Parse, Classify,
Distribute
Queue
Mgr. 2.5G
PCIe
PCIe
5.0
(XoR,
CRC)
PCIe
2x DUART
Security
PCIe
eSDHC
TDM/HDLC
TDM/HDLC
IFC
Power Management
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory
Memory
Controller
Controller
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Target Deep Sleep 150mW
on special Part Numbers
(1/2W AC System)
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
5
Processor
• 2x e5500, 64b, up to 1.4GHz
• Each with 256 KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory SubSystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4 PCIe Gen2 Controllers
• SATA 2.0, 3Gb/s
• 2 USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• 5x 10/100/1000 Ethernet Controllers
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation dual-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
Performance
QorIQ T Series: One of the Industry’s Most Scalable, PinCompatible Communications Processor Family
- Eight Virtual Cores up to 1.8GHz
T2081
- Quad-Core up to 1.4GHz
- Integrated GbE Switch
T1040
- Quad-Core up to 1.4GHz
T1042
- Dual-Core up to 1.4GHz
- Integrated GbE Switch
T1020
- Dual-Core up to 1.4GHz
Scale from dual, quad to
eight virtual cores with
QorIQ T1/T2 devices
T1022
Power
TM
External Use
6
Personality Comparison Chart
CPU
L2 Cache
Platform Cache
DDR I/F
Type/Width
10/100/1000
Ethernet (with
IEEE1588v2)
P1020,
P1011,
P1021,
P1012
P1022,
P1013
T1020
T1022
T1040
T1042
T2081
1 to 2 x e500
1 to 2 x
e500
2 x e5500
2 x e5500
4 x e5500
4 x e5500
4 x e6500/8
threads
Up to 800MHz
Up to
1200MHz
12001400MHz
1200-1400MHz
1500 1800MHz
32K I/D
32K I/D
256KB
256KB
32K I/D
256KB/Core
32K I/D
256KB/Core
32K I/D
256KB/Core
32K I/D
256KB/Core
32K I/D
2MB shared
256KB
256KB
256KB
256KB
512KB
DDR2/3
DDR2/3
DDR3L/4
DDR3L/4
DDR3L/4
DDR3L/4
DDR3/3L
16/32-bit ,
800MHz
32/64-bit,
800MHz
32/64-bit,
1600MT/s
32/64-bit,
1600MT/s
32/64-bit,
1600MT/s
32/64-bit,
1600MT/s
32/64-bit,
2133MT/s
2x 2.5
+
5 x 10/100/1000
4x
10/100/1000
2x 2.5
+
5 x 10/100/1000
2x 2.5/10G
+
6x 1G
No
8-Port GE
Switch
No
No
Yes
Yes
Yes
No
3x
2x
4x
10/100/1000 10/100/1000 10/100/1000
Ethernet Switch
--
--
Yes
Yes
In P1021/12
No
SERDES
4 lanes
6 lanes
PCI-Exp
2 (Gen-1)
3 (Gen-1)
TDM
QUICC Engine
Package
8-Port GE
Switch
Yes
TDM and
HDLC
1200-1400MHz 1200-1400MHz
TDM and HDLC TDM and HDLC TDM and HDLC
8 lanes(5GHz) 8 lanes(5GHz)
4 (Gen-2)
4 (Gen-2)
8 lanes(5GHz)
8 lanes(5GHz)
8
lanes(10GHz)
4 (Gen-2)
4 (Gen-2)
3 (Gen2) and
1 (Gen3)
Pin Compatible
TM
External Use
7
No
Personality Comparison Chart
P1020,
P1011,
P1021,
P1012
P1022,
P1013
T1020
T1022
T1040
T1042
T2081
DIU
--
Yes
Yes
Yes
Yes
Yes
No
SATA
--
2 controller
2 controller
2 controller
2 controller
2 controller
No
1.5 or 3Gbaud
1.5 or 3Gbaud
1.5 or 3Gbaud
No
USB2.0
1.5 or 3Gbaud
2 ULPI
controllers
1.5 or 3Gbaud
2 ULPI
controllers
2 with PHY
2 with PHY
2 with PHY
2 with PHY
2 with PHY
Memory Card
SD/MMC
SD/MMC
Accelerators
SEC3.3
Power
Management
Power
Management
SEC3.3
SD/MMC/SDXC SD/MMC/SDXC SD/MMC/SDXC SD/MMC/SDXC SD/MMC/SDXC
DPAA, PME
SEC5.0 with
Trust
Architecture
DPAA, PME
SEC5.0 with
Trust
Architecture
DPAA, PME
SEC5.0 with
Trust
Architecture
DPAA, PME
SEC5.0 with
Trust
Architecture
Power
Power
Power
Power
Power
Management
Management
Management
Management
Management
with Deep sleep with Deep sleep with Deep sleep with Deep sleep with Deep sleep
Package
Pin Compatible
TM
External Use
8
DPAA, PME,
DCE, SEC5.2
with Trust
Architecture
Power
Management
QorIQ T1 Family Features & Benefits
Features
Benefits
Scalable Performance
Pin compatible dual core to eight virtual cores
Future Proofing
Upgrade to higher performance as needed
>2x-4x the performance of existing P1 series
Gigabit Ethernet Switch
Integrated Gigabit Ethernet Switch
Lowers System Cost/Simplifies design
Eliminates cost of external GE switch
Simplifies HW and SW implementation
Reduces overall system power
Accelerators
DPAA - Classification, Traffic Management
Pattern Matching
Security
Enforce SLAs/Reduce CPU cycles
Manage traffic guarantees to enforce SLAs
Security policies based on application/services
High performance HW based encryption
VortiQa Security Appliance S/W and AppID
Hardware Assisted Virtualization
Hypervisor level
I/O MMU – controls memory I/Os can access
Support for Topaz, KVM, Linux Containers,
Higher performance (Vs. software emulation)
Enables virtualization layer to enforce system security
Simplifies I/O virtualization and sharing
Flexibility to use multiple options to meet system needs
Support for S/W Hypervisor, KVM and Linux Containers
Power Management
Best performance per watt
Deep Sleep – proxy for sleeping hosts
Enables ½ Watt AC
Green Energy Efficient System Designs
Optimized for best performance and power
Enables Compliance with Energy Consumption standards
(ECC, EnergyStar, ECMA 393)
Power Management software as part of SDK
TM
External Use
9
QorIQ T1040 Software & Tools at a Glance
•
Two Reference Design Boards
− T1040RDB
− T1042RDB
•
Software Support
− Yocto
based SDK
− SDK support includes
 Legacy
features (refer SDK 1.4 release notes)
 New features
 FMAN and QE microcode
 Linux based QE drivers for TDM, UART and HDLC
•
QorIQ Configuration Suite
• Code Warrior based debugger, flash programmer
TM
External Use
10
QorIQ T1040RDB System
TM
External Use
11
QorIQ T1042RDB Block Diagram
por config
Single Oscillator
Source Clocking
Battery Backed
RTC
DDR
1333MT/s DDR3L 64bit 4GB
IFC
64MB
NOR
128MB
NOR& &NAND
1GB NAND
I2C
EEPROM
PCIe
GE
RS232
Serial
RJ45
QorIQ
T1042
SATA
GE
DUART
SPI
COP
SDXC
DIU
RGMII
RGMII
Realtek PHY
Realtek PHY
DVI XCVR
EEPROM
x1
JTAG
SDXC Card
TM
External Use
12
PCIe x4
SATA
x4
Mini PCIe
USB2.0
Mini PCIe
USB TypeA x 2
RJ45
x1
USB2.0
RJ45
RJ45
HD LCD
QorIQ T1040RDB Block Diagram
POR cfg.
4x FXS/FXO
TDM
EEPROM
IFC
128MB NOR & 1GB NAND
QE
SATA
SATA
PCIe
QorIQ
T1040
RS232
Serial
GE
GE
GE
DUART
EEPROM
SPI
JTAG
COP SDXC
x1
x1
RGMII
RGMII
SGMII
Realtek
Realtek
Realtek
RJ45
RJ45
RJ45
QSGMII
Vitesse
QSGMII
Vitesse
RJ45
RJ45
RJ45
RJ45
RJ45
RJ45
RJ45
RJ45
SDXC Card
TM
External Use
13
PCIe x1
USB2.0
Mini PCIe
x1
USB2.0
USB TypeA x 2
RJ45
1600MT/s DDR3L/72bit 4GB
I2C
T1/E1
RJ45
DDR
Mini PCIe
QE connector
for PMC plugin card.
Clocking
QorIQ T10xx Product Kit Options
Integrated Gigabit Ethernet Switch
And bundled 2x QUAD PHYs
T1040
Quad-Core
8-Port GE
Switch
T1020
Dual-Core
8-Port GE
Switch
QSGMII
QSGMII
QSGMII
QSGMII
TM
External Use
14
Without Gigabit Switch
F104
Quad
PHY
F104
Quad
PHY
T1042
Quad-Core
F104
Quad
PHY
F104
Quad
PHY
T1022
Dual-Core
Pin Multiplexing
RGMII
MI
1588
RGMII
USB:PHY
USB:PHY
LVDD
MII
L1VDD
OVDD
LVDD
CVDD
DVDD
T1040
O1VDD/
OVDD
CVDD
EVDD
eSDHC
System
SPI
Local Bus
TDM
G1VDD
DVDD
QE
DMA
I2C
IRQ
UART
DDR
•
O1VDD/OVDD (1.8V)
•
CVDD (3.3V/1.8V)
•
L1VDD (3.3V/ 2.5V)
•
EVDD (runtime switchable supply 1.8V / 3.3 V)
•
LVDD (2.5 V)
•
G1VDD (1.35V / 1.2V)
•
DVDD (3.3V/2.5V)
TM
External Use
15
Agenda
•
Introduction
− Block
Diagram
− Market
Trend
• QorIQ T1040 processor features
− Ethernet
Switch
− Serdes
− Clocking
− Power
Management
• Collaterals
• Conclusion
TM
External Use
16
QorIQ T1040: Gigabit Ethernet Switch
Priority flow control - lossless
− Lower latency and shared buffer
management
− Advanced classification, shaping
and policing
•
IEEE 1588v2
2.5G
MAC
2.5G
MAC
IEEE 1588v2
1G
MAC
L2- Switch
8K MACs
4K VLANs
1G
MAC
1G
MAC
1G
MAC
SGMII
QSGMII
1G
MAC
SGMII
SGMII
SGMII
SGMII
SGMII
−
•
1G/
2.5G
MAC
RMON
Counters
Through switch integration, low-pin
count QSGMII connectivity and port
count / cost optimization
Increased ROI - Lower TTM and high
re-use
1G
MAC
1G
MAC
1G
MAC
QSGMII
Integrated solution kit with software
reuse potential
Support for Full featured L2 software
stacks
TM
External Use
17
FMan
MACSec
1G/
2.5G
MAC
TCAM 1K
With support for latest standards
including IEEE 802.3az Energy
Efficient Ethernet (EEE)
Cost savings
−
•
Parse, Classify,
Distribute
Power savings
−
•
Management
I/F
Fabric
I/F
4 x SGMII or
Quad
PHY
2 x SGMII or Quad
PHY
5GHz
SERDES
1G MAC
−
BMan
I/F
1G MAC
QMan
I/F
Advanced Features
1G MAC
•
Ethernet Switch Interface with Frame Manager
•
Core
Core
Core
Core
Queues
Frame Manager
2.5GE
2.5GE
1GE
1GE
1GE
Register interface
(in the configuration
space CCSR) for
control packets
8-port
Ethernet switch
Control packets are queued on the
Ethernet Switch CPU-register
interface and can be accessed
(receive and transmit) through any
e5500 core. This space is memory
mapped in T1040 (CCSR space).
x2 QSGMII / x6 SGMII
SerDes x8
TM
External Use
8 L2-switch ports + 3 FMAN ports
• 2 ports of Ethernet switch is
connected to FMAN and operating
2.5 Gbps (aggregating to 5 Gbps)
OR
• 8 L2-switch ports + 4 FMAN ports. 1
port of Ethernet switch is connected
to FMAN @ 2.5 Gbps.
18
QorIQ T104x SERDES
•
QorIQ T104x device supports single 8 lane SerDes.
•
There are two PLL’s in the SerDes.
− PLL1
provides clocking for lanes A:H and Ethernet switch
− PLL2 provides clocking for Lanes C:H
− QoriQ
T104x device supports the following network protocols through
SerDes
 QSGMII
(T1040, T1020 only)
 1000 Base-KX
 SGMII 2.5G (T1042, T1022 only)
 SGMII
TM
External Use
19
Quad Serial Gigabit Media Independent Interface)
•
The QSGMII is a method of combining four SGMII lines into
a 5Gbit/s interface.
• QSGMII uses significantly fewer signal lines than
four SGMII busses
1000BASE-T
100BASE-TX
VSC8574
10BASE-T
Serdes
SFP
SFP
SFP
SFP
Fiber
SFPs
Copper
SFPs
1000BASE-LX
1000BASE-T
1000BASE-SX
10/100/1000BT
100BASE-FX
TM
External Use
20
QorIQ T1040/20 SerDes Lane Multiplexing
With Ethernet switch
SRDS_PRTCL_S1
RCW[128:135]
Lane Lane
A
B
Lane
C
Lane
D
Lane
E
Lane
F
Lane
G
Lane
H
Parallel Port
Availability
69
PCIe1
(5/2.5)
SGMII
(m3)
QSGMII QSGMII
(s1-4)
(s5-8)
PCIe2
(5/2.5)
PCIe3
(5/2.5)
SGMII
(m4)
SATA1
RGMII (FMAN MAC#5)
RGMII (FMAN MAC#2,
MAC#5
66
PCIe1
(5/2.5)
SGMII
(m3)
QSGMII QSGMII
(s1-4)
(s5-8)
PCIe2
(5/2.5)
PCIe3
(5/2.5)
PCIe4
(5/2.5)
SATA1
2 RGMII (FMAN MAC #4
& #5)
67
PCIe1
(5/2.5)
SGMII
(m3)
QSGMII QSGMII
(s1-4)
(s5-8)
PCIe2
(5/2.5)
PCIe3
(5/2.5)
PCIe4
SGMII (m5) 1 RGMII (FMAN MAC #4)
(5/2.5)
60
PCIe1
(5/2.5)
SGMII
(m3)
QSGMII QSGMII
(s1-4)
(s5-8)
8D
PCIe1
(5/2.5)
PCIe1
(5/2.5)
SGMII
(s3)
SGMII
(s3)
89
SGMII
(s1)
SGMII
(s1)
SGMII
(s2)
SGMII
(s2)
2 RGMII (FMAN MAC #4
& #5)
PCIe2 (5/2.5)
PCIe2
(5/2.5)
PCIe2
(5/2.5)
SGMII
(s6)
PCIe3
(5/2.5)
SGMII
(s4)
SGMII
(s4)
SGMII (s5)
2 RGMII (FMAN MAC #4
& #5)
SATA1
2 RGMII (FMAN MAC #4
& #5)
•
Ethernet switch connects with FMAN using MAC#1 and/or MAC#2
• MAC#2 used as additional RGMII port if Ethernet switch connected through MAC#1 only
• MAC#1 and MAC#2 are 2.5G ports.
LEGEND
“mn” indicates MAC# from FMan
“sn” indicates MAC# from Ethernet switch
TM
External Use
21
QorIQ T1042/22 SerDes Lane Multiplexing
Without Ethernet switch
SRDS_PRTCL_S1
RCW[128:135]
Lane
A
Lane
B
Lane
C
Lane
D
Lane
E
Lane
F
Lane
G
Lane
H
86
PCIe1
(5/2.5)
SGMII
(m3)
SGMII
(m1)
SGMII
(m2)
PCIe2
(5/2.5)
PCIe3
(5/2.5)
PCIe4
(5/2.5)
SATA1
87
PCIe1
(5/2.5)
SGMII
(m3)
SGMII
(m1)
SGMII
(m2)
PCIe2
(5/2.5)
PCIe3
(5/2.5)
PCIe4
(5/2.5)
SGMII (m5)
A7
PCIe1
(5/2.5)
SGMII
(m3)
SGMII
SGMII
(m1) 2.5G (m2) 2.5G
PCIe2
(5/2.5)
PCIe3
(5/2.5)
PCIe4
(5/2.5)
SGMII (m5)
1 RGMII
(FMAN MAC #4)
AA
PCIe1
(5/2.5)
SGMII
(m3)
SGMII
SGMII
(m1) 2.5G (m2) 2.5G
PCIe2
(5/2.5)
PCIe3
(5/2.5)
SGMII
(m4)
SGMII (m5)
0 RGMII
2 RGMII
(FMAN MAC #4 & #5)
2 RGMII
(FMAN MAC #4 & #5)
2 RGMII
(FMAN MAC #4 & #5)
40
SGMII
(m1)
PCIe1 (5/2.5)
SGMII
(m2)
PCIe2 (5/2.5)
Parallel Port
availability
2 RGMII
(FMAN MAC #4 & #5)
1 RGMII
(FMAN MAC #4)
06
PCIe1 (5/2.5)
PCIe2
(5/2.5)
PCIe3
(5/2.5)
PCIe4
(5/2.5)
SATA1
08
PCIe1 (5/2.5)
PCIe2
(5/2.5)
PCIe3
(5/2.5)
SATA2
SATA1
SGMII
(m4)
SGMII (m5)
0 RGMII
PCIe2 (5/2.5)
SGMII
(m4)
SGMII (m5)
0 RGMII
PCIe2 (5/2.5)
SGMII
(m4)
SGMII (m5)
0 RGMII
8F
PCIe1
(5/2.5)
SGMII
(m3)
85
PCIe1
(5/2.5)
SGMII
(m3)
A5
PCIe1
(5/2.5)
SGMII
(m3)
00
SGMII
SGMII
(m1)2.5G (m2)2.5G
SGMII
(m1)
SGMII
(m2)
SGMII
SGMII
(m1) 2.5G (m2) 2.5G
PCIe1 (5/2.5)
PCIe2 (5/2.5)
LEGEND
“mn” indicates MAC# from FMan
TM
External Use
22
2 RGMII
(FMAN MAC #4 & #5)
Ethernet Parallel Interfaces on QorIQ T104x Processors
•
2x RGMII or 1x MII interface supported.
• MII/RGMII selection for EC1 via RCW[EC1] field.
• MAC2 or MAC4 selection for EC1 via RCW[MAC2_GMII_SEL] field
• RGMII interface enabled for EC2 via RCW[EC2] field.
RGMII/MII
MAC2
RGMII/MII
MAC3
MAC4
MAC5
TM
External Use
RGMII/MII
MUX
Frame Manager
MAC1
23
EC2
RGMII
EC1
USB PHY
•
Supports Dual on-chip integrated USB PHY
• Supports USB 2.0
• Works on 24MHz clock (non spread spectrum) on the SOC’s
USBCLK pin
• Can also work on an internal reference clock (system clock
at 100MHz) which can be pre divided to obtain 20 MHz
reference clock
TM
External Use
24
DIU
•
QorIQ T1040 has the same DIU programming model as QorIQ
P1022 with the following differences
Feature
P1022 DIU
T1040 DIU
Data Interface
24 bit RGB
12 bit dual data rate RGB
Pin multiplexing
Multiplexed with eLBC
Multiplexed with QUICC
Engine
Platform to pixel clock
frequency ratio
≥3
≥4
Maximum pixel clock
133MHz
150MHz
TM
External Use
25
eSDHC New Features
•
Supports SDXC cards
− Up
•
to 2TB space
Supports cards with UHS-I speed grade
− Ultra
high speed grade
 SDR12,
SDR25, SDR50, SDR104, DDR50
− UHS-I
cards work on 1.8V signaling
− On board dual voltage regulators are needed to support UHS-I cards
because card initialization happens at 3.3V and regular operations happen
at 1.8V
− SD controller provides a signal to control the voltage regulator. The signal is
controlled via SDHC_VS pin
•
•
eMMC 4.5 support (HS200, DDR)
All modes of SD3.0, eMMC 4.4 and eMMC4.5 are supported except 8 bit
DDR for eMMC.
TM
External Use
26
QorIQ T1040 DDR Controller Features
•
Legacy Features:
− Support
for 32/ 64 bit DDR3L and DDR4 SDRAM with ECC
− Chip-Select interleaving support
− Support for unbuffered and registered DIMMs, single-ranked, dualranked, and quad-ranked DIMMs
•
DDR4 Specific Features:
− New
JEDEC POD12 interface standard (1.2V)
− Support for 4 bank groups
− DBI (Data Bus Inversion) feature
− Command Address (CA Parity)
− CRC for data bus
− CAL mode (CS to Command Address Latency)
− Low power auto self-refresh
TM
External Use
27
Core, PAMU, PME for QorIQ T1040 Processors
•
QorIQ T1040 has 64-bit core with backside L2 cache of size 256KB
• e5500 Backside L2 cache can significantly improve performance
− Much
lower L2 latency
− 36-bit physical address support
Core
L2 Latency
Dhrystone DMIPS/MHz
e500v2 (Frontside L2)
23 core cycles
2.4
e5500 (Backside L2)
12 core cycles
3.0
Single PAMU catering to all the I/O’s (PAACT entries are 128)
• Pattern Matching engine (2.2) supports 16,384 patterns as
compared to 32K pattern support in PME 2.0
•
TM
External Use
28
QUICC Engine in QorIQ T1040 Processors
•
•
Supports one uQE block
64MHz SYSCLK support for ProfiBUS
BRG1 BRG3
BRG1
BRG2 BRG4
CLK9
CLK11
CLK10
CLK12/CLK8
BRG2
•
Support for two TDM [TDMA, TDMB]
and two UCC [UCC1, UCC3]
BRG3
BRG4
R
X
UCC1
•
Protocols:
−
−
−
−
CLK3
T
X
HDLC, Transparent
Synchronous UART
ProfiBUS
TDM/SI
UCC3
R
X
uQUICC Engine
T
X
RX TX
•
UCC1 signals are multiplexed with
TDMA signals
• UCC3 signals are multiplexed with
TDMB signals
TM
External Use
29
TDM
A1
RX TX
TDM
B1
CLK15
Platform
/2
What is VID?
•
•
•
•
VID is a specific method of selecting
the optimum voltage-level to
guarantee performance and power
targets.
QorIQ device contains fuse block
registers defining required voltage
level. This eFUSE definition is
accessed through the Fuse Status
Register (DCFG_FUSESR).
Customer software will read the VID
value from factory-set efuse values
and configure regulator values
appropriately.
For T1040, the core VDD/VDDC
value will range from 0.97V to
1.025V in 12.5mV steps
TM
External Use
30
Power Pins
Power Islands on
T1040
VDD
Switchable Core
and Platform
VDDC
Always ON core
and Platform
Supply
USB_SVDD
USB supply
Start up voltage
1.025 ± 30mV
During normal
operation
VID ± 30mV
QorIQ T1040 Clock Signals
Signal
Function
Range
SYSCLK
Single ended primary clock input
64MHz to 133MHz
DIFF_SYSCLK/
DIFF_SYSCLK_B
Differential primary clock input
100MHz
DDRCLK
Reference clock for DDR controller
64MHz to 133MHz
USBCLK
Clock input to the USB PHY’s
24MHz
SD1_REF_CLKn_P/
SD1_REF_CLKn_N
Clock input to High speed Serial
interfaces
100MHz, 125MHz
TM
External Use
31
‘‘Single Oscillator Source ’’ clock Mode
SYSCLK (64-133.33MHz)
SYSTEM
CLOCK
1
On Board
Oscillator
(100MHz)
3 Differential
Outputs
3
POR CONFIG
[cfg_eng_use0]
USB
PHY PLL
Core
PLL
2
DDR
PHY
1.0V
1.0V
RCW[DDR_REFCLK_SEL]
DDR PLL
Platform
PLL
XTAL
SERDES PLL1
SERDES PLL2
TM
External Use
32
LVCMOS
IO
LVDS
LVDS
DIFF_SYSCLK/DIFF_SYSCLK_B
100MHz
1.0V
MUX
OSC
64 - 133.33 MHz
DDRCLK
Multiple reference clock mode (Legacy mode)
64MHz -133MHz
Oscillator
64MHz -133MHz
Oscillator
DDRCLK
DDR PLL
Platform
PLL
SYSCLK
Core PLL’s
USBCLK
24MHz
Oscillator
25MHz Osc
USB PHY
PLL
SERDES PLL1
(5GHz for PCIe, QSGMII,
SGMII)
PCIe Gen2
compliant
Clock
Generator &
Buffer
SERDES PLL2
(3GHz for SATA,
3.125GHz for SGMII 2.5G)
TM
External Use
33
QorIQ T1040 Power States
e5500 States: Run, Doze and Nap
Each core can independently support each state
Run
Doze
Core
activity
state
CPU Processor
Clocks
State
Snoops
Responded
Interrupts
Responded
PH00
Run
PH10
PH15
On
Yes
Yes
Core clock adaption
can be enabled
Doze
On
Yes
Yes
Core stops dispatching
new instructions
Nap
Off
No
Yes
Flush data cache
before entering
(Except time
base)
Nap
TM
External Use
34
Comments
QorIQ T1040 SoC Power Management States
QorIQ T1040 Device (SoC) states: LPM10, LPM20, LPM35, Deep Sleep
SOC
RCPM
state
Equivalent
P1022 State
Device Clocks
ASLEEP
Asserted
LPM10
---
On
No
Software configured
variant of the ‘full ON’
state where some
cores are placed in a
lower power state
LPM20
Sleep
Cores in Nap,
time base stopped
Yes
Only modules required
for wakeup will have a
running clock.
LPM35
Deep Sleep
Only the blocks in
ON domain have
clock running.
Yes
Only used for entry to
deep sleep
Deep
Sleep
Comments
Power is removed from
a major portion of SOC
TM
External Use
35
QorIQ T1040 Deep Sleep
•
A major portion of the QorIQ T1040 processor is switched OFF including the cores
and DDR Controller.
• Only the blocks needed to detect wakeup and sequence the chip out of deep sleep
are ON.
• QorIQ T1040 responds to incoming wake-up events, from Ethernet interface, USB
or GPIO interrupt, while consuming very little power.
e5500
Core 1 & 2
Ethernet
Switch
e5500
Core 3 & 4
DDR
CoreNet
Rest of the Platform (PME, IFC, QE, eSDHC, SATA, PCIe, `DMA, TDM, Serdes etc.)
COP +
Platform PLL
+ EPU
•
•
•
PIC
Fusebox
GPIO
FMAN
2x USB
(Controller + PHY)
VDD is switchable supply
VDDC is always ON
USB and SEC block can optionally be in ON/OFF domain
TM
External Use
36
QM
BM
SEC
T1040
VDD
VDDC
Clocking in Deep sleep mode (check with Anju)
PLATFORM CLOCK
System Clock
EC1_GTX_CLK125 / MII_CRS
Clock Doubler
250 MHz
FMan core
clock during
deep sleep
+
Duty cycle
Reshaper
EC2_GTX_CLK125
SCFG_EMIIOCR
[GTXCLKSEL]
•
•
•
•
MAC 1
125MHz
Duty cycle
corrected
clock
RGMII1 TX CLK
FMAN
125MHz
MAC 2
RGMII2 TX CLK
SCFG_FMCLKDPSLPCR
[CLKCTRL]
Deep Sleep operation switches platform clock to system reference clock
Frame Manager is ON during Deep sleep for Auto response.
Frame Manager is clocked with 2* 125MHz RGMII_GTXCLK from PHY
MII mode requires Frame Manager to be clocked with System clock
TM
External Use
37
QorIQ T1040 Deep Sleep
HW-SW Seq of QM/BM
DDR Memory
Linux on e5500
DHCP
User
App
256 KB
Back
side
L2 Cache
User-space
Kernel
Linux
PM
core
Network Stack
ARP
NetBIOS
ND
PCIe
Driver
IGMP
Power
Architecture®
e5500
32 KB
D-Cache
32 KB
I-Cache
SFP
Power Mgt
eSDHC
Ethernet Driver
AR Config API
2x DUART
DPAA
2x USB 2.0
DIU
QM
/
BM
FM Eth Port
Auto-Response ucode
Classifier
TM
External Use
38
Peripheral Access
Mgmt Unit
PAMU
Sec
5.x
Queue
Mgr.
(XoR,
CRC)
2x I2C
SPI, GPIO
256KB
Platform
Cache
CoreNet Coherency Fabric
Security Monitor
16b IFC
AR Control
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory
Memory
Controller
Controller
P
M
E
2.0
2xDMA
1G1G1G
8 Port
Buffer
Mgr.
QUICC
Engine
PCD
8-Lane 5GHz
SERDES
TDM/HDLC
TDM/HDLC
SNMP
PCIe
PCIe
PCIe
PCIe
SATA 2.0
SATA 2.0
User
App
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
QorIQ T1040 Deep Sleep Auto-response and wakeup
DDR Memory
Linux on e5500
DHCP
User
App
256 KB
Back
side
L2 Cache
User-space
Kernel
Linux
PM
core
Network Stack
ARP
NetBIOS
ND
PCIe
Driver
IGMP
Power
Architecture®
e5500
32 KB
D-Cache
SFP
32 KB
I-Cache
Power Mgt
eSDHC
Ethernet Driver
AR Config API
2x DUART
DPAA
2x USB 2.0
DIU
QM
/
BM
FM Eth Port
Sec
Queue
Mgr.
(XoR,
2xDMA
1G1G1G
CRC)
P
M
E
2.0
8 Port
Buffer
Mgr.
8-Lane 5GHz
SERDES
Classifier
Session Request
Ping/ARP/IGMP Packet
External Use
39
QUICC
Engine
PCD
5.x
Auto-Response ucode
TM
Peripheral Access
Mgmt Unit
PAMU
2x I2C
SPI, GPIO
256KB
Platform
Cache
CoreNet Coherency Fabric
Security Monitor
16b IFC
AR Control
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory
Memory
Controller
Controller
TDM/HDLC
TDM/HDLC
SNMP
PCIe
PCIe
PCIe
PCIe
SATA 2.0
SATA 2.0
User
App
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
Deep sleep related
•
•
•
•
•
•
•
VDD and VDDC can be powered through separate regulators
VDDC should ramp before/along with VDD
Lossless mode supported for RGMII
FMAN works on SYSCLK for MII mode and may not be lossless
EVT_B2 aka power enable, should not be sampled when
PORESET_B is asserted. There should be an on board pull up on
this signal.
USB and SEC block can optionally be switched ON/OFF in deep
sleep, board level considerations required
EPU and NPC resources are not available as Debug
SDHC related
•
RCW loading from SD interface using voltage translators is
not supported
TM
External Use
40
Agenda
•
Introduction
− Block
Diagram
− Market
Trend
• QorIQ T1040 processor features
− Ethernet
Switch
− Serdes
− Clocking
− Power
Management
• Collaterals
• Conclusion
TM
External Use
41
Collaterals / Documentation
•
On the Core:
− e5500
•
core Reference Manual (Rev4 , 2013)
On the SoC device:
− QorIQ
T104x Processor Fact-sheet and Product brief
− HW Spec Rev D
− Reference Manual Rev B
− Advanced Debug and Performance Monitoring Reference Manual
− QEIWRM
− Errata-sheet Rev A
− Application Notes
 AN4773
- Migration Guide from T2081 to T1040
TM
External Use
42
Agenda
•
Introduction
− Block
Diagram
− Market
Trend
• QorIQ T1040 processor features
− Ethernet
Switch
− Serdes
− Clocking
− Power
Management
• Collaterals
• Summary
TM
External Use
43
QorIQ T1 and T2 Families Extend Market Leadership
•
First 64-bit embedded processor with an
integrated GbE switch
− Reduces
system cost, design complexity
and power
•
One of the industry’s most scalable, pincompatible family of devices
− Performance
scalability with a common
architecture
•
Energy efficiency and low power
− Designed
to be compliant to European Code of
Conduct, and EnergyStar energy consumption
standards
•
Ideal for low- to mid-range networking and
industrial connectivity applications
TM
External Use
44
QorIQ Processors:
Accelerating the
Network’s IQ
Freescale’s Comprehensive Ecosystem
Tools and
Operating Systems
Virtualization
TM
External Use
45
Application
Software
Systems
Integration & Services
Development
Systems
Introducing The
QorIQ LS2 Family
Breakthrough,
software-defined
approach to advance
the world’s new
virtualized networks
New, high-performance architecture built with ease-of-use in mind
Groundbreaking, flexible architecture that abstracts hardware complexity and
enables customers to focus their resources on innovation at the application level
Optimized for software-defined networking applications
Balanced integration of CPU performance with network I/O and C-programmable
datapath acceleration that is right-sized (power/performance/cost) to deliver
advanced SoC technology for the SDN era
Extending the industry’s broadest portfolio of 64-bit multicore SoCs
Built on the ARM® Cortex®-A57 architecture with integrated L2 switch enabling
interconnect and peripherals to provide a complete system-on-chip solution
TM
External Use
46
QorIQ LS2 Family
Key Features
High performance cores with leading
interconnect and memory bandwidth
•
SDN/NFV
Switching
•
•
8x ARM Cortex-A57 cores, 2.0GHz, 4MB L2
cache, w Neon SIMD
1MB L3 platform cache w/ECC
2x 64b DDR4 up to 2.4GT/s
A high performance datapath designed
with software developers in mind
Data
Center
•
•
Wireless
Access
•
New datapath hardware and abstracted
acceleration that is called via standard Linux
objects
40 Gbps Packet processing performance with
20Gbps acceleration (crypto, Pattern
Match/RegEx, Data Compression)
Management complex provides all
init/setup/teardown tasks
Leading network I/O integration
Unprecedented performance and
ease of use for smarter, more
capable networks
TM
External Use
47
•
•
•
•
8x1/10GbE + 8x1G, MACSec on up to 4x 1/10GbE
Integrated L2 switching capability for cost savings
4 PCIe Gen3 controllers, 1 with SR-IOV support
2 x SATA 3.0, 2 x USB 3.0 with PHY
See the LS2 Family First in the Tech Lab!
4 new demos built on QorIQ LS2 processors:
Performance Analysis Made Easy
Leave the Packet Processing To Us
Combining Ease of Use with Performance
Tools for Every Step of Your Design
TM
External Use
48
TM
www.Freescale.com
© 2014 Freescale Semiconductor, Inc. | External Use
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement