A 12-W GaN-HEMT Power Amplifier for Ku-Band Satellite

A 12-W GaN-HEMT Power Amplifier for Ku-Band Satellite
A 12-W GaN-HEMT Power Amplifier for Ku-Band
Satellite Communication
Daniel Maassen∗ , Felix Rautschke∗ , Thomas Huellen‡ , Georg Boeck∗† ,
∗ Microwave
Engineering Laboratory, Berlin Institute of Technology, Berlin, Germany
(FBH), Leibniz-Institut fuer Hoechstfrequenztechnik, Berlin, Germany
‡ GloMic GmbH, Berlin, Germany
Email: daniel.maassen@tu-berlin.de
† Ferdinand-Braun-Institut
Abstract—This paper describes a hybrid microwave integrated
circuit (MIC) power amplifier (PA) covering the extended Kuband uplink (13.75 - 14.5 GHz) for satellite communication. A
high relative permittivity alumina substrate and a 250 nm GaN
bare-die technology have been chosen realizing the amplifier.
The designed PA was characterized in its small- and large-signal
behavior. The measured device performance is about 12 W output
power for a continuous wave (CW) signal with a minimum drain
efficiency of 31 %. Additional modulated measurements state an
average output power of more than 9 W and a peak power of
about 18 W achieving an efficiency of 25 % using a 10 MSym/s
QPSK signal.
Index Terms—Digital video broadcasting, gallium nitride,
HEMTs, microwave circuits, power amplifiers, satellite ground
stations.
I. I NTRODUCTION
Satellite services provide various applications including
telephony, high-speed data communication, satellite news
gathering (SNG) and digital video broadcasting (DVB). Traditional Ku-band satellite communication becomes interesting,
especially for very small aperture terminals (VSAT) used
for time-sensitive and critical communications. GaN-HEMT
technology can play a major role in lowering the costs of block
up-converters (BUC) within VSAT. Modern 250 nm GaN/SiCHEMT device technology is able to achieve high power densities with acceptable high transition frequencies [1]. Research
activities in the Ku-band focus on monolithic microwave
integrated circuits (MMIC) [2], [3]. A hybrid approach for the
PA design using a bare-die as power bar leads to a considerable
cost reduction for the monolithic process technology. There are
two major drawbacks for such a high frequency design. First,
huge parasitics introduced by assembling and the necessity of
bondwires connecting the substrate with the device. Second,
tolerances due to manufacturing constraints which complicate
matching over a certain bandwidth.
In this paper a hybrid Ku-band power amplifier based on
a single GaN bare-die is presented. At the beginning a short
introduction of the technology is given in section II which
contains the bare-die itself as well as the substrate definitions
and manufacturing constraints. The following section III delivers insight into the design of the matching networks and the
implementation of the whole amplifier. Measurement results,
CW and modulated ones, are presented in section IV. The
conclusion is given in section V.
978-1-5090-2214-4/16/$31.00 ©2016 IEEE
II. T ECHNOLOGY
In this work a 250 nm GaN-HEMT bare-die from Wolfspeed
(formerly Cree Inc.), the medium sized device CGHV1J025D,
has been chosen. It is suitable of handling an output power
up to 25 W for a size of only 1.92 mm x 0.8 mm. Input and
output capacitances are stated at CGS = 5.1 pF and CDS = 1.2 pF
respectively for a total gate width of 4.8 mm [4]. The optimum bias point is at VDS = 40 V and IQ = 250 mA with a
breakdown voltage of 100 V. At these operating conditions
the transition frequency is slightly above 40 GHz which makes
the device suitable for a Ku-band PA. A large-signal model
for simulations is provided by the manufacturer. With this
model former load-pull simulations were done using Keysight
ADS. Tab. I gives an impression of the optimum in- and
output-impedances. Matching the device to 50 Ω requires a
transformation ratio of 120:1 and 30:1 respectively.
The bare-die benefits from less parasitics introduced by a
packaged device but causes tolerances due to the necessity of
bondwires. Therefore the matching structures are realized on
one single substrate, in this case a polished alumina (Al2 O3 ),
keeping manufacturing tolerances as low as possible. This substrate features a high relative permittivity of εr = 9.9 which is
necessary for the realization of the extremely low impedances
especially at the input side of the transistor. Furthermore a low
loss tangent of tan δ = 2 · 10−4 and low surface roughness of
Ra = 0.05 µm reduces dielectric and ohmic losses within the
conductive path. For high current handling a conductor height
of 10 µm is chosen. Therefore the conductor width and spacing
is limited to a minimum of 50 µm. The layer stack is composed
of 60 nm NiCr, 80 nm Ti, 200 nm Pd followed by a 9.8 µm gold
plating. By the use of the NiCr layer it is possible realizing
low tolerance thin film resistors on the substrate.
S OURCE -
AND
TABLE I
L OADPULL -S IMULATION
f
GHz
ZS, opt
Ω
ZL, opt
Ω
PAE
%
Pout
dBm
Gain
dB
13.75
14
14.25
14.5
0.42 − j0.58
0.42 − j0.67
0.42 − j0.73
0.43 − j0.80
1.70 + j5.57
1.65 + j5.19
1.61 + j5.09
1.56 + j5.02
46.7
46.4
46.3
45.6
43.1
42.9
42.8
42.6
9.5
9.3
9.3
9.1
Vgs
III. D ESIGN AND I MPLEMENTATION
(b)
0
1.5
40
35
41
4240
1
0.5
35
41
f
(dBm)
PAE (%)
ZS IMN,realized
40
15
20
25
38
30
39
403
42 41
5
40
out
42
40
1
1.5
P
35
0.5
41
0
35
41
42
40
Im{Z} (Ω)
0.5
15
20
2
35
8
309
40
Fig. 2. Realized PA design; (a) schematic; (b) photograph of the Al2 O3
substrate.
2
2.5
Re{Z} (Ω)
3
3.5
4
(a)
1
1.5
2
2.5
Re{Z} (Ω)
40
40
4125
1359
38
0.5
PAE (%)
ZL OMN,realized
42
40 4125
0
Pout (dBm)
41
25
41
42
15
38
40 39
25
41
35 40
38
39
Im{Z} (Ω)
35
40
42
4
f
25
5
4235
5.5
35
41
6
4.5
0.06
50 Ω
9.5 mm
35
Capacitance (pF)
9.5 mm
0.07
50 Ω
15
Measurement
Lumped element model
EM−model
50
(a)
25
0.08
ZS,realized ZL,realized
50
41
403540
39
38
30
25
20
15
The first design step is the analysis of operating conditions
especially the dissipated power (max. 28.8 W) and arising
junction temperature. To provide a best possible heat flow,
the device is mounted using an eutectic die attach procedure
on a CuMoCu flange recommended by the manufacturer. For
further simulations a realistic junction temperature of 80 ◦ C is
assumed for the self-heating large-signal model.
The bias network is realized using the bus-bar concept
[5]. With this method the DC feed is located as close as
possible to the transistor. At this low-impedance plane it is
simple generating an open at the end of the bus-bar using a
high impedance quarter-wavelength line in combination with a
radial stub. Furthermore, the distributed matching method [6]
can guarantee a homogeneous wave at all individual transistor
pads. Afterwards a detailed bondwire analysis is done via
the full 3D-EM solver CST. These results are used in further
simulations realizing the matching network.
After defining the DC feed as well as the bondwire characteristics a lumped element approach is done without considering parasitics for a fast straight forward development. These
structures are transformed into ideal transmission line models,
followed by an accurate 2.5D Momentum simulation. Much
attention was paid to the DC block which is implemented as
interdigital capacitors right in front of the bus-bar. This method
provides a high accuracy and a sufficient large capacitance to
be utilized as DC block as well as matching elements. The
finger width and spacing are set to 50 µm due to manufacturing
constraints. Lumped element models has been developed and
verified by Momentum and CST simulations. Fig. 1 depicts a
comparison between the simulated and measured results for
one input capacitor as well as the behavior of the equivalent model (Fig. 1(b)). The values for the equivalent model
are Cs = 0.06 pF, Cp = 0.11 pF and Ls = 0.14 nH for the finger
length Lf = 0.2 mm and width Wf = 50 µm as well as a distance
Wgap = 50 µm in-between this structure. As can be seen the
Vds
3
3.5
4
(b)
0.05
0
5
10
Frequency (GHz)
15
20
(a)
Ls
Cs
Cp
Cp
(b)
Wgap
Wf
Lf
(c)
Fig. 1. Interdigital capacitor; (a) measured and simulated capacitance; (b)
equivalent model; (c) layout.
Fig. 3. Multi-frequency (a) source- and (b) load-pull contours and simulated impedances of the matching networks at the transistor reference plane
(f = 13.75 - 14.5 GHz).
parallel capacitance is about twice as high as the series one but
this behavior compensates the bondwire inductance. Therefore
the capacitors are utilized as complex matching elements.
Another functionality in relation to the interdigital capacitors
is the small- as well as large-signal stability enhancement
due to its high insertion loss at low frequencies. Furthermore
additional thin film resistors at the DC feed of the gate side are
IV. M EASUREMENTS
Fig. 4. Comparison between small-signal simulation (solid) and measurement
(symbols) results (VDS = 40 V; IQ = 250 mA).
45
Pout (dBm), Gain (dB), PAE & η (%)
implemented to ensure stability. Fig. 2(a) shows an idealized
schematic of the PA including microstrip line based matching
structures, the mentioned capacitors as well as bias tees. This
idealized schematic view is transformed via distributed transmission lines to parallelized lines shown in the photograph of
the realized amplifier (Fig. 2(b)).
Fig. 3 shows simulated multi-frequency source- and loadpull contours and the EM-simulated impedances at the transistor reference plane in the frequency range of 13.75 - 14.5 GHz.
In contradiction to conventional single frequency contours, the
multi-frequency contours are constructed by the least intersection of all single frequency contours within the bandwidth of
operation with the same power or PAE level, respectively. This
simulation results give an impression of the PA performance at
the transistor reference planes. Additional transmission losses
of the designed matching networks will lower the performance
at the 50 Ω reference plane. Furthermore it can be verified,
that all simulated source-/ load-impedances of the matching
networks are located within the the 42 dBm output power and
35 % PAE contours over the frequency band of operation.
Supplying DC is done via an additional test-fixture which is
fabricated on a Rogers RO4003c substrate with a thickness of
203 µm. Furthermore supplementary capacitors and inductors
are soldered on this substrate realizing a more reliable DC
feed. SMA connectors are implemented on the in- and output
side of the test-fixture. The 50 Ω lines on both substrates are
connected via a ribbon bond with an additional compensation
on the laminate for the introduced inductance. The whole
structure is also used as a water cooled heat sink.
40
35
30
25
Pout
20
Gain
PAE
η
15
10
5
Detailed stability analysis was performed at different bias
points with and without applying an input signal. Afterwards
small-signal measurements were done with a PNA N5232A
from Keysight Technologies using GSG-probes. An additional
TRL de-embedding in Matlab was necessary removing the
mismatch losses caused by the probes. As can be seen in
Fig. 4 simulation and measurement fit very well to each other.
The gain is larger than 10 dB within the desired bandwidth,
furthermore a return loss of more than 10 dB is achieved.
A slight shift to lower frequencies which is about 100 MHz
can be noticed. This can be explained by bondwire tolerances
mentioned in III and is proven by a Monte-Carlo simulation.
A more complex measurement setup was necessary for
analyzing the large-signal characteristics of the PA. A preamplifier with a gain of 30 dB and 36 dBm output power is
necessary driving the designed PA into saturation. Low loss
WR-75 directional couplers were used measuring input and
output power simultaneously in an automated measurement
environment. A calibration of the setup guarantees a constant
input power over frequency. A waveguide power load was used
as termination at the output-side of the setup. The large-signal
measurements were done under CW-conditions at the SMA
reference plane of the test-fixture and afterwards de-embedded
to the alumina reference plane.
0
13.5
13.75
14
14.25
Frequency (GHz)
14.5
14.75
Fig. 5. Comparison between measured (symbols) and simulated (solid) largesignal behavior over frequency at Pin = 35 dBm (VDS = 40 V; IQ = 250 mA).
Fig. 5 states a comparison between simulation and measurements at 35 dBm input power over frequency. The output
power results in at least 41 dBm which is more than 12 W
from 13.75 to 14.5 GHz. An efficiency of 31 % with a flat
gain of 6 dB and a resulting PAE of 23 % is achieved. The
gain variance over the frequency range of interest is less
than ± 0.5 dB as well as the output power ripple. Besides of
small deviations between simulated and measured PAE and
drain efficiency results, the graphs show a very satisfactory
agreement. The measured efficiency drop can be explained by
a higher channel temperature of the device than simulated.
It can be assumed that the device is in thermal saturation
for CW operation. This degradation is seriously decreased
in pulsed and modulated operation of the device. A power
sweep at 14.1 GHz with respect to the input power is shown
in Fig. 6. It can be seen that the PA behaves like in simulation.
The constant power and gain compression is typical for GaN
TABLE II
COMPARISON OF STATE OF THE ART
PA S IN THE K U - BAND
fc
FBW
Pout
Gain
PAE
GHz
%
W
dB
%
Total
gate
width
mm
[2] MMIC
[3] MMIC
14.1
14.1
5
5
25 (CW)
20 (CW)
20
10
18
16
9.6
[8] MIC
13.6
3.6
22 (pulse)
7
25
6
This
work
MIC
14.1
14.1
14.1
6
6
6
9 (avg QPSK)
18 (peak QPSK)
≥ 12 (CW)
6
6
6
19
19
23
4.8
4.8
4.8
V. C ONCLUSION
Fig. 6. Comparison between measured (symbols) and simulated (solid) largesignal behavior over Pin at 14.1 GHz (VDS = 40 V; IQ = 250 mA).
40
EVM
ACLR left
ACLR right
η
EVM (%), ACLR (dBc) & η (%)
35
30
25
20
In this paper a hybrid Ku-band PA based on GaN baredie technology has been presented. The PA was designed and
realized on one substrate (Al2 O3 ). The resulting performance
from 13.75 to 14.5 GHz at saturation is about 12 W output
power and 31 % drain efficiency under saturated CW conditions. Furthermore, a peak power value of 18 W and 25 %
efficiency were obtained for a 10 MSym/s QPSK signal. The
results are compared with previously reported PAs in Tab. II.
This work achieves the highest bandwidth and PAE under
CW operation while using the smallest transistor. In pulsed
or modulated operation, similar results as in [8] are achieved
with a much higher bandwidth.
ACKNOWLEDGMENT
15
The author would like to thank GloMic GmbH for continuous interest and advice. This work is financially supported
by the German Space Agency (DLR) under the frame work
of the project ISISTAR (No. 50YB1401).
10
5
0
1
2
3
4
5
6
Pout,avg (W)
7
8
9
Fig. 7. Modulated measurements with 10 MSym/s QPSK at 14.1 GHz
(VDS = 40 V; IQ = 250 mA).
devices operating in high efficiency modes. However, this
behavior can be easily compensated by todays digital and
analog linearizers.
Additional modulated measurements were done with a
10 MSym/s QPSK signal at 0.35 roll-off factor and a resulting
PAPR of 3.9 dB. Fig. 7 shows ACLR, EVM and efficiency vs.
Pout . A strong non-linear behavior can be noticed especially
at saturation. At 9 W average output power an efficiency of
25 % can be obtained. The resulting EVM is about 10 %
with an ACLR of 20 dBc. The measured PAPR is about
2.9 dB achieving a peak power of 18 W. The peak power
measurement results are close to the load-pull simulation
data. By applying pre-distortion techniques as presented in
[7] linearity requirements, e.g. Eutelsat, can be fulfilled.
R EFERENCES
[1] R. S. Pengelly, S. M. Wood, J. W. Milligan, S. T. Sheppard, and W. L. .
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no. 6, pp. 1764–1783, dec. 2012.
[2] CMPA1D1E025F preliminary Datasheet, Wolfspeed, 5 2015, rev. 1.0.
[3] K. Kanaya, S. Kunihiro, M. Koyanagi, H. Koyama, K. Tsujioka, A. Ohta,
A. Inoue, and Y. Hirano, “A Ku-band 20 W GaN-MMIC amplifier with
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[4] “CGHV1J025D datasheet,” Wolfspeed, Durham, USA, vol. 5, 2012.
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[5] S. P. Marsh, “MMIC power splitting and combining techniques,” in Design of RFIC’s and MMIC’s (Ref. No. 1997/391), IEE Tutorial Colloquium
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[6] ——, Practical MMIC Design. Artech House, 2006.
[7] D. Maassen, F. Rautschke, and G. Boeck, “IF Predistortion in the Block
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in Microwave Integrated Circuits Conference (EuMIC), 2015 European,
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[8] W. Luo, X. Chen, L. Pang, T. Yuan, and X. Liu, “A 22W Ku band
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