April 2007

HCPL-3700

AC/DC to Logic Interface Optocoupler

■

■

■

Features

■

■

AC or DC input

Programmable sense voltage

Logic level compatibility

Threshold guaranteed over temperature (0°C to 70°C)

Optoplanar™ construction for high common mode immunity

■

■

UL recognized (file # E90700)

VDE certified – ordering option ‘V’, e.g., HCPL3700V

■

■

■

■

■

Applications

■ Low voltage detection

5 V to 240 V AC/DC voltage sensing

Relay contact monitor

Current sensing

Microprocessor Interface

Industrial controls

Description

The HCPL-3700 voltage/current threshold detection optocoupler consists of an AlGaAs LED connected to a threshold sensing input buffer IC which are optically coupled to a high gain darlington output. The input buffer chip is capable of controlling threshold levels over a wide range of input voltages with a single resistor. The output is TTL and CMOS compatible.

tm

Schematic Package

AC 1

DC+ 2

DC3

AC 4

8 V

CC

7 NC

6 V

O

5 GND

8

1

8

8

1

1

TRUTH TABLE

(Positive Logic)

Input

H

L

Output

L

H

A 0.1 µF bypass capacitor must be connected between pins 8 and 5.

AC/DC

POWER

R

X

HCPL-3700

GND 1

LOGIC

GND 2

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

www.fairchildsemi.com

Absolute Maximum Ratings

(No derating required up to 70°C)

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Parameter Symbol

T

STG

T

OPR

T

SOL

EMITTER

I

IN

Storage Temperature

Operating Temperature

Lead Solder Temperature

Value

-55 to +125

-40 to +85

260 for 10 sec

Units

°C

°C

°C mA

V

IN

P

IN

P

T

DETECTOR

I

O

V

CC

V

O

P

O

Input Current Average

Surge, 3ms, 120Hz Pulse Rate

Transient, 10µs, 120Hz Pulse Rate

Input Voltage (Pins 2-3)

Input Power Dissipation

(1)

Total Package Power Dissipation

(2)

Output Current (Average)

(3)

Supply Voltage (Pins 8-5)

Output Voltage (Pins 6-5)

Output Power Dissipation

(4)

50 (Max.)

140 (Max.)

500 (Max.)

-0.5 (Max.)

230 (Max.)

305 (Max.)

30 (Max.)

-0.5 to 20

-0.5 to 20

210 (Max.)

V mW mW mA

V

V mW

Notes:

1. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C.

2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C.

3. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.

4. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol

V

CC

T

A f

Parameter

Supply Voltage

Operating Temperature

Operating Frequency

Min.

2

0

0

Max.

18

70

4

Units

V

°C kHz

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

2 www.fairchildsemi.com

Electrical Characteristics

(T

A

= 0°C to 70°C Unless otherwise specified)

Symbol

I

TH+

I

TH-

V

TH+

V

TH-

V

TH+

V

TH-

I

HYS

V

HYS

V

IHC1

V

IHC2

V

IHC3

V

ILC

I

IN

V

D1,2

V

D3,4

V

OL

I

OH

I

CCL

I

CCH

C

IN

Parameter Test Conditions

Input Threshold Current

Input Threshold

Voltage

DC

(Pins 2,3)

AC

(Pins 1,4)

V

IN

= V

TH+

, V

CC

= 4.5 V

V

O

= 0.4 V, I

O

≥ 4.2mA

(5)

V

IN

= V

V

CC

2

– V

3

(Pins 1 & 4 Open)

= 4.5 V, V

O

= 0.4V

(5)

I

O

≥ 4.2mA

V

IN

= V

V

CC

2

- V

3

(Pins 1 & 4 Open)

= 4.5 V, V

O

= 2.4 V

(5)

I

O

≥ 100µA

|V

IN

= V

1

– V

4

| (Pins 2 & 3 Open)

V

CC

= 4.5 V, V

O

I

O

≥ 4.2 mA

= 0.4 V

(5)

|V

IN

= |V

1

- V

4

| (Pins 2 & 3 Open)

V

CC

= 4.5 V, V

O

I

O

≤ 100µA

= 2.4 V

(5)

Hysteresis I

HYS

= I

TH+

– I

TH-

V

HYS

= V

TH+

– V

TH-

Input Clamp Voltage V

IHC1

= V

2

- V

3

, V

3

= GND

I

IN

= 10 mA,

Pins 1 & 4 connected to Pin 3

Input Current

Bridge Diode

Forward Voltage

Logic LOW Output Voltage

Logic HIGH Output Current

Logic LOW Supply Current

Logic HIGH Supply Current

Input Capacitance

V

IHC2

= |V

1

– V

4

|, |I

(Pins 2 & 3 Open)

IN

| = 10mA

V

IHC3

= V

2

– V

3

, V

3

= GND,

I

IN

= 15mA (Pins 1 & 4 Open)

V

ILC

= V

2

– V

3

, V

3

= GND,

I

IN

= -10mA

V

IN

= V

2

– V

3

= 5.0V

(Pins 1 & 4 Open)

I

IN

= 3mA

I

IN

= 3mA

V

CC

= 4.5 V, I

OL

= 4.2mA

(5)

V

OH

= V

CC

= 18V

(5)

V

2

– V

3

= 5.0V, V

O

V

CC

= 5V

= Open,

V

CC

= 18V, V

O

= Open f = 1MHz, V

IN

= 0V

(Pins 2 & 3, Pins 1 & 4 Open)

Min.

Typ.

Max.

Unit

1.96

2.4

3.11

mA

1.00

3.35

1.2

3.8

1.62

4.05

mA

V

2.01

4.23

2.87

5.4

6.1

3.0

2.5

5.0

3.7

1.2

1.3

6.3

7.0

12.5

-0.75

3.7

0.65

0.65

0.04

1.0

0.01

50

2.86

5.50

4.20

6.6

7.3

13.4

4.4

0.4

100

4

4

V

V

V mA

V

V

V

V

V mA

µA pF

V

V

V

µA mA

Note:

5. Logic LOW output level at pin 6 occurs when V

IN

Logic HIGH output level at pin 6 occurs when V

IN

≥

≤

V

TH+

and when V

IN

> V

TH-

once V

IN

exceeds V

TH+

.

V

TH-

and when V

IN

< V

TH+

once V

IN

decreases below V

TH-

.

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

3 www.fairchildsemi.com

Switching Characteristics

(T

A

= 25°C, V

CC

= 5 V Unless otherwise specified)

Symbol AC Characteristics

T

T

PHL

PLH

Propagation Delay Time

(to Output Low Level)

Propagation Delay Time

(to Output High Level) t r t f

Output Rise Time (10–90%)

Output Fall Time (90–10%)

|CM

H

| Common Mode Transient

Immunity (at Output High Level)

|CM

L

| Common Mode Transient

Immunity (at Output Low Level)

Test Conditions

R

L

= 4.7k

Ω, C

L

= 30pF

(6)

R

L

= 4.7k

Ω, C

L

= 30pF

(6)

R

L

= 4.7k

Ω, C

L

= 30pF

R

L

= 4.7k

Ω, C

L

= 30pF

I

IN

= 0 mA, R

V

O min

L

= 4.7k

Ω,

= 2.0 V, V

CM

= 1400V

(7)(8)

I

N

= 3.11mA, R

V

O max

L

= 4.7k

Ω,

= 0.8V, V

CM

= 140V

(7)(8)

Min.

Typ.

Max.

Unit

6.0

15 µs

25.0

45

0.5

4000

600

40 µs

µs

µs

V/µs

V/µs

Package Characteristics

(T

A

= 0°C to 70°C Unless otherwise specified)

Symbol

V

ISO

R

I-O

C

I-O

Characteristics

Withstand Insulation Voltage

Resistance (input to output)

Capacitance (input to output)

Test Conditions

Relative humidity < 50%,

T

A

= 25°C, t = 1 min,

I

I-O

≤ 2µA (9)(10)

V

IO

= 500Vdc

(9) f = 1MHz, V

IO

= 0Vdc

Min.

Typ.

Max.

Unit

2500 V

RMS

10

12

0.6

Ω pF

Notes:

6. T

PHL

propagation delay is measured from the 2.5V level of the leading edge of a 5.0V input pulse (1µs rise time) to the 1.5 V level on the leading edge of the output pulse. T

PLH

propagation delay is measured on the trailing edges of the input and output pulse. (Refer to Fig. 9)

7.

Common mode transient immunity in logic high level is the maximum tolerable (positive) dV cm

/dt on the leading edge of the common mode pulse signal V

CM

, to assure that the output will remain in a logic high state (i.e., V

O

>

2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dV cm

/dt on the trailing edge of the common mode pulse signal, V

CM

, to assure that the output will remain in a logic low state

(i.e., V

O

< 0.8 V). Refer to Fig. 10.

8.

In applications where dV cm

/dt may exceed 50,000 V/µs (Such as static discharge), a series resistor, R

CC

, should be included to protect the detector chip from destructive surge currents. The recommended value for

R

CC

is 240V per volt of allowable drop in V

CC

(between pin 8 and V

CC

) with a minimum value of 240 Ω.

9.

Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.

10. The 2500 V

RMS

/1 min. capability is validated by a 3.0 kV

RMS

/1 sec. dielectric voltage withstand test.

11. AC voltage is instantaneous voltage for V

TH+

& V

TH-

.

12. All typicals at T

A

= 25°C, V

CC

= 5V unless otherwise specified.

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

4 www.fairchildsemi.com

Typical Performance Curves

Fig. 1 Logic Low Supply Current vs. Operating Supply Voltage

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4 20 6 8 10 12 14 16

V

CC

- OPERATING SUPPLY VOLTAGE (V)

18

4.2

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

-40

Fig. 3 Input Current/Low Level Output Voltage vs. Temperature

-20

I

V

IN

IN

= 5.0 V

(PINS 2 and 3)

V

CC

= 5.0 V

I

V

OL

V

CC

= 5.0 V

OL

= 4.2 mA

65 0 25 45

T

A

- TEMPERATURE (°C)

120

110

100

90

80

70

30

20

10

85

0

60

50

40

Fig. 5 Propagation Delay vs. Temperature

70

60

50

40

30

20

10

0

-60

TPLH

TPHL

-40 -20 0 20 40

T

A

- TEMPERATURE (°C)

60 80 100

Fig. 2 Input Current vs. Input Voltage

20

15

10

5

0

-5

-10

0

50

45 DC (Pins 1,2 shorted together pins 3,4 shorted together)

40

35

30

25

2

DC (Pins 1 & 4 Open)

AC (pins 2 & 3 Open)

4 6 8

V

IN

- INPUT VOLTAGE (V)

10 12 14

4.2

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

-40

Fig. 4 Current Threshold/Voltage Threshold

vs. Temperature

-20

V TH +

I TH +

V TH -

I TH -

65 0 25 45

T

A

- TEMPERATURE (°C)

1.8

1.6

1.4

1.2

1.0

85

0.8

2.6

2.4

2.2

2.0

3.2

3.0

2.8

Fig. 6 Rise and Fall Time vs. Temperature

100

90

80

70

60

50

40

30

20

10

0

-40 -20

Tf

Tr

0 25 45

T

A

- TEMPERATURE (°C)

65

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

85

0.0

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

5 www.fairchildsemi.com

1000

100

I

V

CC

V

O

IN

= 18 V

= OPEN

= 0 mA

Fig. 7 Logic High Supply Current vs. Temperature

10

1

-60 -40 -20 0 20 40

T

A

- TEMPERATURE (°C)

60 80 100

200

150

100

50

0

0

300

Fig. 8 External Threshold Characteristics V+/V- vs. Rx

V+ (AC)

V- (AC)

250

V+ (DC)

V- (DC)

40 80 120 160 200

R

X

- EXTERNAL SERIES RESISTOR (K Ω)

240

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

6 www.fairchildsemi.com

Pulse

Generator tr = 5ns

Z = 50 Ω

+5V

1 AC

2 DC+

3 DC-

4 AC

V

CC

8

7

V

O

6

GND 5

.1uf

bypass

R

L

Output

V

IN

Pulse Amplitude = 50 V

Pulse Width = 1 ms f = 100 Hz

T = T = 1.0 µs (10 - 90%)

Input

(V ) t

PHL

Output 90%

10% t r

Fig. 9. Switching Test Circuit

t

PLH

5V

2.5V

0V

10%

90%

1.5 V t f

V

FF

I

IN

A

B

1 AC

2 DC+

3 DC-

V

CC

8

7

V

O

6

4 AC GND 5

+

V

-

CM

Pulse Gen

.1uf

bypass

+5V

R

L

Output

V

CM

V

O

* SEE NOTE 8

Switching Pos. (A)

V

CM

H

V

CM

L

5V

5V CM

H

Switching Pos. (B)

AND STRAY WIRING CAPACITANCE

V

O

V

OL CM

L

Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

7 www.fairchildsemi.com

Package Dimensions

Through Hole

PIN 1

ID.

4 3 2 1

0.270 (6.86)

0.250 (6.35)

5 6 7 8

0.200 (5.08)

0.140 (3.55)

0.390 (9.91)

0.370 (9.40)

0.070 (1.78)

0.045 (1.14)

0.020 (0.51) MIN

0.022 (0.56)

0.016 (0.41)

0.154 (3.90)

0.120 (3.05)

0.016 (0.40)

0.008 (0.20)

0.100 (2.54) TYP

15° MAX

0.300 (7.62)

TYP

Surface Mount

4

0.390 (9.91)

0.370 (9.40)

3 2 1

PIN 1

ID.

0.270 (6.86)

0.250 (6.35)

5 6 7 8

0.070 (1.78)

0.045 (1.14)

0.020 (0.51)

MIN

0.300 (7.62)

TYP

0.016 (0.41)

0.008 (0.20)

0.022 (0.56)

0.016 (0.41)

0.100 (2.54)

TYP

Lead Coplanarity : 0.004 (0.10) MAX

0.045 [1.14]

0.315 (8.00)

MIN

0.405 (10.30)

MIN

Note:

All dimensions are in inches (millimeters)

0.4" Lead Spacing

4 3 2 1

PIN 1

ID.

0.270 (6.86)

0.250 (6.35)

0.200 (5.08)

0.140 (3.55)

5 6 7 8

0.390 (9.91)

0.370 (9.40)

0.070 (1.78)

0.045 (1.14)

0.004 (0.10) MIN

0.022 (0.56)

0.016 (0.41)

0.154 (3.90)

0.120 (3.05)

0.016 (0.40)

0.008 (0.20)

0.100 (2.54) TYP

0° to 15°

0.400 (10.16)

TYP

Recommended Pad Layout for Surface Mount

Leadforms

0.070 (1.78)

0.060 (1.52)

0.415 (10.54)

0.295 (7.49)

0.100 (2.54)

0.030 (0.76)

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

8 www.fairchildsemi.com

Ordering Information

Option

No Suffix

S

SD

W

V

WV

SV

SDV

Example Part Number

HCPL3700

HCPL3700S

HCPL3700SD

HCPL3700W

HCPL3700V

HCPL3700WV

HCPL3700SV

HCPL3700SDV

Description

Shipped in Tubes

Surface Mount Lead Bend

Surface Mount; Tape and Reel

0.4" Lead Spacing

VDE0884

VDE0884; 0.4” Lead Spacing

VDE0884; Surface Mount

VDE0884; Surface Mount; Tape and Reel

Marking Information

V

3700

XX YY T1

1

2

6

3 4 5

Definitions

4

5

6

1

2

3

Fairchild logo

Device number

VDE mark (Note: Only appears on parts ordered with VDE option – See order entry table)

Two digit year code, e.g., ‘07’

Two digit work week ranging from ‘01’ to ‘53’

Assembly package code

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

9 www.fairchildsemi.com

Carrier Tape Specifications

4.90 ±0.20

0.30 ±0.05

13.2 ±0.2

12.0 ±0.1

4.0 ±0.1

4.0 ±0.1

Ø1.55 ±0.05

1.75 ±0.10

7.5 ±0.1

16.0 ±0

10.30 ±0.20

Reflow Profile

0.1 MAX 10.30 ±0.20

User Direction of Feed

300

250

200

150

225

C peak

215 C, 10–30 s

100

50

0

0 0.5

1 1.5

2 2.5

Time (Minute)

3 3.5

4 4.5

C (package surface temperature)

• Time of temperature higher than 183

• One time soldering reflow is recommended

Ø1.6 ±0.1

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

10 www.fairchildsemi.com

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx

®

Across the board. Around the world.™

ActiveArray™

Bottomless™

Build it Now™

CoolFET™

CROSSVOLT™

CTL™

Current Transfer Logic™

DOME™

E

2

CMOS™

EcoSPARK

®

EnSigna™

FACT Quiet Series™

FACT

®

FAST

®

FASTr™

FPS™

FRFET

®

GlobalOptoisolator™

GTO™

HiSeC™

i-Lo™

ImpliedDisconnect™

IntelliMAX™

ISOPLANAR™

MICROCOUPLER™

MicroPak™

MICROWIRE™

Motion-SPM™

MSX™

MSXPro™

OCX™

OCXPro™

OPTOLOGIC

®

OPTOPLANAR

®

PACMAN™

PDP-SPM™

POP™

Power220

®

Power247

®

PowerEdge™

PowerSaver™

PowerTrench

QS™

STEALTH™

SuperFET™

SyncFET™

TCM™

™

®

Programmable Active Droop™

QFET

®

QT Optoelectronics™

Quiet Series™

RapidConfigure™

RapidConnect™

ScalarPump™

SMART START™

SPM

®

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

The Power Franchise

®

TinyBoost™

TinyBuck™

TinyLogic

®

TINYOPTO™

TinyPower™

TinyWire™

TruTranslation™

µSerDes™

UHC

®

UniFET™

VCX™

Wire™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER

ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status

Advance Information Formative or In Design

Preliminary

No Identification Needed

Obsolete

First Production

Full Production

Not In Production

Definition

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.

Rev. I25

©2005 Fairchild Semiconductor Corporation

HCPL-3700 Rev. 1.0.1

11 www.fairchildsemi.com