Multistandard video decoder with adaptive comb filter and

Multistandard video decoder with adaptive comb filter and
INTEGRATED CIRCUITS
yc
-d
z.
co
m
DATA SHEET
w.
SAA7118
Multistandard video decoder with
adaptive comb filter and component
video input
ww
Product specification
Supersedes data of 2004 Mar 04
2004 Jul 22
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
10
BOUNDARY SCAN TEST
1
FEATURES
10.1
10.2
Initialization of boundary scan circuit
Device identification codes
1.1
1.2
1.3
1.4
1.5
11
LIMITING VALUES
12
THERMAL CHARACTERISTICS
13
CHARACTERISTICS
1.6
1.7
1.8
Video acquisition/clock
Video decoder
Component video processing
Video scaler
Vertical Blanking Interval (VBI) data decoder
and slicer
Audio clock generation
Digital I/O interfaces
Miscellaneous
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
Decoder
Component video processing
Decoder output formatter
Scaler
VBI data decoder and capture
(subaddresses 40H to 7FH)
Image port output formatter
(subaddresses 84H to 87H)
Audio clock generation
(subaddresses 30H to 3FH)
8.7
15.4
15.5
15.6
15.7
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Analog terminals
Audio clock signals
Clock and real-time synchronization signals
Interrupt handling
Video expansion port (X port)
Image port (I port)
Host port for 16-bit extension of video data I/O
(H port)
Basic input and output timing diagrams I port
and X port
ww
w.
INPUT/OUTPUT INTERFACES AND PORTS
2004 Jul 22
I2C-BUS DESCRIPTION
I2C-bus format
I2C-bus details
Programming register RGB/Y-PB-PR
component input processing
Interrupt mask registers
Programming register audio clock generation
Programming register VBI data slicer
Programming register interfaces and scaler
part
PROGRAMMING START SET-UP
-d
16
9
9.8
APPLICATION INFORMATION
z.
15.1
15.2
15.3
co
15
yc
8.6
14
m
CONTENTS
2
16.1
16.2
16.3
16.4
16.5
Decoder part
Component video part and interrupt mask
Audio clock generation part
Data slicer and data type control part
Scaler and interfaces
17
PACKAGE OUTLINES
18
SOLDERING
18.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
18.2
18.3
18.4
18.5
19
DATA SHEET STATUS
20
DEFINITIONS
21
DISCLAIMERS
22
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
1
SAA7118
FEATURES
1.1
Video acquisition/clock
m
• Up to sixteen analog CVBS, split as desired (all of the
CVBS inputs optionally can be used to convert e.g.
Vestigial Side Band (VSB) signals)
• Up to four analog component inputs, with embedded or
separate sync, split as desired
1.3
• Four on-chip anti-aliasing filters in front of the
Analog-to-Digital Converters (ADCs)
• Switchable white peak control
• Four 9-bit low noise CMOS ADCs running at twice the
oversampling rate (27 MHz)
• RGB component inputs
• Y-PB-PR component inputs
• Fast blanking between CVBS and synchronous
component inputs
• Digital RGB to Y-CB-CR matrix.
1.4
• Horizontal and vertical downscaling and upscaling to
randomly sized windows
• Horizontal and vertical scaling range: variable zoom to
1⁄ (icon) (it should be noted that the H and V zoom are
64
restricted by the transfer data rates)
• On-chip line-locked clock generation in accordance with
“ITU 601”
• Requires only one crystal (32.11 or 24.576 MHz) for all
standards
1.2
Video decoder
• Anti-alias and accumulating filter for horizontal scaling
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• Horizontal and vertical sync detection.
Video scaler
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• Fully programmable static gain or Automatic Gain
Control (AGC), matching to the particular signal
properties
Component video processing
z.
• Automatic Clamp Control (ACC) for CVBS, Y and C
(or VSB) and component signals
co
• Independent gain and offset adjustment for raw data
path.
• Up to eight analog Y + C inputs, split as desired
• Digital PLL for synchronization and clock generation
from all standards and non-standard video sources e.g.
consumer grade VTR
• Automatic detection of any supported colour standard
w.
• Luminance and chrominance signal processing for
PAL B, G, D, H, I and N, combination PAL N, PAL M,
NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
• Vertical scaling with linear phase interpolation and
accumulating filter for anti-aliasing (6-bit phase
accuracy)
• Horizontal phase correct up and downscaling for
improved signal quality of scaled data, especially for
compression and video phone applications, with 6-bit
phase accuracy (1.2 ns step width)
• Two independent programming sets for scaler part, to
define two ‘ranges’ per field or sequences over frames
• Fieldwise switching between decoder part and
expansion port (X port) input
• Adaptive 2/4-line comb filter for two dimensional
chrominance/luminance separation, also with VTR
signals
• Brightness, contrast and saturation controls for scaled
outputs.
– Increased luminance and chrominance bandwidth for
all PAL and NTSC standards
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1.5
– Reduced cross colour and cross luminance artefacts
Vertical Blanking Interval (VBI) data decoder
and slicer
• Versatile VBI data decoder, slicer, clock regeneration
and byte synchronization e.g. for World Standard
Teletext (WST), North American Broadcast Text System
(NABTS), closed caption, Wide Screen Signalling
(WSS), etc.
• PAL delay line for correcting PAL phase errors
• Brightness Contrast Saturation (BCS) adjustment,
separately for composite and baseband signals
• User programmable sharpness control
• Detection of copy-protected signals according to the
Macrovision(1) standard, indicating level of protection
(1) Macrovision is a registered trademark of the Macrovision
Corporation.
2004 Jul 22
3
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
2
Audio clock generation
• PC-video capture and editing
• Generation of a field-locked audio master clock to
support a constant number of audio clocks per video
field
• Personal video recorders (time shifting)
• Cable, terrestrial, and satellite set-top boxes
• Generation of an audio serial and left/right (channel)
clock signal.
• Internet terminals
• Flat-panel monitors
co
1.7
• DVD recordable players
Digital I/O interfaces
• AV-ready hard-disk drivers
• Real-time signal port (R port), inclusive continuous
line-locked reference clock and real-time status
information supporting RTC level 3.1 (refer to document
“RTC Functional Specification” for details)
– Output from decoder part, real-time and unscaled
– Input to scaler part, e.g. video from MPEG decoder
(extension to 16-bit possible)
• Discontinuous data streams supported
• Video surveillance/security
• Video editing/post production
• Video phones
• Video projectors
• Digital VCRs.
3
The SAA7118 is a video capture device for applications at
the image port of VGA controllers.
Philips X-VIP is a new multistandard comb filter video
decoder chip with additional component processing,
providing high quality, optionally scaled, video.
• 32-word × 4-byte FIFO register for video output data
yc
• 28-word × 4-byte FIFO register for decoded VBI data
output
• Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-CB-CR
output
• Scaled 8-bit luminance only and raw CVBS data output
• Sliced, decoded VBI data output.
w.
Miscellaneous
• Power-on control
• 5 V tolerant digital inputs and I/O ports
• Software controlled power saving standby modes
supported
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• Programming via serial I2C-bus, full read back ability by
an external controller, bit rate up to 400 kbit/s
• Boundary scan test circuit complies with the “IEEE Std.
1149.b1 - 1994”.
2004 Jul 22
GENERAL DESCRIPTION
-d
• Video image port (I port) configurable for 8-bit data
(extension to 16-bit possible) in master mode (own
clock), or slave mode (external clock), with auxiliary
timing and handshake signals
• Digital televisions/scan conversion
z.
• Bidirectional expansion port (X port) with half duplex
functionality (D1), 8-bit Y-CB-CR:
1.8
APPLICATIONS
m
1.6
SAA7118
4
The SAA7118 is a combination of a four-channel analog
preprocessing circuit including source selection,
anti-aliasing filter and ADC with succeeding decimation
filters from 27 to 13.5 MHz data rate. Each preprocessing
channel comes with an automatic clamp and gain control.
The SAA7118 combines a Clock Generation Circuit
(CGC), a digital multistandard decoder containing
two-dimensional chrominance/luminance separation by an
adaptive comb filter and a high performance scaler,
including variable horizontal and vertical up and
downscaling and a brightness, contrast and saturation
control circuit.
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
The SAA7118 also provides a means for capturing the
serially coded data in the vertical blanking interval (VBI
data). Two principal functions are available:
QUICK REFERENCE DATA
SYMBOL
PARAMETER
1. To capture raw video samples, after interpolation to
the required output data rate, via the scaler
co
2. A versatile data slicer (data recovery) unit.
The SAA7118 also incorporates field-locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of synchronization
between video and audio during capture or playback.
z.
All of the ADCs may be used to digitize a VSB signal for
subsequent decoding; a dedicated output port and a
selectable VSB clock input is provided.
The circuit is I2C-bus controlled (full write/read capability
for all programming registers, bit rate up to 400 kbit/s).
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4
m
It is a highly integrated circuit for desktop video and similar
applications. The decoder is based on the principle of
line-locked clock decoding and is able to decode the colour
of PAL, SECAM and NTSC signals into ITU 601
compatible colour component values. The SAA7118
accepts CVBS or S-video (Y/C) as analog inputs from TV
or VCR sources, including weak and distorted signals as
well as baseband component signals Y-PB-PR or RGB. An
expansion port (X port) for digital video (bidirectional half
duplex, D1 compatible) is also supported to connect to
MPEG or a video phone codec. At the so called image port
(I port) the SAA7118 supports 8 or 16-bit wide output data
with auxiliary reference data for interfacing to VGA
controllers.
The target application for the SAA7118 is to capture and
scale video images, to be provided as a digital video
stream through the image port of a VGA controller, for
capture to system memory, or just to provide digital
baseband video to any picture improvement processing.
SAA7118
digital supply voltage
digital core supply voltage
VDDA
analog supply voltage
Tamb
ambient temperature
PA+D
analog and digital power dissipation
yc
VDDD
VDDD(C)
CONDITIONS
Note
note 1
MIN.
TYP.
MAX.
UNIT
3.0
3.3
3.6
V
3.0
3.3
3.6
V
3.1
3.3
3.5
V
0
−
70
°C
−
1.1
1.35
W
5
w.
1. Power dissipation is measured in component mode (four ADCs active) and 8-bit image port output mode, expansion
port is 3-stated.
ORDERING INFORMATION
TYPE
NUMBER
SAA7118E
DESCRIPTION
2004 Jul 22
VERSION
BGA156
plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm
SOT472-1
QFP160
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28 × 28 × 3.4 mm; high stand-off height
SOT322-2
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SAA7118H
NAME
PACKAGE
5
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AI41
AI42
AI43
AI44
AI4D
I2C-BUS REGISTER MAP
and
ADC2
ANALOG3
and
ADC3
ANALOG INPUT CONTROL
ANALOG2
CB
C
CROMINANCE
PROCESSING
CR
COMB FILTER
Y
S
LUMININANCE
PROCESSING
c-
S
Y-CB-CR
Y
RAW
Y-CB-CR
ANALOG4
S
and
S
ADC4
AGND
SAA7118
VBI-DATA SLICER
S
SYNCHRONIZATION
CB-CR
AOUT
AGNDA
dz
POWER-ON CONTROL
POWER SUPPLY
VDDA
RTS0
CRYSTAL
RTCO
RTS1
XTALI
XTALO
X PORT
XRDY
XCLK
XTOUT XPD [7:0]
XDQ
H PORT
XRH
XTRI
XRV
Fig.1 Block diagram.
AUDIO
CLOCK
AMCLK
om
VIDEO/TEXT ARBITER
AMXCLK ALRCLK
HPD [7:0]
ICLK
IDQ
ITRDY
ITRI
BOUNDARY
SCAN
TDO
ASCLK
TRST
TDI
TCK
TMS
MHB724
SAA7118
VDD(xtal) LLC2
VSS(xtal)
VDDD
LLC
VSSD
GPO
IGP1
IGP0
IGPV
IGPH
IPD [7:0]
Product specification
VSSA
VIDEO
CLOCK
.c
TEXT
FIFO
CB-CR
Y-CB-CRS
OUTPUT FORMATTER I PORT
CR
RAW
VIDEO FIFO
COMPONENTS
PROCESSING
HORIZONTAL
FINE (PHASE) SCALING
B
LINE FIFO BUFFER
G
SCALER EVENT CONTROLLER
BCS-SCALER
ADC1
Y
CB
FIR-PREFILTER
PRESCALER
R
VERTICAL SCALING
.y
SECOND TASK I2C-BUS REGISTER MAP SCALER
DECODER OUTPUT CONTROL
and
INT_A
FIRST TASK I2C-BUS REGISTER MAP SCALER
FAST SWITCH DELAY
ANALOG1
SCL
Philips Semiconductors
6
AI31
AI32
AI33
AI34
AI3D
CONTROL
SDA
Multistandard video decoder with adaptive
comb filter and component video input
AI21
AI22
AI23
AI24
AI2D
DNC0 to DNC5
BLOCK DIAGRAM
CE
AD PORT
AI11
AI12
AI13
AI14
AI1D
RES
6
CLKEXT
FSW
ndbook, full pagewidth
2004 Jul 22
ww
w
ADP [8:0]
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
7
SAA7118
PINNING
PIN
TYPE(1)
SYMBOL
DESCRIPTION
DNC6
1
O
do not connect, reserved for future extensions and for testing
AI41
2
B1
I
analog input 41
AGND
3
C2
P
analog ground
VSSA4
4
C1
P
ground for analog inputs AI4x
AI42
5
D2
I
analog input 42
co
B2
m
QFP160 BGA156
6
D3
I
differential input for ADC channel 4 (pins AI41 to AI44)
AI43
7
D1
I
analog input 43
VDDA4
8
D4
P
analog supply voltage for analog inputs AI4x (3.3 V)
VDDA4A
9
E2
P
analog supply voltage for analog inputs AI4x (3.3 V)
AI44
10
E1
I
analog input 44
AI31
11
E3
I
analog input 31
VSSA3
12
E4
P
ground for analog inputs AI3x
AI32
13
F2
I
analog input 32
AI3D
14
F1
I/O
AI33
15
F3
I
VDDA3
16
F4
P
VDDA3A
17
G2
P
AI34
18
G1
I
AI21
19
G4
I
-d
VSSA2
20
H3
P
ground for analog inputs AI2x
AI22
21
G3
I
analog input 22
AI2D
22
H1
I
differential input for ADC channel 2 (pins AI24 to AI21)
AI23
23
H2
I
analog input 23
VDDA2
24
H4
P
analog supply voltage for analog inputs AI2x (3.3 V)
VDDA2A
AI1D
w.
z.
AI4D
AI24
AI11
VSSA1
differential input for ADC channel 3 (pins AI31 to AI34)
analog input 33
analog supply voltage for analog inputs AI3x (3.3 V)
analog supply voltage for analog inputs AI3x (3.3 V)
analog input 34
yc
analog input 21
25
J1
P
analog supply voltage for analog inputs AI2x (3.3 V)
26
J3
I
analog input 24
27
J2
I
analog input 11
28
J4
P
ground for analog inputs AI1x
29
K1
I
analog input 12
30
K3
I
differential input for ADC channel 1 (pins AI14 to AI11)
AI13
31
K2
I
analog input 13
VDDA1
32
K4
P
analog supply voltage for analog inputs AI1x (3.3 V)
VDDA1A
33
L1
P
analog supply voltage for analog inputs AI1x (3.3 V)
AI14
34
L3
I
analog input 14
AGNDA
35
L2
P
analog signal ground
AOUT
36
M1
O
analog test output (do not connect)
VDDA0
37
M3
P
analog supply voltage (3.3 V) for internal clock generation circuit
VSSA0
38
M2
P
ground for internal Clock Generation Circuit (CGC)
ww
AI12
2004 Jul 22
7
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
PIN
SAA7118
TYPE(1)
SYMBOL
DESCRIPTION
m
QFP160 BGA156
39
N1
NC
do not connect, reserved for future extensions and for testing
DNC14
40
N2
I/pu
do not connect, reserved for future extensions and for testing
DNC18
41
P2
I/O
do not connect, reserved for future extensions and for testing
DNC15
42
N3
I/pd
do not connect, reserved for future extensions and for testing
EXMCLR
43
P3
I/pd
external mode clear (with internal pull-down)
CE
44
N4
I/pu
chip enable or reset input (with internal pull-up)
VDDD1
45
M4
P
digital supply voltage 1 (peripheral cells)
LLC
46
P4
O
line-locked system clock output (27 MHz nominal)
VSSD1
47
L4
P
digital ground 1 (peripheral cells)
LLC2
48
N5
O
line-locked 1⁄2 clock output (13.5 MHz nominal)
RES
49
P5
O
reset output (active LOW)
VDDD2
50
M5
P
digital supply voltage 2 (core)
VSSD2
51
L5
P
digital ground 2 (core; substrate connection)
CLKEXT
52
N6
I
external clock input intended for analog-to-digital conversion of VSB
signals (36 MHz)
ADP8
53
P6
O
ADP7
54
M6
O
ADP6
55
L6
O
ADP5
56
N7
O
ADP4
57
P7
O
-d
z.
co
DNC13
ADP3
58
L7
O
MSB − 5 of direct analog-to-digital converted output data (VSB)
VDDD3
59
M8
P
digital supply voltage 3 (peripheral cells)
ADP2
60
M7
O
MSB − 6 of direct analog-to-digital converted output data (VSB)
ADP1
61
P8
ADP0
62
N8
VSSD3
63
L8
64
P9
O/od
65
M9
P
digital supply voltage 4 (core)
66
N9
I
serial clock input (I2C-bus)
digital ground 4 (core)
VDDD4
SCL
VSSD4
MSB − 3 of direct analog-to-digital converted output data (VSB)
yc
MSB − 4 of direct analog-to-digital converted output data (VSB)
O
MSB − 7 of direct analog-to-digital converted output data (VSB)
O
LSB of direct analog-to-digital converted output data (VSB)
P
digital ground 3 (peripheral cells)
67
L9
P
68
P10
I/O/od
ww
SDA
MSB − 1 of direct analog-to-digital converted output data (VSB)
MSB − 2 of direct analog-to-digital converted output data (VSB)
w.
INT_A
MSB of direct analog-to-digital converted output data (VSB)
I2C-bus interrupt flag (LOW if any enabled status bit has changed)
serial data input/output (I2C-bus)
RTS0
69
M10
O
real-time status or sync information, controlled by subaddresses
11H and 12H
RTS1
70
N10
O
real-time status or sync information, controlled by subaddresses
11H and 12H
RTCO
71
L10
AMCLK
72
P11
2004 Jul 22
O/st/pd real-time control output; contains information about actual system clock
frequency, field rate, odd/even sequence, decoder status, subcarrier
frequency and phase and PAL sequence (see document “RTC Functional
Description”, available on request); the RTCO pin is enabled via I2C-bus
bit RTCE; see notes 5, 6 and Table 36
O
audio master clock output, up to 50% of crystal clock
8
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
PIN
SAA7118
TYPE(1)
SYMBOL
DESCRIPTION
m
QFP160 BGA156
VDDD5
73
M11
P
digital supply voltage 5 (peripheral cells)
ASCLK
74
N11
O
audio serial clock output
ALRCLK
75
P12
AMXCLK
76
M12
I
ITRDY
77
N12
I/pu
target ready input for image port data
DNC0
78
P13
I/pu
do not connect, reserved for future extensions and for testing: scan input
DNC16
79
N13
NC
do not connect, reserved for future extensions and for testing
DNC17
80
N14
NC
do not connect, reserved for future extensions and for testing
DNC19
81
−
NC
do not connect, reserved for future extensions and for testing
DNC20
82
−
NC
do not connect, reserved for future extensions and for testing
FSW
83
M13
I/pd
fast switch (blanking) with internal pull-down inserts component inputs into
CVBS signal
ICLK
84
M14
I/O
IDQ
85
L13
O
ITRI
86
L12
I/(O)
IGP0
87
L14
VSSD5
88
L11
IGP1
89
IGPV
90
IPD7
IPD6
co
z.
-d
clock output signal for image port, or optional asynchronous back-end
clock input
output data qualifier for image port (optional: gated clock output)
yc
image port output control signal, affects all input port pins inclusive ICLK,
enable and active polarity is under software control (bits IPE in subaddress
87H); output path used for testing: scan output
O
general purpose output signal 0; image port (controlled by subaddresses
84H and 85H)
P
digital ground 5 (peripheral cells)
K13
O
general purpose output signal 1; image port (controlled by subaddresses
84H and 85H)
K14
O
multi purpose vertical reference output signal; image port (controlled by
subaddresses 84H and 85H)
91
K12
O
multi purpose horizontal reference output signal; image port (controlled by
subaddresses 84H and 85H)
92
K11
O
MSB of image port data output
93
J13
O
MSB − 1 of image port data output
94
J14
O
MSB − 2 of image port data output
P
digital supply voltage 6 (core)
ww
IPD5
audio master external clock input
w.
IGPH
O/st/pd audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor
to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal
pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1);
notes 5 and 7
VSSD6
96
J11
P
digital ground 6 (core)
IPD4
97
H13
O
MSB − 3 of image port data output
IPD3
98
H14
O
MSB − 4 of image port data output
IPD2
99
H11
O
MSB − 5 of image port data output
IPD1
100
G12
O
MSB − 6 of image port data output
VDDD7
101
H12
P
digital supply voltage 7 (peripheral cells)
IPD0
102
G14
O
LSB of image port data output
VDDD6
2004 Jul 22
95
J12
9
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
PIN
SAA7118
TYPE(1)
SYMBOL
DESCRIPTION
103
G13
I/O
VSSD7
104
G11
P
HPD6
105
F14
I/O
MSB of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
digital ground 7 (peripheral cells)
MSB − 1 of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
co
HPD7
m
QFP160 BGA156
VDDD8
106
F12
P
HPD5
107
F13
I/O
digital supply voltage 8 (core)
VSSD8
108
F11
P
HPD4
109
E14
I/O
MSB − 3 of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
HPD3
110
E12
I/O
MSB − 4 of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
HPD2
111
E13
I/O
MSB − 5 of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
HPD1
112
E11
I/O
MSB − 6 of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
HPD0
113
D14
I/O
MSB − 2 of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
-d
z.
digital ground 8 (core)
LSB of host port data I/O, extended CB-CR input for expansion port,
extended CB-CR output for image port
VDDD9
114
D12
P
DNC1
115
D13
I/pu
digital supply voltage 9 (peripheral cells)
DNC2
116
C14
I/pu
do not connect, reserved for future extensions and for testing: scan input
DNC7
117
B13
NC
do not connect, reserved for future extensions and for testing
DNC8
118
B14
NC
do not connect, reserved for future extensions and for testing
DNC11
119
C12
NC
do not connect, reserved for future extensions and for testing
DNC12
120
C13
NC
do not connect, reserved for future extensions and for testing
yc
do not connect, reserved for future extensions and for testing: scan input
121
−
NC
do not connect, reserved for future extensions and for testing
122
−
NC
do not connect, reserved for future extensions and for testing
DNC3
123
A13
I/pu
do not connect, reserved for future extensions and for testing: scan input
DNC4
124
B12
O
DNC5
125
A12
I/pu
XTRI
126
B11
I
ww
w.
DNC21
DNC22
do not connect, reserved for future extensions and for testing: scan output
do not connect, reserved for future extensions and for testing: scan input
X port output control signal, affects all X port pins (XPD7 to XPD0, XRH,
XRV, XDQ and XCLK), enable and active polarity is under software control
(bits XPE in subaddress 83H)
XPD7
127
C11
I/O
MSB of expansion port data
XPD6
128
A11
I/O
MSB − 1 of expansion port data
VSSD9
129
D11
P
digital ground 9 (peripheral cells)
XPD5
130
B10
I/O
MSB − 2 of expansion port data
XPD4
131
A10
I/O
MSB − 3 of expansion port data
VDDD10
132
C10
P
digital supply voltage 10 (core)
VSSD10
133
D10
P
digital ground 10 (core)
2004 Jul 22
10
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
PIN
SAA7118
TYPE(1)
SYMBOL
DESCRIPTION
QFP160 BGA156
134
B9
I/O
MSB − 4 of expansion port data
XPD2
135
A9
I/O
MSB − 5 of expansion port data
VDDD11
136
C9
P
digital supply voltage 11 (peripheral cells)
VSSD11
137
D9
P
digital ground 11 (peripheral cells)
XPD1
138
B8
I/O
MSB − 6 of expansion port data
XPD0
139
A8
I/O
LSB of expansion port data
co
m
XPD3
XRV
140
D8
I/O
vertical reference I/O expansion port
XRH
141
C7
I/O
horizontal reference I/O expansion port
VDDD12
142
C8
P
XCLK
143
A7
I/O
clock I/O expansion port
XDQ
144
B7
I/O
data qualifier for expansion port
VSSD12
145
D7
P
digital ground 12 (core)
task flag or ready signal from scaler, controlled by XRQT
z.
digital supply voltage 12 (core)
XRDY
146
A6
O
TRST
147
C6
I/pu
TCK
148
B6
I/pu
TMS
149
D6
I/pu
TDO
150
A5
O
VDDD13
151
C5
P
TDI
152
B5
I/pu
VSSD13
153
D5
VSS(xtal)
154
A4
XTALI
155
B4
XTALO
156
A3
VDD(xtal)
157
B3
P
supply voltage for crystal oscillator
XTOUT
158
A2
O
crystal oscillator output signal; auxiliary signal
-d
test reset input (active LOW), for boundary scan test (with internal pull-up);
notes 2, 3 and 4
test clock for boundary scan test; note 2
test mode select input for boundary scan test or scan test; note 2
test data output for boundary scan test; note 2
digital supply voltage 13 (peripheral cells)
yc
test data input for boundary scan test; note 2
digital ground 13 (peripheral cells)
P
ground for crystal oscillator
I
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection
of external oscillator with TTL compatible square wave clock signal
O
24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL
clock input of XTALI is used
w.
P
DNC9
159
C3
NC
do not connect, reserved for future extensions and for testing
DNC10
160
C4
NC
do not connect, reserved for future extensions and for testing
ww
Notes
1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.
2. In accordance with the “IEEE1149.1” standard the pads TDI, TMS, TCK and TRST are input pads with an internal
pull-up transistor and TDO is a 3-state output pad.
3. For board design without boundary scan implementation connect the TRST pin to ground.
4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
5. Pin strapping is done by connecting the pin to the supply via a 3.3 kΩ resistor. During the power-up reset sequence
the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping
resistor is necessary (internal pull-down).
2004 Jul 22
11
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
6. Pin RTCO operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave
address 40H/41H.
2
AGND
3
VSSA4
AI42
4
AI4D
6
AI43
7
VDDA4
8
VDDA4A 9
AI44 10
VSSA3 12
AI32 13
AI3D 14
AI33 15
VDDA3 16
VDDA3A 17
AI34 18
AI21 19
AI2D 22
AI23 23
VDDA2 24
VDDA2A 25
AI24 26
AI13 31
VDDA1 32
VDDA1A 33
AI14 34
AGNDA 35
ww
AOUT 36
121 DNC21
122 DNC22
123 DNC3
124 DNC4
125 DNC5
126 XTRI
129 VSSD9
128 XPD6
130 XPD5
131 XPD4
133 VSSD10
132 VDDD10
134 XPD3
135 XPD2
137 VSSD11
136 VDDD11
138 XPD1
139 XPD0
140 XRV
127 XPD7
114 VDDD9
113 HPD0
112 HPD1
111 HPD2
110 HPD3
109 HPD4
108 VSSD8
107 HPD5
106 VDDD8
105 HPD6
104 VSSD7
103 HPD7
102 IPD0
101 VDDD7
100 IPD1
99 IPD2
98 IPD3
97 IPD4
96 VSSD6
95 VDDD6
94 IPD5
93 IPD6
w.
AI11 27
118 DNC8
115 DNC1
SAA7118H
AI22 21
119 DNC11
116 DNC2
yc
VSSA2 20
120 DNC12
117 DNC7
-d
AI31 11
AI1D 30
142 VDDD12
141 XRH
143 XCLK
145 VSSD12
144 XDQ
146 XRDY
147 TRST
148 TCK
149 TMS
151 VDDD13
150 TDO
152 TDI
154 VSS(xtal)
153 VSSD13
155 XTALI
157 VDD(xtal)
156 XTALO
5
VSSA1 28
AI12 29
co
1
AI41
z.
DNC6
159 DNC9
160 DNC10
handbook, full pagewidth
158 XTOUT
m
7. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.
92 IPD7
91 IGPH
90 IGPV
89 IGP1
88 VSSD5
87 IGP0
86 ITRI
85 IDQ
2004 Jul 22
12
75
76
77
78
79
80
AMXCLK
ITRDY
DNC0
DNC16
DNC17
73
VDDD5
74
72
AMCLK
ASCLK
71
ALRCLK
70
RTS1
69
RTS0
Fig.2 Pin configuration (QFP160).
RTCO
68
SDA
65
VDDD4
67
64
INT_A
66
63
VSSD3
SCL
62
VSSD4
61
57
ADP4
ADP0
56
ADP5
ADP1
55
ADP6
60
54
ADP7
ADP2
53
ADP8
59
52
CLKEXT
58
51
VSSD2
ADP3
50
VDDD3
49
48
LLC2
RES
47
VDDD2
46
45
VDDD1
LLC
44
CE
VSSD1
43
EXMCLR
81 DNC19
42
82 DNC20
DNC14 40
41
83 FSW
DNC13 39
DNC15
84 ICLK
VSSA0 38
DNC18
VDDA0 37
MHC564
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
MHB725
P
N
M
L
K
J
H
G
F
E
D
C
B
A
z.
SAA7118E
co
handbook, halfpage
-d
1 2 3 4 5 6 7 8 9 10 11 12 13 14
ww
w.
yc
Fig.3 Pin configuration (BGA156).
2004 Jul 22
m
SAA7118
13
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ww
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1
4
5
6
7
8
9
10
11
12
13
XTOUT
XTALO
VSS(xtal)
TDO
XRDY
XCLK
XPD0
XPD2
XPD4
XPD6
TEST1
TEST2
AI41
TEST3
VDD(xtal)
XTALI
TDI
TCK
XDQ
XPD1
XPD3
XPD5
XTRI
TEST4
TEST5
C
VSSA4
AGND
TEST7
TEST8
VDDD13
TRST
XRH
VDDD12
VDDD11
VDDD10
XPD7
TEST9
TEST10 TEST11
D
AI43
AI42
AI4D
VDDA4
VSSD13
TMS
VSSD12
XRV
VSSD11
VSSD10
VSSD9
VDDD9
TEST12
HPD0
E
AI44
VDDA4A
AI31
VSSA3
HPD1
HPD3
HPD2
HPD4
F
AI3D
AI32
AI33
VDDA3
VSSD8
VDDD8
HPD5
HPD6
G
AI34
VDDA3A
AI22
AI21
VSSD7
IPD1
HPD7
IPD0
H
AI2D
AI23
VSSA2
VDDA2
IPD2
IPD4
IPD3
J
VDDA2A
AI11
AI24
VSSA1
VSSD6
VDDD6
IPD6
IPD5
K
AI12
AI13
AI1D
VDDA1
L
VDDA1A
AGNDA
AI14
VSSD1
VSSD2
ADP6
ADP3
VSSD3
VSSD4
M
AOUT
VSSA0
VDDA0
VDDD1
VDDD2
ADP7
ADP2
VDDD3
VDDD4
.c
VDDD7
ITRDY
A
B
.y
14
c-
dz
IPD7
om
14
TEST6
IGPH
IGP1
IGPV
ITRI
IDQ
IGP0
FSW
ICLK
RTCO
VSSD5
RTS0
VDDD5 AMXCLK
N
TEST13 TEST14 TEST15
CE
LLC2
CLKEXT
ADP5
ADP0
SCL
RTS1
ASCLK
TEST16 TEST17
P
TEST18 EXMCLR
LLC
RES
ADP8
ADP4
ADP1
INT_A
SDA
AMCLK ALRCLK TEST19
Product specification
3
SAA7118
2
Philips Semiconductors
Pin assignment (top view)
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
Table 1
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ww
w
SYMBOL
8-BIT
INPUT
MODES
16-BIT INPUT
MODES (ONLY
FOR I2C-BUS
PROGRAMMING)
ALTERNATIVE
INPUT
FUNCTIONS
Y data input
8-BIT
OUTPUT
MODES
15
A7 (143)
XCLK
clock
input
B7 (144)
XDQ
data
qualifier
input
A6 (146)
XRDY
input
ready
output
C7 (141)
XRH
horizontal
reference
input
decoder
horizontal
reference
output
D8 (140)
XRV
vertical
reference
input
decoder
vertical
reference
output
B11
(126)
XTRI
output
enable
input
.y
D1
decoder
output
c-
gated clock
input
active task A/B
flag
I/O
CONFIGURATION
PROGRAMMING
BITS
XCODE[92H[3]]
XPE[1:0] 83H[1:0]
+ pin XTRI
decoder
clock
output
XPE[1:0] 83H[1:0]
+ pin XTRI
XPCK[1:0] 83H[5:4]
XCKS[92H[0]]
data
qualifier
output
(HREF and
VREF
gate)
XDQ[92H[1]]
XPE[1:0] 83H[1:0]
+ pin XTRI
dz
.c
XRQT[83H[2]]
XPE[1:0] 83H[1:0]
+ pin XTRI
om
XDH[92H[2]]
XPE[1:0] 83H[1:0]
+ pin XTRI
XDV[1:0] 92H[5:4]
XPE[1:0] 83H[1:0]
+ pin XTRI
XPE[1:0] 83H[1:0]
Product specification
D1 data
input
ALTERNATIVE
OUTPUT
FUNCTIONS
SAA7118
C11,
XPD7 to
A11,
XPD0
B10,
A10, B9,
A9, B8,
A8 (127,
128, 130,
131, 134,
135, 138,
139)
16-BIT OUTPUT
MODES (ONLY
FOR I2C-BUS
PROGRAMMING)
Philips Semiconductors
PIN(1)
8-bit/16-bit and alternative pin function configurations
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
Table 2
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ww
w
SYMBOL
HPD7 to
G13,
HPD0
F14,
F13,
E14,
E12,
E13,
E11, D14
(103,
105, 107,
109 to
113)
16
K11,
IPD7 to
J13, J14, IPD0
H13,
H14,
H11,
G12,
G14 (92
to 94, 97
to 99,
100,
102)
ALTERNATIVE
INPUT
FUNCTIONS
8-BIT
OUTPUT
MODES
CB-CR data input
.y
c-
D1 scaler
output
16-BIT OUTPUT
MODES (ONLY
FOR I2C-BUS
PROGRAMMING)
ICODE[93H[7]]
ISWP[1:0] 85H[7:6]
I8_16[93H[6]]
IPE[1:0] 87H[1:0]
+ pin ITRI
Y scaler output
ICODE[93H[7]]
ISWP[1:0] 85H[7:6]
I8_16[93H[6]]
IPE[1:0] 87H[1:0]
+ pin ITRI
IDQ
data
qualifier
output
N12 (77)
ITRDY
target
ready input
K12 (91)
IGPH
H gate
output
ICKS[1:0] 80H[1:0]
IPE[1:0] 87H[1:0]
+ pin ITRI
om
gated clock
output
ICKS[3:2] 80H[3:2]
IDQP[85H[0]]
IPE[1:0] 87H[1:0]
+ pin ITRI
extended
H gate,
horizontal
pulses
IDH[1:0] 84H[1:0]
IRHP[85H[1]]
IPE[1:0] 87H[1:0]
+ pin ITRI
Product specification
L13 (85)
.c
clock input
SAA7118
clock
output
I/O
CONFIGURATION
PROGRAMMING
BITS
CB-CR scaler
output
dz
M14 (84) ICLK
ALTERNATIVE
OUTPUT
FUNCTIONS
Philips Semiconductors
16-BIT INPUT
MODES (ONLY
FOR I2C-BUS
PROGRAMMING)
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
PIN(1)
8-BIT
INPUT
MODES
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ww
w
SYMBOL
K14 (90)
IGPV
K13 (89)
IGP1
L14 (87)
IGP0
L12 (86)
ITRI
ALTERNATIVE
INPUT
FUNCTIONS
8-BIT
OUTPUT
MODES
16-BIT OUTPUT
MODES (ONLY
FOR I2C-BUS
PROGRAMMING)
V gate
output
.y
17
Note
1. Pin numbers for QFP160 in parenthesis.
ALTERNATIVE
OUTPUT
FUNCTIONS
V-sync, vertical
pulses
general
purpose
c-
I/O
CONFIGURATION
PROGRAMMING
BITS
IDV[1:0] 84H[3:2]
IRVP[85H[2]]
IPE[1:0] 87H[1:0]
+ pin ITRI
IDG1[1:0] 84H[5:4]
IG1P[85H[3]]
IPE[1:0] 87H[1:0]
+ pin ITRI
general
purpose
IDG0[1:0] 84H[7:6]
IG0P[85H[4]]
IPE[1:0] 87H[1:0]
+ pin ITRI
output
enable
input
dz
.c
Product specification
SAA7118
om
Philips Semiconductors
16-BIT INPUT
MODES (ONLY
FOR I2C-BUS
PROGRAMMING)
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
PIN(1)
8-BIT
INPUT
MODES
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
The anti-alias filters are adapted to the line-locked clock
frequency via a filter control circuit. The characteristic is
shown in Fig.4. During the vertical blanking period gain
and clamping control are frozen.
FUNCTIONAL DESCRIPTION
8.1
8.1.1
Decoder
ANALOG INPUT PROCESSING
m
8
SAA7118
V
(dB)
0
−6
-d
−12
−18
−24
−36
2
4
6
2004 Jul 22
8
Fig.4 Anti-alias filter.
ww
w.
0
yc
−30
−42
MGD138
z.
6
co
The SAA7118 offers sixteen analog signal inputs, four
analog main channels with source switch, clamp circuit,
analog amplifier, anti-alias filter and video 9-bit CMOS
ADC with a Decimation Filter (DF); see Figs 5 and 8.
18
10
12
f (MHz)
14
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
MBL753
m
6
handbook, full pagewidth
G
(dB)
0
co
−6
−12
−18
−30
−36
−42
0
1
2
3
4
5
6
7
8
-d
−48
z.
−24
ww
w.
yc
Fig.5 Decimation filter.
2004 Jul 22
19
9
10
11
12
13
14
f (MHz)
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.1.1.1
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
Component inputs are gain adjusted manually at a fixed
gain. The AGC active time is the sync bottom of the video
signal.
Clamping
m
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the four ADC channels are fixed for luminance (120),
chrominance (256) and for component inputs as
component Y (32), components PB and PR (256) or
components RGB (32). Clamping time in normal use is set
with the HCL pulse on the back porch of the video signal.
co
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 9 and 10) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
Gain control
z.
8.1.1.2
SAA7118
TV line
analog line blanking
511
GAIN
120
1
yc
handbook, halfpage
-d
The gain control circuit receives (via the I2C-bus) the static
gain levels for the four analog amplifiers or controls one of
these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).
CLAMP
HCL
Analog line with clamp (HCL) and gain
range (HSY).
2004 Jul 22
0 dB
maximum
range 9 dB
0 dB
(1 V (p-p) 18/56 Ω)
−6 dB
minimum
MHB325
Fig.7 Automatic gain range.
ww
Fig.6
+3 dB
controlled
ADC input level
MHB726
w.
HSY
analog input level
20
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
co
m
SAA7118
handbook, full pagewidth
TEST
SELECTOR
AND
BUFFER
DIGITAL
TEST
SELECTOR
AOSL[2:0]
SOURCE
SWITCH
ANALOG
AMPLIFIER
DAC9
CLAMP
CIRCUIT
ANTI-ALIAS
FILTER
BYPASS
SWITCH
ADP[8:0]
DOSL[1:0]
ADPE
z.
AI44
AI43
AI42
AI41
AI4D
AOUT
ADC4
FUSE[1:0]
SOURCE
SWITCH
ANALOG
AMPLIFIER
DAC9
CLAMP
CIRCUIT
ANTI-ALIAS
FILTER
BYPASS
SWITCH
ADC3
-d
AI34
AI33
AI32
AI31
AI3D
FUSE[1:0]
AI24
AI23
AI22
AI21
AI2D
SOURCE
SWITCH
ANALOG
AMPLIFIER
DAC9
CLAMP
CIRCUIT
ANTI-ALIAS
FILTER
BYPASS
SWITCH
ADC2
FUSE[1:0]
ANALOG
AMPLIFIER
DAC9
CLAMP
CIRCUIT
SOURCE
SWITCH
ANTI-ALIAS
FILTER
yc
AI14
AI13
AI12
AI11
AI1D
CLAMP
CONTROL
GAIN
CONTROL
w.
MODE
CONTROL
HCL
GLIMB HSY
GLIMT
WIPA
SLTCA
ww
MODE[5:0]
9
CVBS/Y
ANTI-ALIAS
CONTROL
HOLDG
GAFIX
WPOFF
GUDL[1:0]
GAI[48:40]
GAI[38:30]
HLNRS
UPTCV
REFA
BYPASS
SWITCH
ADC1
FUSE[1:0]
VERTICAL
BLANKING
CONTROL
VBLNK
SVREF
VBSL
9
9
9
9
DF
DF
DF
DF
ANALOG CONTROL
CROSS MULTIPLEXER
9
9
CHROMA
R/R - Y
9
G/Y
9
B/B - Y
9
9
AD2/4BYP AD1/3BYP
Fig.8 Analog input processing using the SAA7118 as differential front-end with 9-bit ADC.
2004 Jul 22
21
MBL758
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
handbook, full pagewidth
SAA7118
ANALOG INPUT
DAC
ANTI-ALIAS FILTER
ADC
9
VBLK
1
LUMA/CHROMA DECODER
0
z.
1
NO ACTION
0
HOLDG
1
0
X
1
0
<4
> 510
1
1
1
ww
0
0
+1/L
w.
STOP
> 510
X=1
yc
+1/F
> 496
1
0
<1
X=0
1
0
HSY
-d
0
9
co
gain
AMPLIFIER
+1/LLC2
−1/LLC2
+/− 0
−1/LLC2
GAIN ACCUMULATOR (18 BITS)
ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB]
1
0
X
1
0
HSY
1
AGV
Y
UPDATE
0
FGV
X = system variable.
Y = AGV – FGV > GUDL .
GAIN VALUE 9-BIT
GUDL = gain update level (adjustable).
VBLK = vertical blanking pulse.
HSY = horizontal sync pulse.
AGV = actual gain value.
FGV = frozen gain value.
MHB728
Fig.9 Gain flow chart.
2004 Jul 22
22
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
m
ANALOG INPUT
1
NO BLANKING ACTIVE
VBLK
0
<- CLAMP
1
CLL
0
HCL
0
0
− CLAMP
1
NO CLAMP
HSY
+ GAIN
SBOT
1
− GAIN
-d
+ CLAMP
GAIN ->
yc
WIPE = white peak level (510).
SBOT = sync bottom level (1).
CLL = clamp level [120 for CVBS, Y(C), S; 256 for C(Y), PB-PR; 32 for RGB, Y].
HSY = horizontal sync pulse.
HCL = horizontal clamp pulse.
ww
w.
Fig.10 Clamp and gain flow chart.
2004 Jul 22
0
z.
1
co
ADC
23
1
fast − GAIN
WIPE
0
slow + GAIN
MGC647
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.y
QUADRATURE
MODULATOR
LOW-PASS 1
DOWNSAMPLING
SUBCARRIER
GENERATION 2
24
CHROMINANCE
INCREMENT
DELAY
SUBCARRIER
GENERATION 1
HUEC
LCBW [ 2:0]
LDEL
YCOMB
CHR
CB-CR
INTERPOLATION
LOW-PASS 3
LUBW
c-
LUFI [ 3:0]
CSTD [ 2:0]
YDEL [ 2:0]
CB-CR
ADAPTIVE
COMB FILTER
CB-CR
SET_RAW
SET_VBI
LOW-PASS 2
dz
SET_RAW CCOMB
SET_VBI YCOMB
LDEL
BYPS
BRIGHTNESS
CONTRAST
SATURATION
CONTROL
RAW DATA
GAIN AND
OFFSET
CONTROL
.c
SUBCARRIER
INCREMENT
GENERATION
AND
DIVIDER
AMPLITUDE
DETECTOR
CHROMA
GAIN
CONTROL
BURST GATE
ACCUMULATOR
CB-CR
ADJUSTMENT
LOOP FILTER
CODE
DBRI [ 7:0]
DCON [ 7:0]
DSAT [ 7:0]
RAWG [ 7:0]
RAWO [ 7:0]
COLO
SECAM
PROCESSING
PHASE
DEMODULATOR
SECS
CB-CR
CB-CR -OUT
HREF-OUT
SET_RAW
SET_VBI
om
PAL DELAY LINE
SECAM
RECOMBINATION
SET_RAW
SET_VBI
DCVF
MHB729
fH /2 switch signal
SAA7118
Fig.11 Chrominance and luminance processing.
Y-OUT/
CVBS OUT
Product specification
FCTC
ACGC
CGAIN [ 6:0]
IDEL [ 3:0]
Y/CVBS
CHBW
CHROMINANCE
INCREMENT
DTO RESET
CDTO INCS
CSTD [ 2:0]
RTCO
LUMINANCE-PEAKING
OR
LOW-PASS,
Y-DELAY ADJUSTMENT
Philips Semiconductors
QUADRATURE
DEMODULATOR
SUBTRACTOR
Multistandard video decoder with adaptive
comb filter and component video input
CVBS-IN
or CHR-IN
Y
DELAY
COMPENSATION
CHROMINANCE AND LUMINANCE PROCESSING
LDEL
YCOMB
8.1.2
ndbook, full pagewidth
2004 Jul 22
ww
w
CVBS-IN
or Y-IN
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.1.2.1
SAA7118
The succeeding chrominance gain control block amplifies
or attenuates the CB-CR signal according to the required
ITU 601/656 levels. It is controlled by the output signal
from the amplitude detection circuit within the burst
processing block.
Chrominance path
m
The 9-bit CVBS or chrominance input signal is fed to the
input of a quadrature demodulator, where it is multiplied by
two time-multiplexed subcarrier signals from the subcarrier
generation block 1 (0° and 90° phase relationship to the
demodulator axis). The frequency is dependent on the
chosen colour standard.
co
The burst processing block provides the feedback loop of
the chrominance PLL and contains the following:
• Burst gate accumulator
The time-multiplexed output signals of the multipliers are
low-pass filtered (low-pass 1). Eight characteristics are
programmable via LCWB3 to LCWB0 to achieve the
desired bandwidth for the colour difference signals (PAL,
NTSC) or the 0° and 90° FM signals (SECAM).
• Colour identification and colour killer
• Comparison nominal/actual burst amplitude (PAL/NTSC
standards only)
• Loop filter chrominance gain control (PAL/NTSC
standards only)
z.
The chrominance low-pass 1 characteristic also influences
the grade of cross-luminance reduction during horizontal
colour transients (large chrominance bandwidth means
strong suppression of cross-luminance). If the Y-comb
filter is disabled by YCOMB = 0 the filter influences directly
the width of the chrominance notch within the luminance
path (a large chrominance bandwidth means wide
chrominance notch resulting in a lower luminance
bandwidth).
• Loop filter chrominance PLL (only active for PAL/NTSC
standards)
• PAL/SECAM sequence detection, H/2-switch
generation.
-d
The increment generation circuit produces the Discrete
Time Oscillator (DTO) increment for both subcarrier
generation blocks. It contains a division by the increment
of the line-locked clock generator to create a stable
phase-locked sine signal under all conditions (e.g. for
non-standard signals).
w.
yc
The low-pass filtered signals are fed to the adaptive comb
filter block. The chrominance components are separated
from the luminance via a two-line vertical stage (four lines
for PAL standards) and a decision logic between the
filtered and the non-filtered output signals. This block is
bypassed for SECAM signals. The comb filter logic can be
enabled independently for the succeeding luminance and
chrominance processing by YCOMB (subaddress 09H,
bit D6) and/or CCOMB (subaddress 0EH, bit D0). It is
always bypassed during VBI or raw data lines
programmable by the LCRn registers (subaddresses
41H to 57H); see Section 8.3.
ww
The separated CB-CR components are further processed
by a second filter stage (low-pass 2) to modify the
chrominance bandwidth without influencing the luminance
path. Its characteristic is controlled by CHBW
(subaddress 10H, bit D3). For the complete transfer
characteristic of low-passes 1 and 2 see Figs 12 and 13.
The SECAM processing (bypassed for QAM standards)
contains the following blocks:
• Baseband ‘bell’ filters to reconstruct the amplitude and
phase equalized 0° and 90° FM signals
• Phase demodulator and differentiator
(FM-demodulation)
• De-emphasis filter to compensate the pre-emphasized
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM switch signal).
2004 Jul 22
25
The PAL delay line block eliminates crosstalk between the
chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards the
delay line can be used as an additional vertical filter.
If desired, it can be switched off by DCVF = 1. It is always
disabled during VBI or raw data lines programmable by the
LCRn registers (subaddresses 41H to 57H); see
Section 8.3. The embedded line delay is also used for
SECAM recombination (cross-over switches).
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
MHB533
3
0
−3
co
V
(dB)
−6
−9
−12
(1)
−15
(2)
−18
(3)
−21
(4)
−24
z.
−27
−30
−33
−36
−39
−42
(1)
(2)
(3)
(4)
LCBW[2:0] = 000.
LCBW[2:0] = 010.
LCBW[2:0] = 100.
LCBW[2:0] = 110.
−48
−51
−54
−57
−60
0
3
0
−3
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
f (MHz)
yc
V
(dB)
-d
−45
−6
−9
−12
−15
(5)
−18
(6)
−21
(7)
w.
−24
(8)
−27
−30
−33
−36
−39
−42
−45
−48
ww
(5) LCBW[2:0] = 001.
(6) LCBW[2:0] = 011.
(7) LCBW[2:0] = 101.
(8) LCBW[2:0] = 111.
−51
−54
−57
−60
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
f (MHz)
Fig.12 Transfer characteristics of the chrominance low-pass at CHBW = 0.
2004 Jul 22
26
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
MHB534
3
0
−3
co
V
(dB)
−6
−9
−12
(1)
−15
(2)
−18
(3)
−21
(4)
−24
z.
−27
−30
−33
−36
−39
−42
(1)
(2)
(3)
(4)
LCBW[2:0] = 000.
LCBW[2:0] = 010.
LCBW[2:0] = 100.
LCBW[2:0] = 110.
−48
−51
−54
−57
−60
0
3
0
−3
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
f (MHz)
yc
V
(dB)
-d
−45
−6
−9
−12
−15
(5)
−18
(6)
−21
(7)
w.
−24
−27
(8)
−30
−33
−36
−39
−42
−45
−48
ww
(5) LCBW[2:0] = 001.
(6) LCBW[2:0] = 011.
(7) LCBW[2:0] = 101.
(8) LCBW[2:0] = 111.
−51
−54
−57
−60
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
f (MHz)
Fig.13 Transfer characteristics of the chrominance low-pass at CHBW = 1.
2004 Jul 22
27
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.1.2.2
SAA7118
The frequency characteristic of the separated luminance
signal can be further modified by the succeeding
luminance filter block. It can be configured as peaking
(resolution enhancement) or low-pass block by LUFI3 to
LUFI0 (subaddress 09H, bits D3 to D0). The 16 resulting
frequency characteristics can be seen in Fig.18. The
LUFI3 to LUFI0 settings can be used as a user
programmable sharpness control.
Luminance path
m
The rejection of the chrominance components within the
9-bit CVBS or Y input signal is achieved by subtracting the
remodulated chrominance signal from the CVBS input.
co
The comb filtered CB-CR components are interpolated
(upsampled) by the low-pass 3 block. Its characteristic is
controlled by LUBW (subaddress 09H, bit D4) to modify
the width of the chrominance ‘notch’ without influencing
the chrominance path. The programmable frequency
characteristics available, in conjunction with the LCBW2 to
LCBW0 settings, can be seen in Figs 14 to 17. It should be
noted that these frequency curves are only valid for
Y-comb disabled filter mode (YCOMB = 0). In comb filter
mode the frequency response is flat. The centre frequency
of the notch is automatically adapted to the chosen colour
standard.
z.
The luminance filter block also contains the adjustable
Y-delay part; programmable by YDEL2 to YDEL0
(subaddress 11H, bits D2 to D0).
ww
w.
yc
-d
The interpolated CB-CR samples are multiplied by two
time-multiplexed subcarrier signals from the subcarrier
generation block 2. This second DTO is locked to the first
subcarrier generator by an increment delay circuit
matched to the processing delay, which is different for PAL
and NTSC standards according to the chosen comb filter
algorithm. The two modulated signals are finally added to
build the remodulated chrominance signal.
2004 Jul 22
28
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
MHB535
3
0
−3
−6
−9
(1)
−12
(2)
−15
(3)
−18
(4)
−21
−24
z.
−27
−30
−33
−36
−39
−42
−45
−48
LCBW[2:0] = 000.
LCBW[2:0] = 010.
LCBW[2:0] = 100.
LCBW[2:0] = 110.
−51
-d
(1)
(2)
(3)
(4)
−54
−57
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
3
0
−3
yc
V
(dB)
co
V
(dB)
−6
−9
−12
−15
−18
−21
−24
(5)
(6)
(7)
(8)
w.
−27
−30
−33
−36
−39
−42
−45
ww
−48
(5) LCBW[2:0] = 001.
(6) LCBW[2:0] = 011.
−51
(7) LCBW[2:0] = 101.
(8) LCBW[2:0] = 111.
−57
−54
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
Fig.14 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at
LUBW = 0.
2004 Jul 22
29
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
MHB536
3
0
−3
−6
−9
(1)
−12
(2)
−15
(3)
−18
(4)
−21
−24
z.
−27
−30
−33
−36
−39
−42
−45
−48
LCBW[2:0] = 000
LCBW[2:0] = 010
LCBW[2:0] = 100
LCBW[2:0] = 110
−51
-d
(1)
(2)
(3)
(4)
−54
−57
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
3
0
−3
yc
V
(dB)
co
V
(dB)
−6
−9
−12
(5)
−15
(6)
−18
(7)
−21
(8)
−24
w.
−27
−30
−33
−36
−39
−42
−45
ww
−48
(5) LCBW[2:0] = 001
(6) LCBW[2:0] = 011
−51
(7) LCBW[2:0] = 101
(8) LCBW[2:0] = 111
−57
−54
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
Fig.15 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at
LUBW = 1.
2004 Jul 22
30
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
MHB537
3
V
(dB)
0
−3
co
−6
−9
−12
(1)
−15
(2)
−18
(3)
−21
(4)
−24
z.
−27
−30
−33
−36
−39
−42
−45
−48
LCBW[2:0] = 000.
LCBW[2:0] = 010.
LCBW[2:0] = 100.
LCBW[2:0] = 110.
−51
-d
(1)
(2)
(3)
(4)
−54
−57
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
3
0
−3
yc
V
(dB)
−6
−9
−12
−15
−18
−21
−24
(5)
(6)
(7)
(8)
w.
−27
−30
−33
−36
−39
−42
−45
ww
−48
(5) LCBW[2:0] = 001.
(6) LCBW[2:0] = 011.
−51
(7) LCBW[2:0] = 101.
(8) LCBW[2:0] = 111.
−57
−54
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
Fig.16 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at
LUBW = 0.
2004 Jul 22
31
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
MHB538
3
V
(dB)
0
−3
co
−6
−9
−12
(1)
−15
(2)
−18
(3)
−21
(4)
−24
z.
−27
−30
−33
−36
−39
−42
−45
−48
LCBW[2:0] = 000.
LCBW[2:0] = 010.
LCBW[2:0] = 100.
LCBW[2:0] = 110.
−51
-d
(1)
(2)
(3)
(4)
−54
−57
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
3
0
−3
yc
V
(dB)
−6
−9
−12
−15
−18
−21
−24
(5)
(6)
(7)
(8)
w.
−27
−30
−33
−36
−39
−42
−45
ww
−48
(5) LCBW[2:0] = 001.
(6) LCBW[2:0] = 011.
−51
(7) LCBW[2:0] = 101.
(8) LCBW[2:0] = 111.
−57
−54
−60
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
f (MHz)
Fig.17 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at
LUBW = 1.
2004 Jul 22
32
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
MHB539
9
V
(dB)
co
8
(1)
(2)
7
(3)
(4)
(5)
6
(6)
(7)
5
z.
(8)
4
3
LUFI[3:0] = 0001.
LUFI[3:0] = 0010.
LUFI[3:0] = 0011.
LUFI[3:0] = 0100.
LUFI[3:0] = 0101.
LUFI[3:0] = 0110.
LUFI[3:0] = 0111.
LUFI[3:0] = 0000.
2
1
0
−1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
f (MHz)
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
f (MHz)
6.0
yc
3
V
(dB) 0
-d
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
−3
−6
−9
−12
w.
−15
−18
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
−21
(9) LUFI[3:0] = 1000.
−24
(10) LUFI[3:0] = 1001.
(11) LUFI[3:0] = 1010.
−27
−30
ww
(12) LUFI[3:0] = 1011.
(13) LUFI[3:0] = 1100.
(14) LUFI[3:0] = 1101.
(15) LUFI[3:0] = 1110.
(16) LUFI[3:0] = 1111.
−33
−36
−39
0
0.5
1.0
1.5
2.0
Fig.18 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).
2004 Jul 22
33
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.1.2.3
SAA7118
Brightness Contrast Saturation (BCS) control and decoder output levels
The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions:
m
• Chrominance saturation control by DSAT7 to DSAT0
• Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0
• Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0
+235
+128
white
LUMINANCE 100%
+255
+240
blue 100%
+255
+240
red 100%
+212
blue 75%
+212
red 75%
z.
+255
handbook, full pagewidth
co
• Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil “ITU Recommendation 601/656”.
+128
colourless
+128
CB-COMPONENT
+44
black
0
CR-COMPONENT
yellow 75%
-d
+16
+16
yellow 100%
0
a. Y output range.
colourless
b. CB output range.
+44
cyan 75%
+16
cyan 100%
0
MHB730
c. CR output range.
Luminance:
yc
“ITU Recommendation 601/656” digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H.
Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT.
DCON
Y OUT = Int ----------------- × ( Y – 128 ) + DBRI
68
DSAT
Chrominance: ( C R C B ) OUT = Int ---------------- × ( C R, C B – 128 ) + 128
64
w.
It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”.
ww
Fig.19 Y-CB-CR range for scaler input and X port output.
2004 Jul 22
34
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
+255
white
+199
LUMINANCE
+71
+60
LUMINANCE
black
black shoulder
+60
black shoulder = black
SYNC
SYNC
sync bottom
1
sync bottom
z.
1
white
co
+209
m
+255
SAA7118
b. Sources not containing black level offset.
-d
a. Sources containing 7.5 IRE black level offset
(e.g. NTSC M).
MGD700
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128.
Equation for modification of the raw data levels via bytes RAWG and RAWO:
RAWG
CVBS OUT = Int ------------------ × ( CVBS nom – 128 ) + RAWO
64
It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”.
8.1.3
SYNCHRONIZATION
yc
Fig.20 CVBS (raw data) range for scaler input, data slicer and X port output.
w.
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a
low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided
clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals
(e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an
oscillator to generate the line frequency control signal LFCO; see Fig.21.
The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is also achieved within the
synchronization circuit.
ww
The result is reported as flag COPRO within the decoder status byte at subaddress 1FH.
2004 Jul 22
35
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
Table 3
CLOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required for
the video input processor.
Decoder clock frequencies
CLOCK
XTALO
The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is the multiple of
the line frequency:
FREQUENCY (MHz)
24.576 or 32.110
m
8.1.4
SAA7118
LLC
27
13.5
co
LLC2
6.75 MHz = 429 × fH (50 Hz), or
6.75 MHz = 432 × fH (60 Hz).
LLC4 (internal)
6.75
LLC8 (virtual)
3.375
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
yc
LFCO
-d
z.
The LFCO signal is multiplied by a factor of 2 and 4 in the
internal PLL circuit (including phase detector, loop filtering,
VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50% duty
factor.
LOOP
FILTER
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
LLC2
MHB330
8.1.5
w.
Fig.21 Block diagram of the clock generation circuit.
It is possible to force a reset by pulling the Chip Enable pin
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA
return from 3-state to active, while the other signals have
to be activated via programming.
POWER-ON RESET AND CHIP ENABLE (CE) INPUT
ww
A missing clock, insufficient digital or analog VDDA0 supply
voltages (below 2.8 V) will start the reset sequence; all
outputs are forced to 3-state (see Fig.22). The indicator
output RES is LOW for approximately 128 LLC after the
internal reset and can be applied to reset other circuits of
the digital TV system.
2004 Jul 22
36
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
co
m
SAA7118
POC VDDA
POC VDDD
ANALOG
DIGITAL
POC
LOGIC
POC
DELAY
RES
z.
CLOCK
PLL
LLC
CE
RESINT
CLK0
-d
CE
XTALO
yc
LLCINT
RESINT
w.
LLC
some ms
20 to 200 µs
PLL-delay
896 LCC
digital delay
<1 ms
ww
RES
(internal
reset)
POC = Power-on control.
CE = chip enable input.
XTALO = crystal oscillator output.
LLCINT = internal system clock.
RESINT = internal reset.
LLC = line-locked clock output.
RES = reset output.
Fig.22 Power-on control circuit.
2004 Jul 22
37
128 LCC
MHB331
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
Component video processing
handbook, full pagewidth
FSW DELAY
Y
G/Y
RGB/Y-CB-CR CB
MATRIX
CR
B/CB
R/CR
bypass
DOWN
FOMATTER
and
Y
BCS
and
CB-CR
COMPONENT
DELAY
MIXER
z.
FSW
co
m
8.2
SAA7118
Y-CB-CR decoder
CB-CR
MHB731
-d
BCS
Y
to X-port
Fig.23 Component video processing.
RGB-TO-(Y-CB-CR) MATRIX
yc
8.2.1
The matrix converts the RGB signals from the analog-to-digital converters/downsamplers to the Y-CB-CR representation.
The input and output word widths are 9 bits. The matrix has a gain factor of 1. The block provides a delay compensated
bypass for component input signals.
The matrix is represented by the following equations:
Y = 0.299 × R + 0.587 × G + 0.114 × B
w.
CB = 0.5772 × (B − Y)
ww
CR = 0.7296 × (R − Y)
2004 Jul 22
38
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.2.2
DOWNFORMATTER
The delay compensation for the Y signal already provides
most of the registers required for a small high-pass filter.
It can be used to compensate high frequency losses in the
analog part. It provides 2 dB gain at 6.75 MHz.
m
The block mainly consists of 2 parts: the colour difference
signal downsampler and the Y-path.
The colour difference signals are first passed through
low-pass filters which reduce alias effects due to the lower
data rate. The ITU sampling scheme requires that both
colour difference samples fit to the first Y sample of the
current time slot. Thus the CR signal is delayed by 1 clock
before it is fed to the multiplexer. The switch signal defines
the data multiplex phase at the output: a ‘0’ marks the first
clock of a time slot, this is a CB sample. The output is fed
through a register, so that the multiplexer runs with the
opposite phase.
co
The Y high-pass filter frequency response is shown in
Fig.26. The DC gain of the filter is 1, so a limiter is required
at the filter output. The current implementation clips at the
maximum values of 0 and 511. The entire filter can be
controlled by the I2C-bus bit CMFI in subaddress 29H.
z.
handbook, full pagewidth
-d
LOW-PASS
CR
SAA7118
D
Q
0
D
Q
(CR-CB)OUT
1
LOW-PASS
yc
CB
switch
delay compensation
n
HIGH-PASS
Y
D
Q
w.
bypass
CMFI
ww
Fig.24 Downformatter block diagram.
2004 Jul 22
39
YOUT
MHB732
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
MHB788
4
handbook, halfpage
co
Z
(dB)
3
2
0
0
2
z.
1
−1
4
6
8
-d
f (MHz)
yc
Fig.25 CB-CR low-pass filter frequency response.
MHB787
2
handbook, halfpage
w.
Z
(dB)
0
ww
−20
−40
−60
0
2
4
6
f (MHz)
8
Fig.26 Y high-pass filter frequency response.
2004 Jul 22
m
SAA7118
40
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.2.3
SAA7118
COMPONENT VIDEO BCS CONTROL
The resulting Y and CB-CR signals are fed to the Component BCS (CBCS) block, which contains the following functions:
m
• Chrominance saturation control by CSAT7 to CSAT0
• Luminance contrast and brightness control by CCON7 to CCON0 and CBRI7 to CBRI0
+235
+128
white
LUMINANCE 100%
+255
+240
blue 100%
+255
+240
red 100%
+212
blue 75%
+212
red 75%
z.
+255
handbook, full pagewidth
co
• Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil “ITU Recommendation 601/656”.
+128
colourless
+128
CB-COMPONENT
black
0
CR-COMPONENT
yellow 75%
+44
cyan 75%
yellow 100%
+16
cyan 100%
-d
+44
+16
+16
0
b. CB output range.
0
MHB730
c. CR output range.
yc
a. Y output range.
colourless
“ITU Recommendation 601/656” digital levels with default CBCS (decoder) settings CCON[7:0] = 44H, CBRI[7:0] = 80H and CSAT[7:0] = 40H.
Equations for modification to the Y-CB-CR levels via CBCS control I2C-bus bytes CBRI, CCON and CSAT.
Luminance:
CCON
Y OUT = Int ----------------- × ( Y – 128 ) + CBRI
68
w.
CSAT
Chrominance: ( C B C R ) OUT = Int ---------------- × ( C B, C R – 128 ) + 128
64
It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”.
ww
Fig.27 Components Y-CB-CR range.
2004 Jul 22
41
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.3
Decoder output formatter
For each LCR value from 2 to 23 the data type can be
programmed individually; LCR2 to LCR23 refer to line
numbers. The selection in LCR24 values is valid for the
rest of the corresponding field. The upper nibble contains
the value for field 1 (odd), the lower nibble for field 2
(even). The relationship between LCR values and line
numbers can be adjusted via VOFF8 to VOFF0, located in
subaddresses 5BH (bit D4) and 5AH (bits D7 to D0) and
FOFF subaddress 5BH (bit D7). The recommended
values are VOFF[8:0] = 03H for 50 Hz sources (with
FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with
FOFF = 1), to accommodate line number conventions as
used for PAL, SECAM and NTSC standards;
see Tables 5 to 8.
co
m
The output interface block of the decoder part contains the
ITU 656 formatter for the expansion port data output XPD7
to XPD0 (for a detailed description see Section 9.5.1) and
the control circuit for the signals needed for the internal
paths to the scaler and data slicer part. It also controls the
selection of the reference signals for the RT port (RTCO,
RTS0 and RTS1) and the expansion port (XRH, XRV
and XDQ).
Data formats at decoder output
DATA TYPE NUMBER
z.
The generation of the decoder data type control signals
SET_RAW and SET VBI is also done within this block.
These signals are decoded from the requested data type
for the scaler input and/or the data slicer, selectable by the
control registers LCR2 to LCR24 (see also Chapter 15;
subaddresses 41H to 57H).
Table 4
DATA TYPE
DECODER OUTPUT DATA FORMAT
teletext EuroWST, CCST
1
European closed caption
raw
2
Video Programming Service (VPS)
raw
3
wide screen signalling bits
raw
4
US teletext (WST)
raw
5
US closed caption (line 21)
raw
6
video component signal, VBI region
7
CVBS data
raw
8
teletext
raw
9
VITC/EBU time codes (Europe)
raw
10
VITC/SMPTE time codes (USA)
raw
11
reserved
raw
US NABTS
raw
14
yc
raw
Y-CB-CR 4 : 2 : 2
MOJI (Japanese)
raw
Japanese format switch (L20/22)
raw
video component signal, active video region
ww
15
w.
13
-d
0
12
2004 Jul 22
SAA7118
42
Y-CB-CR 4 : 2 : 2
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521
522
Line number
(2nd field)
259
260
LCR
523
524
525
1
262
263
264
active video
261
active video
2
3
4
equalization pulses
.y
265
6
7
269
270
serration pulses
266
267
equalization pulses
24
5
268
3
4
9
equalization pulses
serration pulses
2
8
271
272
equalization pulses
5
6
7
8
9
Table 6 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2)
Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 1 (subaddress 5BH[7])
Line number
(1st field)
10
Line number
(2nd field)
273
LCR
10
11
12
13
14
43
c-
15
16
17
18
19
20
21
22
nominal VBI lines F1
274
275
276
277
278
279
11
12
13
14
15
16
17
24
25
active video
280
nominal VBI lines F2
23
281
282
283
dz
18
19
284
285
286
287
288
active video
20
21
22
23
24
Table 7 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1)
Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 0 (subaddress 5BH[7])
Line number
(1st field)
621
Line number
(2nd field)
309
622
623
624
active video
625
equalization pulses
310
311
active video
312
.c
2
3
4
serration pulses
313
equalization pulses
LCR
1
314
315
serration pulses
24
316
Philips Semiconductors
ww
w
Line number
(1st field)
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
Table 5 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1)
Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 1 (subaddress 5BH[7])
5
equalization pulses
317
om
318
equalization pulses
2
3
4
5
Table 8 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2)
Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and
59H[7:0]); FOFF = 0 (subaddress 5BH[7])
Line number
(2nd field)
319
320
321
322
323
324
325
6
7
8
9
10
11
12
LCR
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
nominal VBI lines F1
326
327
328
22
14
15
24
25
active video
329
330
331
332
333
334
335
336
16
17
18
19
20
21
22
23
nominal VBI lines F2
13
23
337
338
active video
24
Product specification
6
SAA7118
Line number
(1st field)
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
623
310
622
309
624
311
625
312
1
1
2
2
3
3
4
4
5
5
6
6
7
7
...
...
CVBS
F_ITU656
V123 (1)
VSTO [8:0] = 134H
FID
z.
VGATE
VSTA [8:0] = 15H
(a) 1st field
310
310
CVBS
HREF
312
312
313
313
314
1
315
2
316
3
317
4
318
5
319
6
yc
F_ITU656
V123 (1)
311
311
...
...
335
22
336
23
-d
309
309
23
23
co
HREF
ITU counting
single field counting
22
22
m
ITU counting
single field counting
SAA7118
VSTO [8:0] = 134H
VGATE
FID
w.
(b) 2nd field
VSTA [8:0] = 15H
MHB540
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during
the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field
is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a
few clock cycles from version to version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
RTS0
RTS1
XRH
XRV
X
X
X
−
ww
NAME
HREF
F_ITU656
−
−
−
X
V123
X
X
−
X
VGATE
X
X
−
−
FID
X
X
−
−
For further information see Section 15.2: Tables 57, 58 and 59.
Fig.28 Vertical timing diagram for 50 Hz/625 line systems.
2004 Jul 22
44
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
1
1
525
262
3
3
2
2
4
4
5
5
6
6
7
7
8
8
9
9
CVBS
...
...
F_ITU656
V123 (1)
VSTO [8:0] = 101H
FID
z.
VGATE
263
263
CVBS
HREF
265
2
266
3
267
4
268
5
269
6
270
7
271
8
272
9
yc
F_ITU656
V123 (1)
264
1
...
...
284
21
285
22
-d
262
262
22
22
VSTA [8:0] = 011H
(a) 1st field
ITU counting
single field counting
21
21
co
HREF
10
10
m
ITU counting
single field counting
SAA7118
VSTO [8:0] = 101H
VGATE
FID
w.
(b) 2nd field
VSTA [8:0] = 011H
MHB541
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during
the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field
is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a
few clock cycles from version to version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
RTS0
RTS1
XRH
XRV
X
X
X
−
ww
NAME
HREF
F_ITU656
−
−
−
X
V123
X
X
−
X
VGATE
X
X
−
−
FID
X
X
−
−
For further information see Section 15.2: Tables 57, 58 and 59.
Fig.29 Vertical timing diagram for 60 Hz/525 line systems.
2004 Jul 22
45
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
burst
CVBS input
co
m
SAA7118
expansion port
data output
z.
processing delay ADC to expansion port:
140 × 1/LLC
sync clipped
HREF (50 Hz)
720 × 2/LLC
CREF2
-d
CREF
12 × 2/LLC
144 × 2/LLC
5 × 2/LLC
HS (50 Hz)
0
yc
programming range 108
(step size: 8/LLC)
2 × 2/LLC
−107
HREF (60 Hz)
720 × 2/LLC
16 × 2/LLC
138 × 2/LLC
CREF
w.
CREF2
1 × 2/LLC
2 × 2/LLC
HS (60 Hz)
107
−106
0
MHB542
ww
programming range
(step size: 8/LLC)
The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 15.2.19 Tables 57 and 58);
their polarity can be inverted via RTP0 and/or RTP1.
The signals HREF and HS are available on pin XRH (see Section 15.2.20 Table 59).
Fig.30 Horizontal timing diagram (50/60 Hz).
2004 Jul 22
46
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.4
The overall H and V zooming (HV_zoom) is restricted by
the input/output data rate relationships. With a safety
margin of 2% for running in and running out, the maximum
HV_zoom is equal to:
T_input_field – T_v_blanking
0.98 × -------------------------------------------------------------------------------------------------------------------------------------in_pixel × in_lines × out_cycle_per_pix × T_out_clk
Scaler
co
m
The High Performance video Scaler (HPS) is based on the
system as implemented in previous products, but with
some aspects enhanced. Vertical upsampling is supported
and the processing pipeline buffer capacity is enhanced, to
allow more flexible video stream timing at the image port,
discontinuous transfers, and handshake. The internal data
flow from block to block is discontinuous dynamically, due
to the scaling process.
For example:
1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit
data at 13.5 MHz data rate, 1 cycle per pixel; output:
8-bit data at 27 MHz, 2 cycles per pixel; the maximum
HV_zoom is equal to:
20 ms – 24 × 64 µs
0.98 × -------------------------------------------------------- = 1.18
720 × 288 × 2 × 37 ns
z.
The flow is controlled by internal data valid and data
request flags (internal handshake signalling) between the
sub-blocks; therefore the entire scaler acts as a pipeline
buffer. Depending on the actually programmed scaling
parameters the effective buffer can exceed to an entire
line. The access/bandwidth requirements to the VGA
frame buffer are reduced significantly.
The high performance video scaler in the SAA7118 has
the following major blocks:
SAA7118
2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit
data at 27 MHz data rate (ITU 656), 2 cycles per pixel;
output via I + H port: 16-bit data at 27 MHz clock,
1 cycle per pixel; the maximum HV_zoom is equal to:
16.666 ms – 22 × 64 µs
0.98 × -------------------------------------------------------------- = 2.34
720 × 240 × 1 × 37 ns
-d
• Acquisition control (horizontal and vertical timer) and
task handling (the region/field/frame based processing)
• Prescaler, for horizontal downscaling by an integer
factor, combined with appropriate band limiting filters,
especially anti-aliasing for CIF format
• Brightness, saturation, contrast control for scaled output
data
yc
• Line buffer, with asynchronous read and write, to
support vertical upscaling (e.g. for videophone
application, converting 240 into 288 lines, Y-CB-CR
4 : 2 : 2)
w.
• Vertical scaling, with phase accurate Linear Phase
Interpolation (LPI) for zoom and downscale, or phase
accurate Accumulation Mode (ACM) for large
downscaling ratios and better alias suppression
• Variable Phase Delay (VPD), operates as horizontal
phase accurate interpolation for arbitrary non-integer
scaling ratios, supporting conversion between square
and rectangular pixel sampling
The input data stream is sorted into two data paths, one for
luminance (or raw samples) and one for time multiplexed
chrominance CB and CR samples. An Y-CB-CR 4 : 1 : 1
input format is converted to 4 : 2 : 2 for the horizontal
prescaling and vertical filter scaling operation.
The scaler operation is defined by two programming pages
A and B, representing two different tasks, that can be
applied field alternating or to define two regions in a field
(e.g. with different scaling range, factors and signal source
during odd and even fields).
Each programming page contains control:
• Output formatter for scaled Y-CB-CR 4 : 2 : 2,
Y-CB-CR 4 : 1 : 1 and Y only (format also used for raw
data)
ww
• For signal source selection and formats
• For task handling and trigger conditions
• For input and output acquisition window definition
• FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-CR
formats
• For H-prescaler, V-scaler and H-phase scaling.
• Output interface, 8 or 16-bit (only if extended by H port)
data pins wide, synchronous or asynchronous
operation, with stream events on discrete pins, or coded
in the data stream.
2004 Jul 22
The video scaler receives its input signal from the video
decoder or from the expansion port (X port). It gets 16-bit
Y-CB-CR 4 : 2 : 2 input data at a continuous rate of
13.5 MHz from the decoder. Discontinuous data stream
can be accepted from the expansion port (X port),
normally 8-bit wide ITU 656 such as Y-CB-CR data,
accompanied by a pixel qualifier on XDQ.
Raw VBI data is handled as a specific input format and
needs its own programming page (equals own task).
47
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
In VBI pass through operation the processing of prescaler
and vertical scaling has to be set to no-processing,
however, the horizontal fine scaling VPD can be activated.
Upscaling (oversampling, zooming), free of frequency
folding, up to a factor of 3.5 can be achieved, as required
by some software data slicing algorithms.
8.4.1.1
m
co
The bits XFDV[92H[7]] and XFDH[92H[6]] define the
detection event and state of the flag from the X port. For
the default setting of XFDV and XFDH at ‘00’ the state of
the H-input at the falling edge of the V-input is taken.
ACQUISITION CONTROL AND TASK HANDLING
(SUBADDRESSES 80H, 90H, 91H, 94H TO 9FH
AND C4H TO CFH)
z.
The scaler directly gets a corresponding field ID
information from the SAA7118 decoder path.
The acquisition control receives horizontal and vertical
synchronization signals from the decoder section or from
the X port. The acquisition window is generated via pixel
and line counters at the appropriate places in the data
path. From X port only qualified pixels and lines (lines with
qualified pixel) are counted.
The FID flag is used to determine whether the first or
second field of a frame is going to be processed within the
scaler and it is used as trigger condition for the task
handling (see bits STRC[1:0] 90H[1:0]).
According to ITU 656, when FID is at logic 0 means first
field of a frame. To ease the application, the polarities of
the detection results on the X port signals and the internal
decoder ID can be changed via XFDH.
-d
The acquisition window parameters are as follows:
Input field processing
The trigger event for the field sequence detection from
external signals (X port) are defined in subaddress 92H.
From the X port the state of the scalers H reference signal
at the time of the V reference edge is taken as field
sequence identifier FID. For example, if the falling edge of
the XRV input signal is the reference and the state of XRH
input is logic 0 at that time, the detected field ID is logic 0.
These raw samples are transported through the image
port as valid data and can be output as Y only format. The
lines are framed by SAV and EAV codes.
8.4.1
SAA7118
• Signal source selection regarding input video stream
and formats from the decoder, or from X port
(programming bits SCSRC[1:0] 91H[5:4] and FSC[2:0]
91H[2:0])
yc
Remark: The input of raw VBI data from the internal
decoder should be controlled via the decoder output
formatter and the LCR registers; see Section 8.3
• Vertical offset defined in lines of the video source,
parameter YO[11:0] 99H[3:0] 98H[7:0]
• Vertical length defined in lines of the video source,
parameter YS[11:0] 9BH[3:0] 9AH[7:0]
w.
• Vertical length defined in number of target lines, as a
result of vertical scaling, parameter YD[11:0] 9FH[3:0]
9EH[7:0]
• Horizontal offset defined in number of pixels of the video
source, parameter XO[11:0] 95H[3:0] 94H[7:0]
ww
• Horizontal length defined in number of pixels of the
video source, parameter XS[11:0] 97H[3:0] 96H[7:0]
• Horizontal destination size, defined in target pixels after
fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0].
The source start offset (XO11 to XO0 and YO11 to YO0)
opens the acquisition window, and the target size
(XD11 to XD0 and YD11 to YD0) closes the window,
however the window is cut vertically if there are less output
lines than expected. The trigger events for the pixel and
line counts are the horizontal and vertical reference edges
as defined in subaddress 92H. The task handling is
controlled by subaddress 90H; see Section 8.4.1.2.
2004 Jul 22
48
As the V-sync from the decoder path has a half line timing
(due to the interlaced video signal), but the scaler
processing only knows about full lines, during 1st fields
from the decoder the line count of the scaler possibly shifts
by one line, compared to the 2nd field. This can be
compensated for by switching the V-trigger event, as
defined by XDV0, to the opposite V-sync edge or by using
the vertical scalers phase offsets. The vertical timing of the
decoder can be seen in Figs 28 and 29.
As the H and V reference events inside the ITU 656 data
stream (from X port) and the real-time reference signals
from the decoder path are processed differently, the
trigger events for the input acquisition also have to be
programmed differently.
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
Processing trigger and start
XDV1
92H[5]
XDV0
92H[4]
XDH
92H[2]
DESCRIPTION
m
Table 9
SAA7118
1
0
0
0
0
0
0
0
8.4.1.2
4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count)
2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count)
External ITU 656 stream: The processing starts earliest with SAV at line number 23
(50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count)
Task handling
Remarks:
The task handler controls the switching between the two
programming register sets. It is controlled by
subaddresses 90H and C0H. A task is enabled via the
global control bits TEA[80H[4]] and TEB[80H[5]].
• To activate a task the start condition must be
fulfilled and the acquisition window offsets must be
reached.
For example, in case of ‘start immediately’, and two
regions are defined for one field, the offset of the lower
region must be greater than (offset + length) of the
upper region, if not, the actual counted H and V position
at the end of the upper task is beyond the programmed
offsets and the processing will ‘wait for next V’.
-d
The handler is then triggered by events, which can be
defined for each register set.
z.
0
co
Internal decoder: The processing triggers at the falling edge of the V123 pulse
[see Figs 28 (50 Hz) and 29 (60 Hz)], and starts earliest with the rising edge of the
decoder HREF at line number:
yc
In the event of a programming error the task handling and
the complete scaler can be reset to the initial states by
setting the software reset bit SWRST[88H[5]] to logic 0.
Especially if the programming registers, related acquisition
window and scale are reprogrammed while a task is active,
a software reset must be performed after programming.
Contrary to the disabling/enabling of a task, which is
evaluated at the end of a running task, when SWRST is at
logic 0 it sets the internal state machines directly to their
idle states.
w.
The start condition for the handler is defined by bits
STRC[1:0] 90H[1:0] and means: start immediately, wait for
next V-sync, next FID at logic 0 or next FID at logic 1. The
FID is evaluated, if the vertical and horizontal offsets are
reached.
• After power-on or software reset (via
SWRST[88H[5]]) task B gets priority over task A.
8.4.1.3
Output field processing
As a reference for the output field processing, two signals
are available for the back-end hardware.
When RPTSK[90H[2]] is at logic 1 the actual running task
is repeated (under the defined trigger conditions), before
handing control over to the alternate task.
ww
These signals are the input field ID from the scaler source
and a TOGGLE flag, which shows that an active task is
used an odd (1, 3, 5...) or even (2, 4, 6...) number of times.
Using a single or both tasks and reducing the field or frame
rate with the task handling function, the TOGGLE
information can be used to reconstruct an interlaced
scaled picture at a reduced frame rate. The TOGGLE flag
isn’t synchronized to the input field detection, as it is only
dependent on the interpretation of this information by the
external hardware, whether the output of the scaler is
processed correctly; see Section 8.4.3.
To support field rate reduction, the handler is also enabled
to skip fields (bits FSKP[2:0] 90H[5:3]) before executing
the task. A TOGGLE flag is generated (used for the correct
output field processing), which changes state at the
beginning of a task, every time a task is activated;
examples are given in Section 8.4.1.3.
2004 Jul 22
• Basically the trigger conditions are checked, when a
task is activated. It is important to realize, that they are
not checked while a task is inactive. So you can not
trigger to next logic 0 or logic 1 with overlapping offset
and active video ranges between the tasks (e.g. task A
STRC[2:0] = 2, YO[11:0] = 310 and task B
STRC[2:0] = 3, YO[11:0] = 310 results in output field
rate of 50⁄3 Hz).
49
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Additionally the bit D7 of SAV and EAV can be defined via CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the
SAV/EAV bit D7. So it is possible to mark the output of the both tasks by different SAV/EAV codes. This bit can also be seen as ‘task flag’ on the
pins IGP0 (IGP1), if TASK output is selected.
Table 10 Examples for field processing
SUBJECT
1/1
1/2
Processed by task
A
A
State of detected
ITU 656 FID
0
1
TOGGLE flag
1
0
Bit D6 of SAV/EAV byte
50
Required sequence
conversion at the vertical
scaler(8)
Output(9)
.y
EXAMPLE 1(1)
FIELD SEQUENCE FRAME/FIELD
EXAMPLE 2(2)(3)
c-
EXAMPLE 3(2)(4)(5)
EXAMPLE 4(2)(4)(6)
2/1
1/1
1/2
2/1
2/2
1/1
1/2
2/1
2/2
3/1
3/2
1/1
1/2
2/1
2/2
3/1
3/2
A
B
A
B
A
B
B
A
B
B
A
B
B
A
B
B
A
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
1
0
0
0(7)
1
1
1(7)
0
0
1
1
1(7)
0
0
dz
1
1
0
0
1
1
0
1
1
0
0
0(7)
LO
↓
LO
UP
↓
UP
LO
↓
LO
UP
↓
LO
LO
↓
UP
UP
↓
LO
LO
↓
LO
UP
↓
UP
LO
↓
UP
UP
↓
UP
LO
↓
LO
UP
↓
LO
LO
↓
LO
UP
↓
UP
LO
↓
UP
O
O
O
O
O
O
O
O
O
NO
O
O
NO
O
O
0
1
0
0
1
UP
↓
UP
LO
↓
LO
UP
↓
UP
UP
↓
UP
O
O
O
O
Notes
1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0.
2. Tasks are used to scale to different output windows, priority on task B after SWRST.
3. Both tasks at 1⁄2 frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.
.c
om
Philips Semiconductors
ww
w
When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID
output is selected.
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is
selected.
4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.
5. Task B at 2⁄3 frame rate constructed from neighbouring motion phases; task A at 1⁄3 frame rate of equidistant motion phases; OFIDC = 1;
subaddresses 90H at 41H and C0H at 45H.
8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.
9. O = data output; NO = no output.
SAA7118
7. State of prior field.
Product specification
6. Task A and B at 1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.4.2
SAA7118
• The bit XC2_1[A2H[3]], which defines the weighting of
the incoming pixels during the averaging process:
HORIZONTAL SCALING
The overall horizontal required scaling factor has to be split
into a binary and a rational value according to the
equation:
output pixel
H-scale ratio = -----------------------------input pixel
m
– XC2_1 = 0 ⇒ 1 + 1...+ 1 +1
– XC2_1 = 1 ⇒ 1 + 2...+ 2 +1.
co
The prescaler creates a prescale dependent FIR low-pass,
with up to (64 + 7) filter taps. The parameter XACL[5:0]
can be used to vary the low-pass characteristic for a given
integer prescale of 1⁄XPSC[5:0]. The user can therefore
decide between signal bandwidth (sharpness impression)
and alias.
1
1024
H-scale ratio = ---------------------------- × ------------------------------XPSC[5:0] XSCY[12:0]
where the parameter of prescaler XPSC[5:0] = 1 to 63 and
the parameter of VPD phase interpolation
XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical
values). For example, 1⁄3.5 is to split in 1⁄4 × 1.14286. The
binary factor is processed by the prescaler, the arbitrary
non-integer ratio is achieved via the variable phase delay
VPD circuitry, called horizontal fine scaling. The latter
calculates horizontally interpolated new samples with a
6-bit phase accuracy, which relates to less than 1 ns jitter
for regular sampling scheme. Prescaler and fine scaler
create the horizontal scaler of the SAA7118.
z.
Equation for XPSC[5:0] calculation is:
Npix_in
XPSC[5:0] = lower integer of ----------------------Npix_out
Where:
the range is 1 to 63 (value 0 is not allowed);
Npix_in = number of input pixel, and
-d
Npix_out = number of desired output pixel over the
complete horizontal scaler.
Using the accumulation length function of the prescaler
(XACL[5:0] A1H[5:0]), application and destination
dependent (e.g. scale for display or for a compression
machine), a compromise between visible bandwidth and
alias suppression can be determined.
DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1)
Horizontal prescaler (subaddresses
A0H to A7H and D0H to D7H)
yc
8.4.2.1
The use of the prescaler results in a XACL[5:0] and
XC2_1 dependent gain amplification. The amplification
can be calculated according to the equation:
The prescaling function consists of an FIR anti-alias filter
stage and an integer prescaler, which creates an adaptive
prescale dependent low-pass filter to balance sharpness
and aliasing effects.
w.
The FIR prefilter stage implements different low-pass
characteristics to reduce alias for downscales in the range
of 1 to 1⁄2. A CIF optimized filter is built-in, which reduces
artefacts for CIF output formats (to be used in combination
with the prescaler set to 1⁄2 scale); see Table 11.
The renormalization range of XDCG[2:0] is 1, 1⁄2 down
to 1⁄128.
Other amplifications have to be normalized by using the
following BCS control circuitry. In these cases the
prescaler has to be set to an overall gain of ≤1, e.g. for an
accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and
XC2_1 = 0), XDCG[2:0] must be set to ‘010’, this equals 1⁄4
and the BCS has to amplify the signal to 4⁄3 (SATN[7:0]
and CONT[7:0] value = lower integer of 4⁄3 × 64).
The function of the prescaler is defined by:
ww
• An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals
1 to 63), which covers the integer downscale
range 1 to 1⁄63
The use of XACL[5:0] is XPSC[5:0] dependent.
XACL[5:0] must be <2 × XPSC[5:0].
• An averaging sequence length XACL[5:0] A1H[5:0]
(equals 0 to 63); range 1 to 64
XACL[5:0] can be used to find a compromise between
bandwidth (sharpness) and alias effects.
• A DC gain renormalization XDCG[2:0] A2H[2:0];
1 down to 1⁄128
2004 Jul 22
It is recommended to use sequence lengths and weights,
which results in a 2N DC gain amplification, as these
amplitudes can be renormalized by the XDCG[2:0]
1
controlled -----shifter of the prescaler.
N
2
51
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
For example, if XACL[5:0] = 5, XC2_1 = 1, then the
DC gain = 10 and the required XDCG[2:0] = 4.
Remark: Due to bandwidth considerations XPSC[5:0] and
XACL[5:0] can be chosen differently to the previously
mentioned equations or Table 12, as the H-phase scaling
is able to scale in the range from zooming up by factor 3 to
downscaling by a factor of 1024⁄8191.
m
The horizontal source acquisition timing and the
prescaling ratio is identical for both the luminance path and
chrominance path, but the FIR filter settings can be
defined differently in the two channels.
co
Figures 33 and 34 show some resulting frequency
characteristics of the prescaler.
Fade-in and fade-out of the filters is achieved by copying
an original source sample each as first and last pixel after
prescaling.
Table 12 shows the recommended prescaler
programming. Other programmings, other than given in
Table 12, may result in better alias suppression, but the
resulting DC gain amplification needs to be compensated
by the BCS control, according to the equation:
XDCG[2:0]
Figures 31 and 32 show the frequency characteristics of
the selectable FIR filters.
2XDCG[2:0] ≥ DC gain
Table 11 FIR prefilter functions
PFUV[1:0] A2H[7:6]
PFY[1:0] A2H[5:4]
00
10
CHROMINANCE COEFFICIENTS
bypassed
bypassed
121
121
−1 1 1.75 4.5 1.75 1 −1
3 8 10 8 3
12221
12221
ww
w.
11
LUMINANCE FILTER
COEFFICIENTS
yc
01
-d
DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1).
z.
2
CONT[7:0] = SATN[7:0] = lower integer of ---------------------------------DC gain × 64
Where:
2004 Jul 22
SAA7118
52
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
MHB543
6
m
V
3
(dB)
0
−6
(1)
−9
(2)
−12
−15
(3)
−18
−21
z.
−24
−27
−30
−33
−36
−42
0
0.05
0.1
-d
−39
(1) PFY[1:0] = 01.
(2) PFY[1:0] = 10.
(3) PFY[1:0] = 11.
co
−3
0.15
0.2
0.25
0.3
0.35
0.4
0.45
f_sig/f_clock
0.5
yc
Fig.31 Luminance prefilter characteristic.
6
V
3
(dB)
0
−3
w.
−6
MHB544
(1)
−9
(2)
−12
(3)
−15
−18
−21
ww
−24
−27
−30
−33
−36
−39
(1) PFUV[1:0] = 01.
(2) PFUV[1:0] = 10.
(3) PFUV[1:0] = 11.
−42
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
Fig.32 Chrominance prefilter characteristic.
2004 Jul 22
53
0.2
0.225
0.25
f_sig/f_clock
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
MHB545
6
m
V
3
(dB)
0
−6
(5)
(4)
co
−3
(3)
(2)
−9
−12
−15
−18
−21
z.
−24
−27
−30
−33
−36
−42
0
-d
−39
XC2_1 = 0; Zero’s at
1
f = n × ------------------------XACL + 1
with XACL = (1), (2), (3), (4) or (5)
(1)
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
f_sig/f_clock
0.5
yc
Fig.33 Examples for prescaler filter characteristics: effect of increasing XACL[5:0].
MHB546
6
V
3
(dB)
0
(1)
−3
−6
(5)
(4)
6 dB at 0.33
(3)
w.
(6)
3 dB at 0.25
(2)
−9
−12
−15
−18
−21
ww
−24
(1) XC2_1 = 0 and XACL[5:0] = 1.
(2) XC2_1 = 1 and XACL[5:0] = 2.
(3) XC2_1 = 0 and XACL[5:0] = 3.
(4) XC2_1 = 1 and XACL[5:0] = 4.
(5) XC2_1 = 0 and XACL[5:0] = 7.
(6) XC2_1 = 1 and XACL[5:0] = 8.
−27
−30
−33
−36
−39
−42
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Fig.34 Examples for prescaler filter characteristics: setting XC2_1 = 1.
2004 Jul 22
54
0.4
0.45
f_sig/f_clock
0.5
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 12 XACL[5:0] example of usage
RECOMMENDED VALUES
FOR LOWER BANDWIDTH
REQUIREMENTS
XC2_1
XDCG[2:0]
0
1
1
0
0
2
2
1
(1 2 1) ×
4
2
1⁄ (1)
4
4
7
3
5
3
1
(1 2 2 2 2 2 2 2 1) ×
1⁄
6
6
8
(1)
16
8
(1)
16
1
8
15
0
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) ×
1⁄
9
9
15
0
(1 1 1 1 1 1 1 1) ×
10
16
1
4
1⁄
2
3
2
3
2
3
3
7
3
3
4
3
1⁄ (1)
8
0
4
8
1⁄
(1)
16
4
(1 2 2 2 2 2 2 2 1) ×
8
5
1⁄
1
1⁄ (1)
16
4
3
(1 2 2 2 2 2 2 2 1) × 1⁄16(1)
8
(1)
32
1
1
(1 2 2 2 2 2 2 2 1) ×
4
3
1⁄ (1)
16
13
16
1
5
16
1
5
3
15
15
31
0
5
16
1
5
3
16
16
32
1
1⁄
19
1⁄
31
1⁄
32
1⁄
2
13
35
Note
6
16
1
5
3
19
32
1
6
32
1
6
3
31
32
1
6
32
1
6
3
32
63
1
7
32
1
6
3
35
63
1
7
63
1
7
3
w.
1⁄
0 to 2
(1 1 1 1 1 1 1 1) × 1⁄8(1)
(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) ×
1⁄
1
1⁄ (1)
8
0
(1 1 1 1 1 1 1 1) ×
yc
10
0 to 2
1⁄ (1)
4
0
7
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) × 1⁄16(1)
1⁄
0
1⁄ (1)
2
1
7
(1 2 2 2 2 2 2 2 1) × 1⁄16(1)
1⁄
8
FIR
PREFILTER
PFY[1:0]/
PFUV[1:0]
(1 2 2 2 1) × 1⁄8(1)
4
1⁄
XDCG[2:0]
0
-d
7
0
4
4
1⁄
1
(1 2 2 2 2 2 2 2 1) ×
1⁄
7
1
(1 1 1 1) ×
0
8
0
3
1⁄ (1)
8
(1 1 1 1 1 1 1 1) × 1⁄8(1)
1⁄
5
0
(1 1) ×
1
(1 2 2 2 1) ×
1⁄
4
XC2_1
z.
3
XACL[5:0]
co
XACL[5:0]
1⁄
2
1⁄
3
FOR HIGHER BANDWIDTH
REQUIREMENTS
m
PRESCALE XPSC
RATIO
[5:0]
ww
1. Resulting FIR function.
2004 Jul 22
55
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.4.3.1
Horizontal fine scaling (variable phase delay
filter; subaddresses A8H to AFH and
D8H to DFH)
Line FIFO buffer (subaddresses 91H, B4H and
C1H, E4H)
The line FIFO buffer is a dual ported RAM structure for
768 pixels, with asynchronous write and read access. The
line buffer can be used for various functions, but not all
functions may be available simultaneously.
m
8.4.2.2
SAA7118
co
The horizontal fine scaling (VPD) should operate at scaling
ratios between 1⁄2 and 2 (0.8 and 1.6), but can also be
used for direct scaling in the range from 1⁄7.999 to
(theoretical) zoom 3.5 (restriction due to the internal data
path architecture), without prescaler.
The line buffer can buffer a complete unscaled active video
line or more than one shorter lines (only for non-mirror
mode), for selective repetition for vertical zoom-up.
In combination with the prescaler a compromise between
sharpness impression and alias can be found. This is
signal source and application dependent.
For zooming up 240 lines to 288 lines e.g., every fourth
line is requested (read) twice from the vertical scaling
circuitry for calculation.
z.
For the luminance channel a filter structure with 10 taps is
implemented, and for the chrominance a filter with 4 taps.
For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling
scheme (MPEG, video phone, Indeo YUV-9) to ITU like
sampling scheme 4 : 2 : 2, the chrominance line buffer is
read twice or four times, before being refilled again by the
source. It has to be preserved by means of the input
acquisition window definition, so that the processing starts
with a line containing luminance and chrominance
information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits
FSC[2:1] 91H[2:1] define the distance between the Y/C
lines. In the event of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1
have to be set to ‘00’.
-d
Luminance and chrominance scale increments
(XSCY[12:0] A9H[4:0] A8H[7:0] and XSCC[12:0] ADH[4:0]
ACH[7:0]) are defined independently, but must be set in a
2 : 1 relationship in the actual data path implementation.
The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0]
AEH[7:0] can be used to shift the sample phases slightly.
XPHY[7:0] and XPHC[7:0] covers the phase offset range
7.999T to 1⁄32T. The phase offsets should also be
programmed in a 2 : 1 ratio.
The underlying phase controlling DTO has a 13-bit
resolution.
yc
According to the equations
Npix_in
1
XSCY[12:0] = 1024 × ---------------------------- × ----------------------- and
XPSC[5:0] Npix_out
8.4.3
w.
XSCY[12:0]
XSCC[12:0] = ------------------------------2
the VPD covers the scale range from 0.125 to zoom 3.5.
VPD acts equivalent to a polyphase filter with 64 possible
phases. In combination with the prescaler, it is possible to
get very accurate samples from a highly anti-aliased
integer downscaled input picture.
VERTICAL SCALING
ww
The vertical scaler of the SAA7118 consists of a line FIFO
buffer for line repetition and the vertical scaler block, which
implements the vertical scaling on the input data stream in
2 different operational modes from theoretical zoom by 64
down to icon size 1⁄64. The vertical scaler is located
between the BCS and horizontal fine scaler, so that the
BCS can be used to compensate the DC gain amplification
of the ACM mode (see Section 8.4.3.2) as the internal
RAMs are only 8-bit wide.
2004 Jul 22
56
The line buffer can also be used for mirroring, i.e. for
flipping the image left to right, for the vanity picture in video
phone applications (bit YMIR[B4H[4]]). In mirror mode only
one active prescaled line can be held in the FIFO at a time.
The line buffer can be utilized as an excessive pipeline
buffer for discontinuous and variable rate transfer
conditions at the expansion port or image port.
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.4.3.2
SAA7118
Remark: The vertical start phase, as well as scaling
ratio are defined independently for the luminance and
chrominance channel, but must be set to the same
values in the actual implementation for accurate
4 : 2 : 2 output processing.
Vertical scaler (subaddresses B0H to BFH and
E0H to EFH)
m
Vertical scaling of any ratio from 64 (theoretical zoom)
to 1⁄63 (icon) can be applied.
The vertical scaling block consists of another line delay,
and the vertical filter structure, that can operate in two
different modes; Linear Phase Interpolation (LPI) and
accumulation (ACM) mode. These are controlled by
YMODE[B4H[0]]:
co
The vertical processing communicates on its input side
with the line FIFO buffer. The scale related equations are:
• Scaling increment calculation for ACM and LPI mode,
downscale and zoom: YSCY[15:0] and YSCC[15:0]
Nline_in
= lower integer of  1024 × -------------------------

Nline_out
• LPI mode: In LPI mode (YMODE = 0) two neighbouring
lines of the source video stream are added together, but
weighted by factors corresponding to the vertical
position (phase) of the target output line relative to the
source lines. This linear interpolation has a 6-bit phase
resolution, which equals 64 intra line phases. It
interpolates between two consecutive input lines only.
LPI mode should be applied for scaling ratios around 1
(down to 1⁄2), it must be applied for vertical zooming.
z.
• BCS value to compensate DC gain in ACM mode
(contrast and saturation have to be set): CONT[7:0]
A5H[7:0] respectively SATN[7:0] A6H[7:0]
Nline_out
= lower integer of  ------------------------- × 64 , or
 Nline_in

1024
= lower integer of  ------------------------------- × 64
 YSCY[15:0]

-d
• ACM mode: The vertical Accumulation (ACM) mode
(YMODE = 1) represents a vertical averaging window
over multiple lines, sliding over the field. This mode also
generates phase correct output lines. The averaging
window length corresponds to the scaling ratio, resulting
in an adaptive vertical low-pass effect, to greatly reduce
aliasing artefacts. ACM can be applied for downscales
only from ratio 1 down to 1⁄64. ACM results in a scale
dependent DC gain amplification, which has to be
precorrected by the BCS control of the scaler part.
yc
8.4.3.3
Use of the vertical phase offsets
As described in Section 8.4.1.3, the scaler processing may
run randomly over the interlaced input sequence.
Additionally the interpretation and timing between ITU 656
field ID and real-time detection by means of the state of
H-sync at the falling edge of V-sync may result in different
field ID interpretation.
A vertically scaled interlaced output also gets a larger
vertical sampling phase error, if the interlaced input fields
are processed, without regard to the actual scale at the
starting point of operation (see Fig.35).
By programming appropriate, opposite, vertical start
phase values (subaddresses B8H to BFH and
E8H to EFH) depending on odd or even field ID of the
source video stream and A or B page cycle, frame ID
conversion and field rate conversion are supported (i.e.
de-interlacing, re-interlacing).
Four events should be considered, they are illustrated in
Fig.36.
ww
w.
The phase and scale controlling DTO calculates in 16-bit
resolution, controlled by parameters YSCY[15:0] B1H[7:0]
B0H[7:0] and YSCC[15:0] B3H[7:0] B2H[7:0], continuously
over the entire filed. A start offset can be applied to the
phase processing by means of the parameters YPY3[7:0]
to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to
YPC0[7:0] in BBH[7:0] to B8H[7:0]. The start phase covers
the range of 255⁄32 to 1⁄32 lines offset.
Figures 35 and 36 and Tables 13 and 14 describe the use
of the offsets.
2004 Jul 22
57
For correct interlaced processing the vertical scaler must
be used with respect to the interlace properties of the input
signal and, if required, for conversion of the field
sequences.
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
field 1
field 2
field 1
field 2
co
field 2
scaled output,
with phase offset
m
scaled output,
no phase offset
unscaled input
field 1
SAA7118
correct scale dependent position
scale dependent start offset
-d
z.
mismatched vertical line distances
MHB547
handbook, full pagewidth
field 1
upper
B
A
yc
Fig.35 Basic problem of interlaced vertical scaling (example: downscale 3⁄5).
field 2
field 1
field 2
field 1
field 2
lower
case UP-UP
case LO-LO
case UP-LO
case LO-UP
ww
w.
C
D
MHB548
1024
Offset = ------------- = 32 = 1 line shift
32
1
YSCY[15:0]
C = --- scale increment = ------------------------------2
64
1
A = --- input line shift = 16
2
D = no offset = 0
1
1
YSCY[15:0]
B = --- input line shift + --- scale increment = ------------------------------- + 16
2
2
64
Fig.36 Derivation of the phase related equations (example: interlace vertical scaling down to 3⁄5,
with field conversion).
2004 Jul 22
58
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
In Tables 13 and 14 PHO is a usable common phase
offset.
SAA7118
The registers are assigned to the following events; e.g.
subaddresses B8H to BBH:
• B8H: 00 = input field ID 0, task status bit D0 (toggle
status; see Section 8.4.1.3)
m
It should be noted that the equations of Fig.36 produce an
interpolated output, also for the unscaled case, as the
geometrical reference position for all conversions is the
position of the first line of the lower field; see Table 13.
• B9H: 01 = input field ID 0, task status bit D1
co
• BAH: 10 = input field ID 1, task status bit D0
• BBH: 11 = input field ID 1, task status bit D1.
If there is no need for UP-LO and LO-UP conversion and
the input field ID is the reference for the back-end
operation, then it is UP-LO = UP-UP and LO-UP = LO-LO
and the 1⁄2 line phase shift (PHO + 16) that can be
skipped. This case is listed in Table 14.
Depending on the input signal (interlaced or
non-interlaced) and the task processing 50 Hz or field
reduced processing with one or two tasks (see examples
in Section 8.4.1.3), other combinations may also be
possible, but the basic equations are the same.
z.
The SAA7118 supports 4 phase offset registers per task
and component (luminance and chrominance). The value
of 20H represents a phase shift of one line.
Table 13 Examples for vertical phase offset usage: global equations
OUTPUT FIELD
USED ABBREVIATION
INTERPRETATION
Upper input lines
upper output lines
UP-UP
PHO + 16
Upper input lines
lower output lines
UP-LO
YSCY[15:0]
PHO + ------------------------------- + 16
64
Lower input lines
upper output lines
LO-UP
PHO
Lower input lines
lower output lines
LO-LO
YSCY[15:0]
PHO + ------------------------------64
yc
w.
ww
2004 Jul 22
EQUATION FOR PHASE OFFSET
CALCULATION (DECIMAL VALUES)
-d
INPUT FIELD UNDER
PROCESSING
59
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 14 Vertical phase offset usage; assignment of the phase offsets
0 = upper lines
TASK STATUS BIT
0
VERTICAL PHASE
OFFSET
YPY0[7:0] and
YPC0[7:0]
CASE
EQUATION TO BE USED
m
DETECTED INPUT
FIELD ID
case 1(1) UP-UP (PHO)
case 2(2) UP-UP
1 = lower lines
YPY1[7:0] and
YPC1[7:0]
0
YPY2[7:0] and
YPC2[7:0]
case 1
UP-UP (PHO)
case 2
UP-LO
case 3
UP-UP
case 1
YSCY[15:0]
LO-LO  PHO + ------------------------------- – 16


64
1
YPY3[7:0] and
YPC3[7:0]
case 2
LO-UP
case 3
LO-LO
case 1
YSCY[15:0]
LO-LO  PHO + ------------------------------- – 16


64
case 2
LO-LO
-d
1 = lower lines
1
z.
0 = upper lines
co
case 3(3) UP-LO
case 3
Notes
LO-UP
1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper
output lines.
yc
2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output
lines.
3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output
lines.
8.5
VBI data decoder and capture
(subaddresses 40H to 7FH)
w.
The SAA7118 contains a versatile VBI data decoder.
The implementation and programming model is in
accordance with the VBI data slicer built into the
multimedia video data acquisition circuit SAA5284.
To adjust the slicers processing to the input signal source,
there are offsets in the horizontal and vertical direction
available: parameters HOFF[10:0] 5BH[2:0] 59H[7:0],
VOFF[8:0] 5BH[4] 5AH[7:0] and FOFF[5BH[7]].
The circuitry recovers the actual clock phase during the
clock run-in period, slices the data bits with the selected
data rate, and groups them into bytes. The result is
buffered into a dedicated VBI data FIFO with a capacity of
2 × 56 bytes (2 × 14 Dwords). The clock frequency, signal
source, field frequency and accepted error count must be
defined in subaddress 40H.
ww
Contrary to the scalers counting, the slicers offsets define
the position of the H and V trigger events related to the
processed video field. The trigger events are the falling
edge of HREF and the falling edge of V123 from the
decoder processing part.
The relationship of these programming values to the input
signal and the recommended values are given in
Tables 5 to 8.
The supported VBI data standards are shown in Table 15.
For lines 2 to 24 of a field, per VBI line, 1 of 16 standards
can be selected (LCR24_[7:0] to LCR2_[7:0] in 57H[7:0] to
41H[7:0]: 23 × 2 × 4 bit programming bits).
2004 Jul 22
The definition for line 24 is valid for the rest of the
corresponding field, normally no text data (video data)
should be selected there (LCR24_[7:0] = FFH) to stop the
activity of the VBI data slicer during active video.
60
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 15 Data types supported by the data slicer block
DATA RATE
(Mbit/s)
STANDARD TYPE
FC
WINDOW
HAM
CHECK
0000
teletext EuroWST, CCST
6.9375
27H
0001
European closed caption
0.500
001
0010
VPS
5
9951H
0011
wide screen signalling bits
5
1E3C1FH
WSS
0100
US teletext (WST)
5.7272
27H
WST525
0101
US closed caption (line 21)
0.503
001
CC525
0110
(video data selected)
5
none
disable
0111
(raw data selected)
5
none
disable
1000
teletext
6.9375
programmable
general text optional
1001
VITC/EBU time codes (Europe)
1.8125
programmable
VITC625
1010
VITC/SMPTE time codes (USA)
1.7898
programmable
VITC525
1100
US NABTS
5.7272
programmable
1101
MOJI (Japanese)
5.7272
programmable (A7H) Japtext
1110
Japanese format switch (L20/22) 5
programmable
open
1111
no sliced data transmitted
(video data selected)
none
disable
always
CC625
VPS
co
z.
5
yc
Image port output formatter
(subaddresses 84H to 87H)
w.
The output interface consists of a FIFO for video and for
sliced text data, an arbitration circuit, which controls the
mixed transfer of video and sliced text data over the I port
and a decoding and multiplexing unit, which generates the
8 or 16-bit wide output data stream and the accompanied
reference and supporting information.
The clock for the output interface can be derived from an
internal clock, decoder, expansion port, or an externally
provided clock which is appropriate for e.g. VGA and frame
buffer. The clock can be up to 33 MHz. The scaler provides
the following video related timing reference events
(signals), which are available on pins as defined by
subaddresses 84H and 85H:
always
NABTS
optional
The discontinuous data stream at the scaler output is
accompanied by a data valid flag (or data qualifier), or is
transported via a gated clock. Clock cycles with invalid
data on the I port data bus (including the HPD pins in 16-bit
output mode) are marked with code 00H.
The output interface also arbitrates the transfer between
scaled video data and sliced text data over the I port
output.
The bits VITX1 and VITX0 (subaddress 86H) are used to
control the arbitration.
ww
As a further operation the serialization of the internal 32-bit
Dwords to 8-bit or optional 16-bit output, as well as the
insertion of the extended ITU 656 codes (SAV/EAV for
video data, ANC or SAV/EAV codes for sliced text data)
are done here.
• Output field ID
For handshake with the VGA controller, or other memory
or bus interface circuitry, programmable FIFO flags are
provided; see Section 8.6.2.
• Start and end of vertical active video range
• Start and end of active video line
• Data qualifier or gated clock
• Actually activated programming page (if CONLH is
used)
• Threshold controlled FIFO filling flags (empty, full, filled)
• Sliced data marker.
2004 Jul 22
WST625
reserved
-d
1011
8.6
FRAMING CODE
m
DT[3:0]
62H[3:0]
61
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.6.1
SAA7118
FSI[2:0] defines the horizontal packing of the data,
FOI[1:0] defines how many Y only lines are expected,
before a Y/C line will be formatted. If FYSK is set to logic 0
preceding Y only lines will be skipped, and the output will
always start with a Y/C line.
SCALER OUTPUT FORMATTER
(SUBADDRESSES 93H AND C3H)
m
The output formatter organizes the packing into the output
FIFO. The following formats are available:
Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1, Y-CB-CR 4 : 2 : 0,
Y-CB-CR 4 : 1 : 0 and Y only (e.g. for raw samples). The
formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0]
93H[4:3] and FYSK[93H[5]].
co
Additionally the output formatter limits the amplitude range
of the video data (controlled by ILLV[85H[5]]); see
Table 18.
Table 16 Byte stream for different output formats
OUTPUT FORMAT
z.
The data formats are defined on Dwords, or multiples, and
are similar to the video formats as recommended for PCI
multimedia applications (compares to SAA7146A), but
planar formats are not supported.
BYTE SEQUENCE FOR 8-BIT OUTPUT MODES
CB0
Y0
CR0
Y1
CB2
Y-CB-CR 4 : 1 : 1
CB0
Y0
CR0
Y1
CB4
Y only
Y0
Y1
Y2
Y3
Y4
Table 17 Explanation to Table 16
NAME
Y2
CR2
Y3
CB4
Y4
CR4
Y5
CB6
Y6
Y2
CR4
Y3
Y4
Y5
Y6
Y7
CB 8
Y8
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
-d
Y-CB-CR 4 : 2 : 2
EXPLANATION
CB (B − Y) colour difference component, pixel number n = 0, 2, 4 to 718
CBn
Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719
CRn
CR (R − Y) colour difference component, pixel number n = 0, 2, 4 to 718
yc
Yn
Table 18 Limiting range on I port
VALID RANGE
SUPPRESSED CODES (HEXADECIMAL VALUE)
DECIMAL VALUE
HEXADECIMAL VALUE
LOWER RANGE
UPPER RANGE
0
1 to 254
01 to FE
00
FF
8 to 247
08 to F7
00 to 07
F8 to FF
1
8.6.2
w.
LIMIT STEP
ILLV[85H[5]]
VIDEO FIFO (SUBADDRESS 86H)
These are:
• The FIFO Almost Empty (FAE) flag
The video FIFO at the scaler output contains 32 Dwords.
That corresponds to 64 pixels in 16-bit Y-CB-CR 4 : 2 : 2
format. But as the entire scaler can act as a pipeline buffer,
the actual available buffer capacity for the image port is
much higher, and can exceed beyond a video line.
ww
• The FIFO Combined Flag (FCF) or FIFO filled, which is
set at almost full level and reset, with hysteresis, only
after the level crosses below the almost empty mark
• The FIFO Almost Full (FAF) flag
The image port, and the video FIFO, can operate with the
video source clock (synchronous mode) or with an
externally provided clock (asynchronous and burst mode),
as appropriate for the VGA controller or attached frame
buffer.
• The FIFO Overflow (FOVL) flag.
The video FIFO provides 4 internal flags, reporting to what
extent the FIFO is actually filled.
The state of this flag can be seen on the pins IGP0 or
IGP1. The pin mapping is defined by subaddresses
84H and 85H; see Section 9.6.
2004 Jul 22
The trigger levels for FAE and FAF are programmable by
FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0]
(16, 8, 4, empty).
62
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
If the video data is transferred without any interrupt and the
video FIFO does not need to buffer any output pixel, the
text data is inserted after the end of a scaled video line,
normally during the blanking interval of the video.
TEXT FIFO
The data of the internal VBI data slicer is collected in the
text FIFO before the transmission over the I port is
requested (normally before the video window starts). It is
partitioned into two FIFO sections. A complete line is filled
into the FIFO before a data transfer is requested.
So normally, one line of text data is ready for transfer,
while the next text line is collected. Thus sliced text data is
delivered as a block of qualified data, without any
qualification gaps in the byte stream of the I port.
DATA STREAM CODING AND REFERENCE SIGNAL
GENERATION (SUBADDRESSES 84H, 85H AND 93H)
co
8.6.5
m
8.6.3
SAA7118
As H and V reference signals are logic 1, active gate
signals are generated, which frame the transfer of the valid
output data. As an alternative to the gates, H and V trigger
pulses are generated on the rising edges of the gates.
The decoded VBI data is collected in the dedicated VBI
data FIFO. After the capture of a line has been completed,
the FIFO can be streamed through the image port,
preceded by a header, giving line number and standard.
z.
Due to the dynamic FIFO behaviour of the complete scaler
path, the output signal timing has no fixed timing
relationship to the real-time input video stream. So fixed
propagation delays, in terms of clock cycles, related to the
analog input cannot be defined.
The VBI data period can be signalled via the sliced data
flag on pin IGP0 or IGP1. The decoded VBI data is lead by
the ITU ancillary data header (DID[5:0] 5DH[5:0] at value
<3EH) or by SAV/EAV codes selectable by DID[5:0] at
value 3EH or 3FH. Pin IGP0 or IGP1 is set if the first byte
of the ANC header is valid on the I port bus. It is reset if an
SAV occurs. So it may frame multiple lines of text data
output, in the event that the video processing starts with a
distance of several video lines to the region of text data.
Valid sliced data from the text FIFO is available on the
I port as long as the IGP0 or IGP1 flag is set and the data
qualifier is active on pin IDQ.
The data stream is accompanied by a data qualifier.
Additionally invalid data cycles are marked with code 00H.
-d
If ITU 656 like codes are not required, they can be
suppressed in the output stream.
As a further option, it is possible to provide the scaler with
an external gating signal on pin ITRDY. Thereby making it
possible to hold the data output for a certain time and to
get valid output data in bursts of a guaranteed length.
• RECODE = 0: values 00H and FFH may occur in the
data stream as detected.
Table 19 shows the relevant and supported SAV and EAV
coding.
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• RECODE = 1: values 00H and FFH will be recoded to
even parity values 03H and FCH
The sketched reference signals and events can be
mapped to the I port output pins IDQ, IGPH, IGPV, IGP0
and IGP1. For flexible use the polarities of all the outputs
can be modified. The default polarity for the qualifier and
reference signals is logic 1 (active).
8.6.4
w.
The decoded VBI data is presented in two different data
formats, controlled by bit RECODE.
VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H)
ww
Sliced text data and scaled video data are transferred over
the same bus, the I port. The mixed transfer is controlled
by an arbitration circuit.
2004 Jul 22
63
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MSB(2) OF SAV/EAV BYTE = 0
EVENT DESCRIPTION
MSB(2) OF SAV/EAV BYTE = 1
COMMENT
FIELD ID = 0
FIELD ID = 1
FIELD ID = 0
FIELD ID = 1
Next pixel is FIRST pixel of any active
line
0E
49
80
C7
HREF = active;
VREF = active
Previous pixel was LAST pixel of any
active line, but not the last
13
.y
54
9D
DA
HREF = inactive;
VREF = active
25
62
AB
EC
HREF = active;
VREF = inactive
B6
F1
HREF = inactive;
VREF = inactive
Next pixel is FIRST pixel of any
V-blanking line
Previous pixel was LAST pixel of the
last active line or of any V-blanking line
No valid data, don’t capture and don’t
increment pointer
Notes
38
1. The leading byte sequence is: FFH-00H-00H.
64
2. The MSB of the SAV/EAV code byte is controlled by:
c-
7F
00
IDQ pin inactive
dz
a) Scaler output data: task A ⇒ MSB = CONLH[90H[7]]; task B ⇒ MSB = CONLH[C0H[7]].
.c
b) VBI data slicer output data: DID[5:0] 5DH[5:0] = 3EH ⇒ MSB = 1; DID[5:0] 5DH[5:0] = 3FH ⇒ MSB = 0.
...
invalid data
or
end of raw VBI line
timing reference code
...
FF
FF
00
00
00
00
00
00
internal header
SAV SDID DC
IDI1
sliced data
IDI2 D1_3 D1_4 D2_1
and filling data
...
DDC_3 DDC_4 CS
D1_1 D1_2
EAV
ANC header
00
FF
internal header
FF
DID SDID DC
IDI1
om
invalid data
FF
00
00
00
ANC data output is only filled up
to the Dword boundary
sliced data
IDI2 D1_3 D1_4 ... DDC_3 DDC_4 CS
BC
timing reference code
BC
00
...
MHB549
SAA7118
Fig.37 Sliced data formats on the I port in 8-bit mode.
...
00
Product specification
ANC header active for DID (subaddress 5DH) <3EH
00
EAV
Philips Semiconductors
ww
w
SAV/EAV CODES ON I PORT(1) (HEX)
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
Table 19 SAV/EAV codes on I port
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 20 Explanation to Fig.37
NAME
EXPLANATION
start of active data; see Table 21
SDID
sliced data identification: NEP(1), EP(2), SDID5 to SDID0, freely programmable via I2C-bus subaddress
5EH, D5 to D0, e. g. to be used as source identifier
DC
Dword count: NEP(1), EP(2), DC5 to DC0. DC describes the number of succeeding 32-bit words:
co
m
SAV
• For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH)
• For ANC mode it is: DC = 1⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and
n = number of decoded bytes according to the chosen text standard.
It should be noted that the number of valid bytes inside the stream can be seen in the BC byte.
internal data identification 1: OP(3), FID (field 1 = 0, field 2 = 1),
LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 21
IDI2
internal data identification 2: OP(3), LineNumber2 to LineNumber0,
DataType3 to DataType0 = Dword 1 byte 2; see Table 21
z.
IDI1
Dword number n, byte number m
last Dword byte 4, note: for SAV/EAV framing DC is fixed to 0BH, missing data bytes are filled up; the fill
value is A0H
CS
the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the DDC_4 byte
BC
number of valid sliced bytes counted from the IDI1 byte
EAV
end of active data; see Table 21
Notes
-d
Dn_m
DDC_4
1. Inverted EP (bit D7); for EP see note 2.
yc
2. Even parity (bit D6) of bits D5 to D0.
ww
w.
3. Odd parity (bit D7) of bits D6 to D0.
2004 Jul 22
65
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 21 Bytes stream of the data slicer
NICK
NAME
D6
D5
D4
D3
subaddress
5DH = 00H
NEP(1)
EP(2)
0
1
0
subaddress 5DH;
D5 = 1
NEP(1)
EP(2)
0
subaddress 5DH
D5 = 3EH; note 5
1
FID(3)
V(6)
H(7)
P3
P2
P1
P0
subaddress 5DH
D5 = 3FH; note 5
0
FID(3)
V(6)
H(7)
P3
P2
P1
P0
programmable via
subaddress 5EH
NEP(1)
EP(2)
DC(8)
NEP(1)
EP(2)
DC5
DC4
DC3
DC2
DC1
DC0
IDI1
OP(9)
FID(3)
LN8(10)
LN7(10)
LN6(10)
LN5(10)
LN4(10)
LN3(10)
IDI2
OP(9)
LN2(10)
LN1(10)
LN0(10)
DT3(11)
DT2(11)
DT1(11)
DT0(11)
check sum byte
CS6
CS6
CS5
CS4
CS3
CS2
CS1
CS0
valid byte count
OP(9)
0
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
BC
Notes
1. NEP = inverted EP (see note 2).
2. EP = Even Parity of bits D5 to D0.
3. FID = 0: field 1; FID = 1: field 2.
FID(3)
I1(4)
D0
I0(4)
co
D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH]
z.
CS
D1
D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH]
-d
SDID
D2
m
D7
DID,
SAV,
EAV
COMMENT
yc
4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1:
line 24 to end of field.
5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value.
6. V = 0: active video; V = 1: blanking.
7. H = 0: start of line; H = 1: end of line.
w.
8. DC = Data Count in Dwords according to the data type.
9. OP = Odd Parity of bits D6 to D0.
10. LN = Line Number.
ww
11. DT = Data Type according to table.
2004 Jul 22
66
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.7
See Table 22 for examples.
Audio clock generation
(subaddresses 30H to 3FH)
Remark: For standard applications the synthesized audio
clock AMCLK can be used directly as master clock and as
input clock for port AMXCLK (short cut) to generate
ASCLK and ALRCLK. For high-end applications it is
recommended to use an external analog PLL circuit to
enhance the performance of the generated audio clock.
co
m
The SAA7118 incorporates the generation of a field-locked
audio clock as an auxiliary function for video capture.
An audio sample clock, that is locked to the field
frequency, ensures that there is always the same
predefined number of audio samples associated with a
field, or a set of fields. This ensures synchronous playback
of audio and video after digital recording (e.g. capture to
hard disk), MPEG or other compression, or non-linear
editing.
MASTER AUDIO CLOCK
z.
8.7.1
SAA7118
The audio clock is synthesized from the same crystal
frequency as the line-locked video clock is generated. The
master audio clock is defined by the parameters:
audio frequency
ACPF[17:0] = round  ------------------------------------------
 field frequency 
-d
• Audio master Clocks Per Field, ACPF[17:0] 32H[1:0]
31H[7:0] 30H[7:0] according to the equation:
• Audio master Clocks Nominal Increment, ACNI[21:0]
36H[5:0] 35H[7:0] 34H[7:0] according to the equation:
yc
audio frequency
23
ACNI[21:0] = round  --------------------------------------------- × 2 
 crystal frequency

Table 22 Programming examples for audio master clock generation
XTALO
(MHz)
FIELD
(Hz)
ACPF
DECIMAL
ACNI
HEX
DECIMAL
HEX
32.11
24.576
w.
AMCLK = 256 × 48 kHz (12.288 MHz)
50
245760
3C000
3210190
30FBCE
59.94
205005
320CD
3210190
30FBCE
50
−
−
−
−
59.94
−
−
−
−
50
225792
37200
2949362
2D00F2
59.94
188348
2DFBC
2949362
2D00F2
50
225792
37200
3853517
3ACCCD
59.94
188348
2DFBC
3853 517
3ACCCD
ww
AMCLK = 256 × 44.1 kHz (11.2896 MHz)
32.11
24.576
AMCLK = 256 × 32 kHz (8.192 MHz)
32.11
24.576
2004 Jul 22
50
163840
28000
2140127
20A7DF
59.94
136670
215DE
2140127
20A7DF
50
163840
28000
2796203
2AAAAB
59.94
136670
215DE
2796203
2AAAAB
67
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
8.7.2
SAA7118
SIGNALS ASCLK AND ALRCLK
m
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for
channel-select. The frequencies of these signals are defined by the following parameters:
co
• SDIV[5:0] 38H[5:0] according to the equation:
f AMXCLK
f AMXCLK
f ASCLK = ------------------------------------- ⇒ SDIV[5:0] = -------------------- – 1
( SDIV + 1 ) × 2
2f ASCLK
f ASCLK
f ASCLK
• LRDIV[5:0] 39H[5:0] according to the equation: f ALRCLK = -------------------------- ⇒ LRDIV[5:0] = ----------------------LRDIV × 2
2f ALRCLK
See Table 23 for examples.
12.288
11.2896
8.192
8.7.3
SDIV
ASCLK
(kHz)
DECIMAL
HEX
1536
3
03
768
7
07
1411.2
3
03
2822.4
1
1024
3
2048
1
OTHER CONTROL SIGNALS
ALRCLK
(kHz)
HEX
16
10
48
44.1
01
03
32
01
LRDIV
DECIMAL
-d
AMXCLK
(MHz)
z.
Table 23 Programming examples for ASCLK/ALRCLK clock generation
8
08
16
10
32
10
16
10
32
10
yc
Further control signals are available to define reference clock edges and vertical references; see Table 24.
Table 24 Control signals for reference clock edges and vertical references
SIGNAL
APLL[3AH[3]]
DESCRIPTION
Audio PLL mode
w.
0 = PLL closed
1 = PLL open
AMVR[3AH[2]]
Audio Master clock Vertical Reference
0 = internal V
1 = external V
LRPH[3AH[1]]
ALRCLK phase
ww
0 = invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1 = don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
SCPH[3AH[0]]
ASCLK phase
0 = invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1 = don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
2004 Jul 22
68
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
9
Component signals with e.g. sync-on-Y or sync-on-green
are also supported; they are fed to two ADC channels, one
for the video contents, the other for sync conversion.
Additionally, there are four differential reference inputs,
which must be connected to ground via a capacitor
equivalent to the decoupling capacitors at the 16 inputs.
There are no peripheral components required other than
these decoupling capacitors and 18 Ω/56 Ω termination
resistors, one set per connected input signal; see
application example in Fig.47. Four anti-alias filters are
integrated.
INPUT/OUTPUT INTERFACES AND PORTS
The SAA7118 has 5 different I/O interfaces:
m
• Analog video input interface, for analog CVBS and/or
Y and C input signals and/or component video signals
• Audio clock port
co
• Digital real-time signal port (RT port)
• Digital video expansion port (X port), for unscaled digital
video input and output
• Digital image port (I port) for scaled video data output
and programming
Clamp and gain control for the four ADCs are also
integrated. An analog video output (pin AOUT) is provided
for testing purposes.
z.
• Digital host port (H port) for extension of the image port
or expansion port from 8 to 16-bit.
9.1
SAA7118
Analog terminals
Table 25 Analog pin description
I/O
AI11 to AI14
J2, K1, K2 and L3
(27, 29, 31 and 34)
I
AI21 to AI24
G4, G3, H2 and J3
(19, 21, 23 and 26)
AI31 to AI34
E3, F2, F3 and G1
(11, 13, 15 and 18)
AI41 to AI44
B1, D2, D1 and E1
(2, 5, 7 and 10)
M1 (36)
AI1D, AI2D,
K3, H1, F1 and D3
AI3D and AI4D (30, 22, 14 and 6)
Note
analog video signal inputs, e.g. 16 CVBS signals or
eight Y/C pairs, or four RGB plus separate sync (or
Y-PB-PR plus separate sync) signal groups can be
connected simultaneously to this device; many
combinations are possible; see Figs 51 to 91
w.
AOUT
DESCRIPTION
MODE5 to MODE0
O
analog video output, for test purposes
AOSL2 to AOSL0
I
analog reference pins for differential ADC operation;
connect to ground via 47 nF
−
ww
1. Pin numbers for QFP160 in parenthesis.
2004 Jul 22
BIT
yc
PIN(1)
SYMBOL
-d
The SAA7118 has 16 analog inputs AI41 to AI44,
AI31 to AI34, AI21 to AI24 and AI11 to AI14 for composite
video CVBS or S-video Y/C signal pairs or component
video input signals RGB plus separate sync (or Y-PB-PR
plus separate sync).
69
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
9.2
Audio clock signals
An audio master clock AMCLK and two divided clocks
ASCLK and ALRCLK are generated:
The SAA7118 also synchronizes the audio clock and
sampling rate to the video frame rate, via a very slow PLL.
This ensures that the multimedia capture and compression
processes always gather the same predefined number of
samples per video frame.
m
• ASCLK: can be used as audio serial clock
• ALRCLK: audio left/right channel clock.
co
The ratios are programmable; see Section 8.7.
Table 26 Audio clock pin description
SYMBOL PIN(1) I/O
SAA7118
DESCRIPTION
BIT
P11
(72)
O
audio master clock output
ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] and
ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0]
AMXCLK
M12
(76)
I
external audio master clock input for the clock
division circuit, can be directly connected to
output AMCLK for standard applications
−
ASCLK
N11
(74)
O
serial audio clock output, can be synchronized
to rising or falling edge of AMXCLK
SDIV[5:0] 38H[5:0] and SCPH[3AH[0]]
ALRCLK
P12
(75)
O
audio channel (left/right) clock output, can be
LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]
synchronized to rising or falling edge of ASCLK
-d
z.
AMCLK
Note
1. Pin numbers for QFP160 in parenthesis.
9.3
Clock and real-time synchronization signals
yc
For the generation of the line-locked video (pixel) clock
LLC, and of the frame-locked audio serial bit clock, a
crystal accurate frequency reference is required. An
oscillator is built-in for fundamental or third harmonic
crystals. The supported crystal frequencies are
32.11 or 24.576 MHz (defined during reset by strapping
pin ALRCLK).
w.
Alternatively pin XTALI can be driven from an external
single-ended oscillator.
ww
The crystal oscillation can be propagated as a clock to
other ICs in the system via pin XTOUT.
2004 Jul 22
70
The Line-Locked Clock (LLC) is the double pixel clock of
nominal 27 MHz. It is locked to the selected video input,
generating baseband video pixels according to “ITU
recommendation 601”. In order to support interfacing
circuits, a direct pixel clock (LLC2) is also provided.
The pins for line and field timing reference signals are
RTCO, RTS1 and RTS0. Various real-time status
information can be selected for the RTS pins. The signals
are always available (output) and reflect the
synchronization operation of the decoder part in the
SAA7118. The function of the RTS1 and RTS0 pins can
be defined by bits RTSE1[3:0] 12H[7:4] and RTSE0[3:0]
12H[3:0].
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 27 Clock and real-time synchronization signals
SYMBOL PIN(1) I/O
DESCRIPTION
BIT
m
Crystal oscillator
−
XTALI
B4
(155)
I
input for crystal oscillator or reference clock
XTALO
A3
(156)
O
output of crystal oscillator
XTOUT
A2
(158)
O
reference (crystal) clock output drive (optional)
co
−
Real-time signals (RT port)
XTOUTE[14H[3]]
P4
(46)
O
line-locked clock, nominal 27 MHz, double pixel clock locked to the
selected video input signal
−
LLC2
N5
(48)
O
line-locked pixel clock, nominal 13.5 MHz
−
RTCO
L10
(71)
O
real-time control output, transfers real-time status information
−
supporting RTC level 3.1 (see document “RTC Functional Description”,
available on request)
RTS0
M10
(69)
O
real-time status information line 0, can be programmed to carry various RTSE0[3:0] 12H[3:0]
real-time information; see Table 57
RTS1
N10
(70)
O
real-time status information line 1, can be programmed to carry various RTSE1[3:0] 12H[7:4]
real-time information; see Table 58
-d
z.
LLC
Note
9.4
9.4.1
Interrupt handling
INTERRUPT FLAGS
yc
1. Pin numbers for QFP160 in parenthesis.
9.4.1.1
w.
The pin INT_A is an open-drain output (active LOW). All
flags can be independently enabled. For the default setting
all flags are disabled after reset. For the description of
interrupt mask registers; see Section 15.4.
COPRO, COLSTR and TYPE3: various levels of copy
protection have changed.
9.4.1.3
VBI data slicer
VPSV: VPS identification found or lost.
Power state
PPV: PALplus identification found or lost.
PRDON: a power fail has been detected during normal
operation, the device needs re-programming.
CCV: Closed caption identification found or lost.
9.4.1.4
Video decoder
ww
9.4.1.2
DCSTD[1:0]: detected colour standard has changed or
colour lost.
Scaler
ERROF: scaler output formatting error detected.
INTL: interlaced/non-interlaced source detected.
HLCK: horizontal PLL state changed (locked ↔ unlocked).
9.4.2
HLVLN: vertical lock state changed (locked ↔ unlocked).
The status information read after an interrupt will always
be the LATEST state, that means the status will not be
‘frozen’ when an interrupt is being generated. Therefore, if
there is a long time between interrupt generation and
status reading, the original trigger condition might have
been overridden by the present state.
FIDT: detected field frequency has changed
(50 Hz ↔ 60 Hz).
RDCAP: ready for capture (true ↔ false).
2004 Jul 22
71
STATUS READING CONDITIONS
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
9.4.3
The expansion port consists of two groups of signals/pins:
ERASING CONDITIONS
• 8-bit data, I/O, regularly components video Y-CB-CR
4 : 2 : 2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw
video samples (e.g. ADC test). In input mode the data
bus can be extended to 16-bit by pins HPD7 to HPD0.
The status flags are grouped into four 8-bit registers.
m
The interrupt flag will only be cleared on a read access to
the status register in which the signal is located which
caused the interrupt. This implies that it is sufficient to clear
the interrupt by reading only those registers which have
been enabled by their corresponding masks.
co
• Clock, synchronization and auxiliary signals,
accompanying the data stream, I/O.
As output, these are direct copies of the decoder signals.
Priority: If a new trigger condition occurs at the SAME time
(clock) on which a status is being read, the flag will NOT
be cleared.
The data transfers through the expansion port represent a
single D1 port, with half duplex mode. The SAV and EAV
codes may be inserted optionally for data input (controlled
by bit XCODE[92H[3]]). The input/output direction is
switched for complete fields only.
Video expansion port (X port)
z.
9.5
The expansion port is intended for transporting video
streams image data from other digital video circuits such
as MPEG encoder/decoder and video phone codec, to the
image port (I port).
XDQ
B7 (144)
XRDY
A6 (146)
I/O data valid flag of the expansion port input (qualifier):
if output, then decoder (HREF and VGATE) gate (see
Fig.30)
−
O
data request flag = ready to receive, to work with optional
buffer in external device, to prevent internal buffer
overflow;
second function: input related task flag A/B
XRQT[83H[2]]
C7 (141)
I/O horizontal reference signal for the X port:
as output: HREF or HS from the decoder (see Fig.30);
as input: a reference edge for horizontal input timing and a
polarity for input field ID detection can be defined
XRHS[13H[6]],
XFDH[92H[6]]
and
XDH[92H[2]]
D8 (140)
I/O vertical reference signal for the X port:
as output: V123 or field ID from the decoder,
see Figs 28 and 29;
as input: a reference edge for vertical input timing and for
input field ID detection can be defined
XRVS[1:0]
13H[5:4],
XFDV[92H[7]]
and XDV[1:0]
92H[5:4]
B11 (126)
I
port control: switches X port input 3-state
Note
1. Pin numbers for QFP160 in parenthesis.
2004 Jul 22
OFTS[2:0]
13H[2:0],
91H[7:0] and
C1H[7:0]
XCKS[92H[0]]
ww
XTRI
BIT
I/O clock at expansion port: if output, then copy of LLC;
as input normally a double pixel clock of up to 32 MHz or a
gated clock (clock gated with a qualifier)
w.
A7 (143)
XRV
DESCRIPTION
C11, A11, B10, A10, I/O X port data: in output mode controlled by decoder section,
B9, A9, B8 and A8
data format see Table 29; in input mode Y-CB-CR 4 : 2 : 2
(127, 128, 130, 131,
serial input data or luminance part of a 16-bit
134, 135, 138 and 139)
Y-CB-CR 4 : 2 : 2 input
XCLK
XRH
I/O
yc
XPD7 to
XPD0
PIN(1)
-d
Table 28 Signals dedicated to the expansion port
SYMBOL
SAA7118
72
XPE[1:0]
83H[1:0]
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
9.5.1
The amplitude and offset of the CVBS signal is
programmable via RAWG7 to RAWG0 and
RAWO7 to RAWO0; see Chapter 15, Tables 64 and 65.
The nominal levels are illustrated in Fig.20.
X PORT CONFIGURED AS OUTPUT
m
If data output is enabled at the expansion port, then the
data stream from the decoder is presented. The data
format of the 8-bit data bus is dependent on the chosen
data type, selectable by the line control registers
LCR2 to LCR24; see Table 4. In contrast to the image
port, the sliced data format is not available on the
expansion port. Instead, raw CVBS samples are always
transferred if any sliced data type is selected.
co
The relationship of LCR programming to line numbers is
described in Section 8.3, Tables 5 to 8.
The data type selections by LCR are overruled by setting
OFTS2 = 1 (subaddress 13H bit D2). This setting is mainly
intended for device production test. The VPO-bus carries
the upper or lower 8 bits of the two ADCs depending on the
OFTS[1:0] 13H[1:0] settings; see Table 59. The input
configuration is done via MODE[5:0] 02H[5:0] settings; see
Table 41. If a Y/C mode is selected, the expansion port
carries the multiplexed output signals of both ADCs, and in
CVBS mode the output of only one ADC. No timing
reference codes are generated in this mode.
Some details of data types on the expansion port are as
follows:
z.
• Active video (data type 15): contains component
Y-CB-CR 4 : 2 : 2 signal, 720 active pixels per line. The
amplitude and offsets are programmable via
DBRI7 to DBRI0, DCON7 to DCON0,
DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and
OFFV0. The nominal levels are illustrated in Fig.19.
Remark: The LSBs (bit D0) of the ADCs are also available
on pin RTS0; see Table 57.
The SAV/EAV timing reference codes define the start and
end of valid data regions. The ITU-blanking code
sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the
horizontal blanking period between EAV and SAV.
-d
• Test line (data type 6): is similar to the active video
format, with some constraints within the data
processing:
SAA7118
– adaptive chrominance comb filter, vertical filter
(chrominance comb filter for NTSC standards, PAL
phase error correction) within the chrominance
processing are disabled
The position of the F-bit is constant in accordance with
ITU 656; see Tables 31 and 32.
yc
– adaptive luminance comb filter, peaking and
chrominance trap are bypassed within the luminance
processing.
The F and V bits change synchronously with the EAV
code.
w.
This data type is defined for future enhancements.
It could be activated for lines containing standard test
signals within the vertical blanking period. Currently the
most sources do not contain test lines. The nominal
levels are illustrated in Fig.19.
The V-bit can be generated in two different ways
(see Tables 31 and 32) controlled via OFTS1 and OFTS0;
see Table 59.
• Raw samples (data types 0 to 5 and 7 to 14): CB-CR
samples are similar to data type 6, but CVBS samples
are transferred instead of processed luminance samples
within the Y time slots.
ww
Table 29 Data format on the expansion port
BLANKING
PERIOD
...
80
TIMING
REFERENCE
CODE (HEX)(1)
720 PIXELS Y-CB-CR 4 : 2 : 2 DATA(2)
TIMING
REFERENCE
CODE (HEX)(1)
BLANKING
PERIOD
10 FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80
10
...
Notes
1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to 010; see Table 59. In this
event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.
2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced
by CVBS samples.
2004 Jul 22
73
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 30 SAV/EAV format on expansion port XPD7 to XPD0
field bit
BIT D4
(H)
vertical blanking bit
BIT D3 BIT D2 BIT D1 BIT D0
(P3)
(P2)
(P1)
(P0)
format
1st field: F = 0
VBI: V = 1
2nd field: F = 1
active video: V = 0
reserved; evaluation not
H = 0 in SAV format recommended (protection bits
according to ITU 656)
H = 1 in EAV format
co
1
BIT D5
(V)
m
BIT D6
(F)
BIT D7
for vertical timing see Tables 31 and 32
Table 31 525 lines/60 Hz vertical timing
V
F (ITU 656)
1
4 to 19
0
20
0
21
0
22 to 261
0
262
0
263
0
264 and 265
0
266 to 282
1
283
1
1
525
1
according to selected VGATE
position type via VSTA and VSTO
(subaddresses 15H to 17H);
see Tables 61 to 63
1
0
0
0
0
0
1
1
0
yc
284
285 to 524
OFTS[2:0] = 001
z.
1 to 3
OFTS[2:0] = 000 (ITU 656)
-d
LINE NUMBER
0
1
0
1
0
Table 32 625 lines/50 Hz vertical timing
1 to 22
23
24 to 309
310
OFTS[2:0] = 000 (ITU 656)
OFTS[1:0] = 10
0
1
0
0
0
0
according to selected VGATE
position type via VSTA and VSTO
(subaddresses 15H to 17H);
see Tables 61 to 63
0
0
0
1
1
1
ww
311 and 312
313 to 335
V
F (ITU 656)
w.
LINE NUMBER
336
1
0
337 to 622
1
0
623
1
0
624 and 625
1
1
2004 Jul 22
74
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
9.5.2
SAA7118
The data formats at the image port are defined in Dwords
of 32 bits (4 bytes), such as the related FIFO structures.
However the physical data stream at the image port is only
16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to
HPD0 are used for chrominance data. The four bytes of
the Dwords are serialized in words or bytes.
X PORT CONFIGURED AS INPUT
m
If the data input mode is selected at the expansion port,
then the scaler can select its input data stream from the
on-chip video decoder, or from the expansion port
(controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial
Y-CB-CR 4 : 2 : 2, or subsets for other sampling schemes,
or raw samples from an external ADC may be input (see
also bits FSC[2:0] 91H[2:0]). The input stream must be
accompanied by an external clock (XCLK), qualifier XDQ
and reference signals XRH and XRV. Instead of the
reference signal, embedded SAV and EAV codes
according to ITU 656 are also accepted. The protection
bits are not evaluated.
co
Available formats are as follows:
• Y-CB-CR 4 : 2 : 2
• Y-CB-CR 4 : 1 : 1
• Raw samples
• Decoded VBI data.
z.
For handshake with the receiving VGA controller, or other
memory or bus interface circuitry, F, H and V reference
signals and programmable FIFO flags are provided. The
information is provided on pins IGP0, IGP1, IGPH and
IGPV. The functionality on these pins is controlled via
subaddresses 84H and 85H.
XRH and XRV carry the horizontal and vertical
synchronization signals for the digital video stream
through the expansion port. The field ID of the input video
stream is carried in the phase (edge) of XRV and state of
XRH, or directly as FS (frame sync, odd/even signal) on
the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]]
and XDV[1:0] 92H[5:4]).
-d
VBI data is collected over an entire line in its own FIFO,
and transferred as an uninterrupted block of bytes.
Decoded VBI data can be signed by the VBI flag on pin
IGP0 or IGP1.
yc
The trigger events on XRH (rising/falling edge) and XRV
(rising/falling/both edges) for the scalers acquisition
window are defined by XDV[1:0] 92H[5:4] and
XDH[92H[2]]. The signal polarity of the qualifier can also
be defined (bit XDQ[92H[1]]). Alternatively to a qualifier,
the input clock can be applied to a gated clock (clock gated
with a data qualifier, controlled by bit XCKS[92H[0]]).
In this event, all input data will be qualified.
9.6
w.
As the VBI data slicer may have different requirements for
its input reference signals from X port XRV, XRH, XDQ,
XCLK and XPD7 to XPD0, a second set of parameters is
available for defining the meaning of the X port input
signals and polarities for the VBI data slicer input path.
These bits are defined in subaddresses 81H and 82H.
Image port (I port)
ww
The image port transfers data from the scaler as well as
from the VBI data slicer, if selected (maximum 33 MHz).
The reference clock is available at the ICLK pin, as an
output, or as an input (maximum 33 MHz). As output, ICLK
is derived from the line-locked decoder or expansion port
input clock. The data stream from the scaler output is
normally discontinuous. Therefore valid data during a
clock cycle is accompanied by a data qualifying (data
valid) flag on pin IDQ. For pin constrained applications the
IDQ pin can be programmed to function as a gated clock
output (bit ICKS2[80H[2]]).
2004 Jul 22
75
As scaled video data and decoded VBI data may come
from different and asynchronous sources, an arbitration
scheme is needed. Normally the VBI data slicer has
priority.
The image port consists of the pins and/or signals, as
listed in Table 33.
For pin constrained applications, or interfaces, the relevant
timing and data reference signals can also get encoded
into the data stream. Therefore the corresponding pins do
not need to be connected. The minimum image port
configuration requires 9 pins only, i.e. 8 pins for data
including codes, and 1 pin for clock or gated clock. The
inserted codes are defined in close relationship to the
ITU-R BT.656 (D1) recommendation, where possible.
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
• Decoded VBI data is transported as Ancillary (ANC)
data, two modes:
The following deviations from “ITU 656 recommendation”
are implemented at the SAA7118 image port interface:
– direct decoded VBI data bytes (8-bit) are directly
placed in the ANC data field, 00H and FFH codes
may appear in data block (violation to ITU-R BT.656)
• There may be more or less than 720 pixels between
SAV and EAV
– recoded VBI data bytes (8-bit) directly placed in ANC
data field, 00H and FFH codes will be recoded to
even parity codes 03H and FCH to suppress invalid
ITU-R BT.656 codes.
co
m
• SAV and EAV codes are only present in those lines,
where data is to be transferred, i.e. active video lines, or
VBI raw samples, no codes for empty lines
• Data content and the number of clock cycles during
horizontal and vertical blanking is undefined, and may
not be constant
z.
• Data stream may be interleaved with not-valid data
codes, 00H, but SAV and EAV 4-byte codes are not
interleaved with not-valid data codes
There are no empty cycles in the ancillary code and its
data field. The data codes 00H and FFH are suppressed
(changed to 01H or FEH respectively) in the active video
stream, as well as in the VBI raw sample stream (VBI
pass-through). Optionally, the number range can be
further limited.
• There may be an irregular pattern of not-valid data, or
IDQ, and as a result, CB-Y-CR-Y is not in a fixed phase
to a regular clock divider
-d
• VBI raw sample streams are enveloped with
SAV and EAV, like normal video
Table 33 Signals dedicated to the image port
IPD7 to
IPD0
PIN(1)
IDQ
L13 (85)
BIT
ICODE[93H[7]], ISWP[1:0]
85H[7:6] and IPE[1:0] 87H[1:0]
I/O continuous reference clock at image port, can
be input or output, as output decoder LLC or
XCLK from X port
ICKS[1:0] 80H[1:0] and IPE[1:0]
87H[1:0]
O
ICKS2[80H[2]], IDQP[85H[0]] and
IPE[1:0] 87H[1:0]
data valid flag at image port, qualifier, with
programmable polarity;
secondary function: gated clock
w.
M14 (84)
K12 (91)
O
horizontal reference output signal, copy of the IDH[1:0] 84H[1:0], IRHP[85H[1]]
H gate signal of the scaler, with programmable and IPE[1:0] 87H[1:0]
polarity; alternative function: HRESET pulse
K14 (90)
O
vertical reference output signal, copy of the
IDV[1:0] 84H[3:2], IRVP[85H[2]]
V gate signal of the scaler, with programmable and IPE[1:0] 87H[1:0]
polarity; alternative function: VRESET pulse
ww
IGPV
DESCRIPTION
K11, J13, J14, I/O I port data
H13, H14, H11,
G12 and G14
(92 to 94, 97 to
100 and 102)
ICLK
IGPH
I/O
yc
SYMBOL
IGP1
K13 (89)
O
general purpose output signal for I port
IDG12[86H[4]], IDG1[1:0] 84H[5:4],
IG1P[85H[3]] and IPE[1:0] 87H[1:0]
IGP0
L14 (87)
O
general purpose output signal for I port
IDG02[86H[5]], IDG0[1:0] 84H[7:6],
IG0P[85H[4]] and IPE[1:0] 87H[1:0]
ITRDY
N12 (77)
I
target ready input signals
−
ITRI
L12 (86)
I
port control, switches I port into 3-state
IPE[1:0] 87H[1:0]
Note
1. Pin numbers for QFP160 in parenthesis.
2004 Jul 22
76
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
9.7
SAA7118
Host port for 16-bit extension of video data I/O (H port)
The H port pins HPD can be used for extension of the data I/O paths to 16-bit.
m
The I port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H port are enabled depending
on the I port enable control. For I8_16 = 0, the HPD output is disabled.
co
Table 34 Signals dedicated to the host port
SYMBOL
PIN(1)
I/O
DESCRIPTION
HPD7 to HPD0
G13, F14, F13, E14, E12,
E13, E11 and D14 (103,
105, 107 and 109 to 113)
I/O
16-bit extension for digital I/O
(chrominance component)
1. Pin numbers for QFP160 in parenthesis.
9.8
9.8.1
Basic input and output timing diagrams I port
and X port
I PORT OUTPUT TIMING
IPE[1:0] 87H[1:0], ITRI[8FH[6]]
and I8_16[93H[6]]
z.
Note
BIT
9.8.2
X PORT INPUT TIMING
At the X port the input timing requirements are the same as
those for the I port output. But different to those below:
• It is not necessary to mark invalid cycles with a 00H
code
-d
The following diagrams illustrate the output timing via the
I port. IGPH and IGPV are logic 1 active gate signals.
If reference pulses are programmed, these pulses are
generated on the rising edge of the logic 1 active gates.
Valid data is accompanied by the output data qualifier on
pin IDQ. In addition invalid cycles are marked with output
code 00H.
• No constraints on the input qualifier (can be a random
pattern)
yc
• XCLK may be a gated clock (XCLK AND external XDQ).
ICLK
IDQ
00
FF
00
00
ww
IPD [ 7:0 ]
w.
The IDQ output pin may be defined to be a gated clock
output signal (ICLK AND internal IDQ).
SAV
00
CB
Remark: All timings illustrated in Figs 38 to 44 are given
for an uninterrupted output stream (no handshake with the
external hardware).
CR
Y
Y
00
CB
Y
CR
Y
00
IGPH
MHB550
Fig.38 Output timing I port for serial 8-bit data at start of a line (ICODE = 1).
2004 Jul 22
77
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
ICLK
IDQ
IPD [ 7:0 ]
CB
CR
Y
Y
00
CB
Y
CR
z.
00
co
m
SAA7118
00
MHB551
-d
IGPH
Y
IDQ
00
CB
Y
CR
Y
00
CB
CR
Y
Y
00
FF
00
ww
IPD [ 7:0 ]
w.
ICLK
yc
Fig.39 Output timing I port for serial 8-bit data at start of a line (ICODE = 0).
00
EAV
00
IGPH
MHB552
Fig.40 Output timing I port for serial 8-bit data at end of a line (ICODE = 1).
2004 Jul 22
78
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
ICLK
IDQ
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
z.
IPD [ 7:0 ]
co
m
SAA7118
MHB553
-d
IGPH
yc
Fig.41 Output timing I port for serial 8-bit data at end of a line (ICODE = 0).
IDQ
w.
ICLK
00
FF
00
00
Y0
Y1
00
Y2
Y3
Yn − 1
Yn
00
FF
00
00
HPD [ 7:0 ]
00
00
SAV
00
CB
CR
00
CB
CR
CB
CR
00
00
EAV
00
ww
IPD [ 7:0 ]
IGPH
MHB554
Fig.42 Output timing for 16-bit data output via I port and H port with codes (ICODE = 1), timing is like 8-bit output,
but packages of 2 bytes per valid cycle.
2004 Jul 22
79
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
co
handbook, full pagewidth
IDQ
z.
IGPH
MHB555
-d
IGPV
yc
Fig.43 H gate and V gate output timing.
handbook, full pagewidth
IDQ
w.
ICLK
00
00
FF
FF
DID
HPD [ 7:0 ]
00
FF
00
00
SAV
ww
IPD [ 7:0 ]
SDID
XX
YY
ZZ
CS
BC
00
00
00
BC
FF
00
00
EAV
sliced data
flag on IGP0
or IGP1
MHB733
Fig.44 Output timing for sliced VBI data in 8-bit serial output mode (dotted graphs for SAV/EAV mode).
2004 Jul 22
80
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
The Boundary Scan Test (BST) functions BYPASS,
EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all
supported; see Table 35. Details about the JTAG
BST-TEST can be found in specification “IEEE Std.
1149.1”. A file containing the detailed Boundary Scan
Description Language (BSDL) description of the SAA7118
is available on request.
10 BOUNDARY SCAN TEST
co
m
The SAA7118 has built-in logic and 5 dedicated pins to
support boundary scan testing which allows board testing
without special hardware (nails). The SAA7118 follows the
“IEEE Std. 1149.1 - Standard Test Access Port and
Boundary-Scan Architecture” set by the Joint Test Action
Group (JTAG) chaired by Philips.
The 5 special pins are Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
Table 35 BST instructions supported by the SAA7118
This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO
when no test operation of the component is required.
EXTEST
This mandatory instruction allows testing of off-chip circuitry and board level interconnections.
SAMPLE
This mandatory instruction can be used to take a sample of the inputs during normal operation of the
component. It can also be used to preload data values into the latched outputs of the boundary scan
register.
CLAMP
This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary scan register is in external test mode.
IDCODE
This optional instruction will provide information on the components manufacturer, part number and
version number.
INTEST
This optional instruction allows testing of the internal logic (no customer support available).
USER1
This private instruction allows testing by the manufacturer (no customer support available).
-d
BYPASS
yc
10.1
DESCRIPTION
z.
INSTRUCTION
Initialization of boundary scan circuit
w.
The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.
ww
To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting the TRST pin
LOW.
10.2
SAA7118
Device identification codes
A device identification register is specified in “IEEE Std.
1149.1b-1994”. It is a 32-bit register which contains fields
for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage
is the possibility to check for the correct ICs mounted after
production and determination of the version number of ICs
during field service.
2004 Jul 22
81
When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between pins TDI and TDO of the IC. The
identification register will load a component specific code
during the CAPTURE_DATA_REGISTER state of the TAP
controller and this code can subsequently be shifted out.
At board level this code can be used to verify component
manufacturer, type and version number. The device
identification register contains 32 bits, numbered 31 to 0,
where bit D31 is the most significant bit (nearest to TDI)
and bit D0 is the least significant bit (nearest to TDO);
see Fig.45.
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
31
12 11
1
nnnn
0111000100011000
00000010101
4-bit
version
code
16-bit part number
11-bit manufacturer
identification
0
1
TDO
co
TDI
LSB
28 27
m
MSB
handbook, full pagewidth
MHB734
z.
Fig.45 32 bits of identification code.
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and
grounded (0 V); all supply pins connected together.
SYMBOL
PARAMETER
CONDITIONS
digital supply voltage
VDDA
analog supply voltage
Vi(A)
input voltage at analog inputs
Vi(n)
input voltage at pins XTALI, SDA and SCL
Vi(D)
input voltage at digital inputs or I/O pins
-d
VDDD
voltage difference between VSSA(n) and VSSD(n)
Tstg
storage temperature
Tamb
ambient temperature
Vesd
electrostatic discharge voltage
yc
∆VSS
Notes
MIN.
MAX.
UNIT
−0.5
+4.6
V
−0.5
+4.6
V
−0.5
+4.6
V
−0.5
VDDD + 0.5
V
outputs in 3-state
−0.5
+4.6
V
outputs in 3-state; note 1
−0.5
+5.5
V
−
100
mV
−65
+150
°C
0
70
°C
human body model; note 2
−
±2000
V
machine model; note 3
−
±150
V
w.
1. Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V.
2. Class 2 according to EIA/JESD22-114-B.
3. Class A according to EIA/JESD22-115-A.
12 THERMAL CHARACTERISTICS
PARAMETER
CONDITIONS
VALUE
UNIT
SAA7118E
38(1)
K/W
SAA7118H
29(1)
K/W
ww
SYMBOL
Rth(j-a)
thermal resistance from junction to ambient
in free air
Note
1. The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and
ground pins must be connected to the power and ground layers directly. An ample copper area direct under the
SAA7118 with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer),
can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In addition the usage
of soldering glue with a high thermal conductance after curing is recommended.
2004 Jul 22
82
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
SYMBOL
PARAMETER
CONDITIONS
MIN.
Supplies
IDDD
digital supply
current
PD
power dissipation
digital part
VDDA
analog supply
voltage
IDDA
analog supply
current
3.0
X port 3-state; 8-bit I port
CVBS mode
V
−
85
−
mA
−
280
−
mW
3.1
3.3
3.5
V
−
75
−
mA
−
130
−
mA
250
−
mA
−
248
−
mW
Y/C mode
−
430
−
mW
component mode
−
825
−
mW
CVBS mode
−
533
−
mW
Y/C mode
−
710
−
mW
component mode
−
1105
1350
mW
−
5
−
mW
75
−
mW
-d
total power
dissipation analog
and digital part
3.6
−
yc
Ptot(A+D)
3.3
CVBS mode
component mode
power dissipation
analog part
UNIT
AOSL1 and AOSL0 = 0
Y/C mode
PA
MAX.
co
digital supply
voltage
TYP.
z.
VDDD
m
13 CHARACTERISTICS
VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 0 to 70 °C (typical values measured at Tamb = 25 °C); timings and levels
refer to drawings and conditions illustrated in Fig.46; unless otherwise specified.
total power
CE pulled down to ground
dissipation analog
and digital part in
power-down mode
Ptot(A+D)(ps)
total power
dissipation analog
and digital part in
power-save mode
I2C-bus controlled via subaddress −
88H = 0FH
clamping current
VI = 1 V DC
−
±8
−
µA
input voltage
(peak-to-peak
value)
for normal video levels 1 V (p-p),
−3 dB termination 18/56 Ω and
AC coupling required; coupling
capacitor is 47 nF
−
0.7
−
V
Zi
input impedance
clamping current off
200
−
−
kΩ
Ci
input capacitance
−
−
10
pF
αcs
channel crosstalk
−
−
−50
dB
Analog part
Iclamp
ww
Vi(p-p)
w.
Ptot(A+D)(pd)
2004 Jul 22
fi < 5 MHz
83
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SYMBOL
PARAMETER
SAA7118
CONDITIONS
MIN.
TYP.
MAX.
UNIT
m
B
analog bandwidth
at −3 dB
−
φdiff
differential phase
amplifier plus anti-alias filter
bypassed
−
−
MHz
2
−
deg
Gdiff
differential gain
amplifier plus anti-alias filter
bypassed
−
2
−
%
fclk(ADC)
ADC clock
frequency
25.4
−
28.6
MHz
LEdc(d)
DC differential
linearity error
−
0.7
−
LSB
LEdc(i)
DC integral
linearity error
−
1
−
LSB
∆GADC
ADC gain
inequality
−
3
−
%
−
+0.3VDD(I2C)
V
z.
deviation
 maximum
- – 1 × 100 ;
 -------------------------------------------------minimum deviation
note 1
Digital inputs
VIL(SCL,SDA)
LOW-level input
voltage pins SDA
and SCL
note 2
VIH(SCL,SDA)
HIGH-level input
voltage pins SDA
and SCL
note 2
VIL(XTALI)
co
7
-d
9-bit analog-to-digital converters
−0.5
VDD(I2C) + 0.5 V
LOW-level CMOS
input voltage pin
XTALI
−0.3
−
+0.8
V
VIH(XTALI)
HIGH-level CMOS
input voltage pin
XTALI
2.0
−
VDDD + 0.3
V
VIL(n)
LOW-level input
voltage all other
inputs
−0.3
−
+0.8
V
HIGH-level input
voltage all other
inputs
2.0
−
5.5
V
input leakage
current
−
−
1
µA
ILI/O
I/O leakage
current
−
−
10
µA
Ci
input capacitance
I/O at high-impedance
−
−
8
pF
SDA at 3 mA sink current
−
−
0.4
V
−0.5
−
+0.6
V
ww
ILI
w.
VIH(n)
yc
0.7VDD(I2C) −
Digital outputs; note 3
VOL(SDA)
LOW-level output
voltage pin SDA
VOL(clk)
LOW-level output
voltage for clocks
2004 Jul 22
84
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
PARAMETER
CONDITIONS
MIN.
HIGH-level output
voltage for clocks
2.4
VOL(n)
LOW-level output
voltage all other
digital outputs
0
VOH(n)
HIGH-level output
voltage all other
digital outputs
output load
capacitance
Tcy
cycle time
δ
duty factors for
tLLCH/tLLC and
tLLC2H/tLLC2
CL = 40 pF
tr
rise time LLC and
LLC2
tf
td(LLC-LLC2)
2.4
−
VDDD + 0.5
V
15
−
50
pF
ns
70
−
78
ns
40
−
60
%
0.2 V to VDDD − 0.2 V
−
−
5
ns
fall time LLC and
LLC2
VDDD − 0.2 V to 0.2 V
−
−
5
ns
delay time
between LLC and
LLC2 output
measured at 1.5 V; CL = 25 pF
−4
−
+8
ns
50 Hz field
−
15625
−
Hz
60 Hz field
−
15734
−
Hz
−
−
5.7
%
−
4433619 −
Hz
−
3579545 −
Hz
PAL M
−
3575612 −
Hz
PAL N
−
3582056 −
Hz
±400
−
−
Hz
MHz
-d
yc
nominal line
frequency
permissible static
deviation
w.
nominal subcarrier PAL BGHI
frequency
NTSC M
lock-in range
ww
∆fsc
V
39
Subcarrier PLL
fsc(nom)
0.4
V
−
Horizontal PLL
∆fhor/fhor(nom)
VDDD + 0.5
UNIT
35
pin LLC
pin LLC2
fhor(nom)
−
z.
Clock output timing (LLC and LLC2); note 4
CL
−
MAX.
co
VOH(clk)
TYP.
m
SYMBOL
SAA7118
Crystal oscillator for 32.11 MHz; note 5
fxtal(nom)
nominal frequency
−
32.11
−
∆fxtal(nom)
permissible
nominal frequency
deviation
−
−
±70 × 10−6
∆fxtal(nom)(T)
permissible
nominal frequency
deviation with
temperature
−
−
±30 × 10−6
2004 Jul 22
85
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SYMBOL
PARAMETER
SAA7118
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CRYSTAL SPECIFICATION (X1)
0
CL
load capacitance
8
Rs
series resonance
resistor
−
C1
motional
capacitance
C0
parallel
capacitance
∆fxtal(nom)(T)
permissible
nominal frequency
deviation with
temperature
CRYSTAL SPECIFICATION (X1)
−
−
pF
40
80
Ω
1.5 ±20% −
fF
−
4.3 ±20% −
pF
24.576
−
MHz
10−6
−
−
±50 ×
−
−
±20 × 10−6
0
−
70
°C
-d
permissible
nominal frequency
deviation
°C
−
−
nominal frequency
∆fxtal(nom)
70
z.
Crystal oscillator for 24.576 MHz; note 5
fxtal(nom)
−
m
ambient
temperature
co
Tamb(X1)
ambient
temperature
CL
load capacitance
8
−
−
pF
Rs
series resonance
resistor
−
40
80
Ω
C1
motional
capacitance
−
1.5 ±20% −
fF
C0
parallel
capacitance
−
3.5 ±20% −
pF
cycle time
31
−
45
ns
duty factors for
tLLCH/tLLC
40
50
60
%
rise time
−
−
5
ns
−
−
5
ns
w.
yc
Tamb(X1)
Clock input timing (XCLK)
Tcy
δ
ww
tr
tf
fall time
Data and control signal input timing X port, related to XCLK input
tSU;DAT
input data set-up
time
10
−
−
ns
tHD;DAT
input data hold
time
6
−
−
ns
2004 Jul 22
86
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SYMBOL
PARAMETER
SAA7118
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock output timing
50
pF
−
39
ns
35
−
65
%
−
−
5
ns
−
−
5
ns
15
Tcy
cycle time
35
δ
duty factors for
tXCLKH/tXCLKL
tr
rise time
0.6 to 2.6 V
tf
fall time
2.6 to 0.6 V
co
output load
capacitance
m
−
CL
15
−
50
pF
4
−
−
ns
−
−
19
ns
-d
z.
Data and control signal output timing X port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default);
note 4
15
−
50
pF
CL
output load
capacitance
tOHD;DAT
output data hold
time
tPD
propagation delay CL = 15 pF
from positive edge
of XCLK output
CL = 15 pF
Control signal output timing RT port, related to LLC output
output load
capacitance
tOHD;DAT
output hold time
CL = 15 pF
4
−
−
ns
tPD
propagation delay CL = 15 pF
from positive edge
of LLC output
−
−
19
ns
15
−
50
pF
31
−
45
ns
35
−
65
%
ICLK output timing
Tcy
δ
tr
cycle time
duty factors for
tICLKH/tICLKL
rise time
0.6 to 2.6 V
−
−
5
ns
fall time
2.6 to 0.6 V
−
−
5
ns
ww
tf
output load
capacitance
w.
CL
yc
CL
2004 Jul 22
87
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SYMBOL
PARAMETER
SAA7118
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CL
output load
capacitance at all
outputs
tOHD;DAT
output data hold
time
CL = 15 pF
to(d)
output delay time
CL = 15 pF
−
50
pF
−
−
ns
−
−
19
ns
31
−
100
ns
15
co
4
ICLK input timing
Tcy
m
Data and control signal output timing I port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default)
cycle time
z.
Notes
1. ADC1 is not taken into account, since component video is always converted by ADC2, ADC3 and ADC4.
2. VDD(I2C) is the supply voltage of the I2C-bus. For VDD(I2C) = 3.3 V then VIL(SCL,SDA)(max) = 1 V; for VDD(I2C) = 5 V then
VIL(SCL,SDA)(max) = 1.5 V. For VDD(I2C) = 3.3 V then VIH(SCL,SDA)(min) = 2.3 V; for VDD(I2C) = 5 V then
VIH(SCL,SDA)(min) = 3.5 V.
3. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL = 50 pF.
-d
4. The effects of rise and fall times are included in the calculation of tOHD;DAT and tPD. Timings and levels refer to
drawings and conditions illustrated in Fig.46.
ww
w.
yc
5. The crystal oscillator drive level is typical 0.28 mW.
2004 Jul 22
88
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
Tcy
handbook, full pagewidth
t XCLKH
co
m
SAA7118
2.4 V
t SU;DAT
tf
t HD;DAT
data and
control inputs
(X port)
1.5 V
z.
clock input
XCLK
0.6 V
tr
2.0 V
-d
not valid
0.8 V
t SU;DAT
2.0 V
0.8 V
yc
input
XDQ
t HD;DAT
t o(d)
t OHD;DAT
w.
data and
control outputs
X port, I port
−2.4 V
−0.6 V
t X(I)CLKL
t X(I)CLKH
−2.6 V
ww
clock outputs
LLC, LLC2, XCLK, ICLK
and ICLK input
−1.5 V
−0.6 V
tf
tr
Fig.46 Data input/output timing diagram (X port, RT port and I port).
2004 Jul 22
89
MHB735
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
VDDD or VSSD
for crystal strapping
BF840
TDO
A5
FSW
CVBS1
AI12
CVBS2
AI13
S
AI14
AI1D
56 Ω
(3×)
AGND
18 Ω (4×)
AI21
VSB1
AI22
VSB2
AI23
G
AI24
YS
AI2D
56 Ω
(4×)
18 Ω (4×)
AI31
Y1
AI32
Y2
AI33
B
AI34
PB
AI3D
56 Ω
(4×)
AGNDA
AI41
C1
AI42
C2
AI43
R
AI44
PR
AI4D
56 Ω
(4×)
EXMCLR
AOUT
K1
K2
L3
K3
C2
G4
G3
H2
H1
E3
F2
F3
G1
F1
L2
ww
10
µF
DGND
2.2 µH
10
µF
AGND
SCL INT_A CE
N9
P9
N4
M10
N5
P4
B11
D8
C7
A6
B7
L12
K13
L14
K14
D2
N12
D1
L13
P3
M1
M3,
K4,
H4,
F4,
D4
VDDA0
to
VDDA4
L1,
J1,
G2,
E2
L5,
L9,
J11,
F11,
D10,
D7
VDDA1A
to
VDDA4A
VSSD2
VSSD4
VSSD6
VSSD8
VSSD10
VSSD12
M5,
M9,
J12,
F12,
C10,
C8
L4,
L8,
L11,
G11,
D11,
D9,
D5
VDDD2
VDDD4
VDDD6
VDDD8
VDDD10
VDDD12
DGND
RTS1
RTS0
LLC2
LLC
XTRI
XRV
XRH
XRDY
XDQ
M4,
M8,
M11,
H12,
D12,
C9,
C5
VSSD1
VSSD3
VSSD5
VSSD7
VSSD9
VSSD11
VSSD13
DGND
VDDD1
VDDD3
VDDD5
VDDD7
VDDD9
VDDD11
VDDD13
ITRI
IGP1
IGP0
IGPV
IGPH
ITRDY
IDQ
ICLK
M14
K11, J13, J14, H13, IPD[7:0]
H14, H11, G12, G14
E1
M2,
J4,
H3,
E4,
C1
RTCO
G13, F14, F13, E14, HPD[7:0]
E12, E13, E11, D14
K12
D3
4.7
kΩ
XCLK
A7
C11, A11, B10, A10, XPD[7:0]
B9, A9, B8, A8
CLKEXT
N6
P6, M6, L6, N7, P7, ADP[8:0]
L7, M7, P8, N8
A4
B3
A2 A3
B4
XTALO XTALI
24.576 MHz
(3rd harmonic)
XTOUT
DGND
10 µH
100
nF
100
nF 0 Ω
100
nF
100
nF
100
nF
100
nF
100
nF
100
nF
10
pF
DGND
AGND
(1) For board design without boundary scan implementation this pin should be connected to ground.
Fig.47 Application example with 24.576 MHz crystal (BGA156 package).
2004 Jul 22
RES
P5
B1
AGND
VDDD
P10
SAA7118E
VSSA0
to
VSSA4
VDDA
N11
L10
J2
J3
P12
N10
w.
AOUT
P11
M13
yc
18 Ω (4×)
ALRCLK ASCLK SDA
M12
VSS(xtal)
AI11
TMS
D6
VDD(xtal)
18 Ω (3×)
B6
z.
47 nF
C6
I2C-bus port
-d
DGND
TCK
TDI
B5
audio
clock
90
real-time
AMXCLK
expansion port
boundary scan(1)
TRST
75 Ω
4.7 kΩ
host port
∆t
680 Ω
FB
VDDD or VSSD
for I2C-bus
slave address
strapping
4.7 kΩ
AMCLK
scaled image port
BAT83
VDDD
10
pF
mhb736
1 nF
AD port
680 Ω
co
VDDD
150 pF
m
14 APPLICATION INFORMATION
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
m
SAA7118
VDDD or VSSD
for crystal strapping
VDDD
AMXCLK
TRST
BF840
TDO TDI
75 Ω
150
AI12
CVBS2
AI13
S
AI14
AI1D
56 Ω
(3×)
AGND
18 Ω (4×)
AI21
VSB1
AI22
VSB2
AI23
G
AI24
YS
AI2D
56 Ω
(4×)
18 Ω (4×)
AI31
Y1
AI32
Y2
AI33
B
AI34
PB
AI3D
56 Ω
(4×)
AGNDA
18 Ω (4×)
C1
AI42
C2
AI43
R
AI44
PR
AI4D
56 Ω
(4×)
EXMCLR
AOUT
31
34
30
3
19
21
23
26
13
15
18
14
35
ww
VDDD
10
µF
DGND
2.2 µH
10
µF
AGND
SCL INT_A CE
66
64
44
46
126
140
141
146
103, 105, 107, 109,
110, 111, 112, 113
86
89
87
90
2
91
5
77
10
43
36
38,
28,
20,
12,
4
37,
32,
24,
16,
8
51,
67,
96,
108,
133,
145
33,
25,
17,
9
VSSA0
VDDA0
VDDA1A
to
VSSA4
to
VDDA4
to
VDDA4A
VSSD2
VSSD4
VSSD6
VSSD8
VSSD10
VSSD12
50,
65,
95,
106,
132,
142
VDDD2
VDDD4
VDDD6
VDDD8
VDDD10
VDDD12
DGND
47,
63,
88,
104,
129,
137,
153
45,
59,
73,
101,
114,
136,
151
VSSD1
VSSD3
VSSD5
VSSD7
VSSD9
VSSD11
VSSD13
VDDD1
VDDD3
VDDD5
VDDD7
VDDD9
VDDD11
VDDD13
DGND
DGND
100
nF
100
nF
RTCO
RTS1
RTS0
LLC2
LLC
XTRI
XRV
XRH
XRDY
HPD[7:0]
ITRI
IGP1
IGP0
IGPV
IGPH
ITRDY
IDQ
85
ICLK
84
92, 93, 94, 97, IPD[7:0]
98, 99, 100, 102
7
6
4.7
kΩ
XDQ
144
XCLK
143
XPD[7:0]
127, 128, 130, 131,
134, 135, 138, 139
CLKEXT
52
53, 54, 55, 56, 57, ADP[8:0]
58, 60, 61, 62
154 157 158 156
155
XTALO XTALI
24.576 MHz
(3rd harmonic)
XTOUT
10 µH
100
nF
100
nF 0 Ω
100
nF
100
nF
100
nF
100
nF
10
pF
DGND
AGND
(1) For board design without boundary scan implementation this pin should be connected to ground.
Fig.48 Application example with 24.576 MHz crystal (QFP160 package).
2004 Jul 22
RES
49
48
SAA7118H
AGND
VDDA
68
69
29
11
74
70
27
22
75
71
w.
AOUT
72
83
yc
AI41
76
VSS(xtal)
CVBS1
ALRCLK ASCLK SDA
149
VDD(xtal)
AI11
148
z.
47 nF
TCK TMS
147
I2C-bus port
-d
FSW
DGND
18 Ω (3×)
152
audio
clock
91
real-time
AMCLK
boundary scan(1)
VDDD or VSSD
for I2C-bus
slave address
strapping
4.7 kΩ
expansion port
∆t
680 Ω
FB
co
4.7 kΩ
host port
BAT83
150 pF
10
pF
mhc565
1 nF
scaled image port
680 Ω
AD port
VDDD
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
SAA7118
XTALI
B4 (155)
XTALO
A3 (156)
XTALI
32.11 MHz
4.7 µH
SAA7118
SAA7118
A3 (156)
15
pF
XTALO
33
pF
33
pF
A3 (156)
XTALI
XTALO
24.576 MHz
4.7 µH
1 nF
SAA7118
B4 (155)
A3 (156)
XTALI
XTALO
39
pF
39
pF
A3 (156)
XTALI
XTALO
A3 (156)
XTALI
XTALO
24.576 MHz
15
pF
15
pF
(2c) With fundamental quartz.
Crystal load = 8 pF.
SAA7118
SAA7118
B4 (155)
B4 (155)
MHB784
(2b) With fundamental quartz.
Crystal load = 20 pF.
w.
(2a) With 3rd harmonic quartz.
Crystal load = 8 pF.
MHB781
SAA7118
24.576 MHz
18
pF
10
pF
(1c) With fundamental quartz.
Crystal load = 8 pF
yc
18
pF
10
pF
-d
B4 (155)
XTALO
(1b) With fundamental quartz.
Crystal load = 20 pF.
handbook, full pagewidth
SAA7118
XTALI
z.
1 nF
(1a) With 3rd harmonic quartz.
Crystal load = 8 pF.
A3 (156)
32.11 MHz
32.11 MHz
15
pF
B4 (155)
co
B4 (155)
m
handbook, full pagewidth
B4 (155)
A3 (156)
XTALI
XTALO
32.11 MHz or
24.576 MHz
Rs
ww
n.c.
clock
(3a) With direct clock.
Pin numbers for QFP160 in parenthesis.
MHB786
(3b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator
is too high a resistance Rs can be placed in series with the output of the oscillator XTALO.
Note: The decreased crystal amplitude results in a lower drive level but on the other hand
the jitter performance will decrease.
Fig.49 Oscillator application.
2004 Jul 22
92
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15 I2C-BUS DESCRIPTION
I2C-bus format
S
SLAVE ADDRESS W
ACK-s
co
15.1
m
The SAA7118 supports the ‘fast mode’ I2C-bus specification extension (data rate up to 400 kbit/s).
ACK-s
SUBADDRESS
DATA
data transferred
(n bytes + acknowledge)
z.
a. Write procedure.
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
Sr
SLAVE ADDRESS R
ACK-s
DATA
ACK-m
P
MHB339
P
MHB340
-d
data transferred
(n bytes + acknowledge)
ACK-s
b. Read procedure (combined).
yc
Fig.50 I2C-bus format.
Table 36 Description of I2C-bus format
CODE
S
START condition
Sr
repeated START condition
‘0100 0010’ (42H, default) or ‘0100 0000’ (40H; note 1)
w.
SLAVE ADDRESS W
DESCRIPTION
SLAVE ADDRESS R
‘0100 0011’ (43H, default) or ‘0100 0001’ (41H; note 1)
ACK-s
acknowledge generated by the slave
ACK-m
acknowledge generated by the master
subaddress byte; see Tables 37 and 38
DATA
data byte; see Table 38; if more than one byte DATA is transmitted the subaddress pointer is
automatically incremented
ww
SUBADDRESS
P
STOP condition
X
read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver);
X = 1, order to read (the circuit is slave transmitter)
Note
1. If pin RTCO strapped to supply voltage via a 3.3 kΩ resistor.
2004 Jul 22
93
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 37 Subaddress description and access
DESCRIPTION
00H
chip version
F0H to FFH
reserved
ACCESS (READ/WRITE)
read only
m
SUBADDRESS
−
01H to 05H
front-end part
06H to 19H
decoder part
1AH to 1DH
reserved
1EH and 1FH
video decoder status bytes
co
Video decoder: 01H to 1FH
read and write
read and write
−
Component processing and interrupt masking: 20H to 2FH
read only
−
reserved
23H to 25H
analog input control
26H to 28H
reserved
29H to 2CH
component control
read and write
2DH to 2FH
interrupt mask
read and write
-d
Audio clock generation: 30H to 3FH
z.
20H to 22H
30H to 3AH
audio clock generator
3BH to 3FH
reserved
read and write
−
read and write
−
40H to 5EH
VBI data slicer
5FH
reserved
−
yc
General purpose VBI data slicer: 40H to 7FH
read only
60H to 62H
63H to 7FH
VBI data slicer status
reserved
read and write
−
X port, I port and the scaler: 80H to EFH
90H to BFH
read and write
task A definition
read and write
task B definition
read and write
ww
C0H to EFH
task independent global settings
w.
80H to 8FH
2004 Jul 22
94
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SUB
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
00
ID7
ID6
ID5
ID4
−
−
−
−
Chip version: register 00H
Chip version (read only)
Video decoder: registers 01H to 1FH
FRONT-END PART: REGISTERS 01H TO 05H
Increment delay
01
Analog input control 1
02
Analog input control 2
03
Analog input control 3
04
Analog input control 4
05
DECODER PART: REGISTERS 06H TO 1FH
.y
(1)
WPOFF
GUDL1
GUDL0
IDEL3
IDEL2
IDEL1
IDEL0
FUSE1
FUSE0
MODE5
MODE4
MODE3
MODE2
MODE1
MODE0
(1)
HLNRS
VBSL
CPOFF
HOLDG
GAFIX
GAI28
GAI18
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
95
c-
Horizontal sync start
06
HSB7
HSB6
HSB5
Horizontal sync stop
07
HSS7
HSS6
HSS5
Sync control
08
AUFD
FSEL
FOET
Luminance control
09
BYPS
YCOMB
LDEL
Luminance brightness control
0A
DBRI7
DBRI6
DBRI5
Luminance contrast control
0B
DCON7
DCON6
DCON5
Chrominance saturation control
0C
DSAT7
DSAT6
DSAT5
Chrominance hue control
0D
HUEC7
HUEC6
HUEC5
Chrominance control 1
0E
CDTO
CSTD2
Chrominance gain control
0F
ACGC
Chrominance control 2
10
OFFU1
Mode/delay control
11
RT signal control
dz
HSB4
HSB3
HSB2
HSB1
HSB0
HSS4
HSS3
HSS2
HSS1
HSS0
HTC1
HTC0
HPLL
VNOI1
VNOI0
LUBW
LUFI3
LUFI2
LUFI1
LUFI0
DBRI4
DBRI3
DBRI2
DBRI1
DBRI0
DCON4
DCON3
DCON2
DCON1
DCON0
.c
DSAT2
HUEC2
DSAT1
CSTD1
CSTD0
DCVF
FCTC
CGAIN6
CGAIN5
CGAIN4
CGAIN3
OFFU0
OFFV1
OFFV0
CHBW
COLO
RTP1
HDEL1
HDEL0
RTP0
YDEL2
12
RTSE13
RTSE12
RTSE11
RTSE10
RTSE03
RTSE02
RT/X port output control
13
RTCE
XRHS
XRVS1
XRVS0
HLSEL
OFTS2
Analog/ADC/compatibility
control
14
CM99
UPTCV
AOSL1
AOSL0
XTOUTE
AUTO1
VGATE start, FID change
15
VSTA7
VSTA6
VSTA5
VSTA4
VSTA3
VGATE stop
16
VSTO7
VSTO6
VSTO5
VSTO4
VSTO3
DSAT0
om
HUEC1
HUEC0
AUTO0
CCOMB
CGAIN2
CGAIN1
CGAIN0
LCBW2
LCBW1
LCBW0
YDEL1
YDEL0
RTSE01
RTSE00
OFTS1
OFTS0
APCK1
APCK0
VSTA2
VSTA1
VSTA0
VSTO2
VSTO1
VSTO0
Product specification
DSAT3
HUEC3
SAA7118
DSAT4
HUEC4
Philips Semiconductors
ww
w
REGISTER FUNCTION
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
Table 38 I2C-bus receiver/transmitter overview
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D6
D5
D4
D3
D2
D1
D0
Miscellaneous, VGATE
configuration and MSBs
17
LLCE
LLC2E
LATY2
LATY1
LATY0
VGPS
VSTO8
VSTA8
Raw data gain control
18
RAWG7
RAWG6
RAWG5
RAWG4
RAWG3
RAWG2
RAWG1
RAWG0
Raw data offset control
19
RAWO7
RAWO6
RAWO5
RAWO4
RAWO3
RAWO2
RAWO1
RAWO0
1A to 1D
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Status byte 1 video decoder
(read only)
1E
−
HLCK
SLTCA
GLIMT
GLIMB
WIPA
DCSTD1
DCSTD0
Status byte 2 video decoder
(read only)
1F
INTL
HLVLN
FIDT
−
TYPE3
COLSTR
COPRO
RDCAP
(1)
(1)
(1)
(1)
(1)
REFA
(1)
EXMCE
GAI48
GAI38
GAI34
GAI33
GAI32
GAI31
GAI30
GAI44
GAI43
GAI42
GAI41
GAI40
(1)
(1)
(1)
(1)
(1)
FSWDL0
CMFI
CPDL2
CPDL1
CPDL0
ww
w
Reserved
.y
c-
Component processing and interrupt masking part: registers 20H to 2FH
Reserved
20 to 22
Analog input control 5
23
Analog input control 6
24
Analog input control 7
25
(1)
(1)
(1)
96
AOSL2
ADPE
EXCLK
GAI37
GAI36
GAI35
GAI47
GAI46
GAI45
26 to 28
(1)
(1)
(1)
Component delay
29
FSWE
FSWI
FSWDL1
Component brightness control
2A
CBRI7
CBRI6
CBRI5
Component contrast control
2B
CCON7
CCON6
CCON5
Component saturation control
2C
CSAT7
CSAT6
CSAT5
(1)
(1)
Reserved
Interrupt mask 1
2D
(1)
Interrupt mask 2
2E
(1)
MHLCK
(1)
Interrupt mask 3
2F
MINTL
MHLVLN
MFIDT
dz
CBRI3
CBRI2
CBRI1
CBRI0
CCON3
CCON2
CCON1
CCON0
CSAT4
CSAT3
CSAT2
CSAT1
CSAT0
(1)
MERROF
MVPSV
MPPV
MCCV
(1)
(1)
(1)
(1)
MTYPE3
MCOLSTR
MCOPRO
MRDCAP
ACPF1
ACPF0
Audio clock generator part: registers 30H to 3FH
Audio master clock cycles per
field
.c
CBRI4
CCON4
om
Philips Semiconductors
D7
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
SUB
ADDR.
(HEX)
REGISTER FUNCTION
MDCSTD1 MDCSTD0
ACPF6
ACPF5
ACPF4
ACPF3
ACPF2
31
ACPF15
ACPF14
ACPF13
ACPF12
ACPF11
ACPF10
ACPF9
ACPF8
(1)
(1)
(1)
(1)
(1)
ACPF17
ACPF16
(1)
(1)
ACNI1
ACNI0
32
(1)
Reserved
33
(1)
(1)
(1)
(1)
(1)
(1)
Audio master clock nominal
increment
34
ACNI7
ACNI6
ACNI5
ACNI4
ACNI3
ACNI2
35
ACNI15
ACNI14
ACNI13
ACNI12
ACNI11
ACNI10
ACNI9
ACNI8
36
(1)
(1)
ACNI21
ACNI20
ACNI19
ACNI18
ACNI17
ACNI16
Product specification
ACPF7
SAA7118
30
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D6
D5
D4
D3
D2
D1
D0
37
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Clock ratio AMXCLK to ASCLK
38
(1)
(1)
SDIV5
SDIV4
SDIV3
SDIV2
SDIV1
SDIV0
Clock ratio ASCLK to ALRCLK
39
(1)
(1)
LRDIV5
LRDIV4
LRDIV3
LRDIV2
LRDIV1
LRDIV0
Audio clock generator basic
setup
3A
(1)
(1)
(1)
(1)
APLL
AMVR
LRPH
SCPH
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
ww
w
Reserved
.y
3B to 3F
General purpose VBI data slicer part: registers 40H to 7FH
Slicer control 1
40
(1)
HAM_N
FCE
HUNT_N
(1)
(1)
(1)
(1)
97
c-
LCR2 to LCR24 (n = 2 to 24)
41 to 57
LCRn_7
LCRn_6
LCRn_5
LCRn_4
LCRn_3
LCRn_2
LCRn_1
LCRn_0
Programmable framing code
58
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Horizontal offset for slicer
59
HOFF6
HOFF5
HOFF4
HOFF3
HOFF2
HOFF1
HOFF0
Vertical offset for slicer
5A
VOFF7
VOFF6
VOFF5
Field offset and MSBs for
horizontal and vertical offset
5B
FOFF
RECODE
(1)
Reserved (for testing)
5C
(1)
(1)
(1)
Header and data identification
(DID) code control
5D
FVREF
(1)
DID5
Sliced data identification (SDID)
code
5E
(1)
(1)
SDID5
Reserved
5F
(1)
(1)
(1)
Slicer status byte 0 (read only)
60
−
FC8V
FC7V
Slicer status byte 1 (read only)
61
−
−
F21_N
LN8
Slicer status byte 2 (read only)
62
LN3
LN2
LN1
LN0
63 to 7F
(1)
(1)
(1)
(1)
Reserved
HOFF7
dz
VOFF4
VOFF3
VOFF2
VOFF1
VOFF0
VOFF8
(1)
HOFF10
HOFF9
HOFF8
(1)
(1)
(1)
(1)
(1)
DID4
DID3
DID2
DID1
DID0
SDID4
SDID3
SDID2
SDID1
SDID0
(1)
(1)
(1)
(1)
(1)
PPV
CCV
LN7
LN6
DT3
DT2
(1)
(1)
VPSV
X port, I port and the scaler part: registers 80H to EFH
.c
Reserved
X port I/O enable and output
clock phase control
80
(1)
SMOD
TEB
TEA
ICKS3
ICKS2
81 and
82
(1)
(1)
(1)
(1)
(1)
(1)
83
(1)
(1)
XPCK1
XPCK0
(1)
XRQT
DT1
DT0
(1)
(1)
ICKS1
ICKS0
(1)
(1)
XPE1
XPE0
SAA7118
Global control 1
om
−
LN4
Product specification
TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH
−
LN5
Philips Semiconductors
D7
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
SUB
ADDR.
(HEX)
REGISTER FUNCTION
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D6
D5
D4
D3
D2
D1
D0
I port signal definitions
84
IDG01
IDG00
IDG11
IDG10
IDV1
IDV0
IDH1
IDH0
I port signal polarities
85
ISWP1
ISWP0
ILLV
IG0P
IG1P
IRVP
IRHP
IDQP
I port FIFO flag control and
arbitration
86
VITX1
VITX0
IDG02
IDG12
FFL1
FFL0
FEL1
FEL0
I port I/O enable, output clock
and gated clock phase control
87
Power save/ADC port control
88
ww
w
Reserved
Status information scaler part
.y
IPCK3
IPCK2
IPCK1
IPCK0
(1)
(1)
IPE1
IPE0
DOSL1
DOSL0
SWRST
DPROG
SLM3
(1)
SLM1
SLM0
89 to 8E
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
8F
XTRI
FFOV
PRDON
ERROF
FIDSCI
FIDSCO
TASK A DEFINITION: REGISTERS 90H TO BFH
Basic settings and acquisition window definition
98
c-
ITRI
FFIL
dz
CONLH
OFIDC
FSKP2
FSKP1
FSKP0
RPTSK
STRC1
STRC0
91
CONLV
HLDFV
SCSRC1
SCSRC0
SCRQE
FSC2
FSC1
FSC0
X port input reference signal
definition
92
XFDV
XFDH
XDV1
XDV0
XCODE
XDH
XDQ
XCKS
I port output formats and
configuration
93
ICODE
I8_16
FYSK
FOI1
FOI0
FSI2
FSI0
Horizontal input window start
94
XO7
XO6
XO5
XO4
XO3
XO2
XO1
XO0
95
(1)
(1)
(1)
XO11
XO10
XO9
XO8
96
XS7
XS6
XS5
XS1
XS0
97
(1)
(1)
(1)
XS9
XS8
98
YO7
YO6
YO1
YO0
99
(1)
(1)
YO9
YO8
9A
YS7
.c
FSI1
YS1
YS0
YS9
YS8
XD1
XD0
XD9
XD8
YD1
YD0
YD9
YD8
Horizontal input window length
Vertical input window start
Vertical input window length
Horizontal output window length
Vertical output window length
(1)
XS4
XS3
XS2
(1)
XS11
XS10
YO5
YO4
YO3
YO2
(1)
(1)
YO11
YO10
YS6
YS5
YS4
YS3
YS2
9B
(1)
(1)
(1)
(1)
YS11
YS10
9C
XD7
XD6
XD5
XD4
XD3
XD2
9D
(1)
(1)
(1)
(1)
XD11
XD10
9E
YD7
YD6
YD5
YD4
YD3
YD2
9F
(1)
(1)
(1)
(1)
YD11
YD10
om
Product specification
90
X port formats and configuration
SAA7118
Task handling control
Philips Semiconductors
D7
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
SUB
ADDR.
(HEX)
REGISTER FUNCTION
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D6
D5
D4
D3
D2
D1
D0
A0
(1)
(1)
XPSC5
XPSC4
XPSC3
XPSC2
XPSC1
XPSC0
Accumulation length
A1
(1)
(1)
XACL5
XACL4
XACL3
XACL2
XACL1
XACL0
Prescaler DC gain and FIR
prefilter control
A2
PFUV1
PFUV0
PFY1
PFY0
XC2_1
XDCG2
XDCG1
XDCG0
Reserved
A3
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XSCY7
XSCY6
XSCY5
XSCY4
XSCY3
XSCY2
XSCY1
XSCY0
(1)
(1)
XSCY12
XSCY11
XSCY10
XSCY9
XSCY8
XPHY4
XPHY3
XPHY2
XPHY1
XPHY0
ww
w
FIR filtering and prescaling
Horizontal prescaling
Luminance brightness control
A4
Luminance contrast control
A5
Chrominance saturation control
A6
Reserved
A7
Horizontal phase scaling
.y
99
c-
Horizontal luminance scaling
increment
A8
A9
(1)
Horizontal luminance phase
offset
AA
XPHY7
XPHY6
XPHY5
Reserved
AB
(1)
(1)
(1)
Horizontal chrominance scaling
increment
AC
XSCC7
XSCC6
XSCC5
(1)
(1)
dz
(1)
.c
(1)
(1)
(1)
(1)
XSCC4
XSCC3
XSCC2
XSCC1
XSCC0
XSCC12
XSCC11
XSCC10
XSCC9
XSCC8
XPHC4
XPHC3
XPHC2
XPHC1
XPHC0
(1)
(1)
AE
XPHC7
XPHC6
XPHC5
Reserved
AF
(1)
(1)
(1)
(1)
Vertical luminance scaling
increment
B0
YSCY7
YSCY6
YSCY5
YSCY4
YSCY3
YSCY2
B1
YSCY15
YSCY14
YSCY13
YSCY12
YSCY11
YSCY10
Vertical chrominance scaling
increment
B2
YSCC7
YSCC6
YSCC5
YSCC4
YSCC3
YSCC2
YSCC1
YSCC0
B3
YSCC15
YSCC14
YSCC13
YSCC12
YSCC11
YSCC10
YSCC9
YSCC8
Vertical scaling mode control
B4
(1)
(1)
(1)
YMIR
(1)
(1)
(1)
YMODE
B5 to B7
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
B8
YPC07
YPC06
YPC05
YPC04
YPC03
YPC02
YPC01
YPC00
Vertical scaling
Reserved
Vertical chrominance phase
offset ‘00’
om
(1)
(1)
YSCY1
YSCY0
YSCY9
YSCY8
Product specification
Horizontal chrominance phase
offset
SAA7118
AD
(1)
Philips Semiconductors
D7
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
SUB
ADDR.
(HEX)
REGISTER FUNCTION
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D6
D5
D4
D3
D2
D1
D0
Vertical chrominance phase
offset ‘01’
B9
YPC17
YPC16
YPC15
YPC14
YPC13
YPC12
YPC11
YPC10
Vertical chrominance phase
offset ‘10’
BA
YPC27
YPC26
YPC25
YPC24
YPC23
YPC22
YPC21
YPC20
Vertical chrominance phase
offset ‘11’
BB
Vertical luminance phase
offset ‘00’
BC
Vertical luminance phase
offset ‘01’
BD
Vertical luminance phase
offset ‘10’
BE
Vertical luminance phase
offset ‘11’
BF
ww
w
.y
100
YPC37
YPC36
YPC35
YPC34
YPC33
YPC32
YPC31
YPC30
YPY07
YPY06
YPY05
YPY04
YPY03
YPY02
YPY01
YPY00
YPY17
YPY16
YPY15
YPY13
YPY12
YPY11
YPY10
YPY27
YPY26
YPY25
YPY24
YPY23
YPY22
YPY21
YPY20
YPY37
c-
YPY14
YPY36
YPY35
YPY34
YPY33
YPY32
YPY31
YPY30
FSKP1
FSKP0
RPTSK
.c
STRC1
STRC0
TASK B DEFINITION REGISTERS C0H TO EFH
Basic settings and acquisition window definition
dz
Task handling control
C0
CONLH
OFIDC
FSKP2
X port formats and configuration
C1
CONLV
HLDFV
SCSRC1
SCSRC0
SCRQE
FSC2
FSC1
FSC0
XDV0
XCODE
XDH
XDQ
XCKS
FOI1
FOI0
FSI2
FSI1
FSI0
XO4
XO3
XO2
XO11
XO10
XFDV
XFDH
XDV1
C3
ICODE
I8_16
FYSK
Horizontal input window start
C4
XO7
XO6
XO5
C5
(1)
(1)
(1)
(1)
C6
XS7
XS6
XS5
XS4
XS3
XS2
C7
(1)
(1)
(1)
(1)
XS11
XS10
C8
YO7
YO6
YO5
YO4
YO3
YO2
C9
(1)
(1)
(1)
(1)
YO11
YO10
CA
YS7
YS6
YS5
YS4
YS3
YS2
CB
(1)
(1)
(1)
(1)
YS11
YS10
CC
XD7
XD6
XD5
XD4
XD3
XD2
CD
(1)
(1)
(1)
(1)
XD11
XD10
Horizontal input window length
Vertical input window start
Vertical input window length
Horizontal output window length
om
XO1
XO0
XO9
XO8
XS1
XS0
XS9
XS8
YO1
YO0
YO9
YO8
YS1
YS0
YS9
YS8
XD1
XD0
XD9
XD8
Product specification
C2
I port formats and configuration
SAA7118
Input reference signal definition
Philips Semiconductors
D7
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
SUB
ADDR.
(HEX)
REGISTER FUNCTION
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D6
D5
D4
D3
D2
D1
D0
CE
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
CF
(1)
(1)
(1)
(1)
YD11
YD10
YD9
YD8
Horizontal prescaling
D0
(1)
(1)
XPSC5
XPSC4
XPSC3
XPSC2
XPSC1
XPSC0
Accumulation length
D1
(1)
(1)
XACL5
XACL4
XACL3
XACL2
XACL1
XACL0
Prescaler DC gain and FIR
prefilter control
D2
PFUV1
PFUV0
PFY1
PFY0
XC2_1
XDCG2
XDCG1
XDCG0
Reserved
D3
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
ww
w
Vertical output window length
FIR filtering and prescaling
Luminance brightness control
D4
Luminance contrast control
D5
Chrominance saturation control
D6
Reserved
D7
.y
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Horizontal phase scaling
101
c-
BRIG7
CONT7
Horizontal luminance scaling
increment
D8
XSCY7
XSCY6
XSCY5
D9
(1)
(1)
(1)
Horizontal luminance phase
offset
DA
XPHY7
XPHY6
XPHY5
Reserved
DB
(1)
(1)
(1)
Horizontal chrominance scaling
increment
DC
XSCC7
XSCC6
XSCC5
DD
(1)
(1)
(1)
Horizontal chrominance phase
offset
DE
XPHC7
XPHC6
Reserved
DF
(1)
(1)
dz
XSCY4
XSCY3
XSCY2
XSCY1
XSCY0
XSCY12
XSCY11
XSCY10
XSCY9
XSCY8
XPHY4
XPHY3
XPHY2
XPHY1
XPHY0
(1)
(1)
(1)
(1)
(1)
XSCC4
XSCC3
XSCC2
XSCC1
XSCC0
XSCC12
XSCC11
XSCC10
XSCC9
XSCC8
XPHC5
XPHC4
XPHC3
XPHC2
XPHC1
XPHC0
(1)
(1)
(1)
(1)
(1)
(1)
Vertical scaling
.c
YSCY7
YSCY6
YSCY5
YSCY4
YSCY3
YSCY2
YSCY1
YSCY0
E1
YSCY15
YSCY14
YSCY13
YSCY12
YSCY11
YSCY10
YSCY9
YSCY8
Vertical chrominance scaling
increment
E2
YSCC7
YSCC6
YSCC5
YSCC4
YSCC3
YSCC2
YSCC1
YSCC0
E3
YSCC15
YSCC14
YSCC13
YSCC12
YSCC11
YSCC10
YSCC9
YSCC8
Vertical scaling mode control
E4
(1)
(1)
(1)
YMIR
(1)
(1)
(1)
YMODE
E5 to E7
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
Product specification
E0
SAA7118
om
Vertical luminance scaling
increment
Philips Semiconductors
D7
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
SUB
ADDR.
(HEX)
REGISTER FUNCTION
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D6
D5
D4
D3
D2
D1
D0
Vertical chrominance phase
offset ‘00’
E8
YPC07
YPC06
YPC05
YPC04
YPC03
YPC02
YPC01
YPC00
Vertical chrominance phase
offset ‘01’
E9
YPC17
YPC16
YPC15
YPC14
YPC13
YPC12
YPC11
YPC10
Vertical chrominance phase
offset ‘10’
EA
Vertical chrominance phase
offset ‘11’
EB
Vertical luminance phase
offset ‘00’
EC
Vertical luminance phase
offset ‘01’
ED
Vertical luminance phase
offset ‘10’
EE
Vertical luminance phase
offset ‘11’
EF
ww
w
Note
.y
YPC27
YPC26
YPC25
YPC24
YPC23
YPC22
YPC21
YPC20
YPC37
YPC36
YPC35
YPC34
YPC33
YPC32
YPC31
YPC30
YPY07
YPY06
YPY05
YPY03
YPY02
YPY01
YPY00
YPY17
YPY16
YPY15
YPY14
YPY13
YPY12
YPY11
YPY10
YPY27
YPY26
YPY25
YPY24
YPY23
YPY22
YPY21
YPY20
YPY37
c-
YPY04
YPY36
YPY35
YPY34
YPY33
YPY32
YPY31
YPY30
dz
.c
Philips Semiconductors
102
D7
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
SUB
ADDR.
(HEX)
REGISTER FUNCTION
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
Product specification
SAA7118
om
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.2
15.2.1
SAA7118
I2C-bus details
SUBADDRESS 00H
m
Table 39 Chip Version (CV) identification; 00H[7:4]; read only register
LOGIC LEVELS
FUNCTION
15.2.2
ID6
CV3
CV2
ID5
ID4
CV1
CV0
co
Chip Version (CV)
ID7
SUBADDRESS 01H
Table 40 Horizontal increment delay; 01H[6:0]
D6
DESCRIPTION
white peak control off
D[5:4] update hysteresis for 9-bit
gain; see Fig.9
Note
WPOFF(1)
GUDL[1:0]
IDEL[3:0]
yc
D[3:0] increment delay
SYMBOL
VALUE
FUNCTION
0
white peak control active (AD signal is
attenuated, if nominal luminance
output white level is exceeded)
1
white peak control disabled
00
off
-d
BIT
z.
The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC.
Use recommended position only.
01
±1 LSB
10
±2 LSB
11
±3 LSB
1111
no update
1110
minimum delay
0111
recommended position
0000
maximum delay
ww
w.
1. HLNRS = 1 should not be used in combination with WPOFF = 0.
2004 Jul 22
103
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.2.3
SAA7118
SUBADDRESS 02H
Table 41 Analog input control 1 (AICO1); 02H[7:0]; note 1
SYMBOL
D[7:6] analog function
select; see
Figs 4 and 8
FUSE[1:0]
VALUE
00
FUNCTION
m
DESCRIPTION
amplifier plus anti-alias filter bypassed
01
co
BIT
10
amplifier active
11
amplifier plus anti-alias filter active
CVBS modes 1
000000
Mode 00: CVBS (automatic gain) from AI11; see Fig.51
000001
Mode 01: CVBS (automatic gain) from AI12; see Fig.52
000010
Mode 02: CVBS (automatic gain) from AI21; see Fig.53
000011
000100
000101
Y + C modes 1
Mode 04: CVBS (automatic gain) from AI23; see Fig.55
Mode 05: CVBS (automatic gain) from AI24; see Fig.56
Mode 06: Y (automatic gain) from AI11 + C (gain
adjustable via GAI28 to GAI20) from AI21; note 2;
see Fig.57
-d
000110
Mode 03: CVBS (automatic gain) from AI22; see Fig.54
000111
Mode 07: Y (automatic gain) from AI12 + C (gain
adjustable via GAI28 to GAI20) from AI22; note 2;
see Fig.58
001000
Mode 08: Y (automatic gain) from AI11 + C (gain adapted
to Y gain) from AI21; note 2; see Fig.59
yc
D[5:0] mode selection MODE[5:0]
z.
D[5:0] mode selection MODE[5:0]
Mode 09: Y (automatic gain) from AI12 + C (gain adapted
to Y gain) from AI22; note 2; see Fig.60
001010
Mode 0A: Y (automatic gain) from AI13 + C (gain
adjustable via GAI28 to GAI20) from AI23; note 2;
see Fig.61
001011
Mode 0B: Y (automatic gain) from AI14 + C (gain
adjustable via GAI28 to GAI20) from AI24; note 2;
see Fig.62
001100
Mode 0C: Y (automatic gain) from AI13 + C (gain adapted
to Y gain) from AI23; note 2; see Fig.63
001101
Mode 0D: Y (automatic gain) from AI14 + C (gain adapted
to Y gain) from AI24; note 2; see Fig.64
ww
w.
001001
2004 Jul 22
104
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
BIT
DESCRIPTION
SYMBOL
SAA7118
VALUE
FUNCTION
Mode 0E: CVBS (automatic gain) from AI13; see Fig.65
001111
Mode 0F: CVBS (automatic gain) from AI14; see Fig.66
010000
Mode 10: CVBS (automatic gain) from AI31; see Fig.67
010001
Mode 11: CVBS (automatic gain) from AI32; see Fig.68
010010
Mode 12: CVBS (automatic gain) from AI41; see Fig.69
010011
Mode 13: CVBS (automatic gain) from AI42; see Fig.70
010100
Mode 14: CVBS (automatic gain) from AI43; see Fig.71
010101
Mode 15: CVBS (automatic gain) from AI44; see Fig.72
Y + C modes 2
D[5:0] mode selection MODE[5:0]
010110
Mode 16: Y (automatic gain) from AI31 + C (gain
adjustable via GAI28 to GAI20) from AI41; note 2;
see Fig.73
Mode 17: Y (automatic gain) from AI32 + C (gain
adjustable via GAI28 to GAI20) from AI42; note 2;
see Fig.74
-d
010111
co
001110
z.
D[5:0] mode selection MODE[5:0]
m
CVBS modes 2
Mode 18: Y (automatic gain) from AI31 + C (gain adapted
to Y gain) from AI41; note 2; see Fig.75
011001
Mode 19: Y (automatic gain) from AI32 + C (gain adapted
to Y gain) from AI42; note 2; see Fig.76
011010
Mode 1A: Y (automatic gain) from AI33 + C (gain
adjustable via GAI28 to GAI20) from AI43; note 2;
see Fig.77
yc
011000
Mode 1B: Y (automatic gain) from AI34 + C (gain
adjustable via GAI28 to GAI20) from AI44; note 2;
see Fig.78
011100
Mode 1C: Y (automatic gain) from AI33 + C (gain adapted
to Y gain) from AI43; note 2; see Fig.79
w.
011011
011101
Mode 1D: Y (automatic gain) from AI34 + C (gain adapted
to Y gain) from AI44; note 2; see Fig.80
011110
Mode 1E: CVBS (automatic gain) from AI33; see Fig.81
011111
Mode 1F: CVBS (automatic gain) from AI34; see Fig.82
100000
Mode 20: SY-PB-PR (automatic gain for sync channel only)
from AI11, AI21, AI31, AI41; see Fig.83
100001
Mode 21: SY-PB-PR (automatic gain for sync channel only)
from AI12, AI22, AI32, AI42; see Fig.84
CVBS modes 3
D[5:0] mode selection MODE[5:0]
ww
Y-PB-PR modes
D[5:0] mode selection MODE[5:0]
2004 Jul 22
100010 to 101101 reserved
101110
Mode 2E: SY-PB-PR (automatic gain for sync channel only)
from AI13, AI23, AI33, AI43; see Fig.85
101110
Mode 2F: SY-PB-PR (automatic gain for sync channel only)
from AI14, AI24, AI34, AI44; see Fig.86
105
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
BIT
DESCRIPTION
SYMBOL
SAA7118
VALUE
FUNCTION
110000
Mode 30: SRGB (automatic gain for sync channel only)
from AI11, AI21, AI31, AI41; see Fig.87
110001
Mode 31: SRGB (automatic gain for sync channel only)
from AI12, AI22, AI32, AI42; see Fig.88
110010 to 111101 reserved
Mode 3E: SRGB (automatic gain for sync channel only)
from AI13, AI23, AI33, AI43; see Fig.89
111111
Mode 3F: SRGB (automatic gain for sync channel only)
from AI14, AI24, AI34, AI44; see Fig.90
000000
000001
001110
001111
Mode 00: input AI11; REFA = 1, DOSL = 0, GAFIX = 1
Mode 01: input AI12; REFA = 1, DOSL = 0, GAFIX = 1
Mode 0E: input AI13; REFA = 1, DOSL = 0, GAFIX = 1
Mode 0F: input AI14; REFA = 1, DOSL = 0, GAFIX = 1
Mode 02: input AI21; REFA = 1, DOSL = 1, GAFIX = 1
-d
000010
z.
111110
VSB modes; see Fig.91
D[5:0] mode selection MODE[5:0]
co
D[5:0] mode selection MODE[5:0]
m
RGB modes
Mode 03: input AI22; REFA = 1, DOSL = 1, GAFIX = 1
000100
Mode 04: input AI23; REFA = 1, DOSL = 1, GAFIX = 1
000101
Mode 05: input AI24; REFA = 1, DOSL = 1, GAFIX = 1
010000
Mode 10: input AI31; REFA = 1, DOSL = 2, GAFIX = 1
010001
Mode 11: input AI32; REFA = 1, DOSL = 2, GAFIX = 1
yc
000011
Mode 1E: input AI33; REFA = 1, DOSL = 2, GAFIX = 1
011111
Mode 1F: input AI34; REFA = 1, DOSL = 2, GAFIX = 1
010010
Mode 12: input AI41; REFA = 1, DOSL = 3, GAFIX = 1
010011
Mode 13: input AI42; REFA = 1, DOSL = 3, GAFIX = 1
010100
Mode 14: input AI43; REFA = 1, DOSL = 3, GAFIX = 1
010101
Mode 15: input AI44; REFA = 1, DOSL = 3, GAFIX = 1
w.
Notes
011110
1. Always refer to Table 71, usage of bits FSWE and FSWI.
ww
2. To take full advantage of the Y/C modes 06 to 0D and 16 to 1D the I2C-bus bit BYPS (subaddress 09H, bit D7)
should be set to logic 1 (full luminance bandwidth).
2004 Jul 22
106
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
handbook, halfpage
AI11
LUMA
w.
AD1
yc
Fig.51 MODE00 CVBS1.
AI21
AI22
AI23
AI24
CHROMA
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
CHROMA
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB739
Fig.52 MODE01 CVBS2.
handbook, halfpage
AI11
AI12
AI13
AI14
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB740
MHB741
Fig.53 MODE02 CVBS3.
2004 Jul 22
LUMA
AD2
AD3
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
AD1
AI31
AI32
AI33
AI34
-d
MHB738
AI12
AI13
AI14
AI12
AI13
AI14
LUMA
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
Fig.54 MODE03 CVBS4.
107
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
handbook, halfpage
AI11
LUMA
w.
AD1
yc
Fig.55 MODE04 CVBS5.
AI21
AI22
AI23
AI24
CHROMA
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
MHB744
CHROMA
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB743
Fig.56 MODE05 CVBS6.
handbook, halfpage
AI11
AI12
AI13
AI14
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB745
Fig.57 MODE06 YC1 (gain -> GAI2 level).
2004 Jul 22
LUMA
AD2
AD3
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
AD1
AI31
AI32
AI33
AI34
-d
MHB742
AI12
AI13
AI14
AI12
AI13
AI14
LUMA
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
Fig.58 MODE07 YC2 (gain -> GAI2 level).
108
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
AI12
AI13
AI14
LUMA
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
LUMA
CHROMA
AD2
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB747
-d
MHB746
AD1
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
handbook, halfpage
AI11
AD1
LUMA
w.
AI12
AI13
AI14
Fig.60 MODE09 YC2 (gain adapted to Y gain).
yc
Fig.59 MODE08 YC1 (gain adapted to Y gain).
AI21
AI22
AI23
AI24
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
MHB748
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB749
Fig.61 MODE0A YC3 (gain -> GAI2 level).
2004 Jul 22
AI12
AI13
AI14
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
CHROMA
handbook, halfpage
AI11
Fig.62 MODE0B YC4 (gain -> GAI2 level).
109
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
AI12
AI13
AI14
LUMA
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
LUMA
CHROMA
AD2
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB751
-d
MHB750
AD1
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
handbook, halfpage
AI11
AD1
LUMA
w.
AI12
AI13
AI14
Fig.64 MODE0D YC4 (gain adapted to Y gain).
yc
Fig.63 MODE0C YC3 (gain adapted to Y gain).
AI21
AI22
AI23
AI24
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB752
MHB753
Fig.65 MODE0E CVBS7.
2004 Jul 22
AI12
AI13
AI14
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
CHROMA
handbook, halfpage
AI11
Fig.66 MODE0F CVBS8.
110
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
handbook, halfpage
AI11
LUMA
w.
AD1
yc
Fig.67 MODE10 CVBS9.
AI21
AI22
AI23
AI24
CHROMA
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
CHROMA
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB755
Fig.68 MODE11 CVBS10.
handbook, halfpage
AI11
AI12
AI13
AI14
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB756
MHB757
Fig.69 MODE12 CVBS11.
2004 Jul 22
LUMA
AD2
AD3
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
AD1
AI31
AI32
AI33
AI34
-d
MHB754
AI12
AI13
AI14
AI12
AI13
AI14
LUMA
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
Fig.70 MODE13 CVBS12.
111
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
handbook, halfpage
AI11
LUMA
w.
AD1
yc
Fig.71 MODE14 CVBS13.
AI21
AI22
AI23
AI24
CHROMA
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
MHB760
CHROMA
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB759
Fig.72 MODE15 CVBS14.
handbook, halfpage
AI11
AI12
AI13
AI14
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB761
Fig.73 MODE16 YC5 (gain -> GAI2 level).
2004 Jul 22
LUMA
AD2
AD3
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
AD1
AI31
AI32
AI33
AI34
-d
MHB758
AI12
AI13
AI14
AI12
AI13
AI14
LUMA
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
Fig.74 MODE17 YC6 (gain -> GAI2 level).
112
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
AI12
AI13
AI14
LUMA
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
LUMA
CHROMA
AD2
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB763
-d
MHB762
AD1
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
handbook, halfpage
AI11
AD1
LUMA
w.
AI12
AI13
AI14
Fig.76 MODE19 YC6 (gain adapted to Y gain).
yc
Fig.75 MODE18 YC5 (gain adapted to Y gain).
AI21
AI22
AI23
AI24
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
MHB764
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB765
Fig.77 MODE1A YC7 (gain -> GAI2 level).
2004 Jul 22
AI12
AI13
AI14
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
CHROMA
handbook, halfpage
AI11
Fig.78 MODE1B YC8 (gain -> GAI2 level).
113
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
AI12
AI13
AI14
LUMA
CHROMA
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
LUMA
CHROMA
AD2
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB767
-d
MHB766
AD1
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
handbook, halfpage
AI11
AD1
LUMA
w.
AI12
AI13
AI14
Fig.80 MODE1D YC8 (gain adapted to Y gain).
yc
Fig.79 MODE1C YC7 (gain adapted to Y gain).
AI21
AI22
AI23
AI24
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
AD1
LUMA
CHROMA
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB768
MHB769
Fig.81 MODE1E CVBS15.
2004 Jul 22
AI12
AI13
AI14
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
CHROMA
handbook, halfpage
AI11
Fig.82 MODE1F CVBS16.
114
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
AI12
AI13
AI14
SYNC
(LUMA)
(CHROMA)
AI21
AI22
AI23
AI24
AD2
Y
AD3
CB
AD4
CR
MUX
AD1
SYNC
(LUMA)
w.
AI12
AI13
AI14
yc
Fig.83 MODE20 SY-PB-PR1.
handbook, halfpage
AI11
AI21
AI22
AI23
AI24
(CHROMA)
AD3
AI41
AI42
AI43
AI44
AD4
Y
AD3
AI41
AI42
AI43
AI44
AD4
CB
CR
MUX
MHB772
Y
CB
CR
MUX
MHB771
handbook, halfpage
AI11
AI12
AI13
AI14
AD1
SYNC
(LUMA)
(CHROMA)
AD2
Y
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
CB
CR
MUX
MHB773
Fig.85 MODE2E SY-PB-PR3.
2004 Jul 22
(CHROMA)
Fig.84 MODE21 SY-PB-PR2.
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
SYNC
(LUMA)
AD2
AI31
AI32
AI33
AI34
-d
MHB770
AD1
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
Fig.86 MODE2F SY-PB-PR4.
115
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
AI31
AI32
AI33
AI34
AI41
AI42
AI43
AI44
AD1
(CHROMA)
AI21
AI22
AI23
AI24
AD2
G
AD3
B
AD4
R
MUX
handbook, halfpage
AI11
SYNC
(LUMA)
w.
AD1
yc
Fig.87 MODE30 SRGB1.
AI21
AI22
AI23
AI24
(CHROMA)
AI41
AI42
AI43
AI44
G
AD3
AD4
B
R
MUX
(CHROMA)
AI41
AI42
AI43
AI44
AD4
G
B
R
MUX
MHB775
Fig.88 MODE31 SRGB2.
handbook, halfpage
AI11
AI12
AI13
AI14
AD1
SYNC
(LUMA)
(CHROMA)
AD2
G
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
B
R
MUX
MHB776
MHB777
Fig.89 MODE3E SRGB3.
2004 Jul 22
SYNC
(LUMA)
AD2
AD3
AI21
AI22
AI23
AI24
AD2
ww
AI31
AI32
AI33
AI34
AD1
AI31
AI32
AI33
AI34
-d
MHB774
AI12
AI13
AI14
AI12
AI13
AI14
SYNC
(LUMA)
co
AI21
AI22
AI23
AI24
handbook, halfpage
AI11
z.
AI12
AI13
AI14
m
handbook, halfpage
AI11
SAA7118
Fig.90 MODE3F SRGB4.
116
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
handbook, halfpage
AI11
AD1
AD2
AI31
AI32
AI33
AI34
AD3
AI41
AI42
AI43
AI44
AD4
co
AI21
AI22
AI23
AI24
ADP [8:0]
z.
AI12
AI13
AI14
m
SAA7118
DOSL [1:0]
MUX
-d
MHB778
ww
w.
yc
Fig.91 VSB MODES (use CVBS modes with REFA = 1, DOSL = 0 to 3 and GAFIX = 1).
2004 Jul 22
117
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.2.4
SAA7118
SUBADDRESS 03H
Table 42 Analog input control 2 (AICO2); 03H[6:0]
D6 HL not reference select
HLNRS
D5 AGC hold during vertical
blanking period
VBSL
D4 colour peak off
CPOFF
FUNCTION
m
SYMBOL VALUE
0
normal clamping if decoder is in unlocked state
1
reference select if decoder is in unlocked state
0
short vertical blanking (AGC disabled during equalization
and serration pulses); recommended setting
1
long vertical blanking (AGC disabled from start of
pre-equalization pulses until start of active video (line 22 for
60 Hz, line 24 for 50 Hz)
0
colour peak control active (AD signal is attenuated, if
maximum input level is exceeded, avoids clipping effects on
screen)
co
DESCRIPTION
z.
BIT
1
colour peak off
D3 automatic gain control
integration
HOLDG
0
AGC active
D2 gain control fix
GAFIX
D1 static gain control channel 2
sign bit
GAI28
see Table 44
D0 static gain control channel 1
sign bit
GAI18
see Table 43
1
AGC integration hold (freeze)
automatic gain controlled by MODE5 to MODE0
-d
0
15.2.5
SUBADDRESS 04H
gain is user programmable via GAI[17:10] and GAI[27:20]
yc
1
Table 43 Analog input control 3 (AICO3): static gain control channel 1; 03H[0] and 04H[7:0]
DECIMAL
VALUE
−3
145...
...511
SIGN BIT
03H[0]
CONTROL BITS D7 TO D0
GAI18
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
+6
1
1
1
1
1
1
1
1
1
GAI21
GAI20
w.
0...
...144
SUBADDRESS 05H
ww
15.2.6
GAIN
(dB)
Table 44 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0]
DECIMAL
VALUE
GAIN
(dB)
SIGN BIT
03H[1]
CONTROL BITS D7 TO D0
GAI28
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
0...
−3
0
0
0
0
0
0
0
0
0
...144
0
0
1
0
0
1
0
0
0
0
145...
0
0
1
0
0
1
0
0
0
1
...511
+6
1
1
1
1
1
1
1
1
1
2004 Jul 22
118
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.2.7
SAA7118
SUBADDRESS 06H
Table 45 Horizontal sync start; 06H[7:0]
HSB7
HSB6
−128...−109 (50 Hz)
HSB5
HSB3
HSB2
HSB1
HSB0
co
forbidden (outside available central counter range)
−128...−108 (60 Hz)
−108 (50 Hz)...
1
0
0
1
0
1
0
0
−107 (60 Hz)...
1
0
0
1
0
1
0
1
...108 (50 Hz)
0
1
1
0
1
1
0
0
...107 (60 Hz)
0
1
1
0
1
0
1
1
HSS1
HSS0
forbidden (outside available central counter range)
z.
109...127 (50 Hz)
108...127 (60 Hz)
15.2.8
HSB4
m
CONTROL BITS D7 TO D0
DELAY TIME
(STEP SIZE = 8/LLC)
SUBADDRESS 07H
Table 46 Horizontal sync stop; 07H[7:0]
HSS7
−128...−109 (50 Hz)
1
−107 (60 Hz)...
1
109...127 (50 Hz)
HSS3
HSS2
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
forbidden (outside available central counter range)
ww
2004 Jul 22
HSS4
0
w.
108...127 (60 Hz)
HSS5
yc
−108 (50 Hz)...
...107 (60 Hz)
HSS6
forbidden (outside available central counter range)
−128...−108 (60 Hz)
...108 (50 Hz)
-d
CONTROL BITS D7 TO D0
DELAY TIME
(STEP SIZE = 8/LLC)
119
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.2.9
SAA7118
SUBADDRESS 08H
Table 47 Sync control; 08H[7:0]
automatic field detection
SYMBOL VALUE
AUFD
FUNCTION
m
D7
DESCRIPTION
0
field state directly controlled via FSEL
1
automatic field detection; recommended setting
50 Hz, 625 lines
co
BIT
field selection; active if
AUFD = 0
FSEL
0
1
60 Hz, 525 lines
D5
forced ODD/EVEN toggle
FOET
0
ODD/EVEN signal toggles only with interlaced source
1
ODD/EVEN signal toggles fieldwise even if source is
non-interlaced
00
TV mode, recommended for poor quality TV signals only; do
not use for new applications
D[4:3] horizontal time constant
selection
HTC[1:0]
01
10
11
horizontal PLL
HPLL
reserved
fast locking mode; recommended setting
PLL closed
VNOI[1:0]
1
PLL open; horizontal frequency fixed
00
normal mode; recommended setting
01
fast mode, applicable for stable sources only; automatic field
detection (AUFD) must be disabled
10
free running mode
11
vertical noise reduction bypassed
ww
w.
yc
D[1:0] vertical noise reduction
0
VTR mode, recommended if a deflection control circuit is
directly connected to the SAA7118
-d
D2
z.
D6
2004 Jul 22
120
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.10 SUBADDRESS 09H
Table 48 Luminance control; 09H[7:0]
SYMBOL VALUE
chrominance trap/comb filter
bypass
BYPS
FUNCTION
m
D7
DESCRIPTION
0
chrominance trap or luminance comb filter active;
default for CVBS mode
1
chrominance trap or luminance comb filter bypassed;
default for S-video mode
disabled (= chrominance trap enabled, if BYPS = 0)
co
BIT
adaptive luminance comb filter
YCOMB
0
1
active, if BYPS = 0
D5
processing delay in non comb
filter mode
LDEL
0
processing delay is equal to internal pipelining delay;
recommended setting
remodulation bandwidth for
luminance; see Figs 14 to 17
LUFI[3:0]
one (NTSC standards) or two (PAL standards) video
lines additional processing delay
0
small remodulation bandwidth
(narrow chroma notch ⇒ higher luminance bandwidth)
1
large remodulation bandwidth
(wider chroma notch ⇒ smaller luminance bandwidth)
0001
resolution enhancement filter 8.0 dB at 4.1 MHz
0010
resolution enhancement filter 6.8 dB at 4.1 MHz
0011
resolution enhancement filter 5.1 dB at 4.1 MHz
0100
resolution enhancement filter 4.1 dB at 4.1 MHz
0101
resolution enhancement filter 3.0 dB at 4.1 MHz
0110
resolution enhancement filter 2.3 dB at 4.1 MHz
w.
yc
D[3:0] sharpness control, luminance
filter characteristic; see Fig.18
LUBW
1
-d
D4
z.
D6
0111
resolution enhancement filter 1.6 dB at 4.1 MHz
0000
plain
1000
low-pass filter 2 dB at 4.1 MHz
1001
low-pass filter 3 dB at 4.1 MHz
1010
low-pass filter 3 dB at 3.3 MHz; 4 dB at 4.1 MHz
1011
low-pass filter 3 dB at 2.6 MHz; 8 dB at 4.1 MHz
1100
low-pass filter 3 dB at 2.4 MHz; 14 dB at 4.1 MHz
1101
low-pass filter 3 dB at 2.2 MHz; notch at 3.4 MHz
1110
low-pass filter 3 dB at 1.9 MHz; notch at 3.0 MHz
1111
low-pass filter 3 dB at 1.7 MHz; notch at 2.5 MHz
ww
15.2.11 SUBADDRESS 0AH
Table 49 Luminance brightness control: decoder part; 0AH[7:0]
CONTROL BITS D7 TO D0
OFFSET
DBRI7
DBRI6
DBRI5
DBRI4
DBRI3
DBRI2
DBRI1
DBRI0
255 (bright)
1
1
1
1
1
1
1
1
128 (ITU level)
1
0
0
0
0
0
0
0
0 (dark)
0
0
0
0
0
0
0
0
2004 Jul 22
121
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.12 SUBADDRESS 0BH
Table 50 Luminance contrast control: decoder part; 0BH[7:0]
DCON6
DCON5
DCON4
DCON3
1.984 (maximum)
0
1
1
1
1
1.063 (ITU level)
0
1
0
0
0
1
0
0
0
0
0
0
−1 (inverse luminance)
1
1
0
0
−2 (inverse luminance)
1
0
0
0
15.2.13 SUBADDRESS 0CH
DCON1
DCON0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
z.
1.0
0 (luminance off)
DCON2
co
DCON7
m
CONTROL BITS D7 TO D0
GAIN
Table 51 Chrominance saturation control: decoder part; 0CH[7:0]
CONTROL BITS D7 TO D0
GAIN
DSAT6
DSAT5
DSAT4
DSAT3
DSAT2
DSAT1
DSAT0
1.984 (maximum)
0
1
1
1
1
1
1
1
1.0 (ITU level)
0
1
0
0
0
0
0
0
0 (colour off)
0
0
0
0
0
0
0
0
−1 (inverse chrominance)
1
1
0
0
0
0
0
0
−2 (inverse chrominance)
1
0
0
0
0
0
0
0
yc
15.2.14 SUBADDRESS 0DH
-d
DSAT7
Table 52 Chrominance hue control; 0DH[7:0]
CONTROL BITS D7 TO D0
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
HUEC0
0
1
1
1
1
1
1
1
w.
HUE PHASE (DEG)
+178.6...
0
0
0
0
0
0
0
0
...−180
1
0
0
0
0
0
0
0
ww
...0...
2004 Jul 22
122
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.15 SUBADDRESS 0EH
Table 53 Chrominance control 1; 0EH[7:0]
DESCRIPTION
SYMBOL
VALUE
50 Hz/625 LINES
CDTO
0
disabled
1
Every time CDTO is set, the internal subcarrier DTO
phase is reset to 0° and the RTCO output generates a
logic 0 at time slot 68 (see document “RTC Functional
Description”, available on request). So an identical
subcarrier phase can be generated by an external device
(e.g. an encoder); if a DTO reset is programmed via
CDTO it has always to be executed in the following way:
co
clear DTO
60 Hz/525 LINES
z.
D7
m
FUNCTION
BIT
1. Set CDTO = 0
2. Set CDTO = 1.
D[6:4]
colour standard selection
in non AUTO mode
CSTD[2:0]
000
001
PAL BGDHI (4.43 MHz) NTSC M (3.58 MHz)
NTSC 4.43 (50 Hz)
PAL 4.43 (60 Hz)
Combination-PAL N
(3.58 MHz)
NTSC 4.43 (60 Hz)
011
NTSC N (3.58 MHz)
PAL M (3.58 MHz)
100
reserved
NTSC-Japan (3.58 MHz)
101
SECAM
reserved
-d
010
110
yc
111
colour standard selection
in AUTO mode (AUTO
mode is selected, if either
AUTO0 or AUTO1 is set;
see below)
CSTD[2:0]
ww
w.
D[6:4]
D3
D2
disable chrominance
vertical filter and PAL
phase error correction
DCVF
fast colour time constant
FCTC
2004 Jul 22
000
reserved; do not use
reserved; do not use
preferred standard(1) is preferred standard(1) is
PAL BGDHI (4.43 MHz) NTSC M (3.58 MHz)
001
reserved; do not use
010
reserved; do not use
011
reserved; do not use
100
preferred standard(1) is preferred standard(1) is
PAL BGDHI (4.43 MHz) NTSC-Japan (3.58 MHz, no
7.5 IRE offset)
101
preferred standard(1) is
SECAM
preferred standard(1) is
NTSC M (3.58 MHz)
110
reserved; do not use
111
reserved; do not use
0
chrominance vertical filter and PAL phase error
correction on (during active video lines)
1
chrominance vertical filter and PAL phase error
correction permanently off
0
nominal time constant
1
fast time constant for special applications (high quality
input source, fast chroma lock required, automatic
standard detection off)
123
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
FUNCTION
BIT
DESCRIPTION
SYMBOL
VALUE
adaptive chrominance
comb filter
CCOMB
disabled
active, filter settings and sharpness control are preset to
default values according to the detected standard and
mode; recommended setting
10
active, filter settings are preset to default values
according to the detected standard and mode
11
active, but no filter presets
0
disabled
1
active
co
D0
00
01
z.
14H[2] automatic chrominance
AUTO[1:0]
and
standard detection control
0EH[1]
60 Hz/525 LINES
m
50 Hz/625 LINES
Note
1. The meaning of ‘preferred standard’ is, that the internal search machine will always give priority to the selected
standard, thus the recognition time for these standards is kept short.
15.2.16 SUBADDRESS 0FH
BIT
D7
DESCRIPTION
automatic chrominance
gain control
SYMBOL
VALUE
ACGC
0
on; recommended setting
1
programmable gain via CGAIN6 to CGAIN0; need to be
set for SECAM standard
CGAIN[6:0] 000 0000 minimum gain (0.5)
yc
D[6:0] chrominance gain value
(if ACGC is set to logic 1)
-d
Table 54 Chrominance gain control; 0FH[7:0]
010 0100 nominal gain (1.125)
ww
w.
111 1111 maximum gain (7.5)
2004 Jul 22
124
FUNCTION
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.17 SUBADDRESS 10H
Table 55 Chrominance control 2; 10H[7:0]
DESCRIPTION
D[5:4] fine offset adjustment R − Y component
chrominance bandwidth; see Figs 12 and 13
15.2.18 SUBADDRESS 11H
BIT
D6
polarity of RTS1 output signal
D[5:4] fine position of HS (steps in 2/LLC)
polarity of RTS0 output signal
LSB
10
2
LSB
11
3⁄
4
LSB
00
0 LSB
01
1⁄
4
LSB
10
1⁄
2
LSB
11
3⁄
4
LSB
small
1
wide
000
...
111
smallest chrominance
bandwidth/largest luminance
bandwidth
... to ...
largest chrominance
bandwidth/smallest luminance
bandwidth
COLO
0
1
colour forced on
RTP1
0
non-inverted
1
inverted
00
0
01
1
10
2
11
3
0
non-inverted
1
inverted
YDEL[2:0]
125
0
VALUE
RTP0
D[2:0] luminance delay compensation (steps in 2/LLC)
2004 Jul 22
4
1⁄
SYMBOL
HDEL[1:0]
ww
D3
1⁄
LCBW[2:0]
w.
colour on
0 LSB
01
CHBW
DESCRIPTION
D7
00
OFFV[1:0]
yc
Table 56 Mode/delay control; 11H[7:0]
OFFU[1:0]
-d
D[2:0] combined luminance/chrominance bandwidth
adjustment; see Figs 12 to 18
FUNCTION
z.
D3
VALUE
co
D[7:6] fine offset adjustment B − Y component
SYMBOL
m
BIT
FUNCTION
automatic colour killer enabled;
recommended setting
100
−4...
000
...0...
011
...3
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.19 SUBADDRESS 12H
The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]].
RTS0 OUTPUT
m
Table 57 RT signal control: RTS0 output; 12H[3:0]
RTSE03 RTSE02 RTSE01 RTSE00
0
0
co
3-state
Constant LOW
0
CREF (13.5 MHz toggling pulse; see Fig.30)
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
V123; vertical sync (see vertical timing diagrams Figs 28 and 29)
1
1
0
0
VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1]
16H[7:0] and VGPS[17H[2]]
1
1
0
1
LSBs of the 9-bit ADC’s
1
1
1
0
FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical
timing diagrams Figs 28 and 29
1
1
1
1
CREF2 (6.75 MHz toggling pulse; see Fig.30)
HL; horizontal lock indicator (note 1):
HL = 1: locked
VL; vertical and horizontal lock:
VL = 0: unlocked
VL = 1: locked
DL; vertical and horizontal lock and colour detected:
-d
DL = 0: unlocked
z.
HL = 0: unlocked
DL = 1: locked
Reserved
yc
HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active
line. HREF is also generated during the vertical blanking interval
(see Fig.30).
HS:
programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0]
07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]
(see Fig.30)
ww
Reserved
w.
HQ; HREF gated with VGATE
Note
1. Function of HL is selectable via HLSEL[13H[3]]:
a) HLSEL = 0: HL is standard horizontal lock indicator.
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.
VCRs).
2004 Jul 22
126
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 58 RT signal control: RTS1 output; 12H[7:4]
The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]].
RTSE13 RTSE12 RTSE11 RTSE10
3-state
0
Constant LOW
0
0
CREF2 (6.75 MHz toggling pulse; see Fig.30)
HL; horizontal lock indicator (note 1):
HL = 0: unlocked
HL = 1: locked
VL = 1: locked
DL; vertical and horizontal lock and colour detected:
DL = 0: unlocked
DL = 1: locked
0
0
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active
line. HREF is also generated during the vertical blanking interval
(see Fig.30).
1
0
0
0
HS:
1
0
0
1
1
0
1
0
-d
Reserved
0
0
z.
VL; vertical and horizontal lock:
VL = 0: unlocked
0
co
CREF (13.5 MHz toggling pulse; see Fig.30)
m
RTS1 OUTPUT
yc
programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0]
07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]
(see Fig.30)
HQ; HREF gated with VGATE
1
0
1
1
V123; vertical sync (see vertical timing diagrams Figs 28 and 29)
1
1
0
0
VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1]
16H[7:0] and VGPS[17H[2]]
1
1
0
1
Reserved
1
1
1
0
1
1
1
1
w.
Reserved
ww
FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical
timing diagrams Figs 28 and 29
Note
1. Function of HL is selectable via HLSEL[13H[3]]:
a) HLSEL = 0: HL is standard horizontal lock indicator.
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.
VCRs).
2004 Jul 22
127
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.20 SUBADDRESS 13H
Table 59 RT/X port output control; 13H[7:0]
D7
RTCO output enable
D6
X port XRH output
selection
SYMBOL VALUE
RTCE
XRHS
FUNCTION
m
DESCRIPTION
0
3-state
1
enabled
0
HREF (see Fig.30)
1
HS:
co
BIT
programmable width in LLC8 steps via HSB[7:0] 06H[7:0]
and HSS[7:0] 07H[7:0]
D[5:4] X port XRV output
selection
XRVS[1:0]
00
01
10
11
horizontal lock indicator
selection
0
1
ITU 656 related field ID (see Figs 28 and 29)
inverted V123
inverted ITU 656 related field ID
copy of inverted HLCK status bit (default)
fast horizontal lock indicator (for special applications only)
OFTS[2:0]
000
ITU 656
001
ITU 656 like format with modified field blanking according to
VGATE position (programmable via VSTA[8:0] 17H[0]
15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]])
010
Y-CB-CR 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)
011
reserved
100
multiplexed AD2/AD1 or AD4/AD3 bypass (bits D8 to D1)
dependent on mode settings (see Section 15.2.3); if two
ADCs are selected AD2/AD4 is output at CREF = 1 and
AD1/AD3 is output at CREF = 0
101
multiplexed AD2/AD1 or AD4/AD3 bypass (bits D7 to D0)
dependent on mode settings (see Section 15.2.3); if two
ADCs are selected AD2/AD4 is output at CREF = 1 and
AD1/AD3 is output at CREF = 0
110
reserved
111
multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF = 0
ww
w.
yc
D[2:0] XPD7 to XPD0 (port
output format selection);
see Section 9.5
HLSEL
V123 (see Figs 28 and 29)
-d
D3
z.
fine position adjustment in LLC2 steps via HDEL[1:0]
11H[5:4] (see Fig.30)
2004 Jul 22
128
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.21 SUBADDRESS 14H
Table 60 Analog/ADC/auto/compatibility control; 14H[7:0]
update time interval for
AGC value
23H[7] analog test select
and
14H[5:4]
D3
XTOUT output enable
D2
automatic chrominance
standard detection
control 1
CM99
0
off (default)
1
on (to be set only if SAA7199 is used for re-encoding in
conjunction with RTCO active)
UPTCV
0
horizontal update (once per line)
AOSL[2:0]
000
AOUT connected to ground
001
AOUT connected to input AD1
010
AOUT connected to input AD2
011
AOUT connected to input AD3
100
AOUT connected to input AD4
101
reserved
110
reserved
111
AOUT connected to internal test point BPFOUT
1
XTOUTE
0
vertical update (once per field)
XTOUT 3-stated
1
ADC sample clock phase
delay
XTOUT enabled
AUTO1
APCK[1:0]
00
01
10
ww
w.
11
2004 Jul 22
see Section 15.2.15
application dependent
yc
D[1:0]
FUNCTION
m
VALUE
co
D6
compatibility bit for
SAA7199
SYMBOL
z.
D7
DESCRIPTION
-d
BIT
129
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FRAME LINE
COUNTING
FIELD
50 Hz
60 Hz
1st
1
2nd
314
1st
2
2nd
315
1st
312
2nd
625
1st
4
2nd
267
130
1st
5
2nd
268
1st
265
2nd
3
DECIMAL
VALUE
MSB
17H[0]
VSTA8
.y
CONTROL BITS D7 TO D0
VSTA7
VSTA6
VSTA5
VSTA4
VSTA3
VSTA2
VSTA1
VSTA0
312
1
0
0
1
1
1
0
0
0
0...
0
0
0
0
0
0
0
0
0
...310
1
262
1
0...
0
...260
1
c-
0
0
1
1
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
dz
.c
Product specification
SAA7118
om
Philips Semiconductors
ww
w
Table 61 VGATE start; FID polarity change; 17H[0] and 15H[7:0]
Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figs 28 and 29.
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
15.2.22 SUBADDRESS 15H
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FRAME LINE
COUNTING
FIELD
50 Hz
60 Hz
1st
1
2nd
314
1st
2
2nd
315
1st
312
2nd
625
1st
4
2nd
267
131
1st
5
2nd
268
1st
265
2nd
3
DECIMAL
VALUE
MSB
17H[1]
VSTO8
.y
CONTROL BITS D7 TO D0
VSTO7
VSTO6
VSTO5
VSTO4
VSTO3
VSTO2
VSTO1
VSTO0
312
1
0
0
1
1
1
0
0
0
0...
0
0
0
0
0
0
0
0
0
...310
1
262
1
0...
0
...260
1
c-
0
0
1
1
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
dz
0
0
0
0
0
0
0
0
0
1
0
1
.c
Product specification
SAA7118
om
Philips Semiconductors
ww
w
Table 62 VGATE stop; 17H[1] and 16H[7:0]
Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figs 28 and 29.
Multistandard video decoder with adaptive
comb filter and component video input
2004 Jul 22
15.2.23 SUBADDRESS 16H
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.24 SUBADDRESS 17H
Table 63 Miscellaneous/VGATE MSBs; 17H[7:0]
D6
LLC output enable
LLCE
LLC2 output enable
D[5:3] standard detection search
loop latency
0
enable
1
3-state
LLC2E
0
enable
1
3-state
LATY[2:0]
000
reserved
001
one field
010
two fields
011
three fields; recommended setting
...
111
alternative VGATE
position
VGPS
0
D1
MSB VGATE stop
VSTO8
D0
MSB VGATE start
VSTA8
1
15.2.25 SUBADDRESS 18H
... to ...
seven fields
VGATE position according to Tables 61 and 62
VGATE occurs one line earlier during field 2
see Table 62
-d
D2
FUNCTION
m
SYMBOL VALUE
co
D7
DESCRIPTION
z.
BIT
see Table 61
Table 64 Raw data gain control; RAWG[7:0] 18H[7:0]; see Fig.20
CONTROL BITS D7 TO D0
GAIN
128 (nominal level)
0 (off)
RAWG5
RAWG4
RAWG3
RAWG2
RAWG1
RAWG0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
w.
15.2.26 SUBADDRESS 19H
RAWG6
yc
255 (double amplitude)
RAWG7
Table 65 Raw data offset control; RAWO[7:0] 19H[7:0]; see Fig.20
CONTROL BITS D7 TO D0
OFFSET
RAWO6
RAWO5
RAWO4
RAWO3
RAWO2
RAWO1
RAWO0
−128 LSB
0
0
0
0
0
0
0
0
0 LSB
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ww
RAWO7
+128 LSB
2004 Jul 22
132
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.2.27 SUBADDRESS 1EH
D6
I2C-BUS
CONTROL BIT
DESCRIPTION
status bit for locked horizontal frequency
HLCK
D5
slow time constant active in WIPA mode
D4
gain value for active luminance channel is limited;
maximum (top)
D[1:0]
gain value for active luminance channel is limited;
minimum (bottom)
GLIMT
GLIMB
z.
D2
white peak loop is activated
WIPA
detected colour standard
15.2.28 SUBADDRESS 1FH
0
SLTCA
DCSTD[1:0]
-d
D3
VALUE
FUNCTION
locked
co
BIT
m
Table 66 Status byte 1 video decoder; 1EH[6:0]; read only register
1
unlocked
0
not active
1
active
0
not active
1
active
0
not active
1
active
0
not active
1
active
00
no colour
(black-white)
01
NTSC
10
PAL
11
SECAM
BIT
yc
Table 67 Status byte 2 video decoder; 1FH[7:5] and 1FH[3:0]; read only register
DESCRIPTION
status bit for interlace detection
D6
status bit for horizontal and vertical loop
D5
w.
D7
identification bit for detected field frequency
I2C-BUS
CONTROL BIT
VALUE
INTL
0
1
interlaced
HLVLN
0
both loops locked
1
unlocked
0
50 Hz
1
60 Hz
TYPE3
0
not active
1
active
0
not active
1
active
0
not active
1
active
0
not active
1
active
FIDT
Macrovision encoded colour stripe burst type 3 (4 line
version) detected
D2
Macrovision encoded colour stripe burst detected
(any type)
COLSTR
copy protected source detected according to
Macrovision version up to 7.01
COPRO
ready for capture (all internal loops locked)
RDCAP
ww
D3
D1
D0
2004 Jul 22
133
FUNCTION
non-interlaced
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.3
SAA7118
Programming register RGB/Y-PB-PR component input processing
15.3.1
SUBADDRESS 23H
BIT
DESCRIPTION
m
Table 68 Analog input control 5 (AICO5); 23H[7:4] and 23H[2:0]
SYMBOL VALUE
FUNCTION
AOSL2
D6 AD port output enable
ADPE
0
1
AD port is enabled
D5 ADC clock selector
EXCLK
0
all ADCs are clocked by the internal generated line-locked
clock
1
all ADCs are clocked by the external input clock on CLKEXT
REFA
D2 enable external source
switch indicator input
EXMCLR
EXMCE
0
clamping is dependent on HLNRS[03H[6]]
1
reference selection (input signal is pulled into ADC range)
0
disabled
1
GAI48
D0 static gain control channel 1
sign bit
GAI38
SUBADDRESS 24H
enabled (any slope on EXMCLR input will reset the internal
gain control loop)
see Table 70
-d
D1 static gain control channel 2
sign bit
15.3.2
AD port is set to 3-state
z.
D4 clamping/reference
selection for all ADCs
see Table 60
co
D7 analog output select
see Table 69
DECIMAL
VALUE
GAIN
(dB)
−3
...144
0
145...
0
...511
15.3.3
SIGN BIT
23H[0]
+6
CONTROL BITS D7 TO D0
GAI38
GAI37
GAI36
GAI35
GAI34
GAI33
GAI32
GAI31
GAI30
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
GAI41
GAI40
w.
0...
yc
Table 69 Analog input control 6 (AICO6): static gain control channel 3; 23H[0] and 24H[7:0]
SUBADDRESS 25H
Table 70 Analog input control 7 (AICO7): static gain control channel 4; 23H[1] and 25H[7:0]
GAIN
(dB)
SIGN BIT
23H[1]
ww
DECIMAL
VALUE
CONTROL BITS D7 TO D0
GAI48
GAI47
GAI46
GAI45
GAI44
GAI43
GAI42
0...
−3
0
0
0
0
0
0
0
0
0
...144
0
0
1
0
0
1
0
0
0
0
145...
0
0
1
0
0
1
0
0
0
1
...511
+6
1
1
1
1
1
1
1
1
1
2004 Jul 22
134
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.3.4
SAA7118
SUBADDRESS 29H
Table 71 Component delay/fast switch control; 29H[7:0]
D6
fast switch input
polarity if FSWE = 1
VALUE
FSWE
0
disabled
1
pixelwise switching between decoded CVBS signal and
component input signal is enabled (should only be used for
component sources synchronous to CVBS input)
0
FSW = 0: decoded CVBS signal, FSW = 1: component signal
1
FSW = 1: decoded CVBS signal, FSW = 0: component signal
0
for modes 00H to 1FH
1
for modes 20H to 3FH
FSWI
static selection if
FSWE = 0
D3
component luminance
peaking
15.3.5
SUBADDRESS 2AH
CMFI
00
0 pixel (default)
01
+1 pixel
10
−2 pixel
11
−1 pixel
0
disabled
1
enabled (+1.5 dB at 5 MHz)
CPDL[2:0]
000
0 pixel (default)
001
+4 pixel
010
+8 pixel
011
+12 pixel
100
−16 pixel
101
−12 pixel
110
−8 pixel
111
−4 pixel
yc
D[2:0] component input delay
adjustment relative to
decoded CVBS signal
FSWDL[1:0]
-d
D[5:4] fast switch input delay
adjustment relative to
component input
signal
FUNCTION
m
fast switch enable
SYMBOL
co
D7
DESCRIPTION
z.
BIT
w.
Table 72 Luminance brightness control component part; 2AH[7:0]
CONTROL BITS D7 TO D0
OFFSET
CBRI7
CBRI6
CBRI5
CBRI4
CBRI3
CBRI2
CBRI1
CBRI0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0 (dark)
0
0
0
0
0
0
0
0
ww
255 (bright)
128 (ITU level)
2004 Jul 22
135
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.3.6
SAA7118
SUBADDRESS 2BH
Table 73 Luminance contrast control component part; 2BH[7:0]
m
CONTROL BITS D7 TO D0
GAIN
CCON6
CCON5
CCON4
CCON3
CCON2
CCON1
CCON0
1.984 (maximum)
0
1
1
1
1
1
1
1
1.0 (ITU level)
0
1
0
0
0
0
0
0
co
CCON7
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
−2.0 (inverse luminance)
1
0
0
0
0
0
0
0
15.3.7
SUBADDRESS 2CH
z.
0 (luminance off)
−1.0 (inverse luminance)
Table 74 Chrominance saturation control component part; 2CH[7:0]
CONTROL BITS D7 TO D0
GAIN
CSAT7
CSAT6
CSAT5
CSAT4
CSAT3
CSAT2
CSAT1
CSAT0
0
1
1
1
1
1
1
1
1.0 (ITU level)
0
0 (colour off)
0
−1.0 (inverse chrominance)
1
−2.0 (inverse chrominance)
1
Interrupt mask registers
See also Section 9.4
15.4.1
SUBADDRESS 2DH
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
yc
15.4
0
0
-d
1.984 (maximum)
Table 75 Interrupt mask 1; 2DH[4:2] and 2DH[1]
BIT
DESCRIPTION
w.
D4 interrupt enable ‘VPS signal detected/lost’ (corresponding flag: 60H[4])
D3 interrupt enable ‘PALplus detected/lost’ (corresponding flag: 60H[3])
ww
D2 interrupt enable ‘closed caption detected/lost’ (corresponding flag: 60H[2])
D0 interrupt enable ‘error output formatter’ (corresponding flag: 8FH[2])
2004 Jul 22
136
SYMBOL
MVPSV
MPPV
MCCV
MERROF
VALUE FUNCTION
0
disabled
1
enabled
0
disabled
1
enabled
0
disabled
1
enabled
0
disabled
1
enabled
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.4.2
SAA7118
SUBADDRESS 2EH
Table 76 Interrupt mask 2; 2EH[6] and 2EH[1:0]
SYMBOL
D6 interrupt enable ‘horizontal PLL locked/unlocked’ (corresponding flag:
1EH[6])
VALUE FUNCTION
m
DESCRIPTION
0
disabled
1
enabled
co
BIT
MHLCK
disabled
D1 interrupt enable ‘colour standard changed 1’ (corresponding flag: 1EH[1])
MDCSTD1
0
1
enabled
D0 interrupt enable ‘colour standard changed 0’ (corresponding flag: 1EH[0])
MDCSTD0
0
disabled
1
enabled
SUBADDRESS 2FH
z.
15.4.3
Table 77 Interrupt mask 3; 2FH[7:5] and 2FH[3:0]
BIT
DESCRIPTION
SYMBOL
D7 interrupt enable ‘interlaced/non-interlaced source’ (corresponding flag:
1FH[7])
-d
D6 interrupt enable ‘horizontal and vertical lock reached/lost’ (corresponding
flag: 1FH[6])
D5 interrupt enable ‘field frequency has changed’ (corresponding flag: 1FH[5])
D3 interrupt enable ‘colour stripe type 3 burst detected/lost’ (corresponding
flag: 1FH[3])
MINTL
MHLVLN
MFIDT
MTYPE3
VALUE FUNCTION
0
disabled
1
enabled
0
disabled
1
enabled
0
disabled
1
enabled
0
disabled
1
enabled
disabled
MCOLSTR
0
1
enabled
D1 interrupt enable ‘copy protected signal found/lost’ (corresponding flag:
1FH[1])
MCOPRO
0
disabled
1
enabled
D0 interrupt enable ‘ready for capture/not ready’ (corresponding flag: 1FH[0])
MRDCAP
0
disabled
1
enabled
15.5
w.
yc
D2 interrupt enable ‘colour stripe burst (any type) detected/lost’ (corresponding
flag: 1FH[2])
Programming register audio clock generation
See equations in Section 8.7 and examples in Tables 22 and 23.
15.5.1
SUBADDRESSES 30H TO 32H
ww
Table 78 Audio master clock (AMCLK) cycles per field
SUBADDRESS
CONTROL BITS D7 TO D0
30H
ACPF7
ACPF6
ACPF5
ACPF4
ACPF3
ACPF2
ACPF1
ACPF0
31H
ACPF15
ACPF14
ACPF13
ACPF12
ACPF11
ACPF10
ACPF9
ACPF8
32H
−
−
−
−
−
−
ACPF17
ACPF16
2004 Jul 22
137
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.5.2
SAA7118
SUBADDRESSES 34H TO 36H
SUBADDRESS
34H
ACNI7
ACNI6
ACNI5
ACNI4
ACNI3
35H
ACNI15
ACNI14
ACNI13
ACNI12
ACNI11
36H
−
−
ACNI21
ACNI20
SUBADDRESS 38H
ACNI8
ACNI18
ACNI17
ACNI16
SDIV2
SDIV1
SDIV0
LRDIV2
LRDIV1
LRDIV0
ACNI2
ACNI1
ACNI0
ACNI10
ACNI9
co
15.5.3
CONTROL BITS D7 TO D0
m
Table 79 Audio master clock (AMCLK) nominal increment
ACNI19
Table 80 Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK)
−
38H
15.5.4
CONTROL BITS D7 TO D0
−
SDIV5
SDIV4
SUBADDRESS 39H
SDIV3
z.
SUBADDRESS
Table 81 Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK)
SUBADDRESS
−
LRDIV5
SUBADDRESS 3AH
Table 82 Audio clock control; 3AH[3:0]
BIT
D2
audio PLL modes
audio master clock
vertical reference
ALRCLK phase
D0
ASCLK phase
15.6
15.6.1
SYMBOL VALUE
APLL
0
FUNCTION
PLL active, AMCLK is field-locked
1
PLL open, AMCLK is free-running
0
vertical reference pulse is taken from internal decoder
1
vertical reference is taken from XRV input (expansion port)
LRPH
0
ALRCLK edges triggered by falling edges of ASCLK
1
ALRCLK edges triggered by rising edges of ASCLK
SCPH
0
ASCLK edges triggered by falling edges of AMCLK
1
ASCLK edges triggered by rising edges of AMCLK
AMVR
w.
D1
LRDIV3
yc
D3
DESCRIPTION
LRDIV4
-d
−
39H
15.5.5
CONTROL BITS D7 TO D0
Programming register VBI data slicer
SUBADDRESS 40H
ww
Table 83 Slicer control 1; 40H[6:4]
BIT
D6
D5
D4
DESCRIPTION
Hamming check
framing code error
amplitude searching
2004 Jul 22
SYMBOL VALUE
HAM_N
FCE
HUNT_N
FUNCTION
0
Hamming check for 2 bytes after framing code,
dependent on data type (default)
1
no Hamming check
0
one framing code error allowed
1
no framing code errors allowed
0
amplitude searching active (default)
1
amplitude searching stopped
138
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.6.2
SAA7118
SUBADDRESSES 41H TO 57H
See Sections 8.3 and 8.5.
m
Table 84 Line control register; LCR2 to LCR24 (41H to 57H)
D[7:4]
(41H TO 57H)
DESCRIPTION
FRAMING CODE
co
NAME
DT[3:0] 62H[3:0]
(FIELD 1)
teletext EuroWST, CCST
27H
CC625
European closed caption
001
VPS
video programming service
WSS
wide screen signalling bits
WST525
US teletext (WST)
CC525
US closed caption (line 21)
Test line
video component signal, VBI region
Intercast
raw data
General text teletext
VITC/EBU time codes (Europe)
VITC/SMPTE time codes (USA)
Reserved
reserved
NABTS
US NABTS
Japtext
MOJI (Japanese)
JFS
Japanese format switch (L20/22)
yc
VITC525
SUBADDRESS 58H
0000
0001
9951H
0010
0010
1E3C1FH
0011
0011
27H
0100
0100
001
0101
0101
−
0110
0110
−
0111
0111
programmable
1000
1000
programmable
1001
1001
programmable
1010
1010
−
1011
1011
−
1100
1100
programmable
(A7H)
1101
1101
programmable
1110
1110
−
1111
1111
Active video video component signal, active video
region (default)
15.6.3
0000
0001
-d
VITC625
DT[3:0] 62H[3:0]
(FIELD 2)
z.
WST625
D[3:0]
(41H TO 57H)
w.
Table 85 Programmable framing code; slicer set 58H[7:0]
According to Tables 15 and 84.
FRAMING CODE FOR PROGRAMMABLE DATA TYPES
Default value
15.6.4
CONTROL BITS D7 TO D0
FC[7:0] = 40H
SUBADDRESS 59H
ww
Table 86 Horizontal offset for slicer; slicer set 59H and 5BH
HORIZONTAL OFFSET
Recommended value
2004 Jul 22
CONTROL BITS 5BH[2:0]
CONTROL BITS 59H[7:0]
HOFF[10:8] = 3H
HOFF[7:0] = 47H
139
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.6.5
SAA7118
SUBADDRESS 5AH
Table 87 Vertical offset for slicer; slicer set 5AH and 5BH
VOFF8
0
Maximum value 312
1
Value for 50 Hz 625 lines input
0
Value for 60 Hz 525 lines input
0
15.6.6
VOFF[7:0]
00H
co
Minimum value 0
CONTROL BITS 5AH[7:0]
m
CONTROL BIT 5BH[4]
VERTICAL OFFSET
38H
03H
06H
SUBADDRESS 5BH
DESCRIPTION
D7
field offset
D6
15.6.7
recode
SYMBOL
VALUE
FOFF
0
no modification of internal field indicator (default for 50 Hz
625 lines input sources)
1
invert field indicator (default for 60 Hz 525 lines input sources)
RECODE
SUBADDRESS 5DH
FUNCTION
-d
BIT
z.
Table 88 Field offset, and MSBs for horizontal and vertical offsets; slicer set 5BH[7:6]
See Sections 15.6.4 and 15.6.5 for HOFF[10:8] 5BH[2:0] and VOFF8[5BH[4]].
0
leave data unchanged (default)
1
convert 00H and FFH data bytes into 03H and FCH
Table 89 Header and data identification (DID; ITU 656) code control; slicer set 5DH[7:0]
DESCRIPTION
SYMBOL
VALUE
D7
field ID and V-blank selection
for text output (F and V
reference selection)
FVREF
0
F and V output of slicer is LCR table dependent
1
F and V output is taken from decoder real-time signals
EVEN_ITU and VBLNK_ITU
yc
BIT
D[5:0] default; DID[5:0] = 00H
DID[5:0]
15.6.8
00 0000 ANC header framing; see Fig.37 and Table 21
11 1110 DID[5:0] = 3EH SAV/EAV framing, with FVREF = 1
w.
special cases of DID
programming
FUNCTION
11 1111 DID[5:0] = 3FH SAV/EAV framing, with FVREF = 0
SUBADDRESS 5EH
Table 90 Sliced data identification (SDID) code; slicer set 5EH[5:0]
BIT
DESCRIPTION
ww
D[5:0] SDID codes
2004 Jul 22
SYMBOL
VALUE
SDID[5:0]
00H
140
FUNCTION
default
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.6.9
SAA7118
SUBADDRESS 60H
Table 91 Slicer status byte 0; 60H[6:2]; read only register
SYMBOL
VALUE
FC8V
0
no framing code (0 error) in the last frame detected
1
framing code with 0 error detected
no framing code (1 error) in the last frame detected
framing code valid
FUNCTION
m
D6
DESCRIPTION
co
BIT
D5
framing code valid
FC7V
0
1
framing code with 1 error detected
D4
VPS valid
VPSV
0
no VPS in the last frame
1
VPS detected
no PALplus in the last frame
PALplus valid
PPV
0
D2
closed caption valid
CCV
0
1
1
15.6.10 SUBADDRESSES 61H AND 62H
PALplus detected
z.
D3
no closed caption in the last frame
closed caption detected
-d
Table 92 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]; read only registers
SUBADDRESS
BIT
SYMBOL
61H
D5
F21_N
field ID as seen by the VBI slicer; for field 1: D5 = 0
LN[8:4]
line number
D[4:0]
62H
D[7:4]
15.7
15.7.1
LN[3:0]
DT[3:0]
data type; according to Table 15
yc
D[3:0]
DESCRIPTION
Programming register interfaces and scaler part
SUBADDRESS 80H
Table 93 Global control 1; global set 80H[6:4]; note 1
w.
SWRST moved to subaddress 88H[5].
CONTROL BITS D6 TO D4
TASK ENABLE CONTROL
TEB
TEA
Task of register set A is disabled
X
X
0
Task of register set A is enabled
X
X
1
Task of register set B is disabled
X
0
X
Task of register set B is enabled
X
1
X
ww
SMOD
The scaler window defines the F and V timing of the scaler output
0
X
X
VBI data slicer defines the F and V timing of the scaler output
1
X
X
Note
1. X = don’t care.
2004 Jul 22
141
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 94 Global control 1; global set 80H[3:0]; note 1
CONTROL BITS D3 TO D0
ICLK output and back-end clock is line-locked clock LLC from decoder
ICKS3
ICKS2
ICKS1
ICKS0
X
X
0
0
X
X
0
1
X
X(2)
1
0
X
X
1
1
co
ICLK output and back-end clock is XCLK from X port
m
I PORT AND SCALER BACK-END CLOCK SELECTION
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (DQ AND CLK)
IDQ generation only for valid data
0
X
X
1
X
X
0
X
X
X
1
X
X
X
z.
IDQ qualifies valid data inside the scaling region and all data outside the scaling
region
X
X
Notes
1. X = don’t care.
15.7.2
SUBADDRESSES 83H TO 87H
-d
2. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
Table 95 X port I/O enable and output clock phase control; global set 83H[5:4]
CONTROL BITS D5 AND D4
OUTPUT CLOCK PHASE CONTROL
XPCK1
0
0
0
1
XCLK phase shifted by approximately 3 ns
1
0
XCLK output inverted and shifted by approximately 3 ns
1
1
XCLK output inverted
yc
XCLK default output phase, recommended value
XPCK0
w.
Table 96 X port I/O enable and output clock phase control; global set 83H[2:0]; note 1
CONTROL BITS D2 TO D0
X PORT I/O ENABLE
XPE1
XPE0
X port output is disabled by software
X
0
0
X port output is enabled by software
X
0
1
X port output is enabled by pin XTRI at logic 0
X
1
0
X port output is enabled by pin XTRI at logic 1
X
1
1
XRDY output signal is A/B task flag from event handler (A = 1)
0
X
X
XRDY output signal is ready signal from scaler path (XRDY = 1 means the
SAA7118 is ready to receive data)
1
X
X
ww
XRQT
Note
1. X = don’t care.
2004 Jul 22
142
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 97 I port signal definitions; global set 84H[7:6] and 86H[5]
CONTROL BITS
IGP0 is A/B task flag, as defined by CONLH[90H[7]]
IGP0 is sliced data flag, framing the sliced VBI data at the I port
IGP0 is set to logic 0 (default polarity)
IGP0 is the output FIFO almost filled flag
IDG02
IDG01
IDG00
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
IGP0 is the output FIFO almost full flag, level to be programmed in subaddress 86H
1
1
0
IGP0 is the output FIFO almost empty flag, level to be programmed in subaddress 86H
1
1
1
z.
IGP0 is the output FIFO overflow flag
84H[7:6]
m
IGP0 is output field ID, as defined by OFIDC[90H[6]]
86H[5]
co
I PORT SIGNAL DEFINITIONS
Table 98 I port signal definitions; global set 84H[5:4] and 86H[4]
-d
I PORT SIGNAL DEFINITIONS
CONTROL BITS
86H[4]
84H[5:4]
IDG12
IDG11
IDG10
IGP1 is output field ID, as defined by OFIDC[90H[6]]
0
0
0
0
0
1
0
1
0
IGP1 is set to logic 0 (default polarity)
0
1
1
IGP1 is the output FIFO almost filled flag
1
0
0
IGP1 is the output FIFO overflow flag
1
0
1
IGP1 is the output FIFO almost full flag, level to be programmed in subaddress 86H
1
1
0
IGP1 is the output FIFO almost empty flag, level to be programmed in subaddress 86H
1
1
1
yc
IGP1 is A/B task flag, as defined by CONLH[90H[7]]
IGP1 is sliced data flag, framing the sliced VBI data at the I port
w.
Table 99 I port output signal definitions; global set 84H[3:0]; note 1
CONTROL BITS D3 TO D0
I PORT OUTPUT SIGNAL DEFINITIONS
IDV0
IDH1
IDH0
IGPH is a H gate signal, framing the scaler output
X
X
0
0
IGPH is an extended H gate (framing H gate during scaler output and scaler input
H reference outside the scaler window)
X
X
0
1
ww
IDV1
IGPH is a horizontal trigger pulse, on active going edge of H gate
X
X
1
0
IGPH is a horizontal trigger pulse, on active going edge of extended H gate
X
X
1
1
IGPV is a V gate signal, framing scaled output lines
0
0
X
X
IGPV is the V reference signal from scaler input
0
1
X
X
IGPV is a vertical trigger pulse, derived from V gate
1
0
X
X
IGPV is a vertical trigger pulse derived from input V reference
1
1
X
X
Note
1. X = don’t care.
2004 Jul 22
143
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 100 X port signal definitions text slicer; global set 85H[7:5]; note 1
CONTROL BITS D7 TO D5
ISWP0
ILLV
X
X
0
X
X
1
X
m
ISWP1
co
X PORT SIGNAL DEFINITIONS TEXT SLICER
Video data limited to range 1 to 254
Video data limited to range 8 to 247
Dword byte swap, influences serial output timing
D0 D1 D2 D3 ⇒ FF 00 00 SAV CB0 Y0 CR0 Y1
0
D1 D0 D3 D2 ⇒ 00 FF SAV 00 Y0 CB0 Y1 CR0
D2 D3 D0 D1 ⇒ 00 SAV FF 00 CR0 Y1 CB0 Y0
Note
1. X = don’t care.
0
1
X
1
0
X
1
1
X
z.
D3 D2 D1 D0 ⇒ SAV 00 00 FF Y1 CR0 Y0 CB0
0
Table 101 I port reference signal polarities; global set 85H[4:0]; note 1
CONTROL BITS D4 TO D0
I PORT REFERENCE SIGNAL POLARITIES
IDQ at default polarity (1 = active)
IDQ is inverted
IGPH at default polarity (1 = active)
IGPH is inverted
IGPV is inverted
IGP1 at default polarity
IGP1 is inverted
IGP0 at default polarity
Note
w.
IGP0 is inverted
yc
IGPV at default polarity (1 = active)
ww
1. X = don’t care.
2004 Jul 22
IG1P
IRVP
IRHP
IDQP
X
X
X
X
0
X
X
X
X
1
X
X
X
0
X
X
X
X
1
X
X
X
0
X
X
-d
IG0P
144
X
X
1
X
X
X
0
X
X
X
X
1
X
X
X
0
X
X
X
X
1
X
X
X
X
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 102 I port FIFO flag control and arbitration; global set 86H[7:4]; note 1
CONTROL BITS D7 TO D4
VITX1
IDG02
IDG12
X
X
0
X
X
1
See subaddress 84H: IDG11 and IDG10
X
X
See subaddress 84H: IDG01 and IDG00
I port signal definitions
I port data output inhibited
Only text data is transferred (no EAV, SAV will occur)
Text and video data is transferred, text has priority
Note
1. X = don’t care.
X
X
0
X
X
X
1
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
z.
Only video data is transferred
m
VITX0
co
FUNCTION
-d
Table 103 I port FIFO flag control and arbitration; global set 86H[3:0]; note 1
CONTROL BITS D3 TO D0
I PORT FIFO FLAG CONTROL AND ARBITRATION
FAE FIFO flag almost empty level
<16 Dwords
yc
<8 Dwords
<4 Dwords
0 Dwords
FFL1
FFL0
FEL1
FEL0
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
0
0
X
X
0
1
X
X
FAF FIFO flag almost full level
≥16 Dwords
≥28 Dwords
32 Dwords
Note
w.
≥24 Dwords
ww
1. X = don’t care.
2004 Jul 22
145
1
0
X
X
1
1
X
X
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 104 I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1
CONTROL BITS D7 TO D4
IPCK3(2)
X
ICLK phase shifted by 1⁄2 clock cycle ⇒ recommended for ICKS1 = 1
and ICKS0 = 0 (subaddress 80H)
X
ICLK phase shifted by approximately 3 ns
1⁄
ICLK phase shifted by 2 clock cycle + approximately
3 ns ⇒ alternatively to setting ‘01’
IDQ = gated clock default output phase
2
clock cycle ⇒ recommended
IDQ = gated clock phase shifted by approximately 3 ns
IDQ = gated clock phase shifted by 1⁄2 clock cycle + approximately
3 ns ⇒ alternatively to setting ‘01’
Notes
-d
1. X = don’t care.
IPCK0
X
0
0
X
0
1
X
X
1
0
X
X
1
1
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
z.
IDQ = gated clock phase shifted by
for gated clock output
1⁄
IPCK1
co
ICLK default output phase
IPCK2(2)
m
OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL
2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).
Table 105 I port I/O enable, output clock and gated clock phase control; global set 87H[1:0]
CONTROL BITS D1 AND D0
I PORT I/O ENABLE
IPE0
I port output is disabled by software
0
0
I port output is enabled by software
0
1
I port output is enabled by pin ITRI at logic 0
1
0
I port output is enabled by pin ITRI at logic 1
1
1
ww
w.
yc
IPE1
2004 Jul 22
146
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.7.3
SAA7118
SUBADDRESS 88H
Table 106 ADC port control; global set 88H[7:4]; note 1
DOSL0
SWRST(2)
DPROG
X
X
0
X
X
X
1
X
X
0
X
X
X
1
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
DOSL1
X
DPROG = 1 can be used to assign that the device has been
programmed; this bit can be monitored in the scalers status byte,
bit PRDON; if DPROG was set to logic 1 and PRDON status bit
shows a logic 0 a power-up or start-up fail has occurred
Scaler path is reset to its idle state, software reset
Digitized ADC1 signal is fed to port ADP[8:0]
Digitized ADC2 signal is fed to port ADP[8:0]
Digitized ADC3 signal is fed to port ADP[8:0]
Digitized ADC4 signal is fed to port ADP[8:0]
1. X = don’t care.
2. Bit SWRST is now located here.
-d
Notes
z.
Scaler is switched back to operation
co
DPROG = 0 after reset
m
CONTROL BITS D7 TO D4
ADC PORT OUTPUT CONTROL/START-UP CONTROL
Table 107 Power save control; global set 88H[3] and 88H[1:0]; note 1
CONTROL BITS D3, D1 AND D0
POWER SAVE CONTROL
SLM1
SLM0
Decoder and VBI slicer are in operational mode
X
X
0
Decoder and VBI slicer are in power-down mode; scaler only operates, if scaler
input and ICLK source is the X port (refer to subaddresses 80H and 91H/C1H)
X
X
1
Scaler is in operational mode
X
0
X
Scaler is in power-down mode; scaler in power-down stops I port output
yc
SLM3
1
X
0
X
X
Audio clock generation in power-down and output disabled
1
X
X
Note
w.
X
Audio clock generation active
ww
1. X = don’t care.
2004 Jul 22
147
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.7.4
SAA7118
SUBADDRESS 8FH
Table 108 Status information scaler part; 8FH[7:0]; read only register
I2C-BUS
STATUS BIT
FUNCTION(1)
D7
XTRI
status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use
D6
ITRI
status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use
D5
FFIL
status of the internal ‘FIFO almost filled’ flag
co
D4
FFOV
D3
PRDON
copy of bit DPROG, can be used to detect power-up and start-up fails
D2
ERROF
error flag of scalers output formatter, normally set, if the output processing needs to be
interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all
internal FIFO capacity used
D1
FIDSCI
status of the field sequence ID at the scalers input
D0
FIDSCO
status of the field sequence ID at the scalers output, scaler processing dependent
z.
status of the internal ‘FIFO overflow’ flag
m
BIT
Note
15.7.5
SUBADDRESSES 90H AND C0H
-d
1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read.
Table 109 Task handling control; register set A [90H[7:6]] and B [C0H[7:6]]; note 1
CONTROL BITS D7 AND D6
EVENT HANDLER CONTROL
OFIDC
X
0
Output field ID is task status flag, which changes every time a selected task
is activated (not synchronized to input field ID)
X
1
Scaler SAV/EAV byte bit D7 and task flag = 1, default
0
X
Scaler SAV/EAV byte bit D7 and task flag = 0
1
X
yc
Output field ID is field ID from scaler input
CONLH
w.
Note
1. X = don’t care.
Table 110 Task handling control; register set A [90H[5:3]] and B [C0H[5:3]]
CONTROL BITS D5 TO D3
EVENT HANDLER CONTROL
ww
Active task is carried out directly
FSKP2
FSKP1
FSKP0
0
0
0
1 field is skipped before active task is carried out
0
0
1
... fields are skipped before active task is carried out
...
...
...
6 fields are skipped before active task is carried out
1
1
0
7 fields are skipped before active task is carried out
1
1
1
2004 Jul 22
148
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 111 Task handling control; register set A [90H[2:0]] and B [C0H[2:0]]; note 1
CONTROL BITS D2 TO D0
EVENT HANDLER CONTROL
Event handler triggers immediately after finishing a task
Event handler triggers with field ID = 0
Event handler triggers with field ID = 1
If active task is finished, handling is taken over by the next task
Active task is repeated once, before handling is taken over by the next task
X
0
0
0
1
X
1
0
X
1
1
0
X
X
1
X
X
z.
Note
1. X = don’t care.
SUBADDRESSES 91H TO 93H
STRC0
X
co
Event handler triggers with next V-sync
15.7.6
STRC1
m
RPTSK
Table 112 X port formats and configuration; register set A [91H[7:3]] and B [C1H[7:3]]; note 1
SCALER INPUT FORMAT AND CONFIGURATION SOURCE
SELECTION
CONTROL BITS D7 TO D3
HLDFV
Only if XRQT[83H[2]] = 1: scaler input source reacts on
SAA7118 request
X
X
X
X
0
Scaler input source is a continuous data stream, which cannot
be interrupted (must be logic 1, if SAA7118 decoder part is
source of scaler or XRQT[83H[2]] = 0)
X
X
X
X
1
Scaler input source is data from decoder, data type is
provided according to Table 15
X
X
0
0
X
yc
-d
CONLV
SCSRC1 SCSRC0
SCRQE
X
X
0
1
X
X
X
1
0
X
Scaler input source is raw digital CVBS (or 16-bit Y + CB-CR, if
no 16-bit outputs are active) from X port
X
X
1
1
X
SAV/EAV code bits D6 and D5 (F and V) may change
between SAV and EAV
X
0
X
X
X
SAV/EAV code bits D6 and D5 (F and V) are synchronized to
scalers output line start
X
1
X
X
X
SAV/EAV code bit D5 (V) and V gate on pin IGPV as
generated by the internal processing; see Fig.43
0
X
X
X
X
SAV/EAV code bit D5 (V) and V gate are inverted
1
X
X
X
X
ww
w.
Scaler input source is Y-CB-CR data from X port
Scaler input source is raw digital CVBS from selected analog
channel, for backward compatibility only, further use is not
recommended
Note
1. X = don’t care.
2004 Jul 22
149
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 113 X port formats and configuration; register set A [91H[2:0]] and B [C1H[2:0]]; note 1
CONTROL BITS D2 TO D0
SCALER INPUT FORMAT AND CONFIGURATION FORMAT
CONTROL
FSC1(2)
Input is Y-CB-CR 4 : 2 : 2 like sampling scheme
X
X
0
Input is Y-CB-CR 4 : 1 : 1 like sampling scheme
X
X
1
FSC0
0
0
X
0
1
X
1
0
X
1
1
X
co
m
FSC2(2)
Chroma is provided every line, default
Chroma is provided every 2nd line
Chroma is provided every 3rd line
Chroma is provided every 4th line
z.
Notes
1. X = don’t care.
2. FSC2 and FSC1 only to be used, if X port input source does not provide chroma information for every input line.
X port input stream must contain dummy chroma bytes.
Table 114 X port input reference signal definitions; register set A [92H[7:4]] and B [C2H[7:4]]; note 1
CONTROL BITS D7 TO D4
-d
X PORT INPUT REFERENCE SIGNAL DEFINITIONS
XFDH
XDV1
XDV0
Rising edge of XRV input and decoder V123 is vertical reference
X
X
X
0
Falling edge of XRV input and decoder V123 is vertical reference
X
X
X
1
XRV is a V-sync or V gate signal
X
X
0
X
XRV is a frame sync, V pulses are generated internally on both edges of
FS input
X
X
1
X
X port field ID is state of XRH at reference edge on XRV (defined by
XFDV)
X
0
X
X
Field ID (decoder and X port field ID) is inverted
X
1
X
X
Reference edge for field detection is falling edge of XRV
0
X
X
X
Reference edge for field detection is rising edge of XRV
1
X
X
X
Note
w.
yc
XFDV
ww
1. X = don’t care.
2004 Jul 22
150
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 115 X port input reference signal definitions; register set A [92H[3:0]] and B [C2H[3:0]]; note 1
CONTROL BITS D3 TO D0
X PORT INPUT REFERENCE SIGNAL DEFINITIONS
X
Data rate is defined by XCLK only, no XDQ signal used
X
Data are qualified at XDQ input at logic 1
Data are qualified at XDQ input at logic 0
Rising edge of XRH input is horizontal reference
Falling edge of XRH input is horizontal reference
Note
1. X = don’t care.
XCKS
X
X
0
X
X
1
X
X
0
X
X
X
1
X
X
0
X
X
X
1
X
X
0
X
X
X
1
X
X
X
z.
Reference signals are taken from XRH and XRV
Reference signals are decoded from EAV and SAV
XDQ
co
XCLK input clock and XDQ input qualifier are needed
XDH
m
XCODE
Table 116 I port output format and configuration; register set A [93H[7:5]] and B [C3H[7:5]]; note 1
CONTROL BITS D7 TO D5
-d
I PORT OUTPUT FORMATS AND CONFIGURATION
I8_16
FYSK
X
X
0
Skip the number of leading Y only lines, as defined by FOI1 and FOI0
X
X
1
Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0
X
0
X
Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits
ISWP1 and ISWP0
X
1
X
No ITU 656 like SAV/EAV codes are available
0
X
X
ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a
qualifier
1
X
X
Note
ww
w.
1. X = don’t care.
yc
All lines will be output
ICODE
2004 Jul 22
151
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 117 I port output format and configuration; register set A [93H[4:0]] and B [C3H[4:0]]; note 1
CONTROL BITS D4 TO D0
I PORT OUTPUT FORMATS AND CONFIGURATION
4 : 2 : 2 Dword formatting
X
X
4 : 1 : 1 Dword formatting
X
X
4 : 2 : 0, only every 2nd line Y + CB-CR output, in between
Y only output
X
4 : 1 : 0, only every 4th line Y + CB-CR output, in between
Y only output
X
Y only
X
Not defined
X
FSI1
FSI0
0
0
0
0
0
1
X
0
1
0
X
0
1
1
X
1
0
0
X
1
0
1
z.
Not defined
FSI2
m
FOI0
co
FOI1
X
X
1
1
0
X
X
1
1
1
No leading Y only line, before 1st Y + CB-CR line is output
0
0
X
X
X
1 leading Y only line, before 1st Y + CB-CR line is output
0
1
X
X
X
2 leading Y only lines, before 1st Y + CB-CR line is output
1
0
X
X
X
3 leading Y only lines, before 1st Y + CB-CR line is output
1
1
X
X
X
Note
1. X = don’t care.
15.7.7
SUBADDRESSES 94H TO 9BH
-d
Not defined
yc
Table 118 Horizontal input window start; register set A [94H[7:0]; 95H[3:0]] and B [C4H[7:0]; C5H[3:0]]
HORIZONTAL INPUT
ACQUISITION WINDOW
DEFINITION OFFSET IN
X (HORIZONTAL) DIRECTION(1)
A [95H[3:0]]
B [C5H[3:0]]
A [94H[7:0]]
B [C4H[7:0]]
XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0
0
0
0
0
0
0
0
0
0
0
1
0
Odd offsets are changing the CB-CR
sequence in the output stream to
CR-CB sequence
0
0
0
0
0
0
0
0
0
0
1
1
Maximum possible pixel
offset = 4095
1
1
1
1
1
1
1
1
1
1
1
1
ww
w.
A minimum of ‘2’ should be kept, due
to a line counting mismatch
Note
1. Reference for counting are luminance samples.
2004 Jul 22
CONTROL BITS
152
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 119 Horizontal input window length; register set A [96H[7:0]; 97H[3:0]] and B [C6H[7:0]; C7H[3:0]]
CONTROL BITS
A [96H[7:0]]
B [C6H[7:0]]
m
A [97H[3:0]]
B [C7H[3:0]]
XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0
co
HORIZONTAL INPUT
ACQUISITION WINDOW
DEFINITION INPUT WINDOW
LENGTH IN X (HORIZONTAL)
DIRECTION(1)
0
0
0
0
0
0
0
0
0
0
0
0
Odd lengths are allowed, but will be
rounded up to even lengths
0
0
0
0
0
0
0
0
0
0
0
1
Maximum possible number of input
pixels = 4095
1
1
1
1
1
1
1
1
1
1
1
1
Note
1. Reference for counting are luminance samples.
z.
No output
Table 120 Vertical input window start; register set A [98H[7:0]; 99H[3:0]] and B [C8H[7:0]; C9H[3:0]]
CONTROL BITS
VERTICAL INPUT ACQUISITION
WINDOW DEFINITION OFFSET IN
Y (VERTICAL) DIRECTION(1)
-d
A [99H[3:0]]
B [C9H[3:0]]
A [98H[7:0]]
B [C8H[7:0]]
YO11 YO10 YO9 YO8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0
Line offset = 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Maximum line offset = 4095
1
1
1
1
1
1
1
1
1
1
1
1
Note
yc
Line offset = 1
1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field
dropping. Other trigger conditions: YO > (number of input lines per field − 2), will result in field dropping.
Table 121 Vertical input window length; register set A [9AH[7:0]; 9BH[3:0]] and B [CAH[7:0]; CBH[3:0]]
No input lines
ww
1 input line
w.
VERTICAL INPUT ACQUISITION
WINDOW DEFINITION INPUT
WINDOW LENGTH IN
Y (VERTICAL) DIRECTION(1)
Maximum possible number of input
lines = 4095
CONTROL BITS
A [9BH[3:0]]
B [CBH[3:0]]
YS11 YS10
YS9
A [9AH[7:0]]
B [CAH[7:0]]
YS8 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Note
1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field
dropping. Other trigger conditions: YS > (number of input lines per field − 2), will result in field dropping.
2004 Jul 22
153
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
15.7.8
SAA7118
SUBADDRESSES 9CH TO 9FH
Table 122 Horizontal output window length; register set A [9CH[7:0]; 9DH[3:0]] and B [CCH[7:0]; CDH[3:0]]
m
CONTROL BITS
A [9DH[3:0]]
B [CDH[3:0]]
A [9CH[7:0]]
B [CCH[7:0]]
co
HORIZONTAL OUTPUT
ACQUISITION WINDOW
DEFINITION NUMBER OF
DESIRED OUTPUT PIXELS IN
X (HORIZONTAL) DIRECTION(1)
XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
0
0
0
0
0
0
0
0
0
0
0
0
Odd lengths are allowed, but will be
filled up to even lengths
0
0
0
0
0
0
0
0
0
0
0
1
Maximum possible number of input
pixels = 4095; note 2
1
1
1
1
1
1
1
1
1
1
1
1
Notes
1. Reference for counting are luminance samples.
z.
No output
2. If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated.
VERTICAL OUTPUT ACQUISITION
WINDOW DEFINITION NUMBER
OF DESIRED OUTPUT LINES IN
Y (VERTICAL) DIRECTION
CONTROL BITS
A [9FH[3:0]]
B [CFH[3:0]]
0
1 pixel
Maximum possible number of output
lines = 4095; note 1
Note
A [9EH[7:0]]
B [CEH[7:0]]
YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0
0
0
yc
No output
-d
Table 123 Vertical output window length; register set A [9EH[7:0]; 9FH[3:0]] and B [CEH[7:0]; CFH[3:0]]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
15.7.9
w.
1. If the desired output length is greater than the number of scaled output lines, the processing is cut.
SUBADDRESSES A0H TO A2H
Table 124 Horizontal prescaling; register set A [A0H[5:0]] and B [D0H[5:0]]
CONTROL BITS D5 TO D0
HORIZONTAL INTEGER PRESCALING RATIO (XPSC)
0
ww
Not allowed
XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0
0
0
0
0
0
Downscale = 1
0
0
0
0
0
1
Downscale = 1⁄2
0
0
0
0
1
0
...
...
...
...
...
...
...
1
1
1
1
1
1
Downscale =
2004 Jul 22
1⁄
63
154
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 125 Accumulation length; register set A [A1H[5:0]] and B [D1H[5:0]]
CONTROL BITS D5 TO D0
HORIZONTAL PRESCALER ACCUMULATION
SEQUENCE LENGTH (XACL)
0
0
0
0
...
...
Accumulation length = 64
1
0
0
0
0
0
0
0
1
co
Accumulation length = 1
Accumulation length = 2
m
XACL5 XACL4 XACL3 XACL2 XACL1 XACL0
...
...
...
...
...
1
1
1
1
1
Table 126 Prescaler DC gain and FIR prefilter control; register set A [A2H[7:4]] and B [D2H[7:4]]; note 1
CONTROL BITS D7 TO D4
FIR PREFILTER CONTROL
z.
PFUV1 PFUV0
Luminance FIR filter bypassed
H_y(z) =
H_y(z) =
H_y(z) =
1⁄
4
1⁄
8
1⁄
8
(1 2 1)
(−1 1 1.75 4.5 1.75 1 −1)
(1 2 2 2 1)
H_uv(z) =
1⁄
4
-d
Chrominance FIR filter bypassed
(1 2 1)
H_uv(z) = 1⁄32 (3 8 10 8 3)
H_uv(z) = 1⁄8 (1 2 2 2 1)
Note
yc
1. X = don’t care.
PFY1
PFY0
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
Table 127 Prescaler DC gain and FIR prefilter control; register set A [A2H[3:0]] and B [D2H[3:0]]; note 1
CONTROL BITS D3 TO D0
PRESCALER DC GAIN
XC2_1
XDCG2
XDCG1
XDCG0
X
0
0
0
2
X
0
0
1
Prescaler output is renormalized by gain factor = 1⁄4
X
0
1
0
Prescaler output is renormalized by gain factor = 1
w.
Prescaler output is renormalized by gain factor =
1⁄
8
X
0
1
1
Prescaler output is renormalized by gain factor =
1⁄
16
X
1
0
0
Prescaler output is renormalized by gain factor =
1⁄
32
X
1
0
1
Prescaler output is renormalized by gain factor = 1⁄64
X
1
1
0
ww
Prescaler output is renormalized by gain factor =
1⁄
X
1
1
1
Weighting of all accumulated samples is factor ‘1’;
e.g. XACL = 4 ⇒ sequence 1 + 1 + 1 + 1 + 1
0
X
X
X
Weighting of samples inside sequence is factor ‘2’;
e.g. XACL = 4 ⇒ sequence 1 + 2 + 2 + 2 + 1
1
X
X
X
Prescaler output is renormalized by gain factor =
1⁄
128
Note
1. X = don’t care.
2004 Jul 22
155
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
15.7.10 SUBADDRESSES A4H TO A6H
Table 128 Luminance brightness control; register set A [A4H[7:0]] and B [D4H[7:0]]
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
Value = 0
0
0
0
0
0
0
0
0
Nominal value = 128
1
0
0
0
0
0
0
0
Value = 255
1
1
1
1
1
1
1
1
co
BRIG7
m
CONTROL BITS D7 TO D0
LUMINANCE
BRIGHTNESS CONTROL
Table 129 Luminance contrast control; register set A [A5H[7:0]] and B [D5H[7:0]]
CONTROL BITS D7 TO D0
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
SATN2
SATN1
SATN0
Gain = 0
Gain =
1⁄
0
0
0
1
127⁄
0
1
64
-d
64
Nominal gain = 64
Gain =
z.
LUMINANCE CONTRAST
CONTROL
Table 130 Chrominance saturation control; register set A [A6H[7:0]] and B [D6H[7:0]]
CONTROL BITS D7 TO D0
CHROMINANCE
SATURATION CONTROL
SATN7
0
Gain = 1⁄64
0
Nominal gain = 64
Gain =
127⁄
64
SATN5
SATN4
SATN3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
yc
Gain = 0
SATN6
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
15.7.11 SUBADDRESSES A8H TO AEH
w.
Table 131 Horizontal luminance scaling increment; register set A [A8H[7:0]; A9H[7:0]] and B [D8H[7:0]; D9H[7:0]]
HORIZONTAL LUMINANCE
SCALING INCREMENT
CONTROL BITS
A [A9H[7:4]]
B [D9H[7:4]]
A [A9H[3:0]]
B [D9H[3:0]]
A [A8H[7:4]]
B [D8H[7:4]]
A [A8H[3:0]]
B [D8H[3:0]]
XSCY[15:12](1)
XSCY[11:8]
XSCY[7:4]
XSCY[3:0]
0000
0000
0000
0000
0000
0001
0010
0110
Scale = 1024⁄1023 zoom
0000
0011
1111
1111
Scale = 1, equals 1024
0000
0100
0000
0000
downscale
0000
0100
0000
0001
downscale
0001
1111
1111
1111
Scale =
1024⁄ (theoretical) zoom
1
1024⁄
294, lower limit defined
ww
Scale =
data path structure
Scale =
Scale =
1024⁄
1025
1024⁄
8191
by
Note
1. Bits XSCY[15:13] are reserved and are set to logic 0.
2004 Jul 22
156
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 132 Horizontal luminance phase offset; register set A [AAH[7:0]] and B [DAH[7:0]]
CONTROL BITS D7 TO D0
XPHY7
XPHY6
XPHY5
XPHY4
XPHY3
XPHY2
XPHY1
m
HORIZONTAL LUMINANCE PHASE
OFFSET
XPHY0
0
0
0
0
0
0
0
0
Offset = 1⁄32 pixel
0
0
0
0
0
0
0
1
Offset = 32⁄32 = 1 pixel
0
0
1
255⁄
32
1
1
1
Offset =
pixel
co
Offset = 0
0
0
0
0
0
1
1
1
1
1
Table 133 Horizontal chrominance scaling increment; register set A [ACH[7:0]; ADH[7:0]] and B [DCH[7:0]; DDH[7:0]]
CONTROL BITS
A [ADH[7:4]]
B [DDH[7:4]]
A [ADH[3:0]]
B [DDH[3:0]]
A [ACH[7:4]]
B [DCH[7:4]]
A [ACH[3:0]]
B [DCH[3:0]]
XSCC[15:12](1)
XSCC[11:8]
XSCC[7:4]
XSCC[3:0]
0000
0000
0000
0000
0000
0000
0001
1111
1111
1111
This value must be set to the
luminance value 1⁄2XSCY[15:0]
z.
HORIZONTAL CHROMINANCE
SCALING INCREMENT
0000
Note
-d
0001
1. Bits XSCC[15:13] are reserved and are set to logic 0.
Table 134 Horizontal chrominance phase offset; register set A [AEH[7:0]] and B [DEH[7:0]]
This value must be set to
CONTROL BITS D7 TO D0
yc
HORIZONTAL CHROMINANCE
PHASE OFFSET
1⁄ XPHY[7:0]
2
XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
w.
15.7.12 SUBADDRESSES B0H TO BFH
Table 135 Vertical luminance scaling increment; register set A [B0H[7:0]; B1H[7:0]] and B [E0H[7:0]; E1H[7:0]]
ww
VERTICAL LUMINANCE SCALING
INCREMENT
Scale =
Scale =
1024⁄ (theoretical)
1
1024⁄
1023 zoom
zoom
Scale = 1, equals 1024
Scale =
Scale =
1024⁄
1025 downscale
1⁄
63.999 downscale
2004 Jul 22
CONTROL BITS
A [B1H[7:4]]
B [E1H[7:4]]
A [B1H[3:0]]
B [E1H[3:0]]
A [B0H[7:4]]
B [E0H[7:4]]
A [B0H[3:0]]
B [E0H[3:0]]
YSCY[15:12]
YSCY[11:8]
YSCY[7:4]
YSCY[3:0]
0000
0000
0000
0001
0000
0011
1111
1111
0000
0100
0000
0000
0000
0100
0000
0001
1111
1111
1111
1111
157
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 136 Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]]
CONTROL BITS
A [B3H[3:0]]
B [E3H[3:0]]
A [B2H[7:4]]
B [E2H[7:4]]
A [B2H[3:0]]
B [E2H[3:0]]
YSCC[15:12]
YSCC[11:8]
YSCC[7:4]
YSCC[3:0]
0000
0000
0000
0001
1111
1111
1111
1111
This value must be set to the
luminance value YSCY[15:0]
m
A [B3H[7:4]]
B [E3H[7:4]]
co
VERTICAL CHROMINANCE
SCALING INCREMENT
Table 137 Vertical scaling mode control; register set A [B4H[4 and 0]] and B [E4H[4 and 0]]; note 1
CONTROL BITS D4 AND D0
VERTICAL SCALING MODE CONTROL
YMODE
Vertical scaling performs linear interpolation between lines
X
0
Vertical scaling performs higher order accumulating interpolation, better alias
suppression
X
1
z.
YMIR
No mirroring
Note
1. X = don’t care.
0
X
1
X
-d
Lines are mirrored
Table 138 Vertical chrominance phase offset ‘00’; register set A [B8H[7:0]] and B [E8H[7:0]]
Offset = 0
Offset =
Offset =
32⁄
32 = 1 line
255⁄ lines
32
CONTROL BITS D7 TO D0
yc
VERTICAL CHROMINANCE PHASE
OFFSET
YPC07
YPC06
YPC05
YPC04
YPC03
YPC02
YPC01
YPC00
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
w.
Table 139 Vertical luminance phase offset ‘00’; register set A [BCH[7:0]] and B [ECH[7:0]]
VERTICAL LUMINANCE PHASE
OFFSET
Offset = 0
Offset =
32 = 1 line
255⁄ lines
32
YPY07
YPY06
YPY05
YPY04
YPY03
YPY02
YPY01
YPY00
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
ww
Offset =
32⁄
CONTROL BITS D7 TO D0
2004 Jul 22
158
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
16 PROGRAMMING START SET-UP
Decoder part
The given values force the following behaviour of the SAA7118 decoder part:
m
16.1
• Automatic field detection enabled
• Standard ITU 656 output format enabled on expansion (X) port
co
• The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias
filter and AGC active
• Contrast, brightness and saturation control in accordance with ITU standards
• Adaptive comb filter for luminance and chrominance activated
z.
• Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state.
Table 140 Decoder part start set-up values for the three main standards
SUB
ADDRESS
(HEX)
REGISTER
FUNCTION
BIT
VALUES (HEX)
NAME(1)
NTSC M
PAL B, D,
G, H AND I
SECAM
chip version
ID7 to ID4
01
increment delay
X, WPOFF, GUDL1, GUDL0 and
IDEL3 to IDEL0
47
47
47
02
analog input control 1
FUSE1, FUSE0 and MODE5 to MODE0
C0
C0
C0
03
analog input control 2
X, HLNRS, VBSL, CPOFF, HOLDG,
GAFIX, GAI28 and GAI18
10
10
10
04
analog input control 3
GAI17 to GAI10
90
90
90
05
analog input control 4
GAI27 to GAI20
90
90
90
06
horizontal sync start
HSB7 to HSB0
EB
EB
EB
07
horizontal sync stop
HSS7 to HSS0
E0
E0
E0
08
sync control
AUFD, FSEL, FOET, HTC1, HTC0,
HPLL, VNOI1 and VNOI0
98
98
98
09
luminance control
BYPS, YCOMB, LDEL, LUBW and
LUFI3 to LUFI0
40
40
1B
0A
luminance brightness
control
DBRI7 to DBRI0
80
80
80
0B
luminance contrast
control
DCON7 to DCON0
44
44
44
0C
chrominance saturation
control
DSAT7 to DSAT0
40
40
40
0D
chrominance hue control
HUEC7 to HUEC0
00
00
00
0E
chrominance control 1
CDTO, CSTD2 to CSTD0, DCVF, FCTC,
AUTO0 and CCOMB
89
81
D0
0F
chrominance gain control
ACGC and CGAIN6 to CGAIN0
2A
2A
80
10
chrominance control 2
OFFU1, OFFU0, OFFV1, OFFV0,
CHBW and LCBW2 to LCBW0
0E
06
00
11
mode/delay control
COLO, RTP1, HDEL1, HDEL0, RTP0
and YDEL2 to YDEL0
00
00
00
yc
w.
ww
2004 Jul 22
-d
00
159
read only
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
VALUES (HEX)
REGISTER
FUNCTION
BIT
NAME(1)
NTSC M
PAL B, D,
G, H AND I
SECAM
00
00
00
00
00
00
m
SUB
ADDRESS
(HEX)
SAA7118
RT signal control
RTSE13 to RTSE10 and
RTSE03 to RTSE00
13
RT/X port output control
RTCE, XRHS, XRVS1, XRVS0, HLSEL
and OFTS2 to OFTS0
14
analog/ADC/compatibility
control
CM99, UPTCV, AOSL1, AOSL0,
XTOUTE, AUTO1, APCK1 and APCK0
00
00
00
15
VGATE start, FID change
VSTA7 to VSTA0
11
11
11
16
VGATE stop
VSTO7 to VSTO0
FE
FE
FE
17
miscellaneous, VGATE
configuration and MSBs
LLCE, LLC2E, LATY2 to LATY0, VGPS,
VSTO8 and VSTA8
C0
C0
C0
18
raw data gain control
RAWG7 to RAWG0
40
40
40
19
raw data offset control
RAWO7 to RAWO0
80
80
80
00
00
00
z.
reserved
X, X, X, X, X, X, X, X
1E
status byte 1 video
decoder
−, HLCK, SLTCA, GLIMT, GLIMB, WIPA,
DCSTD1 and DCSTD0
read only
1F
status byte 2 video
decoder
INTL, HLVLN, FIDT, −, TYPE3,
COLSTR, COPRO and RDCAP
read only
Note
ww
w.
yc
1. All X values must be set to logic 0.
-d
1A to 1D
co
12
2004 Jul 22
160
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
16.2
SAA7118
Component video part and interrupt mask
The given values force the following behaviour of the SAA7118 component video part:
m
• The analog inputs AI11, AI21, AI31 and AI41 expect an RGBS signal; analog anti-alias filters and AGC for the sync
channel active
co
• For other settings see decoder part (Section 16.1).
Table 141 Component video part and interrupt mask start set-up values
SUB
ADDRESS
(HEX)
REGISTER
FUNCTION
BIT NAME(1)
VALUES
(HEX)
analog input control 5
AOSL2, ADPE, EXCLK, REFA, X, EXMCE,
GAI48 and GAI38
00
24
analog input control 6
GAI37 to GAI30
90
25
analog input control 7
GAI47 to GAI40
90
reserved
X, X, X, X, X, X, X, X
00
29
component delay
FSWE, FSWI, FSWDL1, FSWDL0, CMFI,
CPDL2 to CPDL0
40
2A
component brightness control
CBRI7 to CBRI0
80
2B
component contrast control
CCON7 to CCON0
40
2C
component saturation control
CSAT7 to CSAT0
47
2D
interrupt mask 1
X, X, X, MVPSV, MPPV, MCCV, X and MERROF
00
2E
interrupt mask 2
X, MHLCK, X, X, X, X, MDCSTD1 and MDCSTD0
00
2F
interrupt mask 3
MINTL, MHLVLN, MFIDT, X, MTYPE3, MCOLSTR,
MCOPRO and MRDCAP
00
Note
-d
yc
26 to 28
z.
23
ww
w.
1. All X values must be set to logic 0.
2004 Jul 22
161
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
16.3
SAA7118
Audio clock generation part
The given values force the following behaviour of the SAA7118 audio clock generation part:
m
• Used crystal is 24.576 MHz
• Expected field frequency is 59.94 Hz (e.g. NTSC M standard)
• Generated audio master clock frequency at pin AMCLK is 256 × 44.1 kHz = 11.2896 MHz
co
• AMCLK is externally connected to AMXCLK [short-cut between pins P11 (72) and M12 (76)]
• ASCLK = 32 × 44.1 kHz = 1.4112 MHz
• ALRCLK is 44.1 kHz.
Table 142 Audio clock part set-up values
z.
START VALUES
BIT NAME(1)
REGISTER FUNCTION
7
6
5
4
3
2
1
0
HEX
audio master clock cycles per
field; bits D7 to D0
ACPF7 to ACPF0
1
0
1
1
1
1
0
0
BC
31
audio master clock cycles per
field; bits D15 to D8
ACPF15 to ACPF8
1
1
0
1
1
1
1
1
DF
32
audio master clock cycles per
field; bits D17 and D16
X, X, X, X, X, X, ACPF17
and ACPF16
0
0
0
0
0
0
1
0
02
33
reserved
X, X, X, X, X, X, X, X
0
0
0
0
0
0
0
0
00
34
audio master clock nominal
increment; bits D7 to D0
ACNI7 to ACNI0
1
1
0
0
1
1
0
1
CD
35
audio master clock nominal
increment; bits D15 to D8
ACNI15 to ACNI8
1
1
0
0
1
1
0
0
CC
36
audio master clock nominal
increment; bits D21 to D16
X, X, ACNI21 to ACNI16
0
0
1
1
1
0
1
0
3A
37
reserved
X, X, X, X, X, X, X, X
0
0
0
0
0
0
0
0
00
38
clock ratio AMXCLK to ASCLK
X, X, SDIV5 to SDIV0
0
0
0
0
0
0
1
1
03
39
clock ratio ASCLK to ALRCLK
X, X, LRDIV5 to LRDIV0
0
0
0
1
0
0
0
0
10
3A
audio clock generator basic
set-up
X, X, X, X, APLL, AMVR, LRPH,
SCPH
0
0
0
0
0
0
0
0
00
reserved
X, X, X, X, X, X, X, X
0
0
0
0
0
0
0
0
00
Note
w.
3B to 3F
yc
30
-d
SUB
ADDRESS
(HEX)
ww
1. All X values must be set to logic 0.
2004 Jul 22
162
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
16.4
SAA7118
Data slicer and data type control part
The given values force the following behaviour of the SAA7118 VBI data slicer part:
m
• Closed captioning data are expected at line 21 of field 1 (60 Hz/525 line system)
• All other lines are processed as active video
Table 143 Data slicer start set-up values
SUB
ADDRESS
(HEX)
START VALUES
BIT NAME(1)
REGISTER FUNCTION
7
6
5
4
3
2
1
0
HEX
1
0
0
0
0
0
0
40
X, HAM_N, FCE, HUNT_N, X, X, X,
X
0
line control register 2 to 20
LCRn_7 to LCRn_0 (n = 2 to 20)
1
1
1
1
1
1
1
1
FF
line control register 21
LCR21_7 to LCR21_0
0
1
0
1
1
1
1
1
5F
55 to 57
line control register 22 to 24
LCRn_7 to LCRn_0 (n = 22 to 24)
1
1
1
1
1
1
1
1
FF
58
programmable framing code
FC7 to FC0
0
0
0
0
0
0
0
0
00
59
horizontal offset for slicer
HOFF7 to HOFF0
0
1
0
0
0
1
1
1
47
5A
vertical offset for slicer
VOFF7 to VOFF0
0
0
0
0
0
1
1
0
06(2)
5B
field offset and MSBs for
horizontal and vertical offset
FOFF, RECODE, X, VOFF8, X,
HOFF10 to HOFF8
1
0
0
0
0
0
1
1
83(2)
5C
reserved
X, X, X, X, X, X, X, X
0
0
0
0
0
0
0
0
00
5D
header and data
identification code control
FVREF, X, DID5 to DID0
0
0
1
1
1
1
1
0
3E
5E
sliced data identification code X, X, SDID5 to SDID0
0
0
0
0
0
0
0
0
00
5F
reserved
0
0
0
0
0
0
0
0
00
60
slicer status byte 0
61
slicer status byte 1
−, −, F21_N, LN8 to LN4
read-only register
62
slicer status byte 2
LN3 to LN0, DT3 to DT0
read-only register
Notes
-d
54
yc
41 to 53
z.
slicer control 1
X, X, X, X, X, X, X, X
−, FC8V, FC7V, VPSV, PPV, CCV,
−, −
w.
40
co
• Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH ⇒ MSB of SAV/EAV = 1).
read-only register
1. All X values must be set to logic 0.
ww
2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H.
2004 Jul 22
163
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
Scaler and interfaces
increment calculations are done with 288, respectively
240 lines.
Table 144 shows some examples for the scaler
programming with:
16.5.1
• prsc = prescale ratio
TRIGGER CONDITION
m
16.5
SAA7118
For trigger condition STRC[1:0] 90H[1:0] not equal to ‘00’.
• vsc = vertical scale ratio.
If the value of (YO + YS) is greater than or equal to 262
(NTSC), respectively 312 (PAL) the output field rate is
reduced to 30 Hz, respectively 25 Hz.
co
• fisc = fine scale ratio
number of input pixel
The ratio is defined as: ----------------------------------------------------------number of output pixel
Horizontal and vertical offsets (XO and YO) have to be
used to adjust the displayed video in the display window.
As this adjustment is application dependent, the listed
values are only dummy values.
z.
In the following settings the VBI data slicer is inactive.
To activate the VBI data slicer, VITX[1:0] 86H[7:6] has to
be set to ‘11’. Depending on the VBI data slicer settings,
the sliced VBI data is inserted after the end of the scaled
video lines, if the regions of VBI data slicer and scaler
overlaps.
16.5.2
The maximum zoom factor is dependent on the back-end
data rate and therefore back-end clock and data format
dependent (8 or 16-bit output). The maximum horizontal
zoom is limited to approximately 3.5, due to internal data
path restrictions.
EXAMPLES
Table 144 Example of configurations
SCALER SOURCE AND REFERENCE EVENTS
yc
EXAMPLE
NUMBER
-d
To compensate the running-in of the vertical scaler, the
vertical input window lengths are extended by
2 to 290 lines, respectively 242 lines for XS, but the scaler
16.5.3
MAXIMUM ZOOM FACTOR
INPUT
OUTPUT
WINDOW WINDOW
SCALE
RATIOS
720 × 240 720 × 240 prsc = 1;
fisc = 1;
vsc = 1
analog input to 8-bit I port output, with SAV/EAV codes, 8-bit
serial byte stream decoder output at X port; acquisition trigger
at falling edge vertical and rising edge horizontal reference
signal; H and V gates on IGPH and IGPV, IGP0 = VBI sliced
data flag, IGP1 = FIFO almost full, level ≥24, IDQ qualifier
logic 1 active
2
analog input to 16-bit output, without SAV/EAV codes, Y on
704 × 288 768 × 288 prsc = 1;
I port, CB-CR on H port and decoder output at X port;
fisc = 0.91667;
acquisition trigger at falling edge vertical and rising edge
vsc = 1
horizontal reference signal; H and V-pulses on IGPH and IGPV,
output FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0
active
3
X port input 8-bit with SAV/EAV codes, no reference signals on
XRH and XRV, XCLK as gated clock; field detection and
acquisition trigger on different events; acquisition triggers at
rising edge vertical and rising edge horizontal; I port output
8-bit with SAV/EAV codes like example number 1
720 × 240 352 × 288 prsc = 2;
fisc = 1.022;
vsc = 0.8333
X port and H port for 16-bit Y-CB-CR 4 : 2 : 2 input (if no 16-bit
output selected); XRH and XRV as references; field detection
and acquisition trigger at falling edge vertical and rising edge
horizontal; I port output 8-bit with SAV/EAV codes, but Y only
output
720 × 288 200 × 80
ww
w.
1
4
2004 Jul 22
164
prsc = 2;
fisc = 1.8;
vsc = 3.6
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 145 Scaler and interface configuration example
I2C-BUS
ADDRESS
(HEX)
m
EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4
MAIN FUNCTIONALITY
HEX
DEC
HEX
DEC
HEX
DEC
HEX
DEC
−
10
−
10
−
Global settings
task enable, IDQ and back-end clock
definition
10
−
10
83
XCLK output phase and X port output enable
01
−
01
−
00
−
00
−
84
IGPH, IGPV, IGP0 and IGP1 output definition
A0
−
C5
−
A0
−
A0
−
85
signal polarity control and I port byte
swapping
10
−
09
−
10
−
10
−
86
FIFO flag thresholds and video/text
arbitration
45
−
40
−
45
−
45
−
87
ICLK and IDQ output phase and I port enable
01
−
01
−
01
−
01
−
88
power save control and software reset
F0
−
F0
−
F0
−
F0
−
−
00
−
00
−
00
−
z.
co
80
Task A: scaler input configuration and output format settings
task handling
00
91
scaler input source and format definition
08
−
08
−
18
−
38
−
92
reference signal definition at scaler input
10
−
10
−
10
−
10
−
93
I port output formats and configuration
80
−
40
−
80
−
84
−
10
16
10
16
10
16
10
16
Input and output window definition
97
98
99
9A
9B
9C
9D
9E
−
00
−
00
−
00
−
720
C0
704
D0
720
D0
720
02
−
02
−
02
−
02
−
vertical input offset (YO)
0A
10
0A
10
0A
10
0A
10
00
−
00
−
00
−
00
−
vertical input (source) window length (YS)
F2
242
22
290
F2
242
22
290
00
−
01
−
00
−
01
−
horizontal output (destination) window length
(XD)
D0
720
00
768
60
352
C8
200
02
−
03
−
01
−
00
−
vertical output (destination) window length
(YD)
F0
240
20
288
20
288
50
80
00
−
01
−
01
−
00
−
horizontal input (source) window length (XS)
ww
9F
00
D0
yc
95
96
horizontal input offset (XO)
w.
94
-d
90
2004 Jul 22
165
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
I2C-BUS
ADDRESS
(HEX)
SAA7118
EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4
MAIN FUNCTIONALITY
DEC
HEX
Prefiltering and prescaling
integer prescale (value ‘00’ not allowed)
01
−
01
A1
accumulation length for prescaler
00
−
00
A2
FIR prefilter and prescaler DC normalization
00
−
A4
scaler brightness control
80
A5
scaler contrast control
40
A6
scaler saturation control
40
A8
horizontal scaling increment for luminance
A9
00
AA
horizontal phase offset luminance
AC
horizontal scaling increment for chrominance
AE
Vertical scaling
B0
vertical scaling increment for luminance
B1
B3
B4
vertical scaling mode control
vertical phase offsets luminance and
chrominance (need to be used for interlace
correct scaled output)
ww
2004 Jul 22
−
02
−
−
02
−
03
−
00
−
AA
−
F2
−
128
80
128
80
128
80
128
64
40
64
40
64
11
17
64
40
64
40
64
11
17
18
1048
34
1844
1024
AA
938
04
−
03
−
04
−
07
−
−
00
−
00
−
00
−
00
512
D5
469
0C
524
9A
922
−
01
−
02
−
03
−
00
−
00
−
00
−
00
−
00
1024
00
1024
55
853
66
3686
04
−
04
−
03
−
0E
−
00
1024
00
1024
55
853
66
3686
04
−
04
−
03
−
0E
−
00
−
00
−
00
−
01
−
start with B8 to BF at 00H, if there are no problems with
the interlaced scaled output optimize according to
Section 8.4.3.2
w.
B8 to BF
vertical scaling increment for chrominance
yc
B2
DEC
00
02
horizontal phase offset chrominance
HEX
02
-d
AD
DEC
−
z.
Horizontal phase scaling
HEX
co
A0
DEC
m
HEX
166
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
17 PACKAGE OUTLINES
BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm
m
SOT472-1
B
D
co
A
D1
ball A1
index area
A2
A
z.
E1 E
-d
A1
e1
∅v M C A B
b
1/2 e
e
detail X
C
y1 C
y
∅w M C
P
N
M
L
K
J
H
G
F
E
D
C
B
A
yc
e
e2
w.
1/2 e
shape
optional (4x)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0
X
10 mm
5
scale
DIMENSIONS (mm are the original dimensions)
A
max.
mm
1.75
A1
A2
b
D
D1
E
E1
e
e1
e2
v
w
y
y1
0.5
0.3
1.25
1.05
0.6
0.4
15.2
14.8
13.7
13.0
15.2
14.8
13.7
13.0
1
13
13
0.3
0.1
0.15
0.35
ww
UNIT
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT472-1
144E
MS-034
---
2004 Jul 22
167
EUROPEAN
PROJECTION
ISSUE DATE
00-03-04
03-01-22
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
c
y
X
120
121
81
80
m
z.
A
SOT322-2
co
QFP160: plastic quad flat package;
160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
-d
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
Lp
yc
bp
L
pin 1 index
detail X
41
160
1
40
ZD
wM
bp
e
D
v M A
UNIT
w.
B
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
4.07
0.50
0.25
3.6
3.2
0.25
0.38
0.22
0.23
0.13
28.1
27.9
28.1
27.9
0.65
HD
v M B
0
5
10 mm
scale
ww
DIMENSIONS (mm are the original dimensions)
HD
HE
31.45 31.45
30.95 30.95
L
Lp
v
w
y
1.6
1.03
0.73
0.3
0.13
0.1
Z D(1) Z E (1)
1.5
1.1
1.5
1.1
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT322-2
135E12
MS-022
2004 Jul 22
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
168
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
To overcome these problems the double-wave soldering
method was specifically developed.
18 SOLDERING
Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
m
18.1
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
co
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
z.
18.2
SAA7118
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
yc
-d
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending
on solder material applied, SnPb or Pb-free respectively.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
w.
Typical reflow peak temperatures range from
215 °C to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
– for all BGA, HTSSON-T and SSOP-T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
ww
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
18.3
18.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270 °C and 320 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Jul 22
Manual soldering
169
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
18.5
SAA7118
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
not suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
co
m
WAVE
PLCC(5), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
suitable
not suitable(4)
suitable
suitable
suitable
not
recommended(5)(6)
not
recommended(7)
suitable
not suitable
z.
not suitable
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
-d
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
yc
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
w.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
ww
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Jul 22
170
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
19 DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
z.
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
co
Development
DEFINITION
m
LEVEL
Notes
-d
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20 DEFINITIONS
21 DISCLAIMERS
yc
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
w.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
ww
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Jul 22
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
171
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
m
22 PURCHASE OF PHILIPS I2C COMPONENTS
ww
w.
yc
-d
z.
co
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2004 Jul 22
172
z.
co
m
Philips Semiconductors – a worldwide company
Contact information
ww
w.
yc
-d
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected]
SCA76
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R21/05/pp173
Date of release: 2004 Jul 22
Document order number:
9397 750 13497
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