Keysight N6469A eDP Automated Test Application Methods of

Keysight N6469A eDP Automated Test Application Methods of
Keysight N6469A eDP
Automated Test Application
Methods of
Implementation
Notices
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Edition
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2
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Testing—At A Glance
The Keysight N6469A Embedded DisplayPort (eDP) automated test application provides a framework
to use the Keysight Infiniium Digital Storage oscilloscopes to perform compliance testing of eDP
standards on a source transmitter device under test (DUT). The eDP Automated Test Application
enables:
•
Identifying and setting up the DUT,
•
Configuring oscilloscope connections to the DUT,
•
Checking automatically for all connections between the oscilloscope and the DUT,
•
Selecting and configuring individual or multiple tests,
•
Running the configured tests,
•
Evaluating the test results by providing detailed information for each test,
•
Printing HTML report of the tests that have been run.
NOTE
The tests performed by the eDP Automated Test Application provides only a
quick check on the electrical health of the DUT. This testing is not a
replacement for an exhaustive test validation plan.
Compliance test measurements are described in the VESA Embedded DisplayPort (eDP) Standard,
Version 1.4. For more information, see the VESA DisplayPort Standards website at http://www.vesa.org.
Required Equipment and Software
In order to run the eDP Automated Test Application, you require the following equipment and
software:
•
N6469A eDP Automated Test Application software.
•
The minimum version of Keysight Infiniium oscilloscope software (see the N6469A eDP Test
Application release notes).
•
Wilder Technologies eDP-TPA Series Embedded Display Port Test Point Adapter.
•
InifiniiMax Series Probes Amplifier and Head with a minimum bandwidth of 10 GHz each.
•
Precision BNC to SMA male adapter (provided with Keysight Infiniium oscilloscope).
•
50-ohm phase aligned coaxial cable with SMA male connector — 24 inch or less
•
E2655A/B/C probe deskew and performance verification kit.
•
Keyboard, quantity = 1 (provided with the Keysight Infiniium oscilloscope)
•
Mouse, quantity = 1 (provided with Keysight Infiniium oscilloscope)
•
Keysight also recommends using a second monitor to view the automated test application.
Required Licenses
•
N6469A eDP Test Application Software license.
Optional Licenses
•
N5465A InfiniiSim Waveform Transformation Toolset Software License
•
N2809A Precision Probe Oscilloscope Software License
Keysight eDP Compliance Testing Methods of Implementation
3
4
Keysight eDP Compliance Testing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
In This Book
This manual describes, in detail, the Electrical Specification tests that are performed by the eDP
Automated Test Application for signaling on an embedded link between a DisplayPort Source and
DisplayPort Sink device. Broadly, the Electrical Specification tests for the Source device (also called,
Source tests) are categorized into Source Differential Tests and Source Single-Ended Tests.
The chapters in this book are:
•
Chapter 1, “Installing the eDP Automated Test Application” describes how to install and license the
automated test application software (if the software was purchased separately).
•
Chapter 2, “Preparing for Measurements” describes how to start the eDP Automated Test
Application and gives a brief overview of how it is used.
•
Chapter 3, “eDP Test Application—Source Tests” provides an overview to the eDP compliance
testing of the source.
•
Chapter 4, “eDP Automated Source Differential Tests” describes the differential tests for
interoperability verification of eDP sources.
•
Chapter 5, “eDP Automated Source Single-Ended Tests” describes the single-ended tests for
interoperability verification of eDP sources.
•
Chapter 6, “Calibrating the Infiniium Oscilloscope and Probe” describes how to calibrate the
Keysight Infiniium Oscilloscope and Probe prior to performing tests.
See Also
•
The eDP Automated Test Application’s online help, which describes:
• Starting the eDP Automated Test Application
• Creating or Opening a Test Project
• Setting Up the Test Environment
• Enabling the Switch Matrix
• Setting Up the Precision Probe/Cable
• Selecting Tests
• Configuring Tests
• Connecting the Oscilloscope to the DUT
• Running tests
• Automating the Application
• Viewing Results
• Viewing/Exporting/Printing the Report
• Saving Test Projects
• Controlling the Application via a Remote PC
• Using a Second Monitor
2
6
Keysight eDP Compliance Testing Methods of Implementation
Contents
Contents
eDP Automated Testing—At A Glance
Required Equipment and Software
Required Licenses 3
Optional Licenses 3
In This Book
Overview
3
3
5
5
1 Installing the eDP Automated Test Application
Installing the Software
8
Installing the License Key
9
2 Preparing for Measurements
Calibrating the Oscilloscope
12
Required and Recommended Equipment
Required Oscilloscope 13
Required Fixtures and Accessories 13
13
Starting the eDP Automated Test Application
Online Help Topics
16
Setting Up the Transmission Path Test Point
14
18
3 eDP Test Application—Source Tests
Overview
20
4 eDP Automated Source Differential Tests
Eye Diagram Test
22
Test Overview 22
Test Conditions 22
Test Procedure 22
Viewing Test Results
Non ISI Jitter Test
23
25
Test Overview 25
Test Conditions 25
Test Procedure 25
Viewing Test Results 25
Keysight eDP Compliance Testing Methods of Implementation
1
Contents
Total Jitter Test
27
Test Overview 27
Test Conditions 27
Test Procedure 27
Viewing Test Results
27
Deterministic Jitter Test
Test Overview 29
Test Conditions 29
Test Procedure 29
Viewing Test Results
29
29
Random Jitter Test 31
Test Overview 31
Test Conditions 31
Test Procedure 31
Viewing Test Results 31
Peak to Peak Differential Vol tage Test
Test Overview 33
Test Conditions 34
Test Procedure 35
Viewing Test Results 35
Differential Vol tage Level Test
Test Overview 39
Test Conditions 40
Test Procedure 41
Viewing Test Results 41
39
Differential Vol tage Level Ratio Test
Test Overview 44
Test Conditions 46
Test Procedure 46
Viewing Test Results 47
Pre-Emphasis Level Test
Test Overview 50
Test Conditions 52
Test Procedure 52
Viewing Test Results
44
50
53
Pre-Emphasis Level Del ta Test
Test Overview 56
Test Conditions 58
Test Procedure 59
Viewing Test Results 59
2
33
56
Keysight eDP Compliance Testing Methods of Implementation
Contents
Rise/Fall Time Test 65
Test Overview 65
Test Conditions 65
Test Procedure 65
Viewing Test Results 65
Inter Pair Skew Test 68
Test Overview 68
Test Conditions 68
Test Procedure 69
Viewing Test Results 69
Main Link Frequency Compliance Test
Test Overview 70
Test Conditions 70
Test Procedure 70
Viewing Test Results 71
SSC Modulation Frequency Test
Test Overview 73
Test Conditions 73
Test Procedure 73
Viewing Test Results 73
SSC Modulation Deviation Test
Test Overview 75
Test Conditions 75
Test Procedure 75
Viewing Test Results 76
70
73
75
5 eDP Automated Source Single-Ended Tests
Intra Pair Skew Test 78
Test Overview 78
Test Conditions 78
Test Procedure 79
Viewing Test Results
79
AC Common Mode Noise Test 81
Test Overview 81
Test Conditions 81
Test Procedure 81
Viewing Test Results
82
6 Calibrating the Infiniium Oscilloscope and Probe
Required Equipment for Calibration
Keysight eDP Compliance Testing Methods of Implementation
84
3
Contents
Internal Calibration
85
Index
4
Keysight eDP Compliance Testing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
Overview
The Keysight N6469A eDP automated test application for Embedded DisplayPort (eDP) standard
provides a framework to use the Keysight Infiniium digital storage oscilloscopes to perform
compliance testing on an embedded link in the Embedded Display Port Test Point Adapter
(eDP-TPA). The eDP Automated Test Application allows you to:
•
Identify and set up the Device Under Test (DUT).
•
Configure oscilloscope connections to the DUT.
•
Check automatically for all connections between the oscilloscope and the DUT.
•
Select and configure individual or multiple tests.
•
Run the configured tests.
•
Evaluate the test results by providing detailed information for each test.
•
Print HTML report of the tests that have been run.
The eDP Automated Test Application allows you to choose the eDP standard (either eDP 1.3 or eDP
1.4) that is implemented on the DUT, based on which you may run compliance tests. Depending on
the Standard you select, the application provides the following tests:
NOTE
Table 1
The Standard Reference used in the table below for eDP 1.4 is the Proposed
VESA Embedded DisplayPort 1.4 PHY Compliance Test Guideline, Version 1,
Draft 1 and VESA Embedded DisplayPort (eDP) Standard 1.4. For eDP 1.3,
the standard reference is the VESA Embedded DisplayPort Source PHY
Compliance Test Guideline, Version 1.0. Visit http://www.vesa.org for more
details.
Source Electrical Specification (Differential and Single-Ended) Tests by Standard Reference
Test name
References
eDP 1.4
See
eDP 1.3
Eye Diagram Test
Refer to eDP CTG
page 22
Non ISI Jitter Test
Refer to eDP CTG
page 25
Total Jitter Test
Refer to eDP CTG
page 27
Deterministic Jitter Test
Refer to eDP CTG
page 29
Random Jitter Test
Refer to eDP CTG
page 31
Peak to Peak Differential Voltage Test
Refer to eDP Specification
page 33
Differential Voltage Level Test
Refer to eDP Specification
page 39
Differential Voltage Level Ratio Test
Refer to eDP Specification
page 44
Pre-Emphasis Level Test
Refer to eDP Specification
page 50
Pre-Emphasis Level Delta Test
Refer to eDP Specification
page 56
Rise/Fall Time Test
Refer to eDP CTG
page 65
Inter Pair Skew Test
Refer to eDP CTG
page 68
Main Link Frequency Compliance Test
Refer to eDP CTG
page 70
Overview
6
Test name
References
See
SSC Modulation Frequency Test
Refer to eDP CTG
page 73
SSC Modulation Deviation Test
Refer to eDP CTG
page 75
Intra Pair Skew Test
Refer to eDP CTG
page 78
AC Common Mode Noise
Refer to eDP CTG
page 81
Keysight eDP Compliance Testing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
1
Installing the eDP Automated
Test Application
Installing the Software / 8
Installing the License Key / 9
If you purchased the N6469A eDP Automated Test Application separately, you must install the
software and license key.
1
Installing the eDP Automated Test Application
Installing the Software
1
Ensure that you have the required version of the Keysight Infiniium Oscilloscope software:
• Refer to the release notes for the Infiniium software to find the minimum version required.
• To check the software version on the oscilloscope, click Help>About Infiniium... from the main
menu of the infiniium oscilloscope software.
2
To obtain the eDP Automated Test Application, go to the Keysight web site:
http://www.keysight.com/find/scope-apps-sw to download the eDP Automated Test Application
software for the desired oscilloscope.
3
Select the desired oscilloscope from the list of oscilloscopes.
4
From the list of available drivers, firmware and software for the specified oscilloscope, click the
link to the eDP Automated Test Application software.
5
Follow the How to Install procedure on the screen and click the Download button to download the
N6469A eDP Automated Test Application software.
NOTE
6
Ensure that the operating system is compliant with the N6469A eDP
Automated Test Application.
Click the download file and follow the instructions to install the application software.
You must make sure to accept the installation of the .NET framework software, which is required to
run the eDP Automated Test Application.
8
Keysight eDP Compliance Tesing Methods of Implementation
Installing the eDP Automated Test Application
1
Installing the License Key
1
Request a license code from Keysight by following the instructions on the Entitlement Certificate.
You require the oscilloscope’s “Option ID Number”, which you can find in the Help > About
Infiniium... dialog.
2
After you receive your license code from Keysight, click Utilities > Install Option License....
3
In the Install Option License dialog, enter license code and click Install License.
4
Click OK on the dialog to restart the Infiniium oscilloscope application to complete the installation
of the license.
5
Click Close to close the Install Option License dialog.
6
Choose File > Exit.
7
Restart the Infiniium Oscilloscope application software to complete the license installation.
Keysight eDP Compliance Tesing Methods of Implementation
9
1
10
Installing the eDP Automated Test Application
Keysight eDP Compliance Tesing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
2
Preparing for Measurements
Calibrating the Oscilloscope / 12
Required and Recommended Equipment / 13
Starting the eDP Automated Test Application / 14
Setting Up the Transmission Path Test Point / 18
2
Preparing for Measurements
Before running the eDP automated tests, you must calibrate the oscilloscope. Once you calibrate the
oscilloscope, you can start the eDP Automated Test Application and perform tests.
Calibrating the Oscilloscope
To calibrate the Keysight Infiniium Oscilloscope, see Chapter 6, “Calibrating the Infiniium Oscilloscope
and Probe”.
NOTE
NOTE
12
If the ambient temperature changes more than 5 degrees Celsius from
the calibration temperature, you must perform internal calibration again.
The delta between the calibration temperature and the present operating
temperature is shown in the Utilities>Calibration menu.
If you switch cables between channels or other oscilloscopes, it is
necessary to perform cable and probe calibration and channel de-skew
calibration again. Keysight recommends that after you perform
oscilloscope calibration, you must label the cables with the channel they
were calibrated for.
Keysight eDP Compliance Testing Methods of Implementation
Preparing for Measurements
2
Required and Recommended Equipment
Required Oscilloscope
All 90000A/90000X/90000Q Infiniium scopes with a bandwidth of 13 GHz and above are supported.
Required Fixtures and Accessories
Following fixtures and accessories are required to run the N6469A eDP automated test application.
Table 2
Required oscilloscope, fixtures and accessories
Required Fixtures/Accessories
Quantity
Recommended Oscilloscope
Embedded DisplayPort Test Point Adapter
(Recommended: Wilder eDP TPA 30/40/50)
1
Infiniium Series
E2655A/B/C Probe De-Skew and Performance
Verification Kit
1
Infiniium Series
BNC to SMA Converter
2
For Infiniium 90000A Series
SMA (male) to SMA (male) Converter
2
For Infiniium 90000X and 90000Q Series
Keysight eDP Compliance Testing Methods of Implementation
13
2
Preparing for Measurements
Starting the eDP Automated Test Application
1
From the Keysight Infiniium Oscilloscope’s main menu, choose Analyze > Automated Test Apps >
N6469A eDP Test App.
Figure 1
Keysight N6469A eDP Automated Test Application
NOTE
If you do not find the N6469A eDP Test App in the Automated Test Apps
menu, it indicates that the eDP Automated Test Application is not installed.
See Chapter 1, “Installing the eDP Automated Test Application”.
Figure 1 shows the eDP Automated Test Application’s main window. The task flow pane and the tabs
in the main pane show the process of preparing to run the automated tests:
14
Keysight eDP Compliance Testing Methods of Implementation
Preparing for Measurements
2
Tasks
Description
Set Up
Lets you identify and set up the test environment, including information about the Device
Under Test (DUT).
Select Tests
Lets you select the tests you want to run. The tests are organized hierarchically so that you
may select all tests in a group. After the tests are run, status indicators show which tests have
passed, failed or not been run, along with indicators for the test groups.
Configure
Lets you configure the test parameters (such as memory depth). This information appears in
the HTML Report.
Connect
Displays an image and lists out instructions on how to connect the oscilloscope to the DUT
for the tests to be run.
Run Tests
Starts the automated tests. If there is a requirement to change the connections to the DUT
while multiple tests are running, the tests pause automatically, the application provides
instructions on how to change the connection and wait for a confirmation that the
connections have been changed before continuing the test runs.
Automation
Enables construction of automated script of commands that drive the functionality of the
application.
Results
Contains detailed information about the tests that have been run. You may change the
thresholds at which marginal or critical warnings appear.
HTML Report
Displays a printable compliance report.
Keysight eDP Compliance Testing Methods of Implementation
15
2
Preparing for Measurements
Online Help Topics
For information on using the eDP Automated Test Application, go to the eDP Automated Test
Application’s main menu and click Help>Contents....
The N6469A eDP Automated Test Application’s online help describes:
•
Starting the eDP Automated Test Application
• To view/minimize the task flow pane
• To view/hide the toolbar
•
Creating or Opening a Test Project
•
Setting Up the Test Environment
• To set load preferences
• Device Definition
• Connection Setup
• Test Controller
•
Enabling the Switch Matrix
•
Setting Up the Precision Probe/Cable
•
Selecting Tests
•
Configuring Tests
• Compliance Limits
•
Connecting the Oscilloscope to the DUT
•
Running Tests
• To select the store mode
• To run multiple tests
• To send email on pauses or stops
• To pause or stop on events
• To set the display preferences
• To specify the event
• To set the run preferences
•
Automating the Application
•
Viewing Results
• To delete trials from the results
• To show reference images and flash mask hits
• To change margin thresholds
• To change the test display order
• To set trial display preferences
•
Viewing/Exporting/Printing the Report
• To export the report
• To print the report
• To set HTML Report preferences
•
Saving Test Projects
• To set AutoRecovery preferences
•
Controlling the Application via a Remote PC
• To check for the App Remote license
• To identify the remote interface version
• To enable the remote interface
16
Keysight eDP Compliance Testing Methods of Implementation
Preparing for Measurements
2
• To enable remote interface hints
•
Using a Second Monitor
Keysight eDP Compliance Testing Methods of Implementation
17
2
Preparing for Measurements
Setting Up the Transmission Path Test Point
Figure 2
Embedded Link Test Point
The links in an Embedded DisplayPort (eDP) contain a Transmitter (TX) and a Receiver (RX), where
the transmitter is connected to the Source device and the receiver to the Sink device. You may
optionally set up connectors anywhere along the embedded channel. Taking into account various
embedded topologies, eDP provides measurement of the physical layer attributes.
Figure 2 shows a pictorial representation of the embedded link transmission path test points to
measure signal voltage and jitter on an embedded channel, which are:
18
TP1
eDP transmitter package pins
TP2
Source device eDP Cable Connector
TP3
Sink device (panel) eDP Cable Connector
TP4
eDP receiver package pins
Keysight eDP Compliance Testing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
3
eDP Test Application—Source
Tests
Overview / 20
3
eDP Source Tests
Overview
This section describes the tests for interoperability verification of eDP sources. Sources must be
tested either at point TP3 or point TP3_EQ, where the latter is placed after the Reference Receiver
Equalizer, as shown below in Figure 3. You must also include the actual eDP cable, which the system
integrator intends to use (or a properly correlated model of this cable) for source test measurements.
The analyzer and test point access fixtures from each test solution provider are identified in this
document. Unless specifically stated under the test conditions, all supported lanes for the DUT must
be evaluated.
Figure 3
Test Point 3 Connection for Source Tests
The Source Tests broadly include two categories namely:
•
Source Differential Tests
•
Source Single-Ended Tests
NOTE
20
All tests performed on the Source DUT are Normative tests only.
Keysight eDP Compliance Testing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
4
eDP Automated Source
Differential Tests
This section describes the differential tests for interoperability verification of eDP sources.
4
eDP Automated Source Differential Tests
Eye Diagram Test
Test Overview
The Eye Diagram Test evaluates the waveform to ensure that the timing variables and amplitude
trajectories support the overall eDP system objective of Bit Error Rate in data transmission.
The source eye diagram performance provides the best visual aid to assess the interoperability
potential by showing the amplitude and timing attributes of the signal and also provides an intuitive
understanding of design margin.
Test Conditions
Specification
Test Point
eDP Version 1.4
eDP Version 1.3
TP3_EQ
TP3 (RBR, HBR)
TP3_EQ (HBR2)
Bit Rate
All bit rates are supported.
Voltage Level and
Pre-emphasis Level
The Source device sets the Voltage level and Pre-emphasis level for each supported data rate, such that it meets the Pass/Fail criteria as
specified in the CTG Specification.
SSC
If the DUT can operate in either the SSC-enabled or the SSC-disabled state, it shall be tested in both conditions.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
HBR2CPAT
PRBS7 (RBR, HBR)
HBR2CPAT (HBR2)
Test Procedure
1
Validate and acquire the signal.
2
Set up the equalizer defined for TP3_EQ base on the CTLE wizard.
3
Determine the threshold of the signal by measuring VTop and VBase.
4
Measure the data rate and validate the test pattern.
5
If random noise is included, use “EZJIT Complete” to perform jitter separation base on the Time
Interval Error (TIE) measurement of the signal.
6
Set up the clock recovery base on the clock recovery setting of the configuration variable.
7
Create eye diagram at the middle of the screen. The range of the eye diagram must be more than
one Unit Interval (UI) but less than 2.5 UI.
8
To obtain the optimum eye height, compute the eye height at different passing points.
9
Load the eye mask and position it centrally at the middle of the eye diagram.
a To measure with the “Dynamic” eye mask height location, note the center eye mask perimeter
value and if required, modify the eye mask height vertices to the optimum eye height location.
• Note the center eye mask and compute the eye mask height and width. The eye mask
supports only four vertices point center mask.
22
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
• To modify the eye mask height point, shift the eye mask height vertices horizontally between
0.375 UI and 0.625 UI as shown in Figure 4.
Figure 4
eDP TP3_EQ Eye Mask
b To measure with the “Fixed” eye mask height location, load the eye mask directly without any
modification.
10 Run the eye mask until you achieve the required number of UIs.
11 Check for any signal trajectories that may have entered into the eye mask.
Viewing Test Results
The measured eye diagram for the test signal must fall within the conformance limit of the
specifications for the CTG Test mentioned under the “References” column of Table 1.
Keysight eDP Compliance Testing Methods of Implementation
23
4
eDP Automated Source Differential Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 5
24
Reference Image for Eye Diagram Test
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
Non ISI Jitter Test
Test Overview
The Non ISI (Inter Symbol Interference) Jitter Test evaluates the amount of Non ISI jitter
accompanying the data transmission.
The overall system jitter budget defines the point of compliance for the Non ISI Jitter Test and the
different amounts of jitter allocation that each system component is allowed to contribute. Exceeding
any of these limits violates the component level jitter budget. Non ISI jitter must be limited in
magnitude because the receiver is unable to compensate any higher amount of jitter.
Test Conditions
Specification
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
eDP Version 1.4
eDP Version 1.3
TP3
TP3 (RBR, HBR)
RBR, HBR
All bit rates are supported.
RBR, HBR
The Source device sets the Voltage level and Pre-emphasis level for each supported data rate, such that it meets the Pass/Fail criteria as
specified in the CTG Specification.
SSC
If the DUT can operate in either the SSC-enabled or the SSC-disabled state, it shall be tested in both conditions.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
HBR2CPAT
PRBS7 (RBR, HBR)
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Set up the clock recovery base on the clock recovery setting in configuration variable.
5
Use “EZJIT Complete” to perform jitter separation base on the Time Interval Error (TIE)
measurement of the signal.
6
Compute the Non ISI Jitter using the following equation:
Non ISI Jitter = Total Jitter — JitterISI
where, JitterISI is the ISI Jitter component induced by ISI, which is the peak-to-peak value of
the histogram of rising edges or of the histogram of the falling edges, whichever is greater.
Viewing Test Results
The measured Non ISI Jitter value for the test signal must fall within the conformance limit of the
specifications for the CTG Test mentioned under the “References” column of Table 1.
Keysight eDP Compliance Testing Methods of Implementation
25
4
eDP Automated Source Differential Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 6
26
Reference Image for Non ISI Jitter Test
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
Total Jitter Test
Test Overview
The Total Jitter Test evaluates the total jitter, which is a form of data time interval error (Data-TIE)
jitter measurement, which accompanies data transmission at either an explicit bit error rate of 10-9
or through an approved estimation technique.
Similar to Non ISI jitter, the overall system jitter budget defines the point of compliance for the Total
Jitter Test and allocates different amounts of jitter that each system component is allowed to
contribute. Exceeding any of these limits violates the component level jitter budget.
Test Conditions
Specification
Test Point
eDP Version 1.4
eDP Version 1.3
TP3_EQ
TP3 (RBR, HBR)
TP3_EQ (HBR2)
Bit Rate
All bit rates are supported
Voltage Level and
Pre-emphasis Level
Voltage level and Pre-emphasis level as set for the Eye Diagram test.
SSC
If the DUT can operate in either the SSC-enabled or the SSC-disabled state, it shall be tested in both conditions.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
HBR2CPAT
PRBS7 (RBR, HBR)
HBR2CPAT (HBR2)
Test Procedure
1
Validate and acquire the signal.
2
Set up the equalizer defined for TP3_EQ base on the CTLE wizard.
3
Determine the threshold of the signal by measuring VTop and VBase.
4
Measure the data rate and validate the test pattern.
5
Set up the clock recovery base on the clock recovery setting of the configuration variable.
6
Use “EZJIT Complete” to perform jitter separation base on the Time Interval Error (TIE)
measurement of the signal.
7
Use the Dual Dirac Technique to estimate the Total Jitter for bit error rate of 10-9 using the following
equation:
Total Jitter = Deterministic Jitterdd + n * Random Jitter
where, Deterministic Jitterdd is the deterministic jitter, Random Jitter is the random jitter,
which is a standard deviation value of an idealized pure noise process and n is the multiplier
that is determined by the bit error ratio (n = 12.0 for bit error ration of 1 * 10-9).
Viewing Test Results
The measured value of Total Jitter for the test signal must fall within the conformance limit of the
specifications for the CTG Test mentioned under the “References” column of Table 1.
Keysight eDP Compliance Testing Methods of Implementation
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eDP Automated Source Differential Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 7
28
Reference Image for Total Jitter Test
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
Deterministic Jitter Test
Test Overview
The Deterministic Jitter Test evaluates the deterministic jitter, which is also a form of Data-TIE jitter
measurement, accompanying the data transmission.
Similar to the previous types of jitter, the overall system jitter budget defines the point of compliance
for the Deterministic Jitter Test and allocates different amounts of jitter that each system component
is allowed to contribute. Exceeding any of these limits violates the component level jitter budget.
Test Conditions
Specification
Test Point
eDP Version 1.4
eDP Version 1.3
TP3_EQ
TP3 (RBR, HBR)
TP3_EQ (HR2)
Bit Rate
All bit rates are supported
Voltage Level and
Pre-emphasis Level
Voltage level and Pre-emphasis level as set for the Eye Diagram test.
SSC
If the DUT can operate in either the SSC-enabled or the SSC-disabled state, it shall be tested in both conditions.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
HBR2CPAT
PRBS7 (RBR, HBR)
HBR2CPAT (HBR2)
Test Procedure
1
Validate and acquire the signal.
2
Set up the equalizer defined for TP3_EQ base on the CTLE wizard.
3
Determine the threshold of the signal by measuring VTop and VBase.
4
Measure the data rate and validate the test pattern.
5
Set up the clock recovery base on the clock recovery setting of the configuration variable.
6
Use “EZJIT Complete” to perform jitter separation base on the Time Interval Error (TIE)
measurement of the signal.
Viewing Test Results
The measured Deterministic Jitter value for the test signal must fall within the conformance limit of
the specifications for the CTG Test mentioned under the “References” column of Table 1.
Keysight eDP Compliance Testing Methods of Implementation
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4
eDP Automated Source Differential Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 8
30
Reference Image for Deterministic Jitter Test
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
Random Jitter Test
Test Overview
The Random Jitter Test evaluates the random jitter, which is also a form of Data-TIE jitter
measurement, accompanying the data transmission.
Similar to the previous types of jitter, the overall system jitter budget defines the point of compliance
for the Random Jitter Test and allocates different amounts of jitter that each system component is
allowed to contribute. Exceeding any of these limits violates the component level jitter budget.
Test Conditions
Specification
Test Point
eDP Version 1.4
eDP Version 1.3
TP3_EQ
TP3 (RBR, HBR)
TP3_EQ (HBR2)
Bit Rate
All bit rates are supported.
Voltage Level and
Pre-emphasis Level
Voltage level and Pre-emphasis level as set for the Eye Diagram test.
SSC
If the DUT can operate in either the SSC-enabled or the SSC-disabled state, it shall be tested in both conditions.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
HBR2CPAT
PRBS7 (RBR, HBR)
HBR2CPAT (HBR2)
Test Procedure
1
Validate and acquire the signal.
2
Set up the equalizer defined for TP3_EQ base on the CTLE wizard.
3
Determine the threshold of the signal by measuring VTop and VBase.
4
Measure the data rate and validate the test pattern.
5
Set up the clock recovery base on the clock recovery setting of the configuration variable.
6
Use “EZJIT Complete” to perform jitter separation base on the Time Interval Error (TIE)
measurement of the signal.
Viewing Test Results
The measured random jitter value for the test signal must fall within the conformance limit of the
specifications for the CTG Test mentioned under the “References” column of Table 1.
Keysight eDP Compliance Testing Methods of Implementation
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eDP Automated Source Differential Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 9
32
Reference Image for Random Jitter Test
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
Peak to Peak Differential Voltage Test
Test Overview
The Peak to Peak Differential Voltage Test evaluates the peak to peak voltage accompanying the
data transmission.
You can measure the transition and non-transition voltage swings for each supported voltage level
and pre-emphasis setting. To obtain the peak to peak voltage, you must combine the High and Low
voltage measurements formed within each transition and non-transition voltage swing.
Compute the peak to peak voltages for transition and non-transition voltage swing for a given
voltage level and pre-emphasis level (LvlX) using the following equations:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
where VT_LvIX_PP is the peak to peak voltage at the transition bit and VN_LvIX_PP is the peak to
peak voltage at the non transition bit. The constituent voltages VT_LvIX_H, VT_LvIX_L, VN_LvIX_H
and VN_LvIX_L are identified in the following figures showing generalized pre-emphasis and non
pre-emphasized waveforms.
NOTE
The condition for Level 0 pre-emphasis is identified separately in the
following figures but is merely a special case. The measurement of high and
low voltage values is an average value derived from a specific number of UI
obtained over a certain number of required test patterns.
For PLTPAT
There are specific qualifying patterns in the 80-Bit Custom pattern (PLTPAT) for ‘High’ and ‘Low’
voltage level measurements. These measurements require a 1-1-1-1-1-0-0-0-0-0 balanced pattern
and no preconditioning is required on this pattern. The transition voltage measurements, VT_LvIX_H
and VT_LvIX_L is the average value over the 40% to 70% UI points in the transition bit. The
non-transition voltage measurement, VN_LvIX_H and VN_LvIX_L is the average value over three UI
points ending at the 50% point of the 5th bit of the five successive transmitted 1s or 0s of the
patterns. Refer to Figure 10.
Figure 10
High and Low Voltage Measurement for PLTPAT
For PRBS7
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eDP Automated Source Differential Tests
There are specific qualifying patterns in PRBS7 and other sequence for ‘High’ and ‘Low’ voltage level
measurements. The ‘High’ level measurements require a 0-1-0-1-1-1-1-1-1-1 pattern and the ‘Low’
level measurements require a 1-0-1-0-0-0-0-1 pattern. Refer to Figure 11 and Figure 12.The first
3-bits in these patterns are a precondition to the transition measurements. The precondition bits for
a transition to high level voltage measurement, are 0-1-0 and for a transition to low level voltage
measurement are 1-0-1.
Figure 11
High Voltage Measurement for PRBS7
The transition voltage measurements, VT_LvIX_H and VT_LvIX_L are the average value over the 40% to
70% UI points in the transition bit. The non-transition voltage measurement, VN_LvIX_H is the average
value over three UI points ending at the 50% point of the 6th bit of the seven successive transmitted
1s of the patterns. The non-transition voltage measurement, VN_LvIX_L is the average value over two
UI points ending at 50% point of the 4th bit of the four successive transmitted 0s of the patterns.
Figure 12
Low Voltage Measurement for PRBS7
Test Conditions
Specification
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
34
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
All bit rates are supported.
Not Applicable
Any Voltage level and Pre-Emphasis level that are compliant to all
normative tests run on the Source.
Not Applicable
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
Specification
eDP Version 1.4
eDP Version 1.3
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
PLTPAT
Not Applicable
SSC
Test Lane
Test Pattern
4
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
5
Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
6
Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
7
Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
8
Compute the peak to peak voltage for both transition and non-transition voltage levels using the
following equations:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
9
Obtain the value of the peak to peak differential voltage from the worst case of both transition
and non-transition voltage measurements using the following equation:
VPP = Worst Case (VT_LvIX_PP, VN_LvIX_PP)
Viewing Test Results
The measured value of the peak to peak differential voltage for the test signal must fall within the
conformance limit of the specifications for the CTG Test mentioned under the “References” column of
Table 1.
Keysight eDP Compliance Testing Methods of Implementation
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4
eDP Automated Source Differential Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 13
36
Reference Image for Peak to Peak Differential Voltage Test — VH Transition Bit
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
Figure 14
Reference Image for Peak to Peak Differential Voltage Test — VL Transition Bit
Figure 15
Reference Image for Peak to Peak Differential Voltage Test — VH Non Transition Bit
Keysight eDP Compliance Testing Methods of Implementation
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eDP Automated Source Differential Tests
Figure 16
38
Reference Image for Peak to Peak Differential Voltage Test — VL Non Transition Bit
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
Differential Voltage Level Test
Test Overview
The Differential Voltage Level Test evaluates the differential voltage level accompanying the data
transmission.
You can define the expected output for each setting of voltage level on the source, such that the
output correlates with the system budget elements such as cable loss, receiver EYE
minimum/maximum values and PC board transmission line loss. Furthermore, it must be kept in
mind that the link must benefit when you increase level settings.
You can measure the transition and non-transition voltage swings for each supported voltage level
and pre-emphasis setting. To obtain the peak to peak voltage, you must combine the High and Low
voltage measurements formed within each transition and non-transition voltage swing.
Compute the peak to peak voltages for transition and non-transition voltage swing for a given
voltage level and pre-emphasis level (LvlX) using the following equations:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
where VT_LvIX_PP is the peak to peak voltage at the transition bit and VN_LvIX_PP is the peak to
peak voltage at the non-transition bit. The constituent voltages VT_LvIX_H, VT_LvIX_L, VN_LvIX_H
and VN_LvIX_L are identified in the following figures showing generalized pre-emphasis and non
pre-emphasized waveforms.
NOTE
The condition for Level 0 pre-emphasis is identified separately in the
following figures but is merely a special case. The measurement of high and
low voltage values is an average value derived from a specific number of UI
obtained over a certain number of required test patterns.
For PLTPAT:
There are specific qualifying patterns in the 80-Bit Custom pattern (PLTPAT) for ‘High’ and ‘Low’
voltage level measurements. These measurements require a 1-1-1-1-1-0-0-0-0-0 balanced pattern
and no preconditioning is required on this pattern. The transition voltage measurements, VT_LvIX_H
and VT_LvIX_L is the average value over the 40% to 70% UI points in the transition bit. The
non-transition voltage measurement, VN_LvIX_H and VN_LvIX_L is the average value over three UI
points ending at the 50% point of the 5th bit of the five successive transmitted 1s or 0s of the
patterns. Refer to Figure 17.
Figure 17
High and Low Voltage Measurement for PLTPAT
Keysight eDP Compliance Testing Methods of Implementation
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eDP Automated Source Differential Tests
For PRBS7:
There are specific qualifying patterns in PRBS7 and other sequence for ‘High’ and ‘Low’ voltage level
measurements. The ‘High’ level measurements require a 0-1-0-1-1-1-1-1-1-1 pattern and the ‘Low’
level measurements require a 1-0-1-0-0-0-0-1 pattern. Refer to Figure 18 and Figure 19. The first
3-bits in these patterns are a precondition to the transition measurements. The precondition bits for
a transition to high level voltage measurement, are 0-1-0 and for a transition to low level voltage
measurement are 1-0-1.
Figure 18
High Voltage Measurement for PRBS7
The transition voltage measurements, VT_LvIX_H and VT_LvIX_L are the average value over the 40% to
70% UI points in the transition bit. The non-transition voltage measurement, VN_LvIX_H is the average
value over three UI points ending at the 50% point of the 6th bit of the seven successive transmitted
1s of the patterns. The non-transition voltage measurement, VN_LvIX_L is the average value over two
UI points ending at 50% point of the 4th bit of the four successive transmitted 0s of the patterns.
Figure 19
Low Voltage Measurement for PRBS7
Test Conditions
Specification
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
40
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
All bit rates are supported.
Not Applicable
Any Voltage level and Pre-Emphasis level that are compliant to all
normative tests run on the Source.
Not Applicable
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
Specification
eDP Version 1.4
eDP Version 1.3
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
PLTPAT
Not Applicable
SSC
Test Lane
Test Pattern
4
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
5
Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
6
Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
7
Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
8
Compute the value of differential voltage level from the peak to peak voltage for non-transition
voltage measurement using the following equation:
Differential Voltage Level (VN_LvIX_PP) = VN_LvIX_H — VN_LvIX_L
Viewing Test Results
The measured value of the differential voltage level for the test signal must fall within the
conformance limit of the specifications for the CTG Test mentioned under the “References” column of
Table 1.
Keysight eDP Compliance Testing Methods of Implementation
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4
eDP Automated Source Differential Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 20
42
Reference Image for Differential Voltage Level Test — VH Non Transition Bit
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
Figure 21
4
Reference Image for Differential Voltage Level Test — VL Non Transition Bit
Keysight eDP Compliance Testing Methods of Implementation
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4
eDP Automated Source Differential Tests
Differential Voltage Level Ratio Test
Test Overview
The Differential Voltage Level Ratio Test evaluates the differential voltage level accompanying the
data transmission and ensures that differential voltage level settings are monotonic so that the sink
device relies on the source device to incrementally increase upon request by the sink.
You can define the expected output for each setting of voltage level on the source, such that the
output correlates with the system budget elements such as cable loss, receiver EYE
minimum/maximum values and PC board transmission line loss. Furthermore, it must be kept in
mind that the link must benefit when you increase level settings.
You can measure the transition and non-transition voltage swings for each supported voltage level
and pre-emphasis setting. To obtain the peak to peak voltage, you must combine the High and Low
voltage measurements formed within each transition and non-transition voltage swing.
Compute the peak to peak voltages for transition and non-transition voltage swing for a given
voltage level and pre-emphasis level (LvlX) using the following equations:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
where VT_LvIX_PP is the peak to peak voltage at the transition bit and VN_LvIX_PP is the peak to
peak voltage at the non-transition bit. The constituent voltages VT_LvIX_H, VT_LvIX_L, VN_LvIX_H
and VN_LvIX_L are identified in the following figures showing generalized pre-emphasis and non
pre-emphasized waveforms.
NOTE
The condition for Level 0 pre-emphasis is identified separately in the
following figures but is merely a special case. The measurement of high and
low voltage values is an average value derived from a specific number of UI
obtained over a certain number of required test patterns.
For PLTPAT:
There are specific qualifying patterns in the 80-Bit Custom pattern (PLTPAT) for ‘High’ and ‘Low’
voltage level measurements. These measurements require a 1-1-1-1-1-0-0-0-0-0 balanced pattern
and no preconditioning is required on this pattern. The transition voltage measurements, VT_LvIX_H
and VT_LvIX_L is the average value over the 40% to 70% UI points in the transition bit. The
non-transition voltage measurement, VN_LvIX_H and VN_LvIX_L is the average value over three UI
points ending at the 50% point of the 5th bit of the five successive transmitted 1s or 0s of the
patterns. Refer to Figure 22.
44
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
Figure 22
4
High and Low Voltage Measurement for PLTPAT
For PRBS7:
There are specific qualifying patterns in PRBS7 and other sequence for ‘High’ and ‘Low’ voltage level
measurements. The ‘High’ level measurements require a 0-1-0-1-1-1-1-1-1-1 pattern and the ‘Low’
level measurements require a 1-0-1-0-0-0-0-1 pattern. Refer to Figure 23 and Figure 24. The first
3-bits in these patterns are a precondition to the transition measurements. The precondition bits for
a transition to high level voltage measurement, are 0-1-0 and for a transition to low level voltage
measurement are 1-0-1.
Figure 23
High Voltage Measurement for PRBS7
The transition voltage measurements, VT_LvIX_H and VT_LvIX_L are the average value over the 40% to
70% UI points in the transition bit. The non-transition voltage measurement, VN_LvIX_H is the average
value over three UI points ending at the 50% point of the 6th bit of the seven successive transmitted
1s of the patterns. The non-transition voltage measurement, VN_LvIX_L is the average value over two
UI points ending at 50% point of the 4th bit of the four successive transmitted 0s of the patterns.
Figure 24
Low Voltage Measurement for PRBS7
For each voltage level and pre-emphasis level setting that you use to run tests, use the following
equation to compute Differential Voltage Level Ratio:
Differential Voltage Level Ratio = 20 * Log10[VPP_LevelA / VPP_LevelB]
The following table identifies the peak to peak voltage level A and peak to peak voltage level B used
in the calculation of the Differential Voltage Level Ratio.
Keysight eDP Compliance Testing Methods of Implementation
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eDP Automated Source Differential Tests
Measurement
Peak to Peak Vol tage Level A
Peak to Peak Vol tage Level B
1
Level 1
Level 0
2
Level 2
Level 1
3
Level 3
Level 2
Test Conditions
Specification
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
All bit rates are supported.
Not Applicable
Any Voltage level and Pre-Emphasis level that are compliant to all
normative tests run on the Source.
Not Applicable
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
PLTPAT
Not Applicable
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
SSC
Test Lane
Test Pattern
Test Procedure
1
Validate and acquire the signal for Level A.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
5
Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
6
Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
7
Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
8
Compute the peak to peak voltage level A from the peak to peak voltage for non-transition
voltage measurement using the following equation:
VPP_LevelA = VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
9
Validate and acquire the signal for Level B.
10 Determine the threshold of the signal by measuring VTop and VBase.
11 Measure the data rate and validate the test pattern.
12 Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
13 Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
14 Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
46
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
4
15 Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
16 Compute the peak to peak voltage level B from the peak to peak voltage for non-transition
voltage measurement using the following equation:
VPP_LevelB = VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
17 Compute the differential voltage level ratio using the following equation:
Differential Voltage Level Ratio = 20 * Log10[VPP_LevelA / VPP_LevelB]
Viewing Test Results
The measured value of the differential voltage level ratio for the test signal must fall within the
conformance limit of the specifications for the CTG Test mentioned under the “References” column of
Table 1.
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 25
Reference Image for Differential Voltage Level Ratio Test: VH Non Transition Bit (Level 1)
Keysight eDP Compliance Testing Methods of Implementation
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48
eDP Automated Source Differential Tests
Figure 26
Reference Image for Differential Voltage Level Ratio Test — VL Non Transition Bit (Level 1)
Figure 27
Reference Image for Differential Voltage Level Ratio Test — VH Non Transition Bit (Level 0)
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Differential Tests
Figure 28
4
Reference Image for Differential Voltage Level Ratio Test — VL Non Transition Bit (Level 0)
Keysight eDP Compliance Testing Methods of Implementation
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eDP Automated Source Differential Tests
Pre-Emphasis Level Test
Test Overview
The Pre-Emphasis level Test evaluates the differential voltage level accompanying the data
transmission. In other words, this test evaluates the effect of pre-emphasis of the source waveform
by measuring the peak differential amplitude to validate the accuracy of the pre-emphasis setting.
You can define settings on the source making it capable to pre-emphasize the main link waveform to
overcome system losses, for example, losses through PC boards, connectors, and cables. The eDP
standard stipulates the relative magnitude of the waveform to overcome specific losses. As
pre-emphasis is negotiable, you may enable interoperability within two units, which have
substantially different degrees of pre-emphasis, by operating them at different settings. This test
ensures that the DUT is compliant to the levels of system loss or the pre-emphasis budget. Also, you
may ensure that the any increase in the pre-emphasis setting provides a improved signal to the sink.
You can measure the transition and non-transition voltage swings for each supported voltage level
and pre-emphasis setting. To obtain the peak to peak voltage, you must combine the High and Low
voltage measurements formed within each transition and non-transition voltage swing.
Compute the peak to peak voltages for transition and non-transition voltage swing for a given
voltage level and pre-emphasis level (LvlX) using the following equations:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
where VT_LvIX_PP is the peak to peak voltage at the transition bit and VN_LvIX_PP is the peak to
peak voltage at the non-transition bit. The constituent voltages VT_LvIX_H, VT_LvIX_L, VN_LvIX_H
and VN_LvIX_L are identified in the following figures showing generalized pre-emphasis and non
pre-emphasized waveforms.
NOTE
The condition for Level 0 pre-emphasis is identified separately in the
following figures but is merely a special case. The measurement of high and
low voltage values is an average value derived from a specific number of UI
obtained over a certain number of required test patterns.
For PLTPAT:
There are specific qualifying patterns in the 80-Bit Custom pattern (PLTPAT) for ‘High’ and ‘Low’
pre-emphasis level measurements. These measurements require a 1-1-1-1-1-0-0-0-0-0 balanced
pattern and no preconditioning is required on this pattern. The transition voltage measurements,
VT_LvIX_H and VT_LvIX_L is the average value over the 40% to 70% UI points in the transition bit. The
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non-transition voltage measurement, VN_LvIX_H and VN_LvIX_L is the average value over three UI
points ending at the 50% point of the 5th bit of the five successive transmitted 1s or 0s of the
patterns. Refer to Figure 29.
Figure 29
High and Low Voltage Measurement for PLTPAT
For PRBS7:
There are specific qualifying patterns in PRBS7 and other sequence for ‘High’ and ‘Low’ voltage level
measurements. The ‘High’ level measurements require a 0-1-0-1-1-1-1-1-1-1 pattern and the ‘Low’
level measurements require a 1-0-1-0-0-0-0-1 pattern. Refer to Figure 30 and Figure 31. The first
3-bits in these patterns are a precondition to the transition measurements. The precondition bits for
a transition to high level voltage measurement, are 0-1-0 and for a transition to low level voltage
measurement are 1-0-1.
Figure 30
High Voltage Measurement for PRBS7
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The transition voltage measurements, VT_LvIX_H and VT_LvIX_L are the average value over the 40% to
70% UI points in the transition bit. The non-transition voltage measurement, VN_LvIX_H is the average
value over three UI points ending at the 50% point of the 6th bit of the seven successive transmitted
1s of the patterns. The non-transition voltage measurement, VN_LvIX_L is the average value over two
UI points ending at 50% point of the 4th bit of the four successive transmitted 0s of the patterns.
Figure 31
Low Voltage Measurement for PRBS7
For each voltage level and pre-emphasis level setting that you use to run tests, use the following
equation to compute Pre-Emphasis level:
Pre-Emphasis Level = 20 * Log10[VT_LvIX_PP / VN_LvIX_PP]
Test Conditions
Specification
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
All bit rates are supported.
Not Applicable
Any Voltage level and Pre-Emphasis level that are compliant to all
normative tests run on the Source.
Not Applicable
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
PLTPAT
Not Applicable
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
SSC
Test Lane
Test Pattern
Test Procedure
52
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
5
Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
6
Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
7
Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
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Compute the value of peak to peak voltage for both transition and non-transition voltage levels
using the following equation:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
9
Compute the value of pre-emphasis level from the peak to peak voltage for both transition and
non-transition voltage levels using the following equation:
Pre-Emphasis Level = 20 * Log10[VT_LvIX_PP / VN_LvIX_PP]
Viewing Test Results
The measured value of the pre-emphasis level for the test signal must fall within the conformance
limit of the specifications for the CTG Test mentioned under the “References” column of Table 1.
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 32
Reference Image for Pre-Emphasis Level Test — VH Transition Bit
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Figure 33
Reference Image for Pre-Emphasis Level Test — VL Transition Bit
Figure 34
Reference Image for Pre-Emphasis Level Test — VH Non Transition Bit
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Figure 35
4
Reference Image for Pre-Emphasis Level Test — VH Non Transition Bit
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Pre-Emphasis Level Delta Test
Test Overview
The Pre-Emphasis Level Delta Test evaluates the differential voltage level accompanying the data
transmission. This test also evaluates the effect of pre-emphasis of the Source waveform by
measuring the peak differential amplitude to ensure accuracy in the pre-emphasis setting.
You can define settings on the source making it capable to pre-emphasize the main link waveform to
overcome system losses, for example, losses through PC boards, connectors, and cables. The eDP
standard stipulates the relative magnitude of the waveform to overcome specific losses. As
pre-emphasis is negotiable, you may enable interoperability within two units, which have
substantially different degrees of pre-emphasis, by operating them at different settings. This test
ensures that the DUT is compliant to the levels of system loss or the pre-emphasis budget. Also, you
may ensure that the any increase in the pre-emphasis setting provides a improved signal to the sink.
You can measure the transition and non-transition voltage swings for each supported voltage level
and pre-emphasis setting. To obtain the peak to peak voltage, you must combine the High and Low
voltage measurements formed within each transition and non-transition voltage swing.
Compute the peak to peak voltages for transition and non-transition voltage swing for a given
voltage level and pre-emphasis level (LvlX) using the following equations:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
where VT_LvIX_PP is the peak to peak voltage at the transition bit and VN_LvIX_PP is the peak to
peak voltage at the non-transition bit. The constituent voltages VT_LvIX_H, VT_LvIX_L, VN_LvIX_H
and VN_LvIX_L are identified in the following figures showing generalized pre-emphasis and non
pre-emphasized waveforms.
NOTE
The condition for Level 0 pre-emphasis is identified separately in the
following figures but is merely a special case. The measurement of high and
low voltage values is an average value derived from a specific number of UI
obtained over a certain number of required test patterns.
For PLTPAT:
There are specific qualifying patterns in the 80-Bit Custom pattern (PLTPAT) for ‘High’ and ‘Low’
pre-emphasis level measurements. These measurements require a 1-1-1-1-1-0-0-0-0-0 balanced
pattern and no preconditioning is required on this pattern. The transition voltage measurements,
VT_LvIX_H and VT_LvIX_L is the average value over the 40% to 70% UI points in the transition bit. The
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non-transition voltage measurement, VN_LvIX_H and VN_LvIX_L is the average value over three UI
points ending at the 50% point of the 5th bit of the five successive transmitted 1s or 0s of the
patterns. Refer to Figure 36.
Figure 36
High and Low Voltage Measurement for PLTPAT
For PRBS7:
There are specific qualifying patterns in PRBS7 and other sequence for ‘High’ and ‘Low’ voltage level
measurements. The ‘High’ level measurements require a 0-1-0-1-1-1-1-1-1-1 pattern and the ‘Low’
level measurements require a 1-0-1-0-0-0-0-1 pattern. Refer to Figure 37 and Figure 38. The first
3-bits in these patterns are a precondition to the transition measurements. The precondition bits for
a transition to high level voltage measurement, are 0-1-0 and for a transition to low level voltage
measurement are 1-0-1.
Figure 37
High Voltage Measurement for PRBS7
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The transition voltage measurements, VT_LvIX_H and VT_LvIX_L are the average value over the 40% to
70% UI points in the transition bit. The non-transition voltage measurement, VN_LvIX_H is the average
value over three UI points ending at the 50% point of the 6th bit of the seven successive transmitted
1s of the patterns. The non-transition voltage measurement, VN_LvIX_L is the average value over two
UI points ending at 50% point of the 4th bit of the four successive transmitted 0s of the patterns.
Figure 38
Low Voltage Measurement for PRBS7
For each voltage level and pre-emphasis level setting that you use to run tests, use the following
equation to compute Pre-Emphasis level:
Pre-Emphasis Level = 20 * Log10[VT_LvIX_PP / VN_LvIX_PP]
Compute the Pre-Emphasis Level Delta using the following equation:
Pre-Emphasis Level Delta = Pre-Emphasis Level A — Pre-Emphasis Level B
The following table identifies the pre-emphasis level A and pre-emphasis level B used to calculate
the Pre-Emphasis Level Delta.
Measurement
Pre-Emphasis Level A
Pre-Emphasis Level B
1
Level 1
Level 0
2
Level 2
Level 1
3
Level 3
Level 2
Test Conditions
Specification
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
SSC
Test Lane
Test Pattern
58
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
All bit rates are supported.
Not Applicable
Any Voltage level and Pre-Emphasis level that are compliant to all
normative tests run on the Source.
Not Applicable
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
PLTPAT
Not Applicable
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Test Procedure
1
Validate and acquire the signal for Pre-Emphasis Level A.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
5
Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
6
Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
7
Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
8
Compute the peak to peak voltage for both transition and non-transition voltage measurements
using the following equation:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
9
Compute the Pre-Emphasis Level A from the peak to peak voltage for both transition and
non-transition voltage measurements using the following equation:
Pre-Emphasis Level A = 20 * Log10[VT_LvIX_PP / VN_LvIX_PP]
10 Validate and acquire the signal for Pre-Emphasis Level B.
11 Determine the threshold of the signal by measuring VTop and VBase.
12 Measure the data rate and validate the test pattern.
13 Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
14 Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
15 Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
16 Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
17 Compute the peak to peak voltage for both transition and non-transition voltage measurements
using the following equations:
VT_LvIX_PP = VT_LvIX_H — VT_LvIX_L
VN_LvIX_PP = VN_LvIX_H — VN_LvIX_L
18 Compute the Pre-Emphasis level B from the peak to peak voltage for both transition and
non-transition voltage measurements using the following equation:
Pre-Emphasis Level B = 20 * Log10[VT_LvIX_PP / VN_LvIX_PP]
19 Compute the value for Pre-Emphasis Level Delta from Pre-Emphasis Level A and Pre-Emphasis
Level B values using the following equation:
Pre-Emphasis Level Delta = Pre-Emphasis Level A — Pre-Emphasis Level B
Viewing Test Results
The measured value of pre-emphasis level delta for the test signal must fall within the conformance
limit of the specifications for the CTG Test mentioned under the “References” column of Table 1.
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For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 39
60
Reference Image for Pre-Emphasis Level Delta Test — VH Transition Bit (Level 1)
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Figure 40
Reference Image for Pre-Emphasis Level Delta Test — VL Transition Bit (Level 1)
Figure 41
Reference Image for Pre-Emphasis Level Delta Test — VH Non Transition Bit (Level 1)
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Figure 42
Reference Image for Pre-Emphasis Level Delta Test — VL Non Transition Bit (Level 1)
Figure 43
Reference Image for Pre-Emphasis Level Delta Test — VH Transition Bit (Level 0)
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Figure 44
Reference Image for Pre-Emphasis Level Delta Test — VL Transition Bit (Level 0)
Figure 45
Reference Image for Pre-Emphasis Level Delta Test — VH Non Transition Bit (Level 0)
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Figure 46
64
Reference Image for Pre-Emphasis Level Delta Test — VL Non Transition Bit (Level 0)
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Rise/Fall Time Test
Test Overview
The Rise/Fall Time Test evaluates the differential rise and fall time of the main link data lanes. The
differential transition time is useful in predicting the Electromagnetic Interference
(EMI)/Radio-Frequency Interference (RFI) performance of the channels.
Reduction in the differential transition time increases the eye opening. However, it also increases the
time domain crosstalk which, decreases the margin and increases risks of higher EMI/RFI, depending
on the type of coupling.
For each lane, use the differential voltage level values to calculate the High and Low levels of
differential transition time. The rise time is measured between 20% to 80% of VL to VH transition and
fall time is measured between 80% to 20% of VH to VL transition. The application reports the
minimum, maximum and average differential rise and fall time values.
Test Conditions
Specification
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
Bit Rate
Highest bit rate is supported.
Not Applicable
Voltage Level and
Pre-emphasis Level
Voltage Level: Level 2
Pre-emphasis Level: Level 0
Not Applicable
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
PLTPAT
Not Applicable
Test Point
SSC
Test Lane
Test Pattern
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level.
5
Set up the Histogram to measure the average value of high voltage level for both transition and
non-transition voltage levels.
6
Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level.
7
Set up the Histogram to measure the average value of low voltage level for both transition and
non-transition voltage levels.
8
Set up the measurement top and base voltage levels based on the High and Low voltage levels.
9
Set up the measurement threshold to 20%, 50%, 80% of top and base voltage levels.
10 Measure the rise time or fall time of the differential signal.
Viewing Test Results
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The measured value of the rise time / fall time for the test signal must fall within the conformance
limit of the specifications for the CTG Test mentioned under the “References” column of Table 1.
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 47
66
Reference Image for Rise Time Test
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Figure 48
4
Reference Image for Fall Time Test
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eDP Automated Source Differential Tests
Inter Pair Skew Test
Test Overview
The Inter Pair Skew Test evaluates the skew, or time delay, between differential data lanes in the eDP
interface.
The eDP interface has the ability to skew or deskew lanes to eliminate simultaneous degradation of
concurrent bytes of transmitted data. It is essential to ensure that the combined components of the
system do not exceed the elasticity of the receiver.
You may capture waveforms on two lanes simultaneously, which are set up on two measurement
channels. Evaluate both waveforms at a common point and measure the time difference between the
corresponding edges at the transition point. Locate each edge by determining the point where the
waveform crosses the transition amplitude.
VTransition = 0 Volts
The VESA DisplayPort Standard specifies an offset of 20 UI from Lane 0 to Lane 1, Lane 1 to Lane 2
and from Lane 2 to Lane 3. The resultant offset is cumulative, which indicates that the offset between
Lane 0 and Lane 2 is 40 UI. Nominal Skew is same as the expected offset between the tested lanes.
Inter Lane Skew = {1 / NumEdges}∑ | TTransition_LaneA — TTransition_LaneB | — Nominal Skew
Operation Type
Two Lane Operation
Four Lane Operation
Lane Direction
Lane A
Lane B
Lane 0 to Lane 1
Lane 0
Lane 1
Lane 0 to Lane 1
Lane 0
Lane 1
Lane 0 to Lane 2
Lane 0
Lane 2
Lane 0 to Lane 3
Lane 0
Lane 3
Lane 1 to Lane 2
Lane 1
Lane 2
Lane 1 to Lane 3
Lane 1
Lane 3
Lane 2 to Lane 3
Lane 2
Lane 3
Test Conditions
Specification
Test Point
eDP Version 1.4
eDP Version 1.3
TP3
Bit Rate
Highest bit rate is supported.
Voltage Level and
Pre-emphasis Level
Voltage Level: Level 2
Pre-emphasis Level: Level 0
SSC
Test Lane
Test Pattern
68
If the DUT can operate in either the SSC-enabled or the SSC-disabled state, it shall be tested in both conditions.
All test lanes must generate a test pattern to induce crosstalk.
PRBS7
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Test Procedure
1
Validate and acquire the signal for Lane A.
2
Determine the threshold of the signal by measuring VTop and VBase for Lane A.
3
Measure the data rate and validate the test pattern for Lane A.
4
Validate and acquire the signal for Lane B.
5
Determine the threshold of the signal by measuring VTop and VBase for Lane B.
6
Measure the data rate and validate the test pattern for Lane B.
7
Decode signal for Lane A and Lane B.
8
Search for the inter pair skew pattern from the decoded signal for Lane A and Lane B.
9
Compute the time difference between the corresponding edges at the transition point of Lane A
and Lane B.
10 Compute the Inter Lane Skew using the following equation:
Inter Lane Skew = {1 / NumEdges}∑ | TTransition_LaneA — TTransition_LaneB | — Nominal Skew
where, Nominal Skew is the expected inter pair skew between Lane A and Lane B.
Viewing Test Results
The measured value of the inter pair skew for the test signal must fall within the conformance limit of
the specifications for the CTG Test mentioned under the “References” column of Table 1.
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 49
Reference Image for Inter Pair Skew Test
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eDP Automated Source Differential Tests
Main Link Frequency Compliance Test
Test Overview
The Main Link Frequency Compliance Test ensures that under any condition, the average transfer
rate does not exceed the minimum or maximum frequency range, as defined in the eDP 1.4
Standard. Excessive frequency error from fundamental references results in receiver errors or poses
difficulty in tracking.
For SSC Enabled:
The minimum acquisition time is 33.4 micro seconds (μs). The application evaluates at least ten full
SSC cycles of the signal, along with evaluating the minimum, maximum and average frequency
values while the spread spectrum clocking is active.
For SSC Disabled:
The minimum acquisition time is 33.4 μs, which is comparable to the acquisition time when SSC is
enabled. The application evaluates at least ten acquisitions of the signal, along with evaluating the
minimum, maximum and average frequency values while the spread spectrum clocking is inactive.
Test Conditions
Specification
eDP Version 1.4
eDP Version 1.3
Test Point
TP3
Bit Rate
All bit rates are supported.
Voltage Level and
Pre-emphasis Level
Any Voltage level and Pre-Emphasis level that are compliant to all
normative tests run on the Source.
SSC
Voltage Level: Level 2
Pre-emphasis Level: Level 0
If the DUT can operate in either the SSC-enabled or the SSC-disabled state, it shall be tested in both conditions.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
D10.2
Test Procedure
70
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
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4
For SSC enabled:
i
Set up the clock recovery base on the clock recovery setting of the configuration variable.
ii Measure the unit interval (UI) of the differential signal.
iii Set up a measurement trend to capture a range of unit interval values of the differential
signal.
iv Apply a low pass filter to the range of unit interval values.
v
Acquire a signal with an acquisition time that covers one full SSC cycle.
vi Measure the clock data recovery rate (CDR rate) for at least ten full SSC cycles.
vii Measure the minimum, maximum and mean unit interval values for at least ten full SSC
cycles.
viii Compute the minimum, maximum and mean data rate values for at least ten full SSC
cycles.
5
For SSC Disabled:
i
Set up the clock recovery base on the clock recovery setting of the configuration variable.
ii Measure the unit interval (UI) of the differential signal.
iii Set up a measurement trend to capture a range of unit interval values of the differential
signal.
iv Apply a low pass filter to the captured range of unit interval values.
v
Acquire a signal that attains the minimum acquisition time (33.4 μs).
vi Measure the clock data recovery rate (CDR rate) for at least ten full cycles that attain the
minimum acquisition time.
vii Measure the minimum, maximum and mean unit interval values for at least ten full cycles
that attain the minimum acquisition time.
viii Compute the minimum, maximum and mean data rate values for at least ten full cycles
that attain the minimum acquisition time.
6
Compute the Main Link Frequency using the following equation:
Main Link Frequency = (CDR Rate — Nominal Data Rate) / Nominal Data Rate) * 1E6
Viewing Test Results
The measured value of the main link frequency for the test signal must fall within the conformance
limit of the specifications for the CTG Test mentioned under the “References” column of Table 1.
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For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 50
72
Reference Image for Main Link Frequency Compliance Test
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SSC Modulation Frequency Test
Test Overview
The SSC Modulation Frequency Test evaluates the frequency of the SSC modulation and validates
that the frequency lies within the specification limits of the eDP Standard. SSC frequency has almost
little to no effect on interoperability of eDP sources.
The minimum acquisition time is 33.4 μs. When running this test, it is essential that you use a low
pass filter to remove the high frequency non-SSC jitter components. This low pass filter is a 2nd order
Butterworth filter with a 3 dB corner frequency of 1.98MHz, which is 60 times more than the highest
acceptable SSC frequency of 33kHz. You must conduct this analysis over a minimum of ten full SSC
cycles.
Test Conditions
Specification
eDP Version 1.4
eDP Version 1.3
Test Point
TP3
Bit Rate
Voltage Level and
Pre-emphasis
Level
All bit rates are supported.
Any Voltage level and Pre-Emphasis level that are
compliant to all normative tests run on the Source.
SSC
Voltage Level: Level 2
Pre-emphasis Level: Level 0
Only such DUTs are tested that operate in the SSC-enabled state.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
D10.2
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Set up the clock recovery base on the clock recovery setting of the configuration variable.
5
Measure the unit interval (UI) value of the differential signal.
6
Set up a measurement trend to capture a range of unit interval values of the differential signal.
7
Apply low pass filter to the range of unit interval values.
8
Measure the frequency of the filtered unit interval range.
Viewing Test Results
The measured value of the SSC modulation frequency for the test signal should be within the
conformance limit of the specifications for the CTG Test mentioned under the “References” column of
Table 1.
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For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 51
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Reference Image for SSC Modulation Frequency Test
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SSC Modulation Deviation Test
Test Overview
The SSC Modulation Deviation Test evaluates the range of SSC down-spreading of the transmitter
signal in Parts Per Million (PPM). One of the requirements of spread spectrum clocking is that the
sink receiver follows the instantaneous frequency of the transmitter signal. This test measures the
range of frequency deviation with SSC. The more the frequency deviates from the standard limits, the
higher are the risks of interoperability in eDP sources.
The minimum acquisition time is 33.4 μs. When running this test, it is essential that you use a low
pass filter to remove the high frequency non-SSC jitter components. This low pass filter is a 2nd order
Butterworth filter with a 3 dB corner frequency of 1.98MHz, which is 60 times more than the highest
acceptable SSC frequency of 33kHz. You must conduct this analysis over a minimum of ten full SSC
cycles.
The application evaluates the minimum and maximum transfer rate for each cycle for at least ten full
SSC Cycles. Evaluating the average transfer rate is optional. Calculate the SSC Range by deducting
the average of the maximum values of data rates from the average of the minimal values of data rate.
Use the following equation:
SSC Range = [Average(Data Rate Min. Values) — Average(Data Rate Max. Values)]
SSC Modulation Deviation = [SSC Range / Nominal Data Rate] * 1E6
Test Conditions
Specification
eDP Version 1.4
eDP Version 1.3
Test Point
TP3
Bit Rate
Voltage Level and
Pre-emphasis
Level
All bit rates are supported.
Any Voltage level and Pre-Emphasis level that are
compliant to all normative tests run on the Source.
SSC
Voltage Level: Level 2
Pre-emphasis Level: Level 0
Only such DUTs are tested that operate in the SSC-enabled state.
Test Lane
All test lanes must generate a test pattern to induce crosstalk.
Test Pattern
D10.2
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Set up the clock recovery base on the clock recovery setting of the configuration variable.
5
Measure the unit interval (UI) value of the differential signal.
6
Set up a measurement trend to capture a range of unit interval values of the differential signal.
7
Apply low pass filter to the range of unit interval values.
8
Measure the frequency of the filtered unit interval range.
9
Acquire a signal with an acquisition time that covers one full SSC cycle.
10 Measure the clock data recovery rate (CDR rate) for at least ten full SSC cycles.
11 Measure the minimum, maximum and mean unit interval values for at least ten full SSC cycles.
Keysight eDP Compliance Testing Methods of Implementation
75
4
eDP Automated Source Differential Tests
12 Compute the SSC Modulation Deviation using the following equations:
SSC Range = [Average(Data Rate Min. values) — Average(Data Rate Max. values)]
SSC Modulation Deviation = [SSC Range / Nominal Data Rate] * 1E6
Viewing Test Results
The measured value of the SSC modulation deviation for the test signal should be within the
conformance limit of the specifications for the CTG Test mentioned under the “References” column of
Table 1.
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 52
76
Reference Image for SSC Modulation Deviation Test
Keysight eDP Compliance Testing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
5
eDP Automated Source
Single-Ended Tests
This section describes the single-ended tests for interoperability verification of eDP sources.
5
eDP Automated Source Single-Ended Tests
Intra Pair Skew Test
Test Overview
The Intra Pair Skew Test evaluates the skew, or time delay, between the n and p legs of the
differential pairs of the eDP interface. You may use these measurements to predict the EMI/RFI
performance of the channels.
Intra-Pair Skew in the channel affects the signal during transition and results in a reduction of the
eye height. The Eye Diagram Test captures the impact of the intra-pair skew.
Prior to taking measurements, you must ensure that the measurement instrument is de-skewed and
compensated to achieve accurate results.
The application captures waveforms of both signal polarities (n and p) simultaneously on one lane, by
using two single-ended measurement channels. The rising edge of the data true signal (D+) is
compared with the falling edge of the complementary signal (D-), and the rising edge of the
complementary signal is compared to falling edge of the data true signal. Determine the point where
the waveform crosses the transition amplitude to find the time of transition.
For each lane composed of two single-ended signals D+ and D-, calculate the High and Low Voltage
levels for each single-ended signal by measuring the average value over the range of 0.6-0.75 UI,
which lies past the rising edge for VH and past the falling edge for VL.
Establish the skew timing threshold as the median voltage between VH and VL.
VThreshold_D+ = (VH_D+ + VL_D+) / 2
VThreshold_D- = (VH_D- + VL_D-) / 2
Calculate the intra pair skew by summing all skew values (high to low and low to high skew values)
and divide the total by the number of edges. Use the following equation:
Intra Pair Skew = {1/NumEdges}∑{[(TTrans_D+_Rise — TTrans_D-_Fall) + (TTrans_D+_Fall —
TTrans_D-_Rise)]/2}
The intra pair skew is measured for each supported lane:
•
Lane 0+ and Lane 0-
•
Lane 1+ and Lane 1-
•
Lane 2+ and Lane 2-
•
Lane 3+ and Lane 3-
Test Conditions
Specification
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
SSC
Test Lane
Test Pattern
78
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
Highest bit rate is supported.
Not Applicable
Any voltage level and pre-emphasis level are compliant to all
source normative tests
Not Applicable
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
HBR2CPAT
Not Applicable
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Single-Ended Tests
5
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level for the single-ended plus signal.
5
Set up the Histogram to measure the average value of high voltage level for the single-ended
plus signal.
6
Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level for the single-ended plus signal.
7
Set up the Histogram to measure the average value of low voltage level for the single-ended plus
signal.
8
Compute the threshold voltage for the single-ended plus signal using the following equation:
VThreshold_D+ = (VH_D+ + VL_D+) / 2
9
Acquire the qualifying test pattern over the specific number of required patterns to measure the
high voltage level for the single-ended minus signal.
10 Set up the Histogram to measure the average value of high voltage level for the single-ended
minus signal.
11 Acquire the qualifying test pattern over the specific number of required patterns to measure the
low voltage level for the single-ended minus signal.
12 Set up the Histogram to measure the average value of low voltage level for the single-ended
minus signal.
13 Compute the threshold voltage for the single-ended minus signal using the following equation:
VThreshold_D- = (VH_D- + VL_D-) / 2
14 Search the intra pair skew pattern for D+Rise to D-Fall from the single-ended plus signal using
InfiniiScan Generic Serial trigger.
15 Compute the time difference between the corresponding edges at the transition point of D+ and
D- over a specific number of required patterns.
16 Search the intra pair skew pattern for D+Fall to D-Rise from the single-ended plus signal using
InfiniiScan Generic Serial trigger.
17 Compute the time difference between the corresponding edges at the transition point of D+ and
D- over a specific number of required patterns.
18 Compute the Intra Lane Skew using the following equation:
Intra Pair Skew = {1/NumEdges}∑{[(TTrans_D+_Rise — TTrans_D-_Fall) + (TTrans_D+_Fall —
TTrans_D-_Rise)]/2}
Viewing Test Results
The measured intra pair skew for the test signal must fall within the conformance limit of the
specifications for the CTG Test mentioned under the “References” column of Table 1.
Keysight eDP Compliance Testing Methods of Implementation
79
5
eDP Automated Source Single-Ended Tests
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 53
80
Reference Image for Intra Pair Skew Test
Keysight eDP Compliance Testing Methods of Implementation
eDP Automated Source Single-Ended Tests
5
AC Common Mode Noise Test
Test Overview
The AC Common Mode Noise Test reports the common mode noise (unfiltered RMS) present in the
main link differential pairs. You may use these measurements to predict the EMI/RFI performance of
the channels.
The conversion of the main link signal from differential mode to common mode reduces the eye. This
effect is already taken into account during the eye measurement. Any increase in the common mode
noise that occurs due to crosstalk does not affect the channel margin measured at TP3_EQ.
Prior to taking measurements, you must ensure that the measurement instrument is de-skewed and
compensated to achieve accurate results.
Calculate the value of the common mode noise using the following equation:
VTX-AC-CM = (VTX-PLUS + VTX-MINUS) / 2
Calculate the value of the common mode noise RMS using the following equation:
VTX-AC-CM_RMS = [(X12 + X22 + X32 + ... + Xn2) / n]0.5
The common mode noise is measured for each supported lane:
•
Lane 0+ and Lane 0-
•
Lane 1+ and Lane 1-
•
Lane 2+ and Lane 2-
•
Lane 3+ and Lane 3-
Test Conditions
Specification
eDP Version 1.4
eDP Version 1.3
TP3
Not Applicable
All bit rates are supported.
Not Applicable
Any Voltage level and Pre-Emphasis level that are compliant to all
normative tests run on the Source.
Not Applicable
If the DUT can operate in either the SSC-enabled or the
SSC-disabled state, it shall be tested in both conditions.
Not Applicable
All test lanes must generate a test pattern to induce crosstalk.
Not Applicable
HBR2CPAT
Not Applicable
Test Point
Bit Rate
Voltage Level and
Pre-emphasis Level
SSC
Test Lane
Test Pattern
Test Procedure
1
Validate and acquire the signal.
2
Determine the threshold of the signal by measuring VTop and VBase.
3
Measure the data rate and validate the test pattern.
4
Set up the common mode signal from the single-ended plus and single-ended minus signals
using the following equation:
VTX-AC-CM = (VTX-PLUS + VTX-MINUS) / 2
5
Apply low pass filter to the common mode signal, if filter is enabled.
Keysight eDP Compliance Testing Methods of Implementation
81
5
eDP Automated Source Single-Ended Tests
6
Measure the value of the RMS voltage for the common mode signal, excluding the DC
component.
Viewing Test Results
The measured value of the AC common mode noise for the test signal is within the conformance limit
of the specifications for the CTG Test mentioned under the “References” column of Table 1.
For each test trial, click the Resul ts tab to view the results. Click the desired test to view its result. The
lower pane contains the displays the detailed description of the test results. A sample reference
image based on the measured values is captured by the oscilloscope. Click the sample reference
image to view the details. For information about viewing the test results, refer to Viewing Resul ts in
the online help.
Figure 54
82
Reference Image for AC Common Mode Noise Test
Keysight eDP Compliance Testing Methods of Implementation
Keysight N6469A eDP Automated Test Application
Methods of Implementation
6
Calibrating the Infiniium
Oscilloscope and Probe
Required Equipment for Calibration / 84
Internal Calibration / 85
This appendix describes the Keysight Infiniium digital storage oscilloscope calibration procedures.
6
Calibrating the Infiniium Oscilloscope and Probe
Required Equipment for Calibration
To calibrate the Infiniium oscilloscope in preparation for running the eDP automated tests, you need
the following equipment:
•
Keyboard, quantity = 1, (provided with the Keysight Infiniium oscilloscope).
•
Mouse, quantity = 1, (provided with the Keysight Infiniium oscilloscope).
•
Precision 3.5 mm BNC to SMA male adapter, quantity = 2, (provided with the Keysight Infiniium
oscilloscope).
•
50 Ω phase-aligned BNC cable with SMA Male connector.
•
BNC shorting cap (provided with the Keysight Infiniium oscilloscope).
Figure 55
84
Accessories provided with the Keysight Infiniium Oscilloscope
Keysight eDP Compliance Testing Methods of Implementation
Calibrating the Infiniium Oscilloscope and Probe
6
Internal Calibration
To perform an internal diagnostic and calibration cycle for the oscilloscope (referred as Calibration
for the Keysight oscilloscope), follow these steps:
1
Set up the oscilloscope with the following steps:
a Connect the keyboard, mouse, and power cord to the rear of the oscilloscope.
b Plug in the power cord.
c Turn on the oscilloscope by pressing the power button located on the lower left of the front
panel.
d Allow the oscilloscope to warm up at least 30 minutes prior to starting the calibration
procedure in step 3 below.
2
Locate and prepare the accessories that will be required for the internal calibration:
a Locate the BNC shorting cap.
b Locate the BNC cable.
c Locate the two Keysight precision SMA/BNC adapters.
d Attach one SMA adapter to the other end of the calibration cable - hand tighten snugly.
e Attach another SMA adapter to the other end of the calibration cable - hand tighten snugly.
3
Referring to Figure 56 below, click Utilities > Calibration on the Infiniium Oscilloscope menu to
open the Calibration dialog box.
Figure 56
4
Accessing the Calibration dialog box
Referring to Figure 57 below, perform the following steps to start the calibration process:
a Uncheck the Cal Memory Protect checkbox.
b Click the Start button to begin the calibration.
c Follow the on-screen instructions.
Keysight eDP Compliance Testing Methods of Implementation
85
6
Calibrating the Infiniium Oscilloscope and Probe
Figure 57
Starting the calibration process
d During the calibration of channel 1, if you are prompted to perform a Time Scale Calibration,
select the Standard Cal and Defaul t Time Scale radio button in the Calibration Options dialog box,
as shown in Figure 58 below.
86
Keysight eDP Compliance Testing Methods of Implementation
Calibrating the Infiniium Oscilloscope and Probe
Figure 58
6
Calibration Options dialog box
e Click the OK button to continue calibration.
f
When the calibration procedure is complete, you will be prompted with a Calibration Complete
message window. Click the OK button to close this window.
g Confirm that the Vertical and Trigger Calibration Status for all Channels passed.
h Click the Close button to close the calibration window.
NOTE
i
The internal calibration is complete.
j
Read receiver below.
These steps do not need to be performed every time a test is run. However, if the ambient
temperature changes more than 5 degrees Celsius from the calibration temperature, this
calibration should be performed again. The delta between the calibration temperature and the
present operating temperature is shown in the Utilities > Calibration menu.
Keysight eDP Compliance Testing Methods of Implementation
87
6
88
Calibrating the Infiniium Oscilloscope and Probe
Keysight eDP Compliance Testing Methods of Implementation
Index
Index
Numerics
P
80-bit PLTPAT Custom Pattern, 33
PLTPAT, 33
PRBS7, 33
Precondition, 34
C
Component Level Jitter, 27
R
D
required equipment for calibration, 84
Data-TIE, 27
Differential Tests, 21
Dual Dirac Technique, 27
S
E
Equations
Common Mode Noise RMS Voltage, 81
Common Mode Noise Voltage, 81
Differential Voltage Level, 41
Differential Voltage Level Ratio, 45, 47
Inter Lane Skew, 68, 69
Intra Pair Skew, 78, 79
Main Link Frequency, 71
Non ISI Jitter, 25
Peak to Peak Differential Voltage, 35
Peak to Peak Non Transition bit
Voltage, 33
Peak to Peak Transition bit Voltage, 33
Pre-Emphasis Level, 52, 53
Pre-Emphasis Level Delta, 58, 59
SSC Modulation Deviation, 75, 76
SSC Range, 75, 76
Threshold Voltage for Data False
Signal, 78
Threshold Voltage for Data True Signal, 78
Total Jitter, 27
Eye Diagram Test, 22
Single-ended Tests, 77
System Jitter, 27
T
TIE, 31
Total Jitter Test, 27
Transition Voltage, 34
I
InfiniiScan Generic Serial trigger, 79
internal calibration, 85
M
Main Link Test
SSC Disabled, 70
SSC Enabled, 70
N
Non, 25
Non ISI Jitter Test, 25
Non-transition voltage, 34
Keysight eDP Compliance Testing Methods of Implementation
1
Index
2
Keysight eDP Compliance Testing Methods of Implementation
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