Fujitsu MB15F74UV Data Sheet

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Fujitsu MB15F74UV Data Sheet | Manualzz

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

Dual S

erial Input

PLL Frequency

Synthesizer

MB15F74UV

DS04-21381-1E

DESCRIPTION

The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the

2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The serial data format is the same as MB15F74UL. Fast locking is achieved for adopting the new circuit.

MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50

%

comparing with the former BCC20 (for dual PLL) .

FEATURES

• High frequency operation : RF synthesizer : 4000 MHz Max

: IF synthesizer : 2000 MHz Max

• Low power supply voltage : V

CC

=

2.7 V to 3.6 V

• Ultra low power supply current : I

CC

=

9.0 mA Typ

(V

CC

=

3.0 V, Ta

= +

25

°

C, SW

IF

=

SW

RF

=

0 in IF/RF locking state)

(Continued)

PACKAGE

18-pin plastic BCC

(LCC-18P-M05)

2

MB15F74UV

(Continued)

• Direct power saving function : Power supply current in power saving mode

Typ 0.1

µ

A (V

CC

=

3.0 V, Ta

= +

25

°

C at 1 system)

10

µ

A (V

CC

=

3.0 V at 1 system)

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ

• Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65)

• 23 bit shift register

• Serial input binary 14-bit programmable reference divider : R

=

3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter : 3 to 2,047

• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit

• On-chip phase control for phase comparator

• On-chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking

• Operating temperature : Ta

= −

40

°

C to

+

85

°

C

• Serial data format compatible with MB15F74UL

• Ultra small package BCC18 (2.4 mm

×

2.7 mm

×

0.45 mm)

PIN ASSIGNMENTS

TOP VIEW

GND fin

IF

Xfin

IF

GND

IF

V

CCIF

D

OIF

Clock

OSC

IN Data

1

4

5

2

3

6

18 17 16 15

14

13

12

11

7 8 9 10

PS

IF

PS

RF

LD/fout

LE fin

RF

Xfin

RF

GND

RF

V

CCRF

D

ORF

(LCC-18P-M05)

MB15F74UV

PIN DESCRIPTION

Pin no.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Pin name

I/O Descriptions

GND

Ground pin for OSC input buffer and the shift register circuit.

fin

IF

I

Prescaler input pin for the IF-PLL.

Connection to an external VCO should be AC coupling.

Xfin

IF

I

Prescaler complimentary input for the IF-PLL section.

This pin should be grounded via a capacitor.

GND

IF

Ground pin for the IF-PLL section.

V

CCIF

Power supply voltage input pin for the IF-PLL section, the shift register and the oscillator input buffer.

Do

IF

O Charge pump output for the IF-PLL section.

PS

IF

I

LD/fout O

Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.)

PS

IF

=

“H” ; Normal mode/PS

IF

=

“L” ; Power saving mode

Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The output signal is selected by LDS bit in a serial data.

LDS bit

=

“H” ; outputs fout signal/LDS bit

=

“L” ; outputs LD signal

PS

Xfin

RF

RF

I

I

Power saving mode control for the RF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited. )

PS

RF

=

“H” ; Normal mode/PS

RF

=

“L” ; Power saving mode

Do

RF

O Charge pump output for the RF-PLL section.

V

CCRF

Power supply voltage input pin for the RF-PLL section.

GND

RF

Ground pin for the RF-PLL section

Prescaler complimentary input pin for the RF-PLL section.

This pin should be grounded via a capacitor.

fin

RF

LE

Data

Clock

OSC

IN

I

I

I

I

I

Prescaler input pin for the RF-PLL.

Connection to an external VCO should be via AC coupling.

Load enable signal input pin (with the schmitt trigger circuit)

When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data.

Serial data input pin (with the schmitt trigger circuit)

Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,

RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.

Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)

One bit data is shifted into the shift register on a rising edge of the clock.

The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor.

3

4

MB15F74UV

BLOCK DIAGRAM

V

CCIF

GND

IF

(5) (4)

PS fin

Xfin

OSC

IF

IF

IF

IN

(7)

(2)

(3)

(18)

Intermittent mode control

(IF-PLL)

Prescaler

(IF-PLL)

(32/33, 64/65)

OR fin

RF

(14)

Xfin

RF

Prescaler

(RF-PLL)

(64/65, 128/129)

PS

RF

(9)

Intermittent mode control

(RF-PLL)

3 bit latch 7 bit latch 11 bit latch

Binary 7-bit swallow counter

(IF-PLL)

Binary 11-bit programmable counter (IF-PLL) fp

IF

Phase comp.

(IF-PLL)

Fast lock

Tuning

Charge pump

(IF-PLL)

Current

Switch

(6) Do

IF

Lock Det.

(IF-PLL)

LD

IF

2 bit latch

T1 T2

14 bit latch

Binary 14-bit programmable ref.

counter(IF-PLL)

1 bit latch

C/P setting counter fr

IF

T1 T2

2 bit latch fr

RF

Binary 14-bit programmable ref.

counter (RF-PLL))

14 bit latch

C/P setting counter

1 bit latch

AND

Fast lock

Tuning

Selector

LD fr

IF fr

RF fp

IF fp

RF

(8) LD fout

/ fp

RF

LD

RF

Lock Det.

(RF-PLL)

3 bit latch

Binary 7-bit swallow counter

(RF-PLL)

Binary 11-bit programmable counter (RF-PLL) fp

RF

Phase comp.

(RF-PLL)

7 bit latch 11 bit latch

Charge pump

(RF-PLL)

Current

Switch

(10) Do

RF

LE (15)

Data (16)

Clock (17)

Schmitt trigger circuit

Schmitt trigger circuit

Schmitt trigger circuit

Latch selector

C

N

1

C

N

2

23-bit shift register

(1)

GND

(11) (12)

V

CCRF

GND

RF

MB15F74UV

ABSOLUTE MAXIMUM RATINGS

Power supply voltage

Input voltage

Rating

Parameter

LD/fout

Do

IF

, Do

RF

Symbol

V

CC

V

I

V

O

V

DO

Tstg

Min

0.5

0.5

GND

Max

4.0

V

CC

+

0.5

V

CC

Unit

V

V

V

Output voltage

Storage temperature

GND

55

+

V

CC

125

V

°

C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

Value

Parameter Symbol Unit Remarks

Min Typ Max

Power supply voltage

Input voltage

Operating temperature

V

CC

V

Ta

I

2.7

GND

40

3.0

3.6

V

+

CC

85

°

V

V

C

V

CCRF

=

V

CCIF

Note :

V

CCRF

and V

CCIF

must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF

and V

CCIF

to keep them equal.

It is recommended that the non-use PLL is controlled by power saving function.

Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry

has been improved in electrostatic protection, observe the following precautions when handling the device.

When storing and transporting the device, put it in a conductive case.

Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench.

Before fitting the device into or removing it from the socket, turn the power supply off.

When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

5

MB15F74UV

6

* ■

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition

(V

CC

=

2.7 V to 3.6 V, Ta

= −

40

°

C to

+

85

°

C)

Value

Unit

Min Typ Max

Power supply current

Power saving current

I

I

CCIF

CCRF

*

*

1

1 fin

IF

=

2000 MHz

V

CCIF

=

3.0 V fin

RF

=

2500 MHz

V

CCRF

=

3.0 V

I

PSIF

PS

IF

=

PS

RF

=

“L”

I

PSRF

PS

IF

=

PS

RF

=

“L” fin

IF

IF PLL fin

IF

* 3

Operating frequency fin

RF

* 3 fin

RF

RF PLL

Input sensitivity

OSC fin

IF fin

RF

Input available voltage OSC

IN

IN f

OSC

Pfin

IF

IF PLL, 50

system

Pfin

RF

RF PLL, 50

system

V

OSC

V

IH

Schmitt trigger input “H” level input voltage

“L” level input voltage

Data

LE

Clock

V

IL

“H” level input voltage

“L” level input voltage

PS

PS

IF

RF

“H” level input current

“L” level input current

Data

LE

Clock

PS

“H” level output voltage LD/

“L” level output voltage fout

“H” level output voltage Do

IF

“L” level output voltage

Do

RF

High impedance cutoff current

Do

IF

Do

RF

“H” level output current LD/

“L” level output current fout

“H” level output current

“L” level output current

Do

IF

* 8

Do

RF

Do

IF

* 8

Do

RF

V

I

IH

I

V

IL

IH

IL

*

*

4

4

Schmitt trigger input

I

V

OH

V

CC

=

3.0 V, I

OH

= −

1 mA

V

OL

V

CC

=

3.0 V, I

OL

=

1 mA

V

DOH

V

CC

=

3.0 V, I

DOH

= −

0.5 mA

I

V

DOL

V

CC

=

3.0 V, I

DOL

=

0.5 mA

I

OFF

V

CC

=

3.0 V

V

OFF

=

0.5 V to V

CC

0.5 V

OH

I

OL

* 4 V

CC

=

3.0 V

V

CC

=

3.0 V

DOH

* 4

V

CC

=

3.0 V,

V

DOH

=

V

CC

/

2,

Ta

= +

25

°

C

CS bit

CS bit

=

=

“1”

“0”

I

DOL

V

CC

=

3.0 V,

V

DOL

=

V

CC

/

2,

Ta

= +

25

°

C

CS bit

CS bit

=

=

“1”

“0”

2.1

5.7

200

2000

3

15

10

0.5

0.7 V

CC

+

0.4

0.7 V

1.0

1.0

V

CC

0.4

V

CC

0.4

1.0

8.2

2.2

4.1

0.8

CC

2.5

6.5

0.1

0.1

* 2

1.0

* 2

6.0

1.5

6.0

1.5

3.2

8.4

10

10

2000

4000

40

+

2

+

2

1.5

0.3 V

CC

0.4

0.3 V

+

+

1.0

1.0

0.4

0.4

2.5

1.0

4.1

0.8

8.2

2.2

CC mA mA

µ

A

µ

A

MHz

MHz

MHz dBm dBm

V

P-P

V

V

V

V

µ

A

µ

A

V

V

V

V nA mA mA mA mA mA mA

(Continued)

MB15F74UV

(Continued)

(V

CC

=

2.7 V to 3.6 V, Ta

= −

40

°

C to

+

85

°

C)

Value

Parameter Symbol Condition

Charge pump current rate

I

DOL

/I

vs V

DOH vs Ta

DO

I

I

I

DOMT

DOVD

DOTA

*

*

*

5

6

7

V

DO

=

V

CC

/

2

0.5 V

V

DO

V

CC

0.5 V

40

°

C

Ta

85

°

C,

V

DO

=

V

CC

/

2

*1 : Conditions ; fosc

=

12.8 MHz, Ta

= +

25

°

C, SW

=

“0” in locking state.

*2 : V

CCIF

=

V

CCRF

=

3.0 V, fosc

=

12.8 MHz, Ta

= +

25

°

C, in power saving mode.

PS

IF

=

PS

RF

=

GND

V

IH

=

V

CC

, V

IL

=

GND (at CLK, Data, LE)

Min

Typ

3

10

5

Max

10

15

10

Unit

%

%

%

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.

*4 : The symbol “–” (minus) means the direction of current flow.

*5 : V

CC

=

3.0 V, Ta

= +

25

°

C (||I

3

|

|I

4

||)

/

[ (|I

3

|

+

|I

4

|)

/

2]

×

100 (

%

)

*6 : V

CC

=

3.0 V, Ta

= +

25

°

C [ (||I

2

|

|I

1

||)

/

2]

/

[ (|I

1

|

+

|I

2

|)

/

2]

×

100 (

%

) (Applied to both l

DOL

and l

DOH

)

*7 : V

CC

=

3.0 V, [||I

DO

( +

85

°

C) |

|I

DO

(

–40

°

C) ||

/

2]

/

[|I

DO

( +

85

°

C) |

+

|I

DO

(

–40

°

C) |

/

2]

×

100 (

%

) (Applied to both I

DOL

and I

DOH

)

*8 : When Charge pump current is measured, set LDS

=

“0” , T1

=

“0” and T2

=

“1”.

I

DOL

I

1

I

3

I

2

I

DOH

I

2

I

4

I

1

0.5

V

CC

/2 V

CC

0.5 V

CC

Charge pump output voltage (V)

7

8

MB15F74UV

FUNCTIONAL DESCRIPTION

1.

Pulse swallow function f

VCO

=

[ (P

×

N)

+

A]

×

f

OSC

÷

R f

VCO

: Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL)

N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A : Preset divide ratio of binary 7-bit swallow counter (0

A

127, A < N) f

OSC

: Reference oscillation frequency (OSC

IN

input frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2.

Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-

PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.

The serial data of binary data is entered through Data pin.

On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting.

CN1

CN2

The programmable reference counter for the IF-PLL

0

The programmable reference counter for the RF-PLL

1

0 0

The programmable counter and the swallow counter for the IF-PLL

0

1

The programmable counter and the swallow counter for the RF-PLL

1

1

(1) Shift Register Configuration

Programmable Reference Counter

(LSB) Data Flow (MSB)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X

CS : Charge pump current select bit

R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)

T1, T2 : LD/fout output setting bit

CN1, CN2 : Control bit

X : Dummy bits (Set “0” or “1”)

Note : Data input with MSB first.

MB15F74UV

• Programmable Counter

(LSB) Data Flow (MSB)

1 2 3

CN1 CN2 LDS

4

SW

IF

/

SW

RF

5

FC

IF

/

FC

RF

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)

LDS : LD/fout signal select bit

SW

IF

/SW

RF

: Divide ratio setting bit for the prescaler (IF : SW

IF

, RF : SW

RF

)

FC

IF

/FC

RF

: Phase control bit for the phase detector (IF : FC

IF

, RF : FC

RF

)

CN1, CN2 : Control bit

22 23

Note : Data input with MSB first.

(2) Data setting

• Binary 14 bit Programmable Reference Counter Data Setting

Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1

3

4

16383

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

1

1

1

0

1

1

0

1

Note : Divide ratio less than 3 is prohibited.

• Binary 11 bit Programmable Counter Data Setting

Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1

3 0 0 0 0 0 0 0 0 0 1 1

4

2047

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

0

1

0

1

Note : Divide ratio less than 3 is prohibited

• Binary 7 bit Swallow Counter Data Setting

Divide ratio A7 A6 A5 A4 A3 A2 A1

0 0 0 0 0 0 0 0

1

127

0

1

0

1

0

1

0

1

0

1

0

1

1

1

9

MB15F74UV

• Prescaler Data Setting

Divide ratio

Prescaler divide ratio IF-PLL

Prescaler divide ratio RF-PLL

• Charge Pump Current Setting

Current value

±

6.0 mA

±

1.5 mA

CS

1

0

SW

====

“1”

32/33

64/65

• LD / fout output Selectable Bit Setting

LD/fout pin state LDS

0 fout output

LD output fr

IF fr

RF fp

IF fp

RF

1

1

0

0

1

1

SW

====

“0”

64/65

128/129

0

1

0

1

T1

0

1

1

• Phase Comparator Phase Switching Data Setting

FC

IF

,

RF

====

“1”

Phase comparator input

Do

IF

, Do

RF fr

>

fp fr

<

fp fr

=

fp

Z : High-impedance

H

L

Z

FC

IF

,

RF

====

“0”

Do

IF

, Do

RF

Depending upon the VCO and LPF polarity, FC bit should be set.

L

H

Z

1

1

0

0

T2

0

0

1

High

(1) VCO polarity FC

=

“1”

(2) VCO polarity FC

=

“0”

VCO Output

Frequency

LPF Output voltage

10

Note : Give attention to the polarity for using active type LPF.

(1)

(2)

Max

MB15F74UV

3.

Power Saving Mode (Intermittent Mode Control Circuit)

Status PS pin

Normal mode

Power saving mode

H

L

The intermittent mode control circuit reduces the PLL power consumption.

By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value.

The phase detector output, Do, becomes high impedance.

For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.

Setting the PS pin high, releases the power saving mode, and the device works normally.

The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.

When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup time.

To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation.

Notes :

When power (VCC) is first applied, the device must be in standby mode.

PS pin must be set “L” at Power-ON.

V

CC

Clock

Data

LE

PS

OFF t

V

1

µ s

ON t

PS

100 ns

(1) (2) (3)

(1) PS

=

L (power saving mode) at Power-ON

(2) Set serial data at least 1

µ s after the power supply becomes stable (V

CC

2.2 V) .

(3) Release power saving mode (PS

IF

, PS

RF

: “L”

“H”) at least 100 ns later after setting serial data.

11

12

MB15F74UV

4.

Serial Data Data Input Timing

Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.

Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing.

1st data 2nd data

Control bit Invalid data

Data MSB LSB

Clock

LE t

7 t

1 t

2 t

3 t

6 t

4 t

5

Parameter Min t

1 t

2

20

20 t

3 t

4

30

30

Typ

Max

Unit ns ns ns ns

Parameter t t

5 t

6

7

Note : LE should be “L” when the data is transferred into the shift register.

Min Typ Max

100

20

100

Unit ns ns ns

MB15F74UV

PHASE COMPARATOR OUTPUT WAVEFORM

fr IF

/

RF fp

IF

/

RF t

WU t

WL

LD

(FC bit

=

“1”)

D o

IF

/

RF

Z

( FC bit = “0” )

D o IF

/

RF

Z

H

L

H

L

• LD Output Logic

IF-PLL section

Locking state/Power saving state

Locking state/Power saving state

Unlocking state

Unlocking state

RF-PLL section

Locking state/Power saving state

Unlocking state

Locking state/Power saving state

Unlocking state

LD output

H

L

L

L

Notes :

Phase error detection range

= −

2

π

to

+

2

π

Pulses on Do

IF/RF

signals during locking state are output to prevent dead zone.

LD output becomes low when phase error is t

WU

or more.

LD output becomes high when phase error is t

WL

or less and continues to be so for three cycles or more.

t

WU

and t

WL

depend on OSC

IN

input frequency as follows.

t

WU

2/fosc : e.g. t

WU

156.3 ns when fosc

=

12.8 MHz t

WU

4/fosc : e.g. t

WL

312.5 ns when fosc

=

12.8 MHz

13

14

MB15F74UV

TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC

IN

)

S.G.

1000 pF

S.G.

50

S.G.

1000 pF

50

OSC

IN

Controller

(divide ratio setting)

Clock Data LE

GND

1000 pF

50

V

CCIF

1000 pF fin

IF

Xfin

IF

GND

IF

V

CCIF

Do

IF

3

4

5

6

1

2

18

PS

IF

7

17

MB15F74UV

8

16

9

LD/ fout

PS

RF

13

12

11

10

15

14 fin

RF

Xfin

RF

1000 pF

GND

RF

V

CCRF

0.1

µ

F

V

CCRF

Do

RF

0.1

µ

F

Oscilloscope

MB15F74UV

TYPICAL CHARACTERISTICS

1.

fin input sensitivity

RF-PLL input sensitivity vs. Input frequency

10

0

10

20

30

40

50

1500

Catalog guaranteed range

2000 2500 3000 fin

RF

[MHz]

3500 4000 4500

IF-PLL input sensitivity vs. Input frequency

5000

Ta = +25 C

V

CC

=

2.7 V

V

CC

=

3.0 V

V

CC

=

3.6 V

SPEC

10

0

10

20

30

40

50

0

Catalog guaranteed range

500 1000 1500 fin

IF

[MHz]

2000 2500 3000

Ta = +25 C

V

CC

=

2.7 V

V

CC

=

3.0 V

V

CC

=

3.6 V

SPEC

15

16

MB15F74UV

2.

OSC

IN

input sensitivity

Input sensitivity vs. Input frequency

10

0

10

20

30

40

50

0

Catalog guaranteed range

20 40 60 80 100

Input frequency f

OSC

(MHz)

120 140 160

V

CC

=

2.7 V

V

CC

=

3.0 V

V

CC

=

3.6 V

SPEC

3.

RF/IF-PLL Do output current

• 1.5 mA mode

I

DO

V

DO

2.50

2.00

1.50

1.00

0.50

0.00

0.50

1.00

1.50

2.00

2.50

0.0

V

CC

=

2.7 V, Ta

=

+25 C

0.5

1.0

1.5

2.0

2.5

Charge pump output voltage V

DO

(V)

3.0

MB15F74UV

• 6.0 mA mode

I

DO

V

DO

8.00

6.00

4.00

2.00

0.00

2.00

4.00

6.00

8.00

0.0

V

CC

=

2.7 V, Ta

=

+25 C

0.5

1.0

1.5

2.0

2.5

Charge pump output voltage V

DO

(V)

3.0

17

18

MB15F74UV

4.

fin input impedance fin

IF input impedance

4

:

30.266

Ω −

102.92

773.21 fF

2 000.000 000 MHz

1

:

494.28

874.84

200 MHz

2

:

58.094

216.47

1 GHz

3

:

39.773

148

1.5 GHz

1

4

3

2

START 100.000 000 MHz STOP 2 000.000 000 MHz fin

RF input impedance

4

:

20.93

Ω −

39.352

1.0111 pF

4 000.000 000 MHz

1

:

2

:

3

:

37.563

109.96

2 GHz

26.125

71.227

3 GHz

22.848

54.025

3.5 GHz

START 2 000.000 000 MHz

4

1

3 2

STOP 4 000.000 000 MHz

5.

OSC

IN

input impedance

OSC

IN input impedance

4

:

278.69

Ω −

1.0537 k

3.7761 pF

40.000 000 MHz

1

:

2.25 k

2.2373 k

10 MHz

2

:

881.62

1.8299 k

20 MHz

4

3

:

448.75

1.353 k

30 MHz

MB15F74UV

START 3.000 000 MHz STOP 40.000 000 MHz

19

MB15F74UV

REFERENCE INFORMATION

(

for Lock

-

up Time

,

Phase Noise and Reference Leakage

)

S.G.

Test Circuit

OSC

IN

Do LPF f

VCO

=

2113.6 MHz

K

V

=

50 MHz/V fr

=

50 kHz f

OSC

=

19.2 MHz

LPF fin

V

CC

=

3.0 V

Ta

= +

25

°

C

CP : 6 mA mode

Spectrum

Analyzer

VCO

0.01 F

7.5 k

1.6 k

0.1 F

To VCO

3300 pF

• PLL Reference Leakage

ATTEN 10 dB

RL 0 dBm

VAVG 16

10 dB/

MKR

80.83 dB

50.0 kHz

MKR

50.0 kHz

80.83 dB

20

• PLL Phase Noise

CENTER 2.1136000 GHz

RBW 1.0 kHz VBW 1.0 kHz

SPAN 200.0 kHz

SWP 500 ms

ATTEN 10 dB

RL 0 dBm

VAVG 16

10 dB/

MKR

65.34 dB/Hz

1.00 kHz

MKR

1.00 kHz

65.34 dB/Hz

CENTER 2.11360000 GHz

RBW 30 Hz VBW 30 Hz

SPAN 10.00 kHz

SWP 1.92 s

(Continued)

(Continued)

MB15F74UV

PLL Lock Up time

2113.6 MHz

2173.6 MHz within

±

1 kHz

L ch

H ch 1.47 ms

A Mkr x: 439.99764

µ s y: 50.0009 MHz

2.173604000 GHz

2.173600000 GHz

2.173596000 GHz

-500

µ s 2.000 ms

500

µ s/div

PLL Lock Up time

2173.6 MHz

2113.6 MHz within

±

1 kHz

H ch

L ch 1.56 ms

A Mkr x: 400.00146

µ s y:

50.0013 MHz

2.113604000 GHz

4.500 ms

2.113600000 GHz

2.113596000 GHz

-500

µ s

2.000 ms

500

µ s/div

4.500 ms

21

22

MB15F74UV

APPLICATION EXAMPLE

TCXO

1000 pF

Controller

(divide ratio setting)

OSC

IN

Clock Data LE

OUTPUT

VCO

GND

1000 pF

1000 pF fin

IF

Xfin

IF

LPF

GND

IF

V

CCIF

5

6

3

4

1

2

18

7

17

MB15F74UV

8

16

9

11

10

13

12

15

14

Do

IF

V

CCIF

PS

IF

LD/ fout

PS

RF

0.1

µ

F fin

RF

1000 pF

Xfin

RF

GND

RF

V

CCRF

Do

RF

1000 pF

OUTPUT

VCO

V

CCRF

0.1

µ

F

LPF

Lock Detect

Note : Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up registor to prevent oscillation when open-circuit in the input) .

MB15F74UV

USAGE PRECAUTIONS

(1) V

CCRF

and V

CCIF

must be equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF

and V

CCIF

to keep them

equal. It is recommended that the non-use PLL is controlled by power saving function.

(2) To protect against damage by electrostatic discharge, note the following handling precautions :

Store and transport devices in conductive containers.

Use properly grounded workstations, tools, and equipment.

Turn off power before inserting or removing this device into or from a socket.

Protect leads with conductive sheet, when transporting a board mounted device

ORDERING INFORMATION

Part number

MB15F74UVPVB

Package

18-pin plastic BCC

(LCC-18P-M05)

Remarks

23

24

MB15F74UV

PACKAGE DIMENSION

18-pin plastic BCC

(LCC-18P-M05)

2.70

± 0.10

(.106

± .004)

15 10

1

INDEX AREA

0.05(.002)

6

2.40

(.094

±

±

0.10

.004)

0.45

± 0.05

(.018

± .002)

(Mount height)

10

2.31(.090)

TYP

0.45(.018)

TYP.

15

0.075

± 0.025

(.003

± .001)

(Stand off)

2.01(.079)

TYP

0.45(.018)

TYP.

6

"C"

"A"

"B"

0.90(.035)

REF

1.90(.075)

REF

1.35(.053)

REF

2.28(.090)

REF

1

Details of "A" part

0.14(.006)

MIN.

0.25

± 0.06

(.010

± .002)

Details of "B" part

C0.10(.004)

0.36

± 0.06

(.014

± .002)

Details of "C" part

0.36

± 0.06

(.014

± .002)

0.25

± 0.06

(.010

± .002)

0.28

± 0.06

(.011

± .002)

0.28

± 0.06

(.011

± .002)

C

2003 FUJITSU LIMITED C18058S-c-1-1

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

MB15F74UV

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F0401

FUJITSU LIMITED Printed in Japan

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