Fujitsu MB39A104 User's Manual
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27231-3E
ASSP For Power Management Applications
(General Purpose DC/DC Converter)
2-ch DC/DC Converter IC
with Overcurrent Protection
MB39A104
■ DESCRIPTION
The MB39A104 is a 2-channel DC/DC converter IC using pulse width modulation (PWM), incorporating an
overcurrent protection circuit (requiring no current sense resistor). This IC is ideal for down conversion.
Operating at high frequency reduces the value of coil.
This is ideal for built-in power supply such as LCD monitors and ADSL.
This product is covered by US Patent Number 6,147,477.
■ FEATURES
•
•
•
•
•
•
•
•
Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor)
Power supply voltage range : 7 V to 19 V
Reference voltage : 5.0 V ± 1 %
Error amplifier threshold voltage : 1.24 V ± 1 %
High-frequency operation capability : 1.5 MHz (Max)
Built-in standby function: 0 µA (Typ)
Built-in soft-start circuit independent of loads
Built-in totem-pole type output for Pch MOS FET
■ PACKAGE
24-pin plastic SSOP
(FPT-24P-M03)
MB39A104
■ PIN ASSIGNMENTS
(TOP VIEW)
VCCO : 1
24 : CTL
VH : 2
23 : GNDO
OUT1 : 3
22 : OUT2
VS1 : 4
21 : VS2
ILIM1 : 5
20 : ILIM2
DTC1 : 6
19 : DTC2
VCC : 7
18 : GND
CSCP : 8
17 : VREF
FB1 : 9
16 : FB2
−INE1 : 10
15 : −INE2
CS1 : 11
14 : CS2
RT : 12
13 : CT
(FPT-24P-M03)
2
MB39A104
■ PIN DESCRIPTION
Pin No.
Symbol
I/O
Descriptions
1
VCCO

Output circuit power supply terminal (Connect to same potential as VCC pin.)
2
VH
O
Power supply terminal for FET drive circuit (VH = VCC − 5 V)
3
OUT1
O
External Pch MOS FET gate drive terminal
4
VS1
I
Overcurrent protection circuit input terminal
5
ILIM1
I
Overcurrent protection circuit detection resistor connection terminal. Set
overcurrent detection reference voltage depending on external resistor and
internal current resource (110 µA at RT = 24 kΩ)
6
DTC1
I
PWM comparator block (PWM) input terminal. Compares the lowest voltage
among FB1 and DTC terminals with triangular wave and controls output.
7
VCC

Power supply terminal for reference power supply and control circuit
(Connect to same potential as the VCCO terminal)
8
CSCP

Timer-latch short-circuit protection capacitor connection terminal
9
FB1
O
Error amplifier (Error Amp 1) output terminal
10
−INE1
I
Error amplifier (Error Amp 1) inverted input terminal
11
CS1

Soft-start capacitor connection terminal
12
RT

Triangular wave oscillation frequency setting resistor connection terminal
13
CT

Triangular wave oscillation frequency setting capacitor connection terminal
14
CS2

Soft-start capacitor connection terminal
15
−INE2
I
Error amplifier (Error Amp 2) inverted input terminal
16
FB2
O
Error amplifier (Error Amp 2) output terminal
17
VREF
O
Reference voltage output terminal
18
GND

Output circuit ground terminal (Connect to same potential as GNDO
terminal.)
19
DTC2
I
PWM comparator block (PWM) input terminal. Compares the lowest voltage
among FB2 and DTC terminals with triangular wave and controls output.
20
ILIM2
I
Overcurrent protection circit detection resistor connection terminal. Set
overcurrent detection reference voltage depending on external resistor and
internal current resource (110 µA at RT = 24 kΩ)
21
VS2
I
Overcurrent protection circuit input terminal
22
OUT2
O
External Pch MOS FET gate drive terminal
23
GNDO

Output circuit ground terminal (Connect to same potential as GND terminal.)
24
CTL
I
Power supply control terminal. Setting the CTL terminal at “L” level places IC
in the standby mode.
3
MB39A104
■ BLOCK DIAGRAM
−INE1 10
VREF
10 µA
CS1 11
PWM
+ Comp.1
+
−
1.24 V
1 VCCO
CH1
L priority
Error
− Amp1
+
+
Drive1
Pch
3 OUT1
L priority
FB1 9
IO = 200 mA
at VCCO = 12 V
Current
Protection
Logic
−
4 VS1
+
5 ILIM1
DTC1 6
−INE2 15
VREF
10 µA
CS2 14
1.24 V
CH2
L priority
Error
− Amp2
+
+
PWM
+ Comp.2
+
−
Drive2
Pch
FB2 16
IO = 200 mA
at VCCO = 12 V
DTC2 19
Current
Protection
Logic
H priority
H: at SCP
SCP
Comp. +
+
−
(3.1 V)
H: at OCP
SCP
Logic
CSCP 8
20 ILIM2
VCC − 5 V
VH
Bias
Voltage
Error Amp Reference
bias
2 VH
Accuracy
±1%
17
VREF
7 VCC
1.24 V
VREF
Power
VR1 ON/OFF
CTL
5.0 V
12 13
RT CT
21 VS2
Error Amp Power Supply
H:UVLO
release
OSC
−
+
23 GNDO
2.5 V
1.5 V
UVLO
4
22 OUT2
L priority
18
GND
24 CTL
MB39A104
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Power supply voltage
VCC
Output current
Condition
Rating
Unit
Min
Max
VCC, VCCO terminal

20
V
IO
OUT1, OUT2 terminal

60
mA
Output peak current
IOP
Duty ≤ 5% (t = 1/fOSC×Duty)

700
mA
Power dissipation
PD
Ta ≤ +25 °C

740*
mW
−55
+125
°C
Storage temperature

TSTG
* : The packages are mounted on the epoxy board (10 cm × 10 cm).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Power supply voltage
VCC
VCC, VCCO terminal
7
12
19
V
Reference voltage output current
IREF
VREF terminal
−1

0
mA
VH output current
IVH
VH terminal
0

30
mA
VINE
−INE1, −INE2 terminal
0

VCC − 0.9
V
VDTC
DTC1, DTC2 terminal
0

VCC − 0.9
V
VCTL
CTL terminal
0

19
V
−45

+45
mA
Input voltage
Control input voltage
Output current
IO
OUT1, OUT2 terminal
Output Peak current
IOP
Duty ≤ 5% (t = 1/fOSC×Duty)
−450

+450
mA
Oscillation frequency
fOSC
Overcurrent detection
by ON resistance of FET
100
500
1000
kHz
*
100
500
1500
kHz
Timing capacitor
CT

39
100
560
pF
Timing resistor
RT

11
24
130
kΩ
VH terminal capacitor
CVH
VH terminal

0.1
1.0
µF
Soft-start capacitor
CS
CS1, CS2 terminal

0.1
1.0
µF
Short-circuit detection capacitor
CSCP
CSCP terminal

0.1
1.0
µF
Reference voltage output
capacitor
CREF
VREF terminal

0.1
1.0
µF
−30
+25
+85
°C
Operating ambient temperature
Ta

* : See“ ■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY”.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB39A104
■ ELECTRICAL CHARACTERISTICS
(VCC = VCCO = 12 V, VREF = 0 mA, Ta = +25 °C)
7.Error amplifier
6.Soft2.Under
5.Triangular
4.Short-circuit 3.Short-circuit
bolck
start
voltage lockout
wave oscillator detection block detection block
[Error Amp1,
block
protection circuit
block [OSC]
[SCP Comp]
[SCP Logic]
Error Amp2] [CS1, CS2]
block [UVLO]
1.Reference
voltage
block [REF]
Parameter
Symbol
Pin No
Conditions
Output voltage
VREF
17
Ta = +25 °C
Output voltage
temperature
variation
∆VREF/
VREF
17
Input stability
Line
Load stability
Short-cuircuit
output current
Value
Unit
Min
Typ
Max
4.95
5.00
5.05
V
Ta = 0 °C to +85 °C

0.5*

%
17
VCC = 7 V to 19 V

3
10
mV
Load
17
VREF = 0 mA to −1 mA

1
10
mV
IOS
17
VREF = 1 V
−50
−25
−12
mA
VTLH
17
VREF =
2.6
2.8
3.0
V
VTHL
17
VREF =
2.4
2.6
2.8
V
Hysteresis
width
VH
17


0.2 *

V
Threshold
voltage
VTH
8

0.68
0.73
0.78
V
Input source
current
ICSCP
8

−1.4
−1.0
−0.6
µA
Reset voltage
VRST
17
2.4
2.6
2.8
V
Threshold
voltage
VTH
8

2.8
3.1
3.4
V
Oscillation
frequency
fOSC
13
CT = 100 pF, RT = 24 kΩ
450
500
550
kHz
∆fOSC/
fOSC
13
Ta = 0 °C to +85 °C

1*

%
Charge current
ICS
11, 14
CS1 = CS2 = 0 V
−14
−10
−6
µA
Threshold
voltage
VTH
9, 16
FB1 = FB2 = 2 V
1.227 1.240 1.253
V
Input bias
current
IB
10, 15
−INE1 = −INE2 = 0 V
−120
−30

nA
Voltage gain
AV
9, 16
DC

100*

dB
Threshold
voltage
Frequency
temperature
variation
VREF =
(Continued)
6
MB39A104
(Continued)
(VCC = VCCO = 12 V, VREF = 0 mA, Ta = +25 °C)
13.Control block
14.General
[CTL]
12.Output block
[Drive1, Drive2]
11.Bias 10.Overcurrent 9.PWM comparator
8.Error amplifier bolck
voltage protection circuit
block
[Error Amp1,
block
block
[PWM Comp.1,
Error Amp2]
[VH]
[OCP1, OCP2]
PWM Comp.2]
Parameter
Symbol
Pin No.
BW
9, 16
VOH
9, 16
VOL
9, 16
ISOURCE
9, 16
ISINK
Conditions
Value
Unit
Min
Typ
Max

1.6*

MHz

4.7
4.9

V


40
200
mV
FB1 = FB2 = 2 V

−2
−1
mA
9, 16
FB1 = FB2 = 2 V
150
200

µA
VT0
6, 19
Duty cycle = 0 %
1.4
1.5

V
VT100
6, 19
Duty cycle = Dtr

2.5
2.6
V
Input current
IDTC
6, 19
DTC1 = DTC2 = 0.4 V
−2.0
−0.6

µA
ILIM terminal input
current
ILIM
5, 20
RT = 24 kΩ, CT = 100 pF
99
110
121
µA
Offset voltage
VIO
5, 20


1*

mV
Output voltage
VH
2
Output source
current
ISOURCE
3, 22
OUT1 to OUT4 = 7 V,
Duty ≤ 5 %
(t = 1/fOSC×Duty)

−300

mA
Output sink current
ISINK
3, 22
OUT1 to OUT4 = 12 V,
Duty ≤ 5 %
(t = 1/fOSC×Duty)

350

mA
Output ON
resistor
ROH
3, 22
OUT1 = OUT2 = −45 mA

8.0
12.0
Ω
ROL
3, 22
OUT1 = OUT2 = 45 mA

6.5
9.7
Ω
VIH
24
IC Active mode
2

19
V
VIL
24
IC Standby mode
0

0.8
V
ICTLH
24
CTL = 5 V

50
100
µA
ICTLL
24
CTL = 0 V


1
µA
Standby current
ICCS
1, 17
CTL = 0 V

0
10
µA
Power supply
current
ICC
1, 17
CTL = 5 V

4.0
6.0
mA
Frequency
bandwidth
Output voltage
Output source
current
Output sink current
AV = 0 dB
Threshold voltage
CTL input voltage
Input current
VCC = VCCO = 7 V to 19 V VCC− VCC− VCC−
VH = 0 mA to 30 mA
5.5
5.0
4.5
V
*: Standard design value.
7
MB39A104
■ TYPICAL CHARACTERISTICS
Power Supply Current vs. Power Supply Voltage
10
Reference voltage VREF (V)
Ta = +25 °C
CTL = 5 V
8
6
4
2
Ta = +25 °C
CTL = 5 V
VREF = 0 mA
8
6
4
2
0
0
0
5
10
15
20
0
5
10
15
20
Power supply voltage VCC (V)
Power supply voltage VCC (V)
Reference Voltage vs. Ambient Temperature
Reference Voltage vs. Ambient Temperature
Reference voltage VREF (V)
10
2.0
Ta = +25 °C
VCC = 12 V
CTL = 5 V
8
Reference voltage ∆VREF (%)
Power supply current ICC (mA)
10
Reference Voltage vs. Power Supply Voltage
6
4
2
0
0
5
10
15
20
25
30
35
Ambient temperature Ta (°C)
VCC = 12 V
CTL = 5 V
VREF = 0 mA
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−40
−20
0
20
40
60
80
100
Ambient temperature Ta (°C)
CTL terminal current ICTL (µA)
500
10
Ta = +25 °C
9
VCC = 12 V
VREF = 0 mA 8
400
7
6
300
VREF
5
4
200
ICTL
3
2
100
1
0
0
5
10
15
Reference voltage VREF (V)
CTL terminal Current vs. CTL terminal Voltage
0
20
CTL terminal voltage VCTL (V)
(Continued)
8
MB39A104
Triangular Wave Oscillation Frequency
vs. Timing Capacitor
10000
Ta = +25 °C
VCC = 12 V
CTL = 5 V
1000
CT = 39 pF
CT = 560 pF
100
CT = 220 pF
CT = 100 pF
10000
Triangular wave oscillattion
frequency fOSC (kHz)
Triangular wave oscillation
frequency fOSC (kHz)
Triangular Wave Oscillation Frequency
vs. Timing Resistor
Ta = +25 °C
VCC = 12 V
CTL = 5 V
1000
RT = 11 kΩ
100
RT = 130 kΩ
10
10
1
10
100
10
1000
100
Timing resistor RT (kΩ)
3.2
Ta = +25 °C
VCC = 12 V
CTL = 5 V
RT = 47 kΩ
3.0
2.8
Upper
2.6
2.4
2.2
2.0
1.8
Lower
1.6
1.4
1.2
0
200
400
600
VCC = 12 V
3.0 CTL = 5 V
2.8 RT = 24 kΩ
CT = 100 pF
2.6
2.2
2.0
1.8
Lower
1.6
1.4
1.2
−40
800 1000 1200 1400 1600
540
520
500
480
460
−20
0
20
40
60
80
Ambient temperature Ta ( °C)
100
0
20
40
60
80
100
Triangular Wave Oscillation Frequency
vs. Power supply voltage
Triangular wave oscillation
frequency fOSC (kHz)
VCC = 12 V
CTL = 5 V
RT = 24 kΩ
CT = 100 pF
−20
Ambient temperature Ta ( °C)
Triangular Wave Oscillation Frequency
vs. Ambient Temperature
560
Upper
2.4
Triangular wave oscillation frequency fOSC (kHz)
440
−40
10000
Triangular Wave Upper and Lower Limit Voltage
vs. Ambient Temperature
Triangular wave upper and
lower limit voltage VCT (V)
Triangular wave upper and
lower limit voltage VCT (V)
3.2
1000
Timing capacitor CT (pF)
Triangular Wave Upper and Lower Limit Voltage
vs. Triangular Wave Oscillation Frequency
Triangular wave oscillation
frequency fOSC (kHz)
RT = 24 kΩ
RT = 68 kΩ
560
Ta = +25 °C
CTL = 5 V
RT = 24 kΩ
CT = 100 pF
540
520
500
480
460
440
0
5
10
15
20
Power supply voltage VCC (V)
(Continued)
9
MB39A104
(Continued)
Error Amplifier, Gain, Phase vs. Frequency
Ta = +25 °C
VCC = 12 V 180
40
ϕ
90
Phase φ (deg)
20
Gain AV (dB)
240 kΩ
AV
30
10
0
0
−10
−20
−90
−30
−180
100
1k
10 k
100 k
1M
10 M
Frequency f (Hz)
Power Dissipation vs. Ambient Temperature
Power dissipation PD (mW)
1000
10
+
IN
10 kΩ
2.4 kΩ
(15)
10
−
11
(14)
+
+
1.24 V
−40
800
740
600
400
200
0
−40
10 kΩ
1 µF
−20
0
20
40
60
Ambient temperature Ta ( °C)
80
100
9
(16)
OUT
Error Amp1
(Error Amp2)
MB39A104
■ FUNCTIONS
1. DC/DC Converter Functions
(1) Reference voltage block (REF)
The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V Typ) from the
voltage supplied from the power supply terminal (pin 7). The voltage is used as the reference voltage for the
IC’s internal circuitry.
The reference voltage can supply a load current of up to 1 mA to an external device through the VREF terminal
(pin 17).
(2) Triangular-wave oscillator block (OSC)
The triangular wave oscillator incorporates a timing capacitor and a timing resistor connected respectively to
the CT terminal (pin 13) and RT terminal (pin 12) to generate triangular oscillation waveform amplitude of 1.5 V
to 2.5 V.
The triangular waveforms are input to the PWM comparator in the IC.
(3) Error amplifier block (Error Amp1, Error Amp2)
The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. In addition,
an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to
inverted input terminal of the error amplifier, enabling stable phase compensation to the system.
Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the
CS1 terminal (pin 11) and CS2 terminal (pin 14) which are the non-inverted input terminal for Error Amp. The
use of Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that
is independent of the output load on the DC/DC converter.
(4) PWM comparator block (PWM Comp.)
The PWM comparator is a voltage-to-pulse width modulator that controls the output duty depending on the input/
output voltage.
The comparator keeps output transistor on while the error amplifier output voltage remain higher than the
triangular wave voltage.
(5) Output block
The output block is in the totem pole configuration, capable of driving an external P-channel MOS FET.
(6) Bias voltage block (VH)
This bias voltage circuit outputs VCC − 5 V(Typ) as minimum potential of the output circuit. In standby mode, this
circuit outputs the potential equal to VCC.
11
MB39A104
2. Control Function
When CTL terminal (pin 24) is “L” level, IC becomes the standby mode. The power supply current is 10 µA (Max)
at the standby mode.
On/Off Setting Conditions
CTL
Power
L
OFF (Standby)
H
ON (Operating)
3. Protective Functions
(1) Timer-latch overcurrent protection circuit block (OCP)
The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an
overcurrent flows, the circuit detects the increase in the voltage between the FET’s drain and source using the
external FET ON resistor, actuates the timer circuit, and starts charging the capacitor CSCP con-nected to the
CSCP terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, latch is set
and OUT terminlas (pin 3,22) of each channel are fixed at “H” level. And the circuit sets the latch to turn off the
external FET. The detection current value can be set by resistor RLIM1 connected between the FET’s drain and
the ILIM1 terminal (pin 5) and resistor RLIM2 connected between the drain and the ILIM2 terminal (pin 20).
Changing connection enables to detect overcurrent at current sense resistor.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (See “1. Setting TimerLatch Overcurrent Protection Detection Current” in “■ABOUT TIMER-LATCH PROTECTION CIRCUIT”.)
(2) Timer-latch short-circuit protection circuit (SCP Logic, SCP Comp.)
The short-circuit detection comparator (SCP Comp.) detects the output voltage level of Error Amp, and if the
error amp output voltage of any channel falls below the short-circuit detection voltage (3.1 V Typ), the timer
circuits are actuated to start charging the external capacitor CSCP connected to the CSCP terminal (pin 8).
When the capacitor voltage reaches about 0.73 V, the circuit is turned off the output transistor and sets the dead
time to 100 %.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 24) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (See “2. Setting Time
Constant for Timer-Latch Short-Circuit Protection Circuit” in “■ABOUT TIMER-LATCH PROTECTION CIRCUIT”.)
(3) Under voltage lockout protection circuit (UVLO)
The transient state or a momentary decrease in supply voltage, which occurs when the power supply is turned
on, may cause the IC to malfunction, resulting in breakdown or degradation of the system. To prevent such
malfunctions, under voltage lockout protection circuit detects a decrease in internal reference voltage with respect
to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the
CSCP terminal (pin 8) at the “L” level.
The circuit restores the output transistor to normal when the supply voltage reaches the threshold voltage of the
undervoltage lockout protection circuit.
(4) Protection circuit operating function table
This table refers to output condition when protection circuit is operating.
Operating circuit
CS1
CS2
12
OUT1
OUT2
Overcurrent protection circuit
L
L
H
H
Short-circuit protection circuit
L
L
H
H
Under-voltage lockout
L
L
H
H
MB39A104
■ SETTING THE OUTPUT VOLTAGE
• Output Voltage Setting Circuit
VO
R1
(−INE2) 15
−INE1
10
R2
(CS2) 14
CS1
11
Error Amp
−
+
+
VO (V) =
1.24
R2
(R1 + R2)
1.24 V
■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY
The triangular oscillation frequency is determined by the timing capacitor (CT) connected to the CT terminal (pin
13), and the timing resistor (RT) connected to the RT terminal (pin 12).
Moreover, it shifts more greatly than the caluculated values according to the constant of timing resistor (RT) when
the triangular wave oscillation frequency exceeds 1 MHz. Therefore, set it referring to “Triangular Wave Oscillation
Frequency vs. Timing Resistor” and “Triangular Wave Oscillation Frequency vs. Timing Capacitor” in “■ TYPICAL
CHARACTERISTICS”.
Triangular oscillation frequency : fOSC
fOSC (kHz) =:
1200000
CT (pF) •RT (kΩ)
13
MB39A104
■ SETTING THE SOFT-START AND DISCHARGE TIMES
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors
(CS1 and CS2) to the CS1 terminal (pin 11) for channel 1 and the CS2 terminal (pin 14) for channel 2, respectively.
When CTL terminal (pin 24) goes to “H” level and IC starts (VCC ≥ UVLO threshold voltage), the external softstart capacitors (CS1 and CS2) connected to CS1 and CS2 terminals are charged at 10 µA. The error amplifier
output (FB1 (pin 9) , FB2 (pin 16) ) is determined by comparison between the lower one of the potentials at two
non-inverted input terminals (1.24 V, CS1 terminal voltages) and the inverted input terminal voltage (−INE1 (pin
10) voltage, −INE2 (pin 15) voltage).
The FB1 (FB2) terminal voltage is decided for the soft-start period by the comparison between 1.24 V in an
internal reference voltage and the voltages of the CS1 (CS2) terminal. The DC/DC converter output voltage
rises in proportion to the CS1 (CS2) terminal voltage as the soft-start capacitor connected to the CS1 (CS2)
terminal is charged.
The soft-start time is obtained from the following formula:
Soft-start time: ts (time to output 100%)
ts (s) =: 0.124 × CS (µF)
CS1 (CS2) terminal voltage
=: 5 V
Error Amp block −INE1 (−INE2) voltage
=: 1.24 V
=: 0 V
t
Soft-start time (ts)
14
MB39A104
• Soft-Start Circuit
VREF
VO
10 µA
R1
−INE1
10
(−INE2)
15
R2
L priority
Error Amp
−
CH ON/OFF signal
L : ON, H : OFF
11
CS1
(CS2)
CS1
(CS2)
FB1
+
+
14
1.24 V
9
(FB2) 16
UVLO
15
MB39A104
■ TREATMENT WITHOUT USING CS TERMINAL
When not using the soft-start function, open the CS1 terminal (pin 11) and the CS2 terminal (pin 14) .
• Without Setting Soft-Start Time
“OPEN”
“OPEN”
11 CS1
16
CS2 14
MB39A104
■ ABOUT TIMER-LATCH PROTECTION CIRCUIT
1. Setting Timer-Latch Overcurrent Protection Detection Current
The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent
flows, the circuit detects the increase in the voltage between the FET’s drain and source using the external FET
ON resistor (RON), actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP
terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, the circuit sets the
latch to fix OUT terminals (pin 3, 22) at “H” level and turn off the external FET. The detection current value can
be set by the resistors (RLIM1 and RLIM2) connected between the FET’s drain and the ILIM1 terminal (pin 5) and
between the drain and the ILIM2 terminal (pin 20), respectively.
The internal current (ILIM) can be set by the timing resistor (RT) connected to the RT terminal (pin 12).
Time until activating timer circuit and setting latch is equal to short-circuit detection time in "2. Setting Time
Constant for Timer-Latch Short-Circuit Protection Circuit".
Internal current value: ILIM
ILIM (µA) =:
2700
RT (kΩ)
Detection current value: IOCP
IOCP (A) =:
RLIM :
RON :
VIN :
VO :
fOSC :
L :
ILIM(A) × RLIM(Ω)
RON (Ω)
−
(VIN(V) − VO(V)) × VO(V)
2 × VIN(V) × fOSC(Hz) × L(H)
Overcurrent detection resistor
External FET ON resistor
Input voltage
DC/DC converter output voltage
Oscillation frequency
Coil inductance
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less.
• Overcurrent detection circuit
VIN
Q1
L
(VS2)
21 VS1
4
VO
Current
Protection
Logic
(1 µA)
−
(ILIM2)
+
20 ILIM1
5
(RLIM)
Each
Channel
Drive
CSCP
8
VREF
S R
Latch
UVLO
17
MB39A104
Overcurrent Protection Circuit: Range of Operation
When an overcurrent flow occurs, if the increased voltage between the drain and source of the FET is detected
by means of the external FET (Q1) resistor, operational stability is lost when the external FET (Q1) ON interval
determined by the oscillation frequency, input voltage, and output voltage falls below 450 ns.
Therefore, the circuit should be used within a range that ensures that the ON interval does not fall below 450ns,
according to the following formula.
ON interval 450 (ns) ≥
VO (V)
VIN (V) × fOSC (Hz)
If the ON interval of the external FET (Q1) is below 450ns, we recommend the use of an overcurrent detection
resistor RS to detect overcurrent, as shown below.
This example shows the range of operation of the overcurrent detection function with a setting of Vo = 3.3V.
• Method to detect by current when external FET(Q1) is turned on
VIN
Overcurrent Detection Function Operating Range
(Rs)
1600
ErrAmp
Q1
1400
(VS2)
VO = set to 3.3 V
1200
fOSC (kHz)
21
4 VS1
1000
800
400
−
+
(ILIM2)
20 ILIM1
5
Connect to RS
when
using RS
Operation Range
200
0
6
8
10
12
14
VCC (V)
16
18
20
• Method to detect by mean current
Overcurrent Detection Function Operating Range
VIN
21 (VS2)
4 VS1
ErrAmp
RS
1600
1400
VO = set to 3.3 V
1200
fOSC (kHz)
Q1
1000
800
Operation Range
600
−
+
(ILIM2)
20 ILIM1
5
400
200
0
18
6
8
10
12
14
VCC (V)
16
18
20
MB39A104
2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit
Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier′s
output level to the reference voltage (3.1 V Typ).
While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output
remains at “L” level, and the CSCP terminal (pin 8) is held at “L” level.
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage
to drop, the output of the short-circuit detection comparator goes to “H” level. This causes the external shortcircuit protection capacitor CSCP connected to the CSCP terminal to be charged at 1 µA.
Short-circuit detection time (tSCP)
tSCP (s) =: 0.73 × CSCP (µF)
When the capacitor CSCP is charged to the threshold voltage (VTH =: 0.73 V), the latch is set and the external
FET is turned off (dead time is set to 100%). At this time, the latch input is closed and the CSCP terminal is
held at “L” level. If a short-circuit is detected on either of the two channels, both channels are shut off.
When the power supply is turned on back or VREF terminal (pin 17) voltage is less than 2.4 V (Min) by setting
CTL terminal (pin 24) to “L” level, the latch is released.
• Timer-latch short-circuit protection circuit
(FB2)
VO
R1
FB1
16
9
(−INE2) 15
−INE1
−
10
Error
Amp
+
R2
(1.24 V)
SCP
Comp.
+
+
−
(3.1 V)
(1 µA)
To each channel
Drive
CSCP
8
VREF
S
R
Latch
UVLO
19
MB39A104
■ TREATMENT WITHOUT USING CSCP TERMINAL
When not using the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 8) to GND with
the shortest distance.
• Treatment
without using CSCP
GND
8
18
CSCP
■ RESETTING THE LATCH OF EACH PROTECTION CIRCUIT
When the overcurrent, or short-circuit protection circuit detects each abnormality, it sets the latch to fix the output
at the "L" level.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less.
20
MB39A104
■ I/O EQUIVALENT CIRCUIT
〈〈Reference voltage block〉〉
〈〈Control block〉〉
〈〈Soft-start block〉〉
VREF
(5.0 V)
VCC 7
1.24 V
CTL 24
+
VCC
72
kΩ
−
77.8
kΩ
CSX
17 VREF
104
kΩ
24.8
kΩ
GND
GND
GND 18
〈〈Triangular wave oscillator
block (RT) 〉〉
VCC
〈〈Short-circuit detection block〉〉
VREF
(5.0 V)
〈〈Triangular wave oscillator
(CT) block〉〉
(3.1 V)
(3.1 V)
2 kΩ
1.35 V
8 CSCP
+
CT 13
−
12 RT
GND
GND
GND
〈〈Overcurrent protection circuit block〉〉
〈〈Error amplifier block (CH1, CH2) 〉〉
VCC
VREF
(5.0 V)
−INEX
ILIMX
CSX
1.24 V
VSX
FBX
GND
GND
〈〈PWM comparator
block (CH1, CH2) 〉〉
〈〈Bias voltage block〉〉
VCC
FBX
VCCO
VCC
VCC
VCCO
GNDO
〈〈Output block (CH1, CH2) 〉〉
VCCO
1
O
CT
2 VH
DTCX
VH
GNDO 23
GND
GND
GNDO
X : Each channel No.
21
22
6
CSCP
C21
1000 pF
Charging
current (1 mA)
H priority
L priority
−
+
+
Error
Amp2
L priority
−
+
+
Error
Amp1
12 13
CT
C1
100 pF
H:
UVLO release
SCP
Comp.
+
+
−
OSC
UVLO
RT
R1
24 kΩ
8
SCP
Logic
H:
at SCP
15
B
VREF
100 kΩ 13 kΩ
R14
CS2 10 µA
CH2 ON/OFF signal 68 kΩ
14
(Hiz : ON, L : OFF) C17
R13
0.1 220
1.24 V
µF kΩ
C14
16
VIN
1000 pF FB2
(7 V to 19 V)
19
DTC2
R15R16 −INE2
DTC1
R10R11 −INE1
10
A
VREF
150 kΩ 56 kΩ
R9
10
µA
CS1
CH1 ON/OFF signal 68 kΩ
11
C16
R8
(Hiz : ON, L : OFF)
0.1 220
1.24 V
µF kΩ
C12
9
1000 pF FB1
3.1 V
5.0 V
17
accuracy
± 1%
Pch
VCC − 5 V
VH
Bias
Voltage
+
−
VREF
Power
18
GND
CTL
VR1 ON/OFF
1.24 V
Error Amp Reference
Error Amp Power Supply
H:
at OCP
Current
Protection
Logic
ILIM1
VS1
OUT1
VCCO
VH
VCC
C2
10
µF
C6
10
µF
C10
0.1 µF
2.7 kΩ
R5
+
2.7 kΩ
R4
+
C7
10
µF
C3
10
µF
Q2
Q1
D2
15 µF
L2
B
Stepdown
D1
15 µF
L1
A
H : ON (Power ON)
L : OFF (Standby mode)
VTH = 1.4 V
CTL
24
7
GNDO
23
2
20
ILIM2
VS2
21
OUT2
22
C11
0.1 µF
5
+
Drive2
CH2
4
IO = 200 mA
at VCCO = 12 V
Current
Protection
Logic
3
1
−
Drive1
Pch
CH1
IO = 200 mA
at VCCO = 12 V
VREF
C20
0.1 µF
bias
2.5 V
1.5 V
PWM
+ Comp.2
+
−
L priority
PWM
+ Comp.1
+
−
L priority
Stepdown
C4
82 µF
+
C8
82 µF
VO2
(3.3 V)
+
VO1
(5.0 V)
MB39A104
■ APPLICATION EXAMPLE
MB39A104
■ PARTS LIST
COMPONENT
ITEM
SPECIFICATION
VENDOR
PARTS No.
Q1, Q2
Pch FET
VDS = −30 V, ID = −6 A
TOSHIBA
TPC8102
D1, D2
Diode
VF = 0.42 V (Max) , at IF = 3 A
ROHM
RB0530L-30
L1, L2
Inductor
15 µH
3.6 A, 50 mΩ
SUMIDA
CDRH104R-150
C1
C2, C6
C3, C7
C4, C8
C10, C11, C20
C12, C14, C21
C16, C17
Ceramics Condenser
OS-CONTM
Ceramics Condenser
OS-CONTM
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
100 pF
10 µF
10 µF
82 µF
0.1 µF
1000 pF
0.1 µF
50 V
20 V
25 V
6.3 V
50 V
50 V
50 V
TDK
SANYO
TDK
SANYO
TDK
TDK
TDK
C1608CH1H101J
20SVP10M
C3225JF1E106Z
6SVP82M
C1608JB1H104K
C1608JB1H102K
C1608JB1H104K
R1
R4, R5
R8, R13
R9, R14
R10
R11
R15
R16
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
24 kΩ
2.7 kΩ
220 kΩ
68 kΩ
150 kΩ
56 kΩ
100 kΩ
13 kΩ
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
RR0816P-243-D
RR0816P-272-D
RR0816P-224-D
RR0816P-683-D
RR0816P-154-D
RR0816P-563-D
RR0816P-104-D
RR0816P-133-D
Note : TOSHIBA : TOSHIBA Corporation
ROHM : ROHM Co., Ltd
SANYO : SANYO Electric Co., Ltd.
TDK
: TDK Corporation
SUMIDA : SUMIDA Electric Co., Ltd.
ssm
: SUSUMU Co., Ltd.
23
MB39A104
■ SELECTION OF COMPONENTS
• Pch MOS FET
The P-ch MOSFET for switching use should be rated for at least 20% more than the maximum input voltage. To
minimize continuity loss, use a FET with low RDS(ON) between the drain and source. For high input voltage and
high frequency operation, on/off-cycle switching loss will be higher so that power dissipation must be considered.
In this application, the Toshiba TPC8102 is used. Continuity loss, on/off switching loss, and total loss are determined by the following formulas. The selection must ensure that peak drain current does not exceed rated values,
and also must be in accordance with overcurrent detection levels.
Continuity loss : PC
PC = ID 2 × RDS (ON) × Duty
On-cycle switching loss : PS (ON)
VD (Max) × ID × tr × fOSC
PS (ON) =
6
Off-cycle switching loss : PS (OFF)
VD (Max) × ID (Max) × tf × fOSC
PS (OFF) =
6
Total loss : PT
PT = PC + PS (ON) + PS (OFF)
Example: Using the Toshiba TPC8102
CH1
Input voltage VIN (Max) = 19 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 500 kHz,
L = 15 µH, drain-source on resistance RDS (ON) =: 50 mΩ, tr = tf =: 100 ns.
Drain current (Max) : ID (Max)
VIN − VO
ID (Max) = IO +
ton
2L
=3+
19 − 5
2 × 15 × 10−6
×
1
× 0.263
500 × 103
×
1
× 0.263
500 × 103
=: 3.25 (A)
Drain current (Min) : ID (Min)
VIN − VO
ID (Min) = IO −
ton
2L
=3−
19 − 5
2 × 15 × 10−6
=: 2.75 (A)
24
MB39A104
= ID 2 × RDS (ON) × Duty
PC
=
3 2 × 0.05 × 0.263
=: 0.118 W
PS (ON)
=
=
VD (Max) × ID × tr × fOSC
6
19 × 3 × 100 × 10−9 × 500 × 103
6
=: 0.475 W
PS (OFF)
=
=
VD (Max) × ID (Max) × tf × fOSC
6
19 × 3.25 × 100 × 10−9 × 500 × 103
6
=: 0.515 W
PT
= PC + PS (ON) + PS (OFF)
=: 0.118 + 0.475 + 0.515
=: 1.108 W
The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (Ta = +25 °C) .
CH2
Input voltage VIN (Max) = 19 V output voltage VO = 3.3 V, drain current ID = 3 A, Oscillation frequency
fOSC = 500 kHz, L = 15 µH, drain-source on resistance RDS (ON) =: 50 mΩ, tr = tf =: 100 ns.
Drain current (Max) : ID (Max)
VIN − VO
ID (Max) = IO +
ton
2L
=3+
19 − 3.3
2 × 15 × 10−6
×
1
× 0.174
500 × 103
×
1
× 0.174
500 × 103
=: 3.18 (A)
Drain current (Min) : ID (Min)
VIN − VO
ton
ID (Min) = IO −
2L
=3−
19 − 3.3
2 × 15 × 10−6
=: 2.82 (A)
25
MB39A104
PC
= ID 2 × RDS (ON) × Duty
=
3 2 × 0.05 × 0.174
=: 0.078 W
PS (ON)
=
VD (Max) × ID × tr × fOSC
6
=
19 × 3 × 100 × 10−9 × 500 × 103
6
=: 0.475 W
PS (OFF)
=
=
VD (Max) × ID (Max) × tf × fOSC
6
19 × 3.18 × 100 × 10−9 × 500 × 103
6
=: 0.504 W
PT = PC + PS (ON) + PS (OFF)
=: 0.078 + 0.475 + 0.504
=: 1.057 W
The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (Ta = +25 °C) .
• Inductors
In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor,
but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous
operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value,
which will enable continuous operation under light loads. Note that if the inductance value is too high, however,
direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at
the point where efficiency is greatest.
Note also that the DC superimposition characteristics become worse as the load current value approaches the
rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing
loss of efficiency. The selection of rated current value and inductance value will vary depending on where the
point of peak efficiency lies with respect to load current.
Inductance values are determined by the following formulas.
The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the
load current or less.
Inductance value : L
2 (VIN − VO)
ton
L ≥
IO
26
MB39A104
Example:
CH1
L ≥
≥
2 (VIN − VO)
ton
IO
2 × (19 − 5)
1
×
× 0.263
IO
500 × 103
≥ 4.91 µH
CH2
L ≥
≥
2 (VIN − VO)
ton
IO
2 × (19 − 3.3)
1
×
× 0.174
IO
500 × 103
≥ 3.64 µH
Inductance values derived from the above formulas are values that provide sufficient margin for continuous
operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore
necessary to determine the load level at which continuous operation becomes possible. In this application, the
Sumida CDRH104R-150 is used. At 15 µH, the load current value under continuous operating conditions is
determined by the following formula.
Load current value under continuous operating conditions : IO
VO
IO ≥
toff
2L
Example: Using the CDRH104R-150
15 µH (allowable tolerance ±30%) , rated current = 3.6 A
CH1
IO ≥
≥
VO
2L
toff
5
2 × 15 × 10−6
×
1
× (1 − 0.263)
500 × 103
≥ 245.7 mA
CH2
IO ≥
≥
VO
2L
toff
3.3
1
× (1 − 0.174)
2 × 15 × 10−6 × 500 × 103
≥ 181.7 mA
27
MB39A104
To determine whether the current through the inductor is within rated values, it is necessary to determine the
peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output
ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following
formulas.
Peak value : IL
VIN − VO
IL ≥ IO +
2L
ton
Peak-to-peak value : ∆IL
VIN − VO
∆IL =
ton
L
Example: Using the CDRH104R-150
15 µH (allowable tolerance ±30%) , rated current = 3.6 A
Peak value:
CH1
IL
VIN − VO
2L
≥ IO +
≥3+
ton
19 − 5
1
× 0.263
2 × 15 × 10−6 × 500 × 103
≥ 3.25 A
CH2
IL
VIN − VO
2L
≥ IO +
≥3+
ton
19 − 3.3
2 × 15 × 10−6
×
1
× 0.174
500 × 103
≥ 3.18 A
Peak-to-peak value:
CH1
∆IL =
=
VIN − VO
L
ton
19 − 5
1
× 0.263
15 × 10−6 × 500 × 103
= 0.491 A
CH2
∆IL =
=
VIN − VO
L
19 − 3.3
1
×
× 0.174
15 × 10−6
500 × 103
= 0.364 A
28
ton
MB39A104
• Flyback diode
The flyback diode is generally used as a Shottky barrier diode (SBD) when the reverse voltage to the diode is
less than 40V. The SBD has the characteristics of higher speed in terms of faster reverse recovery time, and
lower forward voltage, and is ideal for achieving high efficiency. As long as the DC reverse voltage is sufficiently
higher than the input voltage, the average current flowing through the diode is within the average output current
level, and peak current is within peak surge current limits, there is no problem. In this application the Rohm
RB053L-30 is used. The diode average current and diode peak current can be calculated by the following
formulas.
Diode mean current : IDi
VO
)
IDi ≥ IO × (1 −
VIN
Diode peak current : IDip
VO
IDip ≥ (IO +
toff)
2L
Example: Using the Rohm RB053L-30
VR (DC reverse voltage) = 30 V, average output voltage = 3.0 A, peak surge current = 70 A,
VF (forward voltage) = 0.42 V, IF = 3.0 A
CH1
IDi ≥ IO × (1 −
VO
)
VIN
≥ 3 × (1 − 0.263)
≥ 2.21 A
CH2
IDi ≥ IO × (1 −
VO
)
VIN
≥ 3 × (1 − 0.174)
≥ 2.48 A
CH1
IDip ≥ (IO +
VO
toff)
2L
≥ 3.24 A
CH2
IDip ≥ (IO +
VO
toff)
2L
≥ 3.18 A
29
MB39A104
• Smoothing Capacitor
The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smoothing capacitor it is essential to consider equivalent series resistance (ESR) and allowable ripple current. Higher
ESR means higher ripple voltage, so that to reduce ripple voltage it is necessary to select a capacitor with low
ESR. However, the use of a capacitor with low ESR can have substantial effects on loop phase characteristics,
and therefore requires attention to system stability. Care should also be taken to use a capacity with sufficient
margin for allowable ripple current. This application uses the (OS-CON TM) 6SVP82M made by Sanyo. The ESR,
capacitance value, and ripple current can be calculated from the following formulas.
Equivalent Series Resistance : ESR
1
∆VO
−
ESR ≤
∆IL
2πfCL
Capacitance value : CL
∆IL
CL
≥ 2πf (∆VO − ∆IL × ESR)
Ripple current : ICLrms
(VIN − VO) ton
ICLrms ≥
2√3L
Example: Using the 6SVP82M
Rated voltage = 6.3 V, ESR = 50 mΩ, maximum allowable ripple current = 1570 mArms
Equivalent series resistance
CH1
ESR ≤
≤
∆VO
∆IL
−
0.050
0.491
≤ 98.0 mΩ
30
−
1
2πfCL
1
2π × 500 × 103 × 82 × 10−6
MB39A104
CH2
∆VO
∆IL
ESR ≤
−
0.033
0.364
≤
1
2πfCL
−
1
2π × 500 × 103 × 82 × 10−6
≤ 86.8 mΩ
Capacitance value
CH1
CL ≥
≥
∆IL
2πf (∆VO − ∆IL × ESR)
0.491
2π × 500 × 103 × (0.050 − 0.491 × 0.05)
≥ 6.14 µF
CH2
CL ≥
≥
∆IL
2πf (∆VO − ∆IL × ESR)
0.364
2π × 500 × 103 × (0.033 − 0.364 × 0.05)
≥ 7.83 µF
Ripple current
CH1
ICLrms ≥
≥
(VIN − VO) ton
2√3L
(19 − 5) × 0.263
2√3 × 15 × 10−6 × 500 × 103
≥ 141.7 mArms
CH2
ICLrms ≥
≥
(VIN − VO) ton
2√3L
(19 − 3.3) × 0.174
2√3 × 15 × 10−6 × 500 × 103
≥ 105.1 mArms
31
MB39A104
■ REFERENCE DATA
TOTAL Efficiency vs. Input Voltage
100
TOTAL efficiency η (%)
90
80
70
Vin = 7 V
Vin = 10 V
Vin = 12 V
Vin = 19 V
60
Ta = +25 °C
5 V Output
SW1 = OFF
SW2 = ON
50
40
30
10 m
100 m
1
10
Input voltage VIN (V)
Each CH Efficiency vs. Input Voltage
100
Each CH efficiency η (%)
90
80
70
Vin = 7 V
Vin = 10 V
Vin = 12 V
Vin = 19 V
60
Ta = +25 °C
3.3 V Output
SW1 = ON
SW2 = OFF
50
40
30
10 m
100 m
1
10
Input voltage VIN (V)
(Continued)
32
MB39A104
(Continued)
Switching Wave Form (CH1)
VG (V)
Ta = +25 °C
VIN = 12 V
CTL = 5 V
VO = 5 V
RL = 1.67 Ω
15
10
5
VS (V)
0
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
t (µs)
Switching Wave Form (CH2)
VG (V)
Ta = +25 °C
VIN = 12 V
CTL = 5 V
VO = 3.3 V
RL = 1.1 Ω
15
10
5
VS (V)
0
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
t (µs)
33
MB39A104
■ USAGE PRECAUTION
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply negative voltages.
The use of negative voltages below –0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
■ ORDERING INFORMATION
Part number
MB39A104PFV
34
Package
24-pin plastic SSOP
(FPT-24P-M03)
Remarks
MB39A104
■ PACKAGE DIMENSIONS
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) MAX) .
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
24-pin plastic SSOP
(FPT-24P-M03)
0.17±0.03
(.007±.001)
*17.75±0.10(.305±.004)
24
13
*2 5.60±0.10
7.60±0.20
(.220±.004) (.299±.008)
INDEX
Details of "A" part
+0.20
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.25(.010)
1
"A"
12
0.65(.026)
0.24
.009
+0.08
–0.07
+.003
–.003
0.13(.005)
0~8˚
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.10(.004)
C
2003 FUJITSU LIMITED F24018S-c-4-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
35
MB39A104
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
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Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
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Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0308
 FUJITSU LIMITED Printed in Japan
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