TDA7570 - uri=media.digikey
TDA7570
250W PWM high efficiency power audio amplifier
Features
■
Output power 2 x 70W / 1 x 250W @ THD<1%
■
PWM output
■
±30V supply voltage (Max)
■
Stand-by
■
Mute
■
Protections against short circuit across the load
■
Chip thermal protection
■
External temperature sensor possibility
■
Thermal warning pins
■
Adjustable clip detector pin
Description
The TDA7570 is a switchmode power audio
amplifier with differential inputs and PWM output.
Table 1.
HiQUAD64
The maximum output current and voltage swing
are depending by the output circuitry (power
supply, external power transistors and sensing
resistors). The device can work as a stereo
single-ended channels or a mono bridge power
amplifier.
Device summary
Order code
Package
Packing
TDA7570
HiQUAD64
Tray
September 2013
Rev 2
1/17
www.st.com
17
Contents
TDA7570
Contents
1
Block and simplified application diagram . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4
Notes on the electrical schematic shown in Figure 3 . . . . . . . . . . . . . . . . 11
3.4.1
4
Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functions, pins and components description . . . . . . . . . . . . . . . . . . . 12
4.1
Components with critical placement and type: . . . . . . . . . . . . . . . . . . . . . 12
4.2
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Short circuit protection current calculation . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
External thermal protection network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Gate driving network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6
External connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
TDA7570
Block and simplified application diagram
1
Block and simplified application diagram
Figure 1.
Block and simplified application diagram
FEED L IN
5V DIG
IN L+
46
IN L-
45
34
O0-15
CDsel1
CDsel2
CD
5V DIG
NTC
THWint
THWext
31
SPI1
14
SPI2
18
GPL
17
GPLS
22
GNLS
21
GNL
23
SNL2
24
SNL1
6
+VS-5
15
-VS+5
8
SPR1
7
SPR2
4
GPR
5
GPRS
63
GNRS
64
GNR
62
SNR2
CHANNEL LEFT
HSD +
PROTECTIONS
INTERFACE
CHANNEL LEFT
LSD +
PROTECTIONS
+25V
OUTPUT
LOWPASS
FILTER
OUT LEFT
CLIP
38
36
37
-2.5V
52
55
TERM.
49
IN R-
50
RIGHT
CHANNEL
SIGNAL
PROCESSING
10
32
DGND
CHANNEL RIGHT
HSD +
PROTECTIONS
REF
56
IN R+
PGND
42 13
30
54
ST-BY
+VS -LOW
12
29
2.5V
MUTE
OSC
+VS
9
LEFT
CHANNEL
SIGNAL
PROCESSING
33
I-OFCLK
+VS -VREF1
28
40
57
53
SGND
-VS +VREFL
INTERFACE
CHANNEL RIGHT
LSD +
PROTECTIONS
60
-VS +VREFL
25
-VS +VREFL
26,27,58,59
-VS
-25V
+25V
OUTPUT
LOWPASS
FILTER
OUT RIGHT
61
SNR1
-25V
D00AU1198
3/17
Pin description
Pin description
sgnd
+2.5V
MUTE
N.C.
1
52
-2.5V
N.C.
2
51
N.C.
N.C.
3
50
IN R-
Gpr
4
49
IN R+
Gprs
5
48
N.C.
+Vs-5
6
47
N.C.
Spr2
7
46
IN L+
Spr1
8
45
IN L-
+Vs-Vref1
9
44
N.C.
pgnd
10
43
N.C.
N.C.
11
42
+Vs-low
N.C.
+Vs
12
41
Spl1
13
40
5Vdig
Spl2
14
39
N.C.
-Vs+5
15
38
NTC
N.C.
16
37
THWext
Gpls
17
36
THWint
Gpl
18
35
N.C.
N.C.
19
34
O0-I5
N.C.
20
33
I-O-FCLK
dgnd
CD
CDsel2
CDsel1
-Vs
-Vs
-Vs+Vrefl
Snl1
Snl2
Gnl
Gnls
Feed L in
27 28 29 30 31 32
21 22 23 24 25 26
4/17
ST-BY
58 57 56 55 54 53
64 63 62 61 60 59
Table 2.
Feed R in
-Vs
-Vs
-Vs+Vrefr
Snr1
Snr2
Pins connection diagram
Gnr
Figure 2.
Gnrs
2
TDA7570
AC00241
Pins description
Pin
number
Name
Voltage limit
(low)
Voltage limit
(high)
1
N.C.
Not connected
2
N.C.
Not connected
3
N.C.
Not connected
4
Gpr
Gate PMOS, right channel
+Vs-12V
30V
5
Gprs
Sense gate PMOS, right channel
+Vs-12V
30V
6
+Vs-5
7
Spr2
Sensing 2 PMOS, right channel
30V
8
Spr1
Sensing 1 PMOS, right channel
30V
9
+Vs-Vref1
10
pgnd
Power ground
11
N.C.
Not connected
Function
+Vs-6
Supply drivers PMOS
+Vs-12V
0 (ref.)
30V
TDA7570
Pin description
Table 2.
Pins description (continued)
Pin
number
Name
12
+Vs
Positive power supply
30V
13
Spl1
Sensing 1 PMOS, left channel
30V
14
Spl2
Sensing 2 PMOS, left channel
30V
15
-Vs+5
16
N.C.
Not connected
17
Gpls
Sense gate PMOS, left channel
+Vs-12V
30V
18
Gpl
Gate PMOS, left channel
+Vs-12V
30V
19
N.C.
Not connected
20
N.C.
Not connected
21
Gnl
Gate NMOS, left channel
-30V
-Vs+12V
22
Gnls
Gate NMOS, left channel
-30V
-Vs+12V
23
Snl2
Sensing 2 NMOS, left channel
-30V
24
Snl1
Sensing 1 NMOS, left Channel
-30V
25
-Vs+Vrefl
Supply drivers NMOS. left channel
-30V
26
-Vs
Negative power supply
-30V
27
-Vs
Negative power supply
-30V
28
Feed L in
Feedback network left channel
-5V
29
CDsel1
Clip detector selection 1
5.5V
30
CD sel2
Clip detector selection 2
5.5V
31
CD
Clip detector output
5.5V
32
dgnd
33
I-O-FCLK
34
Function
Voltage limit
(low)
Voltage limit
(high)
-Vs+6
Digital ground
-Vs+12V
5V
0 (ref)
Clock frequency input/output pin
5.5V
O0-I5
Input/output FCLK selection
0 = Output; 1 = Input
5.5V
35
N.C.
Not connected
36
THWint
Internal thermal warning output
5.5V
37
THWext
External thermal warning output
5.5V
38
NTC
Sensing resistors network
5.5V
39
N.C.
Not connected
40
5Vdig
Digital 5V supply output
5.5V
Positive voltage supply low power
30V
41
42
+Vs-low
43
N.C.
Not connected
44
N.C.
Not connected
5/17
Pin description
Table 2.
6/17
TDA7570
Pins description (continued)
Pin
number
Name
Voltage limit
(low)
Voltage limit
(high)
45
IN L-
Left channel negative input
-3V
3V
46
IN L+
Left channel positive input
-3V
3V
47
N.C.
Not connected
48
N.C.
Not connected
49
IN R+
Right channel positive input
-3V
3V
50
IN R-
Right channel negative input
-3V
3V
51
N.C.
Not connected
52
-2.5V
Signal -2.5V supply output
-2.75V
53
sgnd
Signal ground
0 (ref)
54
+2.5V
Signal 2.5V supply output
2.75V
55
MUTE
Mute input
5.5V
56
ST-BY
Stand by input
57
Feed R in
58
-Vs
Negative voltage supply
-30V
59
-Vs
Negative voltage supply
-30V
60
-Vs+Vrefr
Supply drivers NMOS. Right channel
-30V
61
Snr1
Sensing 2 NMOS, right channel
-30V
62
Snr2
Sensing 1 NMOS, right channel
-30V
63
Gnrs
Sense gate NMOS, right channel
-30V
-Vs+12V
64
Gnr
Gate NMOS, right channel
-30V
-Vs+12V
Function
Feedback network right channel
6V
-5
5V
-Vs+12V
TDA7570
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
±Vs
Operating supply voltage
±30
V
Ptot
Power dissipation Tcase = 85°C
21
W
Tj
Junction temperature, operating range
-40 to 150
°C
Tstg
Storage temperature, operating range
-55 to 150
°C
Value
Unit
3
°C/W
Thermal data
Table 4.
Thermal data
Symbol
Rth j-case
Parameter
Thermal resistance junction to case
3.3
Electrical characteristics
Table 5.
Electrical characteristics
(VS = ±25V, RL = 4, f = 100Hz, Tj = 25°C, Gain = 28dB, application circuit shown in
Figure 3, 2x65/1x130W system, unless otherwise specified.)
Symbol
±VS
Parameter
Quiescent supply current
Ist-by
Quiescent supply current
Vos
Output offset voltage
Pd
Min.
Operating supply voltage
Iq
Po
Test condition
Typ.
±12
Max.
Unit
±30
V
Vst-by = 5V, Fswitching = 352.8kHz
from +VS
from +VS -low
from -VS
20
5.4
20
25
7
25
35
9
35
mA
mA
mA
Vst-by = 0
from +VS
0.35
0.5
0.65
mA
Vst-by = 0
from -VS
-0.2
-0.3
-0.4
mA
Output-GND (single-ended)
350
mV
Output L - Output R (bridge)
120
mV
Single-ended, @ THD = 1%
2 x 70W system
70
W
Bridge, @ THD = 1%
1 x 250W system
250
W
Quiescent condition
1.5
Output Power
Power dissipation of the
TDA7570
1.75
W
7/17
Electrical specifications
Table 5.
Electrical characteristics (continued)
(VS = ±25V, RL = 4, f = 100Hz, Tj = 25°C, Gain = 28dB, application circuit shown in
Figure 3, 2x65/1x130W system, unless otherwise specified.)
Symbol
Parameter
Pdt
Power dissipation of the external
power transistors (total)
THD
TDA7570
Total harmonic distortion
Test condition
Min.
Typ.
Max.
Unit
@ Pout = 25W, bridge
configuration
10
W
@ Pout = 10 W, single ended
0.1
%
@ Pout = 40 W, bridge
0.03
0.1
%
G
Gain
single-ended
27
28
29
dB
G
Gain
Bridge
33
34
35
dB
En
Output noise Single_Ended
"A" weighted
200
V
E
Output noise bridge
"A" weighted
150
V
Delta gain error between
channels
f = 1kHz, after output filter of TBD
order, 20kHz butterworth
Ri
Input resistance
Single-ended
Ri
Input resistance
Bridge
Ge
0.5
dB
7
10
13
K
3.5
5
6.5
K
Vgspth
Threshold voltage of the
Pchannel Vgs sensor
(VSpx1 - VGpxs)
2.5
3
3.5
V
Vgsnth
Threshold voltage of the
Pchannel Vgs sensor
(VGnxs - VSnx1)
2.5
3
3.5
V
ct
Crosstalk
f = 1kHz, Vo = 2Vrms
50
60
dB
Mute attenuation
Vo = 2Vrms
70
80
dB
SVR
Supply voltage rejection
f = 100Hz, Vr = 0.5V
50
60
dB
FSW
Switching frequency
250
310
Am
Vil
Logic inputs low level voltage
Vih
Logic inputs high level voltage
360
KHz
1.5
V
2.3
V
CLIP DETECTOR
Vcd
Clip detector pin max operating
voltage (open drain)
CDl
CDs
5.5
V
Clip detector pin leakage current CD off
1
A
Clip detector pin saturation
voltage
1
V
0.5
%
CD on, 1mA
CDsel1=0, CDsel2=0
(near clipping detection)
CDi
8/17
Clip detector THD intervention
CDsel1=0, CDsel2=1
1
%
CDsel1=1, CDsel2=0
5
%
CDsel1=1, CDsel2=1
8
%
TDA7570
Table 5.
Electrical specifications
Electrical characteristics (continued)
(VS = ±25V, RL = 4, f = 100Hz, Tj = 25°C, Gain = 28dB, application circuit shown in
Figure 3, 2x65/1x130W system, unless otherwise specified.)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
PROTECTIONS
Thwc
Chip thermal warning intervention
150
°C
Tsdc
Thermal shut-down chip
160
°C
Tsdch
Thermal shut-down chip hysteresis
10
°C
Thws
External thermal warning
intervention
5Vdig
x 0.45
5Vdig
x 0.48
5Vdig
x 0.51
V
Tsds
External thermal shut-down
intervention
5Vdig
x 0.37
5Vdig
x 0.4
5Vdig
x 0.43
V
Tsdsh
External thermal shut-down
hysteresis
5Vdig
x 0.037
5Vdig
x 0.04
5Vdig
x 0.043
V
Vpp
Protection intervention voltage
Pchannel (Vspx1-Vspx2)
85
100
120
mV
Vpn
Protection intervention voltage
Nchannel (Vsnx2-Vsnx1)
85
100
120
mV
Ispx1
Current input pins 7, 13
150
200
260
A
Isnx1
Current output pins 24, 61
-150
-200
-260
A
DRIVERS
Vhgp
High level output voltage (Gpl, Gpr)
+Vs-10
V
Vlgp
Low level output voltage (Gpl, Gpr)
+Vs
V
Vhgn
High level output voltage (Gnl, Gnr)
-Vs
V
Vlgn
Low level output voltage (Gnl, Gnr)
-Vs+10
V
Ihgp
High level output sink current
(Gpl, Gpr, peak)
2.2
A
Ilgp
Low level output source current
(Gpl, Gpr, peak)
2.7
A
Ihgn
High level output sink current
(Gnl, Gnr, peak)
2.5
A
Ilgn
Low level output source current
(Gnl, Gnr, peak)
1.7
A
INTERNAL POWER SUPPLY
5Vdig
5Vdig pin output voltage
Reference: dgnd pin
4.3
4.8
5.3
V
2.5V
2.5V pin output voltage
Reference: sgnd pin
2.15
2.4
2.65
V
-2.5V
-2.5V pin output voltage
Reference: sgnd pin
-2.15
-2.4
-2.65
V
Vref1
Vref1 pin output voltage
Reference: + Vs pin
8.6
9.6
10.6
V
Reference: - Vs pin
-8.6
-9.6
-10.6
V
Vrefl/Vrefr Vrefl, Vrefr pin output voltage
9/17
Electrical specifications
Figure 3.
10/17
Application diagrams
TDA7570
TDA7570
Electrical specifications
3.4
Notes on the electrical schematic shown in Figure 3
3.4.1
Main characteristics
●
2 channels single-ended or 1 channel bridge PWM amplifier
●
Power output: see Table 5
●
Gain single-ended = 28 dB
●
Gain bridge = 34dB
●
Clip detector settled at THD=10%
●
Internal master oscillator
The schematic is depicted showing the suggested structure of the printed circuit board
tracks (star points, high current path, components placement).
To avoid malfunctioning due to the parasitic inductance, short connections lengths are
recommended.
Table 6.
Component characteristics
Component
(See schematic of Figure 4)
Minimum load:
2 x 4 Ohm single-ended
or 8 Ohm bridge
(2 x 65W / 1 x 130W)
Minimum load:
2 x 2 Ohm single-ended
or 4Ohm bridge
(2 x 125W / 1 x 250W))
P-MOS-L
P-MOS-R
STP12PF06
2 x STP12PF06
in parallel
N-MOS-L
N-MOS-R
STP14NF06
2 x STP14NF06
in parallel
Rp-N-L2
RP-P-L2
Rp-N-R2
Rp-P-R2
Not present
4.7K
11/17
Functions, pins and components description
TDA7570
4
Functions, pins and components description
4.1
Components with critical placement and type:
4.2
●
Ci-L1, Ci-L2, Ci-R1, Ci-R2 must be placed as near as possible to the sources of the
respective power MOS. If 2 power MOS in parallel are needed, can be useful to place a
couple of capacitors for each couple of power MOS. These capacitors are needed to
absorb the high di/dt current present during the Pchannel/Nchannel and
Nchannel/Pchannel transition that can cause high peak voltages on the power supply
wiring connection due to their parasitic inductance.
●
The capacitors placed between +Vs to GND and to -Vs are distributed along the power
lines. With P.C. board with very short connections, some of these capacitors can be
avoided (Cvs-1, Cvs-2, Cd3, Cd4, Cd5, Cd6).
●
The current sensing resistors Rsens-N-L, Rsens-P-L, Rsens-P-R and Rsens-N-R must
be not inductive components, as example, made by a costant an wire.
Input capacitors
●
The value of the input capacitors (Cin-L+, Cin-L-, Cin-R+, Cin-R- depends on the
desired -3dB high pass cutoff frequency, following the formula:
1
F  3dB  = --------------------------------------------6.28  10000  C in
4.3
Short circuit protection current calculation
Figure 4.
Short circuit protection current diagram (example for the N-channel)
TDA7570
Imos
Rp1 (typ=4.7kOhm)
Rsens
(not inductive resistor)
Typ. Values = 10 – 30 mOhm
Cfil (typ 2.2nF)
SPx2 pin
Rp2
Rfil (typ. 100 Ohm)
to -Vs
Vp=100mV Typ
comparator
SPx1 pin
Vfil = Ispx1 x Rfil = 20mV Typ
1
Vpx   Rp1 + Rp2 
I lim = ------------------  -------------------------------------------------- + Vfil

Rsens 
Rp2
1
I lim = ------------------  Vpx + Vfil 
Rsens
12/17
if Rp2 is not used
TDA7570
4.4
Functions, pins and components description
External thermal protection network
Example of external thermal protection circuitry
●
●
Components:
–
type: B57621 C621/100k/+
–
Rtext = 10K
Results (simulations):
–
4.5
External thermal warning temperature intervention: 90 °C
–
External thermal shut down temperature intervention: 100 °C
–
External thermal shut down hysteresis: 6 °C
Gate driving network
The main purpose of the 27 Ohm resistors Rd-N-L, Rd-P-L, Rd-N-R and Rd-P-R are the
following:
●
1) Dumping of the L-C equivalent circuit done by the parasitic inductance and
capacitance present in the circuit
●
2) Reduction of the dv/dt of the Vgs and then reduction of the di/dt of the drain current
of the power MOS.
The R-C snubber network done by:
–
Rs-N-L, Cs-N-L
–
Rs-P-L, Cs-P-L
–
Rs-N-R, Cs-N-R
–
Rs-P-R, Cs-P-R
Are in the direction to increase the dumping (point 1) and reduce the dv/dt (point 2.
The value of these components is also depending on the layout structure. With a reduction
of the parasitic inductance present in the P.C. board layout, in the region around the power
transistors, the value of these components can be reduced, giving advantage in terms of
THD, mainly at mid-high power levels, due to the reduction of the "dead zone".
The minimum suggested value of Rd-x-x is around 10, while, is some cases, Rs-x-x and
Cs-x-x can be removed.
4.6
External connections
●
CD, THWEXT, THWINT
These pins, if used, it must be connected to a pull-up resistor (>10k) connected to a
supply voltage referred to the receiver device (as example, a P). Max 10V.
●
MUTE - To have a soft mute-play and play-mute transition, an R-C network can be
applied (as example 47k, 1F)
●
ST-BY - To avoid pop noise due to multiple ST-BY parasitic pulses, an R-C network can
be added (as example 47k, 0.1F)
●
+Vs-low - This pin supply the low voltage circuits. It can be connected to the +Vs or to
a reference voltage comprising between 12V to +Vs.
13/17
Functions, pins and components description
TDA7570
A connection to +Vs through a 100 resistor, together a 1F capacitor placed from
+Vs-low and GND is possible too.
●
14/17
NL+, INL-, INR+, INR- Input pins. The sign is referred to the input of the differential-tosingleended amplifier. Because the power stage is an inverting stage, the output of the
amplifier is with opposite sign with respect these pins. For bridge operation, the
connection INL+ must be shorted to the INR- and the connection INL- must be shorted
to INR+
TDA7570
Package informations
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 5.
HiQUAD-64 mechanical data and package dimensions
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
0.124
A1
0
0.25
0
0.010
A2
2.50
2.90
0.10
0.114
A3
0
0.10
0
0.004
b
0.22
0.38
0.008
0.015
0.012
c
0.23
0.32
0.009
D
17.00
17.40
0.669
D1 (1)
13.90
14.00
14.10
0.547
0.551
D2
2.65
2.80
2.95
0.104
0.110
E
17.00
17.40
0.669
E1 (1)
13.90
14.10
0.547
e
14.00
0.65
0.685
0.555
0.116
0.685
0.551
0.555
0.025
E2
2.35
2.65
0.092
E3
9.30
9.50
9.70
0.366
0.374
0.382
E4
13.30
13.50
13.70
0.523
0.531
0.539
0.104
F
0.12
0.005
G
0.10
0.004
L
0.80
1.10
N
OUTLINE AND
MECHANICAL DATA
MAX.
3.15
0.031
0.043
10 (max.)
0 (min.), 7
S
(max.)
HiQUAD-64
(1): "D1" and "E1" do not include mold flash or protusions
- Mold flash or protusions shall not exceed 0.15 mm (0.006 inch)
N
E2
A2
A
c
A
b
BOTTOM VIEW
⊕
F M A B
33
53
E3
e
D2
(slug tail width)
5
Package informations
B
E1
E3
E
Gauge Plane
slug
(bottom side)
C
0.35
A3
S
SEATING PLANE
L
21
64
G
C
COPLANARITY
1
E4 (slug lenght)
D1
A1
D
0102576 E
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Revision history
6
TDA7570
Revision history
Table 7.
16/17
Document revision history
Date
Revision
Changes
29-Aug-2007
1
Initial release.
17-Sep-2013
2
Updated Disclaimer.
TDA7570
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