CMOS Super8 ROMless MCU
Z88C00
CMOS Super8 ROMless
MCU
Product Specification
PS014602-0103
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© 2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
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under any intellectual property rights.
PS014602-0103
CMOS Super8 ROMless MCU
Product Specification
iii
Table of Contents
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Protopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Working Register Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MODE AND CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ADDRESS SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CPU Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ROMless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ROM and Protopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CPU Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
INSTRUCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SUPER-8 OPCODE MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Fast Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Level or Edge Triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STACK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
User-Defined Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
COUNTER/TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PS014602-0103
CMOS Super8 ROMless MCU
Product Specification
iv
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STANDARD TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INPUT HANDSHAKE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS (20 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTPUT HANDSHAKE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS (12 MHz, 20 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS (12 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS (20 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS (20 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS014602-0103
46
47
47
48
48
49
49
50
50
50
51
51
52
52
54
54
54
54
CMOS Super8 ROMless MCU
Product Specification
v
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
PS014602-0103
Pin Assignments 88-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments 48-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Functions 48-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments 28-Pin Piggyback Socket . . . . . . . . . . . . . . . . . . . . 4
Pin Functions 28-Pin Piggyback Socket . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Super8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Working Register Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Mode and Control Registers (Continued) . . . . . . . . . . . . . . . . . . . . 13
Mode and Control Registers (Continued) . . . . . . . . . . . . . . . . . . . . . 14
Mode and Control Registers (Continued) . . . . . . . . . . . . . . . . . . . . 15
Mode and Control Registers (Continued) . . . . . . . . . . . . . . . . . . . . 16
Mode and Control Registers (Continued) . . . . . . . . . . . . . . . . . . . . . 17
Program and Data Memory Address Spaces . . . . . . . . . . . . . . . . . 23
Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Instruction Formats (Continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupt Levels and Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Standard Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fully Interlocked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Strobed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fully Interlocked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Strobed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External Memory Read and Write Timing. . . . . . . . . . . . . . . . . . . . . 53
EPROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
44-Pin PLCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
48-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CMOS Super8 ROMless MCU
Product Specification
vi
List of Tables
Table 1. Super-8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3. Pin Assignments for Ports 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4. Condition Codes and Meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5. Instruction Set Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6. Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. Second Nibble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8. Super8 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10. AC Characteristics (20 MHz) Input Handshake . . . . . . . . . . . . . . . . .
Table 11. AC Characteristics (12 MHz, 20 MHz) Output Handshake . . . . . . . .
Table 12. AC Characteristics (12 MHz) Read/Write . . . . . . . . . . . . . . . . . . . . .
Table 13. AC Characteristics (20 MHz) Read/Write. . . . . . . . . . . . . . . . . . . . . .
Table 14. AC Characteristics (20 MHz) EPROM Read Cycle . . . . . . . . . . . . . .
PS014602-0103
10
18
19
25
27
29
37
39
48
49
50
51
52
54
CMOS Super8 ROMless MCU
Product Specification
1
FEATURES
•
Improved Z8® instruction set includes multiply and divide instructions, Boolean
and BCD operations.
•
•
Additional instructions support threaded-code languages, such as "Forth."
•
Addressing of up to 128K bytes of memory. Two register pointers allow use of
short and fast instructions to access register groups within 600 nsec.
•
•
•
Direct Memory Access controller (DMA).
•
Interrupt structure supports:
– 27 interrupt sources
– 16 interrupt vectors (2 reserved for future versions)
– 8 interrupt levels
– Servicing in 600 nsec. (1 level only)
•
•
•
•
Full-duplex UART with special features.
325 byte registers, including 272 general-purpose registers, and 53 mode and
control registers.
Two 16-bit counter/timers.
Up to 32 bit-programmable and 8 byte-programmable I/O lines, with 2 handshake
channels.
On-chip oscillator.
20 MHz clock.
8K byte ROM for Z8820
GENERAL DESCRIPTION
The Zilog Super8 single-chip MCU can be used for development and production.
It can be used as I/O- or memory-intensive computers, or configured to address
external memory while still supporting many I/O lines.
PS014602-0103
FEATURES
CMOS Super8 ROMless MCU
Product Specification
7
6
5
4
3
2
1
3
P0
4
P0
5
N
C
Po
P0
P01
2
0
0
N
C
G
N
D
P0
3
5
8
P1
2
P1
1
P1
P1
4
P1
C
N
9
NC
P1
2
68 67 66 65 64 63 62 61
NC
10
60
NC
VCC
11
59
NC
ROMless
12
58
VCC
P16
13
57
PO8
P17
14
56
PO7
P24
15
55
P34
P25
16
54
P35
VCC
17
53
AS
GND
18
52
DS
VCC
19
51
P40
XTAL2
20
50
P41
XTAL1
21
49
GND
P44
22
48
GND
P45
23
47
P42
P46
24
46
P43
P47
25
45
R/W
NC
26
44
NC
SUPER8
0
P2
6
P2
7
P3
7
P3
Re 6
se
t
N
C
P2
1
P3
1
N
C
P3
0
P2
3
P2
3
P3
2
N
C
P2
2
N
C
P3
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Figure 1.Pin Assignments 88-Pin PLCC
The Super8 features a full-duplex universal asynchronous receiver/ transmitter
(UART) with on-chip baud rate generator, two programmable counter/timers, a
direct memory access (DMA) controller, and an on-chip oscillator.
P04
2
P03
P11
3
P02
P12
4
P01
P13
5
P10
P14
6
P00
P15
The Super8 is also available as a 48-pin and 68-pin ROMless microcomputer with
four byte-wide I/O ports plus a byte-wide address/data bus. Additional address
bits can be configured, up to a total of 16.
1
44
43
42
41
40
39
ROMless
7
P05
P16
8
38
VCC
P17
9
37
P06
P24
10
36
P07
11
35
P34
P25
P35
VCC
12
GND
13
33
AS
XTAL2
14
32
DS
XTAL1
15
31
30
P21
P30
P26
26 27
29
28
GND
R/W
RESET
P76
25
P37
24
P27
22 23
P31
20 21
P20
19
P23
16
17
18
P33
P22
34
P32
P47
Z8801
Figure 2.Pin Assignments 44-Pin PLCC
PS014602-0103
GENERAL DESCRIPTION
CMOS Super8 ROMless MCU
Product Specification
3
P10
P00
P11
P01
P12
P02
P13
P03
P14
P04
P15
P05
P16
P06
P17
P07
P24
P34
P25
P35
+5V
AS
SUPER8
XTAL2
DS
P40
XTAL1
P44
P41
P45
P46
GND
P42
P47
P43
P22
R/W
P32
P33
RESET
P36
P23
P37
P20
P27
P21
P26
P31
P30
Figure 3.Pin Assignments 48-Pin DIP
30
TIMING
AND
CONTROL
31
XTAL1
13
38
48
AS
XTAL2
12
22
45
44
43
42
41
1
2
3
4
5
6
7
8
36
PORT 4
(1/2)
11
34
DS
46
PORT 1
+5V
GND
37
47
PORT 0
RESET
R/W
35
33
32
P00
P20
P01
P21
P02
P22
P03
P23
P04
P24
P05
P25
10
P26
26
P27
27
P06
P07
SUPER8
18
21
9
25
P11
P31
24
P12
P32
19
P13
P33
20
P14
P34
P15
P35
P16
P36
P17
P40
P37
P41
P45
P42
P46
P43
P47
P44
CLOCK
23
P30
P10
POWER
40
39
PORT 2
PORT 3
29
28
14
15
16
PORT 4
(1/2)
17
Figure 4.Pin Functions 48-Pin DIP
PS014602-0103
GENERAL DESCRIPTION
CMOS Super8 ROMless MCU
Product Specification
4
+5
1
28
+5
A12
2
27
+5
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
D7
D0
11
18
D6
D1
12
17
D5
D2
13
16
D4
GND
14
15
D3
PROTOPACK
EPROM
SOCKET
Figure 5.Pin Assignments 28-Pin Piggyback Socket
DATA
D0
A0
D1
A1
D2
A2
D3
A3
D4
A4
A5
D5
D6
D7
OE
GND
CE
GND
POWER
PROTOPACK
EPROM
SOCKET
A6
A7
ADDRESS
A8
A9
A10
+5V
A11
+5V
A12
+5V
A13
Figure 6.Pin Functions 28-Pin Piggyback Socket
Protopack
This part functions as an emulator for the basic microcomputer. It uses the same
package and pin-out as the basic microcomputer but also has a 28-pin "piggy
back" socket on the top into which a ROM or EPROM can be installed. The socket
is designed to accept a type 2764 EPROM.
This package permits the protopack to be used in prototype and final PC boards
while still permitting user program development. When a final program is devel-
PS014602-0103
GENERAL DESCRIPTION
CMOS Super8 ROMless MCU
Product Specification
5
oped, it can be mask-programmed into the production microcomputer device,
directly replacing the emulator. The protopack part is also useful in situations
where the cost of mask-programming is prohibitive or where program flexibility is
desired.
I/O
(BIT PROGRAMMABLE)
XTAL AS DS R/W RESET
DMA
MACHINE TIMING AND
INSTRUCTION CONTROL
PORT 4
UART
ALU
FLAGS
COUNTER/
TIMERS
(2)
INTERRUPT
CONTROL
PORT 3
PORT 2
Z8822
EPROM
INTERFACE
REGISTER
POINTERS
ADDRESS
14
8
DATA
PROGRAM
COUNTER
REGISTER FILE
272 X 8-BIT
PORT 0
PORT 1
8
I/O
(BIT PROGRAMMABLE
OR CONTROL)
ADDRESS OR I/O
(BIT PROGRAMMABLE)
ADDRESS/DATA OR I/O
(BYTE PROGRAMMABLE)
2-BUS WHEN USES AS
ADDRESS/DATA BUS
Figure 7.Functional Block Diagram
ARCHITECTURE
The Super8 architecture includes 325 byte-wide internal registers. 272 of these
are available for general purpose use; the remaining 53 provide control and mode
functions.
The instruction set is specially designed to deal with this large register set. It
includes a full complement of 8-bit arithmetic and logical operations, including
multiply and divide instructions and provisions for BCD operations. Addresses and
counters can be incremented and decremented as 16-bit quantities. Rotate, shift,
and bit manipulation instructions are provided. Three new instructions support
threaded-code languages. The UART is a full-function multipurpose asynchronous serial channel with many premium features.
PS014602-0103
ARCHITECTURE
CMOS Super8 ROMless MCU
Product Specification
6
The 16-bit counters can operate independently or be cascaded to perform 32-bit
counting and timing operations. The DMA controller handles transfers to and from
the register file or memory. DMA can use the UART or one of two ports with handshake capability.
The architecture appears in the block diagram (Figure 7).
PIN DESCRIPTIONS
The Super8 connects to external devices via the following TTL-compatible pins:
AS. Address Strobe (output, active Low). AS is pulsed Low once at the beginning
of each machine cycle. The rising edge indicates that addresses R/W and DM,
when used, are valid.
DS. Data Strobe (output, active Low). DS provides timing for data movement
between the address/data bus and external memory. During write cycles, data
output is valid at the leading edge of DS. During read cycles, data input must be
valid prior to the trailing edge of DS.
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47. Port I/O Lines (input/output).
These 40 lines are divided into five 8-bit I/O ports that can be configured under
program control for I/O or external memory interface.
In the ROMless devices, Port 1 is dedicated as a multiplexed address/data port,
and Port 0 pins can be assigned as additional address lines; Port 0 non-address
pins may be assigned as I/O. In the ROM and protopack, Port 1 can be assigned
as input or output, and Port 0 can be assigned as input or output on a bit by bit
basis.
Ports 2 and 3 can be assigned on a bit-for-bit basis as general I/O or interrupt
lines. They can also be used as special-purpose I/O lines to support the UART,
counter/timers, or handshake channels.
Port 4 is used for general I/O.
During reset, all port pins are configured as inputs (high impedance) except for
Port 1 and Port 0 in the ROMless devices. In these, Port 1 is configured as a multiplexed address/data bus, and Port 0 pins PO0-PO4 are configured as address
out, while pins P05-PO7 are configured as inputs.
RESET. Reset (input, active Low). Reset initializes and starts the Super8. When it
is activated, it halts all processing; when it is deactivated, the Super8 begins processing at address 0020H.
ROMless. (input, active High). This input controls the operation mode of a 68-pin
Super8. When connected to VCC, the part functions as a ROMless Z8800. When
connected to GND, the part functions as a Z8820 ROM part.
PS014602-0103
PIN DESCRIPTIONS
CMOS Super8 ROMless MCU
Product Specification
7
R/W. ReadlWrite (output). R/W determines the direction of data transfer for external memory transactions. It is Low when writing to program memory or data memory, and High for everything else.
XTAL1, XTAL2. (Crystal oscillator input.) These pins connect a parallel resonant
crystal or an external clock source to the on-board clock oscillator and buffer.
REGISTERS
The Super8 contains a 256-byte internal register space. However, by using the
upper 64 bytes of the register space more than once, a total of 325 registers are
available.
Registers from 00 to BF are used only once. They can be accessed by any register command. Register addresses C0 to FF contain two separate sets of 64 registers. One set, called control registers, can only be accessed by register direct
commands. The other set can only be addressed by register indirect, indexed,
stack, and DMA commands.
The uppermost 32 register direct registers (E0 to FF) are further divided into two
banks (0 and 1), selected by the Bank Select bit in the Flag register. When a Register Direct command accesses a register between E0 and FF, it looks at the Bank
Select bit in the Flag register to select one of the banks.
The register space is shown in Figure 8.
PS014602-0103
REGISTERS
CMOS Super8 ROMless MCU
Product Specification
8
Set One
FFH
Mode and
Control Registers
(Register Addressing Only)
EOH
DFH
DOH
CFH
COH
Set Two
FFH
Bank1
Bank0
Data Registers
(Indirect Register, Indexed,
Stack or DMA
Access Only)
System Registers:
Stack, Flags, Ports, Etc.
(Register Addressing Only)
Working Registers
(Working Register
Addressing Only)
COH
256
Bytes
BFH
Data Registers
(All Addressing Modes)
192
Bytes
OOH
Figure 8.Super8 Registers
Working Register Window
Control registers R214 and R215 are the register pointers, RPO and RP1. They
each define a moveable, 8-register section of the register space. The registers
within these spaces are called working registers.
Working registers can be accessed using short 4-bit addresses. The process,
shown in section a of Figure 9, works as follows:
•
The high-order bit of the 4-bit address selects one of the two register pointers
(0 selects RPO; 1 selects RP1).
•
The five high-order bits in the register pointer select an 8-register (contiguous)
slice of the register space.
•
The three low-order bits of the 4-bit address select one of the eight registers in the
slice.
The net effect is to concatenate the five bits from the register pointer to the three
bits from the address to form an 8-bit address. As long as the address in the regis-
PS014602-0103
REGISTERS
CMOS Super8 ROMless MCU
Product Specification
9
ter pointer remains unchanged, the three bits from the address always point to an
address within the same eight registers.
The register pointers can be moved by changing the five high bits in control registers R214 for RP0 and R215 for RP1.
The working registers can also be accessed by using full 8-bit addressing. When
an 8-bit logical address in the range 192 to 207 (CO to CF) is specified, the lower
nibble is used similarly to the 4-bit addressing described above. This is shown in
section b of Figure 9.
RP0 (R214)
RP0 (R214)
RP1 (R215)
Selects
RP0 or RP1
Address
Opcode
RP1 (R215)
Selects
RP0 or RP1
1
Address
1
0
8-Bit
Logical Address
0
4-Bit Addess Provides 3 Low-Order Bits
3 Low-Order Bits
Register Pointer Provides
5 High-Order Bits
Register Pointer Provides
5 Low-Order Bits
Together they Create
8-Bit Register Address
a. 4-Bit Addressing
8-Bit Physical Address
b. 8-Bit Addressing
Figure 9.Working Register Window
Since any direct access to logical addresses 192 to 207 involves the register
pointers, the physical registers 192 to 207 can be accessed only when selected
by a register pointer. After a reset, RPO points to R192 and RP1 points to R200.
Register List
Super-8 Registers lists the Super8 registers. For more details, see Figure 10.
PS014602-0103
REGISTERS
CMOS Super8 ROMless MCU
Product Specification
10
Table 15.Super-8 Registers
Address
Decimal
Hexadecimal
Mnemonic
Function
General-Purpose Registers
000-192
00-BF
-
General purpose (all address modes)
192-207
C0-CF
-
Working register (direct only)
192-255
C0-FF
-
General purpose (indirect only)
Mode and Control Registers
208
D0
P0
Port 0 I/O bits
209
DI
P1
Port 1 (I/O only)
210
D2
P2
Port 2
211
D3
P3
Port 3
212
D4
P4
Port 4
213
D5
FLAGS
System Flags Register
214
D6
RP0
Register Pointer 0
215
D7
RP1
Register Pointer 1
216
D8
SPH
Stack Pointer High Byte
217
D9
SPL
Stack Pointer Low Byte
218
DA
IPH
Instruction Pointer High Byte
219
DB
IPL
Instruction Pointer Low Byte
220
DC
IRQ
Interrupt Request
221
DD
IMR
Interrupt Mask Register
222
DE
SYM
System Mode
224
E0
Bank 0
C0CT
CTR 0 Control
Bank 1
COM
CTR 0 Mode
Bank 0
C1CT
CTR 1 Control
Bank 1
C1M
CTR 1 Mode
Bank 0
C0CH
CTR 0 Capture Register, bits 8-15
Bank 1
CTCH
CTR 0 Timer Constant, bits 8-15
Bank 0
C0CL
CTR 0 Capture Register, bits 0-7
225
226
227
E1
E2
E3
PS014602-0103
REGISTERS
CMOS Super8 ROMless MCU
Product Specification
11
Table 15.Super-8 Registers (Continued)
Address
Decimal
228
229
Hexadecimal
E4
E5
Mnemonic
Function
Bank 1
CTCL
CTR 0 Time Constant, bits 0-7
Bank 0
C1CH
CTR 1 Capture Register, bits 8-15
Bank 1
C1TCH
CTR 1 Time Constant, bits 8-15
Bank 0
C1CL
CTR 1 Capture Register, bits 0-7
Bank 1
C1TCL
CTR 1 Time Constant, bits 0-7
235
EB
Bank 0
UTC
UART Transmit Control
236
EC
Bank 0
URC
UART Receive Control
237
ED
Bank 0
UIE
UART Interrupt Enable
239
EF
Bank 0
UIO
UART Data
240
F0
Bank 0
POM
Port 0 Mode
Bank 1
DCH
DMA Count, bits 8-15
Bank 0
PM
Port Mode Register
Bank 1
DCL
DMA Count, bits 0-7
241
F1
244
F4
Bank 0
HOC
Handshake Channel 0 Control
245
F5
Bank 0
H1C
Handshake Channel I Control
246
F6
Bank 0
P4D
Port 4 Direction
247
F7
Bank 0
P40D
Port 4 Open Drain
248
F8
Bank 0
P2AM
Port 2/3 A Mode
Bank 1
UBGH
UART Baud Rate Generator, bits 8-15
Bank 0
P2BM
Port 2/3 B Mode
Bank 1
UBGL
UART Baud Rate Generator, bits 0-7
Bank 0
P2CM
Port 2/3 C Mode
Bank 1
UMA
UART Mode A
Bank 0
P2DM
Port 2/3 D Mode
Bank 1
UMB
UART Mode B
249
250
251
F9
FA
FB
252
FC
Bank 0
P2AIP
Port 2/3 A Interrupt Pending
253
FD
Bank 0
P2BIP
Port 2/3 B Interrupt Pending
254
FE
Bank 0
EMT
External Memory Timing
PS014602-0103
REGISTERS
CMOS Super8 ROMless MCU
Product Specification
12
Table 15.Super-8 Registers (Continued)
Address
Decimal
255
Hexadecimal
FF
Mnemonic
Function
Bank 1
WUMCH
Wakeup Match Register
Bank 0
IPR
Interrupt Priority Register
Bank 1
WUMSK
Wakeup Match Register
MODE AND CONTROL REGISTERS
R213 (D5) Flags
System Flags Register
R218 (DA) IPH
Instruction Pointe High
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Carry Flag
Bank Address
Zero Flag
Fast Interrupt Status
Sign Flag
Half-Carry Flag
Overflow Flag
Decimal Adjust
High Byte (IP8–IP15)
R219 (DB) IPL
Instruction Pointer Low
D7 D6 D5 D4 D3 D2 D1 D0
R214 (D6) RP0
Register Pointer 0
Low Byte (IP0–IP7)
D7 D6 D5 D4 D3 D2 D1 D0
(RP3–RP7)
Not Used
R220 (DC) IRQ
Interrupt Request (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
R215 (D7) RP1
Register Pointer 1
D7 D6 D5 D4 D3 D2 D1 D0
(RP3–RP7)
Not Used
Level 7
Level 0
Level 6
Level 1
Level 5
Level 2
Level 4
Level 3
R216 (D8) SPH
Stack Pointer
R221 (DD) IMR
Interrupt Mask
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
High Byte (SP8–SP15)
R217 (D9) SPL
Stack Pointer
D7 D6 D5 D4 D3 D2 D1 D0
Level 7
Level 0
Level 6
Level 1
Level 5
Level 2
Level 4
Level 3
Low Byte (SP0–SP7)
Figure 10.Mode and Control Registers
PS014602-0103
MODE AND CONTROL REGISTERS
CMOS Super8 ROMless MCU
Product Specification
13
R222 (DE) Sym
System Mode
D7 D6 D5 D4 D3 D2 D1 D0
1 = Global Interrupt Enable
Not Used
1 = Fast Interrupt Enable
Fast Interrupt Select
000 Level 0
001 Level 1
010 Level 2
011 Level 3
100 Level 4
001 Level 5
110 Level 6
111 Level 7
R224, Bank 0 (E0) C0CT
Counter 0 Control
D7 D6 D5 D4 D3 D2 D1 D0
0 = Single Cycle
1 = Continuous
1 = Enable Counter
Read 1 = End of Count
Write 1 = Reset End of Count
0 = Count Down
1 = Count Up
1 = Zero Count Interrupt Enable
1 = Load Counter
1 = Software Capture
1 = Software Trigger
R224 Bank 1 (E0) C0M
Counter 0 Mode
D7 D6 D5 D4 D3 D2 D1 D0
Input Pin Assignments
D7 D6D5 D4 P27
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Capture Mode
00 = No Capture
01 = Capture on Rising
Edge of P27
10 = Bi-Value Mode
11 = Capture on Both
Edges of P27
0 = External
Up/Down Control P27
1 = Programmed
Up/Down Control
1 = Enable Retrigger
P26
I/O
I/O
I/O
Trigger
Gate
I/O
Trigger
Gate
I/O
C0 Output
Trigger
C0 Output
C0 Output
Gate
Gate/
C0 Output
Trigger
C0 Output I/O
C0 Output Trigger
C0 Output Gate
C0 Output Gate/Trigger
C0 Output C0 Output
—Undefined—
—Undefined—
— Cascade Counters—
R225, Bank 0 (E1) C1CT
Counter 1 Control
D7 D6 D5 D4 D3 D2 D1 D0
0 = Single Cycle
1 = Continuous
0 = Count Down
1 = Count Up
1 = Load Counter
1 = Enable Counter
Read 1 = End of Count
Write 1 = Reset End of Count
1 = Zero Count Interrupt Enable
1 = Software Capture
1 = Software Trigger
Figure 11.Mode and Control Registers (Continued)
PS014602-0103
MODE AND CONTROL REGISTERS
CMOS Super8 ROMless MCU
Product Specification
14
R225 Bank 1 (E1) C1M
Counter 1 Mode
D7 D6 D5 D4 D3 D2 D1 D0
Input Pin Assignments
D7 D6D5 D4 P37
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
P36
I/O
Trigger
I/O
Trigger
C0 Input
C0 Input
C0 Input
I/O
I/O
Gate
Gate
I/O
Trigger
Gate
Gate/
C0 Input
Trigger
C0 Output I/O
C0 Output Trigger
C0 Output Gate
Gate/Trigger
C0 Output
C0 Output C0 Output
—Undefined—
—Undefined—
—Undefined—
Capture Mode
00 = No Capture
01 = Capture on Rising
Edge of P37
10 = Bi-Value Mode
11 = Capture on Both
Edges of P37
0 = External
Up/Down Control P37
1 = Programmed
Up/Down Control
1 = Enable Retrigger
R226 Bank 0 (E2) C0CH
Counter 0 Capture
R229 Bank 0 (E5) C1CL
Counter 1 Capture
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Low Byte (C1C0–C1C7)
High Byte (C0C8–C0C15)
R226 Bank 1 (E2) C0TCH
Counter 0 Time Constant
R229 Bank 1 (E5) C1TCL
Counter 1 Time Constant
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Low Byte (C1TC0–C1TC7)
High Byte (C0TC8–C0TC15)
R235 Bank 0 (E8) UTC
UART Transmit Control
R227 Bank 0 (E3) C0CL
Counter 0 Capture
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Low Byte (C0TC0–C1TC7)
Transmit Data Select
0 = Output P31 Data
1 = Output Transmit Data
1 = Transmit DMA Enable
1 = Transmit Buffer Empty
1 = Send Break
R227 Bank 1 (E4) C0TCL
Counter 0 Time Constant
1 = Zero Count
Stop Bits:
0 = 1 Stop Bit
1 = 2 Stop Bits
D7 D6 D5 D4 D3 D2 D1 D0
1 = Transmit Enable
1 = Wake-up Enable
Low Byte (C0TC0–C0TC7)
R228 Bank 0 (E4) C1CH
Counter 1 Capture
R236 Bank 0 (EC) URC
UART Receive Control
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
High Byte (C1C8–C1C15)
1 = Wake-Up Detect
1 = Control Character Detect
1 = Break Detect
R228 Bank 1 (E4) C1TCH
Counter 1 Time Constant
1 = Framing Error
1 = Receive Character
Available
1 = Receive Enable
1 = Parity Error
1 = Overrun Error
D7 D6 D5 D4 D3 D2 D1 D0
High Byte (C1TC8–C1TC15)
Figure 12.Mode and Control Registers (Continued)
PS014602-0103
MODE AND CONTROL REGISTERS
CMOS Super8 ROMless MCU
Product Specification
15
R237 Bank 0 (ED) UIE
UART Interrupt Enable
D7 D6 D5 D4 D3 D2 D1 D0
1 = Receive Character
Available Interrupt Enable
1 = Receive DMA Enable
1 = Wake-Up Interrupt Enable
1 = Control Character
Interrupt Enable
1 = Break Interrupt Enable
1 = Transmit Interrupt Enable
1 = Zero Count Interrupt Enable
1 = Receive Error Interrupt
Enable
R244 Bank 0 (F4) H0C
Handshake 0 Control (Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
R229 Bank 0 (EF) UIO
UART Transmit Data (Write)
UART Receive Data (Read)
1 = Handshake Enable
Deskew Counter
(Range 1-16)
Port Select:
1 = Port 1; 0 = Port 4
D7 D6 D5 D4 D3 D2 D1 D0
DMA Enable:
1 = Enabled
0 = Disabled
Data (D0 = LSB)
Mode:
1 = Fully Interlocked
0 = Strobed
R240 Bank 0 (F0) P0M
Port 0 Mode
D7 D6 D5 D4 D3 D2 D1 D0
R245 Bank 0 (F5) H1C
Handshake 1 Control (Write Only)
P07 Mode
P00 Mode
P06 Mode
P01 Mode
P05 Mode
P02 Mode
P04 Mode
P03 Mode
D7 D6 D5 D4 D3 D2 D1 D0
1 = Handshake Enable
Deskew Counter
(Range 1-16)
Not Used
Mode:
1 = Fully Interlocked
0 = Strobed
0 = I/O; 1 = Address
R240 Bank 1 (F0) DCH
DMA Count
R246 Bank 0 (F6) P4D
Port 4 Direction
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
High Byte (DC8 -DC15)
P40 -P47 I/O Direction
0 = Output; 1 = Input
R241 Bank 0 (F1) PM
Port Mode (Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
R247 Bank 0 (F7) P4OD
Port 4 Open-Drain
Port 0 Direction
0 = Output
1 = Input
Not Used
Port 1 Mode
00 Output
01 Input
0x Address/Data
D7 D6 D5 D4 D3 D2 D1 D0
Open-Drain Port 0
0 = Push-Pull
1 = Open-Drain
Open-Drain Port 1
0 = Push-Pull
1 = Open-Drain
R241 Bank 1 (F1) DCL
DMA Count
Enable DM P35
0 = Disable
1 = Enable
P40 -P47 Open-Drain
0 = Push-Pull; 1 = Open-Drain
R248 Bank 0 (F8) P2AM
Port 2/3 A Mode (Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P31 Mode
P20 Mode
P30 Mode
D7 D6 D5 D4 D3 D2 D1 D0
Low Byte (DC0 -DC7)
P21 Mode
00
01
10
11
Input
Input, Interrupt Enabled
Output, Push-Pull
Output, Open-Drain
Figure 13. Mode and Control Registers (Continued)
PS014602-0103
MODE AND CONTROL REGISTERS
CMOS Super8 ROMless MCU
Product Specification
16
R250 Bank 0 (FA) P2CM
Port 2/3 C Mode (Write Only)
R248 Bank 1 (F8 UBGH
UART Baud Rate Generator
D7
D6
D5
D4
D3
D2
D1
D0
D7 D6 D5 D4 D3 D2 D1 D0
P35 Mode
P24 Mode
High Byte (UBGH8–UBGH15)
P34 Mode
P25 Mode
00
01
10
11
R249 Bank 0 (F9) P2BM
Port 2/3 B Mode (Write Only)
D7
D6
D5
D4
D3
D2
P33Mode
D1
D0
R250 Bank 1 (FA) UMA
UART Mode A
P22 Mode
P32 Mode
D7
P23 Mode
00
01
10
11
Input
Input, Interrupt Enabled
Output, Push-Pull
Output, Open-Drain
Input
Input, Interrupt Enabled
Output, Push-Pull
Output, Open-Drain
D6 D5 D4
D3
D2
D1
D0
Transmit Wake-Up Value
Clock Rate
D7 D6
00
01
10
11
R249 Bank 1 (F9) UBGL
UART Baud Rate Generator
Receive Wake-Up Value
= 5 Bits
= 6 Bits
= 7 Bits
= 8 Bits
1 = Even Parity
1 = Parity Enable
Bits Per Character
D5 D4
D7 D6 D5 D4 D3 D2 D1 D0
00
01
10
11
Low Byte (UBG0–UBG7)
= X1
= X16
= X32
= X64
R251 Bank 0 (FB) P2DM
Port 2/3 D Mode (Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
P37 Mode
P26 Mode
P36 Mode
P27 Mode
00
01
10
11
Input
Input, Interrupt Enabled
Output, Push-Pull
Output, Open-Drain
R251 Bank 1 (FB) UMB
UART Mode B
D7
D6 D5 D4
Clock Output Select
D7 D6
0 0 = P21 Data
0 1 = System Clock (XTAL2)
1 0 = Baud-Rate Generator Output
1 1 = Transmit Data Clock
1 = Auto-Echo
Receive Clock Input Select:
0 = P20
1 = Baud-Rate Generator
Output
D3
D2
D1
D0
1 = Loopback Enable
1 = Baud-Rate Generator Enable
Baud-Rate Generator Source:
0 = P20 (External)
1 = Internal (XTAL/4)
Transmit Clock Input Select:
0 = P21
1 = Baud-Rate Generator Output
Figure 14.Mode and Control Registers (Continued)
PS014602-0103
MODE AND CONTROL REGISTERS
CMOS Super8 ROMless MCU
Product Specification
17
R252 Bank 0 (FC) P2AIP
Port 2/3 A Interrupt Pending (Read Only)
R254 Bank 1 (FE) WUMCH
Wake-Up Match Register
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
P34
P20
P32
P21
P23
P30
P22
P31
This Byte, Minus Masked Bits,
Is Used For Wake-Up Match
R255 Bank 0 (FF) IPR
Interrupt Priority Register
D7
D6 D5 D4
D3
Group Priority
R253 Bank 0 (FD) P2 BIP
Port 2/3 B Interrupt Pending (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
P37
P24
P36
P25
P27
P34
P26
P35
D7 D4 D1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
= Undefined
= B>C>A
= A>B>C
= B>A>C
= C>A>B
= C>B>A
= A>C>B
= Undefined
D2
D1
D0
Group A
0 = IRQ0 > IRQ1
1 = IRQ1 > IRQ0
Group B
0 = IRQ2 > (IRQ3, IRQ4)
1 = (IRQ3, IRQ4) > IRQ2
Subgroup B
0 = IRQ3 > IRQ4
1 = IRQ4 > IRQ3
Group C
0 = IRQ5 > (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) > IRQ5
Subgroup C
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
R254 Bank 0 (FE) EMT
External Memory Timing Register
D7
D6 D5 D4
D3
D2
D1
R255 Bank 1 (FF) WUMSK
Wake-Up Match Register
D0
D7 D6 D5 D4 D3 D2 D1 D0
DMA Select:
0 = Register File
1 = Data Memory
These Bits Correspond to Bits
In Wake-Up Match Register; 0s
Mask Corresponding Match Bits
Stack Select:
0 = Register File
1 = Data Memory
Data Memory Automatic Waits
00 = No Waits
10 = 1 Wait
10 = 2 Waits
11 = 3 Waits
Program Memory Automatic Waits
00 = No Waiits
01 = 1 Wait
10 = 2 Waits
11 = 3 Waits
Slow Memory Timing
0 = Disabled
1 = Enabled
External Wait Input
0 =P34 is normal I/O
1 =P34 is External Wait Input
Figure 15.Mode and Control Registers (Continued)
I/O PORTS
The Super8 has 40 I/O lines arranged into five 8-bit ports. These lines are all TTLcompatible, and can be configured as inputs or outputs. Some can also be configured as address/data lines.
PS014602-0103
I/O PORTS
CMOS Super8 ROMless MCU
Product Specification
18
Each port has an input register, an output register, and a register address. Data
coming into the port is stored in the input register, and data to be written to a port
is stored in the output register. Reading a port’s register address returns the value
in the input register; writing a port’s register address loads the value in the output
register. If the port is configured for an output, this value appears on the external
pins.
When the CPU reads the bits configured as outputs, the data on the external pins
is returned. Under normal output loading, this has the same effect as reading the
output register, unless the bits are configured as open-drain outputs.
The ports can be configured as shown in Table 2, Port Configuration.
Table 16.Port Configuration
Port
Configuration Choices
0
Address outputs and/or general I/O
1
Multiplexed address/data (or I/O, only for ROM and Protopack)
2 and 3 Control I/O for UART, handshake channels, and counter/timers;
also general I/O and external interrupts
4
General I/O
Port 0
Port 0 can be configured as an I/O port or an output for addressing external memory, or it can be divided and used as both. The bits configured as I/O can be either
all outputs or all inputs; they cannot be mixed. If configured for outputs, they can
be push-pull or open-drain type.
Any bits configured for I/O can be accessed via R208. To write to the port, specify
R208 as the destination (dst) of an instruction; to read the port, specify R208 as
the source (src).
Port 0 bits configured as I/O can be placed under handshake control of handshake channel 1.
Port 0 bits configured as address outputs cannot be accessed via the register.
In ROMless devices, initially the four lower bits are configured as address eight
through twelve.
PS014602-0103
I/O PORTS
CMOS Super8 ROMless MCU
Product Specification
19
Port 1
In the ROMless device, Port 1 is configured as a byte-wide address/data port. It
provides a byte-wide multiplexed address/data path. Additional address lines can
be added by configuring Port 0.
The ROM and Protopack Port 1 can be configured as above or as an I/O port; it
can be a byte-wide input, open-drain output, or push-pull output. It can be placed
under handshake control or handshake channel 0.
Ports 2 and 3
Ports 2 and 3 provide external control inputs and outputs for the UART, handshake channels, and counter/timers. The pin assignments appear in Table 3.
Bits not used for control I/O can be configured as general-purpose I/O lines and/or
external interrupt inputs.
Those bits configured for general I/O can be configured individually for input or
output. Those configured for output can be individually configured for open-drain
or push-pull output.
All Port 2 and 3 input pins are Schmitt-triggered.
The port address for Port 2 is R210, and for Port 3 is R211.
Table 17.Pin Assignments for Ports 2 and 3
Port 2
PS014602-0103
Port 3
Bit
Function
Bit
Function
0
UART receive clock
0
UART receive data
1
UART transmit clock
1
UART transmit data
2
Reserved
2
Reserved
3
Reserved
3
Reserved
4
Handshake 0 input
4
Handshake 1 input/WAIT
5
Handshake 0 output
5
Handshake 1 output/DM
6
Counter 0 input
6
Counter 1 input
7
Counter 0 I/O
7
Counter 1 I/O
I/O PORTS
CMOS Super8 ROMless MCU
Product Specification
20
Port 4
Port 4 can be configured as I/O only. Each bit can be configured individually as
input or output, with either push-pull or open-drain outputs. All Port 4 inputs are
Schmitt-triggered.
Port 4 can be placed under handshake control of handshake channel 0. Its register address is R212.
UART
The UART is a full-duplex asynchronous channel. It transmits and receives independently with 5 to 8 bits per character, has options for even or odd bit parity, and
a wake-up feature.
Data can be read into or out of the UART via R239, Bank 0. This single address is
able to serve a full-duplex channel because it contains two complete 8-bit registers-one for the transmitter and the other for the receiver.
Pins
The UART uses the following Port 2 and 3 pins:
Port/Pin
UART Function
2/0
Receive Clock
3/0
Receive Data
2/1
Transmit Clock
3/1
Transmit Data
Transmitter
When the UART’s register address is specified as the destination (dst) of an operation, the data is output on the UART, which automatically adds the start bit, the
programmed parity bit, and the programmed number of stop bits. It can also add a
wake-up bit if that option is selected.
If the UART is programmed for a 5-, 6-, or 7-bit character, the extra bits in R239
are ignored.
Serial data is transmitted at a rate equal to 1, 1/16, 1/32 or 1/64 of the transmitter
clock rate, depending on the programmed data rate. All data is sent out on the falling edge of the clock input.
PS014602-0103
I/O PORTS
CMOS Super8 ROMless MCU
Product Specification
21
When the UART has no data to send, it holds the output marking (High). It may be
programmed with the Send Break command to hold the output Low (Spacing),
which it continues until the command is cleared.
Receiver
The UART begins receive operation when Receive Enable (URC, bit 0) is set
High. After this, a Low on the receive input pin for longer than half a bit time is
interpreted as a start bit. The UART samples the data on the input pin in the middle of each clock cycle until a complete byte is assembled. This is placed in the
Receive Data register.
If the 1 X clock mode is selected, external bit synchronization must be provided,
and the input data is sampled on the rising edge of the clock.
For character lengths of less than eight bits, the UART inserts ones into the
unused bits, and, if parity is enabled, the parity bit is not stripped. The data bits,
extra ones, and the parity bit are placed in the UART Data register (UIO).
While the UART is assembling a byte in its input shift register, the CPU has time to
service an interrupt and manipulate the data character in UIO.
Once a complete character is assembled, the UART checks it and performs the
following:
•
•
•
If it is an-ASCII control character, the UART sets the Control Character status bit.
•
It sets the Framing Error bit (URC, bit 4) if the character is assembled without any
stop bits. This bit remains set until cleared by software.
It checks the wake-up settings and completes any indicated action.
If parity is enabled, the UART checks to see if the calculated parity matches the
programmed parity bit. If they do not match, it sets the Parity Error bit in URC
(R236 Bank 0), which remains set until reset by software.
Overrun errors occur when characters are received faster than they are read. That
is, when the UART has assembled a complete character before the CPU has read
the current character, the UART sets the Overrun Error bit (URC, bit 3), and the
character currently in the receive buffer is lost.
The overrun bit remains set until cleared by software.
ADDRESS SPACE
The Super8 can access 64K bytes of program memory and 64K bytes of data
memory. These spaces can be either combined or separate. If separate, they are
PS014602-0103
ADDRESS SPACE
CMOS Super8 ROMless MCU
Product Specification
22
controlled by the DM line (Port P35), which selects data memory when Low and
program memory when High.
Figure 16 on page 23 shows the system memory space.
CPU Program Memory
Program memory occupies addresses 0 to 64K. External program memory, if
present, is accessed by configuring Ports 0 and 1 as a memory interface.
The address/data lines are controlled by AS, DS and R/W.
The first 32 program memory bytes are reserved for interrupt vectors; the lowest
address available for user programs is 32 (decimal). This value is automatically
loaded into the program counter after a hardware reset.
ROMless
Port 0 can be configured to provide from 0 to 8 additional address lines. Port 1 is
always used as an 8-bit multiplexed address/data port.
ROM and Protopack
Port 1 is configured as multiplexed address/data or as I/O. When Port 1 is configured as address/data, Port 0 lines can be used as additional address lines, up to
address 15. External program memory is mapped above internal program memory; that is, external program memory can occupy any space beginning at the top
of the internal ROM space up to the 64K (16-bit address) limit.
CPU Data Memory
The external CPU data memory space, if separated from program memory by the
DM optional output, can be mapped anywhere from 0 to 64K (full 16-bit address
space). Data memory uses the same address/data bus (Port 1) and additional
addresses (chosen from Port 0) as program memory. Data memory is distinguished from program memory by the DM pin (P35), and by the fact that data
memory can begin at address OOOOH. This feature differs from the Z8.
PS014602-0103
ADDRESS SPACE
CMOS Super8 ROMless MCU
Product Specification
23
65535
65535
EXTERNAL
PROGRAM
MEM0RY
This Boundary
May be at 0, or
8192 Depending On
ROM Size
32
0
INTERRUPT VECTORS
PROGRAM MEMORY
EXTERNAL
DATA
MEM0RY
On-Chip
ROM or
Protopack
EPROM
DATA MEMORY
Figure 16.Program and Data Memory Address Spaces
INSTRUCTION SET
The Super8 instruction set is designed to handle its large register set. The instruction set provides a full complement of 8-bit arithmetic and logical operations,
including multiply and divide. It supports BCD operations using a decimal adjustment of binary values, and it supports incrementing and decrementing 16-bit
quantities for addresses and counters.
It provides extensive bit manipulation, and rotate and shift operations, and it
requires no special I/O instructions-the I/O ports are mapped into the register file.
Instruction Pointer
A special register called the Instruction Pointer (IP) provides hardware support for
threaded-code languages. It consists of register-pair R218 and R219, and it contains, memory addresses. The MSB is R218.
Threaded-code languages deal with an imaginary higher-level machine within the
existing hardware machine. The IP acts like the PC for that machine. The command NEXT passes control to or from the hardware machine to the imaginary
machine, and the commands ENTER and EXIT are imaginary machine equivalents of (real machine) CALLS and RETURNS.
If the commands NEXT, ENTER, and EXIT are not used, the IP can be used by
the fast interrupt processing, as described in the Interrupts section.
PS014602-0103
INSTRUCTION SET
CMOS Super8 ROMless MCU
Product Specification
24
Flag Register
The Flag register (FLAGS) contains eight bits that describe the current status of
the Super8. Four of these can be tested and used with conditional jump instructions; two others are used for BCD- arithmetic. FLAGS also contains the Bank
Address bit and the Fast Interrupt Status bit.
The flag bits can be set and reset by instructions.
Caution: Do not specify FLAGS as the destination of an instruction
that normally affects the flag bits or the result is unspecified.
The following paragraphs describe each flag bit:
Bank Address. This bit is used to select one of the register banks (0 or 1)
between (decimal) addresses 224 and 255. It is cleared by the SBO instruction
and set by the SB1 instruction.
Fast Interrupt Status. This bit is set during a fast interrupt cycle and reset during
the IRET following interrupt servicing. When set, this bit inhibits all interrupts and
causes the fast interrupt return to be executed when the IRET instruction is
fetched.
Half-Carry. This bit is set to 1 whenever an addition generates a carry out of bit 3,
or when a subtraction borrows out of bit 4. This bit is used by the Decimal Adjust
(DA) instruction to convert the binary result of a previous addition or subtraction
into the correct decimal (BCD) result. This flag, and the Decimal Adjust flag, are
not usually accessed by users.
Decimal Adjust. This bit is used to specify what type of instruction was executed
last during BCD operations, so a subsequent Decimal Adjust operation can function correctly. This bit is not usually accessible to programmers, and cannot be
used as a test condition.
Overflow Flag. This flag is set to 1 when the result of a twos-complement operation was greater than 127 or less than -128. It is also cleared to O during logical
operations.
Sign Flag. Following arithmetic, logical, rotate, or shift operations, this bit identifies the state of the MSB of the result. A 0 indicates a positive number and a 1
indicates a negative number.
Zero Flag. For arithmetic and logical operations, this flag is set to 1 if the result of
the operation is zero.
For operations that test bits in a register, the zero bit is set to 1 if the result is zero.
For rotate and, shift operations, this bit is set to 1 if the result is zero.
PS014602-0103
INSTRUCTION SET
CMOS Super8 ROMless MCU
Product Specification
25
Carry Flag. This flag is set to 1 if the result from an arithmetic operation generates
a carry out of, or a borrow into, bit 7.
After rotate and shift operations, it contains the last value shifted out of the specified register.
It can be set, cleared, or complemented by instructions.
Condition Codes
The flags C, Z, S, and V are used to control the operation of conditional jump
instructions.
The opcode of a conditional jump contains a 4-bit field called the condition code
(cc). This specifies under which conditions it is to execute the jump. For example,
a conditional jump with the condition code for "equal" after a compare operation
only jumps if the two operands are equal.
The condition codes and their meanings are given in Condition Codes and Meanings.
Addressing Modes
All operands except for immediate data and condition codes are expressed as
register addresses, program memory addresses, or data memory addresses. The
addressing modes and their designations are:
•
•
•
•
•
•
•
Register (R)
Indirect Register (IR)
Indexed (X)
Direct (DA)
Relative (RA)
Immediate (IM)
Indirect (IA)
Table 18.Condition Codes and Meanings
Binary
Mnemonic
Flags
Meaning
0000
F
-
Always false
1000
-
-
Always true
01111
C
C=1
Carry
1111
NC
C=0
No carry
1
PS014602-0103
INSTRUCTION SET
CMOS Super8 ROMless MCU
Product Specification
26
Table 18.Condition Codes and Meanings
Binary
Mnemonic
Flags
Meaning
01101
Z
Z=1
Zero
11101
NZ
Z=0
Not zero
1101
PL
S=0
Plus
0101
MI
S=1
Minus
0100
OV
V=1
Overflow
1100
NOV
V=0
No overflow
01101
EQ
Z=1
Equal
11101
NE
Z=0
Not equal
1001
GE
(S XOR V)= 0
Greater than or equal
0001
LT
(S XOR V)= 1
Less than
1010
GT
(Z OR (S XOR V))= 0
Greater than
0010
LE
(Z OR (S XOR V))= 1
Less than or equal
11111
UGE
C=0
Unsigned greater than or equal
01111
ULT
C=1
Unsigned less than
1011
UGT
(C = 0 AND Z = 0)= 1
Unsigned greater than
0011
ULE
(C OR Z)= 1
Unsigned less than or equal
1. Has condition codes that relate to two different mnemonics but test the same flags. For
example, Z and EQ are both True if the Zero flag is set, but after an ADD instruction, Z would
probably be used, while after a CP instruction, EQ would probably be used.
Registers can be addressed by an 8-bit address in the range of 0 to 255. Working,
registers can also be addressed using 4-bit addresses, where five bits contained
in a register pointer (R218 or R219) are concatenated with three bits from the 4-bit
address to form an 8-bit address.
Registers can be used in pairs to generate 16-bit program or data memory
addresses.
Notation and Encoding
The instruction set notations are described in Table 5.
PS014602-0103
INSTRUCTION SET
CMOS Super8 ROMless MCU
Product Specification
27
Functional Summary of Commands
Figure 17 shows the formats followed by a quick reference guide to the commands.
Table 19.Instruction Set Notations
Notation Meaning
Notation
Meaning
cc
Condition code (see Table 4)
DA Direct address (between 0 and
65535)
r
Working register (between 0 and 15)
RA Relative address
rb
Bit of working register
IM
Immediate
r0
Bit 0 of working register
IML
Immediate long
R
Register or working register
dst Destination operand
RR
Register pair or working register pair (Register pairs
always start on an even-number boundary)
@
src Source operand
IA
Indirect address
SP
Stack
Ir
Indirect working register
PC
Program
IR
Indirect register or indirect working register
Irr
Indirect working register pair
FLAGS
Flags
IRR
Indirect register pair or indirect working
register
pair
RP
X
Indexed
#
Immediate
XS
Indexed, short offset
%
Hexadecimal
XL
Indexed, long offset
OPC
Opcode
PS014602-0103
Indirect
IP
INSTRUCTION SET
CMOS Super8 ROMless MCU
Product Specification
28
One-Byte Instructions
OPC
OPC
dst
CCF, DI, EI, ENTER, EXIT, IRET, NEXT, NOP,
RCF, RET, SB0, SB1, SCF, WFI
INC
Two-Byte Instructions
OPC
dst
OPC
src
ADC, ADD, AND, CP, LD, LDC, LDCI, LDCD,
LDE, LDED, OR, SBC, SUB, TCM, TM, XOR
src
dst
LDC, LDCPD, LDCPI, LDE, LDEPD, LDEPI
OPC
dst
CALL, DA, DEC, DECW, INC, INCW, JP, POP,
RL, RLC,M RR, RRC, SWAP, CLR, SRA, COM
OPC
src
PUSH, SRP, SRP0, SRP1
dst
OPC
OPC
dst
b
0
BITC, BITR
b
1
BITS
r
OPC
dst
DJNZ
cc
OPC
dst
JR
dst
OPC
src
LD
src
OPC
dst
LD
Figure 17.Instruction Formats
Three-Byte Instructions
dst
OPC
src
OPC
OPC
dst
b
OPC
src
b
OPC
src
b
OPC
src
dst
ADC, ADD, AND, CP, LD, OR, PUSHUD,
PUSHUI, SBC, SUB, TCM, TM, XOR
dst
ADC, ADD, AND, CP, DIV, LD, LDW, MULT,
OR, POPUD, POPUI, SBC, SUB, TCM, TM, XOR
0
src
BAND, BCP, BOR, BXOR, DB
1
dst
BAND, BOR, BTJRT, BXOR, LDB
0
dst
BTJRF
RA
CPIJE, CPIJNE
OPC
OPC
dst
x
src
LD, LDC, LDE
OPC
src
x
dst
LD, LDC, LDE
OPC
cc
src
OPC
dst
CALL
dst
JP
Four-Byte Instructions
OPC
dst x¹0 or 1
src
src
LDC, LDE
OPC
src
dst
dst
LDC, LDE
OPC
dst
0000
src
src
LDC
OPC
src
0000
dst
dst
LDC
OPC
dst
0001
src
src
LDE
OPC
dst
0001
dst
dst
LDE
OPC
x¹0 or 1
dst
src
}
FOR LDC, x = EVEN
FOR LDE, x = ODD
LDW
Figure 18.Instruction Formats (Continued)
PS014602-0103
INSTRUCTION SET
CMOS Super8 ROMless MCU
Product Specification
29
INSTRUCTION SUMMARY
Table 20.Instruction Summary
Instruction
and Operation
ADC dst, src
Address Mode
dst
src
Flags Affected
Opcode
Byte (Hex) C
Z
S
V
D
H
1
1[ ]
*
*
*
-
0
*
Note1
0[ ]
*
*
*
*
0
*
Note1
5[ ]
-
*
*
0
-
-
-
*
0
U
-
-
Note
dst¬dst + src +C
ADD dst, src
dst¬dst + src
AND dst, src
dst¬dst AND src
BAND dst, src
r0
Rb
67
dst¬dst AND src
Rb
r0
67
BCP dst, src
r0
Rb
17
-
*
0
U
-
-
rb
57
-
*
0
U
-
-
rb
77
-
-
-
-
-
-
rb
77
-
-
-
-
-
-
07
-
*
0
U
-
-
dst – src
BITC dst
dst¬NOT dst
BITR dst
dst¬0
BITS dst
dst¬1
BOR dst, src
r0
Rb
dst¬dst OR src
Rb
r0
BTJRF
RA
rB
37
-
-
-
-
-
-
RA
rB
37
-
-
-
-
-
-
BXOR dst, src
r0
Rb
27
-
*
0
U
-
-
dst¬dst XOR src
Rb
r0
27
CALL dst
DA
-
-
-
-
-
-
If src = 0, PC = PC
+ dst
BTJRT
If src = ‘1, PC = PC
+ dst
PS014602-0103
F6
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
30
Table 20.Instruction Summary (Continued)
Instruction
and Operation
Address Mode
dst
src
Flags Affected
Opcode
Byte (Hex) C
SP¬SP-2
IRR
F4
@SP¬PC,
IA
D4
Z
S
V
D
H
PC¬dst
CCF
EF
*
-
-
-
-
-
-
-
-
-
-
-
-
*
*
0
-
-
C = NOT C
CLR dst
R
B0
dst¬0
IR
B1
COM dst
R
60
dst¬NOT dst
IR
61
Note1
A[ ]
*
*
*
*
-
-
CP dst, src
dst - src
CPIJE
r
Ir
C2
-
-
-
-
-
-
r
Ir
D2
-
-
-
-
-
-
*
*
*
U
-
-
-
*
*
*
-
-
-
*
*
*
-
-
-
-
-
-
-
-
If dst – src = 0,
then
PC¬PC + RA
Ir¬Ir + 1
CPIJNE
If dst – src = 0,
then
PC¬PC + RA
Ir¬Ir + 1
DA dst
R
40
dst¬DA dst
IR
41
DEC dst
R
00
dst¬dst -1
IR
01
DECW dst
RR
80
dst¬dst-1
IR
81
DI
PS014602-0103
8F
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
31
Table 20.Instruction Summary (Continued)
Instruction
and Operation
Address Mode
dst
src
Flags Affected
Opcode
Byte (Hex) C
Z
S
V
D
H
SMR(0)¬0
DIV dst, src
dst ¸ src
RR
R
94
dst
(Upper)¬Quotient
RR
IR
95
dst
(Lower)¬Remaind
er
RR
IM
96
DJNZ r, dst
RA
r
rA
r¬r - 1
*
*
*
*
-
-
-
-
-
-
-
-
9F
-
-
-
-
-
-
1F
-
-
-
-
-
-
2F
-
-
-
-
-
-
rE
-
*
*
*
-
-
(r = 0 to F)
if r = 0
PC¬PC + dst
EI
SMR(0)¬1
ENTER
SP¬SP - 2
@SP¬IP
IP¬PC
PC¬@IP
IP¬IP + 2
EXIT
IP¬@SP
SP¬SP + 2
PC¬@IP
IP¬IP + 2
INC dst
r
dst¬dst + 1
PS014602-0103
(r = 0 to F)
R
20
IR
21
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
32
Table 20.Instruction Summary (Continued)
Instruction
and Operation
Address Mode
dst
src
INCW dst
RR
A0
dst¬1 + dst
IR
A1
IRET (Fast)
Flags Affected
Opcode
Byte (Hex) C
Z
-
S
*
V
*
D
*
H
-
BF
Restored to before interrupt
BF
Restored to before interrupt
-
PC« IP
FLAG¬FLAG‘
FIS¬0
IRET (Normal)
FLAGS¬@SP; SP¬SP + 1
PC¬@SP; SP¬SP + 2;
SMR(0)¬1
JP cc, dst
DA
ccD
if cc is true,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(cc = 0 to F)
PC¬dst
IRR
30
JR cc, dst
RA
ccB
if cc is true,
PC¬PC + d
(cc = 0 to F)
LD dst, src
r
IM
rC
dst¬src
r
R
r8
R
r
r9
(r = 0 to F)
PS014602-0103
r
IR
C7
IR
r
D7
R
R
E4
R
IR
E5
R
IM
E6
IR
IM
D6
IR
R
F5
r
x
87
x
r
97
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
33
Table 20.Instruction Summary (Continued)
Instruction
and Operation
Address Mode
dst
src
Flags Affected
Opcode
Byte (Hex) C
LDB dst, src
r0
Rb
47
dst¬src
Rb
R0
47
r
Irr
C3
Irr
r
D3
r
xs
E7
xs
r
F7
r
x1
A7
x1
r
B7
r
DA
A7
DA
r
B7
r
Irr
r
Z
S
V
D
H
-
-
-
-
-
-
-
-
-
-
-
-
E2
-
-
-
-
-
-
Irr
E3
-
-
-
-
-
-
Irr
r
F2
-
-
-
-
-
-
Irr
r
F3
-
-
-
-
-
-
LDW dst, src
RR
R
C4
-
-
-
-
-
-
dst¬src
RR
IR
C5
RR
IM
C6
RR
R
84
-
-
-
-
-
-
LDC/LDE
dst¬src
LDCD/LDED
dst, src
dst¬src
rr¬rr - 1
LDEI/LDCI dst, src
dst¬src
rr¬rr + 1
LDCPD/LDEPD
dst, src
rr¬rr - 1
dst¬src
LDCPI/LDEPI dst,
src
rr¬rr + 1
dst¬src
MULT dst, src
PS014602-0103
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
34
Table 20.Instruction Summary (Continued)
Instruction
and Operation
dst¬src
Address Mode
dst
src
RR
IR
85
RR
IM
86
NEXT
Flags Affected
Opcode
Byte (Hex) C
Z
S
V
D
H
0F
-
-
-
-
-
-
FF
-
-
-
-
-
-
4[ ]
-
*
*
0
-
-
-
-
-
-
-
-
PC¬@IP
IP¬IP + 2
NOP
OR dst, src
Note1
dst¬dst OR src
POP dst
R
50
dst¬@SP;
IR
51
R
IR
92
-
-
-
-
-
-
R
IR
93
-
-
-
-
-
-
PUSH src
R
70
-
-
-
-
-
-
SP¬SP - 1; @SP¬src
IR
71
IR
R
82
-
-
-
-
-
-
IR
R
83
-
-
-
-
-
-
CF
0
-
-
-
-
-
AF
-
-
-
-
-
-
SP¬SP + 1
POPUD dst, src
dst¬src
IR¬IR - 1
POPUI dst, src
dst¬src
IR¬IR + 1
PUSHUD dst, src
IR¬IR - 1
dst¬src
PUSHUI dst, src
IR¬IR + 1
dst¬src
RCF
C¬0
RET
PS014602-0103
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
35
Table 20.Instruction Summary (Continued)
Instruction
and Operation
Address Mode
dst
src
Flags Affected
Opcode
Byte (Hex) C
Z
S
V
D
H
PC¬@SP; SP¬SP + 2
RL dst
R
90
*
*
*
*
-
-
C¬dst(7)
IR
91
RLC dst
R
10
*
*
*
*
-
-
dst(0)¬C
IR
11
RR dst
R
E0
*
*
*
*
-
-
C¬dst(0)
IR
E1
RRC dst
R
C0
*
*
*
*
-
-
C¬dst(0)
IR
C1
4F
-
-
-
-
-
-
5F
-
-
-
-
-
-
3[ ]
*
*
*
*
1
*
DF
1
-
-
-
-
-
dst(0)¬dst(7)
dst(N + 1)¬dst(N)
N = 0 to 6
C¬dst(7)
dst(N + 1)¬dst(N)
N = 0 to 6
dst(7)¬dst(0)
dst(N)¬dst(N + 1 )
N = 0 to 6
dst(7)¬C
dst(N)¬dst(N + 1 )
N = 0 to 6
SB0
BANK¬0
SB1
BANK¬1
SBC dst, src
Note1
dst¬dst - src - C
SCF
PS014602-0103
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
36
Table 20.Instruction Summary (Continued)
Instruction
and Operation
Address Mode
dst
src
Flags Affected
Opcode
Byte (Hex) C
Z
S
V
D
H
C¬1
SRA dst
R
D0
dst(7)¬dst(7)
IR
D1
*
*
*
0
-
-
C¬dst(0)
dst(N)¬dst(N + 1 )
N = 0 to 6
SRP src
IM
31
-
-
-
-
-
-
IM
31
-
-
-
-
-
-
IM
31
-
-
-
-
-
-
Note1
2[ ]
*
*
*
*
1
*
SWAP dst
R
F0
-
*
*
U
-
-
dst(0-3)« dst(4-7)
IR
F1
Note1
6[ ]
-
*
*
0
-
-
Note1
7[ ]
-
*
*
0
-
-
3F
-
-
-
-
-
-
B[ ]
-
*
*
0
-
-
RP0¬IM
RP0¬IM + 8
SRP0
RP0¬IM
SRP1
RP1¬IM
SUB dst, src
dst¬dst - src
TCM dst, src
(NOT dst) AND src
TM dst, src
dst AND src
WFI
XOR dst, src
Note1
dst¬dst XOR src
1. These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble identifies the command, and is found in the table above. The second nibble,
represented by a [ ], defines the addressing mode as shown in Table 6.
PS014602-0103
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
37
Table 21.Second Nibble
Addr Mode
dst
src
Lower
Opcode
Nibble1
r
r
[2]
r
Ir
[3]
R
R
[4]
R
IR
[5]
R
IM
[6]
1. For example, to use an opcode represented as
x[ ] with an "RR" addressing mode, use the
opcode "x4."
0= Cleared to Zero
1= Set to One
-= Unaffected
*= Set or reset, depending on result of operation.
U= Undefined
PS014602-0103
INSTRUCTION SUMMARY
CMOS Super8 ROMless MCU
Product Specification
38
SUPER-8 OPCODE MAP
Lower Nibble (Hex)
0
0
1
2
6
INC
R1
10
JP
IRR1
6
DA
R1
3
4
Upper Nibble (Hex)
6
DEC
R1
6
RLC
R1
1
6
DEC
IR1
6
RLC
IR1
5
10
POP
R1
6
6
COM
R1
7
8
9
2
4
6
ADC
r1,r2
3
6
ADD
r1,Ir2
6
ADC
r1,Ir2
10
ADD
R2,R1
10
ADD
R2,R1
6
7
10
10
10
ADD ADD BOR*
IR2,R1 R1,IM r0-Rb
10
10
10
ADC ADC
BCP
IR2,R1 R1,IM r1,b,R2
6
INC
IR1
6
SUB
r1,r2
6
SUB
r1,Ir2
10
SUB
R2,R1
10
10
10
SUB SUB BXOR*
IR2,R1 R1,IM r0-Rb
22
EXIT
NOTE
C
6
SBC
r1,r2
6
OR
r1,r2
10
POP
IR1
6
COM
IR1
6
AND
r1,r2
10
SBC
R2,R1
10
OR
R2,R1
10
AND
R2,R1
10
TCM
R2,R1
10
10
NOTE
SBC SBC
A
IR2,R1 R1,IM
10
10
10
OR
OR
LDB*
IR2,R1 R1,IM r0-Rb
10
10
10
AND AND
BITC
r1,b
IR2,R1 R1,IM
10
10
10
TCM TCM BAND*
IR2,R1 R1,IM r0-Rb
10
10
NOTE
TM
TM
B
IR2,R1 R1,IM
6
WFI
6
DA
IR1
6
SBC
r1,Ir2
6
OR
r1,Ir2
6
AND
r1,Ir2
6
TCM
r1,Ir2
6
ADD
r1,r2
6
TCM
r1,r2
6
10
10/12 12/14
6
TM
TM
TM
PUSH PUSH
r1,r2
r1,Ir2 R2,R1
R2
IR2
10
10
24
10
10
DECW DECW PUSHUD PUSHUI MULT
IR1,R2 IR2,R2 R2,RR1
IR1
IRR1
6
6
28/12
6
6
RL POPUD POPUI DIV
RL
IR2,R1 IR2,R1 R2,RR1
IR1
R1
10
A INCW
RR1
B
C
D
E
6
CLR
R1
6
RRC
IRR1
6
SRA
R1
10
INCW
IR1
6
CLR
IR1
6
RRC
IR1
6
SRA
IR1
6
RR
R1
6
RR
IR1
6
CP
r1,r2
6
XOR
r1,r2
16/18
CPIJE
Ir,r2,RA
16/18
CPIJNE
Ir1,r2,RA
16
LDCD*
r1,Irr2
6
10
CP
CP
r1,Ir2 R2,R1
6
10
XOR
XOR
r1,Ir2 R2,R1
12
10
LDC*
LDW
r1,Irr2 RR2,RR1
12
20
LDC* CALL
r2,Irr1
IA1
16
10
LDCI*
LD
r1,Irr2 R2,R1
16
8
18
8
16
F SWAP SWAP LDCPD* LDCPI* CALL
r2,Irr1 r2,Irr1 IRR1
IR1
R1
Note A
16/18 16/18
BTJRF BTJRT
r2,b,RA r2,b,RA
Note D
Note B
8
BITR
r1,b
20
20
LDC* LDC*
r1,Irr2,xL r1,DA2
8
BITS
r1,b
Note E
5
24
24
MULT MULT
8
6
LD
r1,R2
9
6
LD
r2,R1
A
12/10
DJNZ
r1,RA
B
12/10
JR
cc,RA
C
6
LD
r1,RM
D
12/10
JP
cc,DA
E
F
6
INC
r1
14
NEXT
20
ENTER
6
SBO
6
SBI
10
LD
6
DI
IR2,RR1 IM,RR1 r1,x,r2
10
28/12 28/12
DIV
LD
DIV
IR2,RR1 IM,RR1 r2,x,r1
10
10
CP
CP
IR2,R1 R1,IM
10
10
XOR XOR
IR2,R1 R1,IM
12
10
LDW LDW
6
EI
14
RET
NOTE
D
16/6
IRET
NOTE
E
6
LD
r1,Ir2
6
LD
Ir1,r2
IR2,RR1 RR1,IML
10
LD
IR1,IM
6
RCF
6
SCF
10
18
10
LD
LDC*
LD
IR2,R1 R1,IM r1,Irr2,xs
6
CCF
18
18
18
CALL CALL LDC*
R2,IR1 DA1 r1,Irr1,xs
6
NOP
Note C
6
SRP
IM
6
SRP0
IM
20
20
LDC* LDC*
r
,DA
r2,Irr2,xL 2
1
6
SRP1
IM
Legend:
r = 4-bit address
R = 8-bit address
b = bit number
R1 or r1 = dsts address
R2 or r2 = src address
*Examples:
BORr0-R2
is BORr1,b,R2
or BORr2,b,R1
LDCr1,Irr2
is LDCr1,Irr2 = program
or LDEr1,Irr2 = data
Sequence:
Opcode, first, second, third operands
NOTE: The blank areas are not defined.
Figure 19.Opcode Map
PS014602-0103
SUPER-8 OPCODE MAP
CMOS Super8 ROMless MCU
Product Specification
39
INSTRUCTIONS
Table 22.Super8 Instructions
Mnemonic
Operands
Instruction
Load Instructions
CLR
dst
Clear
LD
dst, src
Load
LDB
dst, src
Load bit
LDC
dst, src
Load program memory
LDE
dst, src
Load data memory
LDCD
dst, src
Load program memory and decrement
LDED
dst, src
Load data memory and decrement
LDCI
dst, src
Load program memory and increment
LDEI
dst, src
Load data memory and increment
LDCPD
dst, src
Load program memory with pre-decrement
LDEPD
dst, src
Load data memory with pre-decrement
LDCPI
dst, src
Load program memory with pre-increment
LDEPI
dst, src
Load data memory with pre-increment
LDW
dst, src
Load word
POP
dst
Pop stack
POPUD
dst, src
Pop user stack (decrement)
POPUI
dst, src
Pop user stack (increment)
PUSH
src
Push stack
PUSHUD
dst, src
Push user stack (decrement)
PUSHUI
dst, src
Push user stack (increment)
Arithmetic Instructions
PS014602-0103
ADC
dst, src
Add with carry
ADD
dst, src
Add
CP
dst, src
Compare
DA
dst
Decimal adjust
DEC
dst
Decrement
INSTRUCTIONS
CMOS Super8 ROMless MCU
Product Specification
40
Table 22.Super8 Instructions (Continued)
Mnemonic
Operands
Instruction
DECW
dst
Decrement word
DIV
dst, src
Divide
INC
dst
Increment
INCW
dst
Increment word
MULT
dst, src
Multiply
SBC
dst, src
Subtract with carry
SUB
dst, src
Subtract
Logical Instructions
AND
dst, src
Logical AND
COM
dst
Complement
OR
dst, src
Logical OR
XOR
dst, src
Logical exclusive
Program Control
Instructions
BTJRT
dst, src
Bit test jump relative on True
BTJRF
dst, src
Bit test jump relative on False
CALL
dst
Call procedure
CPIJE
dst, src
Compare, increment and jump on equal
CPIJNE
dst,src
Compare, increment and jump on non-equal
DJNZ
r, dst
Decrement and jump on non-zero
ENTER
Enter
EXIT
Exit
IRET
PS014602-0103
Return from interrupt
JP
cc, dst
Jump on condition code
JP
dst
Jump unconditional
JR
cc, dst
Jump relative on condition code
JR
dst
Jump relative unconditional
NEXT
Next
RET
Return
WFI
Wait for interrupt
INSTRUCTIONS
CMOS Super8 ROMless MCU
Product Specification
41
Table 22.Super8 Instructions (Continued)
Mnemonic
Operands
Instruction
Bit Manipulation
Instructions
BAND
dst,src
Bit AND
BCP
dst, src
Bit compare
BITC
dst
Bit complement
BITR
dst
Bit reset
BITS
dst
Bit set
BOR
dst, src
Bit OR
BXOR
dst, src
Bit exclusive OR
TCM
dst, src
Test complement under mask
TM
dst, src
Test under mask
Rotate and Shift
Instructions
RL
dst
Rotate left
RLC
dst
Rotate left through carry
RR
dst
Rotate right
RRC
dst
Rotate right through carry
SRA
dst
Shift right arithmetic
SWAP
dst
Swap nibbles
CPU Control Instructions
PS014602-0103
CCF
Complement carry flag
DI
Disable interrupts
EI
Enable interrupts
NOP
Do nothing
RCF
Reset carry flag
SB0
Set bank 0
SB1
Set bank 1
SCF
Set carry flag
SRP
src
Set register pointers
SRP0
src
Set register pointer zero
INSTRUCTIONS
CMOS Super8 ROMless MCU
Product Specification
42
Table 22.Super8 Instructions (Continued)
Mnemonic
Operands
Instruction
SRP1
src
Set register pointer one
INTERRUPTS
The Super8 interrupt structure contains 8 levels of interrupt, 16 vectors, and 27
sources.
Interrupt priority is assigned by level, controlled by the Interrupt Priority register
(IPR). Each level is masked (or enabled) according to the bits in the Interrupt
Mask register (IMR), and the entire interrupt structure can be disabled by clearing
a bit in the System Mode register (R222).
The three major components of the interrupt structure are sources, vectors, and
levels. These are shown in Figure 20 and discussed in the following paragraphs.
Sources
A source is anything that generates an interrupt. This can be internal or external to
the Super8 MCU. Internal sources are hardwired to a particular vector and level,
while external sources can be assigned to various external events.
Vectors
The 16 vectors are divided unequally among the eight levels. For example, vector
12 belongs to level 2, while level 3 contains vectors 0, 2, 4, and 6.
The vector number is used to generate the address of a particular interrupt servicing routine; therefore all interrupts using the same vector must use the same interrupt handling routine.
Levels
Levels provide the top level of priority assignment. While the sources and vectors
are hardwired within each level, the priorities of the levels can be changed by
using the Interrupt Priority register (see Figure 15 for bit details).
If more than one interrupt source is active, the source from the highest priority
level is serviced first. If both sources are from the same level, the source with the
lowest vector has priority. For example, if the UART Receive Data bit and UART
Parity Error bit are both active, the UART Parity Error bit is serviced first because
it is vector 16, and UART receive data is vector 20.
PS014602-0103
INTERRUPTS
CMOS Super8 ROMless MCU
Product Specification
43
The levels are shown in Figure 20.
INTERUPT SOURCES
POLLING
VECTORS
LEVELS
COUNTER 0 ZERO COUNT
EXTERNAL INTERRUPT (P26)
EXTERNAL INTERRUPT (P27)
12
IRQ2
COUNTER 1 ZERO COUNT
EXTERNAL INTERRUPT (P36)
EXTERNAL INTERRUPT (P37)
14
IRQ5
28
IRQ4
30
IRQ7
HANDSHAKE CHANNEL 0
EXTERNAL INTERRUPT (P24)
EXTERNAL INTERRUPT (P25)
HANDSHAKE CHANNEL 1
EXTERNAL INTERRUPT (P34)
EXTERNAL INTERRUPT (P35)
0
RESERVED
2
RESERVED
EXTERNAL INTERRUPT (P32)
EXTERNAL INTERRUPT (P22)
EXTERNAL INTERRUPT (P23)
EXTERNAL INTERRUPT (P33)
6
8
IRQ0
10
UART RECEIVE OVERRUN
UART FRAMING ERROR
UART PARITY ERROR
UART WAKEUP DETECT
UART BREAK DETECT
UART CONTROL CHAR DETECT
16
UART RECEIVE DATA
EXTERNAL INTERRUPT (P30)
20
EXTERNAL INTERRUPT (P20)
UART ZERO COUNT
EXTERNAL INTERRUPT (P21)
UART TRANSMIT DATA
EXTERNAL INTERRUPT (P31)
IRQ3
4
18
IRQ6
22
24
IRQ1
26
Figure 20.Interrupt Levels and Vectors
Enables
PS014602-0103
•
•
Interrupts can be enabled or disabled as follows:
•
Level enable. Each level can be enabled or disabled by setting the appropriate bit
in the Interrupt Mask register (R221).
•
Level priority. The priority of each level can be controlled by the values in the Interrupt Priority register (R255, Bank 0).
•
Source enable/disable. Each interrupt source can be enabled or disabled in the
sources’ Mode and Control register.
Interrupt enable/disable. The entire interrupt structure can be enabled or disabled
by setting bit 0 in the System Mode register (R222).
INTERRUPTS
CMOS Super8 ROMless MCU
Product Specification
44
Service Routines
Before an interrupt request can be granted, a) interrupts must be enabled, b) the
level must be enabled, c) it must be the highest priority interrupting level, d) it must
be enabled at the interrupting source, and e) it must have the highest priority
within the level.
If all this occurs, an interrupt request is granted.
The Super8 then enters an interrupt machine cycle that completes the following
sequence:
•
•
•
•
It resets the Interrupt Enable bit to disable all subsequent interrupts.
It saves the Program Counter and status flags on the stack.
It branches to the address contained within the vector location for the interrupt.
It passes control to the interrupt servicing routine.
When the interrupt servicing routine has serviced the interrupt, it should issue an
interrupt return (IRET) instruction. This restores the Program Counter and status
flags and sets the Interrupt Enable bit in the System Mode register.
Fast Interrupt Processing
The Super8 provides a feature called fast interrupt processing, which completes
the interrupt servicing in 6 clock periods instead of the usual 22.
Two hardware registers support fast interrupts. The Instruction Pointer (IP) holds
the starting address of the service routine, and saves the PC value when a fast
interrupt occurs. A dedicated register, FLAG’, saves the contents of the FLAGS
register when a fast interrupt occurs.
To use this feature, load the. address of the service routine in the Instruction
Pointer, load the level number into the Fast Interrupt Select field, and turn on the
Fast Interrupt Enable bit in the System Mode register.
When an interrupt occurs in the level selected for fast interrupt processing, the following occurs:
•
•
•
•
•
PS014602-0103
The contents of the Instruction Pointer and Program Counter are swapped.
The contents of the Flag register are copied into FLAG’.
The Fast Interrupt Status Bit in FLAGS is set.
The interrupt is serviced.
When IRET is issued after the interrupt service outline is completed, the Instruction Pointer and Program Counter are swapped again.
INTERRUPTS
CMOS Super8 ROMless MCU
Product Specification
45
•
•
The contents of FLAG’ are copied back into the Flag register
The Fast Interrupt Status bit in FLAGS is cleared.
The interrupt servicing routine selected for fast processing should be written so
that the location after the IRET instruction is the entry point the next time the
(same) routine is used.
Level or Edge Triggered
Because internal interrupt requests are levels and interrupt requests from the outside are (usually) edges, the hardware for external interrupts uses edge-triggered
flip-flops to convert the edges to levels.
The level-activated system requires that interrupt-serving software perform some
action to remove the interrupting source. The action involved in serving the interrupt may remove the source, or the software may have to actually reset the flipflops by writing to the corresponding Interrupt Pending register.
STACK OPERATION
The Super8 architecture supports stack operations in the register file or in data
memory. Bit 1 in the external Memory Timing register (R254 bank 0) selects
between the two.
Register pair 216-217 forms the Stack Pointer used for all stack operations. R216
is the MSB and R217 is the LSB.
The Stack Pointer always points to data stored on the top of the stack. The
address is decremented prior to a PUSH and incremented after a POP.
The stack is also used as a return stack for CALLs and interrupts. During a CALL,
the contents of the PC are saved on the stack, to be restored later. Interrupts
cause the contents of the PC and FLAGS to be saved on the stack, for recovery
by IRET when the interrupt is finished.
When the Super8 is configured for an internal stack (using the register file), R217
contains the Stack Pointer. R216 may be used as a general-purpose register, but
its contents are changed if an overflow or underflow, occurs as the result of incrementing or decrementing the stack address during normal stack operations.
User-Defined Stacks
The Super8 provides for user-defined stacks in both the register file and program
or data memory. These can be made to increment or decrement on a push by the
choice of opcodes. For example, to implement a stack that grows from low
PS014602-0103
STACK OPERATION
CMOS Super8 ROMless MCU
Product Specification
46
addresses to high addresses in the register file, use PUSHUI and POPUD. For a
stack that grows from high addresses to low addresses in data memory, use LDEI
for pop and LDEPD for push.
COUNTER/TIMERS
The Super8 has two identical independently programmable 16-bit counter/timers
that can be cascaded to produce a single 32-bit counter. They can be used to
count external events, or they can obtain their input internally. The internal input is
obtained by dividing the crystal frequency by four.
The counter/timers can be set to count up or down, by software or external events.
They can be set for single or continuous cycle counting, and they can be set with
a bi-value option, where two preset time constants alternate in loading the counter
each time it reaches zero. This can be used to produce an output pulse train with
a variable duty cycle.
The counter/timers can also be programmed to capture the count value at an
external event or generate an interrupt whenever the count reaches zero. They
can be turned on and off in response to external events by using a gate and/or a
trigger option. The gate option enables counts only when the gate line is Low; the
trigger option turns on the counter after a transient High. The gate and trigger
options used together cause the counter/timer to work in gate mode after initially
being triggered.
The control and status register bits for the counter/timers are shown in Figure 7.
DMA
The Super8 features an on-chip Direct Memory Access (DMA) channel to provide
high bandwidth data transmission capabilities. The DMA channel can be used by
the UART receiver, UART transmitter, or handshake channel 0. Data can be transferred between the peripheral and contiguous locations in either the register file or
external data memory. A 16-bit count register determines the number of transactions to be performed; an interrupt can be generated when the count is exhausted.
DMA transfers to or from the register file require six CPU clock cycles; DMA transfers to or from external memory take ten CPU clock cycles, excluding wait states.
PS014602-0103
COUNTER/TIMERS
CMOS Super8 ROMless MCU
Product Specification
47
ABSOLUTE MAXIMUM RATINGS
Voltage on all pins with respect to ground
-0.3 V to+7.0 V
See Ordering Information
Ambient Operating Temperature
-65 °C to + 150 °C
Storage Temperature
Stresses greater than these may cause permanent damage to the device. This is
a stress rating only; operation of the device under conditions more severe than
those listed for operating conditions may cause permanent damage to the device.
Exposure to absolute maximum ratings for extended periods may also cause permanent damage.
STANDARD TEST CONDITIONS
Figure 21 shows the setup for standard test conditions. All voltages are referenced to ground, and positive current flows into the reference pin.
Standard conditions are:
•
•
•
+ 4.75 V £ VCC £ + 5.25V
GND = 0 V
0°C £ TA £ + 70°C
+5 V
1K
FROM OUTPUT
UNDER TEST
150pF
400
µA
TEST LOAD (FOR ALL PINS)
Figure 21.Standard Test Load
PS014602-0103
ABSOLUTE MAXIMUM RATINGS
CMOS Super8 ROMless MCU
Product Specification
48
DC CHARACTERISTICS
Table 23.DC Characteristics
Symbol
Parameter
Min
Max
Unit
Condition
VCH
Clock Input High Voltage
3.8
VCC
V
Driven by External Clock Generator
VCL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.2
VCC
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
VCC
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
IIL
Input Leakage
IOL
Output Leakage
IIR
ICC
V
IOH = -400 mA
0.4
V
IOL = +4.0 mA
-10
10
mA
-10
10
mA
Reset Input Current
-50
mA
VCC Supply Current
320
rnA
INPUT HANDSHAKE TIMING
DATA IN
3
1
DAV IN
5
4
RDY OUT
7
2
Figure 22.Fully Interlocked Mode
PS014602-0103
DC CHARACTERISTICS
CMOS Super8 ROMless MCU
Product Specification
49
DATA IN
1
DAV IN
5
4
Figure 23.Strobed Mode
AC CHARACTERISTICS (20 MHz)
Input Handshake
Table 24.AC Characteristics (20 MHz) Input Handshake
Number
Symbol
Parameter
Min
1
TsDI(DAV)
Data In to Setup Time
0
2
TdDAVIf(RDY)
DAV ¯ Input to RDY ¯ Delay
3
ThDI(RDY)
Data In Hold Time from RDY ¯
0
4
TwDAV
DAV In Width
45
5
ThDI(DAV)
Data In Hold Time from DAV ¯
130
6
TdDAV(RDY)
DAV ­ Input to RDY ­ Delay
7
TdRDYf(DAV)
RDY ¯ Output to DAV ­ Delay
1.
2.
3.
4.
Max
Notes1,2
200
Note3
100
Note4
0
Times are preliminary and subject to change.
Times given are in ns.
Standard Test Load
This time assumes user program reads data before DAV Input goes high. RDY does not go high before data is read.
PS014602-0103
AC CHARACTERISTICS (20 MHz)
CMOS Super8 ROMless MCU
Product Specification
50
OUTPUT HANDSHAKE TIMING
DATA OUT
1
5
DAV OUT
4
2
RDY IN
3
Figure 24.Fully Interlocked Mode
DATA OUT
6
1
DAV OUT
Figure 25.Strobed Mode
AC CHARACTERISTICS (12 MHz, 20 MHz)
Output Handshake
Table 25.AC Characteristics (12 MHz, 20 MHz) Output Handshake
Number Symbol
Parameter
Min
1
TdDO(DAV)
Data Out to DAV ¯ Delay
90
2
TdRDYr(DAV)
RDY ­ Input to DAV ¯ Delay
0
3
TdDAVOf(RDY)
DAV ¯ Output to RDY ¯ Delay
0
4
TdRDYf(DAV)
RDY ¯ Input to DAV ­ Delay
0
5
TdDAVOr(RDY)
DAV ­ Output to RDY ­ Delay 0
6
TwDAVO
DAV Output Width
1.
2.
3.
4.
PS014602-0103
150
Max
Notes1,2
Note3,4
110
Note3
110
Note3
Note4
Times are preliminary and subject to change.
Times given are in ns.
Standard Test Load
Time given is for zero value in Deskew Counter. For nonzero value of n where n = 1, 2,. . . 15 add 2 x n x TpC to the given time.
OUTPUT HANDSHAKE TIMING
CMOS Super8 ROMless MCU
Product Specification
51
AC CHARACTERISTICS (12 MHz)
Read /Write
Table 26.AC Characteristics (12 MHz) Read/Write
Normal
Timing
Extended
Timing
Number
Symbol
Parameter
Min
Max Min
1
TdA(AS)
Address Valid to AS ­ Delay
35
115
2
TdAS(A)
AS ­ to Address Float Delay
65
150
3
TdAS(DR)
AS ­ to Read Data Required Valid
4
TWAS
AS Low Width
65
150
5
TdA(DS)
Address Float to DS ¯
20
20
6a
TWDS(Read) DS (Read) Low Width
225
470
6b
TwDS(Write)
DS (Write) Low Width
130
295
7
TdDS(DR)
DS ¯ to Read Data Required Valid
8
ThDS(DR)
Read Data to DS ­ Hold Time
0
0
9
TdDS(A)
DS ­ to Address Active Delay
50
135
10
TdDS(AS)
DS ­ to AS ¯ Delay
60
145
11
TdDO(DS)
Write Data Valid to DS (Write) ¯ Delay 35
115
12
TdAS(W)
AS ­ to Wait Delay
13
ThDS(W)
DS ­ to Wait Hold Time
0
0
14
TdRW(AS)
R/W Valid to AS ­ Delay
50
135
270
180
220
Max
Notes1,2
600
Note3
Note3
1
Note3
420
Note3
600
Note4
1. All times are in ns and are for 12 MHz input frequency.
2. Timings are preliminary and subject to change
3.) Wait states add 167 ns to these times.
4.) Auto-wait states add 167 ns to this time..
PS014602-0103
AC CHARACTERISTICS (12 MHz)
CMOS Super8 ROMless MCU
Product Specification
52
AC CHARACTERISTICS (20 MHz)
Read /Write
Table 27.AC Characteristics (20 MHz) Read/Write
Normal
Timing
Extended Timing
Min
Max
Max
Notes1,2
335
Note3
Number
Symbol
Parameter
Min
1
TdA(AS)
Address Valid to AS ­ Delay
20
50
2
TdAS(A)
AS ­ to Address Float Delay
35
85
3
TdAS(DR)
AS ­ to Read Data Required Valid
4
TWAS
AS Low Width
35
85
5
TdA(DS)
Address Float to DS ¯
0
0
6a
TWDS(Read)
DS (Read) Low Width
125
275
Note3
6b
TWDS(Write)
DS (Write) Low Width
65
165
Note3
7
TdDS(DR)
DS ¯ to Read Data Required Valid
8
ThDS(DR)
Read Data to DS ­ Hold Time
0
0
9
TdDS(A)
DS ­ to Address Active Delay
20
70
10
TdDS(AS)
DS ­ to AS 1 Delay
30
80
11
TdDO(DS)
Write Data Valid to DS (Write) ¯ Delay 10
50
12
TdAS(W)
AS ­ to Wait Delay
13
ThDS(W)
DS ­ to Wait Hold Time
0
0
14
TdRW(AS)
R/W Valid to AS ­ Delay
20
70
150
80
90
225
Note3
335
Note4
1. All times are in ns and are for 20 MHz input frequency.
2. Timings are preliminary and subject to change.
3.) Wait states add 100 ns to these times.
4.) Auto-wait states add 100 ns to this time
PS014602-0103
AC CHARACTERISTICS (20 MHz)
CMOS Super8 ROMless MCU
Product Specification
53
R/W
14
PORT 0
DM
A8-A15, DM
9
1
A0-A7
PORT 1
1
D0-D 7, OUT
2
D0-D7
OUT
IN
10
11
8
AS
5
4
7
CS
6
WAIT WINDOW
WAIT
13
12
Figure 26.External Memory Read and Write Timing
ADDRESS OUT
A0-A13
1
DATA IN
D0-D7 IN
Figure 27.EPROM Read Timing
PS014602-0103
AC CHARACTERISTICS (20 MHz)
CMOS Super8 ROMless MCU
Product Specification
54
AC CHARACTERISTICS (20 MHz)
EPROM Read Cycle
Example:
Table 28.AC Characteristics (20 MHz) EPROM Read Cycle
Number
Symbol
Parameter
Min
1
TdA(DR)
Address Valid to Read Data Required Valid 170
Max
Notes1,2
Note3
1. All times are in ns and are for 12 MHz input frequency.
2. Timings are preliminary and subject to change.
3.) Wait states add 167 ns to these times.
Packaging Information
Figure 28.44-Pin PLCC
PS014602-0103
AC CHARACTERISTICS (20 MHz)
CMOS Super8 ROMless MCU
Product Specification
55
Figure 29.48-Pin DIP
PS014602-0103
Packaging Information
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