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P / N 2 1 2 2 8 . 4 0 G b / sQ S F P +L R 4T r a n s c e i v e r
PRODUCT FEATURES
z
4 CWDM lanes Mux/Demux design
z
Up to 11.1Gbps Data rate per wavelength
z
Up to 10km transmission on SMF
z
Electrically hot-pluggable
z
Digital Diagnostics Monitoring Interface
z
Compliant with QSFP+ MSA with LC connector
z
Case operating temperature range:0°C to 70°C
z
Power dissipation < 3.5 W
APPLICATIONS
z
40G Ethernet
z
Data Center and LAN
STANDARD
z
Compliant to IEEE 802.3ba
z
Compliant to SFF-8436
z
RoHS Compliant.
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General Description
QSFP+ LR4 is designed to operate over single-mode fiber system using 4X10 CWDM
channel in 1310 band and links up to 10km. The module converts 4 inputs channel of 10Gb/s
electrical data to 4 CWDM optical signals, and multiplexes them into a single channel for
40Gb/s optical transmission. Reversely, on the receiver side, the module optically
de-multiplexes a 40Gb/s input into 4 CWDM channels signals, and converts them to 4 channel
output electrical data.
The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm. It
contains a duplex LC connector for the optical interface and a 38-pin connector for the electrical
interface. Single-mode fiber (SMF) is applied in this module. This product converts the
4-channel 10Gb/s electrical input data into CWDM optical signals (light), by a 4-wavelength
Distributed Feedback Laser (DFB) array. The 4 wavelengths are multiplexed into a single
40Gb/s data, propagating out of the transmitter module via the SMF. The receiver module
accepts the 40Gb/s optical signals input, and de-multiplexes it into 4 CWDM 10Gb/s channels.
Each wavelength light is collected by a discrete photo diode, and then outputted as electric data
after amplified by a TIA.
The product is designed with form factor, optical/electrical connection and digital diagnostic
interface according to the QSFP+ Multi-Source Agreement (MSA) and compliant to 40G QSFP+
LR4 of IEEE 802.3ba.
ĉ Absolute Maximum Ratings
Parameter
Symbol
Min.
Typ.
Max.
Unit
Storage Temperature
Ts
-40
-
85
ºC
Relative Humidity
RH
5
-
95
%
Power Supply Voltage
VCC
-0.3
-
4
V
Vcc-0.3
-
Vcc+0.3
V
Signal Input Voltage
Note
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Ċ Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Note
Case Operating Temperature
Tcase
0
-
70
ºC
Without air flow
Power Supply Voltage
VCC
3.13
3.3
3.47
V
Power Supply Current
Data Rate
Transmission Distance
ICC
BR
TD
-
900
mA
Gbps
km
Coupled fiber
10.3125
-
10
Each channel
Single mode fiber
9/125um SMF
ċ Optical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Ȝ0
1264.5
1271
1277.5
nm
Ȝ1
1284.5
1291
1297.5
nm
Ȝ2
1304.5
1311
1317.5
nm
Ȝ3
1324.5
1331
1337.5
nm
8.3
dBm
2.3
dBm
1
nm
NOTE
Transmitter
Wavelength Assignment
Total Output. Power
POUT
Average Launch Power Per lane
Spectral Width (-20dB)
-7
ı
SMSR
30
dB
3.5
dB
Optical Extinction Ratio
ER
Average launch Power off per lane
Poff
-30
dBm
Transmitter and Dispersion Peanlty
TDP
2.3
dB
RIN
RIN
-128
dB/Hz
Output Eye Mask
Compliant with IEEE 802.3ba
Receiver
Rx Sensitivity per lane˄OMA˅
RSENS
Input Saturation Power (Overload)
Psat
Receiver Reflectance
Rr
-11.5
dBm
3.3
-26
Notes:
31
1.
Measured with a PRBS 2 -1 test pattern, @10.325Gb/s, BER<10
dBm
-12
.
dB
1
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IV. Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vcc
3.14
3.3
3.46
V
Supply Current
Icc
900
mA
NOTE
Transmitter
ȍ
Input differential impedance
Rin
100
Differential data input swing
Vin,pp
180
1000
mV
Transmit Disable Voltage
VD
Vcc–1.3
Vcc
V
Transmit Enable Voltage
VEN
Vee
Vee+ 0.8
V
10
us
850
mV
3
Transmit Disable Assert Time
1
2
Receiver
Differential data output swing
Vout,pp
300
Data output rise time
tr
28
ps
4
Data output fall time
tf
28
ps
4
LOS Fault
VLOS fault
Vcc–1.3
VccHOST
V
5
LOS Normal
VLOS norm
Vee
Vee+0.8
V
5
Power Supply Rejection
PSR
100
mVpp
6
Notes:
1. Connected directly to TX data input pins. AC coupled thereafter.
2. Or open circuit.
3. Into 100 ohms differential termination.
4. 20 – 80 %.
5. Loss Of Signal is LVTTL. Logic 0 indicates normal operation; logic 1 indicates no signal detected.
6.
Receiver sensitivity is compliant with power supply sinusoidal modulation of 20 Hz to 1.5 MHz up to
specified value applied through the recommended power supply filtering network.
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V.
Pin Assignment
Figure 1---Pin out of Connector Block on Host Board
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
GND
Tx2n
Tx2p
GND
Tx4n
Tx4p
GND
ModSelL
ResetL
VccRx
SCL
SDA
GND
Rx3p
Rx3n
GND
Rx1p
Rx1n
GND
GND
Rx2n
Rx2p
GND
Rx4n
Name/Description
Transmitter Ground (Common with Receiver Ground)
Transmitter Inverted Data Input
Transmitter Non-Inverted Data output
Transmitter Ground (Common with Receiver Ground)
Transmitter Inverted Data Input
Transmitter Non-Inverted Data output
Transmitter Ground (Common with Receiver Ground)
Module Select
Module Reset
3.3V Power Supply Receiver
2-Wire serial Interface Clock
2-Wire serial Interface Data
Transmitter Ground (Common with Receiver Ground)
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Transmitter Ground (Common with Receiver Ground)
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Transmitter Ground (Common with Receiver Ground)
Transmitter Ground (Common with Receiver Ground)
Receiver Inverted Data Output
Receiver Non-Inverted Data Output
Transmitter Ground (Common with Receiver Ground)
Receiver Inverted Data Output
NOTE
1
1
1
2
1
1
1
1
1
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25
26
27
28
29
30
31
32
33
34
35
36
37
38
Rx4p
GND
ModPrsl
IntL
VccTx
Vcc1
LPMode
GND
Tx3p
Tx3n
GND
Tx1p
Tx1n
GND
Receiver Non-Inverted Data Output
Transmitter Ground (Common with Receiver Ground)
Module Present
Interrupt
3.3V power supply transmitter
3.3V power supply
Low Power Mode
Transmitter Ground (Common with Receiver Ground)
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Output
Transmitter Ground (Common with Receiver Ground)
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Output
Transmitter Ground (Common with Receiver Ground)
1
2
2
1
1
1
Notes:
1. GND is the symbol for signal and supply (power) common for QSFP+ modules. All are
common within the QSFP+ module and all module voltages are referenced to this potential
unless otherwise noted. Connect these directly to the host board signal common ground plane.
2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be
applied concurrently. Recommended host board power supply filtering is shown below. Vcc Rx,
Vcc1 and Vcc Tx may be internally connected within the QSFP+ transceiver module in any
combination. The connector pins are each rated for a maximum current of 500mA.
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VI.
Digital Diagnostic Functions
Support the 2-wire serial communication protocol as defined in
the QSFP+ MSA. which allows real-time access to the following operating parameters:
y
Transceiver temperature
y
Laser bias current
y
Transmitted optical power
y
Received optical power
y
Transceiver supply voltage
It also provides a sophisticated system of alarm and warning flags, which may be used to
alert end-users when particular operating parameters are outside of a factory-set normal range.
The operating and diagnostics information is monitored and reported by a Digital
Diagnostics Transceiver Controller (DDTC) inside the transceiver, which is accessed through
the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin)
is generated by the host. The positive edge clocks data into the QSFP+ transceiver into those
segments of its memory map that are not write-protected. The negative edge clocks data from
the QSFP+ transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer.
The host uses SDA in conjunction with SCL to mark the start and end of serial protocol
activation. The memories are organized as a series of 8-bit data words that can be addressed
individually or sequentially. The 2-wire serial interface provides sequential or random access to
the 8 bit parameters, addressed from 000h to the maximum address of the memory.
This clause defines the Memory Map for QSFP transceiver used for serial ID, digital
monitoring and certain control functions. The interface is mandatory for all QSFP devices. The
memory map has been changed in order to accommodate 4 optical channels and limit the
required memory space. The structure of the memory is shown in Figure 2 -QSFP+ Memory
Map. The memory space is arranged into a lower, single page, address space of 128 bytes and
multiple upper address space pages. This structure permits timely access to addresses in the
lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID
information and threshold settings, are available with the Page Select function. The structure
also provides address expansion by adding additional upper pages as needed.
in Figure 29 upper pages 01 and 02 are optional.
For example,
Upper page 01 allows implementation of
Application Select Table, and upper page 02 provides user read/write space.
The lower page
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and upper pages 00 and 03 are always implemented. The interface address used is A0xh and is
mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for
all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can
read out the flag field to determine the effected channel and type of flag.
For more detailed information including memory map definitions, please see the QSFP+
MSA Specification.
Figure 2 --QSFP Memory Map
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Lower Memory Map
The lower 128 bytes of the 2-wire serial bus address space, see Table 1, is used to access
a variety of measurements and diagnostic functions, a set of control functions, and a means to
select which of the various upper memory map pages are accessed on subsequent reads. This
portion of the address space is always directly addressable and thus is chosen for
monitoring and control functions that may need to be repeatedly accessed. The definition of
identifier field is the same as page 00h Byte 128.
Table 1— Lower Memory Map
Byte Address
0
1-2
3-21
22-33
34-81
82-85
86-97
98-99
100-106
107-118
119-122
123-126
127
Description
Identifier (1 Byte)
Status (2 Bytes)
Interrupt Flags (19 Bytes)
Module Monitors (12 Bytes)
Channel Monitors (48 Bytes)
Reserved (4 Bytes)
Control (12 Bytes)
Reserved (2 Bytes)
Module and Channel Masks (7 Bytes)
Reserved (12 Bytes)
Password Change Entry Area (optional) (4 Bytes)
Password Entry Area (optional) (4 Bytes)
Page Select Byte
Type
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Status Indicator Bits
The Status Indicators are defined in Table 2.
Table 2 — Status Indicators
Byte
1
2
Bit
All
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IntL
Data_Not_Ready
Description
Digital state of the IntL interrupt output pin.
Indicates transceiver has not yet achieved power up and
monitor data is not ready. Bit remains high until data is ready to
be read at which time the device sets the bit low.
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Interrupt Flags
A portion of the memory map (Bytes 3 through 21), form a flag field. Within this field, the status
of LOS and Tx Fault as well as alarms and warnings for the various monitored items is reported.
For normal operation and default state, the bits in this field have the value of 0b. For the defined
conditions of LOS, Tx Fault, module and channel alarms and warnings, the appropriate bit or
bits are set, value = 1b. Once asserted, the bits remained set (latched) until cleared by a read
operation that includes the affected bit or reset by the ResetL pin. The Channel Status Interrupt
Flags are defined in Table 3.
Table 3 — Channel Status Interrupt Flags
Byte
3
4
5
Bit
7
6
5
4
3
2
1
0
7-4
3
2
1
0
All
Name
L-Tx4 LOS
L-Tx3 LOS
L-Tx2 LOS
L-Tx1 LOS
L-Rx4 LOS
L-Rx3 LOS
L-Rx2 LOS
L-Rx1 LOS
Reserved
L-Tx4 Fault
L-Tx3 Fault
L-Tx2 Fault
L-Tx1 Fault
Reserved
Description
Latched TX LOS indicator, channel 4 (Not support)
Latched TX LOS indicator, channel 3 (Not support)
Latched TX LOS indicator, channel 2 (Not support)
Latched TX LOS indicator, channel 1 (Not support)
Latched RX LOS indicator, channel 4
Latched RX LOS indicator, channel 3
Latched RX LOS indicator, channel 2
Latched RX LOS indicator, channel 1
Latched TX fault indicator, channel 4
Latched TX fault indicator, channel 3
Latched TX fault indicator, channel 2
Latched TX fault indicator, channel 1
The Module Monitor Interrupt Flags are defined in Table 4.
Table 4 — Module Monitor Interrupt Flags
Byte
6
7
8
Bit
7
6
5
4
3-0
7
6
Name
L-Temp High Alarm
L-Temp Low Alarm
L-Temp High Warning
L-Temp Low Warning
Reserved
L-Vcc High Alarm
Description
Latched high temperature alarm
Latched low temperature alarm
Latched high temperature warning
Latched low temperature warning
L-Vcc Low Alarm
Latched high supply voltage alarm
Latched low supply voltage alarm
5
L-Vcc High Warning
Latched high supply voltage warning
4
L-Vcc Low Warning
Latched low supply voltage warning
3-0
Reserved
All
Reserved
The Channel Monitor Interrupt Flags are defined in Table 5
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Table 5 — Channel Monitor Interrupt Flags
Byte
9
10
11
12
13
14
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Name
L-Rx1 Power High Alarm
L-Rx1 Power Low Alarm
L-Rx1 Power High Warning
L-Rx1 Power Low Warning
L-Rx2 Power High Alarm
L-Rx2 Power Low Alarm
L-Rx2 Power High Warning
L-Rx2 Power Low Warning
L-Rx3 Power High Alarm
L-Rx3 Power Low Alarm
L-Rx3 Power High Warning
L-Rx3 Power Low Warning
L-Rx4 Power High Alarm
L-Rx4 Power Low Alarm
L-Rx4 Power High Warning
L-Rx4 Power Low Warning
L-Tx1 Bias High Alarm
L-Tx1 Bias Low Alarm
L-Tx1 Bias High Warning
L-Tx1 Bias Low Warning
L-Tx2 Bias High Alarm
L-Tx2 Bias Low Alarm
L-Tx2 Bias High Warning
L-Tx2 Bias Low Warning
L-Tx3 Bias High Alarm
L-Tx3 Bias Low Alarm
L-Tx3 Bias High Warning
L-Tx3 Bias Low Warning
L-Tx4 Bias High Alarm
L-Tx4 Bias Low Alarm
L-Tx4 Bias High Warning
L-Tx4 Bias Low Warning
L-Tx1 Power High Alarm
L-Tx1 Power Low Alarm
L-Tx1 Power High Warning
L-Tx1 Power Low Warning
L-Tx2 Power High Alarm
L-Tx2 Power Low Alarm
L-Tx2 Power High Warning
L-Tx2 Power Low Warning
L-Tx3 Power High Alarm
L-Tx3 Power Low Alarm
L-Tx31 Power High Warning
L-Tx3 Power Low Warning
L-Tx4 Power High Alarm
L-Tx4 Power Low Alarm
L-Tx4 Power High Warning
L-Tx4 Power Low Warning
Description
Latched high RX power alarm, channel 1
Latched low RX power alarm, channel 1
Latched high RX power warning, channel 1
Latched low RX power warning, channel 1
Latched high RX power alarm, channel 2
Latched low RX power alarm, channel 2
Latched high RX power warning, channel 2
Latched low RX power warning, channel 2
Latched high RX power alarm, channel 3
Latched low RX power alarm, channel 3
Latched high RX power warning, channel 3
Latched low RX power warning, channel 3
Latched high RX power alarm, channel 4
Latched low RX power alarm, channel 4
Latched high RX power warning, channel 4
Latched low RX power warning, channel 4
Latched high TX bias alarm, channel 1
Latched low TX bias alarm, channel 1
Latched high TX bias warning, channel 1
Latched low TX bias warning, channel 1
Latched high TX bias alarm, channel 2
Latched low TX bias alarm, channel 2
Latched high TX bias warning, channel 2
Latched low TX bias warning, channel 2
Latched high TX bias alarm, channel 3
Latched low TX bias alarm, channel 3
Latched high TX bias warning, channel 3
Latched low TX bias warning, channel 3
Latched high TX bias alarm, channel 4
Latched low TX bias alarm, channel 4
Latched high TX bias warning, channel 4
Latched low TX bias warning, channel 4
Latched high TX Power alarm, channel 1
Latched low TX Power alarm, channel 1
Latched high TX Power warning, channel 1
Latched low TX Power warning, channel 1
Latched high TX Power alarm, channel 2
Latched low TX Power alarm, channel 2
Latched high TX Power warning, channel 2
Latched low TX Power warning, channel 2
Latched high TX Power alarm, channel 3
Latched low TX Power alarm, channel 3
Latched high TX Power warning, channel 3
Latched low TX Power warning, channel 3
Latched high TX Power alarm, channel 4
Latched low TX Power alarm, channel 4
Latched high TX Power warning, channel 4
Latched low TX Power warning, channel 4
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15-16
17-18
19-20
21
All
All
All
All
Reserved
Reserved
Reserved
Reserved
Reserved channel monitor flags, set 4
Reserved channel monitor flags, set 5
Reserved channel monitor flags, set 6
Module Monitors
Real time monitoring for the QSFP module include transceiver temperature, transceiver supply
voltage, and monitoring for each transmit and receive channel. Measured parameters are
reported in 16-bit data fields, i.e., two concatenated bytes. These are shown in Table 6.
Table 6 — Module Monitoring Values
Byte
22
23
24-25
26
27
28-33
Bit
All
All
All
All
All
All
Name
Temperature MSB
Temperature LSB
Reserved
Supply Voltage MSB
Supply Voltage LSB
Reserved
Description
Internally measured module temperature
Internally measured module supply voltage
Channel Monitoring
Real time channel monitoring is for each transmit and receive channel and includes optical input
power Tx bias current and Tx output Power. Measurements are calibrated over vendor specified
operating temperature and voltage and should be interpreted as defined below. Alarm and
warning threshold values should be interpreted in the same manner as real time 16-bit data.
Table 7 defines the Channel Monitoring.
Table 7 — Channel Monitoring Values
Byte
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bit
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
Name
Rx1 Power MSB
Rx1 Power LSB
Rx2 Power MSB
Rx2 Power LSB
Rx3 Power MSB
Rx3 Power LSB
Rx4 Power MSB
Rx4 Power LSB
Tx1 Bias MSB
Tx1 Bias LSB
Tx2 Bias MSB
Tx2 Bias LSB
Tx3 Bias MSB
Tx3 Bias LSB
Tx4 Bias MSB
Tx4 Bias LSB
Tx1 Power MSB
Tx1 Power LSB
Tx2 Power MSB
Tx2 Power LSB
Tx3 Power MSB
Tx3 Power LSB
Description
Internally measured RX input power, channel 1
Internally measured RX input power, channel 2
Internally measured RX input power, channel 3
Internally measured RX input power, channel 4
Internally measured TX bias, channel 1
Internally measured TX bias, channel 2
Internally measured TX bias, channel 3
Internally measured TX bias, channel 4
Internally measured TX output power, channel 1
Internally measured TX output power, channel 2
Internally measured TX output power, channel 3
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56
57
58-65
66-73
74-81
All
All
Tx4 Power MSB
Tx4 Power LSB
Internally measured TX output power, channel 4
Reserved channel monitor set 4
Reserved channel monitor set 5
Reserved channel monitor set 6
Control Bytes
Control Bytes are defined in Table 8
Table 8 — Control Bytes
Byte
86
87
88
89
90
91
92
93
94
95
96
97
98-99
Bit
7-4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
All
All
All
All
2-7
1
0
All
All
All
All
All
Name
Reserved
Tx4_Disable
Tx3_Disable
Tx2_Disable
Tx1_Disable
Rx4_Rate_Select
Rx4_Rate_Select
Rx3_Rate_Select
Rx3_Rate_Select
Rx2_Rate_Select
Rx2_Rate_Select
Rx1_Rate_Select
Rx1_Rate_Select
Tx4_Rate_Select
Tx4_Rate_Select
Tx3_Rate_Select
Tx3_Rate_Select
Tx2_Rate_Select
Tx2_Rate_Select
Tx1_Rate_Select
Tx1_Rate_Select
Rx4_Application_Select
Rx3_Application_Select
Rx2_Application_Select
Rx1_Application_Select
Reserved
Power_set
Power_over-ride
Tx4_Application_Select
Tx3_Application_Select
Tx2_Application_Select
Tx1_Application_Select
Reserved
1. Writing “1” disables the laser of the channel.
Description
Read/write bit that allows software disable of transmitters.1
Read/write bit that allows software disable of transmitters.1
Read/write bit that allows software disable of transmitters.1
Read/write bit that allows software disable of transmitters.1
Software Rate Select, Rx channel 4 msb
Software Rate Select, Rx channel 4 lsb
Software Rate Select, Rx channel 3 msb
Software Rate Select, Rx channel 3 lsb
Software Rate Select, Rx channel 2 msb
Software Rate Select, Rx channel 2 lsb
Software Rate Select, Rx channel 1 msb
Software Rate Select, Rx channel 1 lsb
Software Rate Select, Tx channel 4 msb (Not support)
Software Rate Select, Tx channel 4 lsb (Not support)
Software Rate Select, Tx channel 3 msb (Not support)
Software Rate Select, Tx channel 3 lsb (Not support)
Software Rate Select, Tx channel 2 msb (Not support)
Software Rate Select, Tx channel 2 lsb (Not support)
Software Rate Select, Tx channel 1 msb (Not support)
Software Rate Select, Tx channel 1 lsb (Not support)
Software Application Select per SFF-8079, Rx Channel 4
Software Application Select per SFF-8079, Rx Channel 3
Software Application Select per SFF-8079, Rx Channel 2
Software Application Select per SFF-8079, Rx Channel 1
Power set to low power mode. Default 0.
Override of LPMode signal setting the power mode with software.
Software Application Select per SFF-8079, Tx Channel 4 (Not support)
Software Application Select per SFF-8079, Tx Channel 3 (Not support)
Software Application Select per SFF-8079, Tx Channel 2 (Not support)
Software Application Select per SFF-8079, Tx Channel 1 (Not support)
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LPMode
The LPMode pin shall be pulled up to Vcc in the QSFP module. This function is affected by the LPMode pin and
the combination of the Power_over-ride and Power_set software control bits (Address A0h, byte 93 bits
0,1). The module has two modes a low power mode and a high power mode. When the module is in a low power
mode it has a maximum power consumption of 1.5W. This protects hosts that are not capable of cooling higher
power modules, should such modules be accidentally inserted. A truth table for the relevant configurations of the
LPMode and the Power_over-ride and Power_set are shown in Table 9.
At Power up, the Power_over-ride and Power_set bits shall be set to 0.
Table 9 —Power Mode Truth Table
LPMode
1
0
X
X
Power_Over-ride Bit
0
0
1
1
Power_set Bit
X
X
1
0
Module Power Al owed
Low Power
High Power
Low Power
High Power
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VII. Host - Transceiver Interface Block Diagram
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VIII. Outline Dimensions
3.8
27.2
12.2
R0
D
8QLWVLQPP
.3
2.25
2
2-C0.35X45°
0.6
1
5.2
16.4± 0.1
15.4
13.68
R0.
2
'(7$,/$
6&$/(
2.55
Label
3
29.6± 0.1
8.5± 0.1
6(('(7$,/$
1.4
2.15
5.85
2
6.25± 0.05
72
1
48.4
2.3
16.7
3
0.9
18.35
18.35
4.2
Appendix A. Document Revision
Version No.
1.0
2.0
3.0
Date
2012-08-30
2012-11-24
2013-10-15
Description
Preliminary datasheet
Add power mode function
Update Power Supply Current 800mA to 900mA
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