LT3640 - Dual Monolithic Buck Regulator with Power
LT3640
Dual Monolithic Buck
Regulator with Power-On
Reset and Watchdog Timer
Description
Features
High Voltage Buck Regulator:
4V to 35V Operating Range
1.3A Output Current
n OVLO Protects Input to 55V
n Low Voltage Synchronous Buck Regulator:
2.5V to 5.5V Input Voltage Range
1.1A Output Current
n Synchronizable, Adjustable 350kHz to 2.5MHz
Switching Frequency
n Programmable Power-On Reset Timer
n Programmable Window Mode Watchdog Timer
n Typical Quiescent Current: 290µA
n Short-Circuit Robust
n Programmable Soft-Start
n Low Shutdown Current: I < 1µA
Q
n Available in Thermally Enhanced 28-Lead
(4mm × 5mm) QFN and 28-Lead TSSOP Packages
The LT®3640 is a dual channel, current mode monolithic
buck switching regulator with a power-on reset and a
watchdog timer. Both regulators are synchronized to a
single oscillator with an adjustable frequency (350kHz to
2.5MHz). At light loads, both regulators operate in low
ripple Burst Mode® to maintain high efficiency and low
output ripple.
n
The high voltage channel is a nonsynchronous buck with
an internal 2.4A top switch that operates from an input
of 4V to 35V; a 36.5V OVLO protects the device to 55V.
The low voltage channel operates from an input of 2.5V to
5.5V. Internal synchronous power switches provide high
efficiency without the need of external Schottky diode.
Both channels have cycle-by-cycle current limit, providing
protection against shorted outputs.
The power-on reset and watchdog timeout periods are
both adjustable using external capacitors. The window
mode watchdog timer flags when the µP pulses group
too close together or too far apart.
Applications
Industrial Power Supplies
Automotive Electronic Control Units
n
The LT3640 is available in a 28-pin 4mm × 5mm QFN
package and 28-pin TSSOP package. Both packages have
an exposed pad for low thermal resistance.
n
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
2MHz 3.3V/0.8A and 1.8V/0.8A Step Down Regulators
HV Channel Efficiency,
2MHz, VOUT1 = 3.3V
0.22µF
3.3µH
EN/UVLO VIN SW
SYNC
WDE
PGOOD
BST SW1
LT3640
VIN2
80.6k
DA
FB1
100k
100k
RST1
RST2
WDO
WDI
µP
EN2
1µH
SW2
100k
CWDT
CPOR
1.5nF
RT GND SS2
1.5nF
32.4k
FB2
SS1
1nF
49.9k
1nF
VOUT2
1.8V/0.8A
90
VIN2 = 3.3V
22µF
49.9k
VOUT1
90
VOUT1
3.3V/0.8A
85
85
VIN = 12V
EFFICIENCY (%)
10µF
EFFICIENCY (%)
VIN
5V TO 35V
LV Channel Efficiency,
2MHz, VOUT2 = 1.8V
80
75
80
75
22µF
70
0
0.2
0.4
0.6
0.8
1.0
VOUT1 CURRENT (A)
1.2
3640 TA01b
70
0
0.2
0.4
0.6
VOUT2 CURRENT (A)
0.8
1
3640 TA01c
3640 TA01a
3640f
LT3640
Absolute Maximum Ratings
(Note 1)
VIN, EN/UVLO Voltage (Note 7)..................................55V
WDE Voltage..............................................................30V
BST Above SW, SW1 Voltage........................ –0.3V to 6V
SW1 Above SW Voltage................................ –0.3V to 6V
VIN2, SYNC, EN2, PGOOD, WDI,
WDO, RST1, RST2, Voltages........................ –0.3V to 6V
SS1, SS2, FB1, FB2, RT, CWDT,
CPOR Voltages………............................... –0.3V to 2.5V
SW2 Voltage................................. –0.3V to (VIN2 + 0.3V)
Operating Junction Temperature Range (Note 2)
LT3640E.................................................. –40°C to 125°C
LT3640I................................................... –40°C to 125°C
Storage Temperature Range.................... –65°C to 150°C
Lead Temperature, FE Only (Soldering, 10 sec)..... 300°C
Pin Configuration
TOP VIEW
EN/UVLO
3
26 GND
SYNC
4
25 SW2
SS1
5
24 VIN2
FB1
6
23 GND
RT
7
RST2
8
RST1
9
22 SW2
SS1 2
21 VIN2
FB1 3
20 GND
22 VIN
RT 4
21 BST
RST2 5
20 SW
RST1 6
17 SW
19 SW1
WDO 7
16 SW1
16 GND
WDI 14
15 GND
FE PACKAGE
28-LEAD PLASTIC TSSOP
θJA = 30°C/W, θJC = 8°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
NC
WDE 13
15 DA
9 10 11 12 13 14
GND
17 NC
GND
18 DA
CPOR 12
18 BST
CWDT 8
WDI
CWDT 11
19 VIN
29
GND
WDE
WDO 10
28 27 26 25 24 23
SYNC 1
CPOR
29
GND
GND
27 EN2
EN2
2
SS2
PGOOD
TOP VIEW
FB2
28 SS2
PGOOD
1
EN/UVLO
FB2
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
θJA = 34°C/W, θJC = 2.7°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3640EFE#PBF
LT3640EFE#TRPBF
LT3640FE
28-Lead Plastic TSSOP
–40°C to 125°C
LT3640IFE#PBF
LT3640IFE#TRPBF
LT3640FE
28-Lead Plastic TSSOP
–40°C to 125°C
LT3640EUFD#PBF
LT3640EUFD#TRPBF
3640
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3640IUFD#PBF
LT3640IUFD#TRPBF
3640
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3640f
LT3640
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
PARAMETER
TYP
MAX
VIN Undervoltage Lockout Threshold
l
3.6
4
V
VIN Undervoltage Release Threshold
l
3.8
4.2
V
VIN Overvoltage Lockout Threshold
l
35
36.5
38
V
VIN Overvoltage Release Threshold
l
34
35.5
37
V
0.1
275
1
375
µA
µA
1.26
1.3
V
Quiescent Current from VIN
CONDITIONS
MIN
EN/UVLO = 0.3V
Not Switching
EN/UVLO Threshold Voltage
1.2
UNITS
EN/UVLO High Bias Current
EN/UVLO = Threshold + 60mV
2
µA
EN/UVLO Low Bias Current
EN/UVLO = Threshold – 60mV
0.1
µA
SYNC Input Frequency
0.35
SYNC Threshold Voltage
0.4
0.8
1
l
l
1.75
450
2
500
2.35
550
MHz
kHz
l
1.24
1.265
1.29
V
100
Switching Frequency
RT = 32.4k
RT = 182k
FB1 Voltage
2.5
FB1 Bias Current
FB1 = 1.265V
30
FB1 Line Regulation
5V < VIN < 30V
0.001
SW1 Minimum Off-Time
SW1 VCESAT
70
ISW1 = 800mA
V
nA
%/V
100
400
SW1 Leakage Current
MHz
ns
mV
0.1
1
µA
SW1 Current Limit
FB1 = 1V (Note 3)
FB1 = 0.1V
l
2.2
2.8
1.8
3.4
A
A
DA Current limit
FB1 = 1V (Note 4)
FB1 = 0.1V
l
1.35
1.7
1
2.2
A
A
BST Pin Current
ISW1 = 800mA
30
50
mA
Minimum BST-SW Voltage
ΔFB1 to Start LV Channel
80
ΔFB1 Hysteresis to Stop LV Channel
30
VIN2 Minimum Operating Voltage
l
VIN2 Maximum Operating Voltage
l
EN2 Threshold Voltage
FB2 Voltage
l
FB2 Bias Current
FB2 = 0.6V
FB2 Line Regulation
2.5V < VIN2 < 5.5V
2
2.7
V
100
130
mV
50
90
mV
2.3
2.5
V
5.5
V
0.3
1
1.5
V
588
600
612
mV
0
100
nA
0.01
SW2 Minimum Off-Time
%/V
70
100
ns
SW2 PMOS Current Limit
(Note 5)
l
1.5
1.9
2.2
A
SW2 NMOS Current Limit
(Note 5)
l
1.2
1.6
2
A
SW2 PMOS RDS(ON)
ISW2 = 0.5A (Note 6)
SW2 NMOS RDS(ON)
ISW2 = 0.5A (Note 6)
ΔFB2 to Enable PGOOD
20
FB2 = 0.6V, IPGOOD = 1mA
mΩ
200
20
ΔFB2 Hysteresis to Disable PGOOD
PGOOD Voltage
275
40
mΩ
80
mV
40
80
mV
200
320
mV
3640f
LT3640
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
SS1, SS2 Charge Current
SS1 = 0.5V, SS2 = 0.5V
1.4
1.9
2.5
µA
SS1 to FB1 Offset Voltage
SS1 = 0.6V
5
30
mV
SS2 to FB2 Offset Voltage
SS2 = 0.3V
5
30
mV
92
94
%
92
94
RST1 Threshold as Percentage of VFB
l
90
RST2 Threshold as Percentage of VFB
l
89
Undervoltage to RST Assert Time
20
RST1, RST2, WDO Pull-Up Current
RST1, RST2, WDO = 0V
RST1, RST2, WDO Output Voltage
IRST1, IRST2, IWDO = 2mA
RST1, RST2 Timeout Period (tRST)
CPOR = 220pF
5
l
UNITS
%
µs
15
30
µA
150
250
mV
8
9.5
11
ms
Watchdog Start Delay Time (tDLY)
CWDT = 820pF
14
16
18
ms
Watchdog Upper Boundary (tWDU)
CWDT = 820pF
l
27
32
35
ms
Watchdog Lower Boundary (tWDL)
CWDT = 820pF
l
1.68
2
2.2
ms
WDI Pull-Up Current
WDI = 1.2V
WDI Voltage Threshold
0.55
0.85
WDI Low Minimum Pulse Width
300
ns
WDI High Minimum Pulse Width
300
ns
WDE Pull-Down Current
2
WDE = 2V
WDE Threshold
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3640E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3640I is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range.
µA
1.15
1
l
0.5
0.7
V
µA
0.9
V
Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation
to static test. Slope compensation reduces current limit at higher duty
cycle.
Note 4: The oscillator cycle is extended when DA current exceeds its limit.
DA current limit is flat over duty cycle.
Note 5: If the SW2 NMOS current exceeds its limit at the start of an
oscillator cycle, the PMOS will not be turned on in the cycle.
Note 6: The QFN switch RDS(ON) is guaranteed by correlation to wafer level
measurement.
Note 7: Absolute maximum voltage at VIN and RUN/SS pin is 55V for
nonrepetitive one second transients, and 36V for continuous operation.
3640f
LT3640
Typical Performance Characteristics
HV Channel Efficiency
(2MHz, VOUT1 = 5V)
HV Channel Efficiency
(2MHz, VOUT1 = 3.3V)
90
90
80
VIN = 24V
75
85
VIN = 24V
VIN = 16V
80
75
0
0.2
0.4
0.6
0.8
1.0
VOUT1 CURRENT (A)
70
1.2
0.35
0
0.2
0.4
0.6
0.8
1.0
VOUT1 CURRENT (A)
VIN QUIESCENT CURRENT (mA)
EFFICIENCY (%)
VIN2 = 5V
80
75
0
0.2
0.4
0.6
VOUT2 CURRENT (A)
0.8
0.20
0.15
0.10
0.05
0.00
1.0
0
10
20
1.35
1.2
30
200
150
100
50
0
–50
40
0
50
100
150
TEMPERATURE (°C)
3640 G06
FB2 Voltage vs Temperature
0.70
0.65
1.0
FB2 VOLTAGE (V)
RST1 THRESHOLD
1.15
1.0
250
FB1 Voltage vs SS1
1.25
0.8
3640 G05
1.4
REGULATION
0.4
0.6
VOUT2 CURRENT (A)
300
VIN VOLTAGE (V)
FB1 VOLTAGE (V)
FB1 VOLTAGE (V)
0.2
Quiescent Current vs Temperature
0.25
FB1 Voltage vs Temperature
0.8
0.6
REGULATION
0.60
RST2 THRESHOLD
0.55
0.4
1.10
0.50
0.2
1.05
1.00
–50
0
350
0.30
1.40
1.20
VIN2 = 5V
3640 G03
Quiescent Current vs VIN
3640 G04
1.30
70
1.2
VIN QUIESCENT CURRENT (µA)
90
85
80
3640 G02
LV Channel Efficiency
(2MHz, VOUT2 = 1.8V)
VIN2 = 3.3V
VIN2 = 3.3V
75
3640 G01
70
90
VIN = 12V
EFFICIENCY (%)
VIN = 16V
70
LV Channel Efficiency
(2MHz, VOUT2 = 1.2V)
85
VIN = 12V
EFFICIENCY (%)
EFFICIENCY (%)
85
TA = 25°C, unless otherwise noted.
0
50
100
150
0.0
0
0.5
1.0
1.5
2.0
SS1 VOLTAGE (V)
TEMPERATURE (°C)
3640 G07
0.45
–50
0
50
100
150
TEMPERATURE (°C)
3640 G08
3640 G09
3640f
LT3640
Typical Performance Characteristics
Switching Frequency
vs Temperature
FB2 Voltage vs SS2
0.52
SWITCHING FREQUENCY (MHz)
FB2 VOLTAGE (mV)
600
500
400
300
200
100
0
200
400
6000
800
2.5
RT = 182k
0.51
0.50
0.49
0.48
–50
1000
HV Channel Current Limit
vs Duty Cycle
SW1 PEAK CURRENT LIMIT (A)
700
0
TA = 25°C, unless otherwise noted.
50
0
100
450
1.5
1.0
0.5
60
80
0.40
350
0.35
300
PMOS
250
200
NMOS
150
0.5
0
1
0
5
VIN = 16V
VIN = 24V
0.4
15
0.6
0.8
1.0
1.2
20
25
30
VIN VOLTAGE (V)
2.5
VIN = 12V
0.2
10
3640 G15
3640 G14
SWITCHING FREQUENCY (MHz)
SWITCHING FREQUENCY (MHz)
0
1.5
SW2 CURRENT (A)
RT = 32.4k
0
2MHz
0.15
0.10
0
100
0.20
0.05
0.5
0
80
2.5MHz
0.25
50
100
1.5
60
VOUT1 Minimum Load to Run at
Full Frequency (VOUT1 = 3.3V)
0.30
100
HV Channel Switching Frequency
(VOUT1 = 3.3V)
1.0
0.45
400
3640 G13
2.0
40
20
3640 G12
LV Channel Switch Voltage
Drop vs Current (VIN2 = 3.3V)
DUTY CYCLE (%)
2.5
0
DUTY CYCLE (%)
VOUT1 CURRENT (A)
SW2 VOLTAGE DROP (mV)
SW2 PEAK CURRENT LIMIT (A)
2.0
40
0.5
3640 G11
LV Channel Peak Current Limit
vs Duty Cycle
20
1.0
0.0
150
3640 G10
0
1.5
TEMPERATURE (°C)
SS2 VOLTAGE (mV)
0.0
2.0
LV Channel Switching Frequency
(VOUT2 = 1.8V)
VIN2 = 3.3V
2.0
1.5
VIN2 = 5V
1.0
0.5
0
0
0.2
0.4
0.6
0.8
1.0
VOUT2 CURRENT (A)
VOUT1 CURRENT (A)
3640 G16
3640 G17
3640f
LT3640
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
SW1
10V/DIV
SW1
10V/DIV
IL1
0.5A/DIV
IL1
0.5A/DIV
SW2
5V/DIV
SW2
5V/DIV
IL2
0.5A/DIV
IL2
0.5A/DIV
200ns/DIV
VIN2 = VOUT1
VIN1 = 12V
VOUT1 = 3.3V/0.5A VOUT2 = 1.8V/0.5A
3640 G18
500ns/DIV
VIN2 = VOUT1
VIN1 = 12V
VOUT1 = 3.3V/25mA VOUT2 = 1.8V/30mA
3640 G19
180
160
140
120
100
80
60
40
20
0
0
1000
2000
3000
4000
5000
CWDT CAPACITANCE (pF)
3640 G20
RST/WDO Pull-Up Current
35
20
30
RST/WDO PULL-UP CURRENT (µA)
WATCHDOG UPPER BOUNDARY PERIOD (ms)
Watchdog Upper Boundary
Period vs Temperature
25
20
15
10
5
0
–50
Watchdog Upper Boundary
Period vs CWDT
Light Load Operation Waveforms
WATCHDOG UPPER BOUNDARY PERIOD (ms)
Full Frequency Waveforms
0
50
100
150
TEMPERATURE (°C)
3640 G21
15
10
5
0
0
1
1.5
0.5
RST/WDO VOLTAGE (V)
2
3640 G22
3640f
LT3640
Pin Functions
(FE/QFN)
FB2 (Pin 1/Pin 26): The low voltage converter regulates the
FB2 pin to 600mV. Connect the feedback resistor divider
tap to this pin to set output voltage.
PGOOD (Pin 2/Pin 27): Open-drain logic output that starts
to sink current when FB2 is in regulation.
EN/UVLO (Pin 3/Pin 28): Pull this pin below 0.3V to shut
down the LT3640. The 1.26V threshold can function as an
accurate undervoltage lockout, preventing the LT3640 from
operating until VIN voltage has reached the programmed
level.
SYNC (Pin 4/Pin 1): Driving the SYNC pin with an external
clock signal synchronizes both converters to the applied
frequency. The lowest external clock frequency should be
20% higher than the internal oscillator frequency.
SS1 (Pin 5/Pin 2): The SS1 pin sets the FB1 voltage externally between 0V and 1.265V, providing soft-start and
tracking. Tie this pin 1.5V or higher to use the internal
1.265V reference. A capacitor to ground at this pin sets the
ramp time to regulated output voltage for the high voltage
converter. Use a resistor divider to track another supply.
FB1 (Pin 6/Pin 3): The high voltage converter regulates the
FB1 pin to 1.265V. Connect the feedback resistor divider
tap to this pin to set output voltage.
RT (Pin 7/Pin 4): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the internal oscillator
frequency.
RST2 (Pin 8/Pin 5): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB2 goes above 550mV.
RST1 (Pin 9/Pin 6): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB1 goes above 1.165V.
WDO (Pin 10/Pin 7): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor if
WDE is enabled and WDI pin is not driven by an appropriate signal.
CWDT (Pin 11/Pin 8): Connect a capacitor to ground at
this pin to set watchdog timer.
CPOR (Pin 12/Pin 9): Connect a capacitor to ground at this
pin to set the power-on reset timer and WDO output timer.
WDE (Pin 13/Pin 10): Watchdog Enable Pin.
WDI (Pin 14/Pin 11): The WDI pin receives watchdog
signals from a microprocessor.
GND (Pins 15, 16, 23, 26, Exposed Pad Pin 29/Pins 12,
13, 20, 23, Exposed Pad Pin 29): Ground. These pins
must be soldered to PCB ground.
NC (Pin 17/Pin 14): Not Connected. This pin can be connected to ground.
DA (Pin 18/Pin 15): The DA pin is used to sense the catch
diode current for current limit and protection. Connect this
pin to catch diode anode.
SW1 (Pin 19/Pin 16): Output of the High Voltage Internal
Power Switch. Connect this pin to the inductor and catch
diode cathode.
SW (Pin 20/Pin 17): The SW pin is used to charge the
boost capacitor. Connect this pin to the boost capacitor.
BST (Pin 21/Pin 18): The BST pin is used to provide a drive
voltage, higher than VIN pin voltage, to the high voltage
channel internal power switch. Connect an external boost
diode to this pin.
VIN (Pin 22/Pin 19): The VIN pin supplies current to
the LT3640’s internal circuitry and to the high voltage
channel internal power switch. This pin must be locally
bypassed.
VIN2 (Pin 24/Pin 21): The VIN2 pin supplies current to the
internal power MOSFET of the low voltage converter and
to the LT3640’s internal circuitry when VIN2 is above 3V.
SW2 (Pin 25/Pin 22): Switch Node of the Low Voltage
Converter. Connect this pin to an inductor.
EN2 (Pin 27/Pin 24): Low Voltage Converter Enable Pin.
Pull this pin below 0.3V to shut down the low voltage
converter. Pull this pin above 1.5V to enable the low voltage converter.
SS2 (Pin 28/Pin 25): The SS2 pin sets the FB2 voltage
externally between 0V and 0.6V, providing soft-start and
tracking. Tie this pin 0.8V or higher to use the internal
0.6V reference. A capacitor to ground at this pin sets the
ramp time to regulated output voltage for the low voltage
converter. Use a resistor divider to track another supply.
3640f
LT3640
Block Diagram
CIN
VIN
2µA
BST
EN/
UVLO
100k
+
A4
–
5.5V
–
A3
+
ENABLE
CBST
R
S
Q1
Q
SW
DRIVER
+
–
VREF
1.265V
A1
2µA
R2
L1
SW1
SS1
VOUT1
DBST
+
–
+
gm1
VC1
3
RAMP
GENERATOR
DA
–
A2
+
OSCILLATOR
D1
VOUT1
COUT1
FB1
+
–
R1
RT
SYNC
– +
A8
3
A5
+
–
VIN2
CIN2
2µA
SS2
VOUT2
R4
+
–
+
gm2
VC2
+
A7
–
R
S
Q
SW2
LOGIC
CIRCUIT
50mV
+
–
VREF
600mV
A6
– +
PGOOD
VOUT2
COUT2
FB2
R3
L2
–
+
A9
EN2
2µA
CPOR
2µA
RST1
CWDT
WATCHDOG
TIMER
POR TIMER
RST2
WDE
WDI
WDO
3640 BD
3640f
LT3640
Timing Diagrams
Power-On Reset Timing
FB
tUV
RST
tRST
Watchdog Timing
WDI
WDO
tDLY
t < tWDL tRST
t < tWDU
tWDL < t < tWDU
tWDU
tRST
3640 TD
Operation
The LT3640 is a dual channel, constant-frequency, current
mode monolithic buck switching regulator with power-on
reset and watchdog timer. Both channels are synchronized
to a single oscillator with frequency set by RT. Operation can
be best understood by referring to the Block Diagram.
Buck Regulators
The high voltage channel is a nonsynchronous buck
regulator that operates from the VIN pin. The start of each
oscillator cycle sets an SR latch and turns on the internal
NPN power switch. An amplifier and comparator monitor
the current flowing between the VIN and SW1 pins, turning
the switch off when this current reaches a level determined
by the voltage at VC1 node. An error amplifier measures
the output voltage through an external resistor divider tied
to the FB1 pin and servos the VC1 node. The reference
of the error amplifier is determined by the lower of the
internal reference and the voltage at the SS1 pin. If the error
amplifier’s output increases, more current is delivered to
the output; if it decreases, less current is delivered.
An active clamp (not shown) on the VC1 node provides
peak current limit. A DA pin current comparator extends
the oscillator cycle until the catch diode current is below
the valley current limit. Both the peak and valley current
limits help to control the inductor current in fault conditions such as shorted output with high VIN. Both current
limits are reduced when the voltage at the FB1 pin is below
0.2V. This current foldback helps to control the inductor
current during start-up and overload.
The NPN power switch driver operates from either the VIN
pin or the BST pin. An external capacitor and diode are
used to generate a voltage between the BST and SW pins.
During the power-up of the LT3640, an internal 5mA current
source charges the external BST capacitor. The regulator
starts switching when the (BST-SW) voltage reaches the
2V threshold. The internal NPN power switch can be fully
saturated for efficient operation when the (BST-SW) voltage is between 2.3V and 5.5V.
The low voltage channel is a synchronous buck regulator
that operates from the VIN2 pin. It starts switching only
3640f
10
LT3640
Operation
when the VIN2 pin voltage is above 2.3V, the EN2 pin is
pulled high and the FB1 pin voltage is above 1.165V. The
internal top power MOSFET is turned on each cycle at the
beginning of each oscillator cycle, and turned off when
the current flowing through the top MOSFET reaches a
level determined by the voltage at the VC2 node. An error
amplifier measures the output voltage through an external
resistor divider tied to the FB2 pin and servos the VC2
node. The reference of the error amplifier is determined by
the lower of the internal 600mV reference and the voltage
at the SS2 pin.
While the top MOSFET is off, the bottom MOSFET is turned
on in an oscillator cycle until the inductor current starts
to reverse. If the inductor current is higher than the valley
current limit at the beginning of an oscillator cycle, the top
MOSFET will not turn on in this cycle, limiting inductor
current in shorted output fault.
An internal regulator provides power to the control circuitry.
The regulator draws most power from the VIN2 pin and a
small portion of power from the VIN pin when the VIN2 pin
voltage is higher than 3V. If the voltage at VIN2 pin is lower
than 3V, the regulator draws all power from the VIN pin.
The EN/UVLO pin is used to put the LT3640 in shutdown,
reducing the input current to less than 1µA. The accurate
1.26V threshold of the EN/UVLO pin provides a programmable VIN undervoltage lockout through an external resistor
divider tied to the EN/UVLO pin. A 2µA hysteresis current
on the EN/UVLO pin prevents switching noise from shutting down the LT3640.
The LT3640 has an overvoltage protection feature which
disables switching action in both channels when the VIN
pin voltage goes above 36V. When switching is disabled,
the LT3640 can sustain VIN voltages up to 55V for one
second.
Internal 2µA current sources charge the SS1 pin and
the SS2 pin up to about 2V. Soft-start or output voltage
tracking of the two channels can be independently implemented with capacitors from the SS1 pin and the SS2 pin
to ground. Any overvoltage or undervoltage condition on
the VIN pin triggers an internal latch that discharges the
SS1 pin to below 100mV before it is released. If the EN2
pin goes low, the VIN2 voltage falls below 2.2V or the FB1
pin goes below 1.165V, the SS2 pin will be discharged to
below 100mV before it is released.
To optimize efficiency, the LT3640 switches to low ripple
Burst Mode operation in light load situations. Between
switching pulses, control-circuitry current is minimized.
A power good comparator with 40mV of hysteresis trips
when the low voltage channel is enabled and the FB2 pin is
above 550mV. The PGOOD pin is an open-drain output that
is pulled low when both the outputs are in regulation.
Power-On Reset and Watchdog Timer
The LT3640 includes one power-on reset timer for each
buck regulator and one common watchdog timer. Poweron reset and watchdog timers are both adjustable using
external capacitors. Operation can be best understood by
referring to the Timing Diagram.
The RST1, RST2 and WDO pins are all open-drain outputs
with weak internal pull-ups to about 2V. The RST1 and RST2
pins are pulled low when the LT3640 is enabled and VIN is
above 3.6V. Once the FB1 pin rises above 1.165V, the high
voltage channel reset timer is started and RST1 is released
after the reset timeout period. The low voltage channel reset
timer is started once the FB2 pin rises above 550mV, and
releases RST2 after the reset timeout period.
The watchdog circuit monitors a µP’s activity. As soon
as both RST1 and RST2 are released, a delay timer is
started. The watchdog timer is started after the delay timer
times out. The LT3640 implements windowed watchdog
function for higher system reliability. The watchdog timer
detects falling edges on the WDI pin. If the falling edges
are grouped too close together or too far apart, the WDO
pin is pulled down and the reset timer is started. When the
reset timer times out, WDO is released and the watchdog
timer is again started after the delay period.
3640f
11
LT3640
Applications Information
Setting the Output Voltages
The internal reference voltage is 1.265V for the high voltage channel, and 600mV for the low voltage channel. The
output voltages are set by resistor dividers according to
the following formulas:
 V

R2 = R1 •  OUT1 − 1
 1 . 265V 
V

R4 = R3 •  OUT2 − 1
 0 . 6V

Use 1% resistors in the resistor dividers. To avoid noise
problems, R1 should be 100k or less, and R3 should
be 50k or less. Reference designators refer to the Block
Diagram.
Switching Frequency
The LT3640 uses a constant-frequency PWM architecture
that can be programmed to switch from 350kHz to 2.2MHz
by using a resistor tied from the RT pin to ground. Table
1 shows the necessary RT value for a desired switching
frequency.
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz)
RT (k)
0.35
267
0.5
182
1
82.5
2
32.4
2.2
27.4
Selection of the operating frequency is mainly a trade-off
between efficiency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The disadvantage is lower
efficiency.
The high switching frequency also decreases the duty
cycle range. The reason is that the LT3640 switches have
finite minimum on- and off-times independent of the
switching frequency. The top switch in the high voltage
channel can turn on for a minimum of ~60ns and turn off
for a minimum of ~70ns. The top switch in the low voltage
channel can turn on for a minimum of ~110ns and turn
off for a minimum of ~70ns. The minimum and maximum
duty cycles are:
DCMIN = fS • tON(MIN)
DCMAX = 1 – fS • tOFF(MIN)
where fS is the switching frequency, tON(MIN) is the minimum switch on-time, and tOFF(MIN) is the minimum switch
off-time. These equations illustrate how duty cycle range
increases when switching frequency decreases.
The internal oscillator of the LT3640 can be synchronized
to an external 350kHz to 2.5MHz positive clock signal on
the SYNC pin. The RT value should be chosen such that
the internal oscillator’s frequency is 20% lower than the
lowest SYNC clock frequency (refer to Table 1). To avoid
erratic operation, the LT3640 ignores the SYNC signal
until the FB1 pin voltage is above 1.165V. When applying
a SYNC signal, the rising edges reset the LT3640’s internal
clock and initiate a switch cycle. The amplitude of the
SYNC signal must be at least 2V. The SYNC pulse width
must be at least 40ns.
VIN Voltage Range
The LT3640’s minimum operating voltage is 3.6V typical.
A higher minimum operating voltage can be accurately
programmed with a resistor divider between the VIN pin
and the EN/UVLO pin. The EN/UVLO threshold is 1.26V.
When the LT3640 is enabled, a 2µA current flows out of the
EN/UVLO pin generating hysteresis to prevent the switching action from falsely disabling the LT3640. Choose the
divider resistances for appropriate hysteresis voltage.
The high voltage nonsynchronous channel operates from
the VIN pin. The minimum VIN voltage to regulate output
voltage is:
V
+V 
VIN(MIN) =  OUT1 D  − VD + VCE
 DCMAX 
Where VD is the forward voltage drop of the catch diode, VCE
is the voltage drop of the internal NPN power switch, and
DCMAX is the maximum duty cycle (refer to the Switching
Frequency section). If VIN is below the calculated minimum
voltage, output will lose regulation.
3640f
12
LT3640
Applications Information
The maximum VIN should not exceed the absolute maximum rating. For fixed frequency operation, the maximum
VIN is:
calculated minimum voltage, the output will fall out of
regulation.
The maximum VIN2 for fixed frequency operation is:
V
+V 
VIN(MAX ) =  OUT1 D  − VD + VCE
 DCMIN 
Note that the high voltage buck will still regulate at an input
voltage that exceeds VIN(MAX) (up to 35V). However, the
switching frequency will be lowered to satisfy the equation (Figure 1).
Where DCMIN is the minimum duty cycle (refer to the Switching Frequency section). For voltage that exceeds VIN2(MAX)
(up to 5.5V), the low voltage channel exhi-bits pulse-skipping behavior, and the output ripple will increase.
Once the input voltage reaches 36.5V, an internal overvoltage
lockout (OVLO) circuit is triggered to disable switching action (Figure 2). Without switching, the LT3640 can sustain
VIN voltage transients up to 55V for one second.
The low voltage synchronous channel operates from
the VIN2 pin. The VIN2 pin can be connected to either an
independent voltage supply or the high voltage channel
output for a two-stage power regulator.
In either configuration, if the high voltage channel is overloaded and pulled out of regulation, the low voltage channel
will be disabled. The SS2 pin will be discharged as well.
The minimum VIN2 voltage to regulate output voltage is:
VOUT2
DCMIN
Inductor Selection
Inductor selection involves inductance, saturation current,
series resistance (DCR) and magnetic loss.
The inductance for the high voltage channel is:
VIN2 Voltage Range
VIN2(MIN) ≈
VIN2(MAX ) ≈
VOUT 2
DCMAX
Where DCMAX is the maximum duty cycle (refer to
the Switching Frequency section). If VIN2 is below the
VOUT1 + VD
fS
where VOUT1 is high voltage channel output voltage, VD
is the forward voltage drop of the catch diode, and fS is
the switching frequency. For example, 3.3µH is a reasonable inductance for a 3.3V output with 2MHz switching
frequency.
Once the inductance is selected, the inductor current ripple
and peak current can be calculated:
SW1
10V/DIV
L1 = 1.7 •
∆IL1 =
( VOUT1 + VD )  VOUT1 + VD 
•  1–

IL1 • fS
VIN

IL(PEAK ) = IOUT(MAX ) +
∆ IL
2
IL1
2A/DIV
IL1
0.5A/DIV
200ns/DIV
VIN = 30V
VOUT1 = 3.3V/0.2A
3640 F01
RT SET = 2MHz
Figure 1. Lower Switching Frequency Occurs in High
Voltage Channel When Required On-Time Is Below 50ns
VIN
20V/DIV
55VPK, 40V, 15V
10µs/DIV
3640 F02
Figure 2. VIN Overvoltage Lockout
3640f
13
LT3640
Applications Information
To guarantee sufficient output current, peak inductor current must be lower than the switch current limit (ILIM).
The largest inductor current ripple occurs at the highest
VIN. To guarantee current capacity, use VIN(MAX) in the
above formula.
The inductance for the low voltage channel is:
L2 = 1.5
VOUT 2
fS
For a selected inductance, the inductor current ripple can
be calculated:
∆IL2 =
VOUT2
L2 • fS
 V

•  1– OUT 2 
VIN2 

For robust operation in fault conditions, the inductor
saturation current should be higher than the upper limit
of the corresponding top switch current limit.
To keep the efficiency high, the inductor series resistance
(DCR) should be as small as possible (must be < 0.1Ω),
and the core material should be intended for the chosen
operation frequency. High efficiency converters generally
cannot afford the core loss found in low cost powdered
iron cores; instead use ferrite, molypermalloy or Kool Mµ
cores. Table 2 lists several vendors and suitable inductor
series.
Of course, such a simple design guide will not always
result in the optimum inductors for the applications. A
larger value inductor provides a slightly higher maximum
load current and will reduce the output voltage ripple. A
larger value inductor also results in higher efficiency in the
condition of same DCR and same magnetic loss. However,
for a same series of inductors, a larger value inductor has
higher DCR. The trade-off between inductance and DCR
is not always obvious. Use experiments to find optimum
inductors.
Low inductance may result in discontinuous mode operation, which is okay, but reduces maximum load current.
For details of maximum output current and discontinuous
mode operation, see the Linear Technology Application Note
44. For duty cycles greater than 50%, there is a minimum
inductance required to avoid subharmonic oscillations.
See the Linear Technology Application Note 19.
Input Capacitor
Bypass the VIN pin of the LT3640 with a ceramic capacitor
of X7R (–55°C to 125°C) or X5R (–55°C to 85°C) type.
Buck converters draw pulse current from the input supply. The input capacitor is required to reduce the resulting
voltage ripple. Use a ceramic capacitor with:
Table 2. Inductor Vendors
PART SERIES
VENDOR
LQH55D
Murata
www.murata.com
SLF7045
SLF10145
TDK
www.componenttdk.com
D62CB, D63CB
D75C, D75F
TOKO
www.toko.com
CR54, CDRH74
CDRH6D38, CR75
Sumida
www.sumida.com
CIN ≥
10µF
fS
where fS in the switching frequency in MHz.
A second precaution regarding the ceramic input capacitor
concerns the maximum input voltage rating of the LT3640.
A ceramic input capacitor combined with trace or cable
inductance forms a under damped tank circuit. If the LT3640
circuit is plugged into a live supply, the input voltage can
ring to twice its nominal value, possibly exceeding the
LT3640’s voltage rating. This situation can be easily avoided
(see the Linear Technology Application Note 80).
3640f
14
LT3640
Applications Information
Output Capacitors and Output Ripple
The output capacitor has two essential functions. In steady
state, it determines the output voltage ripple. In transient,
it stores energy in order to satisfy transient loads and
stabilize the control loop. Ceramic capacitors have low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
150
COUT1 =
VOUT • fS
where fS is in MHz, and COUT is the recommended output
capacitance in µF. Use X5R or X7R types. This choice will
provide low output ripple and good transient response.
A good starting value for the low voltage channel output
capacitor is:
COUT2 =
100
VOUT2 • fS
In the case where VIN2 is connected to the high voltage
channel output, the high voltage channel output capacitor
can be used as the low voltage channel input capacitor.
The required VIN2 input capacitor value is usually smaller
than the high voltage output capacitor.
Low ESR ceramic capacitors for VIN2 input and high voltage channel output could form resonant tank and cause
jitter in certain operating area. Avoid VIN2 input capacitor
if possible.
When choosing a capacitor, look carefully through the
data sheet to find out what the actual capacitance is under
operating conditions (applied voltage and temperature).
A physically larger capacitor or one with a higher voltage
rating may be required. High performance tantalum or
electrolytic capacitors can be used for the output capacitor.
Low ESR is important, so choose one that is intended for
use in switching regulators. Table 3 lists several capacitor
vendors.
Table 3. Capacitor Vendors
PART SERIES
VENDOR
Ceramic, Polymer, Tantalum
Panasonic
www.panasonic.com
Ceramic, Tantalum
Kemet
www.kemet.com
Ceramic, Polymer, Tantalum
Sanyo
www.sanyovideo.com
Ceramic
Murata
www.murata.com
Ceramic, Tantalum
AVX
www.avxcorp.com
Ceramic
Taiyo Yuden
www.taiyo-yuden.com
Catch Diode
The high voltage channel requires an external catch diode
to conduct current during switch off-time. Average forward
current in normal operation can be calculated from:
ID( AVG) =
IOUT ( VIN − VOUT )
VIN
where IOUT is the output load current. Use a 1A or 2A
rated Schottky diode. Peak reverse voltage is equal to the
regulator input voltage. Use a diode with a reverse voltage
rating greater than the input voltage. Table 4 lists several
Schottky diodes and their manufacturers.
Table 4. Diode Vendors
PART NUMBER
VR
(V)
IAVE
(A)
VF AT 1A
(MV)
VF AT 2A
(MV)
20
40
1
1
530
595
20
30
20
30
40
1
1
2
2
2
500
500
30
30
1
2
420
On Semiconductor
MBRM120E
MBRM140
Diodes Inc.
B120
B130
B220
B230
DFLS240L
500
500
500
International Rectifier
10BQ030
20BQ030
470
470
3640f
15
LT3640
Applications Information
BST and SW Pin Considerations
The high voltage channel requires an external capacitor
between the BST and SW pins and an external boost diode
from a voltage source to the BST pin. In most cases, a
0.22µF capacitor will work well. The (BST-SW) voltage
cannot exceed 5.5V, and must be more than 2.3V for best
efficiency. Connect the boost diode to any voltage between
2.7V and 5.5V. The VIN2 pin is the best choice if the low
voltage channel is used.
The high voltage channel will not start until the (BST-SW)
voltage is 2V or above. When the LT3640 is enabled, an
internal ~5mA current source from VIN flows out of the BST
pin. The SW pin is disconnected from the SW1 pin, and is
pulled down by an internal current source to ground. The
external boost capacitor can be charged up regardless of
the output. When the (BST-SW) voltage reaches 2V, the SW
pin is connected to the SW1 pin, and the high voltage channel starts switching. However, the internal bipolar power
switch cannot be fully saturated until the (BST-SW) voltage
is further charged to above 2.3V. To start up a traditional
nonsynchronous buck regulator with very light load, the
input voltage needs to be a couple of volts higher than
the minimum running input voltage if the input voltage is
ramping up slowly. The LT3640’s unique boost capacitor
charging scheme solves this start-up issue. Figure 3 shows
that the minimum input voltage to start the high voltage
channel nonsynchronous buck regulator of the LT3640 is
very close to the minimum input voltage to regulate the
output voltage for most of the load range.
Soft-Start
The LT3640 has a soft-start pin for each channel. The
feedback pin voltage is regulated to the lower of the corresponding SS pin and the internal references, which is
1.265V for the high voltage channel, and 600mV for the low
voltage channel. A capacitor from the SS pin to ground is
charged by an internal 2µA current source resulting in an
output ramping linearly from 0V to the regulated voltage.
The duration of the ramp is:
t SS1 = C SS1 •
t SS2 = C SS2 •
1 . 265V
2 µA
600mV
2 µA
where tSS1 is the ramping time for the SS1 pin, tSS2 is
the ramping time for the SS2 pin, CSS1 is the capacitance
from the SS1 pin to ground, and CSS2 is the capacitance
from the SS2 pin to ground.
At power-up, a latch is set to discharge the SS1 pin.
After the SS1 pin is discharged to below 100mV, the latch
is reset. The internal 2µA current source starts to charge
the SS1 pin when the (BST-SW) voltage is charged to
above 2V.
5
5
START
3
2
1
0
0.001
START
4
RUN
VIN VOLTAGE (V)
VIN VOLTAGE (V)
4
RUN
3
2
1
0.01
0.1
VOUT CURRENT (A)
1
0
0.001
0.01
0.1
VOUT CURRENT (A)
3640 F03a
(3a) FS = 2MHz
1
3640 F03b
(3b) FS = 500kHz
Figure 3. High Voltage Channel Minimum Input Voltage for VOUT1 = 3.3V
3640f
16
LT3640
Applications Information
In the event of VIN undervoltage lockout, VIN overvoltage
lockout or the EN/UVLO pin being driven below 1.26V, the
soft-start latch is set, triggering a start-up sequence.
A latch is set to discharge the SS2 pin at power-up. After
the FB1 pin reaches 1.165V, the VIN2 voltage is above 2.3V,
the EN2 pin is enabled, and the SS2 pin is below 100mV,
the latch is reset. The internal 2µA current source starts
to charge the SS2 pin.
EN
2V/DIV
VOUT1
2V/DIV
VOUT2
1V/DIV
PGOOD
2V/DIV
500µs/DIV
In the event of VFB1 out of regulation, the VIN2 pin falling
below 2.2V, or the EN pin going low, the SS2 discharging
latch is set, triggering a start-up sequence.
3640 F04
VIN = 12V
RT SET = 2MHz
Figure 4. Soft-Start of LT3640
The SS pins can also be pulled up by external current
sources or resistors for output tracking. The external pullup current should not exceed 100µA for either SS pin.
Figure 4 shows the soft-start for a 3.3V and 1.8V
application.
SW1
10V/DIV
Shorted-Output Protection
IL1
0.5A/DIV
If an inductor is chosen that will not saturate excessively,
the LT3640 will tolerate a shorted output. For the high
voltage channel, the DA current comparator extends the
internal oscillator period until the catch diode current is
below its limit. Both the top switch and the DA comparator
have current foldback to help limit load current when the
output is shorted to ground. The DA current limit is 1.7A
when the FB1 voltage is above 0.2V, and is 1A when the
FB1 voltage is below 0.2V. Figure 5 shows the high voltage
channel operation under shorted output.
Because of the low VIN2 voltage, the low voltage channel
does not have current foldback. The low voltage channel
does not extend the internal oscillator in shorted output
condition allowing the high voltage channel to operate
in constant frequency. If the bottom MOSFET current
exceeds the NMOS current limit at the start of a clock
cycle, the top MOSFET is kept off in this cycle (similar to
pulse-skipping operation). The inductor valley current is
kept below the NMOS current limit to ensure robustness
in shorted output condition (Figure 6).
1µs/DIV
3640 F05
VIN = 30V
VOUT1 = SHORT
Figure 5. The High Voltage Channel Reduces Frequency
to Protect Against Shorted Output With 30V Input
SW2
2V/DIV
IL2
1A/DIV
1µs/DIV
3640 F06
VIN2 = 5V
VOUT2 = SHORT
Figure 6. The Low Voltage Channel Operates in
Pulse-Skipping Mode to Protect Against Shorted Output
3640f
17
LT3640
Applications Information
Reverse Protection
In battery charging applications or in battery back-up
systems, the output will be held high when the input to the
LT3640 is absent. If the VIN pin is floated and the LT3640 is
enabled, the LT3640’s internal circuitry will pull its quiescent
current through the SW1 pin or the SW2 pin. This is fine if
the system can tolerate a few mA in this state. If the LT3640
is disabled, the SW1 pin and the SW2 pin current will drop
to essentially zero. However, if the VIN pin is grounded while
the high voltage channel output is held high, an external
diode is required at the VIN pin to prevent current being
pulled out of the VIN pin. If the VIN2 pin is grounded while
the low voltage channel output is held high, an external
diode is required at the VIN2 pin to prevent current being
pulled out of the VIN2 pin (Figure 7).
IN
VIN SW
BST SW1
EN/UVLO
DA
FB1
OUT1
SW1
10V/DIV
IL1
0.5A/DIV
SW2
5V/DIV
IL2
0.5A/DIV
3640 F08a
500ns/DIV
VIN2 = VOUT1
VIN = 12V
VOUT1 = 3.3V/25mA VOUT2 = 1.8V/30mA
(8a)
SW1
10V/DIV
IL1
0.5A/DIV
SW2
5V/DIV
IL2
0.5A/DIV
+
–
3640 F08b
2µs/DIV
VIN2 = VOUT1
VIN = 12V
VOUT1 = 3.3V/25mA VOUT2 = 1.8V/20mA
LT3640
SW2
IN2
VIN2
FB2
OUT2
(8b)
+
–
GND
3640 F07
Figure 7. Diodes Prevent Shorted Inputs from
Discharging a Battery Tied to the Outputs
PFM Operation
To improve efficiency at light loads, the LT3640 automatically switches to pulse frequency modulation (PFM)
operation which minimizes the switching loss and keeps
the output voltage ripples small.
Because the two channels of the LT3640 may have different loads, the two channels can have different switching
frequency (Figure 8).
Power-On Reset Timer
Each channel of the LT3640 has a power-on comparator. Both
comparators are enabled when the LT3640 is powered up
and starts monitoring their corresponding feedback voltages.
SW1
10V/DIV
IL1
0.5A/DIV
SW2
5V/DIV
IL2
0.5A/DIV
3640 F08c
2µs/DIV
VIN2 = VOUT1
VIN = 12V
VOUT1 = 3.3V/0mA VOUT2 = 1.8V/30mA
(8c)
Figure 8. PFM Operation
The threshold of power-on comparator is 1.15V for the high
voltage channel, and 550mV for the low voltage channel.
Both RST1 and RST2 are open-drain outputs with weak
internal pull-ups (100k to ~2V). The DC characteristics of
the RST1 and RST2 pull-down strength are shown in the
Typical Performance Characteristics section. The weak
3640f
18
LT3640
Applications Information
pull-ups eliminate the need for external pull-ups when
the rise time of these pins is not critical. The open-drain
configuration allows wired-OR connections.
The two power-on reset timers share one oscillator. The
power-on reset timeout period, t RST (64 cycles on the
CPOR pin), which is the same for the two channels, can
be programmed by connecting a capacitor, CPOR, between
the CPOR pin and ground:
 s
t RST = CPOR • 37 • 10 6  
F
For example, using a capacitor value of 8.2nF gives a
303ms reset timeout period. The accuracy of t RST will be
limited by the accuracy and temperature coefficient of the
capacitor CPOR. Extra parasitic capacitance on the CPOR
pin, such as probe capacitance, can affect t RST.
Watchdog
The WDE pin is the enable pin for the watchdog. As soon
as both RST1 and RST2 are released, the watchdog starts
a delay period, tDLY, during which the input signal at the
WDI pin is ignored for higher reliability. After the delay
period, the watchdog starts detecting falling edges on the
WDI pin. If the time between any two WDI falling edges is
shorter than the watchdog lower boundary, tWDL, or longer
than the watchdog upper boundary, tWDU, the WDO pin
is pulled down for a period of t RST, which is the same as
the power-on reset timeout period. When the WDO pin is
released, the watchdog again starts the delay period.
The WDO is open-drain output with weak internal pull-up,
similar to the RST pins.
The delay period corresponding to 33 cycles on CWDT, the
watchdog lower boundary (4 cycles on CWDT), and the
watchdog upper boundary (64 cycles on CWDT) are all
related and set by a capacitor, CWDT, between the CWDT
pin and ground:
 33 
t DLY = t WDU •  
 64 
t
t WDL = WDU
16
 s
t WDU = C WDT • 37 • 10 6  
 F
The accuracy of the watchdog timer will be limited by
the accuracy and temperature coefficient of the capacitor
CWDT. Extra parasitic capacitance on the CWDT pin, such
as probe capacitance, can affect the watchdog timer.
CWDT
CPOR
WD STARTS
64 CYCLES 64 CYCLES
FB2
FB1
RST1
RST2
20ms/DIV
3640 F09a
(9a)
CWDT
CPOR
WDI
WDO
1ms/DIV
3640 F09b
(9b)
CWDT
CPOR
WDI
WDO
50ms/DIV
3640 F09c
(9c)
Figure 9. Power-On Reset and Watchdog Timing
3640f
19
LT3640
Applications Information
Figure 9a shows the power-on reset timing. Having FB1
or FB2 high starts the CPOR oscillator. After t RST, the corresponding RST is released. When both RST1 and RST2
are released, the CWDT oscillator starts. Figure 9b shows
the watchdog waveform with the WDI period between tWDL
and tWDU. The WDI falling edge resets the CWDT oscillator.
The CPOR oscillator is disabled and WDO remains high.
Figure 9c shows the watchdog waveform with the WDI
period longer than tWDU. WDO is asserted for a period of
t RST when the watchdog upper boundary, tWDU, expires.
PCB Layout
For proper operation and minimum EMI, care must be
taken during the printed circuit board (PCB) layout. Figure
10 shows the recommended component placement with
trace, ground plane and via locations. The input loop of
the high voltage channel, which is formed by the VIN
and SW1 pins, the external catch diode (D1), the input
capacitor (CIN) and the ground, should be as small as
possible. These external components should be placed
COUT2
on the same side of the circuit board as the LT3640, and
their connections should be made on that layer. Place a
local, unbroken ground plane below these components.
The BST and SW nodes should be as small as possible.
The boost capacitor (CBST) should be as close to the BST
and SW pins as possible.
The input loop of the low voltage channel is formed by
the VIN2 pin, the input capacitor (CIN2) and the ground.
Place CIN2 close to the VIN2 and the GND pin to minimize
this loop. Place a local, unbroken ground plane below
this input loop.
Keep the FB1 and FB2 nodes small so that the ground
traces will shield them from the switching nodes. The
Exposed Pad on the bottom of the package must be soldered to the ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3640 to additional ground planes within the circuit
board and on the bottom side.
L2
CIN2
CIN
CBST
L1
COUT1
3640 F10
Figure 10. Recommended PCB Layout, FE28 Package
3640f
20
LT3640
Typical Applications
2MHz 3.3V/1.3A and 1.8V/1A Buck Regulators
VIN
5V TO 35V
0.22µF
4.7µF
100k
D2
301k
L1
3.3µH
EN/UVLO
VIN
SW
BST
SW1
SYNC
DA
FB1
WDE
EN2
LT3640
PGOOD
80.6k
D1
49.9k
VIN2
4.7µF
L2
1µH
RST1
RST2
SW2
100k
WDO
WDI
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: DIODES B240A
D2: CENTRAL SEMI CMDSH-4E
VOUT1
3.3V/1.3A
22µF
VIN2
2.5V TO 5.5V
VOUT2
1.8V/1.1A
22µF
FB2
CWDT
CPOR
RT
1.5nF
GND
SS2
49.9k
1nF
32.4k
1.5nF
SS1
1nF
3640 TA02
2MHz 5V/0.8A and 1.2V/1A Buck Regulators
VIN
7V TO 35V
0.22µF
4.7µF
100k
D2
453k
L1
4.7µH
EN/UVLO
VIN
SW
BST
WDE
WDI
100k
100k
100k
100k
WDI
22µF
100k
EN2
LT3640
VIN2
L2
0.47µH
PGOOD
WDO
SW2
49.9k
RST1
RST2
CWDT
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: DIODES B240A
D2: CENTRAL SEMI CMDSH-4E
301k
D1
DA
FB1
SYNC
OUT1
VOUT1
5V/0.8A
SW1
VOUT2
1.2V/1A
22µF
FB2
CPOR
RT
1.5nF
1.5nF
GND
SS2
SS1
49.9k
1nF
32.4k
1nF
3640 TA03
2MHz 2.5V/0.8A and 0.6V/1A Buck Regulators
0.22µF
D2
VIN
4V TO 30V
4.7µF
L1
3.3µH
EN/UVLO
VIN
SW
BST
SW1
SYNC
DA
FB1
WDE
EN2
LT3640
PGOOD
D1
68.1k
VOUT1
3V/0.8A
22µF
49.9k
VIN2
L2
0.47µH
RST1
RST2
SW2
WDO
FB2
VOUT2
0.6V/1A
22µF
WDI
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: ON SEMI MBRS230
D2: CENTRAL SEMI CMDSH2-3
CWDT
CPOR
RT
1.5nF
1.5nF
GND
32.4k
SS2
SS1
1nF
1nF
3640 TA04
3640f
21
LT3640
Package Description
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3640f
22
LT3640
Package Description
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.25 ± 0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3640f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3640
Typical Application
2MHz 3.3V/0.8A and 0.8V/1.2A Buck Regulators
0.22µF
VIN
4V TO 35V
4.7µF
3.3µH
EN/UVLO
VIN
SW
BST
SW1
80.6k
DA
SYNC
VOUT1
3.3V/0.8A
22µF
FB1
WDE
49.9k
EN2
LT3640
PGOOD
VIN2
RST1
0.47µH
RST2
SW2
16.5k
WDO
WDI
VOUT2
0.8V/1.2A
22µF
FB2
CWDT
CPOR
RT
1.5nF
1.5nF
GND
SS2
32.4k
SS1
49.9k
1nF
1nF
3640 TA05
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LT3689
36V, 60V Transient Protection, 800mA, 2.2MHz High Efficiency
MicroPower Step-Down DC/DC Converter with POR Reset and
Watchdog Timer
VIN: 3.6V to 36V, Transient to 60V, VOUT(MIN) = 0.8V, IQ = 75µA,
ISD < 1µA, 3mm × 3mm QFN-16 Package
LT3686
37V, 55VMAX, 1.2A, 2.5MHz High Efficiency Step-Down DC/DC
Converter
VIN: 3.6V to 37V, Transient to 55V, VOUT(MIN) = 1.21V, IQ = 1.1mA,
ISD < 1µA, 3mm × 3mm DFN-10 Package
LT3682
36V, 60VMAX, 1A, 2.2MHz High Efficiency Micropower
Step-Down DC/DC Converter
VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 75µA, ISD < 1µA, 3mm × 3mm
DFN-12 Package
LT3971
38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC
Converter with Only 2.8µA of Quiescent Current
VIN: 4.2V to 38V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA, 3mm × 3mm
DFN-10, MSOP-10E Packages
LT3991
55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC
Converter with Only 2.8µA of Quiescent Current
VIN: 4.2V to 55V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA, 3mm × 3mm
DFN-10, MSOP-10E Packages
3640f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0510 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2010
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