L6386AD
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L6386AD
High-voltage high and low side driver
Features
■
High voltage rail up to 600 V
■
dV/dt immunity ±50 V/nsec in full temperature
range
■
Driver current capability:
– 400 mA source,
– 650 mA sink
Description
■
Switching times 50/30 nsec rise/fall with 1nF
load
■
CMOS/TTL Schmitt trigger inputs with
hysteresis and pull down
■
Under voltage lock out on lower and upper
driving section
■
Integrated bootstrap diode
■
Outputs in phase with inputs
Figure 1.
SO-14
The L6386AD is an high-voltage device,
manufactured with the BCD "OFF-LINE"
technology. It has a driver structure that enables
to drive independent referenced Channel Power
MOS or IGBT. The high-side (floating) section is
enabled to work with voltage rail up to 600 V. The
Logic Inputs are CMOS/TTL compatible for ease
of interfacing with controlling devices.
Block diagram
BOOTSTRAP DRIVER
Vboot
14
VCC
4
UV
DETECTION
UV
DETECTION
H.V.
HVG
DRIVER
R
R
HIN
SD
3
2
LEVEL
SHIFTER
HVG
13
S
OUT
VCC
LOGIC
12
TO LOAD
LVG
LVG
DRIVER
LIN
CBOOT
1
9
PGND
8
VREF
-
5
DIAG
+
SGND
7
6
CIN
D97IN520D
July 2008
Rev 1
1/17
www.st.com
17
Contents
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L6386AD
Contents
1
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
3.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
L6386AD
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Electrical data
1
Electrical data
1.1
Absolute maximum ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
Vout
Output voltage
-3 to Vboot - 18
V
Vcc
Supply voltage
- 0.3 to +18
V
-1 to 618
V
Vboot
Floating supply voltage
Vhvg
High-side gate output voltage
- 1 to Vboot
V
Vlvg
Low-side gate output voltage
-0.3 to Vcc +0.3
V
Logic input voltage
-0.3 to Vcc +0.3
V
Vdiag
Open drain forced voltage
-0.3 to Vcc +0.3
V
Vcin
Comparator input voltage
-0.3 to 10 V
V
dVout/dt
Allowed output slew rate
50
V/ns
Total power dissipation (TJ = 85 °C)
750
mW
Tj
Junction temperature
150
°C
Tstg
Storage temperature
-50 to 150
°C
Vi
Ptot
Note:
ESD immunity for pins 12, 13 and 14 is guaranteed up to 900V (Human Body Model)
1.2
Thermal data
Table 2.
Thermal data
Symbol
Rth(JA)
1.3
Parameter
Thermal Resistance Junction to ambient
SO-14
Unit
165
°C/W
Recommended operating conditions
Table 3.
Symbol
Recommended operating conditions
Pin
Parameter
Test condition
Min
Vout
12
Output voltage
(1)
VBS (2)
14
Floating supply voltage
(1)
Switching frequency
fsw
Vcc
TJ
4
HVG,LVG load CL = 1 nF
Supply voltage
Junction temperature
-45
Typ
Max
Unit
580
V
17
V
400
kHz
17
V
125
°C
1. If the condition Vboot - Vout < 18 V is guaranteed, Vout can range from -3 to 580 V
2. VBS = Vboot - Vout
3/17
Pin connection
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2
L6386AD
Pin connection
Figure 2.
Pin connection (Top view)
LIN
1
14
Vboot
SD
2
13
HVG
HIN
3
12
OUT
VCC
4
11
N.C.
DIAG
5
10
N.C.
CIN
6
9
LVG
SGND
7
8
PGND
D97IN521A
Table 4.
Pin description
N°
Pin
Type
1
LIN
I
Low-side driver logic input
2
SD(1)
I
Shut down logic input
3
HIN
I
High-side driver logic input
4
VCC
5
DIAG
O
Open drain diagnostic output
6
CIN
I
Comparator input
7
SGND
Ground
8
PGND
Power ground
9
LVG (1)
10, 11
N.C.
12
OUT
13
14
HVG
(1)
Vboot
Function
Low voltage supply
O
Low-side driver output
Not connected
O
High-side driver floating driver
O
High-side driver output
Bootstrapped supply voltage
1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10 mA), with VCC >3V. This allows to omit the
"bleeder" resistor connected between the gate and the source of the external MOSFET normally used to
hold the pin low; the gate driver assures low impedance also in SD condition.
4/17
L6386AD
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Electrical characteristics
3
Electrical characteristics
3.1
AC operation
Table 5.
Symbol
ton
toff
tsd
tr
AC operation electrical characteristcs (VCC = 15 V; TJ = 25 °C)
Pin
High/low-side driver turn-on
1,3 vs propagation delay
9,13 High/low-side driver turn-off
propagation delay
2 vs
9,13
Test condition
Min
Vout = 0 V
Shut down to high/low side
propagation delay
Typ
Max
Unit
110
150
ns
110
150
ns
105
150
Rise time
CL = 1000 pF
50
ns
Fall time
CL = 1000 pF
30
ns
9, 13
tf
3.2
Parameter
DC operation
Table 6.
Symbol
DC operation electrical characteristcs (VCC = 15 V; TJ = 25 °C)
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Low supply voltage section
Vccth1
Vcc UV turn on threshold
9.1
9.6
10.1
V
Vccth2
Vcc UV turn off threshold
7.9
8.3
8.8
V
Vcchys
4
Vcc UV hysteresis
1.3
V
µA
Iqccu
Undervoltage quiescent
supply current
Vcc ≤9 V
200
Iqcc
Quiescent current
Vcc = 15 V
250
320
µA
Bootstrapped supply section
Vbth1
Vboot UV turn on threshold
8.5
9.5
10.5
V
Vbth2
Vboot UV turn off threshold
7.2
8.2
9.2
V
Vbhys
Iqboot
Ilk
RDS(on)
14
Vboot UV hysteresis
1.3
V
Vboot quiescent current
HVG ON
200
µA
High voltage leakage current
Vhvg = Vout = Vboot
= 600 V
10
µA
Bootstrap driver on
resistance (1)
Vcc ≥ 12.5 V;
Vin = 0 V
125
Ω
5/17
Electrical characteristics
查询"L6386AD013TR"供应商
Table 6.
Symbol
L6386AD
DC operation electrical characteristcs (continued)(VCC = 15 V; TJ = 25 °C)
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Driving buffers section
Iso
9,
13
High/low side source short
circuit current
VIN = Vih (tp < 10 µs)
300
400
mA
Isi
9,
13
High/low side sink short
circuit current
VIN = Vil (tp < 10 µs)
500
650
mA
Logic inputs
Vil
Vih
Iih
Low level logic voltage
1.5
1,2, High level logic voltage
3 High level logic input current V = 15 V
IN
Iil
Low level logic input current
3.6
V
V
50
VIN = 0 V
70
µA
1
µA
10
mV
Sense comparator
Vio
Input offset voltage
-10
Iio
6
Input bias current
Vcin ≥ 0.5
Vol
2
Open drain low level output
voltage
Iod = -2.5 mA
Vref
Comparator reference
voltage
0.46
1. RDS(on) is tested in the following way:
( V CC – V CBOOT1 ) – ( V CC – V CBOOT2 )
R DSON = -----------------------------------------------------------------------------------------------------I 1 ( V CC ,V CBOOT1 ) – I 2 ( V CC ,V CBOOT2 )
where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
6/17
µA
0.2
0.50
0.8
V
0.54
V
L6386AD
查询"L6386AD013TR"供应商
3.3
Electrical characteristics
Timing diagram
Figure 3.
Input/output timing diagram
HIN
LIN
SD
HOUT
LOUT
VREF
VCIN
DIAG
D97IN522A
Note: SD active condition is latched until next negative IN edge.
7/17
Bootstrap driver
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4
L6386AD
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6386AD a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with in series a diode, as shown in
Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The
diode connected in series to the DMOS has been added to avoid undesirable turn on of it.
4.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Q gate
C EXT = -------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
CBOOT>>>CEXT
e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage losses.
e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is 5ms, CBOOT has
to supply 1 µC to CEXT. This charge on a 1 µF capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives great advantages: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value:
125 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Q gate
V drop = I ch arg e R dson →V drop = ------------------- R dson
T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor.
8/17
L6386AD
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Bootstrap driver
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 µs. In fact:
30nC
V drop = --------------- ⋅ 125Ω ∼0.8V
5µs
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 4.
Bootstrap driver
DBOOT
VS
VBOOT
VBOOT
VS
H.V.
H.V.
HVG
HVG
CBOOT
VOUT
TO LOAD
TO LOAD
LVG
a
CBOOT
VOUT
LVG
b
D99IN1056
9/17
Typical characteristic
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5
L6386AD
Typical characteristic
Figure 5.
Typical rise and fall times vs
load capacitance
time
(nsec)
D99IN1054
250
Figure 6.
Quiescent current vs supply
voltage
Iq
(µA)
104
D99IN1057
200
Tr
103
150
Tf
100
102
50
10
0
0
1
2
3
4
5 C (nF)
For both high and low side buffers @25˚C Tamb
Figure 7.
Turn on time vs temperature
Figure 8.
4
6
8
10
12
14
16 VS(V)
VBOOT UV turn on threshold
vs temperature
15
250
@ Vcc = 15V
14
@ Vcc = 15V
200
13
Vbth1 (V)
Ton (ns)
2
0
150
Typ.
100
12
Typ.
11
10
9
50
8
0
-45
Figure 9.
-25
0
25
50
Tj (°C)
75
100
7
125
-45
0
25
50
Tj (°C)
75
100
125
Turn Off time vs temperature Figure 10. VBOOT UV turn off threshold
vs temperature
15
250
@ Vcc = 15V
14
@ Vcc = 15V
Vbth2 (V)
200
Toff (ns)
-25
150
Typ.
100
13
12
11
10
Typ.
9
50
8
0
7
-45
10/17
-25
0
25
50
Tj (°C)
75
100
125
-45
-25
0
25
50
Tj (°C)
75
100
125
L6386AD
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Typical characteristic
Figure 11. Shutdown time vs
temperature
Figure 12. VBOOT UV hysteresis
3
250
@ Vcc = 15V
@ Vcc = 15V
2.5
Vbhys (V)
tsd (ns0
200
150
Typ.
100
Typ.
2
1.5
50
0
-45
-25
0
25
50
Tj (°C)
75
100
1
125
Figure 13. VCC UV turn on threshold vs
temperature
-45
-25
0
25
50
Tj (°C)
75
100
125
Figure 14. Output source current vs
temperature
15
1000
14
800
current (mA)
Vccth1(V)
@ Vcc = 15V
13
12
Typ.
600
Typ.
400
11
200
10
9
0
-45
-25
0
25
50
Tj (°C)
75
100
125
Figure 15. VCC UV turn off threshold vs
temperature
-45
-25
0
25
50
Tj (°C)
75
100
125
Figure 16. Output sink current vs
temperature
12
1000
11
800
current (mA)
Vccth2(V)
@ Vcc = 15V
10
Typ.
9
8
7
-45
Typ.
600
400
200
-25
0
25
50
Tj (°C)
75
100
125
0
-45
-25
0
25
50
Tj (°C)
75
100
125
11/17
Typical characteristic
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L6386AD
Figure 17. VCC UV hysteresis vs
temperature
3
Vcchys (V)
2.5
Typ.
2
1.5
1
-45
12/17
-25
0
25
50
Tj (°C)
75
100 125
L6386AD
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6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
13/17
Package mechanical data
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L6386AD
Figure 18. SO-14 mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.35
1.75
0.053
0.069
A1
0.10
0.30
0.004
0.012
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.01
D (1)
8.55
8.75
0.337
0.344
E
3.80
4.0
0.150
0.157
e
1.27
0.050
H
5.8
6.20
0.228
0.244
h
0.25
0.50
0.01
0.02
L
0.40
1.27
0.016
0.050
k
ddd
OUTLINE AND
MECHANICAL DATA
0° (min.), 8° (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO-14
0016019 D
14/17
L6386AD
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7
Order codes
Order codes
Table 7.
Order codes
Order codes
Package
Packaging
L6386AD
SO-14
Tube
L6386AD013TR
SO-14
Tape and reel
15/17
Revision history
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8
Revision history
Table 8.
16/17
L6386AD
Document revision history
Date
Revision
14-Jul-2008
1
Changes
First release
L6386AD
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