Triple Synchronous Buck Controller with NMOS LDO

Triple Synchronous Buck Controller with NMOS LDO
TPS5130-Q1
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TRIPLE SYNCHRONOUS BUCK CONTROLLER WITH NMOS LDO CONTROLLER
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Three Independent Step-Down DC/DC
Controllers and One LDO Controller
Input Voltage Range
– Switcher: 4.5 V to 28 V
– LDO: 1.1 V to 3.6 V
Output Voltage Range
– Switcher: 0.9 V to 8.5 V
– LDO: 0.9 V to 2.5 V
Synchronous for High Efficiency
Precision Vref (±1.5%)
PWM Mode Control : 500-kHz Operation (Max)
Auto PWM/SKIP Mode Available
•
•
•
•
High-Speed Error Amplifier
Overcurrent Protection With Temperature
Compensation Circuit for Each Channel
Overvoltage and Undervoltage Protection
Programmable Short-Circuit Protection
Power Good Output (PGOUT) With
Programmable Delay Time
5-V and 3.3-V Linear Regulators
APPLICATIONS
•
•
•
Notebook PCs, PDAs
Consumer Game Systems
DSP Applications
DESCRIPTION
The TPS5130 is composed of three independent synchronous buck regulator controllers (SBRC) and one low
dropout (LDO) regulator controller. On-chip high-side and low-side synchronous rectifier drivers are integrated to
drive less expensive N-channel MOSFETs. The LDO controller can also drive an external N-channel MOSFET.
Because the input current ripple is minimized by operating 180° out of phase, it allows a smaller input
capacitance, resulting in reduced power supply cost. The SBRC of the TPS5130 automatically adjusts from PWM
mode to SKIP mode to maintain high efficiency under light-load conditions. Resistorless current protection for the
synchronous buck controller and the fixed high-side driver voltage simplifies the system design and reduces the
external parts count. The LDO controller has a current-limit protection and overshoot protection to suppress
output voltage spikes at load transient. To further extend battery life, the TPS5130 features dead-time control
and very low quiescent current.
NIV
NIV
u_1TUO
3oV
V 5.8
)B etoN ees(
1LL
d_1TUO
u_3TUO
3LL
1oV
V 5.8
)B etoN ees(
d_3TUO
0315SPT
1VNI
3VNI
NI_V5GER
NI_ODL
u_2TUO
RUC_ODL
2LL
ETAG_ODL
d_2TUO
ODL_oV
2oV
V 5.8
)B etoN ees(
ODL_VNI
DNG
2VNI
A.
See the Application Information section for more details.
B.
To determine input voltage, see Duty Control in Electrical Characteristics.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS5130-Q1
SLVS866 – MARCH 2009................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGE (2)
TJ
–40°C to 125°C
(1)
LQFP – PT
ORDERABLE PART NUMBER
Reel of 1000
TPS5130QPTRQ1
TOP-SIDE MARKING
5130Q
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2)
ABSOLUTE MAXIMUM RATINGS (1) (2)
over junction temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range
VO
Output voltage range
TJ
Junction temperature range
Tstg
Storage temperature range
VIN
–0.3 V to 30 V
LH1, LH2, LH3
–0.3 V to 35 V
VIN_SENSE12, VIN_SENSE3, LL1, LL2, LL3, STBY_LDO,
STBY_VREF3.3, STBY_VREF5, TRIP1, TRIP2, TRIP3
–0.3 V to 30 V
INV1, INV2, INV3, CT, SS_STBY1, SS_STBY2, SS_STBY3,
INV_LDO, LDO_OUT, FLT, PG_DELAY, VREF3.3, VREF5,
LDO_IN, LDO_CUR, PWM_SEL, REG5V_IN
–0.3 V to 7 V
OUT1_u, OUT2_u, OUT3_u
–0.3 V to 35 V
FB1, FB2, FB3, PGOUT, OUT1_d, OUT2_d, OUT3_d
–0.3 V to 7 V
LDO_GATE
–0.3 V to 9 V
REF
–0.3 V to 3 V
–40°C to 125°C
–55°C to 150°C
Human-Body Model (HBM)
ESD
2000 V
Electrostatic discharge rating Machine Model (MM)
200 V
Charged-Device Model (CDM)
(1)
(2)
500 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE
48-pin PT
2
LOW K/
HIGH K
DERATING
FACTOR ABOVE
TA = 25°C
POWER RATING
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
High
14.60 mW/°C
1459.85 mW
802.92 mW
583.94 mW
Low
9.28 mW/°C
927.64 mW
510.20 mW
371.06 mW
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11.8°C/W
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RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage
4.5
28
LDO_IN
1.1
3.6
REG5V_IN
4.5
5.5
–0.1
33
4.5
28
STBY_LDO, LL1, LL2, LL3, TRIP, STBY_VREF3.3, STBY_VREF5
–0.1
28
LDO_GATE
–0.1
8
INV1, INV2, INV3, INV_LDO, CT, PWM_SEL, FLT, PG_DELAY,
SS_STBY1, SS_STBY2, SS_STBY3
–0.1
6
PGOUT, FB1, FB2, FB3, OUT1_d, OUT2_d, OUT3_d
–0.1
5.5
LDO_CUR, LDO_OUT
–0.1
VIN_SENSE12, VIN_SENSE3
Input voltage
fOSC
Oscillator frequency
TJ
Junction temperature
MAX
VIN
OUT1_u, OUT2_u, OUT3_u, LH1, LH2, LH3
VI
NOM
UNIT
V
V
3.5
300
500
kHz
125
°C
TYP
MAX
UNIT
2
3
mA
–40
ELECTRICAL CHARACTERISTICS
over junction temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Supply Current
ICC
Supply current
TA = 25°C, V(LDO_IN) = 3.6 V,
V(CT) = V(INVx) = V(INV_LDO) = 0 V, V(PWM_SEL) = 0 V
ICC(STBY)
Standby current
V(SS_STBYx) = 0 V, V(STBY_LDO) = 0 V,
V(STBY_VREF3.3/5) = 5 V
150
250
µA
ICC(S)
Shutdown current
V(SS_STBYx) = 0 V, V(STBY_LDO) = 0 V,
V(STBY_VREF3.3/5) = 0 V
0.001
10
µA
Reference Voltage
Vref
Reference voltage
0.85
TA = 25°C
Vref(tol)
V
–1.5
1.5
–2
2
Reference voltage tolerance
Iref = 50 µA
Line regulation
V(VIN) = 4.5 V to 28 V, Iref = 50 µA
0.05
5
mV
Load regulation
Iref = 0.1 µA to 1 mA
0.15
5
mV
TJ = 0°C to 125°C
TJ = -40°C to 125°C
–2.5
%
2.5
5-V Internal Switch
VT(LH)
Threshold voltage, high
REG5V_IN voltage
4.2
4.8
VT(HL)
Threshold voltage, low
REG5V_IN voltage
4.1
4.7
V
V
Vhys
Hysteresis
REG5V_IN voltage
30
200
mV
Output voltage
IO = 0 mA to 50 mA, V(VIN) = 5.5 V to 28 V, TA = 25°C
4.8
5.2
V
Line regulation
V(VIN) = 5.5 V to 28 V, IO = 10 mA
20
mV
40
mV
5-V Regulator
VO
Load regulation
IO = 1 mA to 10 mA, V(VIN) = 5.5 V
IOS
Short-circuit output current
V(VREF5) = 0 V, TA = 25°C
65
VT(LH)
UVLO threshold voltage, high
VREF5 voltage
3.6
VT(HL)
UVLO threshold voltage, low
VREF5 voltage
3.5
4.1
V
Vhys
Hysteresis
VREF5 voltage
30
200
mV
3.45
V
mA
4.2
V
3.3-V Regulator
VO
IOS
Output voltage
IO = 0 mA to 30 mA, V(VIN) = 5.5 V to 28 V, TA = 25°C
3.15
3.30
Line regulation
V(VIN) = 5.5 V to 28 V, IO = 10 mA
20
mV
Load regulation
IO = 1 mA to 10 mA, V(VIN) = 5.5 V
40
mV
Short-circuit output current
V(VREF3.3) = 0 V, TA = 25°C
–30
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ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Control
VIH
High-level input voltage
SS_STBY1, SS_STBY2, SS_STBY3, STBY_LDO,
PWM_SEL, STBY_VREF3.3, STBY_VREF5
VIL
Low-level input voltage
SS_STBY1, SS_STBY2, SS_STBY3, STBY_LDO,
PWM_SEL, STBY_VREF3.3, STBY_VREF5
2.2
V
0.3
V
Output Voltage Monitor
OVP comparator threshold
SBRC, LDO
0.91
0.95
0.99
V
UVP comparator threshold
SBRC, LDO
0.51
0.55
0.59
V
PG comparator low-level
threshold
0.75
0.79
0.81
V
PG comparator high-level
threshold
0.88
0.91
0.94
V
PG propagation delay from INVx,
INV_LDO to PGOUT
No load at PG_DELAY
PGOUT H to L
6.5
PGOUT L to H
16
I(PG_DELAY) PG_DELAY source current
Timer latch current source
µs
µA
–1.8
UVP protection
–1.5
–2.3
–3.1
OVP protection
–80
–125
–180
µA
Oscillator
fOSC
Oscillation frequency
VOH
High-level output voltage
VOL
Low-level output voltage
PWM mode, C(CT) = 44 pF, TA = 25°C
dc
300
1
fOSC = 300 kHz
1.1
kHz
1.2
1.17
dc
0.4
fOSC = 300 kHz
0.5
0.6
0.43
V
V
Error Amplifier for SBRC
VIO
Input offset voltage
INVx voltage, TA = 25°C
2
Open-loop voltage gain
10
50
Unity-gain bandwidth
mV
dB
2.5
MHz
IO(snk)
Output sink current
V(FBx) = 1 V
0.2
0.7
mA
IO(src)
Output source current
V(FBx) = 1 V
–0.2
–0.9
mA
Duty Control
Maximum duty control
fOSC = 300 kHz, V(INVx) = 0 V
CH1, CH3
82
CH2
97
%
Output Drivers
I(TRIPx)
OUTx_u sink current
V(OUTx_u) – V(LLx) = 3 V
1.2
A
OUTx_u source current
V(LHx) – V(OUTx_u) = 3 V
–1.2
A
OUTx_d sink current
V(OUTx_d) = 3 V
1.5
A
OUTx_d source current
V(OUTx_d) = 2 V
–1.5
LDO_GATE sink current
V(LDO_GATE) = 2 V
2
mA
LDO_GATE source current
V(LDO_GATE) = 2 V
–1.4
mA
Output current
TRIP1, TRIP2, TRIP3
Soft-start current
V(SS_STBYx) = 0.7 V
A
11
13
15
µA
–1.6
–2.3
–2.9
µA
2
10
mV
Soft Start
I(SS_STBYx)
Error Amplifier for LDO Controller
VIO
4
Input offset voltage
V(LDO_IN) = 3.3 V, TA = 25°C
Open-loop voltage gain
V(LDO_IN) = 3.3 V
Unity-gain bandwidth
V(LDO_IN) = 3.3 V, CL = 2000 pF
50
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dB
1.4
MHz
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ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
40
50
60
UNIT
Current Limit for LDO Controller
Current limit comparator
threshold voltage
V(LDO_IN) = 3.3 V
mV
Overshoot Protection for LDO Controller
LDO_OUT sink current
V(LDO_OUT) = V(LDO_GATE) = 1.5 V
25
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PIN ASSIGNMENTS
2VNI
d_2TUO
2DNGTUO
1PIRT
2PIRT
u_52
3TUO
43 2HL
4
33 NIV
2YBTS_SS
5
3.32F
3 ERV
LES_MWP
6
51F
3 ERV
7
NI_V053GER
DNG
8
N9I2_ODL
FER
9
RUC
_ODL
82
01
ETAG
_ODL
72
11
TUO
_ODL
62
21
OD5L2_VNI
TC
3DNGTUO
d_3TUO
3ESNES_NIV
u_3TUO
3HL
3LL
71 61 5311 41
3PIRT
91 81
3BF
32 22 12 02
YALED_GP
ODL_YBTS
TUOGP
3.3FERV_YBTS
3VNI
5FERV_YBTS
6
63 2LL
3
2BF
42
1LL
2
21ESNES_NIV
1YBTS_SS
1DNGTUO
1
d_1TUO
1BF
74 84
u_1TUO
44 54 64
1HL
24 34
TLF
83 93 04 14
3YBTS_SS
73
1VNI
PT PACKAGE
(TOP VIEW)
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TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CT
7
I/O
External capacitor from CT to GND adjusts frequency of the triangle oscillator.
FB1
1
O
Feedback output of SBRC-CH1 error amplifier
FB2
4
O
Feedback output of SBRC-CH2 error amplifier
FB3
14
O
Feedback output of SBRC-CH3 error amplifier
FLT
47
I/O
Fault latch timer pin. An external capacitor connected between FLT and GND sets FLT enable time
up.
GND
8
INV1
48
I
Inverting input of SBRC-CH1 error amplifier, skip comparator, OVP1/UVP1 comparator, and PG
comparator
INV2
3
I
Inverting input of SBRC-CH2 error amplifier, skip comparator, OVP2/UVP2 comparator, and PG
comparator
INV3
15
I
Inverting input of SBRC-CH3 error amplifier, skip comparator, OVP3/UVP3 comparator, and PG
comparator
INV_LDO
25
I
Inverting input of LDO error amplifier, OVP/UVP comparators, and PG comparator
LDO_CUR
28
I
Current sense input of LDO regulator
LDO_GATE
27
O
Gate control output of external MOSFET for LDO regulator
LDO_OUT
26
I/O
LDO regulator output. If output voltage has an overshoot when output current changes high to low
quickly, it absorbs electrical charge from this pin.
LDO_IN
29
I
LH1
46
I/O
Bootstrap capacitor connection for SBRC-CH1 high-side gate driver
LH2
34
I/O
Bootstrap capacitor connection for SBRC-CH2 high-side gate driver
LH3
20
I/O
Bootstrap capacitor connection for SBRC-CH3 high-side gate driver
LL1
44
I/O
SBRC-CH1 high-side gate driving return. Connect this pin to the junction of the high-side and
low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current
comparator.
LL2
36
I/O
SBRC-CH2 high-side gate driving return. Connect this pin to the junction of the high-side and
low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current
comparator.
LL3
22
I/O
SBRC-CH3 high-side gate driving return. Connect this pin to the junction of the high-side and
low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current
comparator.
OUT1_d
43
O
Gate drive output for SBRC-CH1 low-side MOSFETs
OUT2_d
37
O
Gate drive output for SBRC-CH2 low-side MOSFETs
OUT3_d
23
O
Gate drive output for SBRC-CH3 low-side MOSFETs
OUT1_u
45
O
Gate drive output for SBRC-CH1 high-side MOSFETs
OUT2_u
35
O
Gate drive output for SBRC-CH2 high-side MOSFETs
OUT3_u
21
O
Gate drive output for SBRC-CH3 high-side MOSFETs
OUTGND1
42
O
Ground for SBRC-CH1 MOSFETs drivers. It is connected to the current limiting comparator's
negative input.
OUTGND2
38
O
Ground for SBRC-CH2 MOSFETs drivers. It is connected to the current limiting comparator's
negative input.
OUTGND3
24
O
Ground for SBRC-CH3 MOSFETs drivers. It is connected to the current limiting comparator's
negative input.
PGOUT
16
O
Power good open-drain output. PG comparators monitor all SBRCs and LDOs overvoltage and
undervoltage status. The threshold is ±7%. When one of the outputs is beyond this condition,
PGOUT goes low.
PG_DELAY
17
I/O
Programmable delay for PGOUT. Connect an external capacitor between this pin and GND to
specify time delay.
PWM_SEL
6
I
Signal GND
Supply voltage input and current sense input of LDO regulator
PWM or auto PWM/SKIP mode select
H= Auto PWM/SKIP
L = PWM fixed
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
REF
9
O
0.85-V reference voltage output. This 0.85-V reference voltage is used to set the output voltage and
the reference for the over and undervoltage protections. This reference voltage is dropped down
from the internal 5-V regulator.
REG5V_IN
30
I
External 5-V input
SS_STBY1
2
I/O
Soft start control and stand by control for SBRC-CH1. Connect an external capacitor between this
pin and GND to specify soft start time.
SS_STBY2
5
I/O
Soft start control and stand by control for SBRC-CH2. Connect an external capacitor between this
pin and GND to specify soft start time.
SS_STBY3
13
I/O
Soft start control and stand by control for SBRC-CH3. Connect an external capacitor between this
pin and GND to specify soft start time.
STBY_LDO
12
I
Standby control input for LDO regulator. LDO regulator can be switched into standby mode by
grounding the STBY_LDO pin.
STBY_VREF3.3
11
I
Standby control for 3.3-V linear regulator
STBY_VREF5
10
I
Standby control for 5-V linear regulator
TRIP1
41
I
External resistor connection for SBRC-CH1 output current protection control
TRIP2
39
I
External resistor connection for SBRC-CH2 output current protection control
TRIP3
18
I
External resistor connection for SBRC-CH3 output current protection control
VIN
33
I
Supply voltage input
VIN_SENSE12
40
I
SBRC-CH1/2 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V.
VIN_SENSE3
19
I
SBRC-CH 3 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V.
VREF3.3
32
O
3.3-V linear regulator output
VREF5
31
O
5-V linear regulator output
8
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FUNCTIONAL BLOCK DIAGRAM
PWM_SEL
SBRC-CH1
SOFTSTART
/STBY
SS_STBY1
Duplicate for CH2 and CH3.
SKIP Comp.
0.85 V
+
FB1
LH1
ERROR Amp.
INV1
-
Oscillator
CT
OUT1_u
PWM Comp.
+
+
+
-
LL1
0.85 V
OUT1_d
OUTGND1
Phase
Inverter
Current Comp. 1
OVP Comp.
-
+
+
Current
Protection
Trigger
0.85 V + 12 %
UVP Comp.
+
SS_STBY
-(VIN_SENSE-TRIP)
-
-
VIN_SENSE12
+
TRIP1
Current Comp. 2
0.85 V - 35 %
LH2
SS_STBY2
SBRC-CH2
FB2
OUT2_u
LL2
OUT2_d
INV2
OUTGND2
TRIP2
SS_STBY3
FB 3
INV3
LH3
SBRC-CH3
+
OUT3_u
+
LL3
+
OUT3_d
+
OUTGND3
-
VIN_SENSE3
TRIP3
-
TIMER
-
0.85 V + 7 %
+
0.85 V - 7 %
Fault
Latch
Timer
PG_DELAY
PGOUT
FLT
STBY_LDO
INV_LDO
UVLO
VIN
SS_STBY
STBY_LDO
STBY_LDO
STBY_VREF5
VREF3.3
VIN_SENSE
ERROR Amp.
STBY_VREF3.3
-
3.3 V
REG.
5V
REG.
VREF5
VREF
0.85 V
0.85 V
+
0.85 V + 12 %
Current Limit
+
REG5V_IN
GND
LDO_GATE
+
OVP Comp.
-
-
-
LDO_IN
LDO_CUR
UVP Comp.
+
LDO Overshoot
Protection
0.85 V - 35 %
4.5 V
LDO_OUT
LDO
REF
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DETAILED DESCRIPTION
PWM Operation
The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck
converter. The output voltage of the SBRC is fed back to the inverting input [INVx (x=1,2,3)] of the error amplifier.
The noninverting input is internally connected to a 0.85-V precise band gap reference circuit. The unity gain
bandwidth of the amplifier is 2.5 MHz. This decreases the amplifier delay during fast load transients and
contributes to a fast response. Loop gain and phase compensation is programmable by an external C, R network
between the FBx and INVx pins. The output signal of the error amplifier is compared with a triangular wave to
achieve the PWM control signal. The oscillation frequency of this triangular wave sets the switching frequency of
the SBRC and is determined by the capacitor connected between the CT and GND pins. The PWM mode is
used for the entire load range if the PWM_SEL pin is set LOW, or used in high output current condition if auto
PWM/SKIP mode is selected by setting the same pin to HIGH.
Skip Mode Operation
The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3-V,
the SBRC operates in the fixed PWM mode. If 2.5 V (minimum) or higher is applied, it operates in auto
PWM/SKIP mode. In the auto PWM/SKIP mode, the operation changes from constant frequency PWM mode to
an energy-saving SKIP mode automatically in accordance with load conditions. Using a MOSFET with ultra-low
rDS(on) when the auto SKIP function is implemented is not recommended. The SBRC block has a hysteretic
comparator to regulate the output voltage of the synchronous buck converter during SKIP mode. The delay from
the comparator input to the driver output is typically 1.2 µs. In the SKIP mode, the frequency varies with load
current and input voltage.
High-Side Driver
The high-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The current rating of
the driver is 1.2 A at source and sink. When configured as a floating driver, a 5-V bias voltage is delivered from
VREF5 pin. The instantaneous drive current is supplied by the flying capacitor between the LHx and LLx pins
since a 5-V power supply does not usually have low impedance. It is recommended to add a 5-Ω to 10-Ω resistor
between the gate of the high-side MOSFET(s) and the OUTx_u pin to suppress noise. The maximum voltage
that can be applied between the LHx and OUTGNDx pins is 33 V.
When selecting the high-current rating MOSFET(s), it is important to pay attention to both gate drive power
dissipation and the rise/fall time against the dead-time between high-side and low-side drivers. The gate drive
power is dissipated from the controller IC and it is proportional to the gate charge at VGS = 5 V, PWM switching
frequency, and the numbers of all MOSFETs used for low-side and high-side switches. This gate drive loss
should not exceed the maximum power dissipation of the device.
Low-Side Driver
The low-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The maximum
drive voltage is 5 V from the internal regulator or REG5V_IN pin. The current rating of the driver is typically 1.5 A
at source and sink. Gate resistance is not necessary for the low-side MOSFET for switching noise suppression
since it turns on after the parallel diode is turned on (ZVS). It needs the same dissipation consideration when
using high current rating MOSFET(s). Another issue that needs precaution is the gate threshold voltage. Even
though the OUTx_d pin is shorted to the OUTGNDx pin with low resistance when the low-side MOSFET(s) is
OFF, high dv/dt of the LLx pin during turnon of the high-side arm generates a voltage peak at the OUTx_d pin
through the drain to gate capacitance, Cdg, of the low-side MOSFET(s). To prevent a short period shoot-through
during this switching event, the application designer should select MOSFET(s) with adequate threshold voltage.
Dead Time
The internally defined dead-time prevents shoot-through-current flowing through the main power MOSFETs
during switching transitions. Typical value of the dead-time is 100 ns.
10
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Standby
The SBRC controller, the LDO controller, and the internal regulators can be switched into standby mode
separately as shown in Table 1. The standby mode current, when both controllers and regulators are off, can be
as low as 1 nA.
Table 1. Standby Logic
INPUT
FUNCTION
STBY_VREF5
SS_STBYx
STBY_VREF3.3
STBY_LDO
V(REG5V_IN) > 4.5 V (1)
VREF5
VREF3.3
SBRCx
LDO
L
L
L
L
False
OFF
OFF
OFF
OFF
(2)
(2)
(2)
(2)
L
(1)
(2)
L
L
L
True
(2)
ON
(2)
OFF
(2)
OFF
(2)
OFF (2)
H
L
L
L
X
ON
OFF
OFF
OFF
L
H
L
L
X
OFF
OFF
OFF
OFF
H
H
L
L
X
ON
OFF
ON
OFF
L
L
H
L
X
ON
ON
OFF
OFF
H
L
H
L
X
ON
ON
OFF
OFF
L
H
H
L
X
ON
ON
OFF
OFF
H
H
H
L
X
ON
ON
ON
OFF
L
L
L
H
X
ON
OFF
OFF
ON
H
L
L
H
X
ON
OFF
OFF
ON
L
H
L
H
X
ON
OFF
OFF
ON
H
H
L
H
X
ON
OFF
ON
ON
L
L
H
H
X
ON
ON
OFF
ON
H
L
H
H
X
ON
ON
OFF
ON
L
H
H
H
X
ON
ON
OFF
ON
H
H
H
H
X
ON
ON
ON
ON
x = True or False
This functional mode is not recommended.
Soft Start
Soft start ramp up of the SBRC is controlled by the SS_STBYx pin voltage, which is controlled by an internal
current source and an external capacitor connected between the SS_STBYx and GND pins. When the
STBY_VREF5 and/or SS_STBYx pin voltages are forced to LOW, the SBRCx is disabled. When the
STBY_VREF5 pin voltage is set to HIGH and the SS_STBYx pin floats, the internal current source starts to
charge the external capacitor. The output voltage ramps up as the SS_STBYx pin voltage increases from 0 V to
0.85 V. The soft start time is easily calculated from the supply current and the capacitance value (see application
information). The soft start timing circuit for the LDO is integrated into the device. The soft start time is fixed and
can be as short as 600 ms. This is observed when the LDO is turned on separately from the SBRC.
Simultaneous start-up of one of the SBRC and the LDO, is also possible. Tie the LDO input to the SBRCx
output, let both the STBY_VREF5 and STBY_LDO voltages rise to the HIGH level, and invoke soft start on the
SS_STBYx pin; the LDO output follows the ramp of the SBRCx output.
Overcurrent Protection (OCP)
Overcurrent protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and low-side
MOSFET to a set-point voltage, which is defined by both the internal current source, I(TRIP), and the external
resistor connected between the VIN_SENSEx and the TRIPx pins. I(TRIP) has a typical value of 13 µA at 25°C.
When the drain-to-source voltage exceeds the set-point voltage during low-side conduction, the high-side current
comparator becomes active, and the low-side pulse is extended until this voltage comes back below the
threshold. If the set-point voltage is exceeded during high-side conduction in the following cycle, the current limit
circuit terminates the high-side driver pulse. Together this action has the effect of decreasing the output voltage
until the under voltage protection circuit is activated to latch both the high-side and low-side drivers OFF. In the
TPS5130, trip current I(TRIP) has a temperature coefficient of 3400 ppm/°C to compensate for temperature drift of
the MOSFET on-resistance.
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OCP for the LDO
To achieve the LDO current limit, a sense resistor must be placed in series with the N-channel MOSFET drain,
connected between the LDO_IN and LDO_CUR pins (see reference schematic). If the voltage drop across this
sense resistor exceeds 50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus it
activates the UVP to start the FLT latch timer. When the time is up, the LDO_GATE pin is pulled LOW to makes
the LDO regulator shut down. Note that all of the SBRCs are latched OFF at the same time since the LDO and
the SBRCs share the same FLT capacitor.
Overvoltage Protection (OVP)
For OVP, the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or INV_LDO pin voltage is
higher than 0.95 V (0.85 V + 12%), the OVP comparator output goes low and the FLT timer starts to charge an
external capacitor connected to FLT pin. After a set time, the FLT circuit latches the high-side MOSFET driver,
the low-side MOSFET drivers, and the LDO. The latched state of each block is summarized in Table 2. The timer
source current for the OVP latch is 125 mA(typ.), and the time-up voltage is 1.185 V (typ.). The OVP timer is
designed to be 50 times faster than the under voltage protection timer described in Table 2.
Table 2. OVP Logic
OVP OCCURRED AT
HIGH-SIDE MOSFET DRIVER
LOW-SIDE MOSFET DRIVER
LDO
SBRC
Off
On
Off
LDO
Off
Off
Off
Undervoltage Protection (UVP)
For UVP, the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or INV_LDO pin voltage is
lower than 0.55 V (0.85 V – 35%), the UVP comparator output goes low, and the FLT timer starts to charge the
external capacitor connected to FLT pin. Also, when the current comparator triggers the OCP, the UVP
comparator detects the under voltage output and starts the FLT capacitor charge, too. After a set time, the FLT
circuit latches all of the MOSFET drivers to the OFF state. The timer latch source current for UVP is 2.3 µA (typ),
and the time-up voltage is also 1.185 V (typ). The UVP function of the LDO controller is disabled when voltage
across the pass transistor is less than 0.23 V (typ).
Fault Latch Timer (FLT)
When an OVP or UVP comparator output goes low, the FLT circuit starts to charge the FLT capacitor. If the FLT
pin voltage goes beyond a constant level, the TPS5130 latches the MOSFET drivers. At this time, the state of
MOSFET is different depending on the OVP alert and the UVP alert (see Table 2). The enable time used to latch
the MOSFET drivers is decided by the value of the FLT capacitor. The charging constant current value depends
on whether it is an OVP alert or a UVP alert as shown in the following equation:
FLT source current (OVP) = FLT source current (UVP) × 50
Undervoltage Lockout (UVLO)
When the output voltage of the internal 5-V regulator or the REG5V_IN voltage decreases below about 4 V, the
output stages of all the SBRCs and the LDO are turned off. This state is not latched, and the operation recovers
immediately after the input voltage becomes higher than the turnon value again. The typical hysteresis voltage is
100 mV.
UVLO for LDO
The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO
circuit disables the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC overcurrent
protection is activated prior to that of the LDO's, this protection function may also be observed.
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LDO Control
The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an
ultralow dropout voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high current
power supply for core and I/O of modern digital processors, one from the SBRC and the other from the LDO. The
LDO_IN voltage range is from 1.1 V to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by an
external resistor divider. Gain and phase of the high-speed error amplifier for this LDO control is internally
compensated and is connected to the 0.85-V band gap reference circuit. The gate driver buffer is supplied by
VIN_SENSE voltage. In the relatively high output voltage applications, make sure that output voltage plus
threshold voltage of the pass transistor is less than the minimum VIN. More precisely,
VIN – 0.7 ≥ Vthn + V(LDO_OUT)
where Vthn is the threshold voltage of the Nch MOSFET.
The LDO controller is also equipped with OVP, UVP, overcurrent limit, and overshoot protection functions.
Overshoot Protection
If the load current changes from high to low very quickly, the LDO regulator output voltage may start to
overshoot. To resist this phenomenon, the LDO controller has an overshoot protection function. If the LDO
regulator output overshoots, the controller draws electrical charge out from the LDO_OUT pin to hold it stable.
Power Good
A single power good circuit monitors the SBRCx output voltages and the LDO output voltage. The PGOUT pin is
an open-drain output. When the INV or INV_LDO voltage goes beyond ±7% of 0.85 V, the PGOUT pin is pulled
down to the low level. PGOUT propagation delay is programmable by controlling rising time using an external
capacitor connected to the PG_DELAY pin. During the soft-start period, PGOUT indicates low, in other words,
power bad.
Table 3. PGOUT Logic
SS_STBY1
SS_STBY2
SS_STBY3
STBY_LDO
L
L
L
L
PGOUT
L
H
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
L
H
L
H
H
L
H
L
H
L
H
H
L
H
H
H
H
L
H
H or L
H or L
H or L
H
H
5-V Regulator
An internal linear voltage regulator is used for the high-side driver bootstrap. Since the input voltage ranges from
4.5 V to 28 V, this feature offers a fixed bootstrap voltage to simplify the drive design. It is active if the
STBY_VREF5 is HIGH and has a tolerance of 4%. The 5-V regulator is used for powering the low-side driver and
the VREF. When this regulator is disconnected from the MOSFET drivers, it is used only for the source of VREF.
3.3-V Regulator
The TPS5130 has a 3.3-V linear regulator. The output is made from the internal 5-V regulator or an external 5 V
from the REG5V_IN pin. The maximum output current of this regulator is limited to 30 mA by an output current
limit control. A ceramic capacitor of 4.7 µF should be connected between the VREF3.3 and GND pins to stabilize
the output voltage.
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External 5-V Input and 5-V Switch
If the internal 5-V switch detects 5-V input from the REG5V_IN pin, the internal 5-V regulator is disconnected
from the MOSFET drivers. The external 5 V is used for both the high-side bootstrap and the low-side driver, thus
increasing the efficiency. When an excess voltage is applied to the REG5V_IN pin, the OVP timer starts to
charge the FLT capacitor and latches all the MOSFET drivers and the LDO at OFF state after a set time.
Phase Inverter
The SBRC3 of the TPS5130 operates in the same phase as the internal triangular oscillator output while the
SBRC1 and the SBRC2 operate 180° out of phase. When the SBRC1 and the SBRC3 (or the SBRC2 and the
SBRC3) share the same input power supply, the TPS5130 realizes 180° out of phase operation that reduces
input current ripple and enables the input capacitor value smaller.
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TYPICAL CHARACTERISTICS
YLPPU
TS
NERRUC
sv
AREPMET NOITCNUJ
)NWODTU
YL
HPSP( U
TS
NERRUC
sv
ERUT
AREPMET NOITCNUJ
3
ERUT
052
VL(
)NI_OD
)RUV
C_=
ODL(
VP(
)LSE_MW
V 6.3 =
V =)TLF( V = )TCV( 0 =
VL(
)NI_OD
,
)RUV
C_=
ODL(
VL=
)XV
NI)(OD
_VNI(
VS(
0)0x2YBTS_S
VS(
FERV_YBT
VP(
)LES_MW
5.2
V 6.3 =
V0=
,
V0=
)5/3.V
3 0=
V0=
051
2
IuS −
Am − tnerruC ylpCpC
001
5.1
05
0
1
05−
051
AREPMET NOITCNUJ
05
0
°C
T noiT
tcJn−−uJ
erutarepme
ECRLUFOTSNERRUC
001
Figure 1.
)PVO(T
sv
ERUT
µ AAn − )nwodtuhS( tnerruC ylppIuS −
CC
001
05
0
05−
ECRLUFOTSNERRUC
AREPMET NOITCNUJ
µA
061−
041−
°C
T noiT
tcJn−−uJ
erutarepme
Figure 2.
)PVU(T
sv
ERUT
3−
5.2−
2−
− )PVU(T
− )PVO(T
021−
001−
5.1−
08−
06−
1−
02−
001
05
0
VL(
)NI_OD
)ODL_VV
N I(
)RUV
C_=
ODL(
V 3.3 =
5.0−
,
V1=
0
05−
051
001
05
0
°C
T noiT
tcJn−−uJ
erutarepme
Figure 3.
TN
PIERRTRUC
LF − tnerruC ecruoS
I −
S
LF − tnerruC ecruoS
I −
S
04−
VL(
)NI_OD
)RUV
C_=
ODL(
)ODL_VV
N I(
T noiT
tcJn−−uJ
erutarepme
ERUT
)ET
sv
EGAT
LOV TUPTUO
3
52
)ODL_VV
N I(
V 1.0 −
VL(
)NI_OD
V2=
VC=_ODL(
)RU
V 3.3 =
5.2
02
2
Am − )ET
µA
°C
Figure 4.
AG_ODL( TKNNEIR
SRUC
AREPMET NOITCNUJ
,
0
05−
sv
)p)V
iErTS(NEVS=
_NIV(
V 3.3 =
V5=
51
5.1
001
05
0
1
5
5.0
0
05−
8
T noiT
tcJn−−uJ
erutarepme
Figure 5.
°C
6
4
AG_ODL( tnerruC kniS
− tnerruC p
Tir
01
2
0
01
0
V tuptV
uO
O − V − egatlo
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
THRESHOLD VOLTAGE (OVP)
vs
JUNCTION TEMPERATURE
SOURCE CURRENT (LDO_GATE)
vs
OUTPUT VOLTAGE
955
V(INV_LDO) = 0 V
V(LDO_IN) = V(LDO_CUR) = 3.3 V
Threshold Voltage (OVP) − mV
Source Current (LDO_GATE) − mA
−2
−1.5
−1
−0.5
950
945
940
935
0
0
2
4
6
8
10
−50
Figure 7.
OSCILLATOR FREQUENCY
vs
CAPACITANCE
Output Maximum Duty Cycle − %
Oscillator Frequency − kHz
100
150
100
TJ = 25°C
100
95
CH2
90
85
CH1/3
80
V(LH) = 5 V, C(CT) = 45 pF,
V(PWM_SEL) = V(FLT) = V(LL) = V(INV)
=0V
75
70
10
0
50
100
150
200
250
300
350
−50
C − Capacitance − pF
Figure 9.
DELAY TIME FLT(OVP)
vs
CAPACITANCE
0
50
100
TJ − Junction Temperature − °C
150
Figure 10.
DELAY TIME FLT(UVP)
vs
CAPACITANCE
100000
100000
VINV = 0.85 to 1.05 V,
TJ = 25°C
10000
t d − Delay Time FLT (UVP) − µ s
t d − Delay Time FLT (OVP) − µ s
50
Figure 8.
OUTPUT MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
1000
VINV = 0.65 to 0.05 V,
TJ = 25°C
10000
1000
100
10
1
0.1
1000
100
10
1
0.1
10
100
1000
10000
C − Capacitance − pF
10
100
1000
10000
C − Capacitance − pF
Figure 11.
16
0
TJ − Junction Temperature − °C
VO − Output Voltage − V
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
SOFT START TIME
vs
CAPACITANCE
CURRENT LIMIT THRESHOLD
VOLTAGE FOR LDO
vs
JUNCTION TEMPERATURE
TJ = 25°C
Soft Start Time − µ s
10000
1000
100
10
1
1
10
100
1000
10000
C − Capacitance − pF
100000
Current Limit Threshold Voltage For LDO − mV
100000
60
50
40
30
20
V(LDO_IN) = 3.3 V
V(INV_LDO) = 0.5 V
10
0
−50
0
50
100
150
TJ − Junction Temperature − °C
Figure 13.
LDO UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
10000
1.2
VTLH
Powergood Delay Time − µ s
LDO UVLO Threshold Voltage − V
Figure 14.
POWERGOOD DELAY TIME
vs
CAPACITANCE
1
VTHL
0.8
0.6
0.4
VIN = 12 V, TJ = 25°C
V(INV_LDO) = 1 V → 0.85 V
1000
100
10
0.2
V(INV_LDO) = 1.2 V
1
0
−50
0
50
100
TJ − Junction Temperature − °C
150
1
10
100
1000
10000
C − Capacitance − pF
Figure 15.
Figure 16.
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APPLICATION INFORMATION
The design shown is a reference design for a notebook PC application. An evaluation module (EVM) is available
for customer testing and evaluation.
The following key design procedures aid in the design of the notebook PC power supply using TPS5130.
B10Q
53C
A10Q
52R
8-5
4
8-5
4
3-1
3-1
10L
14C
1-1OV
B20Q
A20Q
8-5
8-5
4
3-1
4
3-1
4
3-1
4
3-1
10D
73C
20D
03
4C 70D
83C 9
2-1OV
90R
32R
34C
94R
A30R
30C
A10R
20C
B30R
40R
B10R
20R
42R
44C
7164CS2
80Q
62R
30D
10PJ
1
3
11PJ
82R
72R
24C
2
8-5
B40Q
11Q
90Q
1-2OV
92R
82C
93
83
13R
73
24
14
04
54
44
34
84
74
21PJ
60C
70C
30PJ
1
3
2
80C
40PJ
1
90C
3
2
50PJ
1
3
80R
1LL
TP0315SPT
2-2OV
80PJ
2
8-5
3
A30Q
1
2PIRT
22R
u_2TUO
3.3FERV
62C
43
2HL
33
NIV
5FERV
72C
23
3.3FERV
13
1-1NIV
03
92
NIV_ODL
RUC_ODL
1
3-1
B70Q
52
ODL_VNI
2-1NIV
NI_ODL
B12R
8-5
4
62
TUO_ODL
A10C B10C
2
02R
72
ETAG_ODL
A12R
54C
82
1-DNG
01PJ
C12R
3
A70Q
2-DNG
1-TUO_ODL
81R
3
32C
22C
42C
01C
22 3LL
d3_23TUO
3DN
4G
2 TUO
02 3HL
u1_23TUO
3ESNE
9S
1 _NIV
6
T1UOGP
813PIRT
YAL7E1D_GP
31
3YBTS_SS
41 3BF
21R
2
51 3VNI
2-TUO_ODL
31PJ
91R
7164CS2
01Q
23R
50D
31C
70PJ
33R
B60Q
3-1
7012CC 81C
3-1
91C 90D
8-5
30L
41C
1-3OV
4
3-1
12C
B50Q
4
3-1
51C
2-3OV
8-5
A50Q
60D
51R
71R
8-5
DG_RWP
4
8-5
A60Q
61R
B41R
21C
4
43R
41R
11C
11R
31Q
31R
63C
92C
53
NI_V5GER
8
DNG
9
FER
01
5FERV_YBTS
3.3FERV1_1YBTS
2
3
3-1
63
2LL
60PJ
1
1
4
8-5
5FERV
ODL2_1YBTS
2
d_2TUO
1PIRT
5
2YBTS_SS
6
LES_MWP
7 TC
2DNGTUO
1BF
2 _SS
1YBTS
3
2VNI
4 2BF
1DNGTUO
70R
1
21ESNES_NIV
60R
50C
u_1TUO
21Q
3-1
40D
d_1TUO
40C
03C
TLF
1VNI
20PJ
84R
4
03R
B30Q
2
1HL
3
64
10U
1
33C 80D
20L
7164CS2
50R
61C
74R
1433C
C 23C
8-5
A40Q
TILS_NIV
64R
Figure 17. EVM Schematic
An optional circuit composed of Q08, Q09, Q10, R26, R27, R28, R29, R30, R31, R32, R33, and R34 can be
used to increase temperature coefficient of the trip current.
18
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Output Voltage Setpoint Calculation
In Equation 1, assume the output voltage of SBRC1 (VO1), SBRC2 (VO2), SBRC3 (VO3), and LDO (VO4) are
3.3 V, 5 V, 1.8 V, and 1.5 V respectively. The reference voltage and the voltage divider set the output voltage. In
the TPS5130, the reference voltage is 0.85 V, and the divider is composed of three resistors in the EVM design:
• R01A, R01B, and R05 for the first SBRC output
• R03A, R03B, and R07 for the second SBRC output
• R14A, R14B, and R11 for the third SBRC output
• R18 and R19 for LDO regulator output
1R
Vfer
1R
Vfer
V O+
)2R
Vfer ro
+
2R
V O* Vfer
(1)
where
R1 is the top resistor (kΩ) (R01A + R01B or R03A + R03B or R14A + R14B or R18)
R2 is the bottom resistor (kΩ) (R05 or R07 or R11 or R19)
VO is the required output voltage (V)
Vref is the reference voltage (0.85 V in TPS5130).
The value for R1 is set as a part of the compensation circuit and the value of R2 may be calculated to achieve
the desired output voltage. In the EVM design, the value of R1 is determined as R01A = 27 kΩ and
R01B = 1.8 kΩ for VO1, R03A = 47 kΩ and R03B = 1.8 kΩ for VO2, R14A = 10 kΩ and R14B = 1.2 kΩ for VO3,
and R18 = 6.8 kΩ + 820 Ω for VO4 considering stability. For VO1, see Equation 2.
k 72( ))
k 8.1
58.0
50R +
k+
99.9
W
3.3 *
58.0
(2)
Therefore, use 10 kΩ.
In a same manner, R07 = R11 = R19 = 10 kΩ as shown in Equation 3.
k 74( ))
k 8.1
58.0
70R +
k 0+
0.01
W
5*
58.0
11R
k 01(
+
))
k 2.1
58.0
k 2+
0.01
8.1 *
58.0
91R
k 8.6(
+
)
)028 58.0
k+
69.9
5.1 *
58.0
W
W
(3)
The values of R01B, R03B, R14B and R19 are chosen so that the calculated values of R05, R07, R11, and R19
are standard value resistors and the VO setpoint maintains the highest precision. This is best accomplished by
combining two resistor values. If a standard value resistor cannot be applied, use a value for R01A, R03A, R14A,
and R18 that is just slightly less than the desired total. A small resistor value in the range of tens or hundreds of
ohms for R01B, R03B, R14B and R18 can then be added to generate the desired final value.
Output Inductor Selection
The required value for the output filter inductor can be calculated by using Equation 4, assuming the magnitude
of the ripple current is 20% of the maximum output current:
N IV * V O
VO
1
)tL
uo( + 2.0
IO NIV
fS
(4)
where
I(ripple) is the peak-to-peak ripple current (A) through the inductor
IO is the output current
rDS(on) is the on-time resistance of MOSFET (Ω)
RL is the inductor dc resistance (W).
From the equation, it can be seen that the current ripple can be adjusted by changing the output inductor value.
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For example,
If VIN = 8 V, VO = 3.3 V, IO = 4 A, rDS(on) = 25 mΩ, RL = 10 mΩ, fs = 300 kHz, L(out) = 4 µH
Then, the ripple current I(ripple) = 1.57 A
Output Capacitor Selection
Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed on
the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the
output filter sees the entire inductor ripple current then Vpp can be calculated as shown in Equation 5:
Vpp +
)elppiIr(
)R
rse(
(5)
A suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable for the
application.
Output Capacitor RMS Current
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the
output capacitor can be calculated as shown in Equation 6:
)elppiIr(
)s m
I r(
+
O
Ǹ1
2
(6)
where
IO(rms) is maximum RMS current in the output capacitor (A)
I(ripple) is the peak-to-peak inductor ripple current (A)
For example, if I(ripple) = 1.57 A, then IO(rms) = 0.45 A.
Input Capacitor RMS Current
Because the SBRC3 of the TPS5130 operates 180° off phase against the SBRC1 and SBRC2, total RMS current
in the input capacitor (II(rms)) is calculated as follows, assuming the input current totally goes into the input
capacitor to the power ground, and ignoring ripple current in the inductor.
When the duty cycle of the SBRC2 (D2) is over 50%, II(rms) is calculated as shown in Equation 7.
)smIrI(
Ǹ
+ 1D(
I 1
O
I x+1D(
O
2
)
) 2D(
I 2
O
I )1 )2D(
O
2
)
) 3D(
I )2 )32DD(
O
2
I3
O
)
1
) D2(
I )3
O
I )2 )2D(2
O
I1
O
* 1)
I 2
O
I 3*
O
I x
O
w5.0 w1D w3D
2
(7)
where
II(rms) is the input RMS current in the input capacitor
Dx is duty cycles, defined in this case as VO/VI of the SBRCx
When D2 is less than 50%, II(rms) is calculated as shown in Equation 8.
)smIrI(
+ 1ǸD(
IO 1 2)
) 2D(
I 2
O
2
)
) 3D(
I 3
O
2
)
1
) D2(
I 1
O
I )2 *
O
I x
O
2
(8)
For example,
If VIN = 12 V, VO1 = 3.3 V, VO2 = 5 V (D2 = 0.42), VO3 = 1.8 V, IO1 = IO2 = 4 A, IO3 = 6 A
Then, II(rms) = 3.44 A
On the contrary, if three SBRCs operate in a same phase the RMS current is calculated as shown in Equation 9.
)smIrI(
Ǹ
+ 1D(
I 1
O
2
)
) 2D(
I 2
O
2
)
) 3D(
I3
O
2
)
1
) D2(
I1
O
I )2 )
3D2(
O
I )3
O
ǒOI 1)
Ǔ
I 2*
O
I x
O
2
(9)
20
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Soft Start
The soft start timing can be adjusted by selecting the soft-start capacitor value (see Equation 10).
)tfos(t
)tfos(C
+3.2
01 * 6
58.0
(10)
where
C(soft) is the soft-start capacitor (µF) (C05, C07, and C10 in EVM design)
t(soft) is the start-up time (seconds)
For example
If t(soft) = 5 ms
Then, C(soft) = 0.0135 µF
Current Protection
The current limit in TPS5130 is set using an internal current source and an external resistor (R17, R23, and
R24). The current limit protection circuit compares the drain to source voltage of the high-side and low-side
MOSFET(s) with respect to the set-point voltage. If the voltage up exceeds the limit during high-side conduction,
the current limit circuit terminates the high-side driver pulse. If the set point voltage is exceeded during low-side
conduction, the low side pulse is extended through the next cycle. Together this action has the effect of
decreasing the output voltage until the under voltage protection circuit is activated and the fault latch is set and
both the high-side and low-side MOSFET drivers are shut off. Equation 11 should be used for calculating the
external resistor value for current protection set point.
ǒ
r
)lc(R
+
31
I
)elppir(
I )
)pirt(
)no(SD
01
2
Ǔ
6–
(11)
where
R(cl) is the external current limit resistor (R17, R23 and R24)
rDS(on) is the low-side MOSFET(Q02, Q04, and Q06) on-time resistance
I(trip) is the required current limit
For example
If rDS(on) = 25 mΩ, I(trip) = 4 A, I(ripple) = 1.57 A
Then, R(cl)= 9.2 kΩ
It should be noted that rDS(on) of a FET is highly dependent on temperature, so to ensure full output at maximum
operating temperature, the value of rDS(on) in Equation 11 should be adjusted. For maximum stability, it is
recommended that the high-side MOSFET(s) has the same, or slightly higher rDS(on) than the low-side
MOSFET(s). If the low-side MOSFET(s) has a higher rDS(on), in certain low duty cycle applications it may be
possible for the device to regulate at an output current higher than that set by Equation 11 by increasing the
high-side conduction time to compensate for the missed conduction cycle caused by the extension of the
previous low-side pulse.
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Timer Latch
The TPS5130 includes fault-latch function with a user-adjustable timer to latch the MOSFET drivers in case of a
fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge FLT
capacitor (C42), which is connected with FLT pin. The circuit is designed so that, for any value of FLT capacitor,
the undervoltage latch time t(uvplatch) is approximately 50 times larger than the overvoltage latch time t(ovplatch).
Equation 12 shows the equations needed to calculate the required value of the FLT capacitor for the desired
overvoltage and undervoltage latch delay times are:
)h*ct6alpvut (
C
+
3
.
2
0
1
dna
)tal(
581.1
)C
tal( +521
)h*ct6alpvot (
01
581.1
(12)
where
C(lat) is the external capacitor
t(uvplatch) is the time from UVP detection to latch
t(ovplatch) is the time from OVP detection to latch
For the EVM, t(uvplatch) = 5 ms and t(ovplatch) = 0.1 ms, so C(lat) = 0.01 µF. If the voltage on the FLT pin reaches
1.185 V, the fault latch is set, and the MOSFET drivers are set as described in the following sections.
Undervoltage Protection
The undervoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin falls below 65% of the 0.85 V reference, the timer begins to charge the FLT capacitor. if the fault
condition persists beyond the time t(uvplatch), the fault latch is set and both the high-side and low-side drivers, and
LDO regulator drivers are forced OFF.
Short-Circuit Protection
The short-circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current limit
circuit limits the output current, then the output voltage goes below the target output voltage and UVP comparator
detects a fault condition as described above.
Overvoltage Protection
The overvoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin rises above 112% of the 0.85 V reference, the timer begins to charge the FLT capacitor. If the fault
condition persists beyond the time t(ovplatch), the fault latch is set and the high-side drivers are forced OFF, while
the low-side drivers are forced ON, and LDO regulator drivers are forced OFF
CAUTION:
Do not set the FLT terminal to a lower voltage (or GND) while the device is
timing out an OVP or UVP event. If the FLT terminal is manually set to a lower
voltage during this time, output overshoot may occur. The TPS5130 must be
reset by grounding SS_STBYx and STBY_LDO, or dropping down REG5V_IN.
Disablement of the Protection Function
If it is necessary to inhibit the protection functions of the TPS5130 for troubleshooting or other purposes, the
OCP, OVP, and UVP circuits may be disabled.
• OCP(SBRC): Remove the current limit resistors R17, R23 and R24 to disable the current limit function.
• OCP(LDO): Short-circuit R21 to disable the current limit function.
• OVP, UVP: Grounding the FLT terminal can disable OVP and UVP.
22
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LDO Regulator Application Information
Output Capacitor Selection
To keep stable operation of the LDO, capacitance of more than 33 µF and R(esr) of more than 30 mΩ are
recommended for the output capacitor.
Power MOSFET Selection
Also, to keep stable operation of LDO, lower input capacitance is recommended for the external power MOSFET.
However, input capacitance that is too small may lead the feedback loop into an unstable region. In this case, the
gate resistor of several hundreds ohms keeps the LDO operation in the stable state.
Current Protection
If excess output current flows through sense resistor (R21) and the voltage drop exceeds 50 mV, the output
voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer.
When the set current is 3 A, the value of R21 is 16.7 mΩ.
Layout Guidelines
Good power supply results occur only when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less than expected results. With a range of
currents from milliamps to tens amps, good power supply layout is much more difficult than most general PCB
designs. The general design should proceed from the switching node to the output, then back to the driver
section and, finally, parallel the low-level components. Below are specific points to consider before the layout of a
TPS5130 design begins.
• A four-layer PCB design is recommended for design using the TPS5130. For the EVM design, the top layer
contains the interconnection to the TPS5130, plus some additional signal traces. Layer2 is fully devoted to the
ground plane. Layer3 has some signal traces. The bottom layer is almost devoted to ANAGND, and the rest
is to other signal trace.
• All sensitive analog components such as INV, REF, CT, GND, FLT, and SS_STBY should be referenced to
ANAGND.
• Ideally, all of the area directly under the TPS5130 chip should also be ANAGND.
• ANAGND and DRVGND should be isolated as much as possible, with a single point connection between
them.
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CTRIP
TRIP
VIN_SENSE
VREF5
VIN
CBS
LH
CBP
OUT_u
CIN
Vox
LL
INV
FB
COUT
SOFT_START
ANAGND
CT
GND
REF
OUT_d
OUTGND
DRVGND
VoxGND
LDO_IN
LDO_CUR
FLT
LDO_GATE
INV_LDO
LDO_OUT
Vo_LDO
Figure 18. PCB Diagram
Low-Side MOSFET(s)
• The source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject to the
noise of the outputs.
• DRVGND should be connected to the main ground plane close to the source of the low-side MOSFET.
• OUTGND should be placed close to the source of low side MOSFET(s).
• The Schottky diode anode, the returns for the high frequency bypass capacitor for the MOSFETs, and the
source of the low-side MOSFET(s) traces should be routed as close together as possible.
Connections
• Connections from the drivers to the gate of the power MOSFETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used. In addition,
as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s) considerably reduces
the noise at the LL node, improving the performance of the current limit function.
• The connection from LL to the power MOSFETs should be as short and wide as possible.
Bypass Capacitor
• The bypass capacitor for VIN_SENSE should be placed close to the TPS5130.
• The bulk storage capacitors across VIN should be placed close to the power MOSFETs. High-frequency
bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of
the high-side MOSFET(s) and to the source of the low-side MOSFET(s).
• For aligning phase between the drain of high-side MOSFET(s) and the trip-pin, and for noise reduction, a
0.1 µF capacitor C(TRIP) should be placed in parallel with the trip resistor.
Bootstrap Capacitor
• The bootstrap capacitor C(BS) (connected from LH to LL) should be placed close to the TPS5130.
• LH and LL should be routed close to each other to minimize noise coupling to these traces.
• LH and LL should not be routed near the control pin area (INV, FB, REF, etc.).
24
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Output Voltage
• The output voltage sensing trace should be isolated by either ground plane.
• The output voltage sensing trace should not be placed under the inductors on same layer.
• The feedback components should be isolated from output components, such as, MOSFETs, inductors, and
output capacitors. Otherwise the feedback signal line is susceptible to output noise.
• The resistors for setup output voltage should be referenced to ANAGND.
• The INV trace should be as short as possible.
Output Characteristics
YCNEICIFF)EEDOM MWP(
sv
TNERRUC TUPTUO
YCNEICIFF)EEDOM MWP(
sv
TNERRUC TUPTUO
001
001
VV8
NI=
01
1
1.0
I−
A − tnerruC tuptuOO
% − )EDOM MWP( ycneiciffE
0
10.0
06
V 0V2
NI=
V 0V2
NI=
04
CRBS 1HC
V 5 lanretxE
V 3.3V=O 1
V 2V1
NI=
V 2V1
NI=
06
V 0V2
NI=
02
08
04
CRBS 2HC
V 5 lanretxE
V 5V=O 2
02
0
10.0
01
1
1.0
I−
A − tnerruC tuptuOO
Figure 19.
YCNEICIFFE
)EDT
OU
MAP
( IKS O
sv
TNERRUC TUPTUO
Figure 20.
)EDT
OU
MAP
( IKS O
sv
TNERRUC TUPTUO
Figure 21.
)EDT
OU
MAP
( IKS O
sv
TNERRUC TUPTUO
001
VV8
NI=
08
VV8
NI=
0
10.0
YCNEICIFFE
001
08
CRBS 3HC
V 5 lanretxE
V 8.1V=O 3
02
I−
A − tnerruC tuptuOO
YCNEICIFFE
001
% − )EDOM MWP( ycneiciffE
V 2V1
NI=
04
% − )EDOM MWP( ycneiciffE
VV8
NI=
08
06
08
VV8
NI=
V 2V1
NI=
V 2V1
NI=
06
001
VV8
NI=
08
1.0
YCNEICIFF)EEDOM MWP(
sv
TNERRUC TUPTUO
V 2V1
NI=
V 0V2
NI=
V 0V2
NI=
06
06
V 0V2
NI=
CRBS 1HC
V 5 lanretxE
V 3.3V=O 1
0
10.0
01
I−
A − tnerruC tuptuOO
1
02
1.0
Figure 22.
% − )EDOM PIKS OTUA( ycneiciffE
1.0
% − )EDOM PIKS OTUA( ycneiciffE
02
04
04
CRBS 2HC
V 5 lanretxE
V 5V=O 2
0
10.0
01
I−
A − tnerruC tuptuOO
1
02
1.0
Figure 23.
% − )EDOM PIKS OTUA( ycneiciffE
04
CRBS 3HC
V 5 lanretxE
V 8.1V=O 3
0
10.0
I−
A − tnerruC tuptuOO
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SBRC CH2 OUTPUT LINE REGULATION
SBRC CH1 OUTPUT LINE REGULATION
IO = 4 A
IO = 4 A
3.266
3.264
3.262
VO − Output Voltage − V
VO − Output Voltage − V
VO − Output Voltage − V
IO = 6 A
1.764
5.002
3.268
5
4.998
4.996
10
15
VI − Input Voltage − V
5
20
10
15
VI − Input Voltage − V
Figure 25.
1.760
1.758
20
LDO OUTPUT LINE REGULATION
SBRC CH1 OUTPUT LOAD REGULATION
V(LDO_IN = VO3
IO = 3 A
SBRC CH2 OUTPUT LOAD REGULATION
5.030
PWM Mode
VIN = 12 V
VO − Output Voltage − V
1.460
1.458
1.456
3.280
3.275
3.270
3.260
10
15
VI − Input Voltage − V
20
1
2
3
IO− Output Current − A
4
0
1
2
3
IO− Output Current − A
4
Figure 30.
LDO OUTPUT LOAD REGULATION
1.790
1.480
PWM Mode
VIN = 12 V
V(LDO_IN)= VO3
1.475
VO − Output Voltage − V
VO − Output Voltage − V
5.010
Figure 29.
SBRC CH3 OUTPUT LOAD REGULATION
1.780
1.775
1.770
1.765
1.760
0
5.015
5
0
Figure 28.
1.785
5.020
5.005
3.265
1.454
PWM Mode
VIN = 12 V
5.025
VO − Output Voltage − V
3.285
1.462
20
Figure 27.
3.290
5
10
15
VI − Input Voltage − V
Figure 26.
1.464
VO − Output Voltage − V
1.762
1.756
5
4.994
3.260
5
1
2
3
4
IO− Output Current − A
5
6
1.470
1.465
1.460
1.455
1.450
0
1
2
3
IO− Output Current − A
Figure 31.
26
SBRC CH3 OUTPUT LINE REGULATION
1.766
5.004
3.270
Figure 32.
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SBRC CH2 OUTPUT VOLTAGE RIPPLE
SBRC CH1 OUTPUT VOLTAGE RIPPLE
SBRC CH3 OUTPUT VOLTAGE RIPPLE
20 mV/div
50 mV/div
50 mV/div
VIN = 12 V, VO1 = 3.3 V
IO1 = 0 A
IO2 = 0 A
IO2 = 0 A
2A
2A
4A
4A
4A
6A
VIN = 12 V, VO2 = 5 V
1 µs/div
Figure 33.
1 µs/div
VIN = 12 V, VO3 = 1.8 V
Figure 34.
LDO OUTPUT VOLTAGE RIPPLE
1 µs/div
Figure 35.
SBRC CH1 LOAD TRANSIENT RESPONSE
SBRC CH2 LOAD TRANSIENT RESPONSE
10 mV/div
VO2
20 mV/div
VO1
20 mV/div
IO= 0.3 A
1A
4A
4A
3A
IO1
2 A/div
0A
VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V,
IO3 = 0 A
1 µs/div
VIN = 12 V, VO1 = 3.3 V
Figure 36.
IO2
2 A/div
0A
Figure 37.
SBRC CH3 LOAD TRANSIENT RESPONSE
VO3
20 mV/div
100 µs/div
VIN = 12 V, VO2 = 5 V
100 µs/div
Figure 38.
LDO LOAD TRANSIENT RESPONSE
VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V,
V(LDO) = 1.5 V
VO
50 mV/div
6A
3A
IO3
2 A/div
0A
IO
1 A/div
30 mA
VIN = 12 V, VO3 = 1.8 V
100 µs/div
100 µs/div
Figure 39.
Figure 40.
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27
TPS5130-Q1
SLVS866 – MARCH 2009................................................................................................................................................................................................... www.ti.com
SBRC CH1 GAIN AND PHASE
80
SBRC CH2 GAIN AND PHASE
80
240
120
Phase
60
20
0
0
−40
100
1K
Phase
60
20
0
0
Gain
10K
100K
f − Frequency − Hz
120
40
−60
−20
−120
−40
100
1M
SBRC CH3 GAIN AND PHASE
LDO GAIN AND PHASE
20
60
0
0
60
20
Gain
0
0
−60
−20
−120
−40
100
Figure 43.
28
120
Phase
Gain
1M
180
40
Gain − dB
Phase
Phase − Degrees
120
40
Gain − dB
60
180
10K
100K
f − Frequency − Hz
240
Phase Margin = 74 Degrees
60
1K
1M
80
240
Phase Margin = 37 Degrees
−40
100
10K
100K
f − Frequency − Hz
Figure 42.
80
−20
−60
−120
1K
Figure 41.
VIN = 12 V,
VO3 = 1.8 V,
IO3 = 6 A
Gain
VIN = 12 V,
VO2 = 5 V,
IO2 = 4 A
VIN = 12 V,
V(LDO_IN) = VO3 =1.8 V,
I(LDO) = 3 A
1K
10K
100K
f − Frequency − Hz
Phase − Degrees
−20
180
Phase − Degrees
40
60
Gain − dB
180
Phase − Degrees
Gain − dB
Phase Margin = 53 Degrees
60
VIN = 12 V,
VO1 = 3.3 V,
IO1 = 4 A
240
Phase Margin = 59 Degrees
−60
−120
1M
Figure 44.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPS5130QPTRQ1
ACTIVE
LQFP
PT
Pins Package Eco Plan (2)
Qty
48
1000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS5130-Q1 :
• Catalog: TPS5130
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
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Addendum-Page 1
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°– 7°
0,75
0,45
0,10
4040052 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This may also be a thermally enhanced plastic package with leads conected to the die pads.
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