WinSystems PPM-C407 Product manual

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WinSystems PPM-C407 Product manual | Manualzz

PPM-C407

Intel

®

Atom™ E3800 PC/104-Plus

Single Board Computer with Digital I/O

Product Manual

PRELIMINARY

WinSystems, Inc. | 715 Stadium Drive, Arlington, Texas 76011 | 817-274-7553 | [email protected] | www.winsystems.com

v1.0

PPM-C407

Revision History

Document

Version

v1.0

Last Updated

Date

2/2016 Initial release

Brief Description of Change

Copyright and Trademarks

Copyright 2016, WinSystems, Inc.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of WinSystems, Inc. The information in the document is subject to change without notice. The information furnished by WinSystems, Inc. in this publication is believed to be accurate and reliable. However, WinSystems, Inc.

makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. WinSystems, Inc. makes no warranty of merchantability or fitness for any purpose. WinSystems, Inc. assumes no responsibility for any errors that may appear in this document.

Trademark Acknowledgments

WinSystems is a registered trademark of WinSystems, Inc.

Duo-Clasp™ and Pico-Clasp™ are registered trademarks of Molex, Inc.

Phoenix SecureCore™ is a registered trademark of Phoenix Technologies Ltd.

PRELIMINARY www.winsystems.com

Page i

v1.0

Table of Contents

1 Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.1

System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1

Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1.1

Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1.2

Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2

I/O Port Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3

Interrupt Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.4

Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.4.1

Port 0 through 5 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.4.2

INT_PENDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.4.3

PAGE/LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.4.4

POL0 through POL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.4.5

ENAB0 through ENAB2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.5

Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.6

7.7

7.4.6

INT_ID0 through INT_ID2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.5.1

PRELIMINARY

7.8

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.8.1

J1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.8.2

J2 PC/104 bus (C/D, 16-bit ISA bus also includes J3) Connector

J3 PC/104 bus (A/B, 8-bit ISA bus) Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.8.3

J4 External Battery Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.8.4

J5 LVDS and Audio Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.8.5

J6 Mini DisplayPort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PPM-C407 www.winsystems.com

Page ii

v1.0

7.8.6

J7 VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.8.7

J8 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.8.8

J9 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.8.9

J11 Ethernet External LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.8.10 J12 PC/104-Plus (PCI bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.8.11 J500 Backlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.8.12 J501 Mini-PCIe/mSATA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.8.13 J503 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.8.14 J504 Digital Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.8.15 J505 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.9

Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.9.1

JP1 AT/ATX Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.9.2

JP3 Basic Input/Output System (BIOS) Programming Defaults . . . . . . . . . . . . . . . . . . . . . . 34

7.9.3

JP4 Low-Voltage Differential Signaling (LVDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.10 LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.10.1 D504 User LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 BIOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2

Entering Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.3

Navigation of the Menus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.4

BIOS Splash Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.5

BIOS Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9 Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10 Software Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Appendix A. Best Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Appendix B. Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

PRELIMINARY

PPM-C407/ www.winsystems.com

Page iii

v1.0

PPM-C407/Before You Begin

1.

Before You Begin

Review the warnings in this section and the best practice recommendations (see “Best

Practices” on page 53) when using and handling the WinSystems PPM-C407. Following

these recommendations provides an optimal user experience and prevents damage.

Read through this document and become familiar with the PPM-C407 before proceeding.

FAILING TO COMPLY WITH THESE BEST PRACTICES MAY DAMAGE THE PPM-C407

AND VOID YOUR WARRANTY.

1.1

Warnings

Only qualified personnel should configure and install the PPM-C407. While observing the best practices, pay particular attention to the following:

Avoid Electrostatic Discharge (ESD)

Only handle the circuit board and other bare electronics when electrostatic discharge

(ESD) protection is in place. Having a wrist strap and a fully grounded workstation is the minimum ESD protection required before the ESD seal on the product bag is broken.

2.

Introduction

This manual provides configuration and usage information for the PPM-C407. If you still have questions, contact Technical Support at (817) 274-7553, Monday through

Friday, between 8 AM and 5 PM Central Standard Time (CST).

Refer to the WinSystems website for other accessories (including cable drawings and pinouts) that can be used with your PPM-C407.

3.

PRELIMINARY

The PPM-C407 is a full-featured embedded single board computer that operates in the

Windows 7, Windows 8, Windows CE, Linux and DOS environments. It features an

Intel

®

Atom™ E3800 Processor, up to 4 GB soldered DDR3 RAM, PC/104 and PC/104-

Plus bus connectors (stack-through connectors are optional), as well as optional fanless operation. It provides 24 lines of 5 V DC tolerant digital input-output (DIO), and also video output with audio support. Communication interfaces include Gigabit

Ethernet, four USB 2.0 ports, two serial RS-232/422/485 channels and two serial

www.winsystems.com

Page 1

v1.0

PPM-C407/Features

4.

Features

RS-232. channels. Refer to “Features” on page 2 and “General Operation” on page 4 for

specific information.

NOTE WinSystems can provide custom configurations for OEM clients. Please contact an

Application Engineer for details.

The PPM-C407 provides the following features:

Single Board Computer

• PC/104-Plus Compatible Single Board Computer

– Optional stack-through PC/104-Plus connectors

• Available Multi-Core Intel

®

Atom™ E3800 Processors

– E3815 1 core, 1.46 GHz

– E3825 2 core, 1.33 GHz

– E3845 4 core, 1.91 GHz

Operating Systems (compatibility)

• Windows (32/64-bit)

• Linux

• other x86-compatible

Memory

• Available 2 GB or 4 GB Soldered Down DDR3 RAM

BIOS

• Phoenix SecureCore™

Video Interfaces (Intel Gen7 Graphics, one or two simultaneously active displays)

• Mini DisplayPort (version 1.1)

• Low-Voltage Differential Signaling (LVDS, 18 or 24 bpp)

Ethernet

• Intel

® i210 Gigabit Ethernet port (1 gigabit per second, GbE) with Surge

Suppression

Storage

• MiniPCIe/mSATA Socket (same connection as used for Bus Expansion)

• Bootable SATA and mSATA Socket

www.winsystems.com

Page 2

v1.0

PPM-C407/Features

Digital Input/Output (DIO)

• 24 lines (bi-directional) provided within the Lattice Semiconductor Corp.,

MachXO2™ FPGA (field-programmable gate array) interfaced to the processor with the Low Pin Count (LPC) interface.

• 5 V tolerant signals

• Each line programmable for input, output, or event sense

• Lines can be paired with external isolation and relay modules

Bus expansion

• PC/104-Plus (PC/104 and PCI-104)

• MiniPCIe/mSATA Socket (same connection as used for Storage)

Serial Interface

• Four USB 2.0 with Surge Suppression

• Serial Ports

– Two RS232/422/485: speeds to 500 Kbps (0.5 Mbps)

– Two RS232: speeds to 250 Kbps (0.25 Mbps)

Audio

• Stereo Audio (Line In, Line Out, Mic)

Power

• +5 V DC Power Input

Industrial Operating Temperature

• Fanless -40 °C to +85 °C (-40 °F to +185 °F)

Additional features

• Watchdog timer from 1 second to 255 minutes (15,300 seconds)

• Real-Time Clock (RTC) with optional battery back up

• Speaker output

www.winsystems.com

Page 3

v1.0

PPM-C407/General Operation

5.

General Operation

5.1

System Block Diagram

The PPM-C407 is a single-board computer (SBC). It is a full-featured embedded system with a variety of onboard I/O options. The following figure is a simplified system block diagram of the PPM-C407.

DDR3L

Memory Down x64

Display Controller

E3815

E3827

E3845

Legacy

Interface

USB

Audio

SATA 1

SATA 2

PCIe 2

PCIe 1

PCIe 0

LPC

DisplayPort to LVDS

USB Power Switch

HD Audio Codec

MUX

PCIe to PCI Bridge i210 MAC/PHY

VGA

Mini DP

LVDS

USB 1-4

Audio

SATA mini PCIe/ mSATA

PC/104-Plus

Gigabit Enet

FPGA

SUPER I/O

Level Translators

RS232

RS232/RS422/485

PC/104

DIO24

COM 1-2

COM 3-4

Three display interfaces (MiniDisplayPort, VGA, and LVDS) support up to two independent displays along with stereo audio. Communication interfaces include

Gigabit Ethernet, four USB 2.0 ports, two serial RS-232/422/485 channels and two serial RS-232 channels. 24 digital I/O lines with event sense can be programmed

PRELIMINARY

soldered RAM for added shock and vibration resistance, and provides an optional fanless solution for operating temperatures between -40 °C and +85 °C (-40 °F and

+185 °F).

The PPM-C407 processor options provide single, dual, or quad-core processing. Each processor option is available with 2 GB or 4 GB of soldered DDR3 memory and optional stack-through PC/104-Plus connectors.

www.winsystems.com

Page 4

v1.0

PPM-C407/Specifications

Linux, Windows and other x86 operating systems can be initialized from the SATA, mSATA, or USB interfaces. This provides flexible data storage options.

6.

Specifications

The PPM-C407 adheres to the following specifications and requirements:

PPM-C407 Specifications

V

CC

Models

1, 2

1

See processor for 38XX models

2

Add -ST to the end of each part number for a stack-through configuration

Electrical

+5 V DC ±5% required

PPM-C407-38XX-2-0

PC/104-Plus SBC E3825 2 GB with heat spreader

PPM-C407-38XX-2-1

PC/104-Plus SBC E3825 2 GB with heatsink

PPM-C407-38XX-4-0

PC/104-Plus SBC E3825 4 GB with heat spreader

PPM-C407-38XX-4-1

PC/104-Plus SBC E3825 4 GB with heatsink

PPM-C407-38XX-2-0-ST

PC/104-Plus SBC E3845 2 GB with heat spreader

PPM-C407-38XX-2-1-ST

PC/104-Plus SBC E3845 2 GB with heatsink

PPM-C407-38XX-4-0-ST

PC/104-Plus SBC E3845 4 GB with heat spreader

PPM-C407-38XX-4-1-ST

PC/104-Plus SBC E3845 4 GB with heatsink

Processor 3815: E3815 single-core 1.46 GHz, 512 K cache (MOQ

Dimensions required)

3825: E3825 dual-core 1.33 GHz, 1 MB cache

PRELIMINARY

Weight

PCB thickness

7.592 oz (215.23 g), without optional heatsink

0.078 inch (1.98 mm)

www.winsystems.com

Page 5

v1.0

PPM-C407/Specifications

PPM-C407 Specifications (Continued)

-40 °C to +85 °C (-40 °F to +185 °F)

5% to 95% non-condensing

MIL-STD-202G, Method 213B, Condition A 50g half-sine,

11 ms duration per axis, 3 axis

MIL-STD-202G, Method 214A, Condition D .1g/Hz

(11.95g rms), 20 minutes per axis, 3 axis

Yes

Environmental

Temperature

Humidity (RH)

Mechanical Shock

Testing

Random Vibration

Testing

RoHS Compliant

Operating Systems

Runs 32/64-bit Windows, Linux, and other x86-compatible operating systems.

Additional Accessories

Standoff kits are available and recommended for use with the PPM-C407.

• KIT-PCM-STANDOFF-4: Four piece Nylon Hex PC/104 Standoff Kit

• KIT-PCM-STANDOFF-B-4: Four piece Brass Hex PC/104 Standoff Kit

The following table lists the items contained in each kit:

Kit Component Description

KIT-PCM-STANDOFF-4

4 pc. Nylon Hex PC/104

Standoff Kit

Standoff

Hex Nut

Screw

Nylon 0.25” Hex, 0.600" Long

Male/Female 4-40

Hex Nylon 4-40

Phillips-Pan Head (PPH)

4-40 x 1/4" Stainless Steel

KIT-PCM-STANDOFF-B-4 Standoff

Hex Nut

Brass 5 mm Hex, 0.600" Long

Male/Female 4-40

4-40 x 0.095 Thick, Nickel Finish 4

4 pc.Brass Hex PC/104

Standoff Kit

Screw Phillips-Pan Head (PPH)

4-40 x 1/4" Stainless Steel

PRELIMINARY

4

4

4

4

4

Qty www.winsystems.com

Page 6

v1.0

PPM-C407/Configuration

7.

Configuration

This section describes the PPM-C407 components and configuration.

7.1

Component Layout

The PPM-C407 provides components on the top and bottom of the board.

7.1.1 Top View

D1

C1

B1

A1

J12

D30

C30

B30

A30

1

4

J11

J9

1

20

2

D7

J8

D10

D9

19

1

1

3

29

J4

J1

B1

A1

12 7

C0

D0

JP1 JP3 JP4

1 2 3

D19

J2

B32

A32

J5

39

14

J7

1

J6

1

19

1

2

40

30

2

2

20 www.winsystems.com

Page 7

PPM-C407/Configuration

Top View Components

:

Item

J9

J11

J12

JP1

JP3

JP4

D7, D9,

D10

J5

J6

J7

J8

J1

J2

J3

J4

Description Reference

Power Connector

page 16

PC/104 Bus (C/D, 16-bit ISA bus also includes J3) Connector

page 17

PC/104 Bus (A/B, 8-bit ISA bus) Connector

External Battery Connector

page 17

page 19

LVDS and Audio Connector

Mini DisplayPort

VGA

USB

page 20

page 22 page 22

page 23

Serial Ports

Ethernet External LEDs

PC/104-Plus (PCI bus)

AT/ATX Power Mode

Basic Input/Output System (BIOS) Defaults

Low-Voltage Differential Signaling (LVDS)

LED Indicators

page 24

page 26

page 27

page 33

page 34 page 34

page 35

v1.0

PRELIMINARY www.winsystems.com

Page 8

v1.0

PPM-C407/Configuration

7.1.2 Bottom View

50

J504

49

2

D504

1

1

8

J500

J501

Bottom View Components

:

Item Description Reference

J500

J501

J503

J504

Backlight

Mini PCIe/mSATA Connector

Serial ATA (SATA)

Digital Input/Output

page 28

page 29

page 31

page 32

J505

D504

Ethernet

User LED Indicator

PRELIMINARY

page 33

page 35

10

2

J505

9

1

1

7

J503 www.winsystems.com

Page 9

v1.0

PPM-C407/Configuration

7.2

I/O Port Map

The PPM-C407 uses plug-and-play (PnP) BIOS resource allocation. Care must be taken to avoid contention with resources allocated by the BIOS.

The PPM-C407 utilizes a Low Pin Count to Industry Standard Architecture bridge (LPC to ISA Bridge) to address the PC/104 bus. Most legacy PC/104 modules are I/O mapped and function as expected. The LPC controller is the subtractive agent of the Intel Legacy

Block. All transactions not claimed elsewhere are sent to the LPC controller. The LPC to

ISA Bridge does not implement bus mastering cycles or direct memory access (DMA).

The following tables contain the I/O ports used on the PPM-C407.

Movable I/O Ranges

Device

ACPI Power Management

(PCU)

SMBus (PCU)

GPIO (PCU)

RCBA (PCU)

Size (bytes)

128

32

256

1024

Target

ACPI_BASE_ADDR (PM1BLK): PCI[B:0,

D:31, F:0] + 40h

SMBA: PCI[B:0, D:31, F:3] + 20h

GBA: PCI[B:0, D:31, F:0] + 48h

RCRB_BA: PCI[B:0, D:31, F:0] + F0h

PCU Fixed I/O Addresses

I/O Address Device

0000h-001Fh

0020h-0021h

0024h-0025h

0028h-0029h

DMA Controller 82C37

Interrupt Controller 8259 Master

Interrupt Controller 8259 Master

Interrupt Controller 8259 Master

002Ch-002Dh Interrupt Controller 8259 Master

0030h-0031h

0034h-0035h

0038h-0039h

003Ch-003Dh

Interrupt Controller 8259 Master

Interrupt Controller 8259 Master

Interrupt Controller 8259 Master

0040h-0043h

0050h-0053h

0060h

0061h

0062h

0064h

0066h

0070h-0077h

Timer counter 8254

Timer counter 8254

PS2 Control (data port)

NMI controller

8051 download 4K address counter

PS2 Control (status port)

8051 download 8-bit data port

RTC Controller

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PCU Fixed I/O Addresses (Continued)

I/O Address

0080h-0083h

0092h

00A0h-00A1h

00A4h-00A5h

00A8h-00A9h

0ACh-00ADh

00B0h-00B1h

00B2h-00B3h

00B4h-00B5h

00B8h-00B9h

0120h-012Fh

0298h-029Bh

029C

029D

029E-029F

02E8h-02EFh

02F8h-02FFh

03E8h-03EFh

03F8h-03FFh

0564h-0568h

0CF9h

Device

Port 80

Init Register (Reset Generator)

Interrupt Controller 8259 Slave

Interrupt Controller 8259 Slave

Interrupt Controller 8259 Slave

Interrupt Controller 8259 Slave

Interrupt Controller 8259 Slave

Power Management

Interrupt Controller 8259 Slave

Interrupt Controller 8259 Slave

Digital I/O (Default)

Reserved for Super I/O Configuration

Interrupt Status Register

Status LED Register

Watchdog Timer Control

COM4 (Default)

COM2 (Default)

COM3 (Default)

COM1 (Default)

Advanced Watchdog

Reset Generator

7.3

Interrupt Map

Hardware Interrupts (IRQs) are supported for PC/104 (ISA), PCI, and PCIe devices. The user must reserve IRQs in the BIOS CMOS configuration for use by legacy devices. The

PCIe/PnP BIOS will use unreserved IRQs when allocating resources during the boot process. The following tables contain the IRQ resources as used by the PPM-C407.

PRELIMINARY

IRQ2

IRQ3

Chained to Slave controller (IRQ9)

COM2 *

IRQ4

IRQ5

IRQ6

IRQ7

COM1 *

COM3 *

COM4 *

FREE **

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IRQ resources (Continued)

IRQ Device

IRQ8

IRQ9

IRQ10

IRQ11

Real Time Clock

FREE **

Digital I/O

PCI Interrupts

IRQ12

IRQ13

IRQ14

IRQ15

Mouse

Floating point processor

SATA Controller

SATA Controller ***

* These IRQ references are default settings that can be changed by the user in the CMOS Settings utility. Reference the

Super I/O Control section under Intel.

** IRQ9 is commonly used by ACPI when enabled and may be unavailable (depending on operating system) for other uses.

*** IRQ15 is currently unavailable under the Windows operating systems.

Some IRQs can be freed for other uses if the hardware features they are assigned to are not being used. To free an interrupt, use the CMOS setup screens to disable any unused board features or their IRQ assignments.

Interrupt Status Register - 29CH

Bit Name

Bit 0

Bit 1

Bit 2

Bit 3

COM1

COM2

COM3

COM4

Bit 4

Bit 5

Bit 6

Bit 7

N/A

N/A

N/A

N/A

WinSystems does not provide software support for implementing the Interrupt Status Register to share interrupts.

Some operating systems, such as Windows XP and Linux, have support for sharing serial port interrupts (see your specific operating system’s documentation for any available examples). You will need to implement the appropriate software to share interrupts for the other devices.

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7.4

Register Definitions

The PPM-C407 uses the WinSystems exclusive application-specific integrated circuit

(ASIC), the WS16C48. This device provides 48 lines of digital I/O. There are 16 unique registers within the WS16C48. The following table summarizes the registers.

I/O Address Offset

04h

05h

06h

07h

00h

01h

02h

03h

08h

09h

0Ah

Page 0 Page 1 Page 2 Page 3

Port 0 I/O

Port 1 I/O

Port 2 I/O

Port 3 I/O

Port 0 I/O Port 0 I/O Port 0 I/O

Port 1 I/O Port 1 I/O Port 1 I/O

Port 2 I/O Port 2 I/O Port 2 I/O

Port 3 I/O Port 3 I/O Port 3 I/O

Port 4 I/O

Port 5 I/O

Port 4 I/O Port 4 I/O Port 4 I/O

Port 5 I/O Port 5 I/O Port 5 I/O

Int_Pending Int_Pending Int_Pending Int_Pending

Page/Lock Page/Lock Page/Lock Page/Lock

Reserved

Reserved

Reserved

Pol_0

Pol_1

Pol_2

Enab_0

Enab_1

Enab_2

Int_ID0

Int_ID1

Int_ID2

The following sections provide details on each of the internal registers.

7.4.1 Port 0 through 5 I/O

Each I/O bit in each of the six ports can be individually programmed for input or output.

Writing a 0 to a bit position causes the corresponding output pin to go to a highimpedance state (pulled high by external 10 K

 resistors). This allows it to be used as an input. When used in the input mode, a read reflects the inverted state of the I/O pin, such that a high on the pin will read as a 0 in the register. Writing a 1 to a bit position causes that output pin to sink current (up to 12 mA), effectively pulling it low.

7.4.2 INT_PENDING

This read-only register reflects the combined state of the INT_ID0 through INT_ID2 registers. When any of the lower three bits are set, it indicates that an interrupt is

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7.4.3 PAGE/LOCK

This register serves two purposes. The upper two bits (D6 and D7) select the register page in use. Bits 0-5 allow for locking the I/O ports. Write a 1 to the I/O port position to prohibit further writes to the corresponding I/O port:

Page

Page 0

Page 1

Page 2

Page 3

D7

1

1

0

0

D6

0

1

0

1

D5-D0

1/0

1/0

1/0

1/0

7.4.4 POL0 through POL2

These registers are accessible when Page 1 is selected. They allow interrupt polarity selection on a port-by-port and bit-by-bit basis. Writing a 1 to a bit position selects the rising edge detection interrupts while writing a 0 to a bit position selects falling edge detection interrupts.

7.4.5 ENAB0 through ENAB2

These registers are accessible when Page 2 is selected. They allow for port-by-port and bit-by-bit enabling of the edge detection interrupts. When set to a 1, the edge detection interrupt is enabled for the corresponding port and bit. When cleared to 0, the bit’s edge detection interrupt is disabled. Note that this register can be used to individually clear a pending interrupt by disabling and re-enabling the pending interrupt.

7.4.6 INT_ID0 through INT_ID2

These registers are accessible when Page 3 is selected. They are used to identify currently pending edge interrupts. A bit when read as a 1 indicates that an edge of the polarity programmed into the corresponding polarity register has been recognized. Note that a write to this register (value ignored) clears ALL of the pending interrupts in this register.

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PPM-C407/Configuration

7.5

Watchdog Timer

The PPM-C407 features an advanced watchdog timer which can be used to guard against software lockups. Two interfaces are provided to the watchdog timer. The

Advanced interface is the most flexible and recommended for new designs. The other interface option is provided for software compatibility with older WinSystems single board computers.

7.5.1 Advanced

The watchdog timer can be enabled in the BIOS Settings by entering a value for

Watchdog Timeout on the Intel > Super I/O Control screen. Any non-zero value represents the number of minutes prior to reset during system boot. Once the operating system is loaded, the watchdog can be disabled or reconfigured in the application software.

NOTE Use a long timeout if the watchdog is enabled when trying to boot any operating system.

The watchdog can be enabled, disabled, or reset by writing the appropriate values to the configuration registers located at I/O addresses 565h and 566h. The watchdog is enabled by writing a timeout value other than zero to the I/O address 566h and disabled by writing 00h to this I/O address. The watchdog timer is serviced by writing the desired timeout value to I/O port 566h. If the watchdog has not been serviced within the allotted time, the circuit resets the CPU.

The timeout value can be set from 1 second to 255 minutes. If port 565h bit 7 equals 0, the timeout value written into I/O address 566h is in minutes. The timeout value written to address 566h is in seconds if port 565 bit 7 equals 1.

Watchdog Timer Examples

Port

Address

Port Bit 7

Value

Port Address Value Reset Interval

565h x 566h 00h DISABLED

565h

565h

565h

565h

1

1

0

0

566h

566h

566h

566h

03h 3 seconds

1Eh 30 seconds

04h 4 Minutes

05h 5 Minutes

Software watchdog timer PET = PORT 566h, write the timeout value.

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7.6

Real-time Clock/Calendar

A real-time clock is used as the AT-compatible clock/calendar. It supports a number of features including periodic and alarm interrupt capabilities. In addition to the time and date keeping functions, the system configuration is kept in CMOS RAM contained within the clock section. A battery must be enabled for the real-time clock to retain time and date during a power down.

7.7

Power

The PPM-C407 draws power through the J1 connector (see “J1 Power Connector” on page 16). The main supply to the board is 5 V DC. If supplied to the input connector, the

+12 V DC and -12 V DC supply only the PC/104 and PC/104-Plus connectors; 5 V DC stand-by is only required to supply the power connector for ATX mode operation.

The PPM-C407 supports AT or ATX type power supplies. Jumper JP1 (see “JP1 AT/ATX

Power Mode” on page 33) specifies the type of supply connected to the single board

computer. AT Power is a simple on/off power supply with no interaction with the single board computer. Most embedded systems use this type of power supply (default setting).

7.8

Connectors

7.8.1 J1 Power Connector

Use this connection to supply power to the PPM-C407. Set Jumper JP1 (see “JP1 AT/

ATX Power Mode” on page 33) to select the type of power supply operation (AT or

ATX).

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Layout and Pin Reference:

12

6

7

1

Pin

4

5

6

1

2

3

Name

ATX_PWRGOOD

GND

GND

+12VDC

PSON_N

PMC_RSTBTN_N

Pin

10

11

12

7

8

9

Name

+5V_SB

+5 V

+5 V

-12 V

GND

PWRBTN_N

Additional Information

This power connection uses a 12-pin Samtec IPL1-106-01-L-D-RA-K, 2x6, 2.54 mm pitch mini-mate locking header connector.

Matching connector:

• Samtec IPD1-06-D-K housing

• Samtec CC79L-2024-01L crimp pins

WinSystems cable CBL-PWR-700-18 simplifies this connection to the board.

7.8.2 J2 PC/104 bus (C/D, 16-bit ISA bus also includes J3) Connector

J3 PC/104 bus (A/B, 8-bit ISA bus) Connector

The PC/104 bus is electrically equivalent to the 16-bit ISA bus. Standard PC/104 I/O

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Page 17

Layout and Pin Reference:

J2

D0 C0

J3

A1 B1

PPM-C407/Configuration v1.0

D19 D20

A32 B32

Pin Name Pin Name Pin Name Pin Name

D4

D5

D6

D7

D0

D1

D2

D3

D8

D9

D10

D11

DACK0#

DRQ0

DACK5#

DRQ5

D12

D13

DACK6#

DRQ6

D14) DACK7#

D15 DRQ7

GND

MEMCS16#

IOCS16#

IRQ10

IRQ11

IRQ12

IRQ15

IRQ14

C0 GND

C1 SBHE#

C2 LA23

C3 LA22

C4 LA21

C5 LA20

C6 LA19

C7 LA18

C8 LA17

C9 MEMR#

C10 MEMW#

C11 SD8

C12 SB9

C13 SD10

C14 SD11

C15 SD12

A13

A14

A15

A16

A9

A10

A11

A12

A5

A6

A7

A8

A1

A2

A3

A4

SD4

SD3

SD2

SD1

IOCHK#

SD7

SD6

SD5

SD0

IOCHRDY

AEN

SA19

SA18

SA17

SA16

SA15

B1 GND

B2 RESET

B3 +5V

B4 IRQ

B5 -5V

B6 DRQ2

B7 -12V

B8 SRDY#

B9 +12V

B10 GND

B11 SMEMW#

B12 SMEMR#

B13 IOW#

B14 IOR#

B15 DACK3#

B16 DRQ3

D16 +5V C16 SD13 A17 SA14 B17 DACK1#

D17

D18

D19

MASTER#

GND

GND

C17 SD14

C18 SD15

C19 GND

A18

A19

A20

A22

A23

A24

A25

A26

A27

SA13

SA12

SA11

SA9

SA8

SA7

SA6

SA5

SA4

B18 DRQ1

B19 REFRESH#

B20 BCLK

PRELIMINARY

#: Active Low Signal

B10 and C19 are key locations. WinSystems uses key

A21 SA10 B21 IRQ7

B22 IRQ6

B23 IRQ5

B24 IRQ4

B25 IRQ3

B26 DACK2#

B27 TC pins as connections to GND.

A28 SA3 B28 BALE

A29

A30

A31

A32

SA2

SA1

SA0

GND

B29 +5V

B30 OSC

B31 GND

B32 GND

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Page 18

v1.0

PPM-C407/Configuration

Additional Information

This connection uses different on-board connectors for stack-through or non-stackthrough models:

J2 (40-pin) Connector

• Teka PC220-W1BD-M (non-stack-through, solder bearing)

• Teka PC220-W1A7-M (stack-through, solder bearing)

J3 (64-pin) Connector

• Teka PC232-W1BD-M (non-stack-through, solder bearing)

• Teka PC232-W1A7-M (stack-through, solder bearing)

No keys in connector and no cut pins.

7.8.3 J4 External Battery Connector

An optional external battery, connected to J4, supplies the PPM-C407 board with standby power for the real-time clock and CMOS setup RAM. An extended temperature lithium battery is available from WinSystems, part number:

• BAT-LTC-E-36-16-2

• BAT-LTC-E-36-27-2

A power supervisory circuit contains the voltage sensing circuit and an internal power switch to route the battery or standby voltage to the circuits selected for backup. The battery automatically switches ON when the VCC of the systems drops below the battery voltage and back OFF again when VCC returns to normal.

Layout and Pin Reference:

1

3

Pin

1

2

3

Name

GND

BAT+

NC

This connection uses MOLEX part number 501953-0307 (WinSystems part number:

G650-2003-7FB).

Matching connector:

• MOLEX part number: 501939-0300

• MOLEX Crimp Terminal: 501334

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Page 19

PPM-C407/Configuration

WinSystems battery BAT-LTC-E-36-16-2 and BAT-LTC-E-36-27-2 (connected to J3) simplify these connections to the board.

BAT-LTC-E-36-16-2 BAT-LTC-E-36-27-2 v1.0

7.8.4 J5 LVDS and Audio Connector

NOTE The PPM-C407 has one VGA, one DisplayPort and one Low-Voltage Differential

Signaling (LVDS) interface. Only two of the three outputs may be active simultaneously.

The LVDS portion of this connector can be configured (see “JP4 Low-Voltage

Differential Signaling (LVDS)” on page 34). Use the LVDS portion to connect to the

LVDS interface (includes pins 1 through 21, non-shaded in the following table).

Use the audio portion to connect to the Audio interface (pins 22 through 30, shaded in the following table).

Layout and Pin Reference:

Pin

1

3

5

Name

LVDS_VCC (LVDS)

D0- (LVDS)

D1- (LVDS)

Pin

2

4

6

Name

GND (LVDS)

D0+ (LVDS)

D1+ (LVDS)

1 2

29 30

13 LVDS_VCC (LVDS)

15 CLK- (LVDS)

17 DDC_CLK (LVDS)

19 DDC_DATA (LVDS)

21 GND (LVDS)

23 OUT_R (AUDIO)

25 OUT_L (AUDIO)

27 ANALOG_GND (AUDIO)

14

16

18

20

22

24

26

28

GND (LVDS)

CLK+ (LVDS)

GND (LVDS)

GND (LVDS)

ANALOG_GND (AUDIO)

MIC_R (AUDIO)

MIC_L (AUDIO)

ANALOG_GND (AUDIO)

29 LINE_R (AUDIO) 30 LINE_L (AUDIO)

Non-shaded cells designate LVDS interface.

Shaded cells designate Audio Interface.

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Page 20

PPM-C407/Configuration

Additional Information

The LVDS interface terminates at a portion of a Molex 501571-3007, 2x15, 1 mm pitch

(Pico-Clasp™) right angle locking header connector (WS G650-2030-7HB) shared with the Audio interface.

Matching connectors:

• LVDS: Molex 501189-3010 housing with Molex 501193-2000 crimp pins.

• Backlight: Molex 501330-1100 with Molex 501334-0000 crimp pins.

• WinSystems cables simplify connections to the board:

– CBL-LVDSAB-005-12: LVDS/Audio & Bklt to 7" Ampire with Audio Jacks

– CBL-LVDSB-006-12: LVDS & Bklt to 7" Ampire without Audio

– CBL-LVDSA-007-12: LVDS/Audio to 12" Mitsubishi with Audio Jacks

– CBL-LVDSA-008-12: LVDS to 12" Mitsubishi without Audio

– CBL-LVDSAB-003-12: LVDS/Audio & Bklt to 6.5" AUO with Audio Jacks

– CBL-SPL-001-14: LVDS/Audio to unterminated LVDS with Audio Jacks

(shown)

v1.0

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PPM-C407/Configuration

7.8.5 J6 Mini DisplayPort

NOTE The PPM-C407 has one VGA, one DisplayPort and one Low-Voltage Differential

Signaling (LVDS) interface. Only two of the three outputs may be active simultaneously.

Layout and Pin Reference:

1

19

2

20

PIN NAME DESCRIPTION PIN NAME DESCRIPTION

1 GND Ground

3 ML_Lane 0 (p) Lane 0 (positive)

5 ML_Lane 0 (n) Lane 0 (negative)

7 GND Ground

9 ML_Lane 1 (p) Lane 1 (positive)

11 ML_Lane 1 (n) Lane 1 (negative)

13 GND Ground

15 ML_Lane 2 (p) Lane 2 (positive)

17 ML_Lane 2 (n) Lane 2 (negative)

19 GND Ground

2 Hot Plug Detect Hot Plug Detect

4 CONFIG1 CONFIG1

6 CONFIG2

8 GND

CONFIG2

Ground

10 ML_Lane 3 (p) Lane 3 (positive)

12 ML_Lane 3 (n) Lane 3 (negative)

14 GND Ground

16 AUX_CH (p)

18

20

AUX_CH (n)

DP_PWR

Auxiliary Channel

(positive)

Auxiliary Channel

(negative)

Power for connector

7.8.6 J7 VGA

NOTE The PPM-C407 has one VGA, one DisplayPort and one Low-Voltage Differential

Signaling (LVDS) interface. Only two of the three outputs may be active simultaneously.

Layout and Pin Reference:

14

1

Pin Name Description

1 VGA_RED CRT red signal input

2 GND GND

3

4

5

6

VGA_GREEN

GND

VGA_BLUE

GND

CRT green signal input

GND

CRT blue signal input

GND

7 VGA_HSYNC CRT Horizontal Synchronization

8

9

GND

VGA_VSYNC

10 GND

11 DDC_SDA

12 GND

13 DDC_SCL

14 VCC

GND

CRT Vertical Synchronization

GND

CRT DDC Data

GND

CRT DDC clock

5V input for CRT

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v1.0

PPM-C407/Configuration

Additional Information

The VGA interface terminates with a Molex 501568-1407, 1x14, 1 mm pitch (Pico-

Clasp™) right angle locking header connector (WS G650-2014-7FB).

Matching connector: Molex 501330-1400 housing with Molex 501334-0000 crimp pins.

WinSystems cable CBL-VGA-002-12 (Pico-Clasp to DB-15) simplifies this connection to the board.

7.8.7 J8 USB

The PPM-C407 provides four USB2.0 ports with Littlefuse PGB1010603MR (WS G607-

0013-004) ESD surge protection and Murata DLW21HN900SQ2L common mode noise suppressors (WS G605-1014-000). The TI TPS2505B1RGWR (WS G673-0025-131)

USB power switch is used to enhance the stability of powering USB devices.

Layout and Pin Reference:

19

20

1

2

Pin

11

13

7

9

1

3

5

15

17

19

Name

USB1V

USB1_N

USB1_P

GND

GND

GND

USB3V

USB3_N

USB3_P

GND

Pin

8

10

12

14

2

4

6

16

18

20

Name

USB2V

USB2_N

USB2_P

GND

GND

GND

USB4V

USB4_N

USB4_P

GND

The four ports terminate at a Molex 501571-2007, 2x10, 1 mm pitch (Pico-Clasp™) right angle locking header connector (WS G650-2020-7HB).

PRELIMINARY

• CBL-USB4-001-12: Pico-Clasp to Pico-Clasp

• CBL-USB4-002-12: Pico-Clasp to 2each, 2x4, 2 mm pitch housing (shown)

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PPM-C407/Configuration v1.0

7.8.8 J9 Serial Ports

The PPM-C407 provides four serial ports through the Lattice MachX02 FPGA interfaced to the processor with the Low Pin Count (LPC) interface. Two serial ports support

RS232, RS422 and RS485 protocols (using the Exar SP339E multi-protocol transceiver). The other two ports support RS232 (only) using the Maxim MAX3241E transceiver.

Layout and Pin Reference:

1

39

2

40

Pin Name Pin Name

9

11

13

15

5

7

1

3

DCD1

RXD1

TXD1

DTR1

GND

DCD2

RXD2

TXD2

10

12

14

16

6

8

2

4

33

35

37

39

17

19

DTR2

GND

18

20

RI2

GND

21

23

25

27

29

DCD3

RXD3

TXD3

DTR3

GND

22

24

26

28

30

DSR3

RTS3

CTS3

RI3

GND

31 DCD4 32 DSR4

RXD4

TXD4

DTR4

GND

34

36

38

40

RTS4

CTS4

RI4

GND

DSR1

RTS1

CTS1

RI1

GND

DSR2

RTS2

CTS2

Four independent, asynchronous serial channels are on-board. All serial ports are configured as Data Terminal Equipment (DTE). Both the send and receive registers of each port have a 16-byte FIFO. All serial ports have 16C550-compatible UARTs. The

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Page 24

PPM-C407/Configuration

RS-232 transceivers have charge pumps to generate the plus and minus voltages so the

PPM-C407 only requires +5 V to operate. Each port is set up to provide internal diagnostics such as loopback and echo mode on the data stream. An independent, software programmable baud rate generator is selectable from 50 through 115.2 kbps.

Individual modem handshake control signals are supported for all ports.

RS-232 interface levels are supported on all four serial ports which can be enabled in the BIOS. COM3 and COM4 also have RS-422/RS-485 support.

COM1, COM2, COM3, COM4 (DB-9 Male and Female)

5

MALE FEMALE

1

1

5

6

9

9

6

Pin RS-232 RS-422 RS-485

1 DCD

2 RX

3 TX

4 DTR

5 GND

6 DSR

7 RTS

8 CTR

9 RI

N/A

TX+

RX+

N/A

GND

TX-

RX-

N/A

N/A

N/A

TX/RX+

N/A

N/A

GND

TX/RX-

N/A

N/A

N/A

v1.0

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PPM-C407/Configuration

Matching connection: Molex 503110-4000 housing with Molex 501930-1100 crimp pins. WinSystems cables simplify connections to the board:

• CBL-SER4-000-14: Duo-Clasp to unterminated

• CBL-SER4-001-12: Duo-Clasp to Duo-Clasp

• CBL-SER4-002-12: Duo-Clasp to 4xDB9 (shown)

v1.0

7.8.9 J11 Ethernet External LEDs

On-board Ethernet activity signals are provided at this connector. These activity signals are also available off-board for enclosures or other applications that have remote mounting requirements. Each external LED signal has an on-board 200

 resistor (in series).

Layout and Pin Reference:

Pin

1

4

1

2

3

4

Name

EXT_LED0

EXT_LED1

EXT_LED2

V3P3A

Descrption

External LED 0

External LED 1

External LED 2

+3.3V Power

Clasp™) right angle locking header connector (WS G650-2004-7FB).

Matching connection: Molex 501939-0400 housing with Molex 501334-0000 crimp pins. WinSystems cables simplify connections to the board:

• CBL-LED3-000-14A: Pico-Clasp to unterminated (shown)

• CBL-LED3-001-12B: Pico-Clasp to Pico-Clasp

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v1.0

PPM-C407/Configuration

7.8.10 J12 PC/104-Plus (PCI bus)

The PC/104-Plus is electrically equivalent to the 33 MHz PCI bus. Interface is PC/104-

Plus version 2.0 compliant.

Layout and Pin Reference:

D1 D30

A1 A30

Pin A B C

12

13

14

15

10

11

8

9

6

7

4

5

1

2

3

GND

VI/O

AD05

C/BE0#

GND

AD11

AD14

+3.3V

SERR#

GND

STOP#

+3.3V

FRAME#

GND

AD18

C/BE1#

GND

PERR#

+3.3V

TRDY#

GND

AD16

+3.3V

RESERVED

AD02

GND

AD007

AD009

VI/O

AD13

+5V

AD01

AD04

GND

AD08

AD10

GND

AD15

RESERVED

+3.3V

LOCK#

GND

IRDY#

+3.3V

AD17

26

27

28

29

16

17

18

19

AD21

+3.3V

IDSEL0

AD24

AD20

AD23

GND

C/BE3#

GND

AD22

IDSEL1

VI/O

AD19

+3.3V

IDSEL2

IDSEL3

20

21

GND

AD29

AD26

+5V

AD25

AD28

GND

AD27

22

23

24

25

+5V

REQ0#

GND

GNT1#

AD30

GND

REQ2#

VI/O

GND

REQ1#

+5V

GNT2#

AD31

VI/O

GNT0#

GND

+5V

CLK2

GND

+12V

30 -12V

# = Active Low Signal

Shaded cells indicate power pins.

CLK0

+5V

INTD#

INTA#

REQ3#

GND

CLK3

+5V

INTB#

GNT3#

CLK1

GND

RST#

INTC#

GND

AD00

+5V

AD03

AD06

GND

M66EN

AD12

+3.3V

PAR

RESERVED

GND

DEVSEL#

+3.3V

C/BE2#

GND

D www.winsystems.com

Page 27

v1.0

PPM-C407/Configuration

Additional Information

No keys in connector and no cut pins. This connection uses different connectors for stack-through or non-stack-through models:

120 Pin Connector:

• Teka 2MR430-BDWM-368-00 (non-stack-through, solder bearing),

WS G650-0120-0BA

• Teka 2MR430-A7WM-368-0 (stack-through, solder bearing), WS G650-0120-09A

7.8.11 J500 Backlight

Layout and Pin Reference:

1

8

Pin

7

8

5

6

3

4

1

2

Name

V5

BKLT_EN_N

BKLT_EN

GND

V12+

BKLT_PWM

V3P3S

V5

Description

+5V Power

Backlight Enable -

Backlight Enable +

Ground

+12V Power

Backlight PWM Brightness Control

+3.3V Power

+5V Power

The backlight interface terminates at a Molex 501568-0807, 1x8, 1 mm pitch (Pico-

Clasp™) vertical locking header connector (WS G650-2008-6F0).

Matching connector: Molex 501330-1100 with Molex 501334-0000 crimp pins.

• CBL-LVDSB-006-12: LVDS & Backlight to 7" Ampire without Audio

• CBL-LVDSAB-003-12: LVDS/Audio & Backlight to 6.5" AUO with Audio Jacks

www.winsystems.com

Page 28

v1.0

PPM-C407/Configuration

7.8.12 J501 Mini-PCIe/mSATA Connector

The PPM-C407 provides a mini-PCIe socket to support a variety of peripherals as available in this format. The socket alternatively supports a mSATA device in this socket. A sense circuit identifies the type of device present in the socket and autoswitches to handle either type.

Layout and Pin Reference:

Pin Name Pin Name

23

25

27

29

15

17

19

21

11

13

7

9

1

3

5

WAKE#

COEX1

COEX2

CLKREQ#

GND

REFCLK-

REFCLK+

GND

RSVD(UIM_C8)

RSVD(UIM_C4)

GND

PERn0

PERp0

GND

GND

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

31

33

35

37

PERn0

PERp0

GND

GND

32

34

36

38

SMB_DATA

GND

USB_D-

USB_D+

39

41

43

45

47

3.3Vaux

3.3Vaux

GND

RSVD

RSVD

40

42

44

46

48

GND

LED_WWAN#

LED_WLAN#

LED_WPAN#

1.5V

49 RSVD 50 GND

51 MSATA DET

Shaded cells indicate unconnected signals.

52 3.3Vaux

3.3Vaux

GND

1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RST

UIM_VPP

GND

W_DISABLE#

PERST#

3.3Vaux

GND

1.5V

SMB_CLK

www.winsystems.com

Page 29

To install a miniPCIe/mSATA into J501:

1. Insert the miniPCIe/mSATA

PPM-C407/Configuration

2. Push the free end of the card toward the circuit board and then secure it with two (2 mm) screws (WinSystems P/N: G527-0000-400).

v1.0

PRELIMINARY www.winsystems.com

Page 30

PPM-C407/Configuration

7.8.13 J503 Serial ATA (SATA)

The PPM-C407 provides a SATA interface to support connection of a variety of SATA devices.

Layout and Pin Reference:

1

7

Pin

5

6

7

3

4

1

2

GND

A+

A-

GND

B-

B+

GND

Name

The SATA interface terminates at an industry standard 7-pin, right angle SATA connector Molex 47080-4005 (WS G650-7007-600). WinSystems cable

CBL-SATA-701-20 simplifies connection to the board.

v1.0

PRELIMINARY www.winsystems.com

Page 31

v1.0

PPM-C407/Configuration

7.8.14 J504 Digital Input/Output

The PPM-C407 supports 24 lines of digital input/output (DIO) via the Lattice MachX02

FPGA interfaced to the processor with the Low Pin Count (LPC) interface. These lines maintain the WinSystems standard DIO register definition and by using the TI

TXS0108E level converters, all signals are 5 V tolerant.

Layout and Pin Reference:

1

49

2

50

Pin

26

28

30

32

18

20

22

24

10

12

14

16

6

8

2

4

42

44

46

48

50

34

36

38

40

Name

Port 2 Bit 7

Port 2 Bit 6

Port 2 Bit 5

Port 2 Bit 4

Port 2 Bit 3

Port 2 Bit 2

Port 2 Bit 1

Port 2 Bit 0

Port 1 Bit 7

Port 1 Bit 6

Port 1 Bit 5

Port 1 Bit 4

Port 1 Bit 3

Port 1 Bit 2

Port 1 Bit 1

Port 1 Bit 0

Port 0 Bit 7

Port 0 Bit 6

Port 0 Bit 5

Port 0 Bit 4

Port 0 Bit 3

Port 0 Bit 2

Port 0 Bit 1

Port 0 Bit 0

+5 V

Pin

25

27

29

31

17

19

21

23

9

11

13

15

5

7

1

3

41

43

45

47

49

33

35

37

39

The I/O is terminated at a Molex 501571-5007, 2x25, 1 mm pitch (Pico-Clasp™) right

PRELIMINARY

• CBL-DIO24-000-14: Pico-Clasp to unterminated

• CBL-DIO24-001-12: Pico-Clasp to Pico-Clasp

• CBL-DIO24-002-12: Pico-Clasp to 2x25, 0.1" pitch housing

Name

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

www.winsystems.com

Page 32

v1.0

PPM-C407/Configuration

7.8.15 J505 Ethernet

The PPM-C407 has an Intel

® i210 single chip 1 Gb/s Ethernet Controller that includes full magnetics (Bothhand GST5009) and surge suppression.

Layout and Pin Reference:

1

9

2

10

Pin

1

3

5

7

9

Name

MX0_P

MX1_P

MX2_P

MX3_P

NC

Pin

2

4

6

8

10

Name

MX0_N

MX1_N

MX2_N

MX3_N

NC

The Ethernet connection is a Samtec TFM-105-02-L-DH, 2x5, 0.05" pitch locking header connector (WS G650-2010-5H0A).

Matching connector: Samtec ISDF-05-D-M housing with Samtec CC03L-2830-01-G crimp pins. WinSystems cables simplify connection to the board:

• CBL-ENET1-302-12: RJ45 Jack (shown)

• CBL-ENET1-303-12: RJ45 Plug

7.9

Jumpers

Jumper Part Number SAMTEC 2SN-BK-G applies to all jumpers. These are available in a ten piece kit from WinSystems (Part# KIT-JMP-G-200).

7.9.1 JP1 AT/ATX Power Mode

The presence of a jumper at JP1 specifies the style of supply connected to the single

board computer (see “J1 Power Connector” on page 16). AT Power is a simple on/off

power supply with no interaction with the single board computer. Most embedded

PRELIMINARY

Jumper AT / ATX Mode Select

1-2 Jumper Installed: AT Mode (Default)

1 2

Open Open (no jumper installed): ATX Mode

www.winsystems.com

Page 33

v1.0

PPM-C407/Configuration

7.9.2 JP3 Basic Input/Output System (BIOS) Programming Defaults

If you have saved EEPROM values that prevent you from accessing BIOS menus, the board can be reset to factory defaults as follows:

1. Turn the system off.

2. Install the jumper at JP3.

3. Turn the system on and enter the BIOS Main Menu using the F2 key. Factory defaults will be loaded at this point.

4. Remove the jumper on JP3.

5. Select Exit Saving Changes from the Exit Menu.

Jumper Pin Reference

:

1 2

Jumper

1-2

Open

Defaults Mode

Jumper Installed: Boot using BIOS defaults

Open (no jumper installed): Boot using presently saved BIOS settings

7.9.3 JP4 Low-Voltage Differential Signaling (LVDS)

The presence and position of a jumper at JP4 configures the J5 connector (see “J5

LVDS and Audio Connector” on page 20) for the Video Electronics Standards

Association (VESA) or the Japan Electronic Industry Development Association (JEIDA) standard, and bits-per-pixel (bpp).

1 2 3

Jumper

1-2

2-3

Open

LVDS setting

18-bpp VESA or JEIDA (default)

24-bpp VESA

24-bpp JEIDA

PRELIMINARY www.winsystems.com

Page 34

v1.0

PPM-C407/Configuration

7.10 LED Indicators

D7

D7

D9

D10

D504

LED Description

Indicates when an Ethernet activity occurs

Indicates when the board is in stand-by power states (S3, S4, or S5)

Indicates when the board is in the run power state

(S0) and all power supplies are good

Indicates when a user defined event occurs. For

location and details, see “D504 User LED” on page 35.

D10

D9

7.10.1 D504 User LED

A user LED (D504) can be used for any application specific purpose. The LED can be turned on in software applications by writing a 1 to I/O port 29DH. The LED can be turned off by writing a 0 to 29DH.

D504

PRELIMINARY www.winsystems.com

Page 35

v1.0

PPM-C407/BIOS

8.

BIOS

8.1

General Information

The PPM-C407 includes a BIOS from Phoenix Technologies to assure full compatibility with PC operating systems and software. The basic system configuration is stored in battery backed CMOS RAM within the clock/calendar. As an alternative, the CMOS configuration may be stored in EEPROM for operation without a battery. For more information of CMOS configuration, see the BIOS Settings Storage Options section of this manual. Access to this setup information is via the Setup Utility in the BIOS.

8.2

Entering Setup

To enter setup, power up the computer and press F2 when either the splash screen is displayed or when the Press F2 for Setup message is displayed. It may take a few seconds before the main setup menu screen is displayed.

8.3

Navigation of the Menus

Use the Up and Down arrow keys to move among the selections and press Enter when a

selection is highlighted to enter a sub-menu or to see a list of choices. See “BIOS

Screens” on page 37 for available options.

8.4

BIOS Splash Screen

Custom BIOS Splash Screens can be accommodated for OEM customers. Please contact one of our Application Engineers for details.

PRELIMINARY www.winsystems.com

Page 36

PPM-C407/BIOS

8.5

BIOS Screens

The following BIOS screens contain the options and sample settings for the PPM-C407.

Your actual configuration may differ from the screens shown here. Use care when modifying BIOS settings.

Main v1.0

PRELIMINARY www.winsystems.com

Page 37

Main: System Information

PPM-C407/BIOS

Main: Boot Features v1.0

PRELIMINARY www.winsystems.com

Page 38

PPM-C407/BIOS

Main: Error Manager

Advanced v1.0

PRELIMINARY www.winsystems.com

Page 39

Advanced: CPU Configuration

PPM-C407/BIOS

Advanced: CPU Configuration: CPU Power Management v1.0

PRELIMINARY www.winsystems.com

Page 40

Advanced: Uncore Configuration

PPM-C407/BIOS

Advanced: System Component v1.0

PRELIMINARY www.winsystems.com

Page 41

Advanced: Super I/O Configuration

PPM-C407/BIOS

Advanced: South Cluster Configuration v1.0

PRELIMINARY www.winsystems.com

Page 42

Advanced: South Cluster Configuration: PCI Express Configuration

PPM-C407/BIOS

Advanced: South Cluster Configuration: USB configuration v1.0

PRELIMINARY www.winsystems.com

Page 43

Advanced: South Cluster Configuration: Audio Configuration

PPM-C407/BIOS

Advanced: South Cluster Configuration: SATA Drives v1.0

PRELIMINARY www.winsystems.com

Page 44

Advanced: South Cluster Configuration: LPSS & SCC Configuration

PPM-C407/BIOS

Advanced: South Cluster Configuration: Miscellaneous Configuration v1.0

PRELIMINARY www.winsystems.com

Page 45

Advanced: Security Configuration

PPM-C407/BIOS

Advanced: Power Management v1.0

PRELIMINARY www.winsystems.com

Page 46

Advanced: Thermal Configuration

PPM-C407/BIOS

Advanced: SMBIOS Event Log v1.0

PRELIMINARY www.winsystems.com

Page 47

Advanced: SMBIOS Event Log: View SMBIOS event log

PPM-C407/BIOS

Advanced: Memory ECC Error Logging v1.0

PRELIMINARY www.winsystems.com

Page 48

PPM-C407/BIOS

Security

Boot v1.0

PRELIMINARY www.winsystems.com

Page 49

Exit

PPM-C407/BIOS v1.0

PRELIMINARY www.winsystems.com

Page 50

v1.0

PPM-C407/Cables

9.

Cables

WinSystems cables and batteries simplify connection to the PPM-C407. The following table lists available items.

Item Part Number

CBL-PWR-700-18

CBL-LVDSAB-005-12

CBL-LVDSB-006-12

CBL-LVDSA-007-12

CBL-LVDSA-008-12

CBL-LVDSAB-003-12

CBL-SPL-001-14

CBL-VGA-002-12

CBL-USB4-000-14:

Connection

See “J1 Power Connector” on page 16.

See “J5 LVDS and Audio

Connector” on page 20.

See “J7 VGA” on page 22.

CBL-USB4-001-12:

See “J8 USB” on page 23.

Description

Power connection

LVDS/Audio and Backlight to 7" Ampire with Audio Jacks

LVDS and Backlight to 7" Ampire without

Audio

LVDS/Audio to 12" Mitsubishi with Audio

Jacks

LVDS to 12" Mitsubishi without Audio

LVDS/Audio & Bklt to 6.5" AUO with Audio

Jacks

LVDS/Audio to unterminated LVDS with

Audio Jacks

Pico-Clasp to unterminated

Pico-Clasp to Pico-Clasp

Cables

Batteries

CBL-USB4-002-12 Pico-Clasp to 2each, 2x4, 2 mm pitch housing

Duo-Clasp to unterminated CBL-SER4-000-14

CBL-SER4-001-12

CBL-SER4-002-12

CBL-LED3-000-14A

CBL-LED3-001-12B

See “J9 Serial Ports” on page 24.

See “J11 Ethernet External LEDs” on page 26.

Duo-Clasp to Duo-Clasp

Duo-Clasp to 4xDB9.

Pico-Clasp to unterminated

Pico-Clasp to Pico-Clasp

CBL-LVDSAB-005-12 LVDS/Audio and Backlight to 7" Ampire with Audio Jacks

See “J500 Backlight” on page 28.

LVDS and Backlight to 7" Ampire without

Audio

CBL-LVDSB-006-12

CBL-LVDSAB-003-12

CBL-SATA-701-20

CBL-DIO24-000-14

See “J503 Serial ATA (SATA)” on page 31.

LVDS/Audio and Backlight to 6.5" AUO with Audio Jacks

SATA interface

Pico-Clasp to unterminated

See “J504 Digital Input/Output”

CBL-DIO24-001-12 Pico-Clasp to Pico-Clasp

on page 32.

CBL-DIO24-002-12 Pico-Clasp to 2x25, 0.1" pitch housing

CBL-ENET1-302-12

CBL-ENET1-303-12

BAT-LTC-E-36-16-2

BAT-LTC-E-36-27-2

See “J505 Ethernet” on page 33.

See “J4 External Battery

Connector” on page 19.

RJ45 Jack

RJ45 Plug

External 3.6V, 1650 mAH battery with plug-in connector

External 3.6V, 2700 mAH battery with plug-in connector

www.winsystems.com

Page 51

PPM-C407/Software Drivers

10. Software Drivers

Go to www.winsystems.com

for information on available software drivers.

v1.0

PRELIMINARY www.winsystems.com

Page 52

v1.0

PPM-C407/Best Practices

Appendix A. Best Practices

The following paragraphs outline the best practices for operating the PPM-C407 in a safe, effective manner, that will not damage the board. Please read this section carefully.

Power Supply

Avoid Electrostatic Discharge (ESD)—Only handle the circuit board and other bare electronics when electrostatic discharge (ESD) protection is in place. Having a wrist strap and a fully grounded workstation is the minimum ESD protection required before the ESD seal on the product bag is broken.

Power Supply Budget

Evaluate your power supply budget. It is usually good practice to budget twice the typical power requirement for all of your devices.

Zero-Load Power Supply

Use a zero-load power supply whenever possible. A zero-load power supply does not require a minimum power load to regulate. If a zero-load power supply is not appropriate for your application, then verify that the single board computer’s typical load is not lower than the power supply’s minimum load. If the single board computer does not draw enough power to meet the power supply’s minimum load, then the power supply will not regulate properly and can cause damage to the PPM-C407.

Use Proper Power Connections (Voltage)—When verifying the voltage, measure it at the power connector on the PPM-C407. Measuring it at the power supply does not account for voltage drop through the wire and connectors.

The PPM-C407 requires +5V (±5%) to operate. Verify the power connections.

Incorrect voltages can cause catastrophic damage.

Populate all of the +5V and ground connections. Most single board computers will have multiple power and ground pins, and all of them should be populated. The more copper connecting the power supply to the PPM-C407 the better.

If you have a power supply that allows you to adjust the voltage, it is a good idea to set the voltage at the power connector of the PPM-C407 to 5.1 V. The PPM-C407 can tolerate up to 5.25 V, so setting your power supply to provide 5.1 V is safe and allows for a small amount of voltage drop that will occur over time as the power supply ages and the connector contacts oxidize.

Power Harness

Minimize the length of the power harness. This will reduce the amount of voltage drop between the power supply and the PPM-C407.

www.winsystems.com

Page 53

v1.0

PPM-C407/Best Practices

Gauge Wire

Use the largest gauge wire that you can. Most connector manufacturers have a maximum gauge wire they recommend for their pins. Try going one size larger; it usually works and the extra copper will help your system perform properly over time.

Contact Points

WinSystems’ boards mostly use connectors with gold finish contacts. Gold finish contacts are used exclusively on high speed connections. Power and lower speed peripheral connectors may use a tin finish as an alternative contact surface. It is critical that the contact material in the mating connectors is matched properly (gold to gold and tin to tin). Contact areas made with dissimilar metals can cause oxidation/corrosion resulting in unreliable connections.

Pin Contacts

Often the pin contacts used in cabling are not given enough attention. The ideal choice for a pin contact would include a design similar to Molex’s or Trifurcon’s design, which provides three distinct points to maximize the contact area and improve connection integrity in high shock and vibration applications.

Power Down

Make sure that power has been removed from the system before making or breaking any connections.

Power Supply OFF—The power supply should always be off before it is connected to the I/O Module. Do not hot-plug the PPM-C407 on a host platform that is already powered.

I/O Connections OFF—I/O Connections should also be off before connecting them to the embedded computer modules or any I/O cards. Connecting hot signals can cause damage whether the embedded system is powered or not.

• KIT-PCM-STANDOFF-B-4: Four piece Brass Hex PC/104 Standoff Kit

www.winsystems.com

Page 54

v1.0

PPM-C407/Best Practices

The following table lists the items contained in each kit:

KIT-PCM-STANDOFF-4

4 pc. Nylon Hex PC/104

Standoff Kit

Kit

KIT-PCM-STANDOFF-B-4

4 pc.Brass Hex PC/104

Standoff Kit

Component

Standoff

Hex Nut

Screw

Standoff

Hex Nut

Screw

Description

Nylon 0.25” Hex, 0.600" Long

Male/Female 4-40

Hex Nylon 4-40

Phillips-Pan Head (PPH)

4-40 x 1/4" Stainless Steel

Brass 5 mm Hex, 0.600" Long

Male/Female 4-40

4

4

4-40 x 0.095 Thick, Nickel Finish 4

Phillips-Pan Head (PPH)

4-40 x 1/4" Stainless Steel

4

4

4

Qty

Placing the PPM-C407 on Mounting Standoffs—Be careful when placing the PPM-

C407 on the mounting standoffs. Sliding the board around until the standoffs are visible from the top can cause component damage on the bottom of the board.

Do Not Bend or Flex the PPM-C407—Bending or flexing can cause irreparable damage.

Embedded computer modules are especially sensitive to flexing or bending around Ball

Grid Array (BGA) devices. BGA devices are extremely rigid by design and flexing or bending the embedded computer module can cause the BGA to tear away from the printed circuit board.

Mounting Holes—The mounting holes are plated on the top, bottom and through the barrel of the hole and are connected to the embedded computer module’s ground plane.

Traces are often routed in the inner layers right below, above or around the mounting holes.

• Never use a drill or any other tool in an attempt to make the holes larger.

• Never use screws with oversized heads. The head could come in contact with

• nearby components causing a short or physical damage.

• Never use self-tapping screws; they will compromise the walls of the mounting hole.

• Always use all of the mounting holes. By using all of the mounting holes you will provide the support the embedded computer module needs to prevent bending or flexing.

Plug or Unplug Connectors Only on Fully Mounted Boards—Never plug or unplug connectors on a board that is not fully mounted. Many of the connectors fit rather tightly and the force needed to plug or unplug them could cause the embedded computer module to be flexed.

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Page 55

v1.0

PPM-C407/Best Practices

Avoid Cutting the PPM-C407—Never use star washers or any fastening hardware that will cut into the PPM-C407.

Avoid Over-tightening of Mounting Hardware—Causing the area around the mounting holes to compress could damage interlayer traces around the mounting holes.

Use Appropriate Tools—Always use tools that are appropriate for working with small hardware. Large tools can damage components around the mounting holes.

Avoid Conductive Surfaces—Never allow the embedded computer module to be placed on a conductive surface. Many embedded systems use a battery to back up the clockcalendar and CMOS memory. A conductive surface such as a metal bench can short the battery causing premature failure.

Adding PC/104 Boards to your Stack

Be careful when adding PC/104 boards to your stack—Never allow the power to be turned on when a PC/104 board has been improperly plugged onto the stack. It is possible to misalign the PC/104 card and leave a row of pins on the end or down the long side hanging out of the connector. If power is applied with these pins misaligned, it will cause the I/O board to be damaged beyond repair.

Conformal Coating

Applying conformal coating to a WinSystems product will not in itself void the product warranty, if it is properly removed prior to return. Coating may change thermal characteristics and impedes our ability to test, diagnose, and repair products. Any coated product sent to WinSystems for repair will be returned at customer expense and no service will be performed.

Every single board computer has an Operations manual or Product manual.

Periodic Updates—Operations/Product manuals are updated often. Periodically check the WinSystems website (http://www.winsystems.com) for revisions.

Check Pinouts—Always check the pinout and connector locations in the manual before plugging in a cable. Many I/O modules will have identical headers for different functions and plugging a cable into the wrong header can have disastrous results.

www.winsystems.com

Page 56

PPM-C407/Mechanical Drawings

Contact an Applications Engineer—If a diagram or chart in a manual does not seem to match your board, or if you have additional questions, contact a WinSystems

Applications Engineer at: +1-817-274-7553.

Appendix B. Mechanical Drawings

PC/104-Plus SBC E38XX without heatsink

v1.0

95.89 mm

90.81 mm

87.63 mm

72.94 mm

M4-0.7 x 6 mm

(4X)

#4-40 x .250 mm

(3X)

27.28 mm

22.94 mm

8.26 mm

5.08 mm

0 mm

6.32 mm

Ø

3.18 mm

(4X)

PRELIMINARY

MAX

10.16 mm

www.winsystems.com

Page 57

v1.0

PC/104-Plus SBC E38XX with heatsink

95.89 mm

90.81 mm

87.63 mm

PPM-C407/Mechanical Drawings

Ø

3.18 mm

(4X)

8.26 mm

5.08 mm

0 mm

30.00 mm

11.05 mm

0 mm

1.98 mm

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Page 58

v1.0

PPM-C407/Power-on Self-Test (POST) Codes

Appendix C. Power-on Self-Test (POST) Codes

If the system hangs before the BIOS can process the error, the value displayed at the

I/O port address 80h is the code of the last successful operation. In this case, the screen does not display an error code.

Basic POST Codes

The following is a list of the checkpoint codes written at the start of each test and their corresponding audio beep codes issued for terminal errors.

Table C–1: Basic Post Codes

Code Symbol Description

20

21

22

ACPI_SMI

ACPI_SUPPORT

ACPI_TABLE

23 ACPI_TABLEHOLDER

24 AHCI_ASPI

25 AHCI_BUS

26 AHCI_PASS_THRU

27

28

29

2A

BLOCK_IO_THUNK

BOOT_MANAGER

BOOT_MENU

BOOT_MODE

SCT ACPI SMI Services DXE driver

ACPI table manipulating driver

Generic ACPI table support, Simple Boot Flag, various ACPI table producers

ACPI table loader initialization and protocols

AHCI ASPI Legacy SMM driver

AHCI UEFI driver

Driver sending ATA commands to AHCI controller

EFI glue for BIOS INT13h HDD services

UEFI Boot Manager

UEFI Boot Menu

Boot mode selection in PEI phase

2B BOOT_NON_PARTITION

2C BOOT_SCRIPT

User forced boot from non-primary partition

Boot script save

2D BOOT_TIME

2E BOOT_TYPE

Boot time measurement support

PEI boot type support (cold, warm, power on, S3… )

2F CAPSULE_SERVICES

30 CARDBUS

31 CONSOLE_SPLITTER

32 CRISIS_RECOVERY

Capsule update and capsule runtime support

Cardbus support

Locate a crisis recovery firmware volume

33 CRYPTO

34 CSM_SMM

35 DATA_HUB

36 DEVICE_PATH

37 DIAGNOSTIC

38 DISK_IO

39 DXE_IPL

Cryptographic driver in SMM

USB Legacy, APM, INT1A and SD card support in SMM

Creating and manipulating data hub

DevicePath support

Diagnostic and summary splash screen

Disk IO driver. Converts a block oriented device to a byte oriented device

Load DXE core from DXE firmware volume

www.winsystems.com

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v1.0

PPM-C407/Power-on Self-Test (POST) Codes

Table C–1: Basic Post Codes (Continued)

Code Symbol Description

3A

3B

3C

3D

3E

3F

EBC

EMBEDDED_CONTROLLER

ERROR_LOG

FILESYSTEM

FIRMWARE_DEVICE

FIRMWARE_VOLUME

40 FIRSTWARE

41 FLASH_COMMUNICATION

42 FLOPPY

43 FONT

44 GRAPHICS_CONSOLE

45 HDD_PASSWORD

46 HII_DATABASE

47 HII_FORMS_BROWSER

EBC interpret

Embedded/Keyboard Controller driver

Error Manager, Error Log, SERR support

Enhanced FAT filesystem

Generic firmware device (flash part) driver

Firmware volume related drivers (fault tolerant update, simple file system)

(unused)

Phoenix Flash Interface (allocate, initialize, runtime)

ISA Floppy Driver

Installing HII font packages

Text output via GOP driver

HDD password and Software Setting Preservation

UEFI HII support

UEFI HII From Browser (BIOS Setup)

48 HII_FORMS_BROWSER_LAYOUT UEFI HII From Browser Layout (BIOS Setup)

49 HII_FORMS_BROWSER_VIEW UEFI HII From Browser screen interface (BIOS Setup)

4A ICRYPTSVC

4B IDE_BUS

Cryptographic driver in SMM, iCrypt support

IDE bus support driver

4C IDE_CONTROLLER

4D IDE_PASS_THRU

4E IMAGE

4F INTERRUPT_CONTROLLER

Generic IDE controller support driver

Interface to send ATA commands to devices

Image decoder (BMP, GIF, JPEG support)

8259 Interrupt Controller

50 IPMI

51 ISA_BUS

IPMI support

ISA bus support (driver binding)

52 KEY_TRANSLATION Virtual and onscreen keyboard, touch support

53 KEYBOARD_CONTROLLER

54 KEYBOARD_THUNK

55 LEGACY_BIOS

56 LOCK_SMRAM

57 MEMORY_TEST

58 METRONOME

Standard ISA keyboard controller driver

(unused)

Legacy metronome (periodic timer ticks)

59 MONOTONIC_COUNTER

5A NETWORK

5B OEM_ACTIVATION

5C PARTITION

5D PASSWORD

5E PCI_BUS

Monotonic counter

Network stack (SNP, DPC, MNP, ARP, TCP/IP, DHCP, FTP ... )

OEM Activation, SLP support

Partition support - MBR, GPT, El Torito

Password pop-up and reset

PCI bus support drivers

www.winsystems.com

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v1.0

PPM-C407/Power-on Self-Test (POST) Codes

Table C–1: Basic Post Codes (Continued)

Code Symbol Description

5F PPI_NEEDED

60 PROGRESS_INDICATOR

61 PS2_KEYBOARD

62 PS2_MOUSE

63 RESET

64 RTC

65 RUNTIME

66 S3_SSMI

67 S3_SUPPORT

68 SCSI_BUS

69 SCSI_DISK

6A SCSI_PASS_THRU

6B SECTION_EXTRACTION

6C SECURE_BOOT

6D SECURE_FLASH

6E SECURE_KEY

(unused)

Progress bar support in Boot Manager

PS/2 keyboard driver

PS/2 mouse driver

Reset platform via port CF9h

Standard ISA RTC support

Switch over to Runtime

S3 Boot Script support

ACPI S3 Save support

SCSI bus driver

SCSI disk driver

SCSI OpROM Pass Thru

Extracting section from a firmware file

Secure Boot DXE driver

Secure Flash support (capsule flash update)

Phoenix SecureKey SMM support

6F SECURITY_SDM

70 SECURITY_STUB

71 SERIAL

72 SETUP

73 SMBIOS

74 SMBIOS_EVENT_LOG

75 SMM_COMMUNICATION

76 SMM_RUNTIME

SDM driver, providing access to secure data

Platform security stub driver

PCI/ISA serial port, serial mouse

Setup pages

SMBIOS tables initialization and update

SMBIOS Event Log

Phoenix SMM Communication (DXE <-> SMM interface)

SMM Ready To Boot, SMM Runtime Infrastructure

77 SMM_SERVICES

78 SPEAKER

SMM driver register, dispatch and communicate

Speaker support (beeps)

79 SPLASH

7A SSMI_ALLOCATOR

7B STATUS_CODE

7C TCG

7D TEXT_CONSOLE

7E TIMER

Logo splash screen

Software SMI allocator

UEFI Watchdog and 8254 timer

7F TPM_NV (unused)

80 UNICODE

81 USB_BUS

82 USB_CONTROLLER

83 USB_DEVICE

84 USB_PROTOCOL

Unicode character set support

USB bus driver

USB controller driver (UHCI, OHCI, EHCL XHCI)

USB device drivers (keyboard, mouse, mass storage ... )

USB protocol drivers

www.winsystems.com

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v1.0

PPM-C407/Power-on Self-Test (POST) Codes

Table C–1: Basic Post Codes (Continued)

Code Symbol Description

85 USER_MANAGER

86 VARIABLE_DEFAULT

87 VARIABLE_SERVICES

88 VGA

User manager driver (PBA, security)

(unused)

Variable services

Simple Text and GOP on legacy VGA Option ROM

89 APEI ACPI APEI support (aka WHEA)

8A CSM_PREPARETOBOOT_ENTRY CSM "Prepare to boot" called

8B CSM_PREPARETOBOOT_EXIT

8C CSM_INT19_ENTRY

CSM "Prepare to boot" exited

(unused)

8D CSM_BOOTDEVICE_ENTRY

8E CSM_BOOTDEVICE_EXIT

8F CSM_INT19_EXIT

90 FLASH_DEVICE

91 FLASH_CONTROLLER

92 SIO_PEI

93 SIO_DXE

94 HARDWARE_MONITOR

(unused)

(unused)

(unused)

Flash device driver (flash part)

Flash controller driver (chipset / EC)

Super I/O PEI module

Super I/0 DXE driver

Hardware monitor driver

A0 PLATFORM_STAGE0

A1 PLATFORM_STAGE1

A2 PLATFORM_STAGE2

A3 PLATFORM_DXE

A4 PLATFORM_S3SAVE

A5 PLATFORM_FLASH

A6 PLATFORM_SMM

A7 PLATFORM_PCI

A8 PLATFORM_CSM

A9 PLATFORM_ADVHII

Platform Stage0 module (early PEI platform init)

Platform Stage1 module (PEI platform init)

Platform Stage2 module (late PEI platform init)

Platform DXE driver

Platform S3 save DXE and SMM drivers

Platform flash driver

Platform SMM initialization driver

Platform PCI bus driver

Platform specific legacy BIOS protocol

Platform Advanced HII (setup page)

AA PLATFORM_SETUP Setup entry and default configuration

PRELIMINARY www.winsystems.com

Page 62

v1.0

PPM-C407/Power-on Self-Test (POST) Codes

Architectural Diagnostic Codes

Architectural Diagnostic diagnostic codes describe important events in the BIOS initialization sequence.

Table C–2: Architectural Diagnostic Codes

Code Symbol

F0 SEC_ENTRY

F1 SEC_EXIT

F2 PEI_ENTRY

F3 PEI_EXIT

F4 IPL_DXE

F5 IPL_S3

F6 S3_OS

F7 IPL_RECOVERY

F8 IPL_EXIT

F9 DXE_ENTRY

FA DXE_EXIT

FB PEI_MEMORY

FC PEI_IPL

FD IPL_DXE

FE IPL_PPI

FF DXE_ARCH

Description

SEC phase entry (reset vector)

SEC phase exit

PEI phase entry (PEI dispatch)

PEI phase exit

DXE IPL normal boot path

DXE IPL S3 boot path to OS

S3 boot to OS

DXE IPL crisis recovery boot path

Exiting DXE IPL, starting DXE phase

DXE dispatch start

DXE dispatch exit

No permanent memory found in PEI phase

No DXE IPL found in PEI phase

No DXE found in IPL

Missing PPIs needed by DXE

Missing architectural protocols at the end of DXE

PRELIMINARY www.winsystems.com

Page 63

v1.0

PPM-C407/Power-on Self-Test (POST) Codes

Progress and Error Codes

Table C–3: Progress and Error Codes

Code Symbol

01 COMP_PEI_BEGIN

02 COMP_PEI_END

03 COMP_DXE_BEGIN

04 COMP_DXE_END

05 COMP_SUPPORTED

06

07

08

09

0A

0B

0C

0D

COMP_START

COMP_STOP

COMP_SMM_INIT

DEVICE_ERROR

RESOURCE_ERROR

DATA_CORRUPT

Progress and error codes are only displayed on POST diagnostic displays that show four digits. On these displays, the most significant two digits show the progress or error code from the table in this section (Progress and Error Codes), while the least significant two digits show the diagnostic code (see tables above). For example: 0345 indicates the component was loaded, the DXE/UEFI entry point called, and DXE driver initialization of the HDD password feature.

COMP_PEI_CALLBACK

COMP_DXE_CALLBACK

Description

The component was loaded and the PEI entry point called

The component returned from the entry point

The component was loaded and the DXE/UEFI entry point called

The component returned from the entry point

The Supported() member function of the component's instance of the

Driver Binding protocol was called

The Start() member function of the component's instance of the Driver

Binding protocol was called

The Stop() member function of the component's instance of the Driver

Binding protocol was called

The component was loaded and the entry point called inside of SMM

The driver encountered a condition where it cannot proceed due to a hardware failure

The driver encountered a condition where it cannot proceed due to being unable to acquire resources

The driver encountered a condition where it found invalid data and could not continue

The component received a callback in PEI phase

The component received a callback in DXE phase

PRELIMINARY www.winsystems.com

Page 64

v1.0

PPM-C407/Warranty Information

Appendix D. Warranty Information

WinSystems warrants that for a period of two (2) years from the date of shipment, any Products and Software purchased or licensed hereunder which have been developed or manufactured by WinSystems shall be free of any defects and shall perform substantially in accordance with WinSystems' specifications therefor. With respect to any Products or Software purchased or licensed hereunder which have been developed or manufactured by others, WinSystems shall transfer and assign to Customer any warranty of such manufacturer or developer held by WinSystems, provided that the warranty, if any, may be assigned. The sole obligation of WinSystems for any breach of warranty contained herein shall be, at its option, either (i) to repair or replace at its expense any materially defective Products or Software, or (ii) to take back such Products and Software and refund the

Customer the purchase price and any license fees paid for the same. Customer shall pay all freight, duty, broker's fees, insurance, charges and other fees and charges for the return of any Products or Software to WinSystems under this warranty.

WinSystems shall pay freight and insurance charges for any repaired or replaced Products or Software thereafter delivered to

Customer within the United States. All fees and costs for shipment outside of the United States shall be paid by Customer. The foregoing warranty shall not apply to any Products or Software which have been subject to abuse, misuse, vandalism, accident, alteration, neglect, unauthorized repair or improper installation.

THERE ARE NO WARRANTIES BY WINSYSTEMS EXCEPT AS STATED HEREIN. THERE ARE NO OTHER WARRANTIES EXPRESS

OR IMPLIED INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

PARTICULAR PURPOSE. IN NO EVENT SHALL WINSYSTEMS BE LIABLE FOR CONSEQUENTIAL, INCIDENTAL OR SPECIAL

DAMAGES FOR LOSS OF DATA, PROFITS OR GOODWILL. WINSYSTEMS' MAXIMUM LIABILITY FOR ANY BREACH OF THIS

AGREEMENT OR OTHER CLAIM RELATED TO ANY PRODUCTS, SOFTWARE, OR THE SUBJECT MATTER HEREOF, SHALL NOT

EXCEED THE PURCHASE PRICE OR LICENSE FEE PAID BY CUSTOMER TO WINSYSTEMS FOR THE PRODUCTS OR SOFTWARE

OR PORTION THEREOF TO WHICH SUCH BREACH OR CLAIM PERTAINS.

Title to the Products shall remain vested in WinSystems until complete payment is made by Customer. Title to any Software shall remain vested in WinSystems, or WinSystems' licensor from whom WinSystems has obtained marketing rights, both before, during and after the term of the License. Nonpayment when due of the purchase price for any Products or the License fees for any Software, or, if applicable, taxes and/or the cost of any freight and insurance for any Products and/or Software, shall entitle

WinSystems to take possession of the Products and/or Software without notice to Customer or prejudice to WinSystems' rights under contract or any other legal remedy.

Until title to the Products pass in accordance with the provision set out above, except with the prior written approval of

WinSystems, no Products shall be modified, altered, moved or in any way assigned, sublet, mortgaged or charged nor may

Customer part with possession of all or part of the same.

There are no understandings, agreements or representations, express or implied, other than those set forth herein. This Order embodies the entire agreement between the parties and may be waived, amended or supplemented only by a written instrument executed jointly by WinSystems and Customer as evidenced only by the signature of duly authorized officers of each party. The foregoing terms and conditions of any order which may be issued by Customer for the purchase of Products or licensing of

Software hereunder.

In the event this Order is placed in the hands of an attorney or collection agency by WinSystems to collect any sums due hereunder to WinSystems, Customer shall pay all reasonable attorney's fees, expenses, collection and court costs incurred by

WinSystems.

THIS AGREEMENT SHALL BE GOVERNED AND CONSTRUED UNDER THE TEXAS UNIFORM COMMERCIAL CODE AND THE

PRELIMINARY

1.

To obtain service under this warranty, obtain a return authorization number. In the United States, contact the WinSystems

Service Center for a return authorization number. Outside the United States, contact your local sales agent for a return authorization number.

2.

You must send the product postage prepaid and insured. You must enclose the products in an anti-static bag to protect from damage by static electricity. WinSystems is not responsible for damage to the product due to static electricity.

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Page 65

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