MAX77650/MAX77651 - Maxim Integrated

MAX77650/MAX77651 - Maxim Integrated
EVALUATION KIT AVAILABLE
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
General Description
The MAX77650/MAX77651 provide highly-integrated battery charging and power supply solutions for low-power
wearable applications where size and efficiency are
critical. Both devices feature a SIMO buck-boost regulator
that provides three independently programmable power
rails from a single inductor to minimize total solution
size. A 150mA LDO provides ripple rejection for audio
and other noise-sensitive applications. A highly configurable linear charger supports a wide range of Li+ battery
capacities and includes battery temperature monitoring
for additional safety (JEITA).
The devices include other features such as current sinks
for driving LED indicators and an analog multiplexer that
switches several internal voltage and current signals to an
external node for monitoring with an external ADC. A bidirectional I2C interface allows for configuring and checking the status of the devices. An internal on/off controller
provides a controlled startup sequence for the regulators
and provides supervisory functionality when the devices
are on. Numerous factory programmable options allow
the device to be tailored for many applications, enabling
faster time to market.
Simplified System Diagram
VBUS
+
CHGIN
BATT
IN_SBB
SYS
TBIAS
THM
1.5µH
LXA
LXB
SYS
LED0
IN_LDO
SBB0
2.05V
SBB1
1.2V
SBB2
3.3V
nEN
SYSTEM
RESOURCES
1.85V
●● Flexible and Configurable
• I2C Compatible Interface and GPIO
• Factory OTP Options Available
●●
●●
●●
●●
Bluetooth Headphones/Hearables
Fitness, Health, and Activity Monitors
Portable Devices
Internet of Things (IoT)
SDA
SCL
nRST
nIRQ
PWR_HLD
AMUX
Ordering Information appears at end of data sheet.
VIO/POWER
*
*
* PROCESSOR
*
ADC INPUT
*THIS DRAWING ASSUMES THAT THE PROCESSOR HAS INTERNAL PULLUP
RESISTORS FOR THIS NODE.
19-8550; Rev 4; 7/17
●● Charger Optimized for Small Battery Size
• Programmable Fast-Charge Current from 7.5mA to
300mA
• Programmable Battery Regulation Voltage from
3.6V to 4.6V
• Programmable Termination Current from 0.375mA
to 45mA
• JEITA Battery Temperature Monitors Adjust Charge
Current and Battery Regulation Voltage for Safe
Charging
GPIO
GPIO
VIO
LDO
LED1
LED2
●● Low Power
• 0.3μA Standby Current
• 5.6μA Operating Current (3 SIMO Channels +
LDO)
Applications
PGND
SDA
SCL
nRST
nIRQ
PWR_HLD
AMUX
●● Highly Integrated
• Smart Power Selector™ Li+/Li-Poly Charger
• 3 Output, Single-Inductor Multiple-Output (SIMO)
Buck-Boost Regulator
• 150mA LDO
• 3-Channel Current Sink Driver
• Analog MUX Output for Power Monitoring
●● Small Size
• 2.75mm x 2.15mm x 0.7mm WLP Package
• 30-Bump, 0.4mm-Pitch WLP, 6x5 Array
• Small Total Solution Size (19.2mm2)
VSYS
MAX77650
GND
Benefits and Features
Smart Power Selector is a trademark of Maxim Integrated
Products, Inc.
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics—Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics—Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics—Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics—LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics—Current Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Characteristics—I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Support Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SYS POR Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SYS Undervoltage Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SYS Overvoltage Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
nEN Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
nEN Manual Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
nEN Dual-functionality: Push-Button vs. Slide-Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupts (nIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset Output (nRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Hold Input (PWR_HLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General-Purpose Input Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Flexible Power Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Debounced Inputs (nEN, GPI, CHGIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
www.maximintegrated.com
Maxim Integrated │ 2
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
TABLE OF CONTENTS (CONTINUED)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Charger Symbol Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Smart Power Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Input Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Minimum Input Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Minimum System Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Die Temperature Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Charger State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Charger Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Prequalification State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Fast-Charge States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Top-Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Done State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Prequalification Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Fast-Charge Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Battery Temperature Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
JEITA-Modified States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Charger Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Configuring a Valid System Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CHGIN/SYS/BATT Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Thermistor Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Configurable Temperature Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Thermistor Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Using Different Thermistor β . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
NTC Thermistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Analog Multiplexer & Power Monitor AFEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Measuring Battery Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Method for Measuring Discharging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Method for Measuring Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SIMO Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SIMO Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SIMO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SIMO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SIMO Active Discharge Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SIMO Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SIMO Available Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
www.maximintegrated.com
Maxim Integrated │ 3
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
TABLE OF CONTENTS (CONTINUED)
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Boost Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SIMO Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Unused Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LDO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LDO Active Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LDO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
LDO Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Input and Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Current Sink Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LED Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Unused Current Sink Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I2C Interface Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I2C Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I2C Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I2C Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C Communication Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C Communication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Writing to a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Writing Multiple Bytes to Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Reading from a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Reading from Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Engaging HS-mode for operation up to 3.4MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
www.maximintegrated.com
Maxim Integrated │ 4
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
LIST OF FIGURES
Figure 1. Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 2. nEN Usage Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3. GPIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 4. Top-Level On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 5. Power-Up/Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 6. Flexible Power Sequencer Basic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 8. Startup Timing Diagram Due to Charge Source Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9. Debounced Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10. Linear Charger Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 11. Charger Simplified Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 12. Charger State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13. Example Battery Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 14. Thermistor Logic Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 15. Safe-Charging Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 16. Thermistor Bias State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. Thermistor Circuit with Adjusting Series and Parallel Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18. SIMO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 19. LDO Capacitance for Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 20. LDO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 21. Current Sink Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. I2 C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. I2 C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24. I2 ​C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25. Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 26. Slave Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 27. Writing to a Single Register with the Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 28. Writing to Sequential registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 29. Reading from a Single Register with the Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 30. Reading Continuously from Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 31. Engaging HS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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Maxim Integrated │ 5
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
LIST OF TABLES
Table 1. Regulator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 2. On/Off Controller Transition/State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 3. Charger Quick Symbol Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 4. Trip Temperatures vs. Trip Voltages for Different NTC β . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 5. Example RS and RP Correcting Values for NTC β Above 3380K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 6. NTC Thermistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 7. AMUX Signal Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 8. Battery Current Direction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9. SIMO Available Output Current for Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 10. Example Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 11. I2C Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Maxim Integrated │ 6
MAX77650/MAX77651
Absolute Maximum Ratings
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
nEN, PWR_HLD, nIRQ, nRST to GND......-0.3V to VSYS + 0.3V
SCL, SDA, GPIO to GND..............................-0.3V to VIO + 0.3V
CHGIN to GND....................................................-0.3V to +30.0V
SYS, BATT to GND...............................................-0.3V to +6.0V
SYS to IN_SBB.....................................................-0.3V to +0.3V
VL to GND.............................................................-0.3V to +6.0V
AMUX, THM, TBIAS to GND.................................-0.3V to +6.0V
nIRQ, nRST, SDA, AMUX, GPIO Continous Current........±20mA
CHGIN Continuous Current...........................................1.2ARMS
SYS Continuous Current................................................1.2ARMS
BATT Continuous Current (Note 1)................................1.2ARMS
LDO to GND (Note 2)............................-0.3V to VIN_LDO + 0.3V
IN_LDO, VIO to GND.................................. -0.3V to the lower of
(VSYS + 0.3V) and +6.0V
LED0, LED1, LED2 to LGND................................-0.3V to +6.0V
IN_SBB to PGND..................................................-0.3V to +6.0V
LXA Continuous Current (Note 3)..................................1.2ARMS
LXB Continuous Current (Note 4)..................................1.2ARMS
SBB0, SBB1, SBB2 to PGND (Note 2).................-0.3V to +6.0V
BST to IN_SBB......................................................-0.3V to +6.0V
BST to LXB............................................................-0.3V to +6.0V
SBB0, SBB1, SBB2 Short-Circuit Duration................Continuous
PGND to GND.......................................................-0.3V to +0.3V
LGND to GND.......................................................-0.3V to +0.3V
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Continuous Power Dissipation (Multilayer Board)
(TA = +70°C, derate 20.4mW/°C above +70°C).........1632mW
Note 1: Do not repeatedly hot-plug a source to the BATT terminal at a rate greater than 10Hz. Hot plugging low-impedance sources
results in an ~8A momentary (~2µs) current spike.
Note 2: When the active discharge resistor is engaged, limit its power dissipation to an average of 10mW. For example, consider
the case where the active discharge resistance is discharging the output capacitor each time the regulator turns off; the
10mW limit allows you to discharge 80µF of capacitance charged to 5V every 100ms (P = 1/2 x C x V2/t = 1/2 x 80µF x
5V2/100ms = 10mW).
Note 3: LXA has internal clamping diodes to PGND and IN_SBB. It is normal for these diodes to briefly conduct during switching
events. Avoid steady-state conduction of these diodes.
Note 4: Do not externally bias LXB. LXB has an internal low-side clamping diode to PGND, and an internal high-side clamping
diode that dynamically shifts to the selected SIMO output. It is normal for these internal clamping diodes to briefly conduct
during switching events. When the SIMO regulator is disabled, the LXB to PGND absolute maximum voltage is -0.3V to
VSBB0 + 0.3V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE CHARACTERISTICS
VALUES
Package Code
W302H2+1
Outline Number
21-100047
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θJA)
49°C/W (2s2p board)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 7
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Package Information (continued)
Pin 1
Indicator
1
see Note 7
Marking
E
COMMON DIMENSIONS
A
0.64 0.05
0.19 0.03
A
A1
0.45 REF
A2
D
AAAA
0.040 BASIC
0.27 0.03
A3
b
2.148
2.748
D
E
A
SIDE VIEW
TOP VIEW
A3
A1
A2
E1
1.60 BASIC
2.00 BASIC
e
0.40 BASIC
SD
0.00 BASIC
D1
S
0.025
0.025
0.20 BASIC
DEPOPULATED BUMPS:
NONE
SE
0.05 S
FRONT VIEW
E1
SE
e
E
B
D
SD
C
D1
B
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
A
1
2
3
4
5
A
BOTTOM VIEW
- DRAWING NOT TO SCALE -
www.maximintegrated.com
maxim
integrated
6
b
0.05 M
S AB
TITLE
TM
PACKAGE OUTLINE 30 BUMPS
WLP PKG. 0.4 mm PITCH, W302H2+1
APPROVAL
DOCUMENT CONTROL NO.
21-100047
REV.
A
1
1
Maxim Integrated │ 8
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Top Level
(VCHGIN = 0V, VSYS = VBATT = VIN_SBB = VIN_LDO = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over
the operating temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
Operating Voltage
Range
Shutdown Supply
Current
Quiescent Supply
Current
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SYMBOL
CONDITIONS
VSYS
ISHDN
IQ
MIN
TYP
2.7
Current measured
into BATT and SYS
and IN_SBB and
IN_LDO, all
resources are off
(LDO, SBB0, SBB1,
SBB2, LED0, LED1,
LED2), TA = 25°C
Current measured
into BATT and SYS
and IN_SBB and
IN_LDO. LDO,
SBB0, SBB1, and
SBB2 are enabled
with no load. LED0,
LED1, and LED2
are disabled
Main bias is off
(SBIA_EN = 0). This
is the standby state
0.3
Main bias is on in
low-power mode
(SBIA_EN = 1,
SBIA_LPM = 1)
1
Main bias is on in
normal-power mode
(SBIA_EN = 1,
SBIA_LPM = 0)
28
Main bias is in
low-power mode
(SBIA_LPM = 1)
5.6
MAX
UNITS
5.5
V
1
μA
13
μA
Main bias is in
normal-power mode
(SBIA_LPM = 0)
40
60
Maxim Integrated │ 9
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Global Resources
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.6
1.9
2.1
V
POWER-ON RESET (POR)
POR Threshold
VPOR
VSYS falling
POR Threshold
Hysteresis
100
mV
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO Threshold
VSYSUVLO
UVLO Threshold
Hysteresis
VSYSUVLO_HYS
VSYS falling, UVLO_F[3:0] = 0xA
2.5
2.6
2.7
VSYS falling, UVLO_F[3:0] = 0xF
2.75
2.85
2.95
UVLO_H[3:0] = 0x5
300
V
mV
OVERVOLTAGE LOCKOUT (OVLO)
OVLO Threshold
VSYSOVLO
VSYS rising
5.70
5.85
6.00
V
THERMAL MONITORS
Overtemperature
Lockout Threshold
TOTLO
TJ rising
165
°C
Thermal Alarm
Temperature 1
TJAL1
TJ rising
80
°C
Thermal Alarm
Temperature 2
TJAL2
TJ rising
100
°C
15
°C
Thermal Alarm
Temperature Hysteresis
ENABLE INPUT (nEN)
nEN Input Leakage
Current
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InEN_LKG
VSYS = 5.5V, VnEN =
0V, and 5.5V
TA = +25°C
TA = +85°C
-1
±0.001
±0.01
+1
μA
Maxim Integrated │ 10
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Global Resources (continued)
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
nEN Input Falling
Threshold
VTH_nEN_F
nEN falling
nEN Input Rising
Threshold
VTH_nEN_F
nEN falling
Debounce Time
tDBNC_nEN
Manual Reset Time
tMRST
MIN
TYP
VSYS
- 1.4
VSYS
- 1.0
VSYS
- 0.9
MAX
UNITS
V
VSYS
- 0.6
V
DBEN_nEN = 0
100
μs
DBEN_nEN = 1
30
ms
MRT_OTP = 0
14
16
20
MRT_OTP = 1
7
8
10.5
-1
±0.001
+1
s
POWER HOLD INPUT (PWR_HLD)
VSYS = VIO = 5.5V,
VPWR_HLD = 0V,
and 5.5V
TA = +25°C
PWR_HLD Input
Leakage Current
IPWR_HLD_LKG
PWR_HLD Input
Voltage Low
VIL
VIO = 1.8V
PWR_HLD Input
Voltage High
VIH
VIO ​= 1.8V
PWR_HLD Input
Hysteresis
VHYS
VIO​= 1.8V
50
mV
Both rising and falling edges are filtered
100
μs
PWR_HLD Glitch Filter
PWR_HLD Wait Time
tPWR_HLD_GF
TA = +85°C
±0.01
0.3 x
VIO
0.7 x
VIO
Maximum time for PWR_HLD input to assert
tPWR_HLD_WAIT after nRST deasserts during the power-up
sequence
3.5
μA
V
V
4.0
5.0
s
0.4
V
OPEN-DRAIN INTERRUPT OUTPUT (nIRQ)
Output Voltage Low
VOL
ISINK = 2mA
Output Falling Edge
Time
tf_nIRQ
CIRQ = 25pF
Leakage Current
InIRQ_LKG
VSYS = VIO = 5.5V,
nIRQ set to be high
impedance (i.e., no
interrupts), VnIRQ =
0V and 5.5V
2
TA = +25°C
-1
±0.001
ns
+1
μA
TA = +85°C
±0.01
OPEN-DRAIN RESET OUTPUT (nRST)
Output Voltage Low
VOL
ISINK = 2mA
Output Falling Edge
Time
tf_nRST
CRST = 25pF
0.4
V
2
ns
nRST Deassert Delay
Time
tRSTODD
See Figure 5 and Figure 7 for more
information
5.12
ms
nRST Assert Delay Time
tRSTOAD
See Figure 5 for more information
10.24
ms
Leakage Current
www.maximintegrated.com
InRST_LKG
VSYS = VIO = 5.5V,
nRST set to be high
impedance (i.e., not
reset), VnRST = 0V
and 5.5V
TA = +25°C
-1
±0.001
+1
μA
TA = +85°C
±0.01
Maxim Integrated │ 11
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Global Resources (continued)
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.3 x
VIO
V
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Input Voltage Low
VIL
VIO = 1.8V
Input Voltage High
VIH
VIO = 1.8V
Input Leakage Current
IGPI_LKG
0.7 x
VIO
DIR = 1, VIO = 5.5V,
VGPIO = 0V and
5.5V
TA = +25°C
-1
TA = +85°C
V
±0.001
+1
±0.01
0.4
μA
Output Voltage Low
VOL
ISINK = 2mA
Output Voltage High
VOH
ISOURCE = 1mA
Input Debounce Time
tDBNC_GPI
DBEN_GPI = 1
30
ms
Output Falling Edge
Time
tf_GPIO
CGPIO = 25pF
3
ns
Output Rising Edge
Time
tr_GPIO
CGPIO = 25pF
3
ns
0.8 x
VIO
V
V
FLEXIBLE POWER SEQUENCER
Power-Up Event Periods
tEN
See Figure 6
1.28
ms
Power-Down Event
Periods
tDIS
See Figure 6
2.56
ms
Electrical Characteristics—Smart Power Selector Charger
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
7.25
V
DC INPUT
CHGIN Valid Voltage
Range
VCHGIN
Initial CHGIN voltage before enabling
charging
CHGIN Standoff Voltage
Range
VSTANDOFF
DC rising
CHGIN Overvoltage
Threshold
VCHGIN_OVP
DC rising
4.10
28
7.25
CHGIN Overvoltage
Hysteresis
CHGIN Undervoltage
Lockout
www.maximintegrated.com
7.75
100
VCHGIN_UVLO
DC rising
3.9
CHGIN Undervoltage
Lockout Hysteresis
Input Current Limit
Range
7.50
V
4.0
mV
4.1
500
ICHGIN-LIM
VSYS = VSYS-REG - 100mV​, programmable
in 95mA steps
95
V
V
mV
475
mA
Maxim Integrated │ 12
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Smart Power Selector Charger (continued)
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
MIN
TYP
MAX
UNITS
Input Current Limit
Accuracy
PARAMETER
SYMBOL
ICHGIN-LIM = 95mA, VSYS = VSYS-REG 100mV​
90
95
100
mA
Minimum Input Voltage
Regulation Range
VCHGIN falling due to loading conditions
and/or high-impedance charge source,
programmable in 100mV increments with
VCHGIN_MIN[2:0].
4.0
4.7
V
VCHGIN-MIN = 4.5V (VCHGIN_MIN[2:0] =
0b101), ICHGIN reduced by 10%
4.32
4.50
4.68
V
VCHGIN = 5V, time before CHGIN is
allowed to deliver current to SYS or BATT
100
120
140
ms
VCHGIN-MIN
Minimum Input Voltage
Regulation Accuracy
Charger Input
Debounce Timer
tCHGIN-DB
CONDITIONS
SUPPLY AND QUIESCENT CURRENTS
BATT Bias Current
CHGIN Supply Current
CHGIN Suspend Supply
Current
IBATT-BIAS
ICHGIN
ICHGIN
VCHGIN = 5V, charger is not in USB
suspend (USBS = 0), charging is finished
(CHG_DTLS indicate done), ISYS = 0mA
5
VCHGIN = 5V, charger is not in USB
suspend (USBS = 0), Charging is finished
(CHG_DTLS indicate done), ISYS = 0mA
1.0
μA
1.8
mA
VCHGIN = 0V to 1V, VBATT = 3.3V, ISYS =
0A
50
μA
VCHGIN = 5V, charger in USB suspend
(USBS = 1)
50
μA
PREQUALIFICATIONS
Charge Current
Soft-Start Slew Time
Zero to full scale
1
ms
Input Current
Soft-Start Slew Time
Zero to full scale
1
ms
Prequalification Voltage
Threshold Range
Charger is in prequalification mode when
VBATT < VPQ, this threshold has 100mV of
hysteresis, programmable in 100mV steps
with CHG_PQ[2:0]
2.3
3.0
V
VPQ = 3.0V
-3
+3
%
VPQ
Prequalification Voltage
Threshold Accuracy
Prequalification Mode
Charge Current
IPQ
Prequalification Safety
Timer
tPQ
www.maximintegrated.com
VBATT = 2.5V, VPQ = 3.0V, expressed as a
percentage of IFAST-CHG, I_PQ = 0
10
VBATT = 2.5V, VPQ = 3.0V, expressed as a
percentage of IFAST-CHG, I_PQ = 1
20
VBATT < VPQ = 3.0V
%
27
30
33
minutes
Maxim Integrated │ 13
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Smart Power Selector Charger (continued)
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.6
V
FAST CHARGE
Fast-Charge Voltage
Range
VFAST-CHG
Fast-Charge Voltage
Accuracy
Fast-Charge Current
Range
IBATT = 0mA, programmable in 25mV
steps with CHG_CV[5:0]
3.6
IBATT = 0mA, VFAST-CHG = 4.3V, VSYS =
4.5V, TA = +25°C
-0.5
IFAST-CHG
Fast-Charge Current
Accuracy over
Temperature
Fast-Charge Safety
Timer Range
tFC
7.5
300
IFAST-CHG = 15mA, TA = 25°C, VBATT =
VFAST-CHG - 300mV
-1.5
+1.5
IFAST-CHG = 300mA, TA = 25°C, VBATT =
VFAST-CHG - 300mV
-1.5
+1.5
Across all current settings, VBATT = VFASTCHG - 300mV
-10
+10
%
3
7
hours
-10
+10
%
Programmable in 2 hour increments or
disabled with T_FAST_CHG[1:0], from
prequal done to timer fault
tFC = 3 hours
Fast-Charge Safety
Timer Suspend
Threshold
Fast-charge CC mode, loading conditions
and/or a weak charging source caused
charge current to drop below this threshold,
expressed as a percentage of IFAST-CHG
TJ-REG
GTJ-REG
1.0
Programmable in 7.5mA steps with CHG_
CC[5:0]
Fast-Charge Safety
Timer Accuracy
Junction Temperature
Regulation Setting
Range
+0.5
%
IBATT = 0mA, VFAST-CHG = 3.6V to 4.6V,
VSYS = 4.8V
Fast-Charge Current
Accuracy
Junction Temperature
Regulation Loop Gain
±0.15
Programmable in 10°C steps with
TJ_REG[2:0]
mA
%
20
60
%
100
Rate at which IFAST-CHG/IPQ is reduced to
maintain TJ-REG, expressed a percentage
of IFAST-CHG/IPQ per degree centigrade
rise
-5.4
I_TERM = 0b00 (expressed as a percentage
of IFAST-CHG)
5
I_TERM = 0b01 (expressed as a percentage
of IFAST-CHG)
7.5
I_TERM = 0b10 (expressed as a percentage
of IFAST-CHG)
10
I_TERM = 0b11 (expressed as a percentage
of IFAST-CHG)
15
°C
%/°C
TERMINATION AND TOPOFF
End-of-Charge
Termination Current
www.maximintegrated.com
ITERM
%
Maxim Integrated │ 14
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Smart Power Selector Charger (continued)
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
End-of-Charge Termination Current Accuracy
Top-Off Timer Range
tTO
MIN
TYP
MAX
IFAST-CHG = 15mA, ITERM = 1.5mA (10%
of IFAST-CHG), TA = +25°C
CONDITIONS
1.35
1.5
1.65
IFAST-CHG = 300mA, ITERM = 30mA (10%
of IFAST-CHG), TA = +25°C
27
30
33
IBATT < ITERM, programmable in 5 minute
steps with T_TOPOFF[2:0]
0
35
minutes
+10
%
mA
Top-Off Timer Accuracy
tTO = 10 minutes
-10
Charge Restart Threshold
CHG = 0 (charging done), charging resumes when VBATT < VFAST-CHG - VRE-
65
VRESTART
UNITS
150
mV
VBATT = 3.7V, IBATT = 300mA, VCHGIN =
0V, battery is discharging to SYS
100
mΩ
VSYS = 4.5V, VBATT = 0V, TA = 25°C,
charger disabled
0.1
VSYS = 4.5V, VBATT = 0V, TA = 85°C,
charger disabled
1
START
DEVICE ON-RESISTANCE AND LEAKAGE
BATT to SYS
On-Resistance
Charger FET Leakage
Current
CHGIN to SYS
On-Resistance
Input FET Leakage
Current
1.0
μA
VCHGIN = 4.65V
600
VCHGIN = 0V, VSYS = 4.2V, TA = +25°C,
body-switched diode reverse biased
0.1
VCHGIN = 0V, VSYS = 4.2V, TA = +85°C,
body-switched diode is reverse biased
1
mΩ
1.0
μA
SYSTEM NODE
System Voltage
Regulation Range
System Voltage
Regulation Accuracy
Minimum System
Voltage Regulation
Loop Setpoint
Supplement Mode System Voltage Regulation
www.maximintegrated.com
VSYS-REG
VSYS
VSYS-MIN
Programmable in 25mV steps with VSYS_
REG[4:0]
4.1
VSYS-REG = 4.5V, ISYS = 1mA, TA = +25°C
4.41
4.50
4.59
VSYS-REG = 4.5V, ISYS = 1mA, TA = -40°C
to +85°C
4.365
4.500
4.635
VCHGIN = 5V, VSYS-REG = 4.5V, VSYS <
VSYS-REG due to ICHGIN = ICHGIN-LIM (input in current-limit), battery charging, IBATT
reduced to 50% of IFAST-CHG (minimum
system voltage regulation active)
4.34
4.4
4.45
ISYS = 150mA
4.8
VBATT
- 0.15V
V
V
V
V
Maxim Integrated │ 15
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Adjustable Thermistor Temperature Monitors
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
JEITA TEMPERATURE MONITORS
TBIAS Voltage
VTBIAS
THM_EN = 1, VCHGIN = 5V
JEITA Cold Threshold
Range
VCOLD
Voltage rising threshold, programmable
with THM_COLD[1:0] in 5ºC increments
when using an NTC β = 3380K
0.867
1.024
V
JEITA Cool Threshold
Range
VCOOL
Voltage rising threshold, programmable
with THM_COOL[1:0] in 5ºC increments
when using an NTC β = 3380K
0.747
0.923
V
JEITA Warm Threshold
Range
VWARM
Voltage falling threshold, programmable
with THM_WARM[1:0] in 5ºC increments
when using an NTC β = 3380K
0.367
0.511
V
VHOT
Voltage falling threshold, programmable
with THM_HOT[1:0] in 5ºC increments
when using an NTC β = 3380K
0.291
0.411
V
JEITA Hot Threshold
Range
1.25
V
Temperature Threshold
Accuracy
Voltage threshold accuracy expressed as
temperature for an NTC β = 3380K
±3
°C
Temperature Threshold
Hysteresis
Temperature hysteresis set on each voltage threshold for an NTC β = 3380K
3
°C
JEITA Modified FastCharge Voltage Range
VFAST-CHG_
JEITA Modified FastCharge Current Range
IFAST-CHG_JEI-
JEITA
TA
IBATT = 0mA, programmable in 25mV
steps, battery is either cool or warm
3.6
4.6
V
Programmable in 7.5mA steps, battery is
either cool or warm
7.5
300
mA
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG MULTIPLEXER AND POWER MONITOR AFEs
Full-Scale Voltage
1.25
V
GVSYS
VFS corresponds to maximum VSYS-REG
setting
0.26
V/V
CHGIN Current Monitor
Gain
GICHGIN
VFS corresponds to maximum ICHGIN-LIM
setting
2.632
V/A
CHGIN Voltage Monitor
Gain
GVCHGIN
VFS corresponds to VCHGIN_OVP
0.167
V/V
VFS corresponds to 100% of IFAST-CHG
setting (CHG_CC[5:0])
12.5
mV/%
SYS Voltage Monitor
Gain
VFS
CHGIN POWER
BATT MONITOR
Battery Charge Current
Monitor Gain
www.maximintegrated.com
GIBATT-CHG
Maxim Integrated │ 16
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs (continued)
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IFAST-CHG = 15mA, TA = 25°C, VBATT =
VFAST-CHG - 300mV
-3.5
+3.5
IFAST-CHG = 300mA, TA = +25°C, VBATT =
VFAST-CHG - 300mV
-3.5
+3.5
Across all current settings, VBATT = VFASTCHG - 300mV
-10
+10
%
Programmable with IMON_DISCHG_
SCALE[3:0]
8.2
300
mA
Battery Discharge
Current Monitor
Accuracy
15mA to 300mA battery discharge current,
IDISCHG-SCALE = 300mA
-15
+15
%
Battery Discharge
Current Monitor Offset
IBATT = 0mA
-0.5
+0.65
mA
Charge Current Monitor
Accuracy
Charge Current Monitor
Accuracy over
Temperature
Battery Discharge
Monitor Full-Scale
Current Range
Battery Voltage Monitor
Gain
IDISCHG-SCALE
GVBATT
%
VFS corresponds to maximum VFAST-CHG
setting
0.272
V/V
ANALOG MULTIPLEXER
Channel Switching Time
0.3
μs
TA = +25°C
1
TA = +85°C
1
μA
GVTHM
1
V/V
GVTBIAS
1
V/V
VAMUX = 0V, AMUX
is high impedance
Off Leakage Current
500
nA
THM AND TBIAS
THM Voltage Monitor
Gain
TBIAS Voltage Monitor
Gain
Electrical Characteristics—SIMO Buck-Boost
(VSYS = 3.7V, VIN_SBB = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
TA = +25°C
0.05
1
TA = -40°C to
+85°C
0.25
UNITS
GENERAL CHARACTERISTICS
SBB0, SBB1, SBB2
are disabled, VSYS
= VIN_SBB = 5.5V,
VLXA = 0V
Shutdown Current
(Note 3)
SIMO Quiescent Supply
Current (Note 3)
www.maximintegrated.com
IQ
μA
Additional current required to enable the
first SIMO channel
0.8
3.0
Additional current required to enable the
second or third SIMO channel
0.7
1.8
μA
Maxim Integrated │ 17
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—SIMO Buck-Boost (continued)
(VSYS = 3.7V, VIN_SBB = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT VOLTAGE RANGE (SBB0)
Minimum Output
Voltage
0.8
V
Maximum Output
Voltage
2.375
V
Output DAC Bits
6
bits
Output DAC LSB Size
25
mV
OUTPUT VOLTAGE RANGE (SBB1)
Minimum Output
Voltage
MAX77650
0.8
MAX77651
2.4
Maximum Output
Voltage
MAX77650
1.5875
MAX77651
5.25
MAX77650
12.5
MAX77651
50
Minimum Output
Voltage
MAX77650
0.8
MAX77651
2.4
Maximum Output
Voltage
MAX77650
3.95
MAX77651
5.25
Output DAC Bits
V
V
6
Output DAC LSB Size
bits
mV
OUTPUT VOLTAGE RANGE (SBB2)
V
V
Output DAC Bits
6
bits
Output DAC LSB Size
50
mV
STATIC OUTPUT VOLTAGE ACCURACY
VSBBx falling,
threshold where
LXA switches high.
Specified as a
percentage of target
output voltage.
Output Voltage
Accuracy
TA = +25°C
-2.5
+2.5
%
TA = -40°C to +85°C
-4.0
+4.0
TIMING CHARACTERISTICS
Delay time from the SIMO receiving its first
enable signal to when it begins to switch in
order to service that output.
Enable Delay
Soft-Start Slew Rate
www.maximintegrated.com
dV/dtSS
60
3.3
5.0
μs
6.6
mV/μs
Maxim Integrated │ 18
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—SIMO Buck-Boost (continued)
(VSYS = 3.7V, VIN_SBB = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
-1.0
±0.1
+1.0
UNITS
POWER STAGE CHARACTERISTICS
SBB0, SBB1, SBB2
are disabled,
VIN_SBB = 5.5V,
VLXA = 0V, or 5.5V
LXA Leakage Current
SBB0, SBB1,
SBB2 are disabled,
VIN_SBB = 5.5V,
VLXA = 0V or 5.5V,
all VSBBx = 5.5V
LXB Leakage Current
BST Leakage Current
VIN_SBB = 5.5V,
VLXB = 5.5V,
VBST = 11V
Disabled Output
Leakage Current
SBB0, SBB1, SBB2
are disabled, activedischarge disabled
(ADE_SBBx = 0),
VSBBx = 5.5V,
VLXB = 0V, VSYS =
VIN_SBB = VBST =
5.5V
Active Discharge
Impedance
RAD_SBBx
TA = +25°C
μA
TA = +85°C
TA = +25°C
±1.0
-1.0
±0.1
+1.0
μA
TA = +85°C
±1.0
TA = +25°C
+0.01
TA = +85°C
+0.1
TA = +25°C
+0.1
+1.0
μA
+1.0
μA
TA = +85°C
SBB0, SBB1, SBB2 are disabled, active
discharge enabled (ADE_SBBx = 1)
+0.2
80
140
260
IP_SBBx = 0b11
0.414
0.500
0.586
IP_SBBx = 0b10
0.589
0.707
0.806
IP_SBBx = 0b01
0.713
0.866
0.947
IP_SBBx = 0b00
0.892
1.000
1.108
Ω
CONTROL SCHEME
Peak Current Limit
(Note 4)
IP_SBB
A
Note 3: Guaranteed by design and characterization but not directly production tested. Production test coverage is provided by the
shutdown supply current and quiescent supply current specification in the Electrical Characteristics—Top Level table.
Note 4: Typical values align with bench observations using the stated conditions. Minimum and maximum values are tested in production with DC currents. See the Typical Operating Characteristics SIMO switching waveforms to gain more insight on this
specification.
www.maximintegrated.com
Maxim Integrated │ 19
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—LDO
(VSYS = 3.7V, VIN_LDO = 2.05V, VLDO = 1.85V, CLDO = 10μF, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
0.1
1
μA
LDO output enabled
and in regulation,
VIN_LDO = 2.05V,
VLDO = 1.85V
1.7
5.15
LDO output enabled
and in dropout, VIN_
LDO = 1.8V, VLDO
target is 1.85V
2.3
GENERAL CHARACTERISTICS
Input Voltage
VIN_LDO
IN_LDO cannot exceed SYS voltage
(Note 5)
LDO Shutdown Current
IIN_LDO
Current measured into IN_LDO, LDO
output disabled (Note 6)
LDO Quiescent Supply
Current (Note 6)
Maximum Output
Current
Current Limit
IIN_LDO
Current measured
into IN_LDO,
ILDO = 0mA
IOUT
1.8
μA
150
VLDO externally forced to 1.3V
165
mA
255
375
mA
2.9375
V
OUTPUT VOLTAGE RANGE
Output Voltage Range
Programmable with TV_LDO[6:0] in
12.5mV steps
1.3500
Output DAC Bits
Output DAC LSB Size
7
bits
12.5
mV
STATIC CHARACTERISTICS
Initial Output Voltage
Accuracy
ILDO = 75mA, TA = +25°C
Output Voltage
Accuracy
VLDO programmed from 1.35V to 2.9375V,
VIN_LDO = 1.8V to 5.5V, LDO not in dropout, ILDO = 0mA to 150mA, TA = -5°C to
+85°C
Output Noise
f = 10Hz to
100kHz, IOUT =
15mA, VSYS =
3.7V, VIN_LDO =
2.05V, VLDO =
1.85V
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-2.5
+2.5
%
-3
+3
%
Main bias circuits
are in normal-power
mode (SBIA_LPM
= 0)
550
Main bias circuits are
in low-power mode
(SBIA_LPM = 1)
800
μVRMS
Maxim Integrated │ 20
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—LDO (continued)
(VSYS = 3.7V, VIN_LDO = 2.05V, VLDO = 1.85V, CLDO = 10μF, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.6
1.25
ms
1.25
2.50
mV/μs
90
180
mV
100
200
Ω
+0.1
+1.0
TIMING CHARACTERISTICS
Enable Delay
TA = +25°C
Soft-Start Slew Rate
VLDO from 10% to 90% of final value.
TA = +25°C
dV/dtSS
0.5
POWER STAGE CHARACTERISTICS
Dropout Voltage
VLDO_DO
VSYS = 3.7V, 1.85V programmed output
voltage (TV_LDO[6:0] = 0x20), VIN_LDO =
1.8V, ILDO = 150mA (Note 5)
Active-Discharge
Impedance
RAD_LDO
Regulator disabled, active discharge
enabled (ADE_LDO = 1)
Disabled Output
Leakage Current
Regulator disabled,
active discharge
disabled (ADE_
LDO = 0), VSYS =
VIN_LDO = 5.5V,
VLDO = 5.5V and
0V
Dropout On-Resistance
VSYS = 3.7V,
1.85V programmed
output voltage
(TV_LDO[6:0] =
0x20), VIN_LDO =
1.8V, ILDO = IMAX,
(Note 5)
RDSON
TA = +25°C (Note 7)
50
μA
TA = +85°C
+1.0
TA = +25°C
0.6
0.9
Ω
TA = +85°C
1.2
Note 5: Dropout is the condition where the input voltage is in its valid input range but the output cannot be properly regulated
because the input voltage is not sufficiently higher than the output voltage. The dropout voltage is the difference between
the input voltage and the output voltage when the regulator is in dropout. The dropout on-resistance is the resistance of the
power MOSFET between the input and the output when the regulator is in dropout. Generally speaking, applications should
avoid dropout by having sufficient input voltage. A dropout detection interrupt is available (DOD_R; see the Programmer’s
Guide for more information). For example, applications with the output voltage target of 1.85V and the maximum load current is 80mA (ILDO_MAX), has a dropout voltage of 96mV (VLDO_DO = ILDO_MAX x RDSON_LDO = 80mA x 1.2Ω =
96mV). To avoid dropout, the input voltage should be 1.95V (VIN_LDO = VLDO + VLDO_DO).
Note 6: Guaranteed by design and characterization but not directly production tested. Production test coverage is provided by the
shutdown supply current and quiescent supply current specification in the Electrical Characteristics—Top Level table.
Note 7: Guaranteed by design and characterization but not directly production tested. The ability to disconnect the active discharge
resistance is functionally checked in a production test.
www.maximintegrated.com
Maxim Integrated │ 21
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Current Sinks
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
6
12
µA
TA = +25ºC
+0.1
+1.0
TA = +85ºC
+1.0
GENERAL CHARACTERISTICS
Current Sink Quiescent
Current
IQ
Change in supply current at SYS when one
channel is enabled and delivering 12.8mA,
VLEDx = 0.2V
All current sink
drivers combined,
outputs disabled,
VLEDx = 5.5V
Current Sink Leakage
µA
3.2mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b01, VLEDx = 0.2V)
Minimum Sink Current
BRT_LEDx[4:0] = 0b00000
0.1
mA
Maximum Sink Current
BRT_LEDx[4:0] = 0b11111
3.2
mA
Current Sink DAC Bits
5
bits
Current Sink DAC LSB
0.1
mA
Current Sink Accuracy
Dropout Voltage
VDO
TA = +25ºC
3.10
3.20
3.25
TA = -40ºC to +85ºC
3.03
3.20
3.36
35
70
BRT_LEDx[4:0] = 0b11111, ILEDx = 2.9mA
mA
mV
6.4mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b10, VLEDx = 0.2V)
Minimum Sink Current
BRT_LEDx[4:0] = 0b00000
0.2
Maximum Sink Current
BRT_LEDx[4:0] = 0b11111
6.4
mA
5
bits
Current Sink DAC Bits
Current Sink DAC LSB
0.2
Current Sink Accuracy
Dropout Voltage
mA
VDO
mA
TA = +25ºC
6.30
6.40
6.50
TA = -40ºC to +85ºC
6.06
6.40
6.72
35
70
LED_FSx[1:0] = 0b11, BRT_LEDx[4:0] =
0b11111, ILEDx = 5.75mA
mA
mV
12.8mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b11, VLEDx = 0.2V)
Minimum Sink Current
BRT_LEDx[4:0] = 0b00000
0.4
mA
Maximum Sink Current
BRT_LEDx[4:0] = 0b11111
12.8
mA
5
bits
Current Sink DAC Bits
Current Sink DAC LSB
0.4
Current Sink Accuracy
Dropout Voltage
VDO
mA
TA = +25ºC
12.6
12.8
13.0
TA = -40ºC to +85ºC
12.16
12.80
13.44
35
70
mV
32.0
38.4
Hz
BRT_LEDx[4:0] = 0b11111, ILEDx = 11.5mA
mA
TIMING CHARACTERISTICS
Root Clock Frequency
www.maximintegrated.com
25.6
Maxim Integrated │ 22
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—Current Sinks (continued)
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS/BLINK PERIOD SETTINGS
Minimum Blink Period
Maximum Blink Period
Blink Period LSB
0.5
s
16
clocks
8
s
256
clocks
0.5
s
16
clocks
6.25
%
100
%
6.25
%
TIMING CHARACTERISTICS/BLINK DUTY CYCLE
Minimum Blink Duty Cycle
D_LEDx[3:0] = 0b0000
Maximum Blink Duty Cycle
D_LEDx[3:0] = 0b1111
Blink Duty Cycle LSB
Electrical Characteristics—I2C
(VSYS = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
1.8
3.6
V
VIO = 3.6V, VSDA = VSCL = 0V or 3.6V,
TA = +25°C
-1
0
+1
VIO = 1.7V, VSDA = VSCL= 0V or 1.7V
-1
0
+1
POWER SUPPLY
VIO Voltage Range
VIO
VIO Bias Current
μA
SDA AND SCL I/O STAGE
SCL, SDA Input High
Voltage
VIH
VIO = 1.7V to 3.6V
SCL, SDA Input Low
Voltage
VIL
VIO = 1.7V to 3.6V
SCL, SDA Input
Hysteresis
VHYS
SCL, SDA Input
Leakage Current
II
SDA Output Low
Voltage
VOL
SCL, SDA Pin
Capacitance
CI
Output Fall Time from
VIH to VIL (Note 2)
tOF
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0.7 x
VIO
V
0.3 x
VIO
0.05 x
VIO
VIO = 3.6V, VSCL = VSDA = 0V and 3.6V
-10
Sinking 20mA
V
V
+10
μA
0.4
V
10
pF
120
ns
Maxim Integrated │ 23
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—I2C (continued)
(VSYS = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1000
kHz
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST AND FAST MODE PLUS) (Note 8)
Clock Frequency
fSCL
0
tHD;STA
0.26
μs
SCL Low Period
tLOW
0.5
μs
SCL High Period
tHIGH
0.26
μs
Setup Time REPEATED
START Condition
tSU_STA
0.26
μs
Data Hold Time
tHD_DAT
0
μs
Data Setup Time
tSU_DAT
50
ns
Setup Time for STOP
Condition
tSU_STO
0.26
μs
Bus Free Time between
STOP and START
Condition
tBUF
0.5
μs
Pulse Width of Suppressed Spikes
tSP
Hold Time (REPEATED)
START Condition
Maximum pulse width of spikes that must
be suppressed by the input filter
50
ns
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 8)
Clock Frequency
fSCL
3.4
MHz
Setup Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
SCL Low Period
tLOW
160
ns
SCL High Period
tHIGH
60
ns
Data Setup Time
tSU_DAT
10
ns
Data Hold Time
tHD_DAT
0
70
ns
SCL Rise Time
trCL
TA = +25°C
10
40
ns
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
trCL1
TA = +25°C
10
80
ns
SCL Fall Time
tfCL
TA = +25°C
10
40
ns
SDA Rise Time
trDA
TA = +25°C
10
80
ns
SDA Fall Time
tfDA
TA = +25°C
10
80
ns
Setup Time for STOP
Condition
tSU_STO
Bus Capacitance
CB
Pulse Width of Suppressed Spikes
tSP
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160
ns
100
Maximum pulse width of spikes that must
be suppressed by the input filter
10
pF
ns
Maxim Integrated │ 24
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Electrical Characteristics—I2C (continued)
(VSYS = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
MHz
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 8)
Clock Frequency
fSCL
Setup Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
SCL Low Period
tLOW
320
ns
SCL High Period
tHIGH
120
ns
Data Setup Time
tSU_DAT
10
Data Hold Time
tHD_DAT
0
150
ns
SCL Rise Time
tRCL
TA = +25°C
20
80
ns
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
tRCL1
TA = +25°C
20
80
ns
SCL Fall Time
tFCL
TA = +25°C
20
80
ns
SDA Rise Time
tRDA
TA = +25°C
20
160
ns
SDA Fall Time
tFDA
TA = +25°C
20
160
ns
Setup Time for STOP
Condition
Bus Capacitance
Pulse Width of
Suppressed Spikes
tSU_STO
ns
160
ns
CB
tSP
400
Maximum pulse width of spikes that must
be suppressed by the input filter
10
pF
ns
Note 8: Design guidance only. Not production tested.
www.maximintegrated.com
Maxim Integrated │ 25
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, TA = +25°C, unless otherwise noted.)
5
toc 01
6
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS OFF (SBIA_EN = 0)
TA = +85°C
TA = +25°C
TA = -40°C
TA = +85°C
TA = +25°C
TA = -40°C
30
2
20
1
1
10
3.5
4.5
0
5.5
2.5
QUIESCENT SUPPLY CURRENT
vs. BATTERY VOLTAGE
8
6
5
10
9
4
86
6
4
2
1
1
4.5
0
5.5
-40
-15
10
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB2_EFFECTIVE = 3µF
3.45
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
3.50
toc 06
78
70
IP_SBB2 = 3
IP_SBB2 = 2
IP_SBB2 = 1
IP_SBB2 = 0
0.1
1
85
toc 07
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB2_EFFECTIVE = 3µF
IP_SBB2 = 0
IP_SBB2 = 1
IP_SBB2 = 2
IP_SBB2 = 3
3.40
3.35
3.30
3.25
10
100
OUTPUT CURRENT (mA)
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60
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER PEAK CURRENT LIMIT)
SBB2 EFFICIENCY vs. OUTPUT CURRENT
(VSBB2 = 3.3V, PER PEAK CURRENT LIMIT)
80
72
35
TEMPERATURE (°C)
82
74
toc 05
5
3
3.5
5.5
SBB0, SBB1, SBB2, LDO ENABLED
SBB0, SBB1, SBB2 ENABLED
SBB0, SBB1 ENABLED
SBB0 ENABLED
7
2
2.5
4.5
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
8
3
84
76
3.5
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
VBATT (V)
88
2.5
VBATT (V)
toc 04
SBB0, SBB1, SBB2, LDO ENABLED
SBB0, SBB1, SBB2 ENABLED
SBB0, SBB1 ENABLED
SBB0 ENABLED
7
0
0
5.5
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
9
IBATT (µA)
4.5
VBATT (V)
VBATT (V)
10
3.5
IBATT (µA)
2.5
TA = +85°C
TA = +25°C
TA = -40°C
40
3
toc 03
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS ON (SBIA_EN = 1)
NORMAL-POWER MODE (SBIA_LPM = 0)
50
2
0
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
60
4
IBATT (µA)
IBATT (µA)
toc 02
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
5
4
3
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
IBATT (µA)
6
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
1000
3.20
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
Maxim Integrated │ 26
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER PEAK CURRENT LIMIT)
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 2.05V, PER PEAK CURRENT LIMIT)
86
toc08
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
82
80
76
74
IP_SBB0 = 3
IP_SBB0 = 2
IP_SBB0 = 1
IP_SBB0 = 0
0.1
2.15
1
10
100
1000
84
2.05
0.1
1
10
100
10
100
80
78
76
70
1000
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER DRIVE STRENGTH)
toc13
IP_SBB2 = 3, VIN_SBB = 3.7V
CSBB2_EFFECTIVE = 3µF
1000
82
72
1
100
84
74
0.1
10
toc12
OUTPUT CURRENT (mA)
100
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
90
3.32
3.30
CHGIN SUPPLY CURRENT vs.
CHGIN VOLTAGE
(USB SUSPENDED)
toc 14
VCHGIN RISING
80
70
3.34
ICHGIN (µA)
OUTPUT VOLTAGE (V)
1
IP_SBB2 = 3, VIN_SBB = 3.7V
CSBB2_EFFECTIVE = 3µF
86
1.19
60
50
40
30
20
3.28
3.26
0.1
SBB2 EFFICIENCY
vs. OUTPUT CURRENT
(VSBB2 = 3.3V, PER DRIVE STRENGTH)
88
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
1.20
3.36
76
OUTPUT CURRENT (mA)
toc 11
1.21
3.38
78
70
1000
IP_SBB1 = 0
IP_SBB1 = 1
IP_SBB1 = 2
IP_SBB1 = 3
1.22
1.18
80
72
SBB1 LOAD REGULATION
(VSBB1 = 1.2V, PER PEAK CURRENT LIMIT)
1.23
82
OUTPUT CURRENT (mA)
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB1_EFFECTIVE = 8µF
IP_SBB1 = 3
IP_SBB1 = 2
IP_SBB1 = 1
IP_SBB1 = 0
74
OUTPUT CURRENT (mA)
1.24
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB1_EFFECTIVE = 8µF
86
2.10
1.95
toc10
88
IP_SBB0 = 0
IP_SBB0 = 1
IP_SBB0 = 2
IP_SBB0 = 3
2.00
72
70
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB0_EFFECTIVE = 5µF
2.20
84
78
toc 09
2.25
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB0_EFFECTIVE = 5µF
EFFICIENCY (%)
88
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER PEAK CURRENT LIMIT)
10
0.1
1
10
100
OUTPUT CURRENT (mA)
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1000
0
3.5
4.0
4.5
5.0
5.5
6.0
VCHGIN (V)
Maxim Integrated │ 27
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER DRIVE STRENGTH)
88
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
86
82
2.06
2.05
5.0
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
4.5
78
76
1
10
100
1000
70
0.0
1
CHARGE PROFILE, 110mAh BATTERY
toc 18
VPQ = 3V, IPQ = 10%
IFAST-CHG = 75mA, VFAST-CHG = 4.2V
4.0
VBATT (V)
1.0
0.5
0.0
88
86
0.075
0.060
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
BEHAVIOR
1.5
0.0
3.38
0.150
3.36
0.105
IBATT (A)
1.0
0.045
0.030
3.32
3.30
0.1
1
10
100
1000
SBB2 LOAD REGULATION
(VSBB2 = 2.5V, PER INPUT VOLTAGE)
toc20
2.58
DRV_SBB = 0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 5µF
80
2.56
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 5.0V
VIN_SBB = 3.3V
VIN_SBB = 5.5V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
78
76
74
72
0.1
1
toc21
DRV_SBB = 0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 5µF
2.54
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
2.52
2.50
2.48
10
100
OUTPUT CURRENT (mA)
www.maximintegrated.com
0.000
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
SBB2 EFFICIENCY vs. OUTPUT CURRENT
(VSBB2 = 2.5V, PER INPUT VOLTAGE)
82
3.0
toc19
DRV_SBB=0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 3µF
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
2.0
TIME (hr)
84
70
1.0
3.34
3.26
0.000
3.0
0.006
3.28
0.015
2.0
0.012
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER INPUT VOLTAGE)
0.090
2.0
0.0
0.018
TIME (hr)
0.120
3.0
2.5
1000
0.135
VBATT (V)
3.5
100
0.024
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
BEHAVIOR
OUTPUT CURRENT (mA)
IBATT (A)
4.5
10
0.030
IBATT (A)
2.0
0.5
0.1
0.042
0.036
2.5
1.0
OUTPUT CURRENT (mA)
5.0
0.048
3.0
72
0.060
0.054
VBATT (V)
1.5
74
0.1
toc 17
3.5
80
2.04
CHARGE PROFILE, 40mAh BATTERY
VPQ = 3V, IPQ = 10%
IFAST-CHARGE = 30mA, VFAST-CHARGE = 4.2V
4.0
VBATT (V)
2.07
2.03
toc16
IP_SBB1 = 3, VIN_SBB = 3.7V
CSBB1_EFFECTIVE = 8µF
84
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
2.08
toc15
IP_SBB0 = 3, VIN_SBB = 3.7V
CSBB0_EFFECTIVE = 5µF
OUTPUT VOLTAGE (V)
2.09
1000
2.46
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
Maxim Integrated │ 28
IBATT (A)
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER DRIVE STRENGTH)
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
88
86
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 2.05V, PER INPUT VOLTAGE)
toc22
2.09
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
2.08
82
80
78
76
74
72
70
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
84
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
0.1
1
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER INPUT VOLTAGE)
toc23
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
2.07
2.06
2.05
2.04
10
100
2.03
1000
OUTPUT CURRENT (mA)
0.1
86
toc24
1.89
1.88
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
84
82
80
78
88
86
10
100
1000
toc25
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
1.87
1.86
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
1.85
1.83
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 1.5V, PER INPUT VOLTAGE)
SBB0 LOAD REGULATION
(VSBB0 = 1.5V, PER INPUT VOLTAGE)
toc26
1.54
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 6µF
1.53
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
100
1.84
84
82
80
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
78
76
74
72
70
10
SBB0 LOAD REGULATION
(VSBB0 = 1.85V, PER INPUT VOLTAGE)
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
VIN_SBB = 3.7V
VIN_SBB = 3.3V
76 VIN_SBB = 4.2V
VIN_SBB = 3.0V
74
VIN_SBB = 2.8V
72 VIN_SBB = 5.0V
VIN_SBB = 5.5V
70
0.1
1
1
OUTPUT CURRENT (mA)
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 1.85V, PER INPUT VOLTAGE)
88
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
0.1
1
10
100
OUTPUT CURRENT (mA)
www.maximintegrated.com
toc27
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 6µF
1.52
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
1.51
1.50
1.49
1000
1.48
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
Maxim Integrated │ 29
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
86
EFFICIENCY (%)
84
82
80
toc28
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
1.24
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
1.23
OUTPUT VOLTAGE (V)
88
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER INPUT VOLTAGE)
78
76
74
86
EFFICIENCY (%)
84
82
80
78
0.1
1
10
100
toc30
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
1.04
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
1.03
1
10
100
1000
toc31
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
1.02
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
1.01
1.00
0.99
0.1
1
10
100
0.98
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 0.8V, PER INPUT VOLTAGE)
SBB1 LOAD REGULATION
(VSBB1 = 0.8V, PER INPUT VOLTAGE)
toc32
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 9µF
82
80
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
0.84
0.83
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
0.1
SBB1 LOAD REGULATION
(VSBB1 = 1.0V, PER INPUT VOLTAGE)
84
78
76
74
toc33
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 9µF
0.82
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
0.81
0.80
0.79
72
70
1.20
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.0V, PER INPUT VOLTAGE)
72
86
1.21
OUTPUT CURRENT (mA)
74
88
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
OUTPUT CURRENT (mA)
76
70
1.22
1.18
1000
OUTPUT VOLTAGE (V)
88
toc29
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
1.19
72
70
SBB1 LOAD REGULATION
(VSBB1 = 1.2V, PER INPUT VOLTAGE)
0.1
1
10
100
OUTPUT CURRENT (mA)
www.maximintegrated.com
1000
0.78
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
Maxim Integrated │ 30
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
SIMO LINE TRANSIENT
L=2.2µH
VIN_SBB
VOUTN
4.2V
SBB2 LOAD TRANSIENT
toc 34
ISBB0 = ISBB1 = ISBB2 = 10mA
3.2V
VSBB2
VSBB2
50mV/div
1V/div
IP_SBBx SET TO 500mA
LOW-POWER MODE
IP_SBB2 = 866mA, VSBB2 = 3.3V, CSBB2_EFF = 6µF
VINSIDE = 500mA, V
IP_SBB1
SBB1 = 1.2V, CSBB1_EFF = 8µF
IP_SBB0 = 707mA, VSBB0 = 2.05V, CSBB0_EFF = 5µF
VBACKUP
VSBB1
VSBB0
50mV/div
VSBB1
50mV/div
VSBB0
50mV/div
1.2V
CSBB1_EFF = 8µF
ISBB1 = 10mA
2.05V CSBB0_EFF = 5µF
ISBB0 = 10mA
VSBB2
10mA
ISBB2
VSBB0
ISBB2 = 10mA
1.2V CSBB1_EFF = 8µF
VSBB2
50mV/div
3.3V
CSBB2_EFF = 6µF
ISBB0 = 10mA
100mA
VSBB1
VSBB0
50mV/div
1.2V
10mA
VSBB0
500mA/div
10mA
4µs/div
www.maximintegrated.com
100mA/div
SIMO SWITCHING WAVEFORMS
MEDIUM UTILIZATION 25mA PER CHANNEL
SIMO SWITCHING WAVEFORMS
HEAVY UTILIZATION 75mA PER CHANNEL
toc 39
toc 40
IL
500mA/div
50mV/div
VSBB2
50mV/div
VSBB1
50mV/div
VSBB0
50mV/div
IP_SBB1 = 500mA, VSBB1 = 1.2V, CSBB1_EFF =8µF
IP_SBB2 = 707mA, VSBB0 = 2.05V, CSBB0_EFF = 5µF
4µs/div
IL
IP_SBB2 = 1000mA, VSBB2 = 3.3V, CSBB2_EFF =3µF
50mV/div
50mV/div
VSBB1
500mA/div
50mV/div
VSBB2
IP_SBB2 = 866mA, VSBB2 = 3.3V, CSBB2_EFF = 3µF
IP_SBB2 = 500mA, VSBB2 = 3.3V, CSBB2_EFF = 3µF
IP_SBB2 = 500mA, VSBB0 = 2.05V, CSBB0_EFF = 5µF
50mV/div
40µs/div
toc 38
IP_SBB1 = 500mA, VSBB1 = 1.2V, CSBB1_EFF = 8µF
50mV/div
2.05V CSBB0_EFF = 5µF
ISBB0
100mA/div
SIMO SWITCHING WAVEFORMS
LIGHT UTILIZATION 10mA PER CHANNEL
VSBB2
ISBB1 = 10mA
CSBB1_EFF = 8µF
40µs/div
VSBB1
50mV/div
100mA
ISBB1
IL
toc 37
ISBB2 = 10mA
IP_SBBx SET TO 500mA
LOW-POWER MODE
50mV/div
2.05V CSBB0_EFF = 5µF
100mA/div
SBB0 LOAD TRANSIENT
toc 36
IP_SBBx SET TO 500mA
LOW-POWER MODE
VSBB1
50mV/div
40µs/div
SBB1 LOAD TRANSIENT
CSBB2_EFF = 6µF
50mV/div
80mA
10µs/div
3.3V
toc 35
CSBB2_EFF = 6µF
3.3V
IP_SBB1 = 1000mA, VSBB1 = 1.2V, CSBB1_EFF = 8µF
50mV/div
IP_SBB2 = 1000mA, VSBB0 = 2.05V, CSBB0_EFF =5µF
VSBB0
50mV/div
4µs/div
Maxim Integrated │ 31
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
LDO LINE REGULATION
LDO LOAD REGULATION
1.95
1.93
toc41
VLDO TARGET VOLTAGE = 1.85V
1.93
3.0 VIN_LDO
4.2 VIN_LDO
5.5 VIN_LDO
1.91
1.89
1.85
1.83
1.79
1.77
1.77
0.100
0.125
2.35V
1.75
0.150
VIN_LDO
2.05V
200mV/div
1.83
1.81
0.075
toc 43
1.85
1.79
0.050
TA= +85°C
TA= +25°C
TA= -20°C
1.87
1.81
0.025
NO LOAD
1.89
1.87
1.75
0.000
LDO LINE TRANSIENT
toc42
1.91
VLDO (V)
VLDO (V)
1.95
VLDO
3.0
ILDO (A)
4.0
5.0
1mV/div
6.0
200µs/div
VIN_LDO (V)
LDO LOAD TRANSIENT
1.85V
VLDO
LDO LOAD TRANSIENT
toc 44
1.85V
VLDO
50mV/div
toc 45
50mV/div
135mA
80mA
5mA
ILDO
15mA
ILDO
50mV/div
100µs/div
100µs/div
LDO LOAD TRANSIENT
1.85V
LDO POWER-SUPPLY
REJECTION RATIO
toc 46
toc 47
60
VIN_LDO AVERAGE = 2.05V
VLDO AVERAGE = 1.85V
LOAD = 15mA
50
50mV/div
40
PSRR (dB)
VLDO
50mV/div
150mA
30
20
ILDO
2mA
50mV/div
100µs/div
10
0
0.1
1
10
100
1000
INPUT FREQUENCY (kHz)
www.maximintegrated.com
Maxim Integrated │ 32
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
CHGIN SUPPLY CURRENT
vs. CHGIN VOLTAGE
1.8
1.6
CHGIN SUPPLY CURRENT
vs. CHGIN VOLTAGE
toc48
ISYS = 0mA
VCHGIN RISING
1.4
80
70
ICHGIN (µA)
ICHGIN (mA)
VC HGIN RISING
90
1.2
1.0
0.8
0.6
60
50
40
30
0.4
20
0.2
10
0.0
toc 49
100
VBATT = 2.7V
VBATT = 3.6V
VBATT = 4.4V
0
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
3.5
4.0
VCHGIN (V)
9
CHARGER DISABLED
VCHGIN = 5V
TA = +85°C
TA = +25°C
TA = -40°C
0.14
RDS-ON (Ω)
6
IBATT (µA)
IBATT = 10mA
IBATT = 100mA
IBATT = 300mA
0.15
5
4
3
0.13
0.12
0.11
0.10
2
0.09
1
2.5
3.0
3.5
4.0
0.08
4.5
2.5
3.0
VBATT (V)
VBATT (V)
3.7
IBATT (A)
3.5
4.5
0.045
4.3
0.040
4.1
0.035
3.9
0.030
3.7
0.025
3.3
0.020
3.1
0.015
2.7
0.000
2.5
TIME (hr)
www.maximintegrated.com
2.0
2.5
IBATT (A)
0.090
BATTERY
LOADED DURING
THE "DONE"
STATE TO SHOW
THE RESTART
BEHAVIOR
3.1
2.9
1.5
5.0
0.0
0.5
1.0
TIME (hr)
0.045
0.030
0.015
1.5
2.0
2.5
toc54
ICHGIN_LIM = 95mA
ICHGIN = 30mA
VSYS_REG = 4.5V
0mA
ISYS
0.105
0.060
0.005
1.0
0.120
3.3
0.010
0.5
4.5
125mA
0.135
VBATT (V)
0.075
2.7
0.0
0.150
3.5
2.9
2.5
toc53
VPQ = 3V, IPQ = 10%
IFAST-CHG = 90mA, VFAST-CHG = 4.2V
100mA/div
95mA
IBATT (A)
VBATT (V)
3.9
0.050
VBATT (V)
toc52
VPQ = 3V, IPQ = 10%
IFAST-CHARGE = 30mA, VFAST-CHARGE = 4.2V
4.0
SYS LOAD TRANSIENT
CAUSING BATTERY SUPPLEMENT
CHARGE PROFILE, 110mAh BATTERY
IBATT (A)
4.1
3.5
VBATT (V)
CHARGE PROFILE, 40mAh BATTERY
4.3
6.0
toc 51
0.16
7
4.5
5.5
SYS TO BATT IMPEDANCE
toc 50
8
0
5.0
VCHGIN (V)
BATT BIAS CURRENT vs. BATT
10
4.5
ICHGIN
0mA
IBATT
VSYS
30mA
0mA
4.5V
100mA/div
30mA DISCHARGING
100mA/div
30mA CHARGING
1V/div
3.7V
0.000
1ms/div
Maxim Integrated │ 33
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
POWER UP
NO LOAD
POWER DOWN
NO LOAD
toc55
VSBB2
VSBB0
VSBB1
VLDO
VnRST
IBATT
1V/div
1V/div
1V/div
1V/div
1V/div
2V/div
1V/div
1V/div
1V/div
2V/div
50mA/div
50mA/div
VSBB0
VSBB1
VLDO
VnRST
IBATT
2ms/div
4ms/div
POWER UP
10mA LOAD PER CHANNEL
VSBB2
VSBB0
VLDO
toc56
VSBB2
VSBB1
VnRST
POWER DOWN
10mA LOAD PER CHANNEL
toc57
1V/div
1V/div
1V/div
1V/div
1V/div
2V/div
1V/div
1V/div
1V/div
2V/div
toc58
VSBB2
VSBB0
VSBB1
VLDO
VnRST
IBATT
50mA/div
IBATT
2ms/div
www.maximintegrated.com
50mA/div
4ms/div
Maxim Integrated │ 34
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
6
A
PWR_
HLD
nEN
SDA
LED2
LED1
LED0
B
GPIO
nRST
LGND
SCL
LDO
IN_LDO
C
AMUX
nIRQ
GND
VIO
BST
SBB0
D
VL
THM
TBIAS
LXA
LXB
SBB1
E
CHGIN
SYS
BATT
IN_SBB
PGND
SBB2
+
WLP
(2.75mm x 2.15mm)
Pin Description
PIN
NAME
FUNCTION
TYPE
TOP LEVEL
A2
nEN
Active-Low Enable Input. nEN supports pushbutton or slide-switch configurations.
C2
nIRQ
Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between nIRQ and a
digital output
voltage equal to or less than VSYS.
B2
nRST
Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between nRST and a
voltage equal to or less than VSYS.
A1
digital input
Active-High Power Hold Input. Assert PWR_HLD to keep the on/off controller in its on through
PWR_HLD on/off controller state. If PWR_HLD is not needed, connect it to SYS and use the SFT_RST bits
to power down the device.
General-Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.
digital output
digital input
B1
GPIO
C4
VIO
I2C Interface and GPIO Driver Power
power input
B4
SCL
I2C Clock
digital input
A3
SDA
I2C Data
digital I/O
C3
GND
Quiet Ground. Connect GND to PGND, LGND, and the low-impedance ground plane of the
PCB.
www.maximintegrated.com
digital I/O
ground
Maxim Integrated │ 35
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Pin Description (continued)
PIN
NAME
FUNCTION
TYPE
CHARGER
E1
CHGIN
Charger Input. Connect to a DC charging source. Bypass to GND with a 4.7μF ceramic capacitor.
power input
E2
SYS
System Power Output. SYS provides power to the system resources as well as the control logic
power output
of the device. Connect SYS to IN_SBB and bypass to GND with a 22μF ceramic capacitor.
E3
BATT
Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with a 4.7μF
ceramic capacitor.
D1
VL
Internal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a 1μF ceramic
capacitor. Do not load VL externally.
power
D3
TBIAS
Thermistor Bias Supply. Connect a resistor equal to the NTC's room temperature resistance
between TBIAS and THM. Do not load TBIAS with any other external circuitry.
analog
D2
THM
Thermistor Monitor. Thermally couple an NTC to the battery and connect between THM and GND.
analog input
AMUX
Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power
signals.
analog output
Linear Regulator Output
power output
C1
power I/O
LDO
B5
LDO
B6
IN_LDO
Linear Regulator Input
power input
RGB LED DRIVER
A6
LED0
Current Sink Port 0. LED0 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused.
power
A5
LED1
Current Sink Port 1. LED1 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused.
power
A4
LED2
Current Sink Port 2. LED2 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused.
power
B3
LGND
Current Sink Ground. Connect LGND to GND, PGND, and the low-impedance ground plane of
the PCB.
ground
SIMO BUCK BOOST
SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a 10uF ceramic
capacitor as close as possible to the IN_SBB pin.
E4
IN_SBB
C6
SBB0
SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost.
Bypass SBB0 to PGND with a 10μF ceramic capacitor.
power output
D6
SBB1
SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost.
Bypass SBB1 to PGND with a 10μF ceramic capacitor.
power output
E6
SBB2
SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost.
Bypass SBB2 to PGND with a 10μF ceramic capacitor.
power output
C5
BST
SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic capacitor between BST and LXB.
power input
D4
LXA
Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor
between LXA and LXB.
power I/O
D5
LXB
Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is
driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA
and LXB.
power I/O
E5
PGND
Power ground for the SIMO low-side FETs. Connect PGND to GND, LGND, and the low-impedance ground plane of the PCB.
ground
www.maximintegrated.com
power input
Maxim Integrated │ 36
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Detailed Description
Support Materials
The MAX77650/MAX77651 provide a highly-integrated
battery charging and power management solution for lowpower applications. The linear charger provides a wide
range of charge current and charger termination voltage
options to charge various Li+ batteries. Temperature
monitoring and JEITA compliance settings add additional
functionality and safety to the charger. Four regulators
are integrated within this device (see Table 1). A singleinductor, multiple output (SIMO) buck-boost regulator
efficiently provides three independently programmable
power rails. A 150mA LDO provides ripple rejection for
audio and other low-noise applications.
The system includes other features such as current sinks
for driving LED indicators and an analog multiplexer that
switches several internal voltage and current signals to
an external node for monitoring with an external ADC.
A bidirectional I2C serial interface allows for configuring
and checking the status of the device. An internal on/off
controller provides regulator sequencing and supervisory
functionality for the device.
Support materials are available to assist engineering
teams in designing with this device. For example, a full
description of the register bits along with software advice
is available in the Programmer’s Guide. Visit the product
page at www.maximintegrated.com/MAX77650 and/
or contact Maxim for more information on support documents.
Top-Level Interconnect Simplified Diagram
Figure 1 shows the same major blocks as the Typical
Application Circuit with an increased emphasis on the
routing between each block. This diagram is intended
to familiarize the user with the landscape of the device.
Many of the details associated with these signals are
discussed throughout the data sheet. At this stage of
the data sheet, note the addition of the main bias and
clock block that are not shown in the Typical Applications
Circuit. The main bias and clock block provides voltage,
current, and clock references for other blocks as well as
many resources for the top-level digital control.
Table 1. Regulator Summary
REGULATOR
NAME
REGULATOR
TOPOLOGY
MAXIMUM I OUT
(mA)
V IN RANGE (V)
MAX77650 V OUT
RANGE/
RESOLUTION
MAX77651 V OUT
RANGE/
RESOLUTION
SBB0
SIMO
Up to 300*
2.7 to 5.5
0.8V to 2.375V in
25mV steps
0.8 to 2.375V in
25mV steps
SBB1
SIMO
Up to 300*
2.7 to 5.5
0.8V to 1.5875V in
12.5mV steps
2.4 to 5.25V in
50mV steps
SBB2
SIMO
Up to 300*
2.7 to 5.5
0.8V to 3.95V in
50mV steps
2.4 to 5.25V in
50mV steps
LDO
PMOS LDO
150
1.8 to 5.5
1.35V to 2.9375V in
12.5mV steps
1.35 to 2.9375V in
12.5mV steps
*Shared capacity with other SBBx channels. See the SIMO Available Output Current section for more information.
www.maximintegrated.com
Maxim Integrated │ 37
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
VREF
VIREF
SYSRST
nEN
COMM
MAX77650/MAX77651
IRQ_CHG
CHARGER
and
MUX
IRQ_CHG
CHGINPOK
MAIN BIAS
AND CLOCK
SYSUVLO
SYSOVLO
OTLO
POR
BOK
BIAS_EN
SBIA_LPM
SYSRST
FPS
100us/30ms
DEBOUNCE
TIMER
tDBNC_nEN
LDO
CLK
VREF
VIREF
SYSRST
COMM
CURRENT
SINK
DBEN_nEN
DBNEN
100us
GLITCH FILTER
tPWR_HLD_GF
AMUX
AMUX
VIO
PWR_HLD
VREF
VIREF
SYSRST
FPS
COMM
IRQ_CHG
SYS
nEN
SIMO
AMUX
CLK
VREF
VIREF
SYS
VREF
VIREF
SYSRST
FPS
COMM
TOP-LEVEL
DIGITAL
CONTROL
nRST
STAT_PWR_HLD
PWR_HLD2
CHGINPOK
RST
nIRQ
IRQ_TOP
VIO
GPIO
10ns/30ms
DEBOUNCE
TIMER
tDBNC_nEN
DBEN_GPI
DI
SDA
COMM
I 2C
SCL
DO
Figure 1. Top-Level Interconnect Simplified Diagram
www.maximintegrated.com
Maxim Integrated │ 38
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Global Resources
The global resources encompass a set of circuits that
serve the entire device and ensure safe, consistent, and
reliable operation.
Features and Benefits
●● Voltage Monitors
• SYS POR (power-on-reset) comparator generates
a reset signal upon power-up
• SYS undervoltage ensures repeatable behavior when
power is applied to and removed from the device
• SYS overvoltage monitor inhibits operation with
overvoltage power sources to ensure reliability in
faulty environments
●● Thermal Monitors
• 165°C junction temperature shutdown
●● Manual Reset
• 8s or 16s period
●● Wakeup Events
• Charger insertion (with 120ms debounce)
• nEN input assertion
●● Interrupt Handler
• Interrupt output (nIRQ)
• All interrupts are maskable
●● Pushbutton/Slide-Switch Onkey (nEN)
• Configurable pushbutton/slide-switch functionality
• 100μs or 30ms debounce timer interfaces directly
with mechanical switches
●● On/Off Controller
• Startup/shut-down sequencing
• Programable sequencing delay
●● PWR_HLD, GPIO, RST Digital I/Os
Voltage Monitors
The device monitors the system voltage (VSYS) to ensure
proper operation using three comparators (POR, UVLO,
and OVLO). These comparators include hysteresis to
prevent their outputs from toggling between states during
noisy system transitions.
SYS POR Comparator
The SYS POR comparator monitors VSYS and generates
a power-on reset signal (POR). When VSYS is below
VPOR, the device is held in reset (SYSRST = 1). When
VSYS rises above VPOR, internal signals and on-chip
memory stabilize and the device is released from reset
(SYSRST = 0).
SYS Undervoltage Lockout Comparator
The SYS undervoltage lockout (UVLO) comparator monitors VSYS and generates a SYSUVLO signal when the
VSYS falls below UVLO threshold. The SYSUVLO signal
is provided to the top-level digital controller. See Figure 4
www.maximintegrated.com
and Table 2 for additional information regarding the UVLO
comparator:
●● When the device is in the STANDBY state, the UVLO
comparator is disabled.
●● When transitioning out of the STANDBY state, the
UVLO comparator is enabled allowing the device to
check for sufficient input voltage. If the device has
sufficient input voltage, it can transition to the on
state; if there is insufficient input voltage, the device
transitions back to the STANDBY state.
SYS Overvoltage Lockout Comparator
The device is rated for 5.5V maximum operating voltage
(VSYS) with an absolute maximum input voltage of 6.0V.
An overvoltage lockout monitor increases the robustness
of the device by inhibiting operation when the supply voltage is greater than VSYSOVLO. See Figure 4 and Table 2
for additional information regarding the OVLO comparator:
●● When the device is in the STANDBY state, the OVLO
comparator is disabled.
nEN Enable Input
nEN is an active-low internally debounced digital input
that typically comes from the system’s on key. The
debounce time is programmable with DBEN_nEN. The
primary purpose of this input is to generate a wake-up
signal for the PMIC that turns on the regulators. Maskable
rising/falling interrupts are available for nEN (nEN_R and
nEN_F) for alternate functionality.
The nEN input can be configured to work either with a
push-button (nEN_MODE = 0) or a slide-switch (nEN_
MODE = 1). See Figure 2 for more information. In both
pushbutton mode and slide-switch mode, the on/off controller looks for a falling edge on the nEN input to initiate
a power-up sequence.
nEN Manual Reset
nEN works as a manual reset input when the on/off controller is in the on via on/off controller state. The manual
reset function is useful for forcing a power-down in case
the communication with the processor fails. When nEN is
configured for a push-button mode and the input is asserted (nEN = low) for an extended period (tMRST), the on/off
controller initiates a power-down sequence and goes to
standby mode. When nEN is configured for a slide-switch
mode and the input is deasserted (nEN = high) for an
extended period (tMRST), the on/off controller initiates a
power-down sequence and goes to standby mode.
A dedicated internal oscillator is used to create the 30ms
(tDBNC_nEN) and 16s (tMRST) timers for nEN. Whenever
the device is actively counting either of these times, the
Maxim Integrated │ 39
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
supply current increases by the oscillator's supply current
(65μA when the battery voltage is at 3.7V). As soon as
the event driving the timer goes away or is fulfilled, the
oscillator automatically turns off and its supply current
goes away.
nEN Dual-functionality:
Push-Button vs. Slide-Switch
The nEN digital input can be configured to work with
a pushbutton switch or a slide-switch. The timing diagram below shows nEN's dual functionality for power-on
sequencing and manual reset. The default configuration
of the device is pushbutton mode (nEN_MODE = 0) and
no additional programming is necessary. Applications
that use a slide-switch on-key configuration must set
nEN_MODE = 1 within tMRST.
Interrupts (nIRQ)
Several status, interrupt, and interrupt mask registers
monitor key information and assert the nIRQ output signal when an interrupt event has occurred. Refer to the
Programmer’s Guide for a comprehensive list of all interrupt bits and status registers.
nIRQ is an active-low, open-drain output that is typically
routed to the processor's interrupt input to allow for quick
notification of interrupt events. A pullup resistor is required
for this signal. This pullup resistor is typically found
inside the processor that interprets the interrupt signal,
but a board-mounted pullup resistor is required if one is
unavailable. The pullup resistor bias voltage should be
less than or equal to VSYS.
All interrupts are masked by default. Initialization software
should unmask interrupts of interest so nIRQ can be
asserted when they occur.
Reset Output (nRST)
nRST is an open-drain, active-low output that is typically
used to hold the processor in a reset state when the device
is powered down. During a power-up sequence, the nRST
deasserts after the last regulator in the power-up chain
is enabled (tRSTODD). During a power-down sequence,
the nRST output asserts before any regulator is powered
down (tRSTOAD). See Figure 5 for nRST timing.
A pullup resistor is required for the nRST open-drain output. This pullup resistor is typically inside the processor
that is receiving the reset signal. A board-mounted pullup
resistor is required if one is unavailable inside the processor. The pullup resistor bias voltage should be less than
or equal to VSYS.
Power Hold Input (PWR_HLD)
PWR_HLD is an active-high digital input. PWR_HLD has a
100μs glitch filter (tPWR_HLD_GF). As shown in Figure 1, the
output of this glitch filter is logically ORed with the wakeup
signal coming from the charger to create a signal called
PWR_HLD2 that drives the top-level digital control.
NOT DRAWN TO SCALE
STATE
STANDBY
POWER-ON SEQUENCE
POWER-DOWN SEQUENCE
ON
BATTERY
INSERTION
VSYS
SYS
tDBNC_nEN
nEN
tDBNC_nEN
tDBNC_nEN
tMRST
PUSH-BUTTON MODE
SYS
tDBNC_nEN
nEN
tMRST
tDBNC_nEN
SLIDE-SWITCH MODE
Figure 2. nEN Usage Timing Diagram
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Maxim Integrated │ 40
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
●● When there is no valid charge voltage at CHGIN
(CHGINPOK = 0):
• After the power-up sequence, the system processor must assert PWR_HLD within the PWR_HLD
wait time (tPWR_HLD_WAIT) to hold the power
supply in the on state. If the PWR_HLD input is
not asserted within the tPWR_HLD_WAIT period, a
power-down sequence is initiated.
• While in the on state, the system processor must
assert PWR_HLD as long as power is required. If
the system processor wants to turn off, it can either
pull PWR_HLD low or it can write the SFT_RST
bits to execute the SFT_CRST or SFT_OFF functions to execute the power-down sequence.
●● If there is a valid charge voltage at CHGIN
(CHGINPOK = 1):
• The charger sends a wakeup signal to the on/off
controller which is also logically ORed with PWR_
HLD to assert PWR_HLD2. PWR_HLD2 being
asserted satisfies the on/off controller such that the
PWR_HLD signal is a don't care.
See the Figure 7, Top-Level On/Off Controller section,
and Table 2 for additional information regarding PWR_
HLD. If the power hold function is not used, connect
PWR_HLD to SYS and then use the SFT_RST bits to
power the device down.
General-Purpose Input Output (GPIO)
A general-purpose input/output (GPIO) is provided to
increase system flexibility. See Figure 3 for the GPIO
Block Diagram.
Clear DIR to configure GPIO as a general-purpose output
(GPO). The GPO can either be in push-pull mode (DRV =
1) or open-drain mode (DRV = 0).
●● The push-pull output mode is ideal for applications that
need fast (~2ns) edges and low power consumption.
●● The open-drain mode requires an external pullup
resistor (typically 10kΩ–100kΩ). Connect the external
pullup resistor to a bias voltage that is less than or
equal to VIO.
www.maximintegrated.com
• The open-drain mode can be used to communicate
to different logic domains. For example, to send a
signal from the GPO on a 1.8V logic domain (VIO =
1.8V) to a device on a 1.2V logic domain, connect
the external pullup resistor to 1.2V.
• The open-drain mode can be used to connect several open-drain (or open-collector) devices together on
the same bus to create wired logic (wired AND logic
is positive-true; wired OR logic is negative-true).
The general-purpose input (GPI) functions are still available while the pin is configured as a GPO. In other words,
the DI (input status) bit still functions properly and does
not collide with the state of the DIR bit.
Set DIR to disable the output drivers associated with the
GPO and have the device function as a GPI. The GPI
features a 30ms debounce timer (tDBNC_GPI) that can be
enabled or disabled with DBEN_GPI.
●● Enable the debounce timer (DBEN_GPI = 1) if the
GPI is connected to a device that can bounce or
chatter (like a mechanical switch).
●● If the GPI is connected to a circuit with clean logic
transitions and no risk of bounce, disable the
debounce timer (DBEN_GPI = 0) to eliminate unnecessary logic delays. With no debounce timer, the GPI
input logic propagates to nIRQ in 10ns.
A dedicated internal oscillator is used to create the 30ms
(tDBNC_GPI) debounce timer. Whenever the device is
actively counting this time, the supply current increases
by the oscillator's supply current (65μA when the battery
voltage is at 3.7V). As soon as the event driving the timer
goes away or is fulfilled, the oscillator automatically turns
off and its supply current goes away. If GPI is connected
to a signal that toggles infrequently, the oscillator supply
current is inconsequential. However, if the GPI signal is
periodic and greater than 1Hz, this supply current can be
detrimental. Do not allow the GPIO to be unconnected.
To obtain the low VIO supply current, ensure that the
GPIO voltage is either logic-high or logic-low. If the GPIO
is allowed to be unconnected (either as a GPI or an opendrain GPO) and VIO is powered, the GPIO voltage trends
towards the logic level gray area (0.3 x VIO < VGPIO < 0.7
x VIO). If VGPIO is in the gray area, then the VIO current
can be 10µA+.
Maxim Integrated │ 41
MAX77650/MAX77651
SYS
COMM
CNFG_GPIO
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
DRV
DIR
DO
GPI_RM
GPI_FM
DBNC_EN
DI
GPI_R
GPI_F
GPI_R
GPI_RM
nIRQ
Q
OTHER nIRQ ASSERTION
SOURCES NOT SHOWN
D 1
R
IRQ
GPI_FM
GPI_F
VIO
Q
READ
(GPI_R)
D 1
R
READ
(GPI_F)
DBNC_EN
DI
0
1
DRV
30ms DEBOUNCE
(tDBNC_GPI)
DIR
DO
GPIO
LOGIC
GND
Figure 3. GPIO Block Diagram
For example:
●● If the GPI signal has a period of 60ms, the timer runs
continuously, and the supply current increases by the
full 65μA.
●● If the signal has a longer period, the supply current
increase by a fraction of 65μA; a period of 120ms
increases the supply current by 50% of the 65μA
oscillator current (60ms/120ms x 65μA = 32.5μA).
●● The GPI features edge detectors that feed into the
top-level interrupt system of the chip. This allows
software to use interrupts to service events associated with a GPI change instead of having to poll for
these changes.
www.maximintegrated.com
●● If the application wants nIRQ to go low only on a GPI
rising edge, then it should clear the GPI rising edge
interrupt mask bit (GPI_RM = 0) and set the GPI falling edge interrupt mask bit (GPI_FM = 1).
●● If the applications wants nIRQ to go low only on a
GPI falling edge, then it should set the GPI rising
edge interrupt mask bit (GPI_RM = 1) and clear the
GPI falling edge interrupt mask bit (GPI_FM = 0).
●● If the applications wants nIRQ to go low on both GPI
falling and rising edges, then it should clear the GPI
rising edge interrupt mask bit (GPI_RM = 0) and
clear the GPI falling edge interrupt mask bit (GPI_FM
= 0).
Maxim Integrated │ 42
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
On/Off Controller
The on/off controller monitors multiple power-up (wakeup)
and power-down (shutdown) conditions to enable or disable resources that are necessary for the system and its
processor to move between its operating modes.
Many systems have one power management controller
and one processor and rely on the on/off controller to be
the master controller. In this case, the on/off controller
receives the wakeup events and enables some or all of
the regulators in order to power up a processor. That processor then manages the system. To conceptualize this
master operation see Figure 4 and Table 2. A typical path
through the on/off controller in master mode is:
●● Start in the no power state.
●● Apply a battery to the system and transition through
path 1 and 2 to the standby state.
●● Press the system's on key (nEN = low) and transition
through path 3A and 4 to the "PWR_HLD?" state.
●● The processor boots up and drives PWR_HLD high,
which drives the transition through path 4C to the on
through the on/off controller state.
●● The device performs its desired functions in the on
through on/off controller state. When it is ready to turn
off, the processor drives PWR_HLD low that drives the
transition through path 5B and 8 to the standby state.
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Some systems have several power management blocks,
a main processor, and subprocessors. These systems
can use this device as a subpower management block for
a peripheral portion of circuitry as long as there is an I2C
port available from a higher level processor. To conceptualize this slave operation, see Figure 4 and Table 2. A
typical path through the on/off controller in slave mode is:
●● Start in the no power state.
●● Apply a battery to the system and transition through
path 1 and 2 to the standby state.
●● When the higher level processor wants to turn on this
device's resources, it enables the main bias circuits
through I2C (SBIA_EN = 1) to transition along path
2A to the on through software state.
●● The higher level processor can now control this
device's resources with I2C commands (i.e., turn on/
off regulators).
●● When the higher level processor is ready to turn
this device off, it turns off everything through I2C
and then disables the main bias circuits through I2C
(SBIA_EN = 0) to transition along path 2B to the
standby state.
Note that in this slave style of operation, the SFT_RST
bits should not be used to turn the device off. The SFT_
RST bits establish directives to the on/off controller itself
that does not make sense in slave mode. In slave mode,
since the I2C commands enable the device's resources,
they should also disable them.
Maxim Integrated │ 43
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
NO POWER
VCGHIN=0, VSYS<VPOR
STATE
ANY
STATE
0
ACTION
1
DECISION
POWER-ON
RESET (POR)
2
X
TRANSITION NAME.
SEE TABLE 2
2A
STANDBY
3
11
ENABLE MAIN BIAS
ENABLE MAIN BIAS
12
3A
DISABLE MAIN BIAS
6
6
POWER DOWN
SEQUENCE
(FIGURE 5)
POWER UP
SEQUENCE
(FIGURE 5)
3
8
2B
9
IMMEDIATE
SHUTDOWN
(FIGURE 5)
7
4
4B
ANY
STATE
PWR_HLD?
10
4A
4C
3
ON VIA
SOFTWARE
5A
ON VIA ON/OFF
CONTROLLER
10
5B
2B
Figure 4. Top-Level On/Off Controller
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Maxim Integrated │ 44
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Table 2. On/Off Controller Transition/State
TRANSITION/STATE
CONDITION
0
System voltage is below the POR threshold (VSYS < VPOR).
1
System voltage is above the POR threshold (VSYS > VPOR).
2
Internal signals and on-chip memory stabilize and the device is released from reset.
STANDBY
The device is waiting for a wake-up signal or an I2C command to enable the main bias circuits.
* This is the lowest current state of the device (IQ ~0.3μA).
* Main bias circuits are off, POR comparator is on.
* I2C is on when VIO is valid.
* Peripheral functions (LDO, SIMO, LEDs, AMUX) do not operate in this state because the main bias circuits
are off. To utilize a function enter the on through software or on through on/off controller states.
2A
Main bias circuits enabled through I2C (SBIA_EN = 1).
2B
Main bias circuits disabled through I2C (SBIA_EN = 0).
ON VIA
SOFTWARE*
3
3A
4
The main bias circuits are enabled through software and all peripheral functions (LDO, SIMO, LEDs, AMUX)
can be manually enabled or disabled through I2C.
A wake-up signal has been received.
* A debounced onkey (nEN) falling edge has been detected (DBNEN = 1) or
* A charge source has been applied and a rising edge on CHGIN has been detected and debounced
(tCHGIN-DB ~120ms) or
* Internal wake-up flag has been set due to SFT_RST = 0b01 (WKUP = 1)
Main bias circuits are OK (BOK = 1)
Power-up sequence complete.
4A
PWR_HLD wait time has expired and PWR_HLD2 is low (t > tPWR_HLD_WAIT && PWR_HLD2 = 0).
4B
PWR_HLD wait time has not expired and PWR_HLD2 is low (t < tPWR_HLD_WAIT && PWR_HLD2 = 0).
4C
PWR_HLD2 = 1
ON VIA ON/OFF
CONTROLLER*
On state.
* All flexible power sequencers (FPS) are on.
* The main bias circuits are enabled.
* IQ ~5.6µA (typ) with all regulators enabled (no load) and the main bias circuits in low power mode.
5A
PWR_HLD2 = 1
5B
PWR_HLD2 = 0 OR
System overtemperature lockout (TJ >TOTLO) or
Software cold reset (SFT_RST[1:0] = 0b01) or
Software power off (SFT_RST[1:0] = 0b10) or
Manual reset occurred. See the nEN Manual Reset section for more information.
6
System overtemperature lockout (TJ >TOTLO) or
System undervoltage lockout (VSYS < VSYSUVLO + VSYSUVLO_HYS) or
System overvoltage lockout (VSYS > VSYSOVLO)
7
System undervoltage lockout (VSYS < VSYSUVLO) or
System overvoltage lockout (VSYS > VSYSOVLO)
Note: The overvoltage lockout transition does not apply to the ON VIA SOFTWARE state.
8
Finished with the power-down sequence.
9
Finished with immediate shutdown.
10
System overtemperature lockout (TJ > TOTLO).
11
Done disabling main bias.
12
Done enabling main bias.
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Maxim Integrated │ 45
MAX77650/MAX77651
POWER-UP SEQUENCE
START
FROM TOP LEVEL #3A
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
POWER-DOWN SEQUENCE
START FROM TOP LEVEL
#4A OR #5B
CLEAR WAKEUP
FLAG (WKUP = 0)
CLEAR WAKEUP FLAGS
FPS ENABLE SLOT 0
WAIT tEN
TEMPERATURE IS OKAY
(TJ<TOTLO)
WAIT 60ms
FPS ENABLE SLOT 1
WAIT tEN
FPS ENABLE SLOT 2
OTLO?
TEMPERATURE IS
NOT OKAY
(TJ>TOTLO)
SFT_RST = 0b00
OR PWR_HLD2 = 1
SFT_RST = 0b01
SET WAKEUP
FLAG (WKUP = 1)
SFT_RST = 0b10
OR PWR_HLD2 = 0
WAIT tEN
FPS ENABLE SLOT 3
WAIT tRSTODD
DE-ASSERT nRST
END
TO TOP LEVEL #4
IMMEDIATE SHUTDOWN
START
FROM TOP LEVEL #7
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER DOWN EVENT.
ASSERT nRST
WAIT tRSTOAD
FPS DISABLE SLOT 3
WAIT tDIS
FPS DISABLE SLOT 2
WAIT tDIS
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER DOWN EVENT.
ASSERT nRST
DISABLE FPS3, FPS2, FPS1, FPS0
FPS DISABLE SLOT 1
WAIT tDIS
FPS DISABLE SLOT 0
WAIT 125ms
WAIT 125ms
RESET DEVICE
(PULSE SYSRST FOR 5µs)
RESET DEVICE
(PULSE SYSRST FOR 5µs)
END
TO TOP LEVEL #9
END
TO TOP LEVEL #8
RETURN BACK TO
THE ON STATE
Figure 5. Power-Up/Power-Down Sequence
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Maxim Integrated │ 46
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Flexible Power Sequencer
The flexible power sequencer (FPS) allows resources to
power up under hardware or software control. Additionally,
each resource can power up independently or among a
group of other regulators with adjustable power-up and power-down delays (sequencing). Figure 6 shows four resources
powering up under the control of flexible power sequencer.
The flexible sequencing structure consists of 1 master
sequencing timer and 4 slave resources (SBB0, SBB1,
SBB2, and LDO). When the FPS is enabled, a master
timer generates four sequencing events for device powerup and power-down.
NOT DRAWN TO SCALE
ENFPS
tDIS SAME FOR ALL FPS DISABLE PULSES
tEN SAME FOR ALL FPS ENABLE PULSES
PLSFPS
0
1
2
3
tDIS = 2x tEN
3
2
1
0
FPS RESOURCES
SBB0
LDO
SBB1
SBB2
Figure 6. Flexible Power Sequencer Basic Timing Diagram
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Maxim Integrated │ 47
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
NOT DRAWN TO SCALE
STATE
NO POWER
POR
STANDBY
POWER-UP SEQUENCE
ON THROUGH ON/OFF
CONTROLLER
PWR_HLD?
BATTERY
INSERTION
VSYS
VPOR~1.9V
tPOR~100µs
nEN
NOTE 1
tDBNC_nEN
tDBNC_nEN
NOTE 2
STAT_EN
nEN_F
tSBIA_EN
nEN_R
BIAS EN
(INTERNAL)
INTERNAL WAKE-UP
SIGNAL NOTE 3
FPS0
tEN
FPS1
tEN
FPS2
tEN
FPS3
REGULATORS
nIRQ
NOTE 4
tRSTODD
nRST
tPWR_HLD_WAIT
SYSTEM
SOFTWARE
PWR_HLD
NOTES:
1 – nEN LOGIC INPUT IS CONFIGURED TO PUSHBUTTON MODE AND HAS AN EXTERNAL PULLUP TO SYS.
2 – nEN ASSERTION RESULTS IN A WAKE-UP EVEN AFTER A DEBOUNCE TIME (tDBNCEN).
3 – INTERNAL WAKE-UP SIGNAL CAN ALSO BE GENERATED BY CHARGER PLUG-IN EVENT.
NOTE
5
4 – nIRQ HAS AN EXTERNAL PULLUP TO VIO WHICH IS ENABLED IN FLEXIBLE POWER SEQUENCER SLOT #1
NOTE
6
5 – SYSTEM PROCESSOR ASSERTS PWR_HLD INPUT TO PLACE THE DEVICE IN THE ON THROUGH ON/OFF CONTROLLER STATE.
6 – AS PART OF ITS INITIALIZATION ROUTINE, SOFTWARE READS THE INTERRUPT REGISTERS (CLEAR ON READ) AND PROGRAMS THE INTERRUPT MASKS AS DESIRED.
Figure 7. Startup Timing Diagram Due to nEN
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Maxim Integrated │ 48
MAX77650/MAX77651
CHARGER
INSERTION
CHGIN DEBOUNCE
POWER-UP SEQUENCE
PWR_HLD?
ON THROUGH ON/OFF CONTROLLER
PRE-QUAL
FAST CHARGE (CC)
TOP-OFF (CV)
DONE
CHGINOK=1
CHARGER
VOLTAGE
STATE
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
5V
VCHGIN
0V
SYSTEM VOLTAGE
VSYS-REG
VFAST-CHG
tCHGIN-DB (~120ms)
VSYSUVLO~2.9V
VPOR~2.0V
0V
VFAST-CHG
INTERNAL CHARGER GENERATED
WAKE SIGNAL
NOTE 3
VBATT
BATTERY VOLTAGE
VSYS
VPQ
0V
NOTE 4
IBATT
ITOPOFF
IPQ
NOTE 5
nEN
CHARGE CURRENT
VFAST-CHG
0mA
CHG_EN = 1
CHARGER ENABLED
NOTE 1
FPS0
FPS1
tEN
FPS2
tEN
FPS3
NOTES: 1 – nEN LOGIC INPUT IN CONFIGURED TO PUSHBUTTON MODE AND HAS AN
EXTERNAL PULLUP TO SYS.
tEN
2 – IF PWR_HLD IS NOT ASSERTED BY THE END OF THE tPWR_HLD_WAIT PERIOD, DEVICE
INITIATES A POWER-DOWN SEQUENCE.
REGULATORS
tSBIA_EN
3 - IF CHG_EN = 1 (@ OTP) THEN THE CHARGER ENABLED EVENT COINCIDES WITH THE WAKE
EVENT (CHARGING START ALONG WITH POWER-UP SEQUENCE).
tRSTODD
4 – THIS INFLECTION POINT IS SYMBOLIC OF BATTERY PROTECTION FET CLOSING
nRST
tPWR_HLD_WAIT
5 – SOFTWARE SETS CHG_EN = 1 TO ENABLE CHARGING. IF CHG_EN = 1 AT OTP, SEE NOTE 3.
- - - - BLUE DOTTED LINES ARE USER INITIATED EVENTS
PWR_HLD2
NOTE 2
Figure 8. Startup Timing Diagram Due to Charge Source Insertion
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Maxim Integrated │ 49
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Debounced Inputs (nEN, GPI, CHGIN)
nEN, CHGIN, and GPIO (when operating as an input), are
debounced on both rising and falling edges to reject undesired transitions. The input must be at a stable logic level
BOUNCING IS
REJECTED
STABLE
SIGNAL IS
ACCEPTED
for the entire debounce period for the output to change its
logic state. Figure 9 shows an example timing diagram for
the nEN debounce.
BOUNCING IS
REJECTED
STABLE
SIGNALS IS
ACCEPTED
nEN
tDBUF
tDBUF
tDBNCEN
tDBNCEN
EN
(INTERNAL)
DBEN
(INTERNAL)
Figure 9. Debounced Inputs
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Maxim Integrated │ 50
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Smart Power Selector Charger
The linear Li+ charger features Maxim's smart power
selector. This allows separate input current limit and battery charge current settings. Batteries charge faster under
the supervision of the smart power selector because
charge current is independently regulated and not shared
with variable system loads. See the Smart Power Selector
section for more information.
The programmable constant-current charge rate (7.5mA
to 300mA) supports a wide range of battery capacities.
The programmable input current limit (0mA to 475mA)
supports a range of charge sources, including USB. The
charger's programmable battery regulation voltage range
(3.6V–4.6V) supports a wide variety of cell chemistries.
Small battery capacities are supported; the charger accurately terminates charging by detecting battery currents as
low as 0.375mA.
Additionally, the robust charger input withstands overvoltages up to 28V. To enhance charger safety, an NTC thermistor provides temperature monitoring in accordance with the
JEITA recommendations. See the Adjustable Thermistor
Temperature Monitors section for more information.
Features
●● 7.25V maximum operating input voltage with 28V
input standoff
●● 7.5mA to 300mA programmable fast-charge current
●● Programmable termination current from 0.375mA to
45mA
●● Programmable battery regulation voltage from 3.6V
to 4.6V
●● < 1μA battery-only supply current
●● Instant-on functionality
●● Analog multiplexer enables power monitoring
●● JEITA battery temperature monitor adjusts current
and battery regulation voltage for safe charging
●● Programmable die temperature regulation
Figure 10. Linear Charger Simplified Block Diagram
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Maxim Integrated │ 51
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Charger Symbol Reference Guide
Figure 11 indicates the high-level functions of each control
circuit within the linear charger.
Table 3 lists the names and functions of charger-specific
signals and if they can be programmed through I2C.
Consult the Electrical Characteristics and Programmer’s
Guide for more information.
Table 3. Charger Quick Symbol Reference Guide
SYMBOL
I2C PROGRAMMABLE?
NAME
VCHGIN_OVP
CHGIN overvoltage threshold
No
VCHGIN_UVLO
CHGIN undervoltage lockout threshold
No
VCHGIN-MIN
Minimum CHGIN voltage regulation setpoint
Yes, through VCHGIN_MIN[2:0]
ICHGIN-LIM
CHGIN input current limit
Yes, through ICHGIN_LIM[2:0]
VSYS-REG
SYS voltage regulation target
Yes, through VSYS_REG[4:0]
VSYS-MIN
Minimum SYS voltage regulation setpoint
No, tracks VSYS-REG
VFAST-CHG
Fast-charge constant-voltage level
Yes, through CHG_CV[5:0]
IFAST-CHG
Fast-charge constant-current level
Yes, through CHG_CC[5:0]
IPQ
Prequalification current level
Yes, through I_PQ
VPQ
Prequalification voltage threshold
Yes, through CHG_PQ[2:0]
ITERM
Termination current level
Yes, through I_TERM[1:0]
TJ-REG
Die temperature regulation setpoint
Yes, through TJ_REG[2:0]
tPQ
Prequalification safety timer
No
tFC
Fast-charge safety timer
Yes, through T_FAST_CHG[1:0]
tTO
Top-off timer
Yes, through T_TOPOFF[2:0]
BODYSWITCH
CHGIN
SYS
VSYS-MIN
INPUT
CONTROLLER
VSYS-REG
BODYSWITCH
ICHGIN-LIM
CHARGE CONTROLLER
VCHGIN-MIN
VCHGIN_OVP
VCHGIN_UVLO
DIE TEMP
MONITOR
TIMER
VFAST-CHG
TJ-REG
VPQ
IFAST-CHG
IPQ
ITERM
BATT
tPQ
tFC
tTO
Figure 11. Charger Simplified Control Loops
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Maxim Integrated │ 52
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Smart Power Selector
The smart power selector seamlessly distributes power
from the input (CHGIN) to the battery (BATT) and the system (SYS). The smart power selector basic functions are:
●● When the system load current is less than the input
current limit, the battery is charged with residual
power from the input.
●● When a valid input source is connected, the system regulates to VSYS-REG to power system loads
regardless of the battery's voltage (instant on).
●● When the system load current exceeds the input current limit, the battery provides additional current to
the system (supplement mode).
●● When the battery is finished charging and an input
source is present to power the system, the battery
remains disconnected from the system.
●● When the battery is connected and there is no input
power, the system is powered from the battery.
regulation loop also prevents VCHGIN from dropping
below VCHGIN_UVLO if the cable between the charge
source and the charger's input is long or highly resistive.
The input voltage regulation loop improves performance
with current limited adapters. If the charger’s input current
limit is programmed above the current limit of the given
adapter, the input voltage loop allows the input to regulate
at the current limit of the adapter. The input voltage regulation loop also allows the charger to perform well with
adapters that have poor transient load response times.
A maskable interrupt (CHGIN_CTRL_I) signals when the
minimum input voltage regulation loop engages. The state
of this loop is reflected by VCHGIN_MIN_STAT.
Minimum System Voltage Regulation
The input circuit is capable of standing off 28V from
ground. CHGIN suspends power delivery to the system and battery when VCHGIN exceeds VCHGIN_OVP
(7.5V typical). The input circuit also suspends when
VCHGIN falls below VCHGIN_UVLO minus 500mV of hysteresis (3.5V typical). While in OVP or UVLO, the charger
remains off, and the battery provides power to the system.
The minimum system voltage regulation loop ensures that
the system rail remains close to the programmed SYS
regulation voltage (VSYS-REG) regardless of system loading. The loop engages when the combined battery charge
current and system load current causes the CHGIN input
to current-limit at ICHGIN-LIM. When this happens, the
minimum system voltage loop reduces charge current in
an attempt to keep the input out of current limit, thereby
keeping the system voltage above VSYS-MIN (VSYS-REG
- 100mV typical). If this loop reduces battery current to 0
and the system is in need of more current than the input
can provide, then the smart power selector overrides the
minimum system voltage regulation loop and allows SYS
to collapse to BATT for the battery to provide supplement
current to the system. The smart power selector automatically reenables the minimum system voltage loop when
the supplement event has ended.
When an valid charge source is connected to CHGIN,
SYS begins delivering power to the system after a 120ms
debounce timer (tCHGIN-DB).
A maskable interrupt (SYS_CTRL_I) asserts to signal a
change in VSYS_MIN_STAT. This status bit asserts when
the minimum system voltage regulation loop is active.
A maskable interrupt (CHGIN_I) signals changes in the
state of CHGIN's voltage quality. The state of CHGIN is
reflected by CHGIN_DTLS[1:0].
Die Temperature Regulation
Input Current Limiter
The input current limiter limits CHGIN current so as not to
exceed ICHGIN-LIM (programmed by ICHGIN_LIM[2:0]). A
maskable interrupt (CHGIN_CTRL_I) is available to signal
when the input current limit engages. The state of this
loop is reflected by the ICHGIN_LIM_STAT bit.
Minimum Input Voltage Regulation
In the event of a poor-quality charge source, the minimum input voltage regulation loop works to reduce input
current if VCHGIN falls below VCHGIN-MIN (programmed
by VCHGIN_MIN[2:0]). This is important because many
commonly used charge adapters feature foldback protection mechanisms where the adapter completely shuts off
if its output droops too low. The minimum input voltage
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In case the die temperature exceeds TJ-REG (programmed by TJ_REG[2:0]) the charger attempts to limit
the temperature increase by reducing battery charge
current. The TJ_REG_STAT bit asserts whenever charge
current is reduced due to this loop. The charger's current sourcing capability to SYS remains unaffected when
TJ_REG_STAT is high. A maskable interrupt (TJ_REG_I)
asserts to signal a change in TJ_REG_STAT. It is advisable that the TJ_REG_I interrupt be used to signal the
system processor to reduce loads on SYS to reduce total
system temperature.
Maxim Integrated │ 53
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Charger State Machine
The battery charger follows a strict state-to-state progression to ensure that a battery is charged safely. The status
CHGIN INVALID
(CHGIN_DTLS[1:0] = 0b00 or 0b01)
OR
CHARGER DISABLED
(CHG_EN = 0)
ANY STATE
THM_EN = 1
AND
CHG_EN = 1
AND
(TBATT > THOT OR TBATT < TCOLD)
bitfield, CHG_DTLS[3:0], reflects the charger's current
operational state. A maskable interrupt (CHG_I) is available to signal a change in CHG_DTLS[3:0].
CHARGER OFF
CHG_DTLS[3:0] = 0b0000
CHG = 0
RETURNS TO SAME STATE WHEN:
THM_EN = 0
OR
(TBATT < THOT AND TBATT > TCOLD)
BATTERY TEMPERATURE
FAULT
CHG_DTLS[3:0] = 0b1100
CHG = 0
TIMERS PAUSE IN THIS STATE,
RESUME ON EXIT.
CHGIN INSERTED
(CHGIN_DTLS[1:0] = 0b10)
DE-BOUNCE
CHG_DTLS[3:0] = 0b0000
CHG = 0
CHGIN DE-BOUNCED
TIME ELAPSED >= tCHGIN-DB
(CHGIN_DTLS[1:0] = 0b11)
CHARGER ENABLED (CHG_EN = 1)
TIME ELAPSED < tCHGIN-DB
AND
CHGIN DE-BOUNCED & VALID (CHGIN_DTLS[1:0] = 0b11)
AND
BATTERY LOW BY VRESTART (VBATT < VFAST-CHG – 150mV)
PREQUALIFICATION
CHG_DTLS[3:0] = 0b0001
CHG = 1
IBATT = IPQ
TIME ELAPSED > tPQ
PREQUALIFICATION
TIMER FAULT
CHG_DTLS[3:0] = 0b1010
CHG = 0
VBATT < VPQ – 100mV
VBATT < VPQ – 100mV
JEITA-MODIFIED
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0011
CHG = 1
IBATT = IFAST-CHG_JEITA**
VBATT <
VBATT = VFAST-CHG_JEITA
JEITA-MODIFIED
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0101
CHG = 1
VBATT = VFAST-CHG_JEITA
IBATT > ITERM
THM_EN = 0 OR
(TBATT < TWARM AND TBATT > TCOOL)
VBATT < VFAST-CHG
THM_EN = 1 AND
(TBATT > TWARM OR TBATT < TCOOL)
THM_EN = 0 OR
(TBATT < TWARM AND TBATT > TCOOL)
IBATT < ITERM
JEITA-MODIFIED
TOP-OFF
CHG_DTLS[3:0] = 0b0111
CHG = 1
VBATT = VFAST-CHG_JEITA
THM_EN = 0 OR
(TBATT < TWARM AND TBATT > TCOOL)
TIME ELAPSED > tTO
JEITA-MODIFIED DONE
CHG_DTLS[3:0] = 0b1001
CHG = 0
THM_EN = 0 OR
(TBATT < TWARM AND TBATT > TCOOL)
TIME ELAPSED* > tFC
VBATT = VFAST-CHG
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0100
CHG = 1
VBATT = VFAST-CHG
IBATT > ITERM
THM_EN = 1 AND
(TBATT > TWARM OR TBATT < TCOOL)
ANY FAST-CHARGE OR
JEITA-MODIFIED FAST-CHARGE
STATE
CHG_DTLS[3:0] = 0b0010-0b0101
CHG = 1
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0010
CHG = 1
IBATT = IFAST-CHG**
IBATT < ITERM
TOP-OFF
CHG_DTLS[3:0] = 0b0110
CHG = 1
VBATT = VFAST-CHG
TIME ELAPSED > tTO
DONE
CHG_DTLS[3:0] = 0b1000
CHG = 0
VBATT < VFAST-CHG – 150mV
VBATT < VFAST-CHG_JEITA – 150mV
VFAST-CHG_JEITA
THM_EN = 1 AND
(TBATT > TWARM OR TBATT < TCOOL)
VBATT > VPQ
FAST-CHARGE
TIMER FAULT
CHG_DTLS[3:0] = 0b1011
CHG = 0
*TIME ELAPSED IS AGGREGATED
THROUGHOUT THE FAST-CHARGE AND
JEITA-MODIFIED FAST-CHARGE
STATES. ALL FAST-CHARGE STATES
(REGARDLESS OF JEITA STATUS)
SHARE THE SAME SAFETY TIMER.
**IFAST-CHG MAY BE REDUCED BY THE
MINIMUM INPUT VOLTAGE REGULATION
LOOP, THE MINIMUM SYSTEM VOLTAGE
REGULATION LOOP, OR THE DIE
TEMPERATURE REGULATION LOOP.
Figure 12. Charger State Diagram
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Maxim Integrated │ 54
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Charger Off State
The charger is off when CHGIN is invalid, the charger is
disabled, or the battery is fresh.
CHGIN is invalid when the CHGIN input is invalid
(VCHGIN < VCHGIN_UVLO or VCHGIN > VCHGIN_OVP).
While CHGIN is invalid, the battery is connected to the
system. CHGIN voltage quality can be separately monitored by the CHGIN_DTLS[1:0] status bitfield. Refer to
the Programmer’s Guide for details.
The charger is disabled when the charger enable bit is 0
(CHG_EN = 0). The battery is connected or disconnected
to the system depending on the validity of VCHGIN while
CHG_EN = 0. See the Smart Power Selector section.
The battery is fresh when CHGIN is valid and the charger
is enabled (CHG_EN = 1) and the battery is not low by
VRESTART (VBATT > VFAST-CHG - VRESTART). The battery is disconnected from the system and not charged
while the battery is fresh. The charger state machine exits
this state and begin charging when the battery becomes
low by VRESTART (150mV typical). This condition is functionally similar to done state. See Done State section.
Prequalification State
The prequalification state is intended to assess a low-voltage battery's health by charging at a reduced rate. If the
battery voltage is less than the VPQ threshold, the charger
is automatically in prequalification. If the cell voltage does
not exceed VPQ in 30 minutes (tPQ), the charger faults.
The prequalification charge rate is a percentage of IFASTCHG and is programmable with I_PQ. The prequalification voltage threshold (VPQ) is programmable through
CHG_PQ[2:0].
Fast-Charge States
When the battery voltage is above VPQ, the charger
transitions to the fast-charge (CC) state. In this state, the
charger delivers a constant current (IFAST-CHG) to the
cell. The constant current level is programmable from
7.5mA to 300mA by CHG_CC[5:0].
When the cell voltage reaches VFAST-CHG, the charger
state machine transitions to fast-charge (CV). VFASTCHG is programmable with CHG_CV[5:0] from 3.6V to
4.6V. The charger holds the battery's voltage constant
at VFAST-CHG while in the fast-charge (CV) state. As
the battery approaches full, the current accepted by the
battery reduces. When the charger detects that battery
charge current has fallen below ITERM, the charger state
machine enters the top-off state.
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A fast-charge safety timer starts when the state machine
enters fast-charge (CC) or JEITA-modified fast-charge
(CC) from a non-fast-charge state. The timer continues to
run through all fast-charge states regardless of JEITA status. The timer length (tFC) is programmable from 3 hours
to 7 hours in 2 hour increments with T_FAST_CHG[1:0].
If it is desired to charge without a safety timer, program
T_FAST_CHG[1:0] with 0b00 to disable the feature. If the
timer expires before the fast-charge states are exited, the
charger faults. See the Fast-Charge Timer Fault State
section for more information.
If the charge current falls below 20% of the programmed
value during fast-charge (CC), the safety timer pauses.
The timer also pauses for the duration of supplement
mode events. The TIME_SUS bit indicates the status of
the fast-charge safety timer. Refer to the Programmer’s
Guide for more details.
Top-Off State
Top-off state is entered when the battery charge current falls below ITERM during the fast-charge (CV) state.
ITERM is a percentage of IFAST-CHG and is programmable through I_TERM[1:0]. While in the top-off state,
the battery charger continues to hold the battery's voltage
at VFAST-CHG. A programmable top-off timer starts when
the charger state machine enters the top-off state. When
the timer expires, the charger enters the done state. The
top-off timer value (tTO) is programmable from 0 minutes
to 35 minutes with T_TOPOFF[2:0]. If it is desired to stop
charging as soon as battery current falls below ITERM,
program tTO to 0 minutes.
Done State
The charger enters the done state when the top-off timer
expires. The battery remains disconnected from the
system during done. The charger restarts if the battery
voltage falls more than VRESTART (150mV typ) below the
programmed VFAST-CHG value.
Prequalification Timer Fault State
The prequalification timer fault state is entered when the
battery's voltage fails to rise above VPQ in tTO (30 minutes typical) from when the prequalification state was first
entered. If a battery is too deeply discharged, damaged,
or internally shorted, the prequalification timer fault state
can occur. During the timer fault state, the charger stops
delivering current to the battery and the battery remains
disconnected from the system. To exit the prequalification
timer fault state, toggle the charger enable (CHG_EN)
bit or unplug and replug the external voltage source connected to CHGIN.
Maxim Integrated │ 55
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Fast-Charge Timer Fault State
The THM_DTLS[2:0] bitfield reports battery temperature status. See the Adjustable Thermistor Temperature
Monitors section and refer to the Programmer’s Guide for
more information.
The charger enters the fast-charge timer fault state if the
fast-charge safety timer expires. While in this state, the
charger stops delivering current to the battery and the
battery remains disconnected from the system. To exit
the fast-charge timer fault state, toggle the charger enable
bit (CHG_EN) or unplug and replug the external voltage
source connected to CHGIN.
Battery Temperature Fault State
If the thermistor monitoring circuit reports that the battery
is either too hot or too cold to charge (as programmed by
THM_HOT[1:0] and THM_COLD[1:0]), the state machine
enters the battery temperature fault state. While in this
state, the charger stops delivering current to the battery
and the battery remains disconnected from the system.
This state can only be entered if the thermistor is enabled
(THM_EN = 1). Battery temperature fault state has priority over any other fault state, and can be exited when the
thermistor is disabled (THM_EN = 0) or when the battery
returns to an acceptable temperature. When this fault
state is exited, the state machine returns to the last state it
was in before battery temperature fault state was entered.
All active charger timers (fast-charge safety timer,
prequalification timer, or top-off timer) are paused in this
state. Active timers resume when the state is exited.
JEITA-Modified States
If the thermistor is enabled (THM_EN = 1), then the charger state machine is allowed to enter the JEITA-modified
states. These states are entered if the charger's temperature monitors indicate that the battery temperature
is either warm (greater than TWARM) or cool (lesser than
TCOOL). See the Adjustable Thermistor Temperature
Monitors section for more information about setting the
temperature thresholds.
The charger's current and voltage parameters change
from IFAST-CHG and VFAST-CHG to IFAST-CHG_JEITA and
VFAST-CHG_JEITA while in the JEITA-modified states. The
JEITA modified parameters can be independently set to
lower voltage and current values so that the battery can
charge safely over a wide range of ambient temperatures. If the battery temperature returns to normal, or the
thermistor is disabled (THM_EN = 0) the charger exits the
JEITA-modified states.
Typical Charge Profile
A typical battery charge profile (and state progression) is
illustrated in Figure 13.
(mA)
(V)
5
CHGIN
500
SYS
VSYS-REG = 4.5V
4
BATT
VFAST-CHG = 4.25V
400
IFAST-CHG = 300mA
3
300
VPQ= 2.3V
IBATT
2
200
1
100
IPQ = 30mA
FAST-CHARGE (CC)
ITERM = 30mA
FAST-CHARGE (CV)
tTO
TOP-OFF DONE
CHGIN
INVALID
(TIME)
PREQUALIFICATION
Figure 13. Example Battery Charge Profile
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Maxim Integrated │ 56
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Charger Applications Information
Configuring a Valid System Voltage
The smart power selector begins to regulate SYS to
VSYS-REG when CHGIN is connected to a valid source. To
ensure the charger's accuracy specified in the Electrical
Characteristics table, the system voltage must always
be programmed at least 200mV above the charger's
constant-voltage level (VFAST-CHG). If this condition is not
met, then the charger's internal configuration logic forces
VFAST-CHG to reduce to satisfy the 200mV requirement. If
this happens, the charger asserts the SYS_CNFG_I interrupt to alert the user that a configuration error has been
made and that the bits in CHG_CV[5:0] have changed to
reduce VFAST-CHG.
CHGIN/SYS/BATT Capacitor Selection
Bypass CHGIN to GND with a 4.7μF ceramic capacitor to
minimize inductive kick caused by long cables between
the DC charge source and the device. Larger values
increase decoupling for the linear charger, but increase
inrush current from the DC charge source when the
device is first connected to a source through a cable/plug.
If the DC charging source is an upstream USB device,
limit the maximum CHGIN input capacitance based on
the appropriate USB specification (typically no more than
www.maximintegrated.com
10μF). The effective value of the CHGIN capacitor must
be greater than 1µF when biased with 5V.
Bypass SYS to GND with a 22μF ceramic capacitor.
This capacitor is needed to ensure stability of SYS while
it is being regulated from CHGIN. Since SYS must be
connected to IN_SBB, then one capacitor can be used
to bypass this node as long as it is physically close to
the device. Larger values of SYS capacitance increase
decoupling for all SYS loads. When biased with 4.5V, the
effective value of the SYS capacitor must be greater than
4μF and no more than 100μF.
Bypass BATT to GND with a 4.7μF ceramic capacitor.
This capacitor is required to ensure stability of the BATT
voltage regulation loop. When biased with 4.5V, the effective value of the BATT capacitor must be greater than 1μF.
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufacturer's data sheet.
Maxim Integrated │ 57
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Adjustable Thermistor Temperature
Monitors
The optional use of a negative temperature coefficient (NTC) thermistor (thermally coupled to the battery)
MAX77650/
MAX77651
1.25V
enables the charger to operate safely over the JEITA temperature range. When the thermistor is enabled (THM_EN
= 1), the charger continuously monitors the voltage at the
THM pin in order to sense the temperature of the battery
being charged.
CHG_CV[5:0]
D0
CHG_CV_JEITA[5:0]
D1
CHG_CC[5:0]
D0
CHG_CC_JEITA[5:0]
D1
VFAST-CHG
TBIAS
TBIAS SWITCH
CONTROL
(FIGURE 16)
RBIAS
IFAST-CHG
THM
NTC
THM_COLD[1:0]
THM_COOL[1:0]
THM_WARM[1:0]
THM_HOT[1:0]
S0
THM_EN
S0
INTERNAL COOL/WARM SIGNAL
THM_DTLS[2:0] = 0b000 OR 0b101 (NTC
DISABLED OR BATTERY NORMAL).
0b0
CHARGER V&I PARAMETERS FOLLOW
NORMAL SETTINGS.
THM_DTLS[2:0] = 0b010 OR 0b011
(BATTERY COOL OR WARM). CHARGER
0b1
V&I PARAMETERS SWITCH TO JEITA
SETTINGS.
INTERNAL HOT/COLD SIGNAL
0b0
THM_DTLS[2:0] ≠ 0b001 OR 0b100
(BATTERY NOT COLD OR HOT). CHARGER
V&I PARAMETERS FOLLOW NORMAL OR
JEITA SETTINGS.
0b1
THM_DTLS[2:0] = 0b001 OR 0b100
(BATTERY COLD OR HOT). CHARGING IS
PAUSED REGARDLESS OF CHG_EN.
Figure 14. Thermistor Logic Functional Diagram
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Maxim Integrated │ 58
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
See Figure 15 for a visual example of what is described
here in text.
●● If the battery temperature is either above THOT or below
TCOLD, the charger follows the JEITA recommendation
and pauses charging. The charger state machine enters
battery temperature fault state while charging is paused
due to extreme high or low temperatures.
The battery's temperature status is reflected by the
THM_DTLS[2:0] status bitfield. A maskable interrupt
(THM_I) signals a change in THM_DTLS[2:0]. Refer to
the Programmer’s Guide for more information. To completely disable the charger's automatic response to battery temperature, disable the feature by programming
THM_EN = 0.
●● If the battery temperature is higher than TCOOL and
lower than TWARM, the battery charges normally with
the normal values for VFAST-CHG and IFAST-CHG. The
charger state machine does not enter JEITA-modified
states while the battery temperature is normal.
●● If the battery temperature is either above TWARM
but below THOT, or, below TCOOL but above TCOLD,
the battery charges with the JEITA-modified voltage and current values. These modified values,
VFAST-CHG_JEITA and IFAST-CHG_JEITA, are programmable through CHG_CV_JEITA[5:0] and
CHG_CC_JEITA[5:0], respectively. These values are
independently programmable from the nonmodified
VFAST-CHG and IFAST-CHG values and can even
be programmed to the same values if an automatic
response to a warm or cool battery is not desired. The
charger state machine enters JEITA-modified states
while the battery temperature is outside of normal.
EXAMPLE TEMPERATURES
FOR NTC β = 3380K
THM_COLD[1:0] = 0b10 (0°C)
THM_COOL[1:0] = 0b11 (15°C)
THM_WARM[1:0] = 0b10 (45°C)
THM_HOT[1:0] = 0b11 (60°C)
4.4V
BATT REGULATION VOLTAGE (V)
The voltage thresholds corresponding to the JEITA temperature thresholds are independently programmable through
THM_HOT[1:0], THM_WARM[1:0], THM_COOL[1:0], and
THM_COLD[1:0]. Each threshold can be programmed
to one of four voltage options spanning 15°C for an
NTC beta of 3380K. See the Configurable Temperature
Thresholds section and refer to the Programmer’s Guide
for more information.
4.3V
VFAST-CHG = 4.2V
(CHG_CV[5:0] = 0b011000)
4.2V
VFAST-CHG_JEITA = 4.075V
(CHG_CV_JEITA[5:0] = 0b010011)
4.1V
COLD
4.0V
-40°C
-25°C
COOL
NORMAL
0°C
15°C
TCOLD
TCOOL
25°C
WARM
HOT
45°C
60°C
TWARM
THOT
75°C
85°C
FAST-CHARGE CURRENT (A)
BATTERY TEMPERATURE
IFAST-CHG = 150mA
(CHG_CC[5:0] = 0b010011)
0.15
IFAST-CHG_JEITA = 75mA
(CHG_CC_JEITA[5:0] = 0b001001)
0.1
0.05
COLD
COOL
NORMAL
WARM
HOT
0
-40°C
-25°C
0°C
15°C
TCOLD
TCOOL
25°C
45°C
60°C
TWARM
THOT
75°C
85°C
BATTERY TEMPERATURE
Figure 15. Safe-Charging Profile Example
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Maxim Integrated │ 59
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Thermistor Bias
The NTC thermistor's bias source (TBIAS) follows the
simple operation outlined below:
An external ADC can optionally perform conversions on
the THM and TBIAS pins to measure the battery's temperature. An on-chip analog multiplexer is used to route
these nodes to the AMUX pin. The operation of the analog
multiplexer does not interfere with the charger's temperature monitoring comparators or the charger's automatic
JEITA response. See the Analog Multiplexer & Power
Monitor AFEs section for more information.
●● If CHGIN is valid and the thermistor is enabled
(THM_EN = 1), then the thermistor is biased so the
charger can automatically respond to battery temperature changes.
●● If the analog multiplexer is connecting THM or
TBIAS to AMUX, then the thermistor is biased so an
external ADC can perform a meaningful temperature
conversion.
The AMUX pin is a buffered output. The operation of the
analog multiplexer and external ADC does not collide with
the function of the on-chip temperature monitors. Both
functions may be used simultaneously with no ill effect.
THERMISTOR BIASED
TBIAS = 1.25V
Configurable Temperature Thresholds
MUX_SEL ≠ 0b0111 or 0b1000
AND
(THM_EN = 0 OR CHGIN INVALID)
Temperature thresholds for different NTC thermistor beta
values are listed in Table 4. The largest possible programmable temperature range can be realized by using an NTC
with a beta of 3380K. Using a larger beta compresses the
temperature range. The trip voltage thresholds are programmable with the THM_HOT[1:0], THM_WARM[1:0],
THM_COOL[1:0], and THM_COLD[1:0] bitfields. All possible programmable trip voltages are listed in Table 4.
MUX_SEL = 0b0111 or 0b1000
OR
(THM_EN = 1 AND CHGIN VALID)
THERMISTOR OFF
TBIAS = GND
These are theoretical values computed by a formula.
Refer to the particular NTC's data sheet for more accurate
measured data. In all cases, select the value of RBIAS to
be equal to the NTC's effective resistance at +25°C.
Figure 16. Thermistor Bias State Diagram
Table 4. Trip Temperatures vs. Trip Voltages for Different NTC β
TRIP TEMPERATURES (°C)
TRIP VOLTAGE
(V)
3380K
3435K
3940K
4050K
4100K
4250K
1.024
-10.0
-9.5
-5.6
-4.8
-4.5
-3.5
0.976
-5.0
-4.6
-1.1
-0.5
-0.2
0.6
0.923
0.0
0.3
3.3
3.8
4.1
4.8
0.867
5.0
5.3
7.7
8.1
8.3
8.9
0.807
10.0
10.2
12.0
12.4
12.5
12.9
0.747
15.0
15.1
16.4
16.6
16.7
17.0
0.511
35.0
34.8
33.5
33.3
33.2
32.9
0.459
40.0
39.8
37.8
37.4
37.3
36.8
0.411
45.0
44.7
42.0
41.5
41.3
40.7
0.367
50.0
49.6
46.2
45.6
45.3
44.6
0.327
55.0
54.5
50.4
49.7
49.3
48.4
0.291
60.0
59.4
54.6
53.7
53.3
52.2
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Maxim Integrated │ 60
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Thermistor Applications Information
Figure 17
Using Different Thermistor β
TBIAS
If an NTC with a beta larger than 3380K is used and the
resulting available programmable temperature range is
undesirably small, then two adjusting resistors can be
used to expand the temperature range. RS and RP can
be optionally added to the NTC thermistor circuit shown
in Figure 17 to expand the range of programmable temperature thresholds.
RBIAS
THM
RS
Select values for RS and RP based on the information
shown in Table 5.
RP
NTC
NTC Thermistor Selection
Popular NTC thermistor options are listed in Table 6.
Figure 17. Thermistor Circuit with Adjusting Series and Parallel
Resistors
Table 5. Example RS and RP Correcting Values for NTC β Above 3380K
PARAMETER
UNIT
NTC thermistor B-constant (beta)
K
3380
3940
3940
4050
4050
4250
4250
25°C NTC resistance
kΩ
10
10
10
47
47
100
100
RBIAS
kΩ
10
10
10
47
47
100
100
Adjusting parallel resistor, RP
kΩ
open
open
200
open
768
open
1300
Adjusting series resistor, RS
kΩ
short
short
0.59
short
3.32
short
8870
RNTC at 1.024VCOLD threshold
kΩ
45.24
45.24
57.89
212.6
290.7
452.4
685.0
RNTC at 0.867VCOOL threshold
kΩ
22.61
22.61
24.91
106.3
120.0
226.1
264.9
RNTC at 0.459VWARM threshold
kΩ
5.81
5.81
5.39
27.3
25.0
58.1
51.9
RNTC at 0.291VHOT threshold
kΩ
3.04
3.04
2.49
14.3
11.2
30.4
22.2
TACTUAL at VCOLD [-10°C expected]
°C
-10.03
-5.56
-9.97
-4.82
-10.27
-3.55
-10.46
TACTUAL at VCOOL [5°C expected]
°C
4.98
7.66
5.74
8.10
5.57
8.86
5.93
TACTUAL at VWARM [40°C expected]
°C
40.02
37.79
39.63
37.43
39.55
36.82
39.37
TACTUAL at VHOT [60°C expected]
°C
60.04
54.56
60.03
53.68
60.15
52.21
60.18
Table 6. NTC Thermistors
MANUFACTURER
PART
Β-CONSTANT
(25°C/50°C)
R (Ω) AT 25°C
CASE SIZE
TDK
NTCG063JF223HTBX
3380K
22k
0201
Murata
NCP03XH103F05RL
3380K
10k
0201
Murata
NCP15XH103F03RC
3380K
10k
0402
TDK
NTCG103JX103DT1
3380K
10k
0402
Cantherm
CMFX3435103JNT
3435K
10k
0402
Murata
NCP15XV103J03RC
3900K
10k
0402
Panasonic
ERT-JZEP473J
4050K
47k
0201
Panasonic
ABNTC-0402-473J-4100F-T
4100K
47k
0402
Murata
NCP15WF104F03RC
4250K
100k
0402
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Maxim Integrated │ 61
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Analog Multiplexer & Power Monitor AFEs
An external ADC can be used to measure the chip's various signals for general functionality or on-the-fly power
monitoring. The MUX_SEL[3:0] bitfield controls the internal analog multiplexer responsible for connecting the
proper channel to the AMUX pin. Each measurable signal
is listed below with its appropriate multiplexer channel.
The voltage on the AMUX pin is a buffered output that
ranges from 0V to VFS (1.25V typ). The buffer has a
50μA quiescent current draw and is only active when the
device's main bias is active and a channel is selected
(MUX_SEL[3:0] ≠ 0b0000). Disable the buffer by programming to MUX_SEL[3:0] to 0b0000 when not actively
converting the voltage on AMUX.
Table 7 shows how to translate the voltage signal on the
AMUX pin to the value of the parameter being measured.
See the Electrical Characteristics—Analog Multiplexer and
Power Monitor AFEs table and refer to the Programmer’s
Guide for more details.
Table 7. AMUX Signal Transfer Functions
FULL-SCALE
SIGNAL
MEANING
(V AMUX = 1.25V)
ZERO-SCALE
SIGNAL
MEANING
(V AMUX = 0V)
VAMUX
7.5V
0V
VAMUX
0.475A
0A
VAMUX
SIGNAL
MUX_SEL
[3:0]
CHGIN pin
voltage
0b0001
VCHGIN = G
VCHGIN
CHGIN pin
current
0b0010
ICHGIN = G
ICHGIN
BATT pin
voltage
0b0011
VBATT = G
VBATT
4.6V
0V
BATT pin
charging
current
0b0100
VAMUX
100% of IFAST-CHG
(CHG_CC[5:0])
0% of
IFAST-CHG
BATT pin
discharge
current
0b0101
BATT pin
discharge
current NULL
0b0110
VNULL = VAMUX
1.25V
0V
THM pin
voltage
0b0111
VTHM = VAMUX
1.25V
0V
TBIAS pin
voltage
0b1000
VTBIAS = VAMUX
1.25V
0V
AGND pin
voltage*
0b1001
VAGND = VAMUX
1.25V
0V
SYS pin
voltage
0b1010
VSYS = G
VSYS
4.8V
0V
TRANSFER FUNCTION
IBATT(CHG) =
IBATT(DISCHG) =
VFS
× IFAST − CHG
(VAMUX − VNULL) × I
DISCHG − SCALE
(VFS − VNULL)
VAMUX
100% of
IDISCHG-SCALE
(IMON_DISCHG_SCALE[3:0])
0% of
IDISCHG-SCALE
*AGND pin voltage is accessed through a 100Ω (typ) pulldown resistor. Setting MUX_SEL[3:0] to 0b0000 disables the multiplexer
and changes the AMUX pin to a high-impedance state.
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Maxim Integrated │ 62
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Measuring Battery Current
●● Convert the voltage on AMUX pin and use the following
transfer function to determine the discharge current.
It is possible to sample the current in the BATT pin at any
time or in any mode with an external ADC. For improved
accuracy, the analog circuitry used for monitoring battery
discharge current is different from the circuitry monitoring
battery charge current. Table 8 outlines how to determine
the direction of battery current.
IBATT(DISCHG) =
(VAMUX − VNULL) × I
DISCHG − SCALE
(VFS − VNULL)
VFS is 1.25V (typ). IDISCHG-SCALE is programmable
through IMON_DISCHG_SCALE[3:0]. The default value
is 300mA. If smaller currents are anticipated, then
IDISCHG-SCALE can be reduced for improved measurement accuracy.
Method for Measuring Discharging Current
●● Program the multiplexer to switch to the discharge
NULL measurement by changing MUX_SEL[3:0] to
0b0110. A NULL conversion must always be performed first to cancel offsets.
●● Wait the appropriate channel switching time (0.3μs
typ).
●● Convert the voltage on the AMUX pin and store as
VNULL.
●● Program the multiplexer to switch to the battery
discharge current measurement by changing MUX_
SEL[3:0] to 0b0101. A nonnulling conversion should
be done immediately after a NULL conversion.
●● Wait the appropriate channel switching time (0.3μs
typ).
Method for Measuring Charging Current
●● Program the multiplexer to switch to the charge
current measurement by changing MUX_SEL[3:0] to
0b0100.
●● Wait the appropriate channel switching time (0.3μs
typ).
●● Convert the voltage on the AMUX pin and use the following transfer function to determine charging current.
IBATT(CHG) =
VAMUX
VFS
× IFAST − CHG
VFS is 1.25V (typ). IFAST-CHG the charger's fast-charge
constant-current setting and is programmable through
CHG_CC[5:0].
Table 8. Battery Current Direction Decode
MEASUREMENT
Discharging Battery Current
(Positive Battery Terminal Sourcing Current
into the BATT pin of MAX77650/MAX77651)
Charging Battery Current
(Positive Battery Terminal Sinking Current from
the BATT pin of MAX77650/MAX77651)
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CHARGING OR DISCHARGING INDICATORS
CHG BIT
CHG_DTLS[3:0]
CHGIN_DTLS[1:0]
Don't care
Don't care
0b00
0b01
0b10
1
0b0001–0b0111
0b11
Maxim Integrated │ 63
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
SIMO Buck-Boost
SIMO Benefits and Features
●● 3 Output Channels
●● Ideal for Low-Power Designs
• Delivers > 300mA at 1.8V from a 3.7V Input
• ±3% Accurate Output Voltage
●● Small Solution Size
• Multiple Outputs from a Single 1.5μH (0603) Inductor
• Small 10μF (0402) Output Capacitors
●● Flexible and Easy to Use
• Single Mode of Operation
• Programmable Peak Inductor Current
• Programmable On-Chip Active Discharge
●● Long Battery Life
• High Efficiency, > 87% at 3.3V Output
• Better Total System Efficient than Buck + LDOs
• Low Quiescent Current, 1μA per Output
• Low Input Operating Voltage, 2.7V (min)
The device has a micropower single-inductor, multiple-output (SIMO) buck-boost DC-to-DC converter designed for
applications that emphasize low supply current and small
solution size. A single inductor is used to regulate three
separate outputs, saving board space while delivering
better total system efficiency than equivalent power solutions using one buck and linear regulators.
The SIMO configuration utilizes the entire battery voltage
range due to its ability to create output voltages that are
above, below, or equal to the input voltage. Peak inductor current for each output is programmable to optimize
the balance between efficiency, output ripple, EMI, PCB
design, and load capability.
3300pF
(0201)
1.5µH
LXA
MAX77650/MAX77651
SYS
BST
PGND
IN_SBB
SYNCHRONOUS RECTIFIER
MAIN POWER STAGE
IN_SBB
10µF
(0402)
LXB
REVERSE
BLOCKING
SBB0
M1
BST
DRV_SBB
M3_0
IZX
DRV_SBB
CHG
DIS
M2
M4
ILIM
REG0
ERROR COMPARATOR
SIMO
CONTROLLER
CHG
DIS
DIS_SBB[2:0]
REG1
AD_SBB1
RAD_SSB0
(140Ω)
SYNCHRONOUS
RECTIFIER (M3_1)
AND
ERROR COMPARATOR
AND
ACTIVE-DISCHARGE
SBB1
BST
DRV_SBB
DIS_SBB1
10µF
(0402)
/
VREF
VIREF
DIS_SBB1
ACTIVE-DISCHARGE
AD_SBB0
I.LIM
I.ZX
REG[2:0]
10µF
(0402)
COMM
FPS
SYS_RST
DIGITAL AND
REGISTERS
CNFG_SBB_TOP,
CNFG_SBBX_A,
CNFG_SBBX_B
DRV_SBB
AD_SBB[2:0]
REG2
AD_SBB2
SYNCHRONOUS
RECTIFIER (M3_2)
AND
ERROR COMPARATOR
AND
ACTIVE-DISCHARGE
SBB2
BST
DRV_SBB
DIS_SBB2
10µF
(0402)
Figure 18. SIMO Detailed Block Diagram
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Maxim Integrated │ 64
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
SIMO Control Scheme
The SIMO buck-boost is designed to service multiple outputs simultaneously. A proprietary controller ensures that
all outputs get serviced in a timely manner, even while
multiple outputs are contending for the energy stored in
the inductor. When no regulator needs service, the state
machine rests in a low-power rest state.
When the controller determines that a regulator requires
service, it charges the inductor (M1 + M4) until the peak
current limit is reached (ILIM = IP_SBB). The inductor
energy then discharges (M2 + M3_x) into the output until
the current reaches zero (IZX). In the event that multiple
output channels need servicing at the same time, the controller ensures that no output utilizes all of the switching
cycles. Instead, cycles interleave between all the outputs
that are demanding service, while outputs that do not
need service are skipped.
SIMO Soft-Start
The soft-start feature of the SIMO limits inrush current during startup. The soft-start feature is achieved by limiting the
slew rate of the output voltage during startup (dV/dtSS).
More output capacitance results in higher input current
surges during startup. The following set of equations and
example describes the input current surge phenomenon
during startup.
The current into the output capacitor (ICSBB) during soft-start is:
dV
ICSBB = CSBB dt
SS
(Equation 1)
where CSBB is the capacitance on the output of the regulator, and dV/dtSS is the voltage change rate of the output.
The input current (IIN) during soft-start is:
IIN =
(ICSBB + ILOAD)
ξ
VSBBx
VIN
(Equation 2)
where ICSBB is from the calculation above, ILOAD is current consumed from the external load, VSBBx is the output
voltage, and VIN is the input voltage, ξ is the efficiency of
the regulator.
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For example, given the following conditions, the peak
input current (IIN) during soft-start is ~71mA:
Given:
●● VIN is 3.5V
●● VSBB2 is 3.3V
●● CSBB2 = 10µF
●● dV/dtSS = 5mV/µs
●● RLOAD2 = 330Ω (ILOAD2 = 3.3V/330Ω = 10mA)
●● ξ is 80%
Calculation:
●● ICSBB = 10µF x 5mV/µs (from Equation 1)
●● ICSBB = 50mA
3.3V
●●
IIN =
(50mA + 10mA) 3.5V
●● IIN ~ 71mA
0.85
(from Equation1)
SIMO Registers
Each SIMO buck-boost channel has a dedicated register
to program its target output voltage (TV_SBBx) and its
peak current limit (IP_SBBx). Additional controls are available for enabling/disabling the active discharge resistors
(ADE_SBBx), as well as enabling/disabling the SIMO
buck-boost channels (EN_SBBx). For a full description of
bits, registers, default values, and reset conditions, refer
to the Programmer’s Guide.
SIMO Active Discharge Resistance
Each SIMO buck-boost channel has an active-discharge
resistor (RAD_SBBx) that is automatically enabled/disabled based on a ADE_SBBx and the status of the SIMO
regulator. The active discharge feature can be enabled
(ADE_SBBx = 1) or disabled (ADE_SBBx = 0) independently for each SIMO channel. Enabling the active discharge feature helps ensure a complete and timely power
down of all system peripherals. If the active-discharge
resistor is enabled by default, then the active-discharge
resistor is on whenever VSYS is below VSYSUVLO and
above VPOR.
These resistors discharge the output when ADE_SBBx
= 1, and their respective SIMO channel is off. Note if
the regulator is forced on through EN_SBBx = 0b110 or
0b111, then the resistors do not discharge the output even
if the regulator is disabled by the main-bias.
Note that when VSYS is less than 1.0V, the NMOS transistors that control the active discharge resistors lose their
gate drive and become open.
Maxim Integrated │ 65
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
SIMO Applications Information
SIMO Available Output Current
The available output current on a given SIMO channel is
a function of the input voltage, output voltage, peak current limit setting, and the output current of the other SIMO
channels. Maxim offers a SIMO calculator that outlines
the available capacity for specific conditions. See Support
Materials for more information on this and other engineering resources. Table 9 is an extraction from the calculator.
Inductor Selection
Choose an inductance from 1.0μH to 2.2uH; 1.5μH inductors work best for most designs. Larger inductances
transfer more energy to the output for each cycle and
typically result in larger output voltage ripple and better
efficiency. See the Output Capacitor Selection section for
more information on how to size your output capacitor in
order to control ripple.
Table 9. SIMO Available Output Current
for Common Applications
PARAMETERS EXAMPLE 1 EXAMPLE 2 EXAMPLE 3
V.IN.MIN
R.L.DCR
2.7V
3.2V
3.4V
0.1Ω
0.1Ω
0.12Ω
SBB1
1V at 100mA 1.2V at 50mA 1.2V at 20mA
SBB0
1.2V at 75mA
SBB2
1.8V at 50mA 3.3V at 30mA 3.3V at 10mA
2.05V at
100mA
2.05V at 80mA
I.PEAK.0
1A
0.866A
0.5A
I.PEAK.1
1A
0.707A
0.5A
I.PEAK.2
1A
1A
0.5A
Utilized
Capacity
79
76
73
Choose the inductor saturation current to be greater than
or equal to the maximum peak current limit setting that is
used for all of the SIMO buck-boost channels (IP_SBB).
For example, if SBB0 is set for 0.5A, SBB1 is set for
0.866A, and SBB2 is set for 1.0A, then choose the saturation current to be greater than or equal to 1.0A.
Choose the RMS current rating of the inductor (typically
the current at which the temperature rises appreciably)
based on the expected load currents for the system. For
systems where the expected load currents are not well
known, be conservative and choose the RMS current to
be greater than or equal to the half of higher maximum
peak current limit setting [IRMS>=MAX(IP_SBB0, IP_
SBB1, IP_SBB2)/2]. This is a safe/conservative choice
because the SIMO buck-boost regulator implements a
discontinuous conduction mode (DCM) control scheme,
which returns the inductor current to zero each cycle.
Consider the DC-resistance (DCR), AC-resistance (ACR)
and solution size of the inductor. Typically, smaller
sized inductors have larger DC-resistance and larger
AC-resistance that reduces efficiency and the available
output current. Note that many inductor manufacturers
have inductor families which contain different versions
of core material in order to balance trade-offs between
DCR, ACR (i.e., core losses), and component cost. For
this SIMO regulator, inductors with the lowest ACR in
the 1.0MHz to 2.0MHz region tend to provide the best
efficiency.
See Table 10 for examples of inductors that work well
with this device. This table was generated in the middle
of 2016 and the highest efficiency inductors are listed first.
Inductor technology advances rapidly and by the end of
2017 this table may no longer represent the best market
offerings.
*R.C.IN = R.C.OUT = 5mΩ, L = 1.5μH
Table 10. Example Inductors
L (µH)
I SAT (A)
I RMS (A)
DCR (Ω)
X (mm)
Y (mm)
Z (mm)
Samsung
MANUFACTURER
CIGT201610EH2R2MN
PART
2.2
2.9
2.7
0.073
2.0
1.6
1.0
Murata
DFE201610E-2R2M
2.2
2.6
1.9
0.117
2.0
1.6
1.0
Murata
DFE201610E-1R5M
1.5
2.4
3.2
0.076
2.0
1.6
1.0
Murata
DFE201210S-2R2M
2.2
2.3
1.80
0.127
2.0
1.2
1.0
Murata
DFE201210S-1R5M
1.5
2.2
2.6
0.086
2.0
1.2
1.0
Samsung
CIGT201208EH2R2MN
2.2
2.0
1.8
0.095
2.0
1.25
0.8
Murata
DFE201208S-1R5M
1.5
2.4
2.0
0.110
2.0
1.2
0.8
Murata
DFE201208S-2R2M
2.2
2.0
1.6
0.170
2.0
1.2
0.8
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Maxim Integrated │ 66
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Input Capacitor Selection
Choose the input bypass capacitance (CIN_SBB) to be
10µF. Larger values of CIN_SBB improve the decoupling
for the SIMO regulator.
CIN_SBB reduces the current peaks drawn from the battery
or input power source during SIMO regulator operation and
reduces switching noise in the system. The ESR/ESL of the
input capacitor should be very low (i.e., ≤ 5mΩ + ≤ 500pH)
for frequencies up to 2MHz. Ceramic capacitors with X5R
or X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
To fully utilize the available input voltage range of the
SIMO (5.5V max), use a 6.3V capacitor voltage rating.
IN_SBB is a critical discontinuous current path that
requires careful bypassing. When the SIMO detects that
an output is below its regulation threshold, a switching
cycle begins and the IN_SBB current ramps up as a function of the input voltage and inductor (di/dt = VIN_SBB/L)
until it reaches the peak current limit (IP_SBB). Once
IP_SBB is reached, the IN_SBB current falls to zero
rapidly (~5ns). This rapid current decrease makes the
parasitic inductance in the PGND to input capacitor to
IN_SBB path critical. In the PCB layout, place CIN_SBB as
close as possible to the power pins (IN_SBB and PGND)
to minimize parasitic inductance. If making connections
to the input capacitor through vias, ensure that the vias
are rated for the expected input current so they do not
contribute excess inductance and resistance between the
bypass capacitor and the power pins.
Note that most designs concern themselves with having
enough capacitance on the output but there is also a
maximum capacitance limitation that is calculated within
the SIMO Calculator; take care not to exceed the maximum capacitance.
CSBBx is required to keep the output voltage ripple small.
The impedance of the output capacitor (ESR, ESL) should
be very low (i.e., ≤ 5mΩ + ≤ 500pH) for frequencies up to
2MHz. Ceramic capacitors with X5R or X7R dielectric are
highly recommended due to their small size, low ESR,
and small temperature coefficients.
A capacitor's effective capacitance decreases with
increased DC bias voltage. This effect is more pronounced as capacitor case sizes decrease. Due to this
characteristic, it is possible for an 0603 case size capacitor to perform well, while an 0402 case size capacitor of
the same value performs poorly. The SIMO regulator is
stable with low output capacitance (1μF) but the output
voltage ripple would be large; consider the effective output capacitance value after initial tolerance, bias voltage,
aging, and temperature derating.
Choose the boost capacitance (CBST) to be 3.3nF. Smaller
values of CBST (< 1nF) result in insufficient gate drive for
M3. Larger values of CBST (> 10nF) have the potential
to degrade the startup performance. Ceramic capacitors
with 0201 or 0402 case size are recommended.
SBBx is a critical discontinuous current path that requires
careful bypassing. When the SIMO detects that an output
is below its target, it charges the inductor to a peak current limit (IP_SBB) and then discharges that inductor into
the output. At the moment the charge is applied to the
output, the current increases rapidly and then decays
relatively slowly (dt/dt = VOUT/L). This rapid current
increase is a function of the drive strength setting (DRV_
SBB) and makes the parasitic inductance in the SBBx to
output capacitor to PGND path critical. In the PCB layout,
place CSBBx as close as possible to SBBx and PGND
to minimize parasitic inductance. If making connections
to the output capacitor through vias, ensure that the vias
are rated for the expected output current so they do not
contribute excess inductance and resistance.
Output Capacitor Selection
SIMO Switching Frequency
Boost Capacitor Selection
Choose each output bypass capacitance (CSBBx) based
on the desired output voltage ripple; typical values are
10µF. Larger values of CSBBx improve the output voltage ripple but increase the input surge currents during
soft-start and output voltage changes. The output voltage
ripple is a function of the inductance, the output voltage,
and the peak current limit setting. Maxim offers a SIMO
calculator to aid in the selection of the output capacitance.
See Support Materials for more information on this and
other engineering resources.
www.maximintegrated.com
The SIMO buck-boost regulator utilizes a pulse frequency
modulation (PFM) control scheme. The switching frequency for each output is a function of the input voltage,
output voltage, load current, and inductance. Maxim
offers a SIMO calculator to aid in the understanding of the
switching frequency.
Maxim Integrated │ 67
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
At no load, switching frequencies can be as low as 10Hz.
It is possible to get SIMO switching frequencies that are
high (5.7MHz) with all of the worst-case conditions: high
input voltage (4.5V), low inductance (1.0µH), high output
voltage (5.0V), low peak current limit (0.5A), and high
utilization (80% which is 90mA with these conditions).
With these high switching frequencies, the SIMO efficiency is poor. The maximum switching frequencies for
designs should be no more than 3MHz. For example, in
the 5.7MHz example above if we change the inductance
to peak current limit from 0.5A to 0.707A while leaving the
load current at 90mA, then the switching frequency drops
to 2.4MHz. If we put the peak current limit at 0.866A and
change the inductance to 1.5µH, then the switching frequency drops to 1MHz which provides a “nice” efficiency.
Unused Outputs
Do not leave unused outputs unconnected. If an output
left unconnected is accidentally enabled, inductor current
dumps into an open pin, and the output voltage can soar
above the absolute maximum rating, potentially causing
damage to the device. If the unused output is always
disabled (EN_SBBx = 0x4 or 0x5), connect that output to
ground. If an unused output can be enabled at any point
during operation (such as startup or accidental software
access), then implement one of the following:
●● Bypass the unused output with a 1µF ceramic capacitor
to ground.
●● Connect the unused output to the power input (IN_
SBB). This connection is beneficial because it does
not require an external component for the unused
output. The power input and its capacitance receives
the energy packets when the regulator is enabled
and VIN_SBB is below the target output voltage of
the unused output. Circulating the energy back to the
power input ensures that the unused output voltage
does not fly high.
• Note that some OTP options of the device have the
active-discharge resistors enabled by default (ADE_
SBBx) such that connecting an unused output SBBx
to IN_SBB creates a 140Ω (RAD_SBBx) to ground
until software can be ran to disable the active-discharge resistor. Connecting an unused SBBx to
IN_SBB is not recommended if the regulator's
active-discharge resistor is enabled by default.
●● Connect the unused output to another power output
that is above the target voltage of the unused output.
In the same way as the option listed above, this connection is beneficial because it does not require an
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external component for the unused output. Unlike the
option above, this connection is preferred in cases
where the unused output voltage bias level is always
above the unused output voltage target because no
energy packages are provided to the unused output.
• Note that some OTP options of the device have the
active-discharge resistors enabled by default (ADE_
SBBx). If the other power output used to bias the
unused output is normally off, then the active-discharge resistor of the unused output does not create a continuous current draw. Remember that once
the system is enabled, it should turn off the unused
output's active-discharge resistor (ADE_SBBx = 0).
LDO
The device includes one on-chip low-dropout linear regulator (LDO). This LDO is optimized to have low-quiescent
current and low dropout voltage. The input voltage range
of this LDO (VIN_LDO) allows it to be powered directly
from the main energy source such as a Li-Poly battery or
from an intermediate regulator. The linear regulator delivers up to 150mA.
Features
●●
●●
●●
●●
●●
150mA LDO
1.8V to 5.5V Input Volage Range
Adjustable Output Voltage
180mV Maximum Dropout Voltage
Programmable On-Chip Active Discharge
LDO Simplified Block Diagram
The LDO has one input (IN_LDO) and one output (LDO)
and several ports that exchange information with the rest
of the device (VREF, EN_LDO, ADE_LDO). VREF comes
from the main bias circuits. EN_LDO and ADE_LDO
are register bits for controlling the enable and activedischarge feature of the LDO. Refer to the Programmer’s
Guide for more information.
LDO Active Discharge Resistor
The LDO has an active-discharge resistor (RAD_LDO)
that automatically enables/disables based on a configuration bit (ADE_LDO) and the status of the LDO regulator.
Enabling the active discharge feature helps ensure a
complete and timely power down of all system peripherals.
The default condition of the active-discharge resistor feature is enabled such that whenever VSYS is above VPOR
and VIN_LDO is above 1.0V, the LDO active discharge
resistor is turned on. Note that when VIN_LDO is less than
1.0V, the NMOS transistor that controls the LDO active
discharge resistor loses its gate drive and becomes open.
Maxim Integrated │ 68
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
LDO Soft-Start
the LDO, then the two nodes can share the SBB0 output
capacitor (CSBB0). CIN_LDO reduces the current peaks
drawn from the battery or input power source during LDO
regulator operation.
More output capacitance results in higher input current surges during startup. The equation and example
describes the input current surge phenomenon during
startup.
Choose the output capacitor (CLDO) so that the effective
capacitance is equal to or greater than the value found
in Figure 19, based on expected load conditions for the
application. A single 10μF, 1005/0402 (mm/inch) capacitor
is recommended for typical applications, but ensure that
the load current and derated capacitance does not compromise the stability curve in Figure 19. Larger values of
CLDO improve stability and output PSRR, but increases
the input surge currents during soft-start and output voltage changes. The effective output capacitance should not
exceed 100μF to maintain LDO stability.
The soft-start feature of the LDO limits inrush current during startup. The soft-start feature is achieved by limiting the
slew rate of the output voltage during startup (dV/dtSS).
The input current (IIN) during soft-start is:
dV
IIN = CLDO dt
SS
+ ILDO
where CLDO is the capacitance on the output of the regulator, and dV/dtSS is the voltage change rate of the output.
For example, given the following conditions, the input
current (IIN) during soft-start is 22.5mA:
Given:
• CLDO = 10µF
• dV/dtSS = 1.25mV/µs
• RLDO = 185Ω (ILDO = 1.85V/185Ω = 10mA)
Calculation:
• IIN = 10µF x 1.25mV/µs + 10mA
• IIN = 22.5mA
LDO Applications Information
Input and Output Capacitor Selection
Sufficient input bypass capacitance (CIN_LDO) and output
capacitance (CLDO) is required for stable operation of the
LDO. Figure 19 provides guidance on capacitor selection
and refers to required effective capacitance, which is the
actual value of capacitance seen by the LDO during operation. Effective capacitance is almost always lower than
the nominal capacitance and is a commonly overlooked
design parameter. Determine the effective capacitance
by assessing the capacitor’s initial tolerance, variation
with temperature, and variation with DC bias. Consult the
capacitor manufacturer for specific details of derating.
Choose the input capacitor (CIN_LDO) so that the effective
capacitance is equal to or greater than the value found in
Figure 19, based on expected load conditions for the
application. A single 10μF, 1005/0402 (mm/inch) capacitor, is recommended for typical applications but ensure
that the load current and derated capacitance does not
compromise the stability curve in Figure 19. Larger values
of CIN_LDO improve stability and decoupling for the LDO
regulator. The floorplan of the device is such that SBB0
is adjacent to IN_LDO, and if SBB0 powers the input of
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For example, consider the case of the MAX77650A
where:
1. Size is very important.
2. The LDO input is powered by SBB0, which is 2.05V.
3. The LDO output is 1.85V.
4. The LDO output current is ≤80mA.
A small 1005/0402 (mm/inch) capacitor such as the
GRM155R60J106ME15 (Murata, 10μF, 6.3V X5R) gives
5.7μF at 60°C and 5.4μF at -20°C with the 1.85V bias
voltage and has a ± 20% tolerance, so the worst-case
effective capacitance is 4.3μF (5.4μF derated by 20%
tolerance). With just 4.3μF of capacitance at the output,
Figure 19 shows the LDO is stable with load currents of
≤35mA. To get stability at 80mA, 6μF is required. There
are a few options to consider:
●● Add more capacitors to the design.
●● Replace the 1005/0402 (mm/inch) capacitor with a
1608/0603 (mm/inch) capacitor.
●● Consider point-of-load capacitance in your assessment of effective capacitance. For example, if there
is a point-of-load capacitor downstream from the
LDO that is sufficiently close to the local LDO output
capacitor, it can cover the gap. The capacitor can be
considered “sufficiently close” if the PCB does not
add more than 25nH and 25mΩ of extra ESR and
ESL (more or less within 1”).
Note the impedance of either the input or output capacitor
(ESR, ESL) should be very low (i.e., ≤ 50mΩ + ≤ 5nH) for
frequencies up to 0.5MHz. Ceramic capacitors with X5R
or X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
Maxim Integrated │ 69
MAX77650/MAX77651
EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
8
7
6
5
OUTPUT CAPACITANCE
4
3
2
1
0
25
50
75
100
125
STABLE REGION
7
6
5
INPUT CAPACITANCE
4
3
2
1
UNSTABLE REGION
0
EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
8
STABLE REGION
EFFECTIVE CAPACITANCE (μF)
EFFECTIVE CAPACITANCE (μF)
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
0
150
UNSTABLE REGION
0
LOAD CURRENT (mA)
25
50
75
100
125
150
LOAD CURRENT (mA)
Figure 19. LDO Capacitance for Stability
IN_LDO
VREF
EN_LDO
ADE_LDO
150mA
LDO
LDO
RADE_LDO
SBB0
10µF*
(0402)
*THE FLOORPLAN IS SUCH
THAT THE SBB0 OUTPUT
CAPACITOR IS ALSO THE
IN_LDO INPUT CAPACITOR.
10µF
(0402)
LDO
Figure 20. LDO Simplified Block Diagram
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Maxim Integrated │ 70
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Current Sinks
Current Sink Applications Information
LED Assignment
The device has a 3-channel current sink driver designed
to drive LED's in portable devices. This block can also be
used as a general-purpose current sink driver for other
applications. The driver's on-time and frequency are
independently programmable for each output to achieve
a desired blink pattern. Alternatively, the LEDs can be
continuously on (i.e., not blinking). The blink period is
programmable from 0.5s to 8s,with an on-time duty cycle
from 6.25% to 100%.
The three current sinks (LED0, LED1, LED2) are identical. In a typical application where a red, green, blue LED
cluster is used (RGB), the assignment of the RGB elements to the LED0/1/2 pins should be done in whatever
way makes the PCB layout the easiest.
Unused Current Sink Ports
If a current sink port is not utilized in a given application, connect that port to ground. Additionally, software
should ensure that the unused current sink is not enabled
(EN_LEDx = 0).
Figure 21 utilizes a common set of clock dividers to
drive three identical current sink modules. Refer to the
Programmer’s Guide for more information.
BIAS
CLK_64_S
CLK
EN_LED_MSTR
CLOCK
DIVIDER
CLK_64
CLOCK DIVIDER
AND INVERTER
CURRENT SINK
BRT_LED0[4:0]
DAC
INV_LED0
P_LED0[3:0]
D_LED0[3:0]
CLK_32
LED_FS0[1:0]
PWM
LOGIC
BRT_LED1[4:0]
INV_LED0
P_LED1[3:0]
D_LED1[3:0]
CLK_32
LED_FS1[1:0]
BRT_LED24:0]
INV_LED0
P_LED2[3:0]
D_LED2[3:0]
CLK_32
LED_FS2[1:0]
EN_LED0
CLK_32
LED0
2/4/8Ω
CURRENT SINK
LED1
CURRENT SINK
LED2
LGND
Figure 21. Current Sink Block Diagram
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Maxim Integrated │ 71
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
I2C
functional diagram for the I2C based communications
controller. For additional information on I2C, refer to the
I2C Bus Specification and User Manual that is available
for free on the Internet.
The MAX77650 features a revision 3.0 I2C-compatible,
2-wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). The
MAX77650/MAX77651 act as slave-only devices where
they rely on the master to generate a clock signal. SCL
clock rates from 0Hz to 3.4MHz are supported. I2C is
an open-drain bus, and therefore, SDA and SCL require
pullups. Optional resistors (24Ω) in series with SDA and
SCL protect the device inputs from high-voltage spikes
on the bus lines. Series resistors also minimize crosstalk
and undershoot on bus signals. Figure 22 shows the
Features
●● I2C Revision 3 Compatible Serial Communications
Channel
●● 0Hz to 100kHz (Standard Mode)
●● 0Hz to 400kHz (Fast Mode)
●● 0Hz to 1MHz (Fast Mode Plus)
●● 0Hz to 3.4MHz (High-Speed Mode)
●● Does not utilize I2C Clock Stretching
COMMUNICATIONS CONTROLLER
VIO
SCL
INTERFACE
DECODERS
SHIFT REGISTERS
BUFFERS
COM
SDA
GND
PERIPHERAL
0
PERIPHERAL
1
PERIPHERAL
2
PERIPHERAL
N-1
PERIPHERAL
N
Figure 22. I2C Simplified Block Diagram
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Maxim Integrated │ 72
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Figure 23. I2C System Configuration
S
Sr
VIO accepts voltages from 1.7V to 3.6V (VIO). Cycling VIO
does not reset the I2C registers. When VIO is less than
VIOUVLO and VSYS is less than VSYSUVLO, SDA and
SCL are high impedance.
P
SDA
tSU;STA
tSU;STO
SCL
tHD;STA
tHD;STA
Figure 24. I2​C Start and Stop Conditions
I2C System Configuration
The I2C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
A device on the I2C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates the SCL clock signals to control
the data transfer is a master. Any device that is being
addressed by the master is considered a slave. The
MAX77650/MAX77651 I2C compatible interface operates as a slave on the I2C bus with transmit and receive
capabilities.
I2C Interface Power
The MAX77650/MAX77651 I2C interface derives its
power from VIO. Typically a power input such as VIO
would require a local 0.1μF ceramic bypass capacitor to
ground. However, in highly integrated power distribution
systems, a dedicated capacitor might not be necessary. If
the impedance between VIO and the next closest capacitor (≥ 0.1μF) is less than 100mΩ in series with 10nH, then
a local capacitor is not needed. Otherwise, bypass VIO to
GND with a 0.1µF ceramic capacitor.
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I2C Data Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
is high are control signals. See the I2C Start and Stop
Conditions section. Each transmit sequence is framed by
a START (S) condition and a STOP (P) condition. Each
data packet is nine bits long: eight bits of data followed by
the acknowledge bit. Data is transferred with the MSB first.
I2C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a
START condition. A START condition is a high-to low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA, while SCL is high. See Figure 24.
A START condition from the master signals the beginning
of a transmission to the MAX77650/MAX77651. The master terminates transmission by issuing a not-acknowledge
followed by a STOP condition. See the I2C Acknowledge
Bit section for information on the not-acknowledge. The
STOP condition frees the bus. To issue a series of commands to the slave, the master can issue repeated start
(Sr) commands instead of a STOP command to maintain
control of the bus. In general, a repeated start command
is functionally equivalent to a regular start command.
When a STOP condition or incorrect address is detected,
the MAX77650/MAX77651 internally disconnect SCL
from the serial interface until the next START condition,
minimizing digital noise and feedthrough.
Maxim Integrated │ 73
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
I2C Acknowledge Bit
Both the I2C bus master and the MAX77650/MAX77651
(slave) generate acknowledge bits when receiving data.
The acknowledge bit is the last bit of each nine bit data
packet. To generate an acknowledge (A), the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep it
low during the high period of the clock pulse. See Figure
25. To generate a not-acknowledge (nA), the receiving
device allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
The MAX77650/MAX77651 issue an ACK for all register
addresses in the possible address space even if the particular register does not exist.
I2C Slave Address
The I2C controller implements 7-bit slave addressing. An
I2C bus master initiates communication with the slave by
issuing a START condition followed by the slave address.
See Figure 26. The OTP address is factory programmable
for one of two options. See Table 11. All slave addresses
not mentioned in the Table 11 are not acknowledged.
NOT ACKNOWLEDGE (NA)
S
ACKNOWLEDGE (A)
SDA
tSU;DAT
1
SCL
2
8
tHD;DAT
9
Figure 25. Acknowledge Bit
S
SDA
1
0
0
1
0
0
0
R/W
A
ACKNOWLEDGE
SCL
1
2
3
4
5
6
7
8
9
Figure 26. Slave Address Example
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Table 11. I2C Slave Address Options
ADDRESS
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
Main Address
(ADDR = 1)*
0x48, 0b 100 1000
0x90, 0b 1001 0000
0x91, 0b 1001 0001
Main Address
(ADDR = 0)*
0x40, 0b 100 0000
0x80, 0b 1000 0000
0x81, 0b 1000 0001
Test Mode**
0x49, 0b 100 1001
0x92, 0b 1001 0010
0x93, 0b 1001 0011
*Perform all reads and writes on the Main Address. ADDR is a factory one-time programmable (OTP) option, allowing for address
changes in the event of a bus conflict. Contact Maxim for more information.
**When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible, leave the test
mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim.
I2C Clock Stretching
In general, the clock signal generation for the I2C bus is
the responsibility of the master device. The I2C specification allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77650/MAX77651 do not use any
form of clock stretching to hold down the clock line.
I2C General Call Address
The MAX77650/MAX77651 do not implement the I2C
specifications general call address. If the MAX77650/
MAX77651 see the general call address (0b0000_0000),
they do not issue an acknowledge.
I2C Device ID
The MAX77650/MAX77651 do not support the I2C Device
ID feature.
I2C Communication Speed
The MAX77650/MAX77651 are compatible with all 4 communication speed ranges as defined by the Revision 3
I2C specification:
●●
●●
●●
●●
0Hz
0Hz
0Hz
0Hz
to
to
to
to
100kHz (Standard Mode)
400kHz (Fast Mode)
1MHz (Fast Mode)
3.4MHz (High-Speed Mode)
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
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pullup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds, the
pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing
section of the I2C Bus Specification and User Manual
that is available for free on the Internet for detailed guidance on the pullup resistor selection. In general for bus
capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup
resistors, a 400kHz bus needs about a 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω pullup resistors. Note
that when the open-drain bus is low, the pullup resistor is
dissipating power, lower value pullup resistors dissipate
more power (V2/R).
Operating in high-speed mode requires some special considerations. For a full list of considerations, see the I2C
Communication Speed section. The major considerations
with respect to the MAX77650/MAX77651:
●● The I2C bus master use current source pull-ups to
shorten the signal rise.
●● The I2C slave must use a different set of input filters
on its SDA and SCL lines to accommodate for the
higher bus.
●● The communication protocols need to utilize the highspeed master code.
At power-up and after each stop condition, the MAX77650/
MAX77651 input filters are set for standard mode, fast
mode, and fast mode plus (i.e., 0Hz to 1MHz). To switch
the input filters for high-speed mode, use the high-speed
master code protocols that are described in the I2C
Communication Protocols section.
Maxim Integrated │ 75
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
I2C Communication Protocols
●● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●● The master sends an 8-bit register pointer.
●● The slave acknowledges the register pointer.
●● The master sends a data byte.
●● The slave updates with the new data
●● The slave acknowledges or not acknowledges
the data byte. The next rising edge on SDA loads
the data byte into its target register and the data
becomes active.
●● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
The MAX77650/MAX77651 supports both writing and
reading from its registers.
Writing to a Single Register
Figure 27 shows the protocol for the I2C master device to
write one byte of data to the MAX77650/MAX77651. This
protocol is the same as the SMBus specification’s write
byte protocol.
The write byte protocol is as follows:
●● The master sends a start command (S).
●● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1 1
8
1
8
S
SLAVE ADDRESS
0 A
REGISTER POINTER
A
DATA
R/nW
SDA
B1
B0
A
1
1
A OR NA P OR SR*
NUMBER
OF BITS
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
ACKNOWLEDGE
SCL
7
8
9
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR <=1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
Figure 27. Writing to a Single Register with the Write Byte Protocol
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Maxim Integrated │ 76
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Writing Multiple Bytes to Sequential Registers
●● The slave acknowledges the register pointer.
●● The master sends a data byte.
●● The slave acknowledges the data byte. The next rising edge on SDA load the data byte into its target
register and the data will become active.
●● Steps 6 to 7 are repeated as many times as the
master requires.
●● During the last acknowledge related clock pulse, the
master can issue an acknowledge or a not acknowledge.
●● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their
current state.
Figure 28 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte protocol above, except the master continues to write after it
receives the first byte of data. When the master is done
writing it issues a stop or repeated start.
The writing to sequential registers protocol is as follows:
●● The master sends a start command (S).
●● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
●● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●● The master sends an 8-bit register pointer.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1 1
8
1
8
1
S
SLAVE ADDRESS
0 A
REGISTER POINTER X
A
DATA X
A
8
1
8
1
DATA X+1
A
DATA X+2
A
8
1
R/NW
REGISTER POINTER = X + 1
8
1
DATA N-1
A
REGISTER POINTER = X + (N-2)
SDA
B1
B0
Α
NUMBER
OF BITS
Α
NUMBER
OF BITS
Α
REGISTER POINTER = X + 2
A OR
DATA N
NA
Α
REGISTER POINTER = X + (N-1)
A
B9
9
1
1
P OR
SR*
NUMBER
OF BITS
Β
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
ACKNOWLEDGE
SCL
SDA
7
B1
8
B0
DETAIL: Α
A
ACKNOWLEDGE
SCL
7
8
9
DETAIL: Β
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
*P FORCES THE BUS
FILTERS TO SWITCH
TO THEIR <=1MHZ
MODE. SR LEAVES
THE BUS FILTERS IN
THEIR CURRENT
STATE.
Figure 28. Writing to Sequential registers X to N
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Maxim Integrated │ 77
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Reading from a Single Register
●● The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
●● The master issues a not acknowledge (nA).
●● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their current state.
Figure 29 shows the protocol for the I2C master device to
read one byte of data to the MAX77650/MAX77651. This
protocol is the same as the SMBus specification’s read
byte protocol.
The read byte protocol is as follows:
●● The master sends a start command (S).
●● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
●● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●● The master sends an 8-bit register pointer.
●● The slave acknowledges the register pointer.
●● The master sends a repeated start command (Sr).
●● The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
●● The addressed slave asserts an acknowledge by
pulling SDA low.
Note that when the MAX77650/MAX77651 receive a stop
they do not modify their register pointer.
Reading from Sequential Registers
Figure 30 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an acknowledge to signal the
slave that it wants more data: when the master has all the
data it requires it issues a not acknowledge (nA) and a
stop (P) to end the transmission.
LEGEND
MASTER TO SLAVE
*P FORCES THE BUS FILTERS TO SWITCH
TO THEIR <=1MHZ MODE. SR LEAVES THE
BUS FILTERS IN THEIR CURRENT STATE.
SLAVE TO MASTER
1
7
1 1
8
1 1
7
1 1
8
S
SLAVE ADDRESS
0 A
REGISTER POINTER X
A Sr
SLAVE ADDRESS
1 A
DATA X
R/nW
1
1
nA P or Sr*
NUMBER
OF BITS
R/nW
Figure 29. Reading from a Single Register with the Read Byte Protocol
LEGEND
MASTER TO SLAVE
*P FORCES THE BUS FILTERS TO SWITCH TO
THEIR <=1MHZ MODE. SR LEAVES THE BUS
FILTERS IN THEIR CURRENT STATE.
SLAVE TO MASTER
1
7
1 1
8
1 1
7
1 1
8
1
S
SLAVE ADDRESS
0 A
REGISTER POINTER X
A SR
SLAVE ADDRESS
1 A
DATA X
A
1
8
1
A
DATA X+3
A
R/NW
R/nW
8
1
8
DATA X+1
A
DATA X+2
REGISTER POINTER = X + 1
REGISTER POINTER = X + 2
8
1
DATA N-2
A
REGISTER POINTER =
X + (N-3)
NUMBER
OF BITS
REGISTER POINTER = X + 3
8
1
DATA N-1
A
REGISTER POINTER =
X + (N-2)
NUMBER
OF BITS
8
1
DATA N
NA
REGISTER POINTER =
X + (N-1)
1
P OR
SR*
NUMBER
OF BITS
Figure 30. Reading Continuously from Sequential Registers X to N
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Maxim Integrated │ 78
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
The continuous read from sequential registers protocol is
as follows:
●● The master sends a start command (S).
●● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
●● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●● The master sends an 8-bit register pointer.
●● The slave acknowledges the register pointer.
●● The master sends a repeated start command (Sr).
●● The master sends the 7-bit slave address followed
by a read bit (R/W = 1). When reading the RTC timekeeping registers, secondary buffers are loaded with
the timekeeping register data during this operation.
●● The addressed slave asserts an acknowledge by
pulling SDA low.
●● The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
●● The master issues an acknowledge (A) signaling the
slave that it wishes to receive more data.
●● Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a not acknowledge (nA) to signal
that it wishes to stop receiving data.
●● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a stop (P) ensures that
the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their
current state.
Note that when the MAX77650/MAX77651 receive a stop,
they do not modify their register pointers.
Engaging HS-mode for operation up to 3.4MHz
Figure 31 shows the protocol for engaging HS-mode
operation. HS-mode operation allows for a bus operating
speed up to 3.4MHz.
The engaging HS mode protocol is as follows:
●● Begin the protocol while operating at a bus speed of
1MHz or lower
●● The master sends a start command (S).
●● The master sends the 8-bit master code of 0b0000
1XXX where 0bXXX are don’t care bits.
●● The addressed slave issues a not acknowledge (nA).
●● The master may now increase its bus speed up to
3.4MHz and issue any read/write operation.
The master can continue to issue high-speed read/write
operations until a stop (P) is issued. To continue operations in high speed mode, use repeated start (Sr).
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
8
1 1
S
HS-MASTER CODE
nA SR
FAST-MODE
ANY R/W PROTOCOL
FOLLOWED BY SR
SR
ANY R/W PROTOCOL
FOLLOWED BY SR
HS-MODE
SR
ANY READ/WRITE
PROTOCOL
P
FAST-MODE
Figure 31. Engaging HS Mode
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Maxim Integrated │ 79
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Typical Application Circuit
MAX77650/MAX77651
DC CHARGING SOURCE
4.7µF
25V
(0603)
1µF
10V
(0402)
SYS
CHGIN
BATT
GND
LITHIUM ION BATTERY CHARGER
VL
VSYS
4.7µF
6.3V
(0603)
+ LITHIUM ION
BATTERY
T
TBIAS
THM
IN_SBB
VSYS
CSYS
22µF/6.3V
(0603)
L
1.5µH
BIAS
SUCH AS:
SYS, BATT, SBB2
SIMO BUCK-BOOST
GPIO
AMUX
AMUX
SYSTEM
RESOURCES
VSBB1
SBB2
10µF
6.3V
(0402)
BST
LED0
LED1
LED2
LGND
GPIO
VSBB0
SBB1
LXA
LXB
CBST
3300pF/6.3V
(0201)
VSYS
SBB0
PGND
VSBB2
GPIO
IN_LDO
CURRENT
SINKS
LDO
VSBB0
LDO
10µF
6.3V
(0402)
VLDO
VIO
GPIO
I 2C
ANALOG
MULTIPLEXER
SDA
SCL
10kΩ
nRST
nEN
TOP LEVEL
nIRQ
PWR_HLD
VIO/POWER
SDA
SCL
nRST
nIRQ
*
*
PWR_HLD
AMUX
*THE PROCESSOR HAS INTERNAL
PULLUP RESISTORS FOR NRST AND
NIRQ.
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PROCESSOR
ADC INPUT
Maxim Integrated │ 80
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
OPTIONS
MAX77650EWV+T*
-40°C to +85°C
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/1.5875V/3.95V,
samples with various OTP options
MAX77650AEWV+T
-40°C to +85°C
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/1.5875V/3.95V,
production device, DIDM=0b00, CID=0b0011***
MAX77650CEWV+T
-40°C to +85°C
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/1.5875V/3.95V,
production device, DIDM=0b00, CID=0b1010***
MAX77651EWV+T*
-40°C to +85°C
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/5.25V/5.25V,
samples with various OTP options
MAX77651AEWV+T
-40°C to +85°C
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/5.25V/5.25V,
production device, DIDM=0b01, CID=0b0110***
MAX77651BEWVA+T
-40°C to +85°C
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/5.25V/5.25V,
production device, DIDM=0b01, CID=0b1000***
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape-and-reel.
*Samples only, not for production. Contact factory for more information.
**Future product—Contact Maxim for availability.
***See the Programmer’s Guide for the options associated with a specified DIDM and CID.
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Maxim Integrated │ 81
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Charger Optimized for Small Li+
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/17
1
5/17
2
6/17
PAGES
CHANGED
DESCRIPTION
Initial release
—
Updated Electrical Characteristics—SIMO Buck-Boost table, Typical Operating
Characteristics, Table 1. Regulator Summary, Manual Reset in Features and Benefits
section, Inductor Selection section, and LDO Applications Information section, added
new Figure 19, removed future product notation from MAX77651AEWV+T in Ordering
Information table
Updated solution size in Benefits and Features section, updated Absolute Maximum
Ratings section and Figure 18
3
7/17
Fixed typos, added common conditions to Electrical Characteristics tables, updated
Typical Operating Characteristics, updated Figure 19, updated Typical Application
Circuit
4
7/17
Added hyperlink to Programmer’s Guide, added MAX77650CEWV+ to Ordering
Information table
1, 9, 19, 25,
26, 30, 32, 36,
38, 65, 68, 79
1, 7, 63
7, 10−12, 17,
18, 20, 21, 24,
30, 36, 68, 69,
79
21, 37, 40, 52,
55, 56, 59, 62,
65, 68, 71, 81
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 82
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