Design of 2.4GHz Low Power High Gain Current Reuse Low Noise

Design of 2.4GHz Low Power High Gain Current Reuse Low Noise
Design of 2.4GHz Low Power High Gain Current Reuse Low Noise Amplifier
1
S.Manjula1 , D.Selvathi2
Research Scholar, Professor ECE Department, 1,2 Mepco Schlenk Engineering College,
Tamilnadu, India-626005
E- mail: manjulasankar@gmail.com
2
Abstract: In this paper, we present a 2.4GHz t wo-stage structure of current reuse Low No ise Amp lifier (LNA ) in
0.13µm CM OS technology. It consists of two stages which are connected with interstage resonance. The first stage
consists of inductively degenerated common source amplifier and the second stage consists of inductively
degenerated current reuse LNA structure. These two stages are operated at a nominal supply voltage of 1V. This
configuration provides better input matching, lower noise figure, high gain, good reverse isolation and low power
consumption. The simu lated LNA presents a maximu m power gain of 26dB, a high reverse isolation of -38dB and a
good input/output return losses are -20.8dB and -11.3d B at a frequency of 2.4GHz. An excellent noise figure (NF)
of 2.5d B was obtained with a power d issipation of 2 mW at 1V power supply.
PACS : 84.40.Dc
Keywords : LNA,CMOS and lo w power consumption
1. Introduction:
Recently, with the rapid growth of wireless communication technologies led to the development
of wireless sensor networks (WSNs) and wireless body-area networks (WBANs) aiming to cover
applications in the medical and health-care sectors. The IEEE 802.15.4 standard supports 2.4GHz short
range wireless communication in WSN and allows for low power hungry designs [1]. Wireless sensor
network applications demand longer battery life which requires low power transceiver. Due to the
advantages of CMOS technologies such as low power, low cost, and higher integration, etc., analog and
RF circuits are designed in the platform of semiconductor technology [2].
In the RF receiver front-end, Low noise amplifier is a first important component. For designing
LNA, there is tradeoff between gain, noise figure and power consumption. A conventional cascode
topology has been widely used in low noise amplifier (LNA) design to optimize circuit performance such
as high gain and high reverse isolation [3]. Nevertheless, it is not suitable for low-voltage applications
because the supply voltage must be larger than twice the threshold voltage of the transistors. For the same
reason, the cascode structure of common source current reuse LNA is also not suitable for low voltage
and low power applications [4]. It requires approximately supply voltage of 1.5V or above [6]. Now-adays, for low power applications, push pull configuration of current reuse LNA is used. This current
reused LNA is composed of two common source configuration stages under common current structure
that can save power consumption effectively when compared with cascode topology [5].
In this paper, a two-stage current reuse LNA in 0.13µm technology is proposed. In this proposed
LNA, the first stage is adopted common source configuration for high gain. The second stage is adopted
current reuse LNA having push pull configuration with inductive degeneration for further improving gain,
noise figure and power consumption. These two stages are connected with interstage inductor which
provides high gain [6].These two stages are operated at 1V supply voltage. This structure is more suitable
for low voltage and low power applications.
2. Proposed Architecture :
The conventional cascode topology has numerous benefits, such as good reverse isolation, quasi
flat band large gain and low noise figure, which make it very popular in LNA designs. Nevertheless,
stacking of two NMOS transistors, it suffers from a nominal supply voltage which is not suited with
aggressive scaling of the advanced CMOS technologies.
Fig.1 Proposed Architecture
To avoid the drawback of cascode structure, two stage structure of current reuse LNA is proposed
as shown in Fig. 1 which is composed of two stage structure with interstage inductor. In first stage,
inductively degenerated common source amplifier is used to produce gain which is not sufficient for
applications. In this first stage, cascode structure is avoided to reduce the supply voltage. The second
stage is needed to achieve proper gain. In the second stage of current reuse LNA, to further increase the
voltage gain with low DC power under a minimum supply voltage, it consists of inductively degenerated
PMOS CS amplifier stacked on top of inductively degenerated NMOS CS amplifier. Due to this inherent
current reuse complementary structure, the transconductance is increased with same current consumption
i.e. Gm(total)=Gm(P MOS)+Gm(NMOS) Due to the use of the CMOS amplifier stages in current reuse LNA, the
required supply voltage is reduced by one transistor overdrive compared with that of the cascode
amplifiers. The first and second stages are interconnected with series interstage inductor and it is operated
at a low supply voltage of 1V.
Fig.2 shows the input, output and interstage matching networks in two stage structure of current
reuse LNA. The input matching network (L1& L2) is used to match the input impedance to 50Ώ source
impedance.C1 is used as DC block capacitance. The extra capacitor Cd provides an additional degree of
design freedom by decoupling Q from power consumption [7]. L4 , C2 and C3 are used as interstage
matching network. The interstage inductor L4 value is calculated to resonate in series with the input
capacitance of MP and MN [8].C2 and C3 provides DC isolation between gate biases. L6, L7, C4 and C5
are used as output matching network. High impedance loads are presented through inductors L6 and L7 to
achieve high gain, while capacitor C4 helps to tune the output to the desired operating frequency.
Fig.2.Interstage Matching Network
2.1.Small Signal Characteristics:
Fig.3 Small Signal Model of Input Stage of Proposed LNA
The inductive degeneration technique does not degrade the amplifier’s noise performance and it
easily matched the input impedance [3]. From Fig.1, the input impedance of first stage of inductive
degeneration CMOS LNA is expressed by [3]:
(1)
where
(2)
+
(3)
At the resonance (operating) angular frequency
(4)
The resulting impedance at resonance must be
(5)
The quality factor Q of the input circuit is
(6)
The overall transconductance of the device
(7)
is the transconductance of the NMOS device.
2.2. Noise Figure:
In a typical RF system, the sensitivity of the receiver is determined by the noise figure of the
LNA. To have a better understanding on the noise matching, the equivalent circuit of the input stage is
depicted in Fig. 3, where
and Zs indicate the thevenin’s equivalent circuit seen from the MOS
transistor to the source terminal, and
and
represent the mean-square values of the gate-induced
and channel noise currents, respectively.
The expressions of the gate noise current is given by
=4kT
(8)
where
and
+
The expressions of the gate noise current is given by
= 4kT γ
(9)
where δ and γ have typical values of 4/3 and 2/3 respectively.Note that
is zero bias drain
conductance. The noise resistance Rn , the optimum source impedance Zopt and the minimum noise factor
Fmin are expressed as [9],
(10)
(11)
(12)
where α =
and
is a correlation coefficient with a predicted value of 0.395.
2.3.Stability Consideration:
The stability is another important issue in LNA designs, and can be inspected by the reflection
coefficients at the matching networks and terminations. For a general two-port network, in order not to
initiate the undesirable oscillation, the necessary and sufficient conditions for the circuit stability are
given by [10]
(13)
>1
(14)
where
Δ = S11S22 – S12S21
(15)
If the S-parameters of an LNA satisfy conditions (1) and (2), it is stable for any passive load and
generator impedance. In other words, this amplifier is unconditionally stable.
3.Simulation Results:
The designed circuitry has been simulated using ADS. Fig. 4 shows the power gain of 26dB and
input return loss (S11) of -21dB .It shows that we achieve a high power gain and good input impedance
matching. Fig .5 shows the noise figure of 2.5dB. Fig.6 shows that the proposed LNA is unconditionally
stable.
Fig.4 Power Gain (S(2,1)) and Return Loss (S(1,1))
Fig.5 Noise Figure
Fig.6 Stability Factor
Table.1 compares simulated results of proposed LNA with other simulation results of published LNAs.
From this observation, our proposed LNA is suitable for low voltage and low power applications. Also, It
gives high gain and good return loss than other LNAs.
Table 1 Simulation results of this proposed LNA and previously published LNAs
Units
Proposed
work
[6]
[11]
[12]
Frequency
GHz
2.4
5.5
2.4
2.4
Technology
µm
0.13
.18
.18
.18
Supply voltage
V
1
1.8
1.8
0.9
S(2,1)
dB
26
20.5
11.2
-
S(1,1)
dB
-21
-18.5
<-11
-14
Noise figure
dB
2.5
1.8-2.6
2.15-2.7
2.2
Power consumption
mW
2
2
2.7
7.2
4.Conclusion
In this paper, a novel two stage structure of current reuse LNA configuration is proposed by applying an
current reuse structure. The combination of inductive degeneration of current source amplifier and current
reuse structure is produced higher power gain, good input matching and lower noise figure
simultaneously. The proposed LNA allows good trade-off among the LNAs design parameters.
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