MRFIC1819 Technical Data Sheet
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MRFIC1819
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3.6 V 18OO MHz GaAs
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Integrated Power Amplifier
The MRFIC1819 is a single supply, RF power amplifier designed for the
1W DCS1800/PCS1900 handheld radio. The negative power supply is
generated inside the chip using RF rectification, which avoids any spurious
signal. A built in priority switch is provided to prevent Drain Voltage being
applied on the RF lineup if not properly biased by the Negative Voltage. The
device is packaged in the TSSOP–16EP package, with exposed backside
pad, which allows excellent electrical and thermal performance through a
solderable contact.
• Target 3.6 V Characteristics:
RF Input Power: 6.0 dBm
RF Output Power: 33 dBm Typical
Efficiency: 41% Typical
• Single Positive Supply Solution
•
•
•
INTEGRATED RF
POWER AMPLIFIER
DCS1800/PCS1900
SEMICONDUCTOR
TECHNICAL DATA
16
Negative Voltage Generator
1
Positive Step–Up Voltage Generator
VSS Check Switch for Gate–Drain Priority
PLASTIC PACKAGE
CASE 948L
(TSSOP–16EP, Tape and Reel Only)
PIN CONNECTIONS
VP
1
16
VDB
VD3
2
15
VD0
RFout
3
14
InBuf
RFout
4
13
RFin
RFout
5
12
VD1
Bias3
6
11
VD2
Bias2
7
10
VSC
Bias1
8
9
VSS
Simplified Block Diagram
VD1
VD2
VD3
RF In
RF Out
Bias1
Bias2
Bias3
Negative
Voltage Generator
In Buf
(Top View)
VSS
VP
VSC
ORDERING INFORMATION
VD0
VDB
This device contains 9 active transistors.
Device
Operating
Temp Range
Package
MRFIC1819R2
TA = –40 to 85°C
TSSOP–16EP
 Motorola, Inc. 2000
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Rev 3
1
Freescale Semiconductor,
Inc.
MRFIC1819
Symbol
Value
Unit
Supply Voltage
Rating
VD1, 2, 3
6.0
V
RF Input Power
Pin
12
dBm
Pout
36
dBm
RF Output Power
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Recommended Operating
Contitions or Electrical Characteristics tables.
2. ESD (electrostatic discharge) immunity meets Human Body Model (HBM) ≤250 V and
Machine Model (MM) ≤60 V. This device is rated Moisture Sensitivity Level (MSL) 4.
Additional ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
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Characteristic
Symbol
Min
Typ
Max
Unit
VD0, VDB,
VD1, 2, 3
3.0
–
5.0
Vdc
Input Power
Pin
5.0
–
10
dBm
Input Frequency
fRF
1700
–
1900
MHz
Operating Case Temperature Range
TC
–40
–
85
°C
Storage Temperature Range
Tstg
–55
–
150
°C
Supply Voltage
ELECTRICAL CHARACTERISTICS (VD0 = VDB = 3.6 V, VD1, 2, 3 = 3.6 V, Pin = 6.0 dBm, Peak measurement at 12.5%
duty cycle, 4.6 ms Period, TA = 25°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency Range
BW
1710
–
1785
MHz
Output Power
Pout
32
33
–
dBm
Power Added Efficiency
PAE
35
41
–
%
Output Power (Tuned for PCS Band 1850 to 1910 MHz)
Pout
–
33
–
dBm
Power Added Efficiency (Tuned for PCS Band 1850 to 1910 MHz)
PAE
–
41
–
%
Output Power at low voltage (VD0 = VDB = 3.0 V, VD1, 2, 3 = 3.0 V)
Pout
30.5
31
–
dBm
–
–
–45
–35
–40
–30
Harmonic Output
2fo
3fo
–
Input Return Loss
|S11|
–
12
–
dB
Output Power Isolation (Pin = 10 dBm, VD0 = VDB = 3.0 V,
VD1, 2&3 = 0 V)
Poff
–
–30
–
dBm
–
–90
–
dBm
Vss
–4.85
–
–
V
Negative Voltage Setting Time (Pin = 6.0 dBm, VD0 = VDB stepped
from 0 to 3.0 V)
Ts
–
0.7
–
µs
Positive Voltage (Pin = 6.0 dBm,VD0 = VDB = 3.0 V)
VP
5.7
6.6
–
V
Pspur
–
–
–60
dBc
Noise Power (In 100 kHz, 1805 to 1880 MHz)
Negative Voltage (Pin = 6.0 dBm, VD0 = VDB = 3.0 V)
Stability–Spurious Output (Pout = 0 to 33 dBm, Load VSWR 6:1 all phase
angles, source VSWR = 3:1, at any phase angle,
Adjust VD1, 2&3 for specified power)
Load Mismatch Stress (Pout = 3 to 33 dBm, Load VSWR = 10:1
all phase angles, 5 seconds, Adjust VD1, 2&3 for specified power)
2
dBc
No Degradation in Output Power
Before & After Test
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MAXIMUM RATINGS
Freescale Semiconductor,
Inc.
MRFIC1819
Zin
OHMS
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f
MHz
R
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Table 1. Optimum Loads Derived from
Circuit Characterization
ZOL*
OHMS
jX
R
jX
1710
–66.87
14.51
5.88
3.30
1720
–67.40
14.67
5.86
3.20
1730
–68.07
14.82
5.79
3.10
1740
–68.73
15.08
5.74
2.93
1750
–69.29
15.30
5.67
2.75
1760
–69.80
15.55
5.59
2.58
1770
–70.30
15.80
5.53
2.46
1780
–70.89
16.00
5.44
2.28
1790
–71.20
16.16
5.42
2.25
Zin represents the input impedance of the device.
ZOL* represents the conjugate of the optimum output load to present
to the device.
Figure 1. Reference Circuit
VSS
VDB
VP
VD1, 2 and 3
VST
R1
R4
D1
R3
C1
C5
C2
C4
T3
50 Ω In
L1
9
8
N.C.
10
7
T1
T2
T8
11
6
12
5
R5
C12
C15
C16
R2
C3
C6
Gnd
T4
13
MRFIC1819
TSSOP16EP
Note: Use high Q cap for C9
for best PAE/Pout
C10
C9
C11
4
14
3
15
2
16
1
T7
T6
T5
50 Ω Out
C8
C7
L3
L2
C14
C1,C2
C3,C14
C4,C6,C8,C11,
C15,C16
C5
C7
C9
C10
C12
C13
R1,R2
R3
C13
47 nF
330 pF
22 pF
10 nF
2.7 pF
3.9 pF AVX Accu–F
1.0 pF
0.8 pF
47 pF
15 kΩ
7.5 kΩ
R4
R5
L1
L2
L3
D1
T1, T2
T3
T4
T5
T6,T7
T8
1.0 kΩ
680 Ω
1.8 nH
33 nH
2.7 nH
Zener 5.1 V MMSZ4689T1
60 Ω Microstrip Line, L = 3.0 mm
50 Ω Microstrip Line, L = 4.5 mm
80 Ω Microstrip Line, L = 4.0 mm
50 Ω Microstrip Line, L = 17 mm
30 Ω Microstrip Line, L = 1.0 mm
50 Ω Microstrip Line, L = 2.5 mm
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Freescale Semiconductor,
Inc.
MRFIC1819
3.0 V
0V
TxEn
BS
12
8
Vbat
CE
3.0 V
DCS
0V
GSM
7
Vramp
11
1
MC33170
Pin 1
MTSF3N02HD
5
A
B
6
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C5
10 µF
2.0 V
0V
3
U1
G
R11
10 k
R2 10 k
A1
(Micro 8)
S
Pin 1
D
Freescale Semiconductor, Inc...
R5 0
C39
0.1 µF
R1
10 k
C1
100 nF
VD1
VD2
2
4
2
VSS
VDB
VP
5
6
3
4
10
VD3
B
10
Gnd
8
9
R13A 15 kΩ
C16
22 pF
R13B 15 kΩ
C19
330 pF
C17
47 nF
C21
10 nF
C18
47 nF
C6 22 pF
C20 22 pF
9
8
10
7
Zc = 60 Ω L = 3.0 mm 11
Zc = 60 Ω L = 3.0 mm 12
Zc = 50 Ω L = 2.5 mm 13
Zc = 50 Ω
50 Ω In
L1
1.8 nH
L = 4.5 mm
R13C 7.5 kΩ
R15
680 Ω
C15
22 pF
C12
0.8 pF
Zc = 80 Ω
L = 4.0 mm
6
MRFIC1819
TSSOP16EP
C9 3.9 pF
C10 1.0 pF
5
C11 22 pF
4
14
3
15
2
16
1
L3
2.7 nH
Note: Use high Q
cap for C9 for best
PAE/Pout
Zc = 30 Ω
L = 1.0 mm
Zc = 30 Ω
L = 1.0 mm
Zc = 50 Ω L = 17 mm
C7
2.7 pF
50 Ω Out
C8
22 pF
L2 33 nH
C14
330 pF
4
C13
47 pF
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Figure 2. 3.6 V DCS Application Circuit
Freescale Semiconductor,
Inc.
MRFIC1819
3.0 V
0V
TxEn
BS
12
Vbat
CE
3.0 V
DCS
8
7
Vramp
11
1
2.0 V
0V
GSM
0V
MC33170
Pin 1
MTSF3N02HD
5
G
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A
C5
10 µF
B
3
U1
A1
(Micro 8)
R11
10 k
R2 10 k
6
S
D
Pin 1
R5 0
C39
0.1 µF
R1
10 k
C1
100 nF
2
VD1
VD2
VSS
VDB
VP
2
4
5
6
3
4
10
VD3
A
10
Gnd
8
9
R13B 12 k
C29
330 pF
C7
10 nF
C6
56 pF
R13A 6.8 k
Zc = 60 Ω
L = 3.0 mm
C4
56 pF
Zc = 60 Ω
L = 11 mm
50 Ω
In GSM
R13C 12 k
C8
10 nF
8
10
7
11
6
12
13
Zc = 50
C40
8.2 pF
9
L2
12 nH
C14
12 pF
C15
6.8 pF
C16
56 pF
5
MRFIC0919
50 Ω
Out GSM
4
TSSOP16EP
14
3
15
2
16
1
Zc = 50 Ω
Zc = 30 Ω
L = 7.0 mm
Zc = 50 Ω
L = 17 mm
C17
56 pF
C8
10 nF
C12
4.7 pF
L4
6.8 nH
C11
56 pF
C25 10 nF
B
8
C34 47 pF
C35 22 pF
R13A 15 kΩ
C41
47 nF
C36 22 pF
8
10
7
Zc = 60 Ω L = 3.0 mm 11
Zc = 60 Ω L = 3.0 mm 12
Zc = 50 Ω
50 Ω
ID DCS
L10
1.8 nH
Zc = 50 Ω
L = 2.5 mm
R10
680 Ω
C37
13
MRFIC1819
C9 22 pF
2
16
1
Zc = 30 Ω
L = 1.0 mm
50 Ω
Out DCS
Zc = 30 Ω
L = 1.0 mm
Zc = 50 Ω L = 17 mm
C22
2.7 pF
L3
2.7 nH
C10
330 pF
C32 1.0 pF
4
TSSOP16EP
15
L8 33 nH
C31 3.9 pF
5
3
Zc = 80 Ω
L = 4.0 mm
R13C 7.5 kΩ
6
0.8 pF14
L = 4.5 mm
C24
22 pF
C42
22 pF
R13B 15 kΩ
9
C33
22 pF
C30
10 nF
C26
47 pF
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Figure 3. 3.6 V GSM & DCS IPA Dual–Band Application Circuit with Companion Chip & NMOS Switch
Freescale Semiconductor,
Inc.
MRFIC1819
Figure 5. Power Added Efficiency
versus Frequency
35
PAE, POWER ADDED EFFICIENCY (%)
43
34
3.6 V
33
3.0 V
32
31
TA = 25°C
Pin = 6.0 dBm
30
1710
1720
1740
1755
1770
VD = 3.6, 4.2 V
42
3.0 V
41
40
39
TA = 25°C
Pin = 6.0 dBm
38
37
1710
1785
1720
f, FREQUENCY (MHz)
1740
1755
1770
1785
f, FREQUENCY (MHz)
Figure 6. Output Power versus Frequency
Figure 7. Output Power versus Frequency
35
34
Pout , OUTPUT POWER (dBm)
Pout , OUTPUT POWER (dBm)
TA = –40°C
34
TA = –40°C
33
25°C
32
85°C
31
VD = 3.0 V
Pin = 6.0 dBm
30
29
1710
1725
1740
1755
1770
85°C
33.2
32.8
32.4
VD = 3.6 V
Pin = 6.0 dBm
1725
1740
1755
1770
f, FREQUENCY (MHz)
Figure 8. Output Power
versus Frequency
Figure 9. Power Added Efficiency
versus Frequency
1785
46
PAE, POWER ADDED EFFICIENCY (%)
TA = –40°C
34.4
25°C
34
85°C
VD = 4.2 V
Pin = 6.0 dBm
33.2
1710
1725
1740
1755
f, FREQUENCY (MHz)
6
25°C
f, FREQUENCY (MHz)
34.8
33.6
33.6
32
1710
1785
35.2
Pout , OUTPUT POWER (dBm)
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Pout , OUTPUT POWER (dBm)
VD = 4.2 V
1770
1785
44
TA = –40°C
42
25°C
40
85°C
38
36
VD = 3.6 V
Pin = 6.0 dBm
34
1710
1725
1740
1755
1770
1785
f, FREQUENCY (MHz)
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Figure 4. Output Power
versus Frequency
Freescale Semiconductor,
Inc.
MRFIC1819
Figure 11. Power Added Efficiency
versus Drain Voltage
PAE, POWER ADDED EFFICIENCY (%)
70
TA = –40°C
30
85°C
10
25°C
–10
Pin = 6.0 dBm
f = 1750 MHz
–30
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
30
85°C
25°C
10
–10
Pin = 6.0 dBm
f = 1750 MHz
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
VD, DRAIN VOLTAGE (V)
Figure 12. Positive Voltage Generator Output
versus Drain Voltage
Figure 13. Positive Voltage Output
versus Frequency
TA = –40°C
7.2
6.8
85°C
25°C
6.4
Pin = 6.0 dBm
f = 1750 MHz
0
TA = –40°C
VD, DRAIN VOLTAGE (V)
7.6
6.0
50
–30
4.4
Vpos, POSITIVE VOLTAGE OUTPUT (V)
Vpos, POSITIVE VOLTAGE GENERATOR OUTPUT (V)
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Pout , OUTPUT POWER (dBm)
50
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.0
4.4
7.8
7.6
TA = –40°C
25°C
7.4
7.2
85°C
7.0
6.8
1710
VD = 3.6 V
Pin = 6.0 dBm
1725
VD, DRAIN VOLTAGE (V)
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1740
1755
1770
1785
f, FREQUENCY (MHz)
7
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Figure 10. Output Power
versus Drain Voltage
Freescale Semiconductor,
Inc.
MRFIC1819
Design Philosophy
The MRFIC1819 is a high performance three stage GaAs
IPA (Integrated Power Amplifier) designed for DCS/PCS
handheld radios (1710–1785 MHz DCS frequency band,
1850–1910 MHz PCS frequency band). With a 3.6 V battery
supply, it delivers typically 33 dBm of Output Power with 41%
Power Added Efficiency.
It features an internal Negative Voltage Generator based
on RF rectification of the input carrier after its amplification by
two dedicated buffer stages (see Internal Block Diagram).
This method eliminates spurs found on the Output signal
when using dc/dc converter type negative voltage
generators, either on or off chip. The buffer also generates a
step–up positive voltage which can be used to drive a
N–MOS drain switch.
The RF input power is split externally (different from
MRFIC0919) to the 3 stage RF line–up (Q1, Q2 and Q3) and
the Buffer amplifier (Q0, QB). This arrangement allows
separate operation of Voltage Generation and Power
Amplification for maximum flexibility.
External Circuit Considerations
The MRFIC1819 can be tuned by changing the values
and/or positions of the appropriate external components (see
Figure 1: Reference Circuit). While tuning the RF line–up, it is
recommended to apply external negative supply in order to
prevent any damage to the power amplifier stages. Poor
tuning on the input may not provide enough RF power to
operate the negative voltage generator properly.
Input matching is a shunt–L, series–L high–pass structure
and should be optimized at the rated RF Input power
(e.g. 6.0 dBm). However, broadband matching is easier with
a parallel 680 Ω resistor. This part can be removed to get
operation to a lower input power (e.g. 5.0 dBm). Since the
Input line feeds both 1st stage and buffer, Input matching
should be iterated with Buffer and Q1 drain matching. Note
that a dc blocking capacitor is included on chip.
RF input signal is fed to buffer amplifier using C12
capacitor (Figure 1). The value of this capacitor determines
the power split between RF line–up and buffer amplifier. C12
has been tuned to get the best trade–off between RF gain
and negative voltage on Pin 9.
First stage buffer amplifier is tuned with a short 80 Ω
microstrip line which may be replaced by a chip inductor (T4
on Figure 1). Second stage buffer amplifier is supplied and
matched through a discrete chip inductor. Those two
elements are tuned to get the maximum output from voltage
generator. The overall typical buffer current is about 50 mA;
however, the negative generator needs a settling time of
2.0 µsec (see burst mode paragraph). During this transcient
period of time, both stages are biased to IDSS which is about
200 mA each.
8
The step–up positive voltage available at Pin 1 is both
decoupled and maximised by a small shunt capacitor. This
positive voltage which is approximately twice the buffer drain
voltage can be used to drive a NMOS drain switch for best
performances.
Q1 drain is supplied and matched through a printed
microstrip line that could be replaced by a discrete chip
inductor as well. Its length (or equivalent inductor value) is
tuned by sliding the RF decoupling capacitor along to get the
maximum gain on the first stage.
Q2 is supplied through a printed microstrip line that
contributes also to the interstage matching in order to provide
optimum drive to the final stage.
The line length for Q1 and Q2 is small , so replacing it with
a discrete inductor is not practical.
Q3 drain is fed via a printed line that must handle the high
supply current of that stage (2.0 Amp peak) without
significant voltage drop. This line can be buried in an inner
layer to save PCB space or be a discrete RF choke.
Output matching is accomplished with a two stages
low–pass network. Easy implementation is achieved with
shunt capacitors mounted along a 2.0 mm 30 Ω microstrip
transmission line. Value and position are chosen to reach a
load line of 5.5 Ω while conjugating the device output
parasitics. The network must also properly terminate the
second and third harmonic to optimize efficiency and reduce
harmonic level. Use of high Q capacitor for the first output
matching capactor circuit is recommended in order to get the
best Output Power and Efficiency performance.
NOTE: The choice of output matching capacitors type and
supplier will affect H2 and H3 level and efficiency, because
of series resonant frequency.
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APPLICATIONS INFORMATION
Biasing Considerations
The internally generated negative voltage is clamped by
an external Zener diode in order to eliminate variation linked
to Input power or Buffer supply. This negative voltage is used
by three independent bias circuits to set the proper quiescent
current of all stages. Each bias circuitry is equivalent to a
current source sinking its value from the bias pin. When the
bias pins are set to 3.0 V, nominal quiescent current and
operating point of each RF stage are selected.
Q1 and Buffer share the Bias1 (0.25 mA) while Q2 and Q3
have dedicated Bias2 (0.25 mA) and Bias3 (0.5 mA)
respectively. It is also possible to reference those bias pins to
Gnd by changing series resistors R1, R2, R3 (Figure 1) that
drops the 3.0 V.
If those pins are left opened, the corresponding stages are
pinched–off. Thus the bias pins can be used as a mean to
select the MRFIC1819 or the MRFIC0919 in a dual band
configuration. The MRFIC0919 is the partner device to the
MRFIC1819 and is designed for GSM900 applications.
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Freescale Semiconductor,
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MRFIC1819
Pin
Symbol
Description
1
VP
2
VD3
3
RF Out
RF output
4
RF Out
RF output
5
RF Out
RF output
6
Bias3
Third stage bias
7
Bias2
Second stage bias
8
Bias1
Buffer and first stage bias
9
VSS
Negative voltage output
10
VSC
Negative voltage check
Positive voltage output
Third stage drain supply
11
VD2
Second stage drain supply
12
VD1
First stage drain supply
13
RF In
RF input
14
In Buf
Buffer RF input
15
VD0
First buffer stage drain supply
16
VDB
Buffer stage drain supply
Control Considerations
MRFIC01819 application uses the drain control technique
developed for our previous range of GaAs IPAs (refer to
application note AN1599). This method relies on the fact that
for an RF amplifier operating in saturation mode, the RF
output power is proportional to the square of the Amplifier
drain voltage: Pout(Watt)=k*VD(Volt)*VD(Volt).
In the proposed application circuit (see Figure 2), a PMOS
FET is used to switch the IPA drain and vary the drain supply
voltage from 0 to battery voltage. As the PMOS FET has a
non linear behavior, an OpAmp is included in the application.
This OpAmp is linearizing the PMOS by sensing its drain
output and gives a true linear relationship between the
Control voltage and the RF output voltage.
The obtained power control transfer function is so linear
and repeatable than it can be used to predict the output
power within a dynamic range of 25 to 30 dB over frequency
and temperature. This so called “open–loop” arrangement
eliminates the need for coupler and detector required for the
classical but complex closed–loop control and consequently
reduces the Insertion Loss from Power Amplifier to the
Antenna.
The block diagram (Figure 14) shows the principle of
operation as implemented in the application circuit of
Figure 2. The OpAmp is connected as an inverter to
compensate the negative gain of the PMOS switch.
VSC is an open drain internal FET switch which is biased
through the negative voltage. Consequently, this pin is high
impedance when negative voltage is okay and low
impedance (about 40 Ω) when negative voltage is missing.
Operation Procedure
The MRFIC1819 is a standard MESFET GaAs Power
Amplifier, presence of a negative voltage to bias the RF
line–up is essential in order to avoid any damage to the parts.
Due to the fact that the negative voltage is generated through
rectification of the RF input signal, a minimum input power
level is needed for correct operation of the demoboard. The
following procedure will guaranty safe operation for doing the
RF measurements.
Note: make sure that Bias1 (Pin 8 of demoboard Figure 3)
is connected 3.0 V or will have equivalent potential for
nominal biasing of Buffer stage.
1. Apply RF input power (RF In) > 6.0 dBm.
2. Apply VDB = 3.0 to 5.0 V.
3. Check that VSS reaches approximatively –5.1 V (settling of
the negative voltage) (Pin 9).
4. Apply VD1,2&3 = 3.0 to 5.5 V.
5. Measure RF output power and relevant parameters.
Proceed in the reverse order to switch off the Power
Amplifier.
For linear operation, an external negative voltage will have
to be supplied to the VSS pin to maintain initial quiescent
operating conditions of the FET amplifiers since the RF input
will not provide sufficient voltage to operate the negative
voltage generator. When using an external negative voltage
supply, an input to the buffer (Pin 14) and supply voltages to
VDB (Pin 16) and VD0 (Pin 15), would no longer be required.
Figure 14. Drain Control through
PMOS Switch
Vbat
PMOS
Vramp
Vdrain
Gain Set
RF In
RF Out
PA
NOTE:
The positive voltage generated by the Buffer stage can
be used to supply the OpAmp and make it possible to
drive a NMOS switch as a voltage follower. Doing so,
the main advantage is to have a lower Rdson switch
and better intrinsic linearity.
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Table 2. Pin Function Description
In Figure 15, the plot illustrates the “open–loop”
performance regarding temperature stability. The measured
datas are diplayed in a log–log scale in order to have a good
representation of both the dynamic and the linearity of
control. The variation of Pout accross the frequency band are
also very small (less than 1.0 dB ripple) and are kept to that
small amount when controlling Pout through the Drain
voltage.
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9
Freescale Semiconductor,
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MRFIC1819
Pout , OUTPUT POWER (dBm)
40
35
TA = –40°C
30
25°C
25
85°C
20
15
10
5.0
Pin = 6.0 dBm
f = 1750 MHz
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0
–5.0
–20
–15
–10
–5.0
0
5.0
10
15
VDD (dBv)
Figure 16. Timing Guide
3.0 V
OpAmp
shdn
0V
3.0 V
20 µs
Tx En
(&RF In)
0V
2.0 V
Vramp
0V
2.0 µs
Burst mode
Use Figure 16 as a guide line to perform burst mode
measurements with the complete application circuit of
Figure 2. Notice that the VSC pin is connected to Vramp
(through a resistor) and acts as a pull down when negative
voltage is missing so that drain voltage is not applied to the
RF line–up.
– Bursting the OpAmp with its Pin 8 (shdn) is not mandatory
during a call as the OpAmp current consumption is very small
(1.0 to 2mA). This pin is mainly used for the idle mode of the
radio. In any case, the wake–up time of the OpAmp is very
short.
10
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Figure 15. Temperature Stability of the Open
Loop Control
– Vramp can be applied soon after Tx EN since the internal
negative voltage generator settles in less than 2.0 µs.
– Tx EN signal can be used to switch the input power (using
a driver or attenuator) in order to provide higher isolation for
on/off burst dynamic.
References (Motorola application notes)
AN1599 – Power Control with the MRFIC0913 GaAs
Integrated Power Amplifier and MC33169 Support IC.
AN1602 – 3.6 V and 4.8 V GSM/DCS1800 Dual Band PA
Application with DECT capability Using Standard Motorola
RFIC’s.
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Freescale Semiconductor,
Inc.
MRFIC1819
OUTLINE DIMENSIONS
16X
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2X
E/2
NOTES:
1 DIMENSIONS ARE IN MILLIMETERS.
2 INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3 DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 PER
SIDE.
4 DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE.
5 DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSIONS D AND E1 ARE TO BE DETERMINED
AT DATUM PLANE H.
b REF
0.10
0.20 C B A
C B
M
S
A
S
9
16
P1 E1
E
EXPOSED THERMAL
PAD (BOTTOM SURFACE)
8
1
PIN 1
IDENTIFICATION
0.20 C B A
B
P
D
A
0.10 C
GAUGE PLANE
A
R
e
c
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PLASTIC PACKAGE
CASE 948L–01
(TSSOP–16EP)
ISSUE O
H
DETAIL E
PARTING
LINE
A1
N
0.25
c1
c
N
L
DETAIL E
q
b
b1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
DIM
A
A1
b
b1
c
c1
D
E
E1
e
L
P
P1
R
q
MILLIMETERS
MIN
MAX
–––
1.20
0.00
0.10
0.19
0.30
0.19
0.25
0.09
0.20
0.09
0.16
4.90
5.10
6.40 BSC
4.30
4.50
0.65 BSC
0.50
0.75
–––
3.90
–––
3.00
0.18
0.28
0_
8_
SECTION N–N
MOTOROLA WIRELESS SEMICONDUCTOR
For More Information On This Product,
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11
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
Technical Information Center: 1–800–521–6274
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1,
Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
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Inc.
MRFIC1819
ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
852–26668334
HOME PAGE: http://www.motorola.com/semiconductors/
12
◊
MRFIC1819/D
MOTOROLA WIRELESS SEMICONDUCTOR
For More Information On This Product,
Go to: www.freescale.comSOLUTIONS – RF AND IF DEVICE DATA
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