Compal Confidential - ky thuat phan cung
A
B
C
D
E
Model Name : Z5W1M
File Name : LA-B511P
1
1
Compal Confidential
2
2
EA52_BM UMA M/B Schematics Document
Intel Bay Trail M
2014-03-13
REV:1.0
3
3
4
4
PCB@
DAX PCB 12R LA-B211P REV0 M/B
Part Number
DA60016I000
Description
PCB 12R LA-B511P REV0 M/B
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Page
Rev
0.3
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
1
of
39
A
B
C
D
E
Memory BUS
One Channel
204pin DDR3L-SO-DIMM X1
P.13
1.35V DDR3L 1066/1333
Max speed of DDR3L to 1333MT/s for M sku. -- EDS
1
1
port 0
port 1
port 1
Touch Panel
Conn.
USB 3.0 Conn
P.21
LVDS-Translator
RTD2132N P.14
EDP
P.16
P.15
CMOS Camera
DDI x2
HDMI Conn.
LCD Conn.
eDP/LVDS
P.15
P.15
LVDS
USB3.0 x1
port 0
VALLEYVIEW-M
PCIe 2.0 x4
2
port 0
port 2
port 3
USB2.0 x4
USB HUB
GL850G P.21
port 1
SOC
LAN(GbE)
port 1
2
RTL8111GUS
P.17
WLAN
MINI CARD
RJ45 conn.
HUB port1
FCBGA 1170 Pin
P.18
P.17
SATA II x2
port 0
HUB port2
HD Audio
port 1
SPI
HDA Codec
USB 2.0 Conn
P.21
ALC283
P.20
3
USB 2.0 Conn
P.19
SPI ROM
1.8V (8MB)
EC
ENE KB9022
SATA HDD Conn.
HUB port4
Card Reader
RTS5170
SD only
P.20
BT
MINI CARD
page 05~12
LPC BUS
SATA ODD Conn.
HUB port3
P.08
3
P.22
P.20
Int. Analog MIC
P.19
Universal Jack
Sub Board
P.19
Int. Speaker
P.19
Touch Pad
Int.KBD
P.23
P.23
LS-B471P
RTC CKT.
Card Reader
TPM
P.08
RTS5170
2 in 1 (SD)
NPCT650
P.18
DC/DC Interface CKT.
USB 2.0
conn x1
P.24
4
Power Circuit DC/DC
P.25~P.35
4
USB port 2
LED/Power On/Off
P.23
P.21
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
2
of
39
A
B
C
Voltage Rails
Power Plane
1
2
Description
S0
S3
S4/S5
VIN
19V Adapter power supply
ON
ON
ON
BATT+
12V Battery power supply
ON
ON
ON
B+
AC or battery power rail for power circuit. (19V/12V)
ON
ON
ON
+RTCVCC
RTC Battery Power
ON
ON
ON
+1.0VALW
+1.0v Always power rail
ON
ON
ON
+1.8VALW
+1.8v Always power rail
ON
ON
ON
+3VALW
+3.3v Always power rail
ON
ON
ON
+5VALW
+5.0v Always power rail
ON
ON
ON
+1.35V
+1.35V power rail for DDR3L
ON
ON
OFF
+SOC_VCC
Core voltage for SOC
ON
OFF
OFF
+SOC_VNN
GFX voltage for SOC
ON
OFF
OFF
+0.675VS
+0.675V power rail for DDR3L Terminator
ON
OFF
OFF
+1.0VS
+1.0v system power rail
ON
OFF
OFF
+1.05VS
+1.05v system power rail
ON
OFF
OFF
+1.35VS
+1.35v system power rail
ON
OFF
OFF
+1.5VS
+1.5v system power rail
ON
OFF
OFF
+1.8VS
+1.8v system power rail
ON
OFF
OFF
+3VS
+3.3v system power rail
ON
OFF
OFF
+5VS
+5.0v system power rail
ON
OFF
OFF
3
BOM Option Table
Item
BOM Structure
Unpop
@
Connector
CONN@
EMC requirement
EMC@
EMC requirement unpop
@EMC@
IOAC support
AC@
Choose Analog MIC pop
AMIC@
Backlight Keyboard
BL@
EDP panel select
EDP@
LVDS panel select
LVDS@
Power Switch on board
DBG@
Jump for transfer power
JP@
E
Board ID / SKU ID Table for AD channel
Vcc
Ra/Rc/Re
Board ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
12K +/- 5%
15K +/- 5%
20K +/- 5%
27K +/- 5%
33K +/- 5%
43K +/- 5%
56K +/- 5%
75K +/- 5%
100K +/- 5%
130K +/- 5%
160K +/- 5%
200K +/- 5%
240K +/- 5%
1
V AD_BID min
0 V
0.347 V
0.423 V
0.541 V
0.691 V
0.807 V
0.978 V
1.169 V
1.398 V
1.634 V
1.849 V
2.015 V
2.185 V
2.316 V
V AD_BID typ
0 V
0.354 V
0.430 V
0.550 V
0.702 V
0.819 V
0.992 V
1.185 V
1.414 V
1.650 V
1.865 V
2.031 V
2.200 V
2.329 V
V AD_BID max
0 V
0.360 V
0.438 V
0.559 V
0.713 V
0.831 V
1.006 V
1.200 V
1.430 V
1.667 V
1.881 V
2.046 V
2.215 V
2.343 V
BOARD ID Table
Board ID
0
1
2
3
4
5
6
PCB Revision
EVT
DVT
PVT
Pre-MP & MP
2
43 level BOM table
43 Level
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
D
Description
BOM Structure
4319TDBOL01
SMT MB AB511 Z5W1M UMA 2.17G
N3520@/EMC@/AMIC@/EDP@/DBG@/TPM@/PCB@/TS@
4319TDBOL02
SMT MB AB511 Z5W1M UMA 1.86G
N2920@/EMC@/AMIC@/LVDS@/DBG@/TPM@/PCB@/TS@
4319TDBOL03
SMT MB AB511 Z5W1M UMA 1.86G EPD HDMI
N2920@/EMC@/AMIC@/EDP@/DBG@/TPM@/PCB@/TS@
4319TDBOL04
4319TDBOL05
SMT MB AB511 Z5W1M UMA 2.17G LVDS HDMI
N3520@/EMC@/AMIC@/LVDS@/DBG@/TPM@/PCB@/TS@
SMT MB AB511 Z5W1M UMA 2.13G EPD HDMI
N2820@/EMC@/AMIC@/EDP@/DBG@/TPM@/PCB@/TS@
4319TDBOL06
SMT MB AB511 Z5W1M UMA 2.13G LVDS HDMI
N2820@/EMC@/AMIC@/LVDS@/DBG@/TPM@/PCB@/TS@
435MNVBOL01
SMT IO/B SB471 Z5W1M
EMC@
BOM Option Table
Item
CPU for N2920 pop
CPU for N3520 pop
TPM support
No supoort TPM
PCB PN
CLEAN CMOS JUMP
Touch Screen function
EDP + Touch Screen
3
BOM Structure
N2920@
N3520@
TPM@
NTPM@
PCB@
SP@
TS@
ETS@
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
3
of
39
A
B
C
D
2.2K
2.2K
1
BG25
SOC_I2C2_DATA
BJ25
SOC_I2C2_CLK
E
4.7K
+1.8VS
4.7K
+3V_TP
1
I2C2_SDA_TP
DMN63D8LDW
Touch Pad
I2C2_SCL_TP
Dual channel NMOS
2.2K
2.2K
SOC
BH28
SOC_I2C5_DATA
BG28
SOC_I2C5_CLK
2.2K
+1.8VS
2.2K
+5VS_TS
I2C5_SDA_PNL
DMN63D8LDW
I2C5_SCL_PNL
Touch Panel
Dual channel NMOS
2.2K
2.2K
2
BH10
PCU_SMB_CLK
BG12
PCU_SMB_DATA
+1.8VS
2
DMN63D8LDW
Dual channel NMOS
2.2K
2.2K
77
EC_SMB_CK1
78
EC_SMB_DA1
SCL1
SDA1
+3VALW_EC
100 ohm
100 ohm
7
6
BATTERY
CONN
2.2K
2.2K
79
SCL2
KBC
80
SDA2
+3VS
EC_SMB_CK2
EC_SMB_DA2
3
3
200
202
KB9022
DIMMA
SMBUS Address [A0h]
30
32
WLAN
SMBUS Address [TBD]
4.7K
4.7K
85
SCL3
86
SDA3
+3VS_TL
9
EC_SMB_CK3
10
EC_SMB_DA3
DP-LVDS
SMBUS Address [TBD]
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SMB/I2C
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
4
of
39
A
B
C
D
E
1
1
12000mA
VR_ON
ADAPTER
ISL95833HRTZ-T
(PU801)
14000mA
SPOK
SY8208DQNC
(PU601)
325mA
SYSON
RT8207MZQW
(PU501)
5250mA
+SOC_VNN
+SOC_VCC
+1.0VALWP
+1.35VP
2750mA
SUSP
ME4856-G
(U25)
SUSP#
TPS22966DPUR
(U26)
+1.0VS
420mA
+1.35VS
+0.675VSP
2
2
BATTERY
B+
EC_ON
SY8208BQNC
(PU401)
4850mA
+3VALWP
CHARGER
SUSP#
SY8003DFC_DFN8
(PU701)
458mA
SUSP#
APL5930KAI-TRG
(PU602)
1000mA
SPOK
APL5930KAI-TRG
(PU702)
110mA
SUSP#
TPS22966DPUR
(U24)
LAN_PWR_EN
+1.5VSP
+1.05VSP
+1.8VALWP
+3V_LAN
10mA
TPS22966DPUR
(U26)
1000mA
+3VS
G5243AT11U
(U67)
SUSP#
ENVDD
+1.8VS
+3VS_WLAN
G5243AT11U
(U8)
+LCDVDD
3
3
EC_ON
SY8208BQNC
(PU402)
10050mA
SUSP#
+5VALWP
TPS22966DPUR
(U24)
1000mA
1050mA
+5VS
+VDDA
1500mA
+5VS_HDD
1500mA
+5VS_ODD
500mA
+HDMI_5V_OUT
USB_PWR_EN#
SY6288D10CAC
(U17)
1500mA
+USB3_VCCA
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
Power Rail
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
5
of
39
5
4
3
DDR_A_D[0..63]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
2
<14>
<14>
<14>
USOC1A
<14>
DDR_A_MA[0..15]
D
<14>
C
DDR_A_DM[0..7]
<14>
<14>
<14>
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
<14>
<14>
<14>
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
<14>
DDR_A_CS0#
<14>
DDR_A_CS2#
<14>
DDR_A_CKE0
<14>
DDR_A_CKE2
<14>
DDR_A_ODT0
<14>
DDR_A_ODT2
<14>
<14>
DDR_A_CLK0
DDR_A_CLK0#
<14>
<14>
DDR_A_CLK2
DDR_A_CLK2#
<14>
DDR_A_RST#
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
2 R1
2 R2
DRAM0_DQ_0
DRAM0_DQ_1
DRAM0_DQ_2
DRAM0_DQ_3
DRAM0_DQ_4
DRAM0_DQ_5
DRAM0_DQ_6
DRAM0_DQ_7
DRAM0_DQ_8
DRAM0_DQ_9
DRAM0_DQ_10
DRAM0_DQ_11
DRAM0_DQ_12
DRAM0_DQ_13
DRAM0_DQ_14
DRAM0_DQ_15
DRAM0_DQ_16
DRAM0_DQ_17
DRAM0_DQ_18
DRAM0_DQ_19
DRAM0_DQ_20
DRAM0_DQ_21
DRAM0_DQ_22
DRAM0_DQ_23
DRAM0_DQ_24
DRAM0_DQ_25
DRAM0_DQ_26
DRAM0_DQ_27
DRAM0_DQ_28
DRAM0_DQ_29
DRAM0_DQ_30
DRAM0_DQ_31
DRAM0_DQ_32
DRAM0_DQ_33
DRAM0_DQ_34
DRAM0_DQ_35
DRAM0_DQ_36
DRAM0_DQ_37
DRAM0_DQ_38
DRAM0_DQ_39
DRAM0_DQ_40
DRAM0_DQ_41
DRAM0_DQ_42
DRAM0_DQ_43
DRAM0_DQ_44
DRAM0_DQ_45
DRAM0_DQ_46
DRAM0_DQ_47
DRAM0_DQ_48
DRAM0_DQ_49
DRAM0_DQ_50
DRAM0_DQ_51
DRAM0_DQ_52
DRAM0_DQ_53
DRAM0_DQ_54
DRAM0_DQ_55
DRAM0_DQ_56
DRAM0_DQ_57
DRAM0_DQ_58
DRAM0_DQ_59
DRAM0_DQ_60
DRAM0_DQ_61
DRAM0_DQ_62
DRAM0_DQ_63
DRAM0_DM_0
DRAM0_DM_1
DRAM0_DM_2
DRAM0_DM_3
DRAM0_DM_4
DRAM0_DM_5
DRAM0_DM_6
DRAM0_DM_7
M45
M44
H51
DRAM0_RAS#
DRAM0_CAS#
DRAM0_WE#
K47
K44
D52
DRAM0_BS_0
DRAM0_BS_1
DRAM0_BS_2
P44
DRAM0_CS_0#
P45
DRAM0_CS_2#
C47
D48
F44
E46
DRAM0_CKE_0
RESERVED_D48
DRAM0_CKE_2
RESERVED_E46
T41
DRAM0_ODT_0
P42
DRAM0_ODT_2
M50
M48
DRAM0_CKP_0
DRAM0_CKN_0
P50
P48
DRAM0_CKP_2
DRAM0_CKN_2
P41
DRAM0_DRAMRST#
AF44
DDR_TERMN0
DDR_TERMN1
USOC1B
DRAM0_MA_0
DRAM0_MA_1
DRAM0_MA_2
DRAM0_MA_3
DRAM0_MA_4
DRAM0_MA_5
DRAM0_MA_6
DRAM0_MA_7
DRAM0_MA_8
DRAM0_MA_9
DRAM0_MA_10
DRAM0_MA_11
DRAM0_MA_12
DRAM0_MA_13
DRAM0_MA_14
DRAM0_MA_15
DDR_A_DM0 G36
DDR_A_DM1 B36
DDR_A_DM2 F38
DDR_A_DM3 B42
DDR_A_DM4 P51
DDR_A_DM5 V42
DDR_A_DM6 Y50
DDR_A_DM7 Y52
+DDR_SOC_VREF
100K_0402_5% 1
100K_0402_5% 1
K45
H47
L41
H44
H50
G53
H49
D50
G52
E52
K48
E51
F47
J51
B49
B50
DRAM_VREF
AF42
AH42
0.675V
ICLK_DRAM_TERMN_AF42
ICLK_DRAM_TERMN_AH42
DRAM0_DQSP_0
DRAM0_DQSN_0
DRAM0_DQSP_1
DRAM0_DQSN_1
DRAM0_DQSP_2
DRAM0_DQSN_2
DRAM0_DQSP_3
DRAM0_DQSN_3
DRAM0_DQSP_4
DRAM0_DQSN_4
DRAM0_DQSP_5
DRAM0_DQSN_5
DRAM0_DQSP_6
DRAM0_DQSN_6
DRAM0_DQSP_7
DRAM0_DQSN_7
B
<30>
<9>
AD42
AB42
DDR_PWROK
DDR_CORE_PWROK
23.2_0402_1% 1
29.4_0402_1% 1
162_0402_1% 1
2 R3
2 R4
2 R5
DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2
Follow CRB v2.0
DRAM_VDD_S4_PWROK
DRAM_CORE_PWROK
AD44
AF45
AD45
DRAM_RCOMP_0
DRAM_RCOMP_1
DRAM_RCOMP_2
AF40
AF41
AD40
AD41
2
1 DDR_CORE_PWROK
EMC@ C1
0.01U_0402_16V7K
1
RESERVED_AF40
RESERVED_AF41
RESERVED_AD40
RESERVED_AD41
M36
J36
P40
M40
P36
N36
K40
K42
B32
C32
C36
A37
C33
A33
C37
B38
F36
G38
F42
J42
G40
C38
G44
D42
A41
C41
A45
B46
C40
B40
B48
B47
K52
K51
T52
T51
L51
L53
R51
R53
T47
T45
Y40
V41
T48
T50
Y42
AB40
V45
V47
AD48
AD50
V48
V50
AB44
Y45
V52
W51
AC53
AC51
W53
Y51
AD52
AD51
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
J38
K38
C35
B34
D40
F40
B44
C43
N53
M52
T42
T44
Y47
Y48
AB52
AA51
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
AY45
BB47
AW41
BB44
BB50
BC53
BB49
BF50
BC52
BE52
AY48
BE51
BD47
BA51
BH49
BH50
BD38
BH36
BC36
BH42
AT51
AM42
AK50
AK52
AV45
AV44
BB51
AY47
AY44
BF52
AT44
AT45
BG47
BE46
BD44
BF48
AP41
AT42
AV50
AV48
AT50
AT48
AT41
DRAM1_MA_0
DRAM1_MA_1
DRAM1_MA_2
DRAM1_MA_3
DRAM1_MA_4
DRAM1_MA_5
DRAM1_MA_6
DRAM1_MA_7
DRAM1_MA_8
DRAM1_MA_9
DRAM1_MA_10
DRAM1_MA_11
DRAM1_MA_12
DRAM1_MA_13
DRAM1_MA_14
DRAM1_MA_15
DRAM1_DQ_0
DRAM1_DQ_1
DRAM1_DQ_2
DRAM1_DQ_3
DRAM1_DQ_4
DRAM1_DQ_5
DRAM1_DQ_6
DRAM1_DQ_7
DRAM1_DQ_8
DRAM1_DQ_9
DRAM1_DQ_10
DRAM1_DQ_11
DRAM1_DQ_12
DRAM1_DQ_13
DRAM1_DQ_14
DRAM1_DQ_15
DRAM1_DQ_16
DRAM1_DQ_17
DRAM1_DQ_18
DRAM1_DQ_19
DRAM1_DQ_20
DRAM1_DQ_21
DRAM1_DQ_22
DRAM1_DQ_23
DRAM1_DQ_24
DRAM1_DQ_25
DRAM1_DQ_26
DRAM1_DQ_27
DRAM1_DQ_28
DRAM1_DQ_29
DRAM1_DQ_30
DRAM1_DQ_31
DRAM1_DQ_32
DRAM1_DQ_33
DRAM1_DQ_34
DRAM1_DQ_35
DRAM1_DQ_36
DRAM1_DQ_37
DRAM1_DQ_38
DRAM1_DQ_39
DRAM1_DQ_40
DRAM1_DQ_41
DRAM1_DQ_42
DRAM1_DQ_43
DRAM1_DQ_44
DRAM1_DQ_45
DRAM1_DQ_46
DRAM1_DQ_47
DRAM1_DQ_48
DRAM1_DQ_49
DRAM1_DQ_50
DRAM1_DQ_51
DRAM1_DQ_52
DRAM1_DQ_53
DRAM1_DQ_54
DRAM1_DQ_55
DRAM1_DQ_56
DRAM1_DQ_57
DRAM1_DQ_58
DRAM1_DQ_59
DRAM1_DQ_60
DRAM1_DQ_61
DRAM1_DQ_62
DRAM1_DQ_63
DRAM1_DM_0
DRAM1_DM_1
DRAM1_DM_2
DRAM1_DM_3
DRAM1_DM_4
DRAM1_DM_5
DRAM1_DM_6
DRAM1_DM_7
DRAM1_RAS#
DRAM1_CAS#
DRAM1_WE#
DRAM1_BS_0
DRAM1_BS_1
DRAM1_BS_2
DRAM1_CS_0#
DRAM1_CS_2#
DRAM1_CKE_0
RESERVED_BE46
DRAM1_CKE_2
RESERVED_BF48
DRAM1_ODT_0
DRAM1_ODT_2
DRAM1_CKP_0
DRAM1_CKN_0
DRAM1_CKP_2
DRAM1_CKN_2
DRAM1_DRAMRST#
DRAM1_DQSP_0
DRAM1_DQSN_0
DRAM1_DQSP_1
DRAM1_DQSN_1
DRAM1_DQSP_2
DRAM1_DQSN_2
DRAM1_DQSP_3
DRAM1_DQSN_3
DRAM1_DQSP_4
DRAM1_DQSN_4
DRAM1_DQSP_5
DRAM1_DQSN_5
DRAM1_DQSP_6
DRAM1_DQSN_6
DRAM1_DQSP_7
DRAM1_DQSN_7
1 OF 13
BG38
BC40
BA42
BD42
BC38
BD36
BF42
BC44
BH32
BG32
BG36
BJ37
BG33
BJ33
BG37
BH38
AU36
AT36
AV40
AT40
BA36
AV36
AY42
AY40
BJ41
BG41
BJ45
BH46
BG40
BH40
BH48
BH47
AY52
AY51
AP52
AP51
AW51
AW53
AR51
AR53
AP47
AP45
AK40
AM41
AP48
AP50
AK42
AH40
AM45
AM47
AF48
AF50
AM48
AM50
AH44
AK45
AM52
AL51
AG53
AG51
AL53
AK51
AF52
AF51
D
C
BF40
BD40
BG35
BH34
BA38
AY38
BH44
BG43
AU53
AV52
AP42
AP44
AK47
AK48
AH52
AJ51
B
2 OF 13
FH8065301546401_FCBGA131170
@
FH8065301546401_FCBGA131170
@
Close To SOC Pin
USOC1
N3530@
+1.35V
A
USOC1
N2830@
USOC1
N2930@
+DDR_SOC_VREF
1
1
2
R6
4.7K_0402_1%
1
2
R7
4.7K_0402_1%
2
S IC FH8065301728500 QG9T C0 2.17G FCBGA
Part Number = SA00007QQ70
S IC FH8065301729601 QG9V C0 2.17G ABO!
Part Number = SA00007QR30
A
S IC FH8065301729501 QG9U C0 1.83G FCBGA
Part Number = SA00007RV70
C2
.1U_0402_16V7K
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
VLV-M SOC Memory DDR3L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
6
of
39
5
4
3
2
1
D
D
USOC1C
AL3
AL1
D27
<17>
HDMI_HPD#
<17>
<17>
HDMI_DDCDATA
HDMI_DDCCLK
C26
C28
B28
C27
B26
1 R9
2 DDI0_RCOMPP
402_0402_1% DDI0_RCOMPN
C
Follow CRB v2.0 0ohm till to GND
AK12
AK13
AM14
AM13
AM3
AM2
DDI0_TXP_0
DDI0_TXN_0
DDI0_TXP_1
DDI0_TXN_1
DDI0_TXP_2
DDI0_TXN_2
DDI0_TXP_3
DDI0_TXN_3
1.0V
1.0V
DDI0_AUXP
DDI0_AUXN
DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3
1.0V
1.0V
DDI1_AUXP
DDI1_AUXN
DDI1_HPD
1
+1.8VS
@
R10
10K_0402_5%
1
2
B
@
T1
GPIO_NC12
EDP_AUXP <15,16>
EDP_AUXN <15,16>
K30
1.8V
1.8V
1.8V
1.8V
1.8V DDI1_DDCDATA
1.8V DDI1_DDCCLK
P30 DDI1_ENABLE R8
G30
1.8V
1.8V
1.8V
N30 DDI1_ENVDD
J30 DDI1_ENBKL
M30 DDI1_PWM
DDI0_VDDEN
DDI0_BKLTEN
DDI0_BKLTCTL
DDI1_VDDEN
DDI1_BKLTEN
DDI1_BKLTCTL
VSS_AH3
VSS_AH2
DDI0_RCOMP_P
DDI0_RCOMP_N
RESERVED_AM14
RESERVED_AM13
VSS_AM3
VSS_AM2
RESERVED_AH14
RESERVED_AH13
RESERVED_AF14
RESERVED_AF13
RESERVED_T2
RESERVED_T3
RESERVED_AB3
RESERVED_AB2
RESERVED_Y3
RESERVED_Y2
RESERVED_W3
RESERVED_W1
RESERVED_V2
RESERVED_V3
RESERVED_R3
RESERVED_R1
RESERVED_AD6
RESERVED_AD4
RESERVED_AB9
RESERVED_AB7
RESERVED_Y4
RESERVED_Y6
RESERVED_V4
RESERVED_V6
GPIO_S0_NC_13
GPIO_S0_NC14
RESERVED_AB14
GPIO_S0_NC_12
RESERVED_C30
3.3V
3.3V
VGA_HSYNC
VGA_VSYNC
3.3V
3.3V
VGA_DDCCLK
VGA_DDCDATA
RESERVED_T7
RESERVED_T9
RESERVED_AB13
RESERVED_AB12
RESERVED_Y12
RESERVED_Y13
RESERVED_V10
RESERVED_V9
RESERVED_T12
RESERVED_T10
RESERVED_V14
RESERVED_V13
RESERVED_T14
RESERVED_T13
RESERVED_T6
RESERVED_T4
RESERVED_P14
GPIO_S0_NC_15
GPIO_S0_NC_16
GPIO_S0_NC_17
GPIO_S0_NC_18
GPIO_S0_NC_19
GPIO_S0_NC_20
GPIO_S0_NC_21
GPIO_S0_NC_22
GPIO_S0_NC_23
GPIO_S0_NC_24
GPIO_S0_NC_25
GPIO_S0_NC_26
Follow CRB v2.0
3 OF 10
FH8065301546401_FCBGA131170
EDP_HPD#
1
<16>
2 2.2K_0402_5%
+1.8VS
Follow CRB v2.0 0ohm till to GND
AH14
AH13
AF14
AF13
C
BA3
AY2
BA1
AW1
AY3
BD2
BF2
BC1
BC2
T7
T9
AB13
AB12
Y12
Y13
V10
V9
T12
T10
V14
V13
T14
T13
T6
T4
P14
F34
M32
D28
J28
K34
D34
F32
F28
K28
J34
N32
D32
B
eDP
+3VS
1
DDI1_ENBKL
0_0402_5%
2
R13
@
ENBKL
<23>
Modify R02
+1.8VS
@
5
From check list:
GPIO_S0_NC[13] Multiplexed with Hardware
AH3
AH2
<15,16>
<15,16>
<16>
<16>
eDP Panel
AK3
AK2
DDI0_DDCDATA
DDI0_DDCCLK
2
@
T2
R11
10K_0402_1%
GPIO_NC13
GPIO_NC14
EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1
DDI0_HPD
VGA_RED
VGA_BLUE
VGA_GREEN
VGA_IREF
VGA_IRTN
T2
T3
AB3
AB2
Y3
Y2
W3
W1
V2
V3
R3
R1
AD6
AD4
AB9
AB7
Y4
Y6
V4
V6
A29
C29
AB14
B30
C30
AG3
AG1
AF3
AF2
AD3
AD2
AC3
AC1
Straps Pin:MDSI_DDCDATA
1
Y
A
4
ENVDD
<16>
RP1
5
P
Y
A
4
INVT_PWM_SOC
2013/04/12
1
2
3
4
100K_0804_8P4R_5%
<15,16>
NL17SZ07DFT2G_SC70-5
SA00004BV00
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
DDI1_ENBKL 8
DDI1_ENVDD 7
6
DDI1_PWM
5
U3
NC
3
2
2
G
1
DDI1_PWM
2
INVT_PWM_SOC 1
4.7K_0402_5%
R15
NL17SZ07DFT2G_SC70-5
SA00004BV00
+1.8VS
A
1
ENVDD
4.7K_0402_5%
R14
U2
NC
3
DDI1_ENVDD 2
P
HDMI
AV3
AV2
AT2
AT3
AR3
AR1
AP3
AP2
HDMI_TX2+
HDMI_TX2HDMI_TX1+
HDMI_TX1HDMI_TX0+
HDMI_TX0HDMI_CLK+
HDMI_CLK-
G
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
2014/04/12
Deciphered Date
Title
VLV-M SOC Display
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
7
of
39
A
5
4
3
2
1
D
D
USOC1D
HDD
ODD
<21>
<21>
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
<21>
<21>
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
<21>
<21>
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
<21>
<21>
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
BF6
BG7
AU16
AV16
BD10
BF10
AY16
BA16
Follow CRB V2.0 0ohm till to GND
<9>
SOC_SCI#
@ T3
Modify R02
C
SOC_SCI#
DEVSLP_SOC
BB10
BC10
BA12
AY14
AY12
1 R16
2 SATA_RCOMPP AU18
402_0402_1% SATA_RCOMPN AT18
AT22
AV20
AU22
AV22
AT20
AY24
AU26
AT26
AU20
AV26
BA24
AY18
BA18
AY20
BD20
BA20
BD18
BC18
AY26
AT28
BD26
AU28
BA26
BC24
AV28
BF22
BD22
B
BF26
SATA_TXP_0
SATA_TXN_0
PCIE_TXP_0
PCIE_TXN_0
SATA_RXP_0
SATA_RXN_0
PCIE_RXP_0
PCIE_RXN_0
SATA_TXP_1
SATA_TXN_1
PCIE_TXP_1
PCIE_TXN_1
SATA_RXP_1
SATA_RXN_1
PCIE_RXP_1
PCIE_RXN_1
VSS_BB10
VSS_BC10
PCIE_TXP_2
PCIE_TXN_2
SATA_GP0 / GPIO_S0_SC_0
SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1
SATA_LED# / GPIO_S0_SC_2
PCIE_RXP_2
PCIE_RXN_2
PCIE_TXP_3
PCIE_TXN_3
SATA_RCOMP_P
SATA_RCOMP_N
PCIE_RXP_3
PCIE_RXN_3
MMC1_CLK / GPIO_S0_SC_16
VSS_BB7
VSS_BB5
MMC1_D0 / GPIO_S0_SC_17
MMC1_D1 / GPIO_S0_SC_18
MMC1_D2 / GPIO_S0_SC_19
MMC1_D3 / GPIO_S0_SC_20
MMC1_D4 / GPIO_S0_SC_21
MMC1_D5 / GPIO_S0_SC_22
MMC1_D6 / GPIO_S0_SC_23
MMC1_D7 / GPIO_S0_SC_24
PCIE_CLKREQ_0# / GPIO_S0_SC_3
PCIE_CLKREQ_1# / GPIO_S0_SC_4
PCIE_CLKREQ_2# / GPIO_S0_SC_5
PCIE_CLKREQ_3# / GPIO_S0_SC_6
SD3_WP / GPIO_S0_SC_7
MMC1_CMD / GPIO_S0_SC_25
MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26
PCIE_RCOMP_P
PCIE_RCOMP_N
RESERVED_BB4
RESERVED_BB3
MMC1_RCOMP
SD2_CLK / GPIO_S0_SC_27
SD2_D0 / GPIO_S0_SC_28
SD2_D1 / GPIO_S0_SC_29
SD2_D2 / GPIO_S0_SC_30
SD2_D3_CD# / GPIO_S0_SC_31
SD2_CMD / GPIO_S0_SC_32
RESERVED_AV10
RESERVED_AV9
HDA_LPE_RCOMP
HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8
HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9
HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10
HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11
HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12
HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13
SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14
SD3_D0 / GPIO_S0_SC_34
HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15
SD3_D1 / GPIO_S0_SC_35
SD3_D2 / GPIO_S0_SC_36
LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62
SD3_D3 / GPIO_S0_SC_37
LPE_I2S2_FRM / GPIO_S0_SC_63
SD3_CD# / GPIO_S0_SC_38
LPE_I2S2_DATAIN / GPIO_S0_SC_64
SD3_CMD / GPIO_S0_SC_39
LPE_I2S2_DATAOUT / GPIO_S0_SC_65
SD3_1P8EN / GPIO_S0_SC_40
SD3_PWREN# / GPIO_S0_SC_41
RESERVED_P34
RESERVED_N34
SD3_RCOMP
RESERVED_AK9
RESERVED_AK7
4 OF 10
FH8065301546401_FCBGA131170
PROCHOT#
AY7 PCIE_PTX_DRX_P0
AY6 PCIE_PTX_DRX_N0
.1U_0402_16V7K 1
.1U_0402_16V7K 1
2 C5
2 C3
AT14 PCIE_PRX_DTX_P0
AT13 PCIE_PRX_DTX_N0
PCIE_PTX_C_DRX_P0 <18>
PCIE_PTX_C_DRX_N0 <18>
PCIE LAN
PCIE_PRX_DTX_P0 <18>
PCIE_PRX_DTX_N0 <18>
AV6 PCIE_PTX_DRX_P1
AV4 PCIE_PTX_DRX_N1
.1U_0402_16V7K 1
.1U_0402_16V7K 1
2 C4
2 C6
AT10 PCIE_PRX_DTX_P1
AT9 PCIE_PRX_DTX_N1
PCIE_PTX_C_DRX_P1 <19>
PCIE_PTX_C_DRX_N1 <19>
WLAN
PCIE_PRX_DTX_P1 <19>
PCIE_PRX_DTX_N1 <19>
AT7
AT6
AP12
AP10
AP6
AP4
C
+1.8VS
AP9
AP7
RP2
BB7
BB5
BG3
BD7
BG5
BE3
BD5
LAN_CLKREQ#
WLAN_CLKREQ#
PCIE_CLKREQ_2#
PCIE_CLKREQ_3#
AP14
AP13
PCIE_RCOMPP
PCIE_RCOMPN
1
2
3
4
LAN_CLKREQ#
PCIE_CLKREQ_2#
PCIE_CLKREQ_3#
WLAN_CLKREQ#
Follow CRB V2.0 0ohm till to GND
LAN_CLKREQ# <18>
WLAN_CLKREQ# <19>
8
7
6
5
10K_0804_8P4R_5%
RP3
8
7
6
5
HDA_SYNC
HDA_SDOUT
HDA_BIT_CLK
HDA_RST#
1 R17
2
402_0402_1%
BB4
BB3
1
2
3
4
HDA_SYNC_AUDIO
<20>
HDA_SDOUT_AUDIO <20>
HDA_BITCLK_AUDIO <20>
HDA_RST_AUDIO# <20>
33_0804_8P4R_5%
EMC@
AV10
AV9
HDA_RCOMP
BF20
BG22
BH20
BJ21
BG20
BG19
BG21
BH18
BG18
BF28
BA30
BD28
BC30
HDA_RCOMP
HDA_RST#
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0
T4
T5
T6
1
R18
2
1
HDA_BITCLK_AUDIOC7
49.9_0402_1%
2 22P_0402_50V8J
@EMC@
@
@
@
HDA_SDIN0
<20>
GPIO_S0_SC_65
Follow CRB v2.0
P34
N34
R20
73.2_0402_1%
1
2
AK9
AK7
C24
2
1
2
GPIO_S0_SC_63 R19
+1.8VS
1 10K_0402_5%
+1.0VS
H_PROCHOT#
Internal PD 2K
@
B
GPIO_S0_SC_63:
BIOS/EFI Boot Strap (BBS)
0 = LPC
1 = SPI
GPIO_S0_SC_63
<23>
GPIO_S0_SC_65:
Security Flash Descriptors
0 = Override
1 = Normal Operation
(Internal PU)
@EMC@
C8
10P_0402_50V8J
1
+1.8VS
EC programing :
"High"for Flash BIOS
1
2
R21
10K_0402_5%
GPIO_S0_SC_65
D
A
3
S
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
A
2
TXE_DBG <23>
G
Q1
MESS138W-G_SOT323-3
2014/04/12
Deciphered Date
Title
VLV-M SOC SATA/PCI-E/HDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
8
of
39
5
4
3
2
1
+3VS
1
1
AD10
AD12
C9
10P_0402_25V8J
2 4.02K_0402_1% ICLK_ICOMP
2 47.5_0402_1% ICLK_RCOMP
LAN
<18>
<18>
CLK_PCIE_LAN#
CLK_PCIE_LAN
WLAN
<19>
<19>
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
RESERVED_AD10
RESERVED_AD12
AF6
AF4
PCIE_CLKN_0
PCIE_CLKP_0
AF9
AF7
PCIE_CLKN_2
PCIE_CLKP_2
AM4
AM6
R03 modify
1
1
1
R27
R28
R29
@
@
2 51_0402_5% XDP_H_PRDY#
2 51_0402_5% XDP_H_TDO
2 200_0402_5% XDP_H_PREQ_BUF#
5
6
7
8
RESERVED_AM9
RESERVED_AM10
BH7
BH5
BH4
BH8
BH6
BJ9
RP5 @
4
3
2
1
PCIE_CLKN_3
PCIE_CLKP_3
AM9
AM10
For XDP use
XDP_H_TDI
XDP_H_TMS
XDP_H_TCK
XDP_H_TRST#
PMC_PLT_CLK_0 / GPIO_S0_SC_96
PMC_PLT_CLK_1 / GPIO_S0_SC_97
PMC_PLT_CLK_2 / GPIO_S0_SC_98
PMC_PLT_CLK_3 / GPIO_S0_SC_99
PMC_PLT_CLK_4 / GPIO_S0_SC_100
PMC_PLT_CLK_5 / GPIO_S0_SC_101
D14
XDP_H_TCK
G12
XDP_H_TRST#
F14
XDP_H_TMS
F12
XDP_H_TDI
G16
XDP_H_TDO
D18
XDP_H_PRDY#
XDP_H_PREQ_BUF# F16
AT34
51_0804_8P4R_5%
C
@ T10
SOC_SPI_MISO
SOC_SPI_MOSI
SOC_SPI_CLK
<16>
<24>
TS_INT_R#
PCH_TP_INT#
1
1
0_0402_5%
0_0402_5%
SOC_LID_OUT#
SOC_SMI#
ILB_RTC_X1
ILB_RTC_X2
ILB_RTC_EXTPAD
RTC_VCC_P22
SVID_ALERT#
SVID_DATA
SVID_CLK
SIO_PWM_0 / GPIO_S0_SC_94
SIO_PWM_1 / GPIO_S0_SC_95
GPIO_S5_8
GPIO_S5_9
GPIO_S5_10
N26
D26
G24
F18
F22
D22
J20
D20
F26
K26
J26
BG9
F20
J24
G18
1
2
P
3.3V
PLT_RST_BUF#
<18,19,21,23>
NL17SZ07DFT2G_SC70-5
SA00004BV00
3
<23,28>
PLT_RST_BUF#
PLT_RST Buffer
1
2
C10
@EMC@
0.01U_0402_16V7K
D
+1.8VALW
PMC_SUSCLK
@ 32.768k
T7
PMC_SLP_S4#
PMC_SLP_S3#
GPIO_S5_14
PMC_ACIN
PMC_PCIE_WAKE#
PMC_BATLOW#
PMC_PWRBTN#
PMC_RSTBTN#
PMC_PLTRST#
GPIO_S5_17
output
RP4
1
2
3
4
PMC_PCIE_WAKE#
PMC_BATLOW#
GPIO_S5_14
8
7
6
5
10K_0804_8P4R_5%
T8
@
T9
@
PMC_CORE_PWROK
C12
EMC@
1
2 0.01U_0402_16V7K
DDR_CORE_PWROK
C13
EMC@
1
2 0.01U_0402_16V7K
PMC_PLTRST#
C14
EMC@
1
2 .1U_0402_16V7K
C11 RTC_TEST#
C12 RTC_RST#
EC_RSMRST#
B10
B7
EC_RSMRST#
PMC_CORE_PWROK
C9
A9
B8
P22
ILB_RTC_X1
ILB_RTC_X2
ILB_RTC_EXTPAD
EC_RSMRST#
+RTCVCC
1
R30
<23>
2 100K_0402_5%
EMC@
1
2 .1U_0402_16V7K
C15
1
2
C16
.1U_0402_16V7K
B24 VR_SVID_ALERT#_SOC R32
A25 VR_SVID_DATA_SOC
R33
C25
1
1
+1.35VS
R31
73.2_0402_1%
2 20_0402_1%
2 16.9_0402_1%
+3VALW
VR_SVID_ALERT# <33>
VR_SVID_DATA <33>
VR_SVID_CLK <33>
<23>
AU32
AT32
K24
N24
M20
J18
M18
K18
K20
M22
M24
1
3.3V
2
PMC_CORE_PWROK
1
2
R35
10M_0402_5%
U6
1.35V
4
Y
A
C
R38
10K_0402_5%
NC
DDR_CORE_PWROK
<6>
NL17SZ07DFT2G_SC70-5
SA00004BV00
GPIO_RCOMP
SIO_SPI_CS# / GPIO_S0_SC_66
SIO_SPI_MISO / GPIO_S0_SC_67
SIO_SPI_MOSI / GPIO_S0_SC_68
SIO_SPI_CLK / GPIO_S0_SC_69
5 OF 13
RP6
1
PMC_SLP_S4# 2
3
SOC_KBRST#
SOC_LID_OUT# 4
32.768KHZ_12.5PF_Q13FC135000040
2
Y2 1
8
7
6
5
EC_SLP_S4#
EC_KBRST#
EC_LID_OUT#
EC_SLP_S4# <23>
EC_KBRST# <23>
EC_LID_OUT# <23>
0_0804_8P4R_5%
1
2
FH8065301546401_FCBGA131170
AV32
BA28
AY28
AY30
1
C17
18P_0402_50V8J
2
RP7
1
2
SOC_SMI#
3
SOC_SCI#
PMC_PWRBTN# 4
C18
18P_0402_50V8J
<8>
SOC_SCI#
Modify R03
8
7
6
5
EC_SMI#
EC_SCI#
PBTN_OUT#
EC_SMI# <23>
EC_SCI# <23>
PBTN_OUT# <23>
0_0804_8P4R_5%
R213
0_0402_5%
2
SOC_SERIRQ 1
NTPM@
NTPM@
2
PMC_SLP_S3# 1
R214
0_0402_5%
@
1
R37
49.9_0402_1%
ACIN
BF34
BD34
BD32
BF32
4
Y
A
ILB_RTC_X1
ILB_RTC_X2
GPIO_S5_22
GPIO_S5_23
GPIO_S5_24
GPIO_S5_25
GPIO_S5_26
GPIO_S5_27
GPIO_S5_28
GPIO_S5_29
GPIO_S5_30
2
GPIO_RCOMP
1 RB751V40_SC76-2
PMC_PLTRST# 2
+1.0VS
RTC domain
GPIO_S5_0
GPIO_S5_1 / PMC_WAKE_PCIE_1
GPIO_S5_2 / PMC_WAKE_PCIE_2
GPIO_S5_3 / PMC_WAKE_PCIE_3
GPIO_S5_4
GPIO_S5_5 / PMU_SUSCLK_1
GPIO_S5_6 / PMU_SUSCLK_2
GPIO_S5_7 / PMU_SUSCLK_3
C13
A13
C19
B
PMC_RSMRST#
PMC_CORE_PWROK
PCU_SPI_CS_0#
PCU_SPI_CS_1# / GPIO_S5_21
PCU_SPI_MISO
PCU_SPI_MOSI
PCU_SPI_CLK
B18
B16
C18
A17
C17
C16
B14
C15
SOC_KBRST#
SOC_TS_INT#
SOC_TP_INT#
2
2R34
R36
modify R02
@
@
ILB_RTC_TEST#
ILB_RTC_RST#
TAP_TCK
TAP_TRST#
TAP_TMS
TAP_TDI
TAP_TDO
TAP_PRDY#
TAP_PREQ#
RESERVED_AT34
C23
C21
B22
A21
C22
SOC_SPI_CS0#
PMC_SUSPWRDNACK / GPIO_S5_11
PMC_SUSCLK_0 / GPIO_S5_12
PMC_SLP_S0IX# / GPIO_S5_13
PMC_SLP_S4#
PMC_SLP_S3#
GPIO_S5_14
PMC_ACPRESENT
PMC_WAKE_PCIE_0# / GPIO_S5_15
PMC_BATLOW#
PMC_PWRBTN# / GPIO_S5_16
PMC_RSTBTN#
PMC_PLTRST#
GPIO_S5_17
PMC_SUS_STAT# / GPIO_S5_18
PCIE_CLKN_1
PCIE_CLKP_1
AK4
AK6
+1.8VALW
SIO_UART2_RXD / GPIO_S0_SC_74
SIO_UART2_TXD / GPIO_S0_SC_75
SIO_UART2_RTS# / GPIO_S0_SC_76
SIO_UART2_CTS# / GPIO_S0_SC_77
+1.8VALW
1
R25
R26
2
ICLK_ICOMP
ICLK_RCOMP
2
D1
2.2K_0402_5%
2
2
RESERVED_AD9
AD14
AD13
ICLK_ICOMP
ICLK_RCOMP
PMC_ACIN
1
5
4
XTAL_25M_OUT
1
2
R24
P
2
3
AU34
AV34
BA34
AY34
G
GND
AD9
SIO_UART1_RXD / GPIO_S0_SC_70
SIO_UART1_TXD / GPIO_S0_SC_71
SIO_UART1_RTS# / GPIO_S0_SC_72
SIO_UART1_CTS# / GPIO_S0_SC_73
3
3
GND
ICLK_OSCIN
ICLK_OSCOUT
R22
4.7K_0402_5%
U4
NC
1
1
2
C11
10P_0402_25V8J
D
1
1
AH12
XTAL_25M_IN
XTAL_25M_OUT AH10
R23
1M_0402_5%
Y1
25MHZ_10PF_7V25000014
1
1.8V
2
1
USOC1E
G
XTAL_25M_IN
5
+1.8VS
+1.8VALW
EC_SERIRQ
PMC_SLP_S3#
R116 2
B
1 2.2K_0402_5%
TPM@
EC_SLP_S3#
+1.8VALW
+3VALW_EC
+1.8VALW
U27
+BIOS_SPI
2
C19
RTC_TEST#
RTC_RST#
SPI ROM ( 8MByte ) 1.8V
SPI_CS0#
SPI_CLK
SPI_MOSI
SPI_MISO
1
2
3
4
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
8
7
6
5
SOC_SPI_CLK
SOC_SPI_MOSI
SOC_SPI_MISO
SOC_SPI_CS0#
1
2
3
4
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS0#
22_0804_8P4R_5%
EMC@
3
1
Q21
TPM@
MESS138W-G_SOT323-3
trace width 10mil
+RTCBATT
RTC_TEST#
EC_SLP_S3#
<23>
Modify R02
W25Q64DWSSIG_SO8
CL_CMOS
@
S
SP@
JCMOS1
SHORT PADS
SP@
JCMOS2
SHORT PADS
2
1
@EMC@ C23
10P_0402_50V8J
+RTCVCC
Clear CMOS
Close to RAM door
1
1
2
3
Modify R03
A
C22
.1U_0402_16V7K
BAS40-04_SOT23-3
Reserve for EMI(Near SPI ROM)
1
2
@EMC@ R47
33_0402_5%
+RTCVCC
2
D
2
G
Q19
MESS138W-G_SOT323-3
SPI_CLK
W=20mils
+CHGRTC
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
VLV-M SOC CLK/PMU/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
<21,23>
D2
<23>
8
7
6
5
PMC_SLP_S3#
W=20mils
SPI_HOLD#
SPI_CLK
SPI_MOSI
RP9
From CPU
EC_SERIRQ
U7
SPI_CS0#
SPI_MISO
SPI_WP#
22_0804_8P4R_5%
EMC@
A
1
20K_0402_1%
C21
1U_0402_6.3V6K
+BIOS_SPI
1
8
7
6
5
2
3
RP8
1
2
3
4
EC_SPICS#
EC_SPICLK
EC_MOSI
EC_MISO
1
2
R44
D
From EC
(For share ROM)
1
S
2
C20
1U_0402_6.3V6K
6
5
4
2
SPI_HOLD#
VCCB
EO
B4
G2129TL1U_SC70-6
TPM@
+1.8VALW
R42
20K_0402_1%
2
1
1
SPI_WP#
2 3.3K_0402_5%
1
0_0402_5%
1 .1U_0402_16V7K
2
2 3.3K_0402_5%
1
@
VCCA
GND
A4
G
1
R43
2
R40
SOC_SERIRQ
+1.8VALW
Modify R03
SPI_CS0#
1
2 3.3K_0402_5%
2
1
R41
<23> EC_SPICS#
<23> EC_SPICLK
<23> EC_MOSI
<23> EC_MISO
<10>
+RTCVCC
+BIOS_SPI
R39
1
2
SOC_SERIRQ 3
4
3
2
Thursday, March 13, 2014
Sheet
1
9
of
39
5
4
3
2
1
USOC1F
M3
L1
K2
K3
M2
N3
P2
L3
J3
P3
H3
B12
<22>
<22>
USB20_P0
USB20_N0
USB Hub
<22>
<22>
USB20_P1
USB20_N1
Touch Panel
<16>
<16>
USB20_P2
USB20_N2
USB3.0 Connector
Camera
+1.8VALW
R49
R51
C
<16>
<16>
1
1
2 10K_0402_5% USB_OC0#
2 10K_0402_5% USB_OC1#
M16
K16
J14
G14
K12
J12
K10
H10
USB20_P3
USB20_N3
1
1
1K_0402_1%
1K_0402_1%
USB_OC0#
ICLK_USB_TERMP
ICLK_USB_TERMN
USB_OC1#
D10
F10
C20
B20
GPIO_S5_32
GPIO_S5_33
GPIO_S5_34
GPIO_S5_35
GPIO_S5_36
GPIO_S5_37
GPIO_S5_38
GPIO_S5_39
RESERVED_P6
RESERVED_P7
RESERVED_M7
USB3_REXT0
RESERVED_P10
RESERVED_P12
RESERVED_M4
RESERVED_M6
GPIO_S5_40
GPIO_S5_41
GPIO_S5_42
GPIO_S5_43
USB3_RXP0
USB3_RXN0
USB3_TXP0
USB3_TXN0
USB_DP0
USB_DN0
BIOS/EFI Top Swap
M10
M9
While updating the BIOS/EFI boot sector in
flash, unexpected system power loss can
cause an incomplete write resulting in a
corrupt boot sector.
P6
P7
R48
M7
1.24K_0402_1%
M12 USB3_REXT0 1
2
D
Reference EDS v1.5 Page2294
P10
P12
M4
M6
D4
E3
PCH_USB3_RX0_P
PCH_USB3_RX0_N
K6
K7
PCH_USB3_TX0_P
PCH_USB3_TX0_N
<22>
<22>
USB3 Port 0
<22>
<22>
USB_DP1
USB_DN1
USB_DP2
USB_DN2
BIOS/EFI Top Swap
USB_DP3
USB_DN3
RESERVED_H8
RESERVED_H7
ICLK_USB_TERMP
ICLK_USB_TERMN
RESERVED_H4
RESERVED_H5
H8
H7
+1.8VS
H4
H5
Modify R02
C
R53
10K_0402_5%
USB_OC_0# / GPIO_S5_19
USB_OC_1# / GPIO_S5_20
GPIO_S0_SC_56
1
<22>
2 R50
2 R52
RESERVED_M10
RESERVED_M9
1
D
GPIO_S5_31
2
G2
NOTE: Ref checklist rev1.2 p.24
USB_PLL_MON is a single ended signal and should follow
single ended signal routing requirements.
B4
B5
NOTE: Ref checklist rev1.2 p.25
USB_HSIC_RCOMP must NOT float if they are not being used.
1
+1.8VS
2
HSIC_RCOMP
45.3_0402_1%
R57
E2
D2
A7
USB_PLL_MON
USB_HSIC0_DATA
USB_HSIC0_STROBE
ILB_8254_SPKR / GPIO_S0_SC_54
49.9_0402_1%1
<21,23>
<21,23>
<21,23>
<21,23>
<21,23>
<23>
<21>
<21>
<9>
2.2K_0804_8P4R_5%
EMC@
R02 modify
+1.8VS
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_CLK_EC
CLK_PCI_TPM
LPC_CLKRUN#
SOC_SERIRQ
2 R58
SIO_I2C0_DATA / GPIO_S0_SC_78
SIO_I2C0_CLK / GPIO_S0_SC_79
LPC_CLK_0
22_0402_5% 1 EMC@ 2 R61
LPC_CLK_1
22_0402_5% 1 EMC@ 2 R62
LPC_CLKRUN#
BF18
BH16
BJ17
BJ13
BG14
BG17
BG15
BH14
BG16
BG13
SIO_I2C1_DATA / GPIO_S0_SC_80
SIO_I2C1_CLK / GPIO_S0_SC_81
LPC_RCOMP / VGA_RCOMP
ILB_LPC_AD_0 / GPIO_S0_SC_42
ILB_LPC_AD_1 / GPIO_S0_SC_43
ILB_LPC_AD_2 / GPIO_S0_SC_44
ILB_LPC_AD_3 / GPIO_S0_SC_45
ILB_LPC_FRAME# / GPIO_S0_SC_46
ILB_LPC_CLK_0 / GPIO_S0_SC_47
ILB_LPC_CLK_1 / GPIO_S0_SC_48
ILB_LPC_CLKRUN# / GPIO_S0_SC_49
ILB_LPC_SERIRQ / GPIO_S0_SC_50
2
S
D
4 PCU_SMB_CLK
Q4A
DMN63D8LDW_SOT363-6
6
1
SIO_I2C3_DATA / GPIO_S0_SC_84
SIO_I2C3_CLK / GPIO_S0_SC_85
SIO_I2C5_DATA / GPIO_S0_SC_88
SIO_I2C5_CLK / GPIO_S0_SC_89
ILB_LPC_CLK_0 : Output
Need Check with EC
Q4B
DMN63D8LDW_SOT363-6
of
25MHz,
6 OF 13
ILB_LPC_CLK_1 is for CLK_0 feedback.(Input)
Set to Outpot for Normal Usage
2
* 1: DISABLED
0: ENABLED
BH22
BG23
For Touch Screen
BG24
BH24
BG25
BJ25
SOC_I2C2_DATA
SOC_I2C2_CLK
SOC_I2C5_DATA R59
1
SOC_I2C5_CLK
1
R60
+1.8VS
EDP@
2 2.2K_0402_5%
EDP@2 2.2K_0402_5%
B
BG26
BH26
BF27
BG27
BH28
BG28
3
SOC_I2C5_DATA 4
EDP@ Q2A
DMN63D8LDW_SOT363-6
SOC_I2C5_DATA
SOC_I2C5_CLK
SOC_I2C5_CLK
Modify R02
SIO_I2C6_DATA / GPIO_S0_SC_90
SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP
PCU_SMB_DATA
S
D
EC_SMB_DA2
<20>
+1.8VS
PCU_SMB_DATA / GPIO_S0_SC_51
PCU_SMB_CLK / GPIO_S0_SC_52
PCU_SMB_ALERT# / GPIO_S0_SC_53
G
<14,19,23>
SIO_I2C2_DATA / GPIO_S0_SC_82
SIO_I2C2_CLK / GPIO_S0_SC_83
5
BG12
PCU_SMB_DATA
BH10
PCU_SMB_CLK
PCU_SMB_ALERT# BG11
G
3
EC_SMB_CK2
SOC_SPKR
USB_HSIC_RCOMP
SIO_I2C4_DATA / GPIO_S0_SC_86
SIO_I2C4_CLK / GPIO_S0_SC_87
Pull High at EC side
<14,19,23>
LPC_RCOMP
SOC_SPKR
5
B
4 PCU_SMB_CLK
3 PCU_SMB_DATA
2 PCU_SMB_ALERT#
1
BIOS/EFI Top Swap
BH12
GPIO_S0_SC_56
USB_HSIC1_DATA
USB_HSIC1_STROBE
RP10
5
6
7
8
R55 @
10K_0402_5%
GPIO_S0_SC_56
FH8065301546401_FCBGA131170
GPIO_S0_SC_092
GPIO_S0_SC_093
I2C5_SDA_PNL
<16>
I2C5_SCL_PNL
<16>
2
M13
BD12
BC12
BD14
BC14
BF14
BD16
BC16
G
USB_PLL_MON
GPIO_S0_SC_55
GPIO_S0_SC_56
GPIO_S0_SC_57 / PCU_UART_TXD
GPIO_S0_SC_58
GPIO_S0_SC_59
GPIO_S0_SC_60
GPIO_S0_SC_61 / PCU_UART_RXD
1
6
EDP@ Q2B
DMN63D8LDW_SOT363-6
D
2
USB_RCOMPO
USB_RCOMPI
S
R56 1
@
0_0402_5%
D6
C7
USB_RCOMP
G
2
D
R54 1
45.3_0402_1%
S
C24
@EMC@
2
1 10P_0402_50V8J LPC_CLK_0
BJ29
BG29
BH30
BG30
GPIO_S0_SC_92
GPIO_S0_SC_93
T14 @
T15 @
For Touch Pad
+1.8VS
@
SOC_I2C2_DATA R63
1
SOC_I2C2_CLK
1
2 2.2K_0402_5%
PDA (Platform Debug Assistant) Test Points
R64
+3VS
2 2.2K_0402_5%
+1.8VS
CPU Thermal sensor
6
5
SDATA
D+
ALERT#
D-
GND
THERM#
REMOTE1+
3
REMOTE1-
4
2
THERM# 1
@
R258 10K_0402_5%
5
G
2
@ C276
2200P_0402_50V7K
+3VS
REMOTE1-
ADM1032ARMZ-2REEL_MSOP8
Modify R03
1
2
B
C @
Q22
MMST3904-7-F_SOT323-3
I2C2_SDA_TP
<24>
I2C2_SCL_TP
<24>
2
D
3
SOC_I2C2_DATA 4
Q3A
DMN63D8LDW_SOT363-6
REMOTE1+
G
2
2
S
1
SOC_I2C2_CLK
Modify R02
E
1
6
Q3B
DMN63D8LDW_SOT363-6
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
D
7
VDD
S
SCLK
1
1
EC_SMB_DA2
8
@
3
EC_SMB_CK2
0.1U_0402_16V4Z
C275
A
@ U28
2014/04/12
Deciphered Date
Title
VLV-M SOC USB/LPC/SMBus
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
10
of
39
A
5
4
3
2
1
D
D
+1.35V_SOC
12A
+SOC_VCC
USOC1G
AA27
AA29
AA30
AC27
AC29
AC30
AD27
AD29
AD30
AF27
AF29
AG27
AG29
AG30
P26
P27
U27
U29
V27
V29
V30
Y27
Y29
Y30
C
@
AA22
TP2_CORE_VCC_S0iX
T16
CORE_VCC_S0IX_AA27
CORE_VCC_S0IX_AA29
CORE_VCC_S0IX_AA30
CORE_VCC_S0IX_AC27
CORE_VCC_S0IX_AC29
CORE_VCC_S0IX_AC30
DRAM_VDD_S4_AD38
DRAM_VDD_S4_AF38
A48
AK38
AM38
AV41
AV42
BB46
BD49
BD52
BD53
BF44
BG51
BJ48
C51
D44
F49
F52
F53
H46
M41
M42
V38
Y38
DRAM_VDD_S4_A48
DRAM_VDD_S4_AK38
DRAM_VDD_S4_AM38
DRAM_VDD_S4_AV41
DRAM_VDD_S4_AV42
DRAM_VDD_S4_BB46
DRAM_VDD_S4_BD49
DRAM_VDD_S4_BD52
DRAM_VDD_S4_BD53
DRAM_VDD_S4_BF44
DRAM_VDD_S4_BG51
DRAM_VDD_S4_BJ48
DRAM_VDD_S4_C51
DRAM_VDD_S4_D44
DRAM_VDD_S4_F49
DRAM_VDD_S4_F52
DRAM_VDD_S4_F53
DRAM_VDD_S4_H46
DRAM_VDD_S4_M41
DRAM_VDD_S4_M42
DRAM_VDD_S4_V38
DRAM_VDD_S4_Y38
CORE_VCC_S0IX_AD27
CORE_VCC_S0IX_AD29
CORE_VCC_S0IX_AD30
CORE_VCC_S0IX_AF27
CORE_VCC_S0IX_AF29
CORE_VCC_S0IX_AG27
CORE_VCC_S0IX_AG29
CORE_VCC_S0IX_AG30
CORE_VCC_S0IX_P26
CORE_VCC_S0IX_P27
CORE_VCC_S0IX_U27
CORE_VCC_S0IX_U29
CORE_VCC_S0IX_V27
CORE_VCC_S0IX_V29
CORE_VCC_S0IX_V30
CORE_VCC_S0IX_Y27
CORE_VCC_S0IX_Y29
CORE_VCC_S0IX_Y30
JP1 JP@
C25
C26
1
1
JUMP_43X118
1250mA
C
+1.35V_SOC
C27
C28
C29
C30
2
2
2
2
1
1
1
1
C31
C32
1
1
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
TP2_CORE_VCC_S0IX
+1.35VS
AM22
AK32
AK30
AK29
AK27
AK25
AK24
AK22
AJ24
AJ22
AG24
AG22
AF24
AF22
AD22
AC24
AC22
AA24
AD24
+SOC_VCC
1
1
B
BB8
P28
N28
VGFX_VSNS
VCORE_VSNS
VCORE_GSNS
UNCORE_VNN_S3_AM22
UNCORE_VNN_S3_AK32
UNCORE_VNN_S3_AK30
UNCORE_VNN_S3_AK29
UNCORE_VNN_S3_AK27
UNCORE_VNN_S3_AK25
UNCORE_VNN_S3_AK24
UNCORE_VNN_S3_AK22
UNCORE_VNN_S3_AJ24
UNCORE_VNN_S3_AJ22
UNCORE_VNN_S3_AG24
UNCORE_VNN_S3_AG22
UNCORE_VNN_S3_AF24
UNCORE_VNN_S3_AF22
UNCORE_VNN_S3_AD22
UNCORE_VNN_S3_AC24
UNCORE_VNN_S3_AC22
UNCORE_VNN_S3_AA24
UNCORE_VNN_S3_AD24
AG18
AJ19
ICLK_V1P35_S3_F2_AG18
ICLK_V1P35_S3_F1_AJ19
420mA
BD1
VGA_V1P35_S3_F1_BD1
AD36
DRAM_V1P35_S0IX_F1_AD36
AG32
V36
U36
UNCORE_V1P35_S0IX_F2_AG32
UNCORE_V1P35_S0IX_F3_V36
UNCORE_V1P35_S0IX_F4_U36
B
AA25
UNCORE_V1P35_S0IX_F5_AA25
AF19
AG19
UNCORE_V1P35_S0IX_F6_AF19
UNCORE_VNN_SENSE
UNCORE_V1P35_S0IX_F1_AG19
CORE_VCC_SENSE_P28 7 OF 13
CORE_VSS_SENSE_N28
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
1
<33>
<33>
<33>
2
R68
100_0402_1%
2
R67
100_0402_1%
JUMP_43X118
JP2 JP@
2 1U_0402_6.3V6K
2 .1U_0402_16V7K
14A +SOC_VNN
+SOC_VNN
+1.35V
20mil
AD38
AF38
FH8065301546401_FCBGA131170
@
2
R70
100_0402_1%
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
VLV-M SOC Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
11
of
39
5
4
3
2
1
D
D
Follow CRBv1.15
+1.05VS
USOC1H
+1.0VALW
UNCORE_V1P0_G3 1uF*4
USB3_V1P0_G3 0.01uF*1
C48
C49
C46
C50
1
1
1
1
2
2
2
2
C47
1
2 0.01U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.0VS
C
DRAM_V1P0_S0iX 1uF*4
C55
C56
C58
C59
1
1
1
1
2
2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDI_V1P0_S0iX 1uF*4
C60
C61
C62
C64
1
1
1
1
2
2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C68
C69
C71
C72
C73
1
1
1
1
1
2
2
2
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
C74
C76
C78
C80
C81
C82
C83
C84
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
0.01U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
UNCORE_V1P0_S0iX 22uF*3
1uF*2
PCIE_SATA_V1P0_S3 1uF*1
UNCORE_V1P0_S3 1uF*1
PCIE_V1P0_S3 1uF*1
VGA_V1P0_S3 1uF*1
USB_V1P0_S3 0.1uF*1
USB3DEV_V1P0_S3 0.01uF*1
GPIO_V1P0_S3 1uF*1
SVID_V1P0_S3 1uF*1
B
U22
V22
C5
B6
Y19
C3
V32
BJ6
AD35
AF35
AF36
AA36
AJ36
AK35
AK36
Y35
Y36
AK19
AK21
AJ18
AM16
AN29
AN30
V24
Y22
Y24
AF16
AF18
Y18
G1
AK18
AM18
AM21
AN21
AN18
AN19
AF21
AG21
M14
U18
U19
AN25
325mA
UNCORE_V1P0_G3_U22
UNCORE_V1P0_G3_V22
UNCORE_V1P0_G3_C5
UNCORE_V1P0_G3_B6
1000mA
CORE_V1P0_S3_AC32
CORE_V1P0_S3_Y32
USB3_V1P0_G3_Y19
USB3_V1P0_G3_C3
2750mA
SVID_V1P0_S3_V32
VGA_V1P0_S3_BJ6
DRAM_V1P0_S0IX_AD35
DRAM_V1P0_S0IX_AF35
DRAM_V1P0_S0IX_AF36
DRAM_V1P0_S0IX_AA36
DRAM_V1P0_S0IX_AJ36
DRAM_V1P0_S0IX_AK35
DRAM_V1P0_S0IX_AK36
DRAM_V1P0_S0IX_Y35
DRAM_V1P0_S0IX_Y36
DDI_V1P0_S0IX_AK19
DDI_V1P0_S0IX_AK21
DDI_V1P0_S0IX_AJ18
DDI_V1P0_S0IX_AM16
VIS_V1P0_S0IX_AN29
VIS_V1P0_S0IX_AN30
VIS_V1P0_S0IX_V24
VIS_V1P0_S0IX_Y22
VIS_V1P0_S0IX_Y24
UNCORE_V1P0_S3_AF16
UNCORE_V1P0_S3_AF18
UNCORE_V1P0_S3_Y18
UNCORE_V1P0_S3_G1
PCIE_V1P0_S3_AK18
PCIE_V1P0_S3_AM18
PCIE_V1P0_S3_AM21
PCIE_V1P0_S3_AN21
PCIE_SATA_V1P0_S3_AN18
SATA_V1P0_S3_AN19
UNCORE_V1P0_S0IX_AF21
UNCORE_V1P0_S0IX_AG21
USB_V1P0_S3_M14
USB_V1P0_S3_U18
USB_V1P0_S3_U19
GPIO_V1P0_S3_AN25
CORE_V1P05_S3_AA33
CORE_V1P05_S3_AF33
CORE_V1P05_S3_AG33
CORE_V1P05_S3_AG35
CORE_V1P05_S3_U33
CORE_V1P05_S3_U35
CORE_V1P05_S3_V33
F1
TP_CORE_V1P05_S4 AF30
AA33
AF33
AG33
AG35
U33
U35
V33
C51
1
2 0.47U_0402_6.3V6K
C52
C53
C54
1
1
1
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
CORE_V1P05_S3 1uF*3
+1.8VALW
C
UNCORE_V1P8_G3_U24
PCU_V1P8_G3_V25
USB_V1P8_G3_N20
65mA PMU_V1P8_G3_U25
UNCORE_V1P8_G3_AA18
U24
V25
N20
U25
AA18
C57
1
2 1U_0402_6.3V6K
C63
C65
C66
C67
1
1
1
1
2
2
2
2
C70
1
2 1U_0402_6.3V6K
PMC_V1P8_G3 1uF*1
+1.8VS
10mA
UNCORE_V1P8_S3_AM30
UNCORE_V1P8_S3_AN32
UNCORE_V1P8_S3_U38
58mA
HDA_V1P5_S3_AM32
50mA PCU_V3P3_G3_N22
USB_V3P3_G3_N18
USB_V3P3_G3_P18
33mA
VGA_V3P3_S3_AN24
SD3_V1P8V3P3_S3_AN27
LPC_V1P8V3P3_S3_AM27
35mA
USB_HSIC_V1P2_G3_V18
T17
@
AC32
Y32
RESERVED_F1
VSS_AD16
VSS_AD18
AM30
AN32
U38
UNCORE_V1P8_S3 1uF*4
+1.5VS
AM32
N22 +3VALW_SOC
N18
P18
2
R71
C75 1
C77 1
C79 1
HDA_LPE_V1P5V1P8_S3 1uF*1
+3VALW
1
@
0_0402_5% Modify R02
2 .1U_0402_16V7K
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
AN24 +3VS_SOC
2
USB_V3P3_G3 0.1uF*1
USB_ULPI_V1P8_S3 1uF*1
PCU_V3P3_G3 1uF*1
+3VS
1
VGA_V3P3_S3 1uF*1
0_0402_5% Modify R02
+3VS
C85
1U_0402_6.3V6K
+1.8VS
AM27 +1.8VS_3.3VS LPC 2 TPM@ 1
R73
0_0402_5%
2 NTPM@ 1
R74
0_0402_5%
V18
1
2
+1.0VALW
C86
1U_0402_6.3V6K
USB_HSIC_V1P2_G3 1uF*1
AD16
2 1U_0402_6.3V6K
C87 1
Disable HSIC
AD18
@
@
R72
AN27
1
2
B
If the USB HSIC is not used, pin V18 can be connected
to either +V1P2A or +V1P0A.
Pop when use +1.2VALW
TP_CORE_V1P05_S4_AF30
8 OF 13
FH8065301546401_FCBGA131170
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
VLV-M SOC Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
12
of
39
5
4
3
2
1
D
D
C
C
USOC1I
A11
A15
A19
A23
A27
A31
A35
A39
A43
A47
AA1
AA16
AA19
AA21
AA3
AA32
AA35
AA38
AA53
AB10
AB4
AB41
AB45
AB47
AB48
AB50
AB51
AB6
AC16
AC18
AC19
AC21
AC25
AC33
AC35
B2
A6
A52
A51
A5
A49
A3
BH53
BH52
BH2
BH1
BG53
E53
B
U16
AN16
VSS_A11
VSS_AC36
VSS_A15
VSS_AC38
VSS_A19
VSS_AD19
VSS_A23
VSS_AD21
VSS_A27
VSS_AD25
VSS_A31
VSS_AD32
VSS_A35
VSS_AD33
VSS_A39
VSS_AD47
VSS_A43
VSS_AD7
VSS_A47
VSS_AE1
VSS_AA1
VSS_AE11
VSS_AA16
VSS_AE12
VSS_AA19
VSS_AE14
VSS_AA21
VSS_AE3
VSS_AA3
VSS_AE4
VSS_AA32
VSS_AE40
VSS_AA35
VSS_AE42
VSS_AA38
VSS_AE43
VSS_AA53
VSS_AE45
VSS_AB10
VSS_AE46
VSS_AB4
VSS_AE48
VSS_AB41
VSS_AE50
VSS_AB45
VSS_AE51
VSS_AB47
VSS_AE53
VSS_AB48
VSS_AE6
VSS_AB50
VSS_AE8
VSS_AB51
VSS_AE9
VSS_AB6
VSS_AF10
VSS_AC16
VSS_AF12
VSS_AC18
VSS_AF25
VSS_AC19
VSS_AF32
VSS_AC21
VSS_AF47
VSS_AC25
VSS_AG16
VSS_AC33
VSS_AG25
VSS_AC35 9 OF 13VSS_AG36
VSS_B2
VSS_B52
VSS_A6
VSS_B53
VSS_A52
VSS_BE1
VSS_A51
VSS_BE53
VSS_A5
VSS_BG1
VSS_A49
VSS_BJ2
VSS_A3
VSS_BJ3
VSS_BH53
VSS_BJ5
VSS_BH52
VSS_BJ49
VSS_BH2
VSS_BJ51
VSS_BH1
VSS_BJ52
VSS_BG53
VSS_C1
VSS_E53
VSS_C53
VSS_E1
USOC1J
AC36
AC38
AD19
AD21
AD25
AD32
AD33
AD47
AD7
AE1
AE11
AE12
AE14
AE3
AE4
AE40
AE42
AE43
AE45
AE46
AE48
AE50
AE51
AE53
AE6
AE8
AE9
AF10
AF12
AF25
AF32
AF47
AG16
AG25
AG36
B52
B53
BE1
BE53
BG1
BJ2
BJ3
BJ5
BJ49
BJ51
BJ52
C1
C53
E1
AG38
AH4
AH41
AH45
AH7
AH9
AJ1
AJ16
AJ21
AJ25
AJ27
AJ29
AJ3
AJ30
AJ32
AJ33
AJ35
AJ38
AJ53
AK10
AK14
AK16
AK33
AK41
AK44
AM12
AM19
AM24
AM25
AM29
AM33
AM35
AM36
AM40
M28
VSS_AG38
VSS_AH47
VSS_AH4
VSS_AH48
VSS_AH41
VSS_AH50
VSS_AH45
VSS_AH51
VSS_AH7
VSS_AH6
VSS_AH9
VSS_AM44
VSS_AJ1
VSS_AM51
VSS_AJ16
VSS_AM7
VSS_AJ21
VSS_AN1
VSS_AJ25
VSS_AN11
VSS_AJ27
VSS_AN12
VSS_AJ29
VSS_AN14
VSS_AJ3
VSS_AN22
VSS_AJ30
VSS_AN3
VSS_AJ32
VSS_AN33
VSS_AJ33
VSS_AN35
VSS_AJ35
VSS_AN36
VSS_AJ38
VSS_AN38
VSS_AJ53
VSS_AN40
VSS_AK10
VSS_AN42
VSS_AK14
VSS_AN43
VSS_AK16
VSS_AN45
VSS_AK33
VSS_AN46
VSS_AK41
VSS_AN48
VSS_AK44
VSS_AN49
VSS_AM12
VSS_AN5
VSS_AM19
VSS_AN51
VSS_AM24
VSS_AN53
VSS_AM25
VSS_AN6
VSS_AM29
VSS_AN8
VSS_AM33
VSS_AN9
VSS_AM35
VSS_AP40
VSS_AM36
VSS_AT12
VSS_AM40
VSS_AT16
VSS_M28 10 OF 13 VSS_AT19
FH8065301546401_FCBGA131170
@
USOC1K
AH47
AH48
AH50
AH51
AH6
AM44
AM51
AM7
AN1
AN11
AN12
AN14
AN22
AN3
AN33
AN35
AN36
AN38
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN5
AN51
AN53
AN6
AN8
AN9
AP40
AT12
AT16
AT19
AT24
AT27
AT30
AT35
AT38
AT4
AT47
AT52
AU1
AU24
AU3
AU30
AU38
AU51
AV12
AV13
AV14
AV18
AV19
AV24
AV27
AV30
AV35
AV38
AV47
AV51
AV7
AW13
AW19
AW27
AW3
AW35
AY10
AY22
AY32
USOC1L
VSS_AT24
VSS_AY36
VSS_AT27
VSS_AY4
VSS_AT30
VSS_AY50
VSS_AT35
VSS_AY9
VSS_AT38
VSS_BA14
VSS_AT4
VSS_BA19
VSS_AT47
VSS_BA22
VSS_AT52
VSS_BA27
VSS_AU1
VSS_BA32
VSS_AU24
VSS_BA35
VSS_AU3
VSS_BA40
VSS_AU30
VSS_BA53
VSS_AU38
VSS_BB19
VSS_AU51
VSS_BB27
VSS_AV12
VSS_BB35
VSS_AV13
VSS_BC20
VSS_AV14
VSS_BC22
VSS_AV18
VSS_BC26
VSS_AV19
VSS_BC28
VSS_AV24
VSS_BC32
VSS_AV27
VSS_BC34
VSS_AV30
VSS_BC42
VSS_AV35
VSS_BD19
VSS_AV38
VSS_BD24
VSS_AV47
VSS_BD27
VSS_AV51
VSS_BD30
VSS_AV7
VSS_BD35
VSS_AW13
VSS_BE19
VSS_AW19
VSS_BE2
VSS_AW27
VSS_BE35
VSS_AW3
VSS_BE8
VSS_AW35
VSS_BF12
VSS_AY10
VSS_BF16
VSS_AY22
VSS_BF24
VSS_AY32 11 OF 13
VSS_BF38
AY36
AY4
AY50
AY9
BA14
BA19
BA22
BA27
BA32
BA35
BA40
BA53
BB19
BB27
BB35
BC20
BC22
BC26
BC28
BC32
BC34
BC42
BD19
BD24
BD27
BD30
BD35
BE19
BE2
BE35
BE8
BF12
BF16
BF24
BF38
FH8065301546401_FCBGA131170
@
BF30
BF36
BF4
BG31
BG34
BG39
BG42
BG45
BG49
BJ11
BJ15
BJ19
BJ23
BJ27
BJ31
BJ35
BJ39
BJ43
BJ47
BJ7
C14
C31
C34
C39
C42
C45
C49
D12
D16
D24
D30
D36
D38
E19
E35
VSS_BF30
VSS_BF36
VSS_BF4
VSS_BG31
VSS_BG34
VSS_BG39
VSS_BG42
VSS_BG45
VSS_BG49
VSS_BJ11
VSS_BJ15
VSS_BJ19
VSS_BJ23
VSS_BJ27
VSS_BJ31
VSS_BJ35
VSS_BJ39
VSS_BJ43
VSS_BJ47
VSS_BJ7
VSS_C14
VSS_C31
VSS_C34
VSS_C39
VSS_C42
VSS_C45
VSS_C49
VSS_D12
VSS_D16
VSS_D24
VSS_D30
VSS_D36
VSS_D38
VSS_E19
VSS_E35 12 OF 13
USOC1M
VSS_E8
VSS_F19
VSS_F2
VSS_F24
VSS_F27
VSS_F30
VSS_F35
VSS_F5
VSS_F7
VSS_G10
VSS_G20
VSS_G22
VSS_G26
VSS_G28
VSS_G32
VSS_G34
VSS_G42
VSS_H19
VSS_H27
VSS_H35
VSS_J1
VSS_J16
VSS_J19
VSS_J22
VSS_J27
VSS_J32
VSS_J35
VSS_J40
VSS_J53
VSS_K14
VSS_K22
VSS_K32
VSS_K36
VSS_K4
VSS_K50
E8
F19
F2
F24
F27
F30
F35
F5
F7
G10
G20
G22
G26
G28
G32
G34
G42
H19
H27
H35
J1
J16
J19
J22
J27
J32
J35
J40
J53
K14
K22
K32
K36
K4
K50
FH8065301546401_FCBGA131170
@
K9
L13
L19
L27
L35
M19
M26
M27
M34
M35
M38
M47
M51
N1
N16
N38
N51
P13
P16
P19
P20
P24
P32
P35
P38
P4
P47
P52
P9
T40
U1
U11
U12
U14
U21
VSS_K9
VSS_L13
VSS_L19
VSS_L27
VSS_L35
VSS_M19
VSS_M26
VSS_M27
VSS_M34
VSS_M35
VSS_M38
VSS_M47
VSS_M51
VSS_N1
VSS_N16
VSS_N38
VSS_N51
VSS_P13
VSS_P16
VSS_P19
VSS_P20
VSS_P24
VSS_P32
VSS_P35
VSS_P38
VSS_P4
VSS_P47
VSS_P52
VSS_P9
VSS_T40
VSS_U1
VSS_U11
VSS_U12
VSS_U14
VSS_U21 13 OF 13
VSS_U3
VSS_U30
VSS_U32
VSS_U40
VSS_U42
VSS_U43
VSS_U45
VSS_U46
VSS_U48
VSS_U49
VSS_U5
VSS_U51
VSS_U53
VSS_U6
VSS_U8
VSS_U9
VSS_V12
VSS_V16
VSS_V19
VSS_V21
VSS_V35
VSS_V40
VSS_V44
VSS_V51
VSS_V7
VSS_Y10
VSS_Y14
VSS_Y16
VSS_Y21
VSS_Y25
VSS_Y33
VSS_Y41
VSS_Y44
VSS_Y7
VSS_Y9
U3
U30
U32
U40
U42
U43
U45
U46
U48
U49
U5
U51
U53
U6
U8
U9
V12
V16
V19
V21
V35
V40
V44
V51
V7
Y10
Y14
Y16
Y21
Y25
Y33
Y41
Y44
Y7
Y9
B
FH8065301546401_FCBGA131170
@
USB_VSSA_U16
VSSA_AN16
FH8065301546401_FCBGA131170
@
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
VLV-M SOC GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
13
of
39
A
B
C
+DDR_A_VREF_DQ
+1.35V_L
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
1
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
All VREF traces should
have 10 mil trace width
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
<6>
DDR_A_CKE0
<6>
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
2
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<6>
<6>
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_MA10
<6>
DDR_A_BS0
<6>
<6>
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
<6>
DDR_A_CS2#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
3
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
+3VS
R79
2
R80
@
0_0402_5%
@
0_0402_5%
C106
.1U_0402_16V7K
2
1
1
4
1
2
+0.675VS
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1
E
+1.35V_L
CONN@
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
D
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
LCN_DAN06-K4406-0100
Part Number = SP07000WM10
FOX_AS0A621-H2R6-7H_204P
<Address: SA1:SA0=00 (A0H)>
DIMM_1 STD H:4mm
DDR_A_D4
DDR_A_D5
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D[0..63]
DDR_A_D6
DDR_A_D7
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_D12
DDR_A_D13
<6>
<6>
<6>
<6>
<6>
1
DDR_A_DM1
DDR_A_RST#
<6>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_RST#
1
2
C88
.1U_0402_16V7K
DDR_A_DM2
FOR EMI/ESD Require 01/15
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_CKE2
Signal voltage level = 0.675 V
PLACE TWO 4.7K RESISTORS CLOSE TO
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
Decoupling caps are needed; one 0.1 µF placed close to VREF pins of each DDR3 SODIMM.
<6>
DDR_A_MA15
DDR_A_MA14
+1.35V_L
DDR_A_MA11
DDR_A_MA7
+DDR_A_VREF_DQ
2
1
2
R75
4.7K_0402_1%
1
2
R76
4.7K_0402_1%
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
1
2
C89
.1U_0402_16V7K
DDR_A_CLK2 <6>
DDR_A_CLK2# <6>
+1.35V_L
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDR_A_CS0#
DDR_A_ODT0
<6>
<6>
DDR_A_ODT2
<6>
+DDR_A_VREF_CA
1
1
2
R77
4.7K_0402_1%
2
R78
4.7K_0402_1%
1
2
C90
.1U_0402_16V7K
+DDR_A_VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
Layout Note:
Place near JDIMM1
DDR_A_D38
DDR_A_D39
Modify R02
DDR_A_D44
DDR_A_D45
+1.35V_L
+1.35V
+1.35V_L
+1.35VP
+1.35V_L
3
1
DDR_A_DQS#5
DDR_A_DQS5
2
1
L21
HCB2012KF-121T50_0805
EMC@
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
C91
C92
C93
C94
1
1
1
1
2
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C95
C96
C97
C98
C99
C100
C101
C102
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
2
L22
HCB2012KF-221T50_0805
EMC@
+0.675VS
DDR_A_D62
DDR_A_D63
EC_SMB_DA2
EC_SMB_CK2
<10,19,23>
<10,19,23>
C103 1
2 10U_0603_6.3V6M
C104 1
C105 1
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
+0.675VS
Channel A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
4
Layout Note:
Place near JDIMM1.203,204
2013/04/12
2014/04/12
Deciphered Date
Title
DDR3L DIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
14
of
39
A
B
C
D
E
LVDS Translator - RTD2132N
1
1
Close to Pin3
Close to L2
Close to Pin13
Close to Pin18
+DP_V33
Close to Pin27
Close to Pin7
2
2
1
2
C118
LVDS@
0.1U_0402_16V4Z
2
1
C117
LVDS@
0.1U_0402_16V4Z
2
+1.2V_TL
1
C116
LVDS@
0.1U_0402_16V4Z
2
1
C115
LVDS@
10U_0603_6.3V6M
2
1
C114
LVDS@
0.1U_0402_16V4Z
2
1
C113
LVDS@
0.1U_0402_16V4Z
2
1
C112
LVDS@
22U_0805_6.3V6M
2
1
C111
LVDS@
0.1U_0402_16V4Z
0_0603_5%
1
C110
LVDS@
10U_0603_6.3V6M
30mil
2 LVDS@ 1
R81
C109
LVDS@
0.1U_0402_16V4Z
30mil
1
C108
LVDS@
0.1U_0402_16V4Z
+3VS_TL
C107
LVDS@
10U_0603_6.3V6M
+3VS
Close to L3
+SWR_VDD
1
2
1
2
2
2
+3VS_TL
+3VS_TL
U9
<16>
R82 1
2 1K_0402_5%
EC_SMB_CK3
EC_SMB_DA3
9
10
TL_HPD
32
LVDS@
8
4
LVDS@
R83
12K_0402_1%
TXOUT1+ <16>
TXOUT1- <16>
25
26
TXOUT0+
TXOUT0-
TXOUT0+ <16>
TXOUT0- <16>
2.2K_0804_8P4R_5%
LVDS@
R02 modify
+3VS_TL
RTD2132N
AUX_P
AUX_N
LANE0P
LANE0N
CIICSCL1
CIICSDA1
HPD
DP_REXT
DP_GND
GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)
LVDS
EDID
ROM
MIICSCL1
MIICDA1
MODE_CFG1
MODE_CFG0
GND
14
15
16
17
TL_INVT_PWM <16>
TL_ENVDD <16>
INVT_PWM_SOC <16,7>
TL_BKOFF# <16>
29
28
LVDS_SCL
LVDS_SDA
31
30
MODE_CFG1
MODE_CFG0
LVDS_SCL
LVDS_SDA
2
5
6
TXOUT1+
TXOUT1-
2
EDP_TXP0_C_TL
EDP_TXN0_C_TL
2
3
EDP_HPD
2
1
TXOUT2+ <16>
TXOUT2- <16>
23
24
8
7
6
5
R85
4.7K_0402_5%
LVDS@
R84
4.7K_0402_5%
@
1
EC_SMB_CK3
EC_SMB_DA3
EDP_AUXP_C_TL
EDP_AUXN_C_TL
Other
<23>
<23>
EDP_TXP0
EDP_TXN0
LVDS@
C134 1
2 0.1U_0402_16V7K
C133 1
2 0.1U_0402_16V7K
LVDS@ LVDS@
C135 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
C136 1
LVDS@
TXOUT2+
TXOUT2-
1
2
3
4
1
<16,7>
<16,7>
EDP_AUXP
EDP_AUXN
TXE1+
TXE1TXE0+
TXE0-
DP-IN
<16,7>
<16,7>
TXE2+
TXE2-
21
22
LVDS_SCL
LVDS_SDA
EC_SMB_CK3
EC_SMB_DA3
<16>
<16>
2
60mil
SWR_LX
SWR_VCCK
VCCK
DP_V12
TXOUT_CLK+
TXOUT_CLK-
2
+1.2V_TL
SWR_VDD
PVCC
TXOUT_CLK+
TXOUT_CLK-
MODE_CFG0
MODE_CFG1
<16>
<16>
R86
4.7K_0402_5%
LVDS@
33
R87
4.7K_0402_5%
@
3
1
11
27
7
19
20
1
18
60mil12
LVDS
60mil13
RP11
TXEC+
TXEC-
DP_V33
GPIO
60mil
40mil 3
Power
+1.2V_TL
LVDS@
L1 2
1 +DP_V33
HCB2012KF-221T30_0805
LVDS@
2
1 +SWR_VDD
L2
+3VS_TL
HCB2012KF-221T30_0805
L3 1 LVDS@
2
+1.2V_TL_OUT
4.7UH_PG031B-4R7MS_1.1A_20%
1
RTD2132N-CGT_QFN32_5X5
LVDS@
Modify R02,U9 Link CIS symbol
MODE_CFG1(PIN31)
MODE_CFG0(PIN30)
0
1
0
X
EP MODE
1 ROM ONLY MODE* EEPROM MODE
4
4
Compal Secret Data
Security Classification
Issued Date
2013/10/28
2014/10/28
Deciphered Date
Title
LVDS Translator - RTD2132N
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
15
of
39
A
B
C
D
E
Place closed to JLVDS1
+3VS
LCD POWER CIRCUIT
1
+3VS
+LCDVDD
1
U10
W=60mils
1
VOUT
5
B+
W=60mils
VIN
1
2
GND
4
VIN
1
2
3
EN
C124
1U_0402_6.3V6K
SM010014520 3000ma
220ohm@100mhz
DCR 0.04
2
@EMC@
C122
68P_0402_50V8J
G5243AT11U_SOT23-5
2
C119
0.1U_0402_16V4Z
1
2
LCD/ LED PANEL Conn.
C120
0.1U_0402_16V4Z
@
R88
EMC@
+INVPWR_B+
L4
HCB2012KF-221T30_2P
1
2
C121
4.7U_0603_6.3V6K
+LCDVDD
JEDP1
W=60mils
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
+INVPWR_B+
1
1
2
2
@EMC@
C123
1000P_0402_50V7K
INVTPWM
DISPOFF#
EDP_HPD
TL_ENVDD
R89
1 EDP@ 2 0_0402_5%
R90
1 LVDS@ 2 0_0402_5%
<23>
<15>
<15>
<15>
<15>
<23>
<15>
<15>
<15>
<15>
R97 1 EDP@ 2 0_0402_5%
<15,7>
<15,7>
<15,7>
<15,7>
+3VS
For reserve forfixed Voltage level.
TL_BKOFF#
TL_BKOFF#
C127
220P_0402_50V7K
1
@EMC@
2
1
TC7SZ08FU SSOP 5P AND
LVDS@
B
4
Y
A
<7> EDP_TXP1
<7> EDP_TXN1
DISPOFF#
EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
TS_INT#
+5VS_TS
2
<15>
EC_BKOFF#
U11
For reserve forfixed Voltage level.
Modify R03
2
R95
100K_0402_5%
@
2
R96
+3VS
C130
220P_0402_50V7K
1
@EMC@
<10> USB20_P3
<10> USB20_N3
2
R94
100K_0402_5%
@
2
EC_BKOFF#
1
1 LVDS@ 2 0_0402_5%
<23>
P
R93
EDP_TXP0
EDP_TXN0
G
TL_INVT_PWM
<15>
INVTPWM
2
INVT_PWM_SOC
10mils
1 EDP@ 2 0_0402_5%
1
10mils<15,7>
10mils
R92
3
PU to +3VS at CPU side
+3VS
EDP@
2 .1U_0402_16V7K
2 .1U_0402_16V7K
EDP@
2 .1U_0402_16V7K
2 .1U_0402_16V7K
EDP@
2 .1U_0402_16V7K
2 .1U_0402_16V7K
C125 1
C126 1
EDP@
C128 1
C129 1
EDP@
C131 1
C132 1
EDP@
EDP_AUXN
EDP_AUXP
5
2
TS_EN
TXOUT_CLK+
TXOUT_CLKTXOUT2+
TXOUT2TS_RST#
TXOUT1+
TXOUT1TXOUT0+
TXOUT0I2C_SDA
I2C_SCL
TS_EN
TXOUT_CLK+
TXOUT_CLKTXOUT2+
TXOUT2TS_RST#
TXOUT1+
TXOUT1TXOUT0+
TXOUT0-
@
USB20_P2_TS
USB20_N2_TS
1
+3VS_Camcra
USB20_P3
0_0402_5%
USB20_N3
3
<15>
ENVDD
1 0_0402_5%
@
1
W=60mils
+LCDVDD
<7>
2
<BOM Structure>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
G1
G2
G3
G4
G5
G6
41
42
43
44
45
46
2
E-T_0871K-F40N-00L
EDP_AUXN_C R99
2
@
1 100K_0402_5%
EDP_AUXP_C
1
@
2 100K_0402_5%
+LCDVDD
1
SP010011Z00
D13
@EMC@
YSLC05CH_SOT23-3
R100
Modify R02
3
Intel recommends having a pull-up resistor of 100 kΩ for
AUXN and a pull-down resistor of 100 kΩ for AUXP between
the AC capacitor and the connector, to assist source
detection by the sink device.
All reverse on before project.
For Select LVDS EDID or EDP I2C touch
+1.8VS
3
Touch
Modify R02
+5VS_TS
1
1
+5VS
2
0_0402_5%
@
R107
+5VS_TS
R101 2 ETS@
1 2.2K_0402_5%
I2C5_SDA_PNL
L5
R103
10K_0402_5%
1 2.2K_0402_5%
I2C5_SCL_PNL
R104 1 TS@
2 10K_0402_5%
TS_INT#
R106 1 TS@
2 10K_0402_5%
TS_RST#
EDP_HPD#
1
<7>
R102 2 ETS@
2 0_0603_5%
2
R105 1 TS@
<10>
USB20_P2
<10>
USB20_N2
USB20_P2
2
USB20_N2
3
2
EDP_HPD
EDP_HPD
4
1
1
USB20_P2_TS
4
USB20_N2_TS
2
0_0402_5%
@
R108
S
3
3
<15>
1
G
1
WCM2012F2SF-670T04_0805
@EMC@
D
Q6
2N7002K_SOT23-3
2
2
R109
100K_0402_5%
+1.8VS
<15>
LVDS_SDA
<15>
LVDS_SCL
<10>
I2C5_SDA_PNL
<10>
I2C5_SCL_PNL
R111 1 LVDS@ 2 0_0402_5%
I2C_SDA
R112 1 LVDS@ 2 0_0402_5%
I2C_SCL
R113 1 ETS@
2 0_0402_5%
R114 1 ETS@
2 0_0402_5%
Panel
Touch
Cable 1
eDP
I2C,USB
Cable 2
LVDS
USB
BOM option
EDP@,TS@
LVDS@
4
1
4
Solution
2
3
1
S
D
TS_INT_R#
TS_INT_R#
G
<9>
2
TS@ R117
10K_0402_5%
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
TS_INT#
TS@ Q7
MESS138W-G_SOT323-3
2013/04/12
2014/04/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
eDP CONN.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
16
of
39
A
B
C
D
E
Modify R02,R-SHORT R118~R125
W=40mils
+5VS
R118 2
+HDMI_5V_OUT
U12
1
3
OUT
1
HDMI_C_CLK-
1
HDMI_C_CLK+
4
L6
1
IN
2
GND
2
C137
.1U_0402_16V7K
AP2330W-7_SC59-3
<7>
<7>
<7>
<7>
HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+
C138
C139
C140
C141
<7>
<7>
<7>
<7>
HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+
C142
C143
C144
C145
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
HDMI_C_TX0HDMI_C_TX0+
HDMI_C_CLKHDMI_C_CLK+
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
4
HDMI_R_CK-
3
@
3
@
1 0_0402_5%
R120 2
@
1 0_0402_5%
4
HDMI_C_TX0+
1
L7
WCM-2012-900T_0805
3
4
3
1
HDMI_R_D0-
2
@
2
HDMI_R_D0+
R121 2
@
1 0_0402_5%
R122 2
@
1 0_0402_5%
WCM-2012-900T_0805
1
2
1
2
HDMI_C_TX1-
4
L8
HDMI_C_TX1+
HDMI_R_D1-
3
3 @
4
1
HDMI_R_CK+
R119 2
HDMI_C_TX0-
HDMI_C_TX1HDMI_C_TX1+
HDMI_C_TX2HDMI_C_TX2+
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 0_0402_5%
@
WCM-2012-900T_0805
2
1
2
HDMI_R_D1+
R123 2
@
1 0_0402_5%
R124 2
@
1 0_0402_5%
2
2
+1.8VS
RP12
HDMI_DDCDATA
HDMI_DDCCLK
HDMI_SDATA
HDMI_SCLK
5
6
7
8
+HDMI_5V_OUT
4
3
2
1
HDMI_C_TX2-
4
HDMI_C_TX2+
1
L9
WCM-2012-900T_0805
3
4
3
1
R125 2
2.2K_0804_8P4R_5%
2
1
@
HDMI_R_D2-
2
@
HDMI_R_D2+
0_0402_5%
G
5
+1.8VS
G
2
S
3
HDMI_SCLK
Q8A
DMN63D8LDW_SOT363-6
D
4
HDMI_DDCCLK
1
6
Q8B
DMN63D8LDW_SOT363-6
HDMI_SDATA
1
1
1
1
2
2
2
2
619_0402_1%
619_0402_1%
619_0402_1%
619_0402_1%
HDMI_C_TX0HDMI_C_TX0+
HDMI_C_CLKHDMI_C_CLK+
R130
R131
R132
R133
1
1
1
1
2
2
2
2
619_0402_1%
619_0402_1%
619_0402_1%
619_0402_1%
D
HDMI_DDCDATA
S
<7>
R126
R127
R128
R129
HDMI_GND
<7>
HDMI_C_TX1HDMI_C_TX1+
HDMI_C_TX2HDMI_C_TX2+
3
3
3
D
G
5
+3VS
S
4
Q9A
DMN65D8LDW-7 2N SOT363-6
1
+1.8VS
HDMI connector
R134
10K_0402_5%
JHDMI1
2
+HDMI_5V_OUT
HDMI_HPD#
HDMI_SDATA
HDMI_SCLK
2
D
S
1
1
2
HDMI_HPD
HDMI_R_CKR135
100K_0402_5%
2
HDMI_R_CK+
HDMI_R_D0D3
@EMC@
YSLC05CH_SOT23-3
HDMI_R_D0+
HDMI_R_D11
G
Q9B
DMN65D8LDW-7 2N SOT363-6
3
6
<7>
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_HPD
HDMI_R_D1+
HDMI_R_D2-
Reserved for ESD
HDMI_R_D2+
ZZZ
4
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Utility
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND
20
21
22
23
4
ACON_HMR2J-AK120C
CONN@
ACON_HMR2J-AK120C_19P-T
HDMI_ROYALTY
ROYALTY HDMI W/LOGO+HDCP
DC021201210
DC021201210 symbol,
pop DC232003E00
RO0000003HM
45@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
HDMI CONN.
Rev
1.0
Bay Trail M LA-B511P
Thursday, March 13, 2014
Sheet
E
17
of
39
A
B
+3VALW
C
D
E
+3V_LAN
JP10@
W=60mils
IN
2
1
1
@
@
2
2
1
0.1U_0402_16V7K
C201
2
1
0.1U_0402_16V7K
C200
2
1
4.7U_0603_6.3V6K
C199
SA000028Y10
High active.
EN threshold voltage :1.2~2.0V
Current limit threshold :1.5~2.8A
Output turn-on rising time: 1.3~2.7ms
1
4.7U_0603_6.3V6K
C198
+3V_LAN Rising time request: 0.5~100mS
@
+3V_LAN
0.1U_0402_16V7K
2
C192
C197
1
0.1U_0402_16V7K
C191
4.7U_0603_6.3V6K
0.1U_0402_16V7K
IDC=1200mA
C190
0.1U_0402_16V7K
C196
1
0.1U_0402_16V7K
2
C195
C189
4.7U_0603_6.3V6K
0.1U_0402_16V7K
<23>
C194
LAN_PWR_EN
Modify R02
+LAN_VDD
W=60mils
L13
1
2
2.2UH +-5% NLC252018T-2R2J-N
1U_0402_6.3V6K
LAN_PWR_EN
G5243T11U_SOT23-5
SA000028Y10
+REGOUT
2
W=60mils
From EC
3
1
W=60mils
1
EN
1
+3V_LAN
2
Close to Pin 11,32
SWR mode
2
GND
IN
Close to Pin 3,8,22,30
1uF reserved for Pin 22
C193
@ C188
1U_0402_6.3V6K
( Should be place within 200 mils )
Close to Pin 24
Close to U20 Pin23
1
1
4
2
OUT
2
5
2
2
1
1
JUMP_43X39
U19 @
1
1
W=60mils
2
2
1
1
2
close to pin 22
U20
2
2
close to Pin 17, 18
<8>
<8>
<8>
<9>
<9>
LAN_CLKREQ#
PCIE_PTX_C_DRX_P0
PCIE_PTX_C_DRX_N0
CLK_PCIE_LAN
CLK_PCIE_LAN#
MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
MDIP2
MDIN2
AVDD10
MDIP3
MDIN3
AVDD33
CLKREQB
HSIP
HSIN
REFCLK_P
REFCLK_N
HSOP
HSON
PERSTB
ISOLATEB
LANWAKEB
DVDD10
VDDREG
REGOUT
LED2
LED1/GPIO
LED0
CKXTAL1
CKXTAL2
AVDD10
RSET
AVDD33
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PCIE_PRX_C_DTX_P0
PCIE_PRX_C_DTX_N0
PLT_RST_BUF#
ISOLATEB
LAN_PME#
+LAN_VDD
+3V_LAN
+REGOUT
1 @
1 @
C202
C203
R158 2
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PRX_DTX_P0
PCIE_PRX_DTX_N0
PCIE_PRX_DTX_P0 <8>
PCIE_PRX_DTX_N0 <8>
PLT_RST_BUF# <19,21,23,9>
1 0_0402_5%
@
EC_PME#
SJ10000E800
Y4
25MHZ_10PF_7V25000014
<23>
XTLI
EC_PME# pull high 10K to +3VALW at EC
T19 GPO
T20 XTLO
XTLI
+LAN_VDD
LAN_RST
+3V_LAN
2
1
3
3
GND
2
C204
10P_0402_50V8J
XTLO
GND
4
1
C205
10P_0402_50V8J
2
+3V_LAN
R159
1
1
1
2
2.49K_0402_1%
Modify R02
1
PU to +3VS at PCH side
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R160
10K_0402_5%
GPO
2
LAN_MIDI0+
LAN_MIDI0+LAN_VDD
LAN_MIDI1+
LAN_MIDI1LAN_MIDI2+
LAN_MIDI2+LAN_VDD
LAN_MIDI3+
LAN_MIDI3+3V_LAN
LAN_CLKREQ#
PCIE_PTX_C_DRX_P0
PCIE_PTX_C_DRX_N0
CLK_PCIE_LAN
CLK_PCIE_LAN#
R200 2
@
1 0_0402_5%
LAN_GPO
Consider VCC33 may be connected to Main
Power or chipset/bios's GPO, the pull-low
resistor R14 can be NC only when Main Power
or chipset/bios's GPO can ensure to drive the
ISOLATEB pin to a voltage level < 0.8V at the
system state S3~S5.
<23>
RTL8111GS-CG_QFN32_4X4
Modify R02
SA00006ML00
Use 8111GS symbol , pop 8111GUS part
LAN Connector
3
+3VS
3
JRJ45
Place close to TCT pin
2
C207
0.1U_0402_16V7K
RJ45_MIDI2+
RJ45_MIDI2-
15
14
13
RJ45_MIDI3+
RJ45_MIDI3-
RJ45_MIDI3+
7
RJ45_MIDI3-
8
2
6
1
RJ45_MIDI1-
PR3+
PR3-
ISOLATEB
<BOM Structure>
1
5
PR2PR4+
GND
GND
R162
15K_0402_5%
9
10
PR4-
2
MCT4
MX4+
MX4-
18
17
16
RJ45_MIDI2-
R161
1K_0402_5%
PR2+
JP4
B88069X9231T203_4P5X3P2-2
1
@EMC@2
SANTA_130456-291
CONN@
DC234008800
<BOM Structure>
40mil
RJ45_GND
40mil
1
2
C206
10P_0402_50V8J
@
JUMP_43X118
JP11
LANGND
1
TCT4
TD4+
TD4-
GST5009-E
SP050006B10
1
4
MCT3
MX3+
MX3-
4
LANGND
JP5
@EMC@
B88069X9231T203_4P5X3P2-2
D5
MESC5V02BD03_SOT23-3
EMC@
2
10
11
12
TCT3
TD3+
TD3-
RJ45_MIDI1+
RJ45_MIDI1-
RJ45_MIDI2+
PR1-
3
LAN_MIDI3+
LAN_MIDI3-
MCT2
MX2+
MX2-
RJ45_MIDI0+
RJ45_MIDI0-
21
20
19
3
4
1
7
8
9
TCT2
TD2+
TD2-
24
23
22
2
RJ45_MIDI1+
1
R163
75_0402_1%
1
R164
75_0402_1%
2
1
R165
75_0402_1%
2
1
R166
75_0402_1%
LAN_MIDI2+
LAN_MIDI2-
MCT1
MX1+
MX1-
RJ45_MIDI0-
PR1+
2
LAN_MIDI1+
LAN_MIDI1-
4
5
6
TCT1
TD1+
TD1-
2
LAN_MIDI0+
LAN_MIDI0-
1
2
3
LAN_TERMAL
1
2
T21
RJ45_MIDI0+
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOMRJ45_GND
Structure>
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/10/28
2014/10/28
Deciphered Date
Title
LAN_RTL8111GUS-CG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
18
of
39
A
B
C
D
E
For Wireless LAN
1
1
+3VS_WLAN
60mil
+3VS
+3VS_WLAN
JP3 JP@
2
JUMP_43X118
C146
470P_0402_50V7K
1
EMC@
1
2
1
C147
4.7U_0603_6.3V6K
2
JMINI1
1
@
C148
.1U_0402_16V7K
2
<23>
C149
.1U_0402_16V7K
<8>
1
3
5
7
9
11
13
15
WLAN_PME#
WLAN_CLKREQ#
<9> CLK_PCIE_WLAN#
<9> CLK_PCIE_WLAN
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
<8> PCIE_PRX_DTX_N1
<8> PCIE_PRX_DTX_P1
<8> PCIE_PTX_C_DRX_N1
<8> PCIE_PTX_C_DRX_P1
+3VS_WLAN
+3VALW
U13 AC@
2
1
2
VOUT
1
W=60mils
+3VS_WLAN
VIN
2
GND
4
VIN
3
AC@
EN
C150
1U_0402_6.3V6K AP2821KTR-G1_SOT23-5
WLAN_ON
R139 0_0402_5%
R140 0_0402_5%
<23> E51TXD_P80DATA
<23> E51RXD_P80CLK
<23>
1
1
@
@
2
2
53
54
1
5
R141
100K_0402_5%
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WL_OFF# <23>
PLT_RST_BUF# <18,21,23,9>
MINI1_SMBCLK
MINI1_SMBDATA
R137 1
R138 1
@
@
2 0_0402_5%
2 0_0402_5%
EC_SMB_CK2
EC_SMB_DA2
<10,14,23>
<10,14,23>
USB20_HUB_N1
USB20_HUB_P1
<22>
<22>
2
GND1
GND2
BELLW_80053-1021
CONN@
2
DC040009P00
3
3
Lid Switch
Hall sensor
(Hall Effect Switch)
+3VLP
2
2
VDD
VOUT
3
LID_SW#
LID_SW#
<23>
1
C151
@EMC@
10P_0402_50V8J
2
1
C152
0.1U_0402_16V4Z
GND
U14
APX9132GAI-TRG_SOT23-3
1
Modify R02,U14 Link CIS symbol
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
Mini PCIE(WLAN)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
19
of
39
C
D
+5VS
Place near Pin26
2
40
AVDD2
SPKLSPKL+
45
44
SPKR+
SPKR-
32
33
HP_LEFT
HP_RIGHT
10
6
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
5
8
JDMIC1
CPVREF
JDREF
CPVEE
MIC-CAP
AVSS1
AVSS2
48
4.7U_0603_6.3V6M 2
1 C225
GND
4.7U_0603_6.3V6M 2
1 C227
GNDA
29
7
39
27
4.7U_0603_6.3V6M2
28
20K_0402_1% 1
10mil
2 R183
GNDA
CPVEE
Close codec
25
38
2
C233
2.2U_0402_6.3V6M
2
Place next pin27
GND
1
HP_RIGHT
1
@
C278
2
1 R187
2
60.4_0603_1%
HPOUT_L_1
+MICBIAS
@
2
LINE1-L
R192
0_0603_5%
2 4.7U_0603_6.3V6K
C236 1
LINE1-R
C237 1
C238
@EMC@
330P_0402_50V7K
2 4.7U_0603_6.3V6K
D11
2
BLM15PX330SN1D 0402
L20
EMC@
Headphone Out
RING2_L
HPOUT_L_2
3
1
HP_PLUG#
5
6
2
1
2
HPOUT_R_2
2
SLEEVE_L
4
7
C239
@EMC@
330P_0402_50V7K
1
2 R196
1
4.7K_0402_5%
SINGA_2SJ3080-001111F
CONN@
GNDA
2 R197
1
4.7K_0402_5%
DC23000B300 symbol,
same with DC23000B610.
GNDA
BAT54A-7-F_SOT23-3
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
HD Audio Codec_ALC283-CG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
B
4
DC23000B300
1
3
3
SLEEVE
RING2
680P_0402_50V7K
1 EMC@
1 R193
2
60.4_0603_1%
HPOUT_R_1
R185
2.2K_0402_5%
JHP1
GND
Date:
A
2
GND GND
1
GNDA
To solve the background noise while combo jack
connecting to an active
speaker and system entry into S3/S4/S5 without analog
power
GNDA
2
C277
R188
0_0603_5%
DMN65D8LDW-7 2N SOT363-6
3
DMN65D8LDW-7 2N SOT363-6
GNDA
HP_LEFT
Q18A
4
2
R191
100K_0402_5%
C235
100P_0402_50V8J
1
6
Q18B
1
2
G
GND
HDA_RST_AUDIO#
S
JP16
JUMP_43X39
1
2
2
@ 1
JP18
JUMP_43X39
1
2
2
@ 1
@
2 R194
1
10K_0402_5%
2 R195
1
10K_0402_5%
EC_MUTE#
D
JP15
JUMP_43X39
1
2
2
@ 1
JP17
JUMP_43X39
1
2
2
@ 1
SLEEVE_L
RING2_L
680P_0402_50V7K
EMC@ 1
D9
AZ5123-02S.R7G 3P C/A SOT23
EMC@
GNDA
RING2
G
JP14
JUMP_43X39
1
2
2
@ 1
GNDA
2
1
L19
EMC@
BLM15PX330SN1D 0402
1
2
1
2
Modify R03
5
<8>
GND
1
R02 modify
R184
2.2K_0402_5%
Modify R03
GNDA
JP13
JUMP_43X39
1
2
2
@ 1
+MIC2_VREFO
HPOUT_L_2
HPOUT_R_2
GNDA
1 R182
2
100K_0402_5%
CODEC_VREF
15
34
1 C228
GND
2
GND
GND
Add R182 is The main consideration
is shut down after the discharge rate
can be improved boot pop noise.
2 MONO_IN
<23>
4
<8>
+3VLP
@EMC@ 1
5
6
GND
HDA_SDOUT_AUDIO
HDA_SDIN0 <8>
GNDA
C234
1U_0402_6.3V6K
G1
G2
CONN@
D8
MESC5V02BD03_SOT23-3
@EMC@
GND
+MIC2_VREFO
S
SOC_SPKR
R189
47K_0402_5%
2
1
1
1
2
3
4
Modify R03
Footprint -S
16
GND
BEEP#_R
1
2
3
4
DMIC1_DATA
DMIC1_CLK
HDA_SYNC_AUDIO
<8>
HDA_BITCLK_AUDIO <8>
1
DVSS
Thermal PAD
R177 1 @EMC@2 0_0603_5%
R178 1 @EMC@2 0_0603_5%
3
DMIC_DATA
DMIC_CLK
CPVDD
VREF
2
+3VS
1 @EMC@2
1
2 C224 @EMC@
R179
0_0402_5% 22P_0402_50V8J
HDA_SDOUT_AUDIO
1
2
HDA_SDIN0_AUDIO
R180
33_0402_5%
D
<10>
BEEP#
CY000002U00
Digital MIC Conn.
MESC5V02BD03_SOT23-3
D10 @EMC@
<23>
KINGSTATE KEEG1542SBL
CONN@
1
LDO3-CAP
LDO2-CAP
LDO1-CAP
43
42
ALC283-CG_MQFN48_6X6
R186
47K_0402_5%
2
1
@
C220
@EMC@
220P_0402_50V7K
1
CBP
CBN
4
49
+
2
2
MIC2-VREFO
19
AMIC1
1
INT_MIC_R_1
2
46
26
AVDD1
PVDD2
41
2
C231
2.2U_0402_6.3V6M
1 C230
GNDA
C229
0.1U_0402_16V4Z
GNDA
9
SENSE A
SENSE B
20
4.7U_0603_6.3V6M2
SDATA-OUT
SDATA-IN
MONO-OUT
36
+3VS_DVDD
ALC283-CG
PCBEEP
37
35
C226
2.2U_0402_6.3V6M
SYNC
BCLK
SPDIF-OUT/GPIO2
13
14
SENSE_A
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
PDB
RESETB
1
15mil
EMC@
1
2
R175
0_0603_5%
2
12
15mil
1
MONO_IN
SPK-OUT-LSPK-OUT-L+
SPK-OUT-R+
SPK-OUT-R-
MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE
LINE1-VREFO-L
LINE1-VREFO-R
INT_MIC_R
3
47
11
1
3
C219
4.7U_0603_6.3V6M
2
17
18
EC_MUTE#
HDA_RST_AUDIO#
39.2K_0402_1%
1
GNDA
LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)
2
3
10mil
2
24
23
R173
0_0603_5%
2
1
GND
SP02000K200
2
2
ACES_88266-04001
Int. MIC Reserve
R174
2.2K_0402_5%
AMIC@
+1.5VS
3
R181
GND
5
6
G1
G2
Omnidirectional
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)
31
30
+MICBIAS
+MICBIAS2
DMIC_DATA
DMIC_CLK
HP_PLUG#
22
21
PVDD1
U21
GND
2
@
1
+MICBIAS
+MICBIAS2
Close codec
1
Place near Pin40
LINE1-L
LINE1-R
2
1 INT_MIC C221 1
2
LINE2_C_L
AMIC@
R176
1K_0402_5%
AMIC@ 4.7U_0603_6.3V6K
2
2
LINE2_C_R
C2221
C223 1
@EMC@ 1000P_0402_50V7K
AMIC@ 4.7U_0603_6.3V6K
RING2
SLEEVE
Combo MIC
40mil
GND
1
2
3
4
+MICBIAS2
C214,C219 by Vendor command use 4.7uF cap
+1.5VS_VDDA
2
By Vendor command.
INT_MIC_R
+VDDA
R171
0_0603_5%
GNDA
1
1
2
2
@
1
+3VS_DVDD
Internal MIC Reserve
GNDA
2
+3VS_DVDD
1
Place near Pin1
2
1
1
1
2
3
4
SPK_R+
SPK_RSPK_L+
SPK_L-
1
3
2
C214
4.7U_0603_6.3V6M
2
1
1
GND
C216
0.1U_0402_16V4Z
R172
0_0603_5%
+1.5VS_DVDDIO
GND
1
2
20mil
2
@
C215
1U_0603_6.3V6M
1
20mil
C213
0.1U_0402_16V4Z
1
Place near Pin9
+3VS
+AVDD1_HDA
DVDD
Vendor reserve
2
DVDD-IO
R254
0_0603_5%
GND
JSPK1
40mil
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
1
C274
0.1U_0402_16V4Z
20mil
2
@
C273
1U_0603_6.3V6M
1
+1.5VS
(output = 300 mA)
2
2
2
2
@
@
@
@
1
C210
0.1U_0402_16V4Z
Place near Pin41
4.75V
1
1
1
1
R167
R168
R169
R170
D7 @EMC@
MESC5V02BD03_SOT23-3
1
SPKR+
SPKRSPKL+
SPKL-
D6 @EMC@
MESC5V02BD03_SOT23-3
R255
0_0805_5%
40mil
2
JUMP_43X118
@
C208
0.1U_0402_16V4Z
2
@EMC@
2
@
C209
10U_0603_6.3V6M
2
1
1
+VDDA
1
1
+PVDD_HDA
60mil
Int. Speaker Conn.
+VDDA
JP12
40mil
2
HD Audio Codec
E
3
B
2
A
C
D
Thursday, March 13, 2014
Sheet
E
20
of
39
A
B
C
D
E
SATA HDD1 Conn.
1
SATA ODD Conn.
1
JODD1
JHDD1
<8> SATA_PTX_DRX_P0
<8> SATA_PTX_DRX_N0
<8>
<8>
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
C159 1
C156 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C162 1
C157 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
60mils
1
@
2
+5VS_HDD
1
@
2
1
2
C155
.1U_0402_16V7K
Modify R03
C154
1U_0402_6.3V6K
C153
10U_0603_6.3V6M
R143
0_0603_5%
1
2
GND
RX+
RXGND
TXTX+
GND
<8> SATA_PTX_DRX_P1
<8> SATA_PTX_DRX_N1
<8>
<8>
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
C160 1
C161 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
C158 1
C163 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
+5VS
1
@
60mils
2
R142
0_0603_5%
Modify R03
C164
10U_0603_6.3V6M
GND1
GND2
1
C165
.1U_0402_16V7K
2
8
9
10
11
12
13
+5VS_ODD
ODD_MD
1
T18
@
DP
+5V
+5V
MD
GND
GND
14
15
16
17
GND
GND
GND
GND
2
SANTA_201302-1
CONN@
23
24
DC021311120
ALLTO_C166KH-122H9-L
CONN@
2
2
SP011310171
TPM
+3VALW
+3VALW_TPM
2
1
2
1
2
C171 TPM@
0.1U_0402_16V4Z
2
1
C170 TPM@
0.1U_0402_16V4Z
near pin5
1
C169 TPM@
0.1U_0402_16V4Z
2
+3VS_TPM
C168 TPM@
10U_0603_6.3V6M
2
1
+3VS
R145
1
2
0_0603_5%
TPM@
C167 TPM@
0.1U_0402_16V4Z
1
C166 TPM@
10U_0603_6.3V6M
R144
1
2
0_0603_5%
TPM@
FAN1 Conn
+5VS
C172
4.7U_0603_6.3V6K
1
2
near pin10, 19, 24
U15
3
1
2
3
4
+VCC_FAN1
<23>
+3VS_TPM
EN_DFAN1
EN
VIN
VOUT
VSET
8
7
6
5
GND
GND
GND
GND
3
APE8875M_SO8
2
1
R257
10K_0402_5%
TPM@
SA000050J00
LPC_CLKRUN#
U16 TPM@
0_0402_5%
<10>
1
@
2 R146
LPC_CLKRUN#
<10,23>
<10,23>
<10,23>
<10,23>
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
26
23
20
17
LPCPD# had internal PH
<10> CLK_PCI_TPM
<10,23> LPC_FRAME#
<18,19,23,9> PLT_RST_BUF#
<23,9> EC_SERIRQ
CLK_PCI_TPM
LPC_FRAME#
PLT_RST_BUF#
EC_SERIRQ
28
21
22
16
27
7
LAD0/MISO
LAD1/MOSI
LAD2/SPI_IRQ#
LAD3
TEST
NC
NC
NC
NC
LPCPD#
LCLK/SCLK
LRFAME#/SCS#
LRSET#/SPI_RST#
SERIRQ
PP
SERIRQ PH 10K to +3VS at PCH side
4
VSB
VDD
VDD
VDD
5
10
19
24
+3VS
+3VALW_TPM
+3VS_TPM
R147
10K_0402_5%
8
40mil
3
12
13
14
BADD
0
* 1
+VCC_FAN1
SELECTION
<23>
EEh - EFh
FAN_SPEED1
1
7Eh - 7Fh
2
GND
GND
GND
GND
C173
4.7U_0603_6.3V6K
1
2
1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
GPIO0/XOR_OUT
GPIO1
GPIO2/GPX
GPIO3/BADD
GPIO4/CLKRUN#
2
TPM_BADD
LPC_CLKRUN#
1
2
6
9
15
GPIO3/BADD with Internal PH (default)
EMC@
C174
.1U_0402_16V7K
JFAN1
1
2
3
1
2 GND
3 GND
4
5
ACES_88231-03041
CONN@
SP020020710
4
11
18
25
4
NPCT650AA0WX_TSSOP28
SA00007IO00
Issued Date
CLK_PCI_TPM
R148 1
2 33_0402_5% C175 1
2 22P_0402_50V8J
@EMC@
@EMC@
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
HDD/ODD/TPM/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
Rev
1.0
Bay Trail M LA-B511P
C
D
Thursday, March 13, 2014
Sheet
E
21
of
39
A
B
C
D
E
USB3.0 (Port 0)
SM070000S80 WCM2012F2SF-670T04 67ohm
<10>
<10>
PCH_USB3_TX0_P
2
C176
1
PCH_USB3_TX0_P_C
.1U_0402_16V7K
3
PCH_USB3_TX0_N
2
C178
1
PCH_USB3_TX0_N_C
.1U_0402_16V7K
2
L10 EMC@
CMMI21T-900Y-N_4P
4
3
4
2
1
U3TXDP0
+USB3_VCCA
For ESD request
1
10 9
U3RXDN0
U3RXDP0
2 2
9 8
U3RXDP0
U3TXDN0
4 4
7 7
U3TXDN0
W=100mils
C179
220U_6.3V_M
SM070003K00
1
<10>
L11 EMC@
CMMI21T-900Y-N_4P
3
4
3
4
PCH_USB3_RX0_P
PCH_USB3_RX0_P
U3RXDP0
U3TXDP0
5 5
6 6
U3TXDP0
<10>
PCH_USB3_RX0_N
2
1
1
+
2
3 3
2
PCH_USB3_RX0_N
1
U3RXDN0
8
@EMC@
L05ESDL5V0NA-4 SLP2510P8
SM070003K00
2
1
C181
@EMC@
.1U_0402_16V7K
D4
1 1
C180
@EMC@
1000P_0402_50V7K
U3RXDN0
U3TXDN0
SF000002Y00
220U 6.3V OSCON
ESR 17mohm@100Khz
2
USB3.0 Conn.
1
JUSB1
1
2
3
4
5
6
7
8
9
USB20_N0_L
USB20_P0_L
U3RXDN0
U3RXDP0
1
<10>
USB20_P0
<10>
USB20_N0
2
R150
0_0402_5%
SM070001E00
DLW21SN900HQ2L_0805
2
1
2
1
U3TXDN0
U3TXDP0
@
+5VALW
USB20_P0_L
3
4
L17
4
1
2
C177
@EMC@
.1U_0402_16V7K
USB20_N0_L
@EMC@
1
2
3
4
USB_PWR_EN#
1
@
R151
2
0_0402_5%
GND
IN
IN
EN/ENB
1
@
R149
2
0_0402_5%
USB_OC0#
<10>
+USB3_VCCA
SY6288D10CAC_MSOP8
1
2
2
1
2
@
R248
0_0402_5%
SM070001E00
DLW21SN900HQ2L_0805
2
1
2
1
USB20_HUB_P2
3
3
4
L18
2
I/O4
USB2.0 Conn.
6
JUSB3
+USB3_VCCA
4
U2DN2_L
GND
VDD
I/O1
I/O3
1
2
3
4
U2DN2_L
U2DP2_L
5
@EMC@
1
U2DP2_L
1
@
R249
USB_HUB
I/O2
U2DP2_L
2
USB20_HUB_N2
EMC@
C272
0.1U_0402_16V4Z
D12
3
U2DN2_L
2
0_0402_5%
10
11
12
13
GND
GND
GND
GND
DC23300AG00
W=60mils
8
7
6
5
OUT
OUT
OUT
OCB
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
ACON_TARAC-9V1391
CONN@
+USB3_VCCA
U17
3
1
VBUS
DD+
GND
G1
G2
G3
G4
5
6
7
8
ACON_UARC9-4K1986
CONN@
4
DC23300AH00
@EMC@
Modify R02
+3V_HUB
2
.1U_0402_16V7K
1
C280
2
.1U_0402_16V7K
1
C283
2
.1U_0402_16V7K
1
C284
2
.1U_0402_16V7K
+3VALW
C276
C280
C283
C284
close
close
close
close
to
to
to
to
U31
U31
U31
U31
+3V_HUB
U31
2
1
@
1
R259
0_0603_5%
2
+3V_HUB
1
2
2
PSELF
100K_0402_5%
2
OVCUR2#
10K_0402_5%
2
OVCUR3#
10K_0402_5%
1
R267
2
PGANG
100K_0402_5%
5
9
14
21
27
28
18
26
RESET#
1
R261
1
R265
1
R266
USB/B
Modify R03
pin5
pin9
pin14
pin21
C281
.1U_0402_16V7K
1
C279
C282
10U_0603_6.3V6M
3
17
HUB_XIN
HUB_XOUT
10
11
PSELF
PGANG
22
23
Port2,3 is removable.
29
AVDD
AVDD
AVDD
DVDD
V5
V33
DM0
DP0
DM1
DP1
DM2
DP2
TEST/SCL
PWREN1#/SDA
DM3
DP3
RESET#
X1
X2
PSELF
PGANG
GND
DM4
DP4
OVCUR1#/SMC
OVCUR2#/SMD
OVCUR3#
OVCUR4#
RREF
GL850G-OHY31_QFN28_5X5
1
2
USB20_N1
USB20_P1
3
4
USB20_HUB_N1
USB20_HUB_P1
6
7
USB20_HUB_N2
USB20_HUB_P2
12
13
USB20_HUB_N3
USB20_HUB_P3
15
16
USB20_HUB_N4
USB20_HUB_P4
25
24
20
19
OVCUR2#
OVCUR3#
8
RREF
2
R260
3
<10>
<10>
<19>
<19>
+5VALW
JUSB2
To BT
<23>
USB_PWR_EN#
USB_PWR_EN#
USB20_HUB_N3
USB20_HUB_P3
USB20_HUB_N4
USB20_HUB_P4
<23,24>
Port2,3 is removable.
ON/OFF
ON/OFF
+3VS
1
680_0402_1%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
GND
15
16
ACES_51524-0140N-001
CONN@
R02 Modify
Modify R03
Modify R03
SA000066310, S IC GL850G-OHY32 QFN 28P USB2.0 HUB
USB HUB Port
Port1 BT
Port2 USB2.0
Port3 USB2.0
Port4 Card Reader
1
+3V_HUB
R263
10K_0402_5%
2
4
RESET#
2
1
Y5
1
HUB_XIN
C287
20P_0402_50V8
1
2
2
C285
1U_0402_6.3V6K
4
C286
20P_0402_50V8
3
1
4
2 HUB_XOUT
12MHZ_18PF_7V12000001
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
USB Conn & GL850G-OHY32
Rev
1.0
Bay Trail M LA-B511P
Thursday, March 13, 2014
Sheet
E
22
of
39
R203 1
<9> EC_KBRST#
<21,9> EC_SERIRQ
<10,21> LPC_FRAME#
<10,21> LPC_AD3
<10,21> LPC_AD2
<10,21> LPC_AD1
<10,21> LPC_AD0
RP13
1
2
3
4
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<10> LPC_CLK_EC
<18,19,21,9> PLT_RST_BUF#
<25> EC_RST#
<9> EC_SCI#
<19> WLAN_ON
2.2K_0804_8P4R_5%
+1.8VALW_EC
1
1
1
R208
R209
R211
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
EC_SMI#
EC_SCI#
EC_LID_OUT#
2
1
2
C249
@EMC@
0.01U_0402_16V7K
PLT_RST_BUF#
ESD request
2
1 EMC@
C250
0.01U_0402_16V7K
PMC_CORE_PWROK
<24>
<24>
KSI[0..7]
KSI[0..7]
KSO[0..17]
KSO[0..17]
Default unpop,
EC select LVDS EP mode to solve EMI when pop the resister.
R252 1
2 100K_0402_5%
@EMC@
LVDS_EPMODE
Charger and BATT
To SOC
<27,28>
<27,28>
<10,14,19>
<10,14,19>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_RST#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
12
13
37
20
38
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80
+1.8VALW_EC +3VALW_EC
ECAGND
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
AD
BATT_TEMP/AD0/GPIO38
AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
IMON/AD5/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
1
R199
0_0805_5%
<27>
R201
0_0603_5%
NTPM@
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
+3VALW_EC
21
23
26
27
BEEP#
BEEP#
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
SPI Flash ROM
Bus
ENBKL/AD6/GPIO40
PECI_KB930/AD7/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
<20>
CL_CMOS
63
64
65
66
75
76
C248 2
BATT_TEMP
VCIN1_BATT_DROP
ADP_I
AD_BID0
WLAN_PME#
EC_PME#
68
70
71
72
LAN_PWR_EN
EN_DFAN1
TP_EN
KBL_EN#
83
84
85
86
87
88
EC_MUTE#
USB_PWR_EN#
EC_SMB_CK3
EC_SMB_DA3
TP_CLK
TP_DATA
97
98
99
109
ENBKL
TP_PWR_EN
119
120
126
128
EC_MISO
EC_MOSI
EC_SPICLK
EC_SPICS#
73
74
89
90
91
92
93
95
121
127
<9>
1 100P_0402_50V8J
LID_SW#
R204 1
2
47K_0402_5%
WLAN_PME#
R256 1
2
4.7K_0402_5%
ECAGND
BATT_TEMP <27>
VCIN1_BATT_DROP <27>
ADP_I <27,28>
+3VS
WLAN_PME# <19>
EC_PME# <18>
LAN_PWR_EN <18>
EN_DFAN1 <21>
TP_EN <24>
KBL_EN# <24>
EC_MUTE# <20>
USB_PWR_EN# <22>
EC_SMB_CK3 <15>
EC_SMB_DA3 <15>
TP_CLK <24>
TP_DATA <24>
EC_MUTE#
R207 1
@
2
CL_CMOS
R253 2
@
1 100K_0402_5%
<33>
2
VR_HOT#
2
Board ID
Ra
<9> PBTN_OUT#
<9> EC_SLP_S4#
AD_BID0
122
123
XCLKI/GPIO5D
XCLKO/GPIO5E
1
1
R219
100K_0402_5%
Analog Board ID definition,
Please see page 3.
<19> E51TXD_P80DATA
<19> E51RXD_P80CLK
<9> PMC_CORE_PWROK
<24> PWR_SUSP_LED#
R221
20K_0402_1%
2
Rb
Modify R10
1
2
@
C252
.1U_0402_16V7K
S IC KB9022QC LQFP 128P
Part Number = SA000075S20
GPI
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
AGND/AGND
+3VALW_EC
GPIO
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
69
<29,31,32> SPOK
<21> FAN_SPEED1
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
GND/GND
GND/GND
GND/GND
GND/GND
GND0
<9> EC_SMI#
<16> TS_RST#
<16> TS_EN
<19> WL_OFF#
6
14
15
16
17
18
LVDS_EPMODE 19
25
28
29
30
31
32
34
36
11
24
35
94
113
EC_SLP_S3#
V18R
R02 Modify
R212
0_0402_5%
1
@
R02 Modify
R210
0_0402_5%
1
@
H_PROCHOT#
<8>
EC_MISO <9>
EC_MOSI <9>
EC_SPICLK <9>
EC_SPICS# <9>
EC_TP_INT#
EC_TP_INT#
BATT_BLUE_LED#
<24>
BATT_BLUE_LED#
PWR_LED
BATT_AMB_LED#
SYSON
VR_ON
R216 2
EC_ACIN
PWR_LED <24>
BATT_AMB_LED# <24>
SYSON <30>
VR_ON <33>
100
101
102
103
104
105
106
107
108
EC_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT
H_PROCHOT#_EC
MAINPWON
EC_BKOFF#
LAN_GPO
110
112
114
115
116
117
118
EC_ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
VGATE
124
+V18R
1 0_0402_5%
@
ACIN
<28,9>
<24>
C251
2
1 100P_0402_50V8J
EMC@
EC_RSMRST#
<9>
3
10K_0402_5%
2
2
H_PROCHOT#_EC
ENBKL <7>
TP_PWR_EN <24>
TXE_DBG <8>
VCIN0_PH <27>
VCIN0_PH
SPI Device Interface
GPIO
R202
0_0603_5%
TPM@
+VCC_LPC
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
PWM Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
2
@
1
2
2 100K_0402_5% EC_PME#
1
2
3
4
5
7
8
10
+1.8VALW_EC
1
C246
.1U_0402_16V7K
2
U22
1
EC_SLP_S3#
+3VALW_EC
+3VS
1
+1.8VALW
1
2
67
Modify R02
R251 2 TPM@ 1 2.2K_0402_5%
2
2
EC_VDD/AVCC
2
1
C245 @EMC@
1000P_0402_50V7K
2
1
C244 @EMC@
1000P_0402_50V7K
2
1
C243
@
.1U_0402_16V7K
+3VALW_EC
1
C242
@
.1U_0402_16V7K
Modify R03
C241
.1U_0402_16V7K
1
C240
.1U_0402_16V7K
R198
0_0805_5%
E
+EC_VCCA
L15
BLM15AG121SN1D_L0402_2P
1
2 +EC_VCCA
2
+VCC_LPC
@
D
2
+3VALW_EC
1
9
22
33
96
111
125
+3VLP
C
1
B
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
A
EC_RSMRST# <9>
EC_LID_OUT# <9>
VCIN1_PROCHOT <27>
H_PROCHOT#_EC <27>
MAINPWON <27,29>
EC_BKOFF# <16>
LAN_GPO <18>
1
2
C254
EMC@
.1U_0402_16V7K
3
For ESD request
Modify R02
EC_ON <29>
ON/OFF <22,24>
LID_SW# <19>
SUSP# <25,30,31,32>
VGATE <33>
1
@
+1.8VALW_EC
2
R220
0_0603_5%
For 9022 +V18R, +EC_VCCLPC can be
changed to 1.8V if supports 1.8V I/F
Modify R03
20mil
2
ECAGND 1
L16
BLM15AG121SN1D_L0402_2P
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
EC ENE KB9022
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
D
Thursday, March 13, 2014
Sheet
E
23
of
39
A
B
C
D
E
To TP/B Conn.
+3V_TP
2
3
EN
2
TP_PWR_EN
AP2821KTR-G1_SOT23-5
<23>
I2C2_SDA_TP
I2C2_SCL_TP
TP_EN
KSI[0..7]
KSO[0..17]
PCH_TP_INT#
27
28
@
@
1
1
1
1
@
@
@
3
1
EC_TP_INT#
EC_TP_INT#
<23>
@EMC@
C256
100P_0402_50V8J
1
2
1
2
H8
H_3P0
@EMC@
C257
100P_0402_50V8J
Q11
MESS138W-G_SOT323-3
FD1
FD3
FD4
1
@
FIDUCIAL_C40M80
Event
PCH_TP_INT#
EC_TP_INT#
S0
Interrupt
X
S3
X
Wake
<23>
1. Clamshell closed or Lid closed
2. Tablet mode for Convertible design
3. Disable TP function by hot-key
ON/OFF BTN
X
R205 1
2 4.7K_0402_5%
TP_DATA R206 1
2 4.7K_0402_5%
1
I2C2_SDA_TP
R223
1
I2C2_SCL_TP
R225
2
EC_TP_INT#
R227
2 2.2K_0402_5%
TP_CLK
@
FIDUCIAL_C40M80
H9
H_3P2N
+3V_TP
FD2
@
FIDUCIAL_C40M80
@
Modify R03
<23>
KSO[0..17]
@
H12
H_4P1
1
<9>
PCH_TP_INT#
2
KSI[0..7]
@
H11
H_4P1
1
1
R230
2.2K_0402_5%
Modify R03
Footprint -S
Default use JKB1
@
H10
H_4P1
TP_CLK
TP_DATA
SP01001ID00
SP01000IJ00
@
<10>
<10>
<23>
ACES_50578-0080N-001
CONN@
G1
G2
H6
H_3P0
SP010010M00
+1.8VS
HB_A802619-SBHR21
CONN@
E-T_6905-E26N-01R
CONN@
TP_CLK <23>
TP_DATA <23>
I2C2_SDA_TP
I2C2_SCL_TP
EC_TP_INT#
TP_EN
H5
H_3P0
1
SS
C288
4.7U_0603_6.3V6K
H4
H_3P0
1
1
1
2
GND
H3
H_3P0
1
C289
1U_0402_6.3V6K
VOUT
VIN
H2
H_3P0
1
4
H1
H_3P0
1
5
C255
.1U_0402_16V7K
1
2
TP_CLK
TP_DATA
@
FIDUCIAL_C40M80
1
G1
G2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
D
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
+3V_TP
1
2
3
4
5
6
7
8
9
10
1
JKB2
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
GND
GND
1
G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
U30
2
1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
Modify R03
0_0603_5%
JTP1
KB_pitch 0.8
JKB1
2
2
KB_pitch 1.0
@
1
1
R264
1
+3VALW
KB Conn.
@
2
2 2.2K_0402_5%
1 10K_0402_5%
X
LED
KB BackLight Conn.
Modify R03
+3VALW
LED1
<23>
<23>
2
+3VLP
+5VS
R237
100K_0402_5%
3
1
D
+5VS_BL
+5VALW
1
SW1 @
TJE-532QR5_6P
1
3
BL@
Q12
DMG2301U-7_SOT23-3
S
3
ON/OFF
ON/OFF
1
2 KBL_EN_R
R235 BL@
100K_0402_5%
<22,23>
5
6
4
1
@
2
@
BATT_AMB_LED#
4
3
2
1
G2
G1
BATT_AMB_LED#
3
B
A
2
1
R231
2
100_0402_5%
4
1
R232
2
470_0402_5%
2
1
R233
2
100_0402_5%
4
1
R234
2
470_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE
LED2
CONN@
JBL1
4
3
2
1
1
6
5
<23>
PWR_SUSP_LED#
PWR_LED#
1
PWR_SUSP_LED#
3
B
A
3
1
ACES_50504-0040N-001
SP01000Z300
Modify R03
Footprint -S
LTST-C295TBKF-CA_AMBER-BLUE
Need check CIS Symbol
1
1
2
1
PWR_LED#
1
2
KBL_EN#
R236
0_0402_5%
SW2 @
TJE-532QR5_6P
1
3
C259
.1U_0402_16V7K
<23>
Modify R03
2
G
2
BATT_BLUE_LED#
BATT_BLUE_LED#
4
D
2
PWR_LED
1
Q13
2N7002K_SOT23-3
G
2
5
6
<23>
JP19@
JUMP_43X39
2
1
2
JP20@
JUMP_43X39
2
1
2
JP21@
JUMP_43X39
2
1
2
JP22@
JUMP_43X39
2
1
2
3
S
1
JP23@
JUMP_43X39
2
1
2
1
R238
100K_0402_5%
GND
GND
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
KB/TP/LED/Screw Hole
Rev
1.0
Bay Trail M LA-B511P
Sheet
Thursday, March 13, 2014
E
24
of
39
A
B
C
D
VIH=1.2~5.5V
3.3V@100k/0.1uF=3.538ms
3.3V@120k/0.1uF=4.272ms
1
2
SUSP#
+1.0VALW TO +1.0VS
1
0708:Change to SB00000PZ00 / need apply footprint
+1.0VALW
U25
ME4856_SO8
1
2
3
5VS_ON
+5VALW
2
4
5
6
7
ON1
VBIAS
VOUT1
VOUT1
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
14
13
+3VS_OUT
12
2
C260
1 330P_0402_50V7K
2
1
+3VS
1
JUMP_43X118
11
10
330P_0402_50V7K
C262
+5VS_OUT
9
8
15
JP7 JP@
+5VS
JUMP_43X118
2
VIH=1.2~5.5V
3.3V@82k/0.1uF=3.042ms
3.3V@47k/0.1uF=1.893ms
1
+1.0VS_R
2
3
1.8VS_ON
3
SUSP
G
Q14 @
2N7002K_SOT23-3
S
2
U26
1
2
+1.8VALW
R243
82K_0402_5%
2
1
SUSP#
D
C268
.1U_0402_16V7K
1
C267
.1U_0402_16V7K
2
1
R244
47K_0402_5%
1
C270
.1U_0402_16V7K
0701 update
S
3
+5VALW
VIN1
VIN1
Modify R02
1
1
1
D
G
Q15
2N7002K_SOT23-3
1
3
1
1.0VS_GATE
2
3VS_ON
Rise Time:
3.3V@330pF = 889.68us
5.0V@330pF = 1348us
APE8990GN3B DFN 14P DUAL LOAD SW
Modify R03
SUSP
1
2
+3VALW
JP6 JP@
C265
4.7U_0603_6.3V6K
@
R241
470_0603_5%
2
1
R242
1K_0402_5%
2
2
4
1
+5VALW
+1.0VS
8
7
6
5
2
C264
4.7U_0603_6.3V6K
0701 update
U24
R239
100K_0402_5%
1
2
C261
.1U_0402_16V7K
2
R240
120K_0402_5%
1
C263
.1U_0402_16V7K
E
Modify R03
2
+5VALW
1.35VS_ON
2
+1.35V
4
5
6
7
JP8 JP@
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
14
13
+1.8VS_OUT
12
2
C266
1 330P_0402_50V7K
2
1
+1.8VS
Rise Time:
1.8V@330pF = 485.28us
1.35V@330pF = 363.96us
JUMP_43X79
11
10
330P_0402_50V7K
C269
+1.35VS_OUT
9
8
15
2
JP9 JP@
+1.35VS
JUMP_43X79
APE8990GN3B DFN 14P DUAL LOAD SW
Modify R02
Reset Button / Battery discharge screw hole
Follow VA52_HB design
SW3
1
Reset Button
3
2
BI_GATE
BI_GATE
<27>
+5VALW
3
2
SKPMAME010_2P
1
R245
100K_0402_5%
+3VLP
SUSP
SUSP
2
1
<30>
D
R247
10K_0402_5%
<23>
<23,30,31,32>
2
SUSP#
1
EC_RST#
G
G
3
1
S
5
G
BI_GATE
1
D
BI_GATE PH to +RTCVCC at PWR side
S
4
Q17A
DMN65D8LDW-7 2N SOT363-6
Q17B
DMN65D8LDW-7 2N SOT363-6
2
2
D
BI_GATE#
Q16
2N7002K_SOT23-3
3
6
1
S
R246
10K_0402_5%
C271
0.1U_0402_16V4Z
2
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/04/12
2014/04/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
DC INTERFACE
Rev
1.0
Bay Trail M LA-B511P
Thursday, March 13, 2014
Sheet
E
25
of
39
A
B
1
@
PJP101
ACES_50305-00441-001_4P
1
1
1
DC_IN_S1
D
VIN
EMI@ PL101
HCB2012KF-121T50_0805
1
2
EMI@ PC102
100P_0603_50V8
2
2
1
2
3
4
GND
GND
C
EMI@ PC103
1000P_0603_50V7K
2
2
3
3
@PR111
@
PR111
0_0402_5%
1
2
+3VLP
-
PBJ101 @
2
+
1
PR112
560_0603_5%
1
2
PR113
560_0603_5%
1
2
+CHGRTC
+RTCBATT
ML1220T13RE
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
Deciphered Date
2014/09/25
Title
DCIN / RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
A
B
C
Thursday, March 13, 2014
D
Sheet
26
of
39
A
B
C
D
Ezel battery conn
1
@ PR204
10K_0402_1%
BI
@ PU201
1
@ PR206
100K_0402_1%
VCC TMSNS1
MAINPWON
3
+RTCVCC
OT1 TMSNS2
4
OT2 RHYST2
8
7
2
6
1
@ PR207
47K_0402_1%
5
@ PH201
S THERM_ 100K 1% 0402 B25/50 4250K
G718TM1U_SOT23-8
2
BATT+
<45,47>
GND RHYST1
1
1
EMI@ PC201
1000P_0402_50V7K
BI_GATE
1
BI_GATE
<25>
D
3
PR212
100K_0402_1%
2
2
2
2
@ PR205
10K_0402_1%
2
PR211
0_0402_5%
1
2
Conn@
EMI@ PL201
HCB2012KF-121T50_0805
1
2
1
@ PC202
0.1U_0603_25V7K
BATT_TEMP <23>
1
ACES_50458-00801-001
+3VLP
1
PR201
6.49K_0402_1%
1
2
PR210
1K_0402_1%
<23,28>
1
1
1
EC_SMB_CK1
2
+3VLP
<23,28>
2
EC_SMDA
EC_SMCK
TH
BI_1
BATT_S1
PR209 100_0402_1%
1
2
1
2
PR208 100_0402_1%
2
1
EC_SMB_DA1
PJP201
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
GND 10
GND
S
2
G
PQ205
2N7002KW_SOT323-3
For KB9012
OTP
2
℃
56℃
92
For KB9022
OTP
1.2V
1.0V
1.2V
1.0V
Need confirm the setting
For KB9022
sense 20mΩ
Active
2
Recovery
PR216 22.6K ohm32.4K ohm
42.8W,0.43V 34.4W,0.43V
40W
PR227 26.1K ohm30.9K ohm
+EC_VCCA
ADP_I <23,28>
3
1
1
3
PR216
16.9K_0402_1%
2
2
PR202
10K_0402_1%
<23>
VCIN0_PH
B+
@
PR227
26.1K_0402_1%
1
2
MAINPWON
VCIN1_PROCHOT <23>
@ PR223
162K_0402_1%
1
2
@9022@
PR230
80.6K_0402_1%
H_PROCHOT#_EC <23>
B value:4250K±1%
1
VCIN1_BATT_DROP <23>
PH202
S THERM_ 100K 1% 0402 B25/50 4250K
1
@9022@ PC203
2
2
1
@9022@ PR231
0_0402_5%
1
2
2
1
<23,29>
PR203
44.2K_0402_1%
PR229
2
@9022@
1
0.1U_0402_25V6
2
10K_0402_1%
4
4
<23> ECAGND
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2013/9/25
2014/09/25
Title
BATTERY CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Bay Trail M LA-B511P
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Thursday, March 13, 2014
D
Sheet
27
Rev
1.0
of
39
A
B
C
D
PQ301
1
Protection for reverse input
3
2
G
B+
S 2N7002KW _SOT323-3
PR302
SRN
SCL
PC318
0.1U_0603_16V7K
10
9
8
7
ACIN
+3VALW
Max.
18.12V
17.70V
PC322
100P_0402_50V8J
2
1
L-->H
H-->L
Typ
17.63V
17.22V
PR319
66.5K_0402_1%
2
1
Vin Dectector
Min.
17.16V
16.76V
@ PR320
0_0402_5%
1
2
1
2
1
2
PR316
316K_0402_1%
EC_SMB_CK1
<23,27>
EC_SMB_DA1
<23,27>
ADP_I
<23,27>
2
1
VILIM = 20*ILIM*Rsr
ILIM = 3.3*100/(100+316)/20/0.01
= 3.966 A
PC320
0.01U_0402_25V7K
2
1
PR317
100K_0402_1%
BQ24725A_ILIM
BQ24725A_IOUT
PR318
422K_0402_1%
1
2
PC321
0.22U_0402_16V7K
2
1
VIN
BQ24725A_ACDET
3
@ PC323
100P_0402_50V8J
1
1
2
1
2
CSON1
1
CSOP1
1
PC315
10U_0805_25V6K
BQ24725A_BATDRV
PC314
10U_0805_25V6K
11
ILIM
BATDRV
SDA
ACOK
AON7408L_DFN8-5
1
12
PR313
10_0603_1%
2 CSOP1
SRP1
PR314
6.8_0603_1%
2 CSON1
SRN1
13
2
ACDRV
6
<23,9>
PR315
5
IOUT
+3VLP
2
100K_0402_1%
SRP
ACDET
BQ24725A_ACDRV 4
1
CMSRC
2
14
3
2
1
GND
BQ24725ARGRR_QFN20_3P5X3P5
1
ACP
2
2
BQ24725A_CMSRC 3
2
1
4
DL_CHG
3
PC317
0.1U_0402_25V6
5
2
PQ306
2
BATT+
PL302
PR311
10UH_3.5A_20%_7X7X3_M
0.01_1206_1%
1
2 CHG 1
4
PC316
0.1U_0402_25V6
3
2
1
AON7408L_DFN8-5
BQ24725A_LX
15
PC307
0.01U_0402_50V7K
2
1
2
2
PC313
1U_0603_25V6K
LODRV
Power loss: 0.32W for 3.5A
CSR rating: 1W
VSRP-VSRN spec < 81.28mV
7X7X3
Isat: 3.8A
4
2
ACN
2BQ24725A_BATDRV_1
PR305
4.12K_0603_1%
PQ305
PR308
0_0603_5%
1
2
DH_CHG
1
1
5
1
2
BQ24725A_REGN
PD302
RB751V-40_SOD323-2
16
PR307
2.2_0603_5%
1
BQ24725A_BST2
DH_CHG
18
17
BTST
PAD
VF = 0.37V
REGN
1
HIDRV
PU301
19
1U_0603_25V6K
BQ24725A_BATDRV
Rds(on) = 30mohm max
Vgs = 20V
Vds = 30V
ID = 7A (Ta=70C)
PC311
0.047U_0402_25V7K
1
2
1
2
3
PQ304
AO4406AL_SO8
@EMI@ PC319 @EMI@ PR312
680P_0402_50V7K 4.7_1206_5%
2
PR306
10_1206_1%
BQ24725A_LX
2
PD301
BAS40CW _SOT323-3
PC312
1
2
21
VF = 0.5V
PHASE
1
2
PR310
4.12K_0603_1%
1
PC309
0.1U_0402_25V6
BQ24725A_ACN
PR309
4.12K_0603_1%
2
BQ24725A_ACP
2
2
1
1
1
2
PC308
0.1U_0402_25V6
BQ24725A_ACDRV_1
8
7
6
5
@EMI@ PC306
0.1U_0402_25V6
VIN
1
PQ303
AO4406AL_SO8
2
Isat: 4A
DCR: 27mohm
EMI@ PC305
2200P_0402_25V7K
3
1
2
1
CHG_B+
EMI@ PL301
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
PC304
10U_0805_25V6K
PR303
0.02_1206_1%
4
1
1
2
4
8
7
6
5
3
1
PC302
0.1U_0402_25V6
2
1
@ PR304
0_0402_5%
4
PQ302
AON6414AL_DFN8-5
2
1
PC301
2200P_0402_50V7K
5
2
P2
1
2
3
2
P1
1
2
3
PC303
10U_0805_25V6K
VIN
Rds(on) = 35mohm max
Vgs = 20V
Vds = 30V
ID = 7.7A (Ta=70C)
max Power loss 0.22W for 90W;0.12W for 65W system
CSR rating: 1W
VACP-VACN spec < 80.64mV
4
Rds(on) typ = 35mohm max
Vgs = 20V
Vds = 30V
ID = 7.7A (Ta=70C)
3M_0402_5%
Need check the SOA for inrush
1 1
1M_0402_5%
2
BQ24725A_VCC2
1
20
2
VCC
1
Vgs = 20V
Vds = 60V
Id = 250mA
PC310
0.1U_0402_25V6
PR301
1
D
**Design Notes**
#For 65 /90W system, 3S1P/3S2P battery
Maximum Charging current 3.5A
Maximum Battery discharge power 55W.
#Register Setting
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
#Circuit Design
1. ACOK,ILIM pull high voltage need base on 3/5V enable control
2. Use 10X10 choke and 3X3 H/L Side MOSFET
Charge current 3.5A
Power loss : 1.82W
Power density : 0.81 (15X15)
3. If use 4S per cell 4.35V battery, need additional circuit
for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
with PR222 for ACDET setting)
4. PC223 0.22U can't be changed. (Wrong adapter concern)
5. For the design, need double confirm PQ202,PQ203,PQ204 rating
#Protect function
1. ACOVP : ACDET voltage > 3.14V
2. Charger timeout : No communication within 175s(default)
3. ACOC : 3.33 X Input current DAC setting(default)
4. CHGOCP : 3/4.5/6A based on current current setting
5. BATOVP : 103-106%
6. BATLOWV : 2.5V
7. TSHUT : 155C
8. IFAULT HI : 750mV (default)
9. IFAULT LOW : 150mV (default)
3
Close EC chip
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
4
2013/9/25
Deciphered Date
2014/09/25
Title
Charger
Bay Trail M LA-B511P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Thursday, March 13, 2014
D
Sheet
28
Rev
1.0
of
39
A
B
C
D
E
1
1
EN1 and EN2 dont't floating
PR402
499K_0402_1%
1
2
PU401
7
8
PC406
10U_0805_25V6K
2
1
3V_VIN
EN2
IN
EN1
FB
BS
1
3V5V_EN
3
6
1
BST_3V
3V_FB
PR401
2
1_0603_5%
PC402
0.022U_0402_25V7K
1
2
1
PL402
PR412
100K_0402_5%
2
3.3V LDO 150mA~300mA
SPOK
PC410
22U_0603_6.3V6M
PC409
22U_0603_6.3V6M
2
1
1
2
PC408
22U_0603_6.3V6M
2
1
1
2
PC411
4.7U_0603_6.3V6M
+3VALWP
@ PC407
22U_0603_6.3V6M
2
1
+3VLP
PR405
1
5
1 3V_SN
2
LDO
2
1.5UH_PCMB053T-1R5MS_6A_20%
680P_0603_50V7K 4.7_1206_5%
PG
@EMI@
OUT
PC412
2
2
GND
1
LX_3V
4
@EMI@
9
10
SY8208BQNC_QFN10_3X3
<23,31,32>
B+
0.1U_0603_25V7K
LX
@
+3VALWP
2
PR403
1K_0402_5%
1
2
PC403
2
1
PC405
10U_0805_25V6K
2
1
EMI@ PC404
2200P_0402_50V7K
2
1
EMI@ PL401
HCB2012KF-121T50_0805
1
2
@EMI@ PC401
0.1U_0402_25V6
2
1
B+
PR404
150K_0402_1%
2
1
ENLDO_3V5V
2
Vout is 3.234V~3.366V
TDC=6A
@ PJ401
1
+3VALWP
1
2
2
+3VALW
JUMP_43X118
B+
EN1 and EN2 dont't floating
EMI@ PL403
HCB2012KF-121T50_0805
1
2
5V_VIN
@ PJ402
1
@EMI@ PC418
0.1U_0402_25V6
2
1
8
FB
<23,27> MAINPWON
3
5V_FB
6
BST_5V
@ PR407
0_0603_5%
1
2
PC416
0.1U_0603_25V7K
1
2
1
2
2
+5VALW
JUMP_43X118
Vout is 4.998V~5.202V
TDC=6A
PC423
22U_0603_6.3V6M
PC422
22U_0603_6.3V6M
2
1
PC421
22U_0603_6.3V6M
2
1
1
PC420
22U_0603_6.3V6M
2
1
VL
+5VALWP
2
7
680P_0603_50V7K 4.7_1206_5%
LDO
1
PG
SY8208CQNC_QFN10_3X3
2
1.5UH_PCMB053T-1R5MS_6A_20%
1 5V_SN
2
OUT
1
LX_5V
4
2
VCC
10
@EMI@ PC425 @EMI@ PR408
LX
1
2
GND
PC424
4.7U_0603_6.3V6M
5
PR409
2.2K_0402_5%
1
2
1
3V5V_EN
PC413
PR406
6800P_0402_25V7K 1K_0402_5%
1
2
1
2
PL404
9
SPOK
PC419
4.7U_0603_6.3V6M
1
2
<23> EC_ON
EN
BS
VCC_3V
3
IN
1
2
@
EMI@ PC417
2200P_0402_50V7K
2
1
PC415
10U_0805_25V6K
2
1
PC414
10U_0805_25V6K
2
1
+5VALWP
PU402
3
5V LDO 150mA~300mA
@PR410
@
PR410
2
0_0402_5%
1
2
PC426
4.7U_0402_6.3V6M
2
1
PR411
1M_0402_1%
3V5V_EN
EC VDD0 is +3VL, PC426 UNPOP
EC VDD0 is +3VALW, PC426 POP
VC 0/1 controlled by SW method so pop.
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
2014/09/25
Deciphered Date
Title
3VALW/5VALW
Bay Trail M LA-B511P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Sheet
Thursday, March 13, 2014
E
29
Rev
1.0
of
39
5
4
3
2
1
D
D
1.35V_B+
PR501
2.2_0603_5%
1
2
BOOT_1.35V
2
1
PC507
10U_0805_6.3V6K
VTT
C
1
2
3
4
VTTREF_1.35V
1
VTTREF
2
20
19
VLDOIN
BOOT
VDDP
2
FB
6
S3
7
S5
TON
EN_0.675VSP
PR507
887K_0402_1%
1
2
FB_1.35V
PR506
8.06K_0402_1%
2
1
+1.35VP
B
PR509
680K_0402_1%
1
2
SYSON
PC510
0.033U_0402_16V7K
PR508
10K_0402_1%
2
<23>
+1.35VP
1
1.35V_B+
5
2
DDR_PW ROK
MOSFET: 3x3 DFN
H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
8
<6>
VDDQ
9
1
10
2
+5VALW
VDD
EN_1.35V
1
11
PR505 100K_0402_5%
L/S Rds(on): 9.9mohm(Typ), 13mohm(Max)
Idsm: 13.5A@Ta=25C, 11A@Ta=70C
GND
RT8207MZQW _W QFN20_3X3
TON_1.35V
1
2
3
VDD_1.35V
+1.35VP
AON7506_DFN33-8-5
18
1
1
2
3
PC513
1U_0603_10V6K
PQ502
VTTSNS
21
@ PC514
0.1U_0402_16V7K
Choke: 7x7x3
Rdc=8.3mohm(Typ), 10mohm(Max)
Note: S3 - sleep ; S5 - power off
Switching Frequency: 285kHz
Ipeak=10A
Iocp~13A
OVP: 110%~120%
VFB=0.75V, Vout=1.515V
MOSFET footprint: SIS412DN
1
<23,25,31,32> SUSP#
PR510
200K_0402_1%
1
2
<25> SUSP
D
S
2
G
PQ503
2N7002KW _SOT323-3
PC515
0.1U_0402_16V7K
2
VTTREF_1.35V
off
on
on
4
CS
PAD
2
+0.675VSP
off
off
on
@EMI@ PC512
680P_0402_50V7K
12
PU501
VTTGND
PGND
1
Level
L
L
H
+5VALW
PR504
5.1_0603_5%
1
2
13
LGATE
3
Co-Lay
5
1
2
@EMI@ PR503
4.7_1206_5%
1 2
+
B
Mode
S5
S3
S0
PR502
9.1K_0402_1%
1
2 CS_1.35V
PC508
1U_0603_10V6K
1
2
UGATE
15
17
16
DL_1.35V
PHASE
4
2
ESR=15m ohm
1
COMMON PART
H=4.5
PC509
330U_2.5V_ESR17M_6.3X4.5
SF000002Z00
PC506
10U_0805_6.3V6K
SW _1.35V
14
+1.35VP
+0.675VSP
1
2
PC501
0.1U_0603_25V7K
5
PQ501
AON7408L_DFN8-5
PL502
1UH_11A_20%_7X7X3_M
1
2
+1.35VP
DH_1.35V
C
COMMON PART
0.675Volt +/- 5%
TDC 0.84A
Peak Current 1.2A
1
1
2
PC505
10U_0805_25V6K
1
2
PC504
10U_0805_25V6K
1
2
EMI@ PC503
2200P_0402_50V7K
1
2
@EMI@ PC502
0.1U_0402_25V6
BST_1.35V
PGOOD
B+
Pin19 need pull separate from +1.35VP.
If you have +1.35V and +0.675V sequence question,
you can change from +1.35VP to +1.35VS.
EMI@ PL501
HCB2012KF-121T50_0805
1
2
@ PJ503
1
+0.675VSP
1
2
2
+0.675VS
JUMP_43X39
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
2013/9/25
Deciphered Date
2014/09/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
A
2
Title
Size
Custom
Date:
1.35VP/0.675VSP
Bay Trail M LA-B511P
Document Number
Thursday, March 13, 2014
Sheet
1
30
Rev
1.0
of
39
5
4
3
2
1
D
D
EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
PR602
10K_0402_1%
1
2
SPOK
SPOK
<23,29,32>
C
1
1
C
2
2
PR603
1M_0402_1%
PC602
0.1U_0402_16V7K
SY8208DQNC_QFN10_3X3
FB = 0.6V
1
2
PC612
22U_0603_6.3V6M
1
2
1
2
1
PR609
Rdown
20K_0402_1%
2
2
2
@ PR607
0_0402_5%
+3VALW
PC611
22U_0603_6.3V6M
LDO_3V
PC610
22U_0603_6.3V6M
5
2
Rup
7
PC609
22U_0603_6.3V6M
LDO
2
PG
1
BYP
1
PR608
10K_0402_5%
ILMT
2
+1.0V_PGOOD 2
PC614
4.7U_0603_6.3V6K
2
+1.0VALWP
1
COMMON PART
4
1
10 LX_1.0V
LX
FB
1
PL602
1.5UH_PCMC063T-1R5MN_9A_20%
1
2
2
GND
TDC 8A
PC601
0.1U_0603_25V7K
1
2
PC608
330P_0402_50V7K
9
@ PR601
0_0603_5%
2
BST_1.0V1
PR606
13.7K_0402_1%
6
1
1
1
EN
BS
ILMT_1.0V 3
+3VALW
ILMT_1.0V
10U_0805_25V6K
PC607
2
1
@
IN
PC613
4.7U_0603_6.3V6K
@ PR605
0_0402_5%
B+_1.0V 8
10U_0805_25V6K
PC604
2
1
1
LDO_3V
PU601
@EMI@
PC606
0.1U_0402_25V6
2
1
EMI@
PC605
2200P_0402_50V7K
2
1
B+
2
@EMI@ PR604
@EMI@ PC603
4.7_1206_5%
680P_0603_50V7K
1
2SNB_1.0V 1
2
EMI@ PL601
HCB2012KF-121T50_0805
1
2
Pin 7 BYP is for CS.
Common NB can delete
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
B
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.011V
+1.0VALWP
+3VALW and PC614
B
1
1
PJ601
2
2
JUMP_43X118
+3VS
PR610
2.55K_0402_1%
1
2
SUSP#
<23,25,30,32>
PU602
PL603
1UH_2.8A_30%_4X4X2_F
1
2
+1.05VSP
COMMON PART
SY8003DFC_DFN8_2X2
PR614
15K_0402_1%
Rup
FB_1.05V
2
Note:Iload(max)=3A
PR615
20K_0402_1%
@ PJ603
+1.05VSP
1
1
2
2
+1.05VS
A
JUMP_43X79
Rdown
2
1
FB=0.6V
@EMI@ PC620
680P_0402_50V7K
1
A
1
5
LX_1.05V
2
NC
6
PC619
22U_0603_6.3V6M
PGND
7
PC618
22U_0603_6.3V6M
LX
1
EN
IN
2
4
PG
2
PC616
22U_0805_6.3VAM
FB
PC617
68P_0402_50V8J
2
1
JUMP_43X79
3
1
2
1
2
2
1
Note:Iload(max)=2.5A
2
@ PJ602
1
9
8
1
2
+3VALW
PGND
SGND
@EMI@ PR613
4.7_0603_5%
1
@ PR612
1M_0402_5%
2
2
@ PR611
100K_0402_5%
1
PC615
0.1U_0402_16V7K
2
1
1
+1.05VSP_ON
+1.0VALW
@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
Deciphered Date
2014/09/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
Date:
5
4
3
2
1.05VS/1.0VALW
Bay Trail M LA-B511P
Document Number
Thursday, March 13, 2014
Sheet
1
31
Rev
1.0
of
39
5
4
3
2
1
2
@ PJ701
JUMP_43X79
2
1
1
+3VALW
Ultra Low Dropout 0.23V(typical) at 3A Output Current
D
@ PC702
1U_0402_6.3V6K
2
1
D
1
+1.5VSP
@
1
PJ702
1
2
2
+1.5VS
JUMP_43X79
PC704
0.01U_0402_25V7K
PC705
22U_0603_6.3V6M
2
1
1
Rup
2
@ PR702
100K_0402_5%
@ PR704
22K_0402_5%
2
2
+1.5VSP
PR703
20K_0402_1%
1
1
1
2
2
PC701
0.15U_0402_10V6K
1
+3VS
GND
PR701
51K_0402_1%
1
2
1
SUSP#
SUSP#
1
<23,25,30,31>
PU701
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
8
7 EN
2
POK
FB
2
PC703
4.7U_0805_6.3V6K
PR705
22.6K_0402_1%
2
Rdown
C
C
+3VALW
1
Vout=0.8V* (1+Rup/Rdown)=1.507V
2
1
Ultra Low Dropout 0.23V(typical) at 3A Output Current
@ PC706
1U_0402_6.3V6K
+1.8VALWP
+1.8VALWP
@
1
1
B
PJ704
1
2
2
+1.8VALW
JUMP_43X79
1
PC709
0.01U_0402_25V7K
PC710
22U_0603_6.3V6M
1
2
2
PR708
20K_0402_1%
1
Rup
2
2
@ PR707
100K_0402_5%
PU702
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
8
7 EN
2
POK
FB
GND
1
+3VS
PC708
0.1U_0402_16V7K
2
2
@ PR709
22K_0402_5%
1
SPOK
PR706
20K_0402_1%
1
2
1
<23,29,31>
2
B
1
PC707
4.7U_0805_6.3V6K
1
2
1
2
@ PJ703
JUMP_43X79
PR710
15.8K_0402_1%
2
Rdown
Vout=0.8V* (1+Rup/Rdown)=1.81V
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
2014/09/25
Deciphered Date
Title
1.5VSP/1.8VALWP
Bay Trail M LA-B511P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
32
Rev
1.0
of
39
C
D
@ PC802
1000P_0402_50V7K
2
+CPU_B+
5
1
PC808
470P_0402_50V7K
1
2
1
2
PR803
PC809
499_0402_1%
1000P_0402_50V7K
2
1
2
1
2
1
+SOC_VNN
PL802
0.36UH_PDME064T-R36MS_24A_20%
PHASEA_GFX
1
PR815
1_0402_5%
2
PR814
3.65K_0603_1%
VSUMG-
Rds=13.5mΩ(Typ)
16.5mΩ(Max)
3
1
1
1 2
3
2
1
2
1
1.91K_0402_1%
2
2
4
PQ804
AON6554_DFN5X6-8-5
LGA_GFX
PC814
1000P_0402_50V7K
4
2
2
PC813
2 1
2
BOOTA_GFX 1
PR812
2.2_0603_5% 0.1U_0603_25V7K
1
VSUMG+
PR807
2.05K_0402_1%
PR808
2K_0402_1%
PR816
0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A
PQ803
AON7518_DFN8-5
2
1
PR809
21K_0402_1%
PC812
0.047U_0402_25V7K
2
1
PC811
0.1U_0402_16V7K
2
1
PR811
11K_0402_1%
2
1
+3VALWP
UGA_GFX-1 4
@EMI@ PC815
@EMI@ PR813
680P_0402_50V7K
4.7_1206_5%
1
PR806
137K_0402_1%
PR804
0_0603_5%
1
2
1
OCP setting=21A
3
2
1
PR805
324_0402_1%
1
2
UGA_GFX
5
1
PC807
120P_0402_50V8
1
2
PH802
10K_0402_1%_B25/50 3370K
PR810
2.61K_0402_1%
2
1
2
PC810
0.1U_0402_16V7K
2
1
Design Note
This circuit is for ULV 1+1 17W.
CPU: IccMax=33A, TDC=16A(TDP NOM)
Loadline: -2.9 m V/A
Output Cap. follow Intel PDDG
VSUMG+
330uF/9m*3, 22uF_0805*12, 2.2uF_0402*16
GFX(GT2): IccMax=33A, TDC=21.5A
Loadline: -3.9 m V/A
Output Cap. follow Intel PDDG
330uF/9m*2, 22uF_0805*6, 10uF_0603*6 , 1uF_0402*11
2
1
COMMON PART
VSUMG-
1
1 2
PR802
2K_0402_1%
2
1
PC804
6800P_0402_25V7K
Close GFX choke
2
1
PC805
10U_0805_25V6K
2
PC803
0.01UF_0402_25V7K
2
VGFX_VSNS
1
<11>
E
Layout Note
Reduce Acoustic Noise
1. The AL bulk capacitor of B+ should be very
close to CPU_CORE MOSFET.
2. Input ceramic caps must place on symmetry
same location on top side and bottom side.
PC806
10U_0805_25V6K
B
1
A
BOOTA_GFX
UGA_GFX
PHASEA_GFX
2
1
2
1
1
BOOT_CPU
1
+
2@
<23>
PR827
1.91K_0402_1%
+CPU_B+
5
COMMON PART
Close CPU L/S MOS
OCP setting=18A
4
PQ801
AON7518_DFN8-5
PL803
0.36UH_PDME064T-R36MS_24A_20%
3
2
1
4
A
1
2
COMMON PART
4
2
3
2
1
PR832
3.65K_0603_1%
PR833
1_0402_5%
Cn = L/((Rntcnet*Rsum)/(Rntcnet+Rsum))*DCR)
If Cn is correctly selected, when the load current has a
square change, the output voltage also has a square response.
Issued Date
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
Deciphered Date
2014/09/25
Title
CPU_CORE/GFX_CORE
Bay Trail M LA-B511P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
B
+SOC_VCC
PC833
0.1U_0402_16V7K
2
1
VSUM+
1
2
1
2
Rds=13.5mΩ(Typ)
16.5mΩ(Max)
@EMI@ PC825
@EMI@ PR831
680P_0402_50V7K 4.7_1206_5%
4
PQ802
AON6554_DFN5X6-8-5
3
2
1
PH804
10K_0402_1%_B25/50 3370K
2
5
PR836
2.61K_0402_1%
2
LG1_CPU
VSUM-
@ PC834
330P_0402_50V7K
1
2
PC835
0.01UF_0402_25V7K
PC824
2 1
2
PR830
2.2_0603_5% 0.1U_0603_25V7K
BOOT_CPU 1
1
1
11K_0402_1%
2
PR840
1
2
PC830
0.1U_0402_16V7K
2
1
1
1
Layout Note
<11> VCORE_VSNS
SVID routing
1. Alert# signal must be routed between
the Clock and Date lines to reduce the cross
talk between them. Signal order arrangement:
mobile order is Clock-Alert-Date.
<11> VCORE_GSNS
2. SVID spacing requirement is 18mils(0.475mm).
3. Maximum total microstrip routing length of
each SVID signal must not exceed 6000mils(152.4mm).
4. The SVID bus must be ground reference, It cannot be
referenced to input (Vbat or 12V) power plans as they can
couple noise into the SVID bus as power states change.
5. Avoid routing under noisy circuit, e.g. switch node ,
Gate driver, B+, Vin, high speed signal.
6. When SVID signal changes Layer, GND return path
may be changed also. We need add GND via for GND
reference.
PHASE1_CPU
Close CPU choke
1
1
PR842
137K_0402_1%
PC829
0.047U_0402_25V7K
PC831
1000P_0402_50V7K
2
1
2
PR839
280_0402_1%
PC828
120P_0402_50V8
1
2
2
PR841
1.78K_0402_1%
1
2
PC832
PR838
6800P_0402_25V7K
2K_0402_1%
2
1
2
1
PC827
470P_0402_50V7K
1
2
1
2
PR837
499_0402_1%
VSUM+
PR835
66.5K_0402_1%
1
2
3
0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A
1
UG1_CPU-1
2
PR828
0_0603_5%
1
2
VSUM-
UG1_CPU
VDD source use +5VS and PGOOD source use +3VS
Please confirm power on and down sequence,
make sure VGATE after CPU_CORE on.
PR834
2K_0402_1%
1
2
B+
Height 8 mm
100u_SF000000I80
Height 6 mm
68u_SF000000W00
+1.8VALW
2
3
PC826
680P_0402_50V7K
1
2
PC822
33U_25V_M
1
2
1
2
@EMI@ PC823
0.1U_0402_25V6
1
1
2
UG1_CPU
2
PHASE1_CPU
17
EMI@ PL801
HCB2012KF-121T50_0805
1
2
PC819
10U_0805_25V6K
LG1_CPU
18
+CPU_B+
2
20
VGATE
PR826
27.4K_0402_1%
PH801
470K_0402_5%_B25/50 4700K
2
21
19
2
EMI@ PC821
2200P_0402_50V7K
BOOT1
UGATE1
22
@ PR819 PR821
@PR819
0_0402_5% 1_0402_5%
16
15
9
ISEN2
PGOOD
PHASE1
COMP
LGATE1
NTC
FB
VR_HOT#
23
PR817 and PR826
27.4K ohm for 100 degree
61.9K ohm for 110 degree
PC817
1U_0402_6.3V6K
2
1
VDD
PWM2
PC816
1U_0402_6.3V6K
2
1
25
UGATEG
27
28
29
30
31
32
33
26
BOOTG
PGOODG
COMPG
FBG
RTNG
ISUMNG
ISUMPG
SDA
14
1
PR829
3.83K_0402_1%
1
PR825
69.8_0402_1%
@PC801
@
PC801
0.1U_0402_16V7K
2
2
0_0402_5%
8
ALERT#
ISL95833BHRTZ-T_TQFN32_4X4
24
1
1
1
+1.0VS
7
2
+5VALW
2
2
@
2
1
PR801
499_0402_1%
1
2
@ PC818
47P_0402_50V8J
1
PR824
69.8_0402_1%
NTC
@PR823
@
PR823
1
VCCP
13
VR_HOT#
LGATEG
SCLK
RTN
6
<23>
For VR_HOT#, already
pull high at power side.
VR_ON
12
VR_SVID_DATA
1 PR843 2
3
20_0402_1%
SVID_ALERT# 4
PR844
16.9_0402_1%
1
2
5
SVID_DATA
PHASEG
ISUMN
VR_SVID_ALERT#
<9>
2
470K_0402_5%_B25/50 4700K
0_0402_5%
NTCG
11
<9>
PAD
COMMON PART
2
VR_ON
VR_SVID_CLK
1
ISUMP
@PR820
@
PR820
1
<23>
<9>
2
ISEN1
1
PR818
3.83K_0402_1%
1
2
10
2
+5VALW
LGA_GFX
PU801
PR817
27.4K_0402_1%
1
2
NTCG_1
PH803
PC820
10U_0805_25V6K
Close GFX L/S MOS
C
D
Thursday, March 13, 2014
E
Sheet
33
of
Rev
1.0
39
5
需需需需需SPEC.
PWR Rule
Modify 8/6.
4
3
2
1
3 X 330u/9m(47W)
2 X 330u/9m(37W)
24 pcs 22uF and reserve 4 pcs
2013/08/16
D
D
+SOC_VNN =+VGFX_CORE
+SOC_VCC =+CPU_CORE
+SOC_VNN
+SOC_VCC
Output Cap
(330uF*2+22uF*4)
PC903 1
PC904 1
PC905 1
PC906 1
2
2
2
2
PC913 1
PC914 1
PC915 1
PC916 1
Output Cap
(330uF*3+22uF*4)
2
2
2
2
PC917 2
1 330U_D2_2V_Y
1 330U_D2_2V_Y
PC918 2
+
1 330U_D2_2V_Y
1 330U_D2_2V_Y
+
PC902 2
+
@ PC919 2
1 330U_D2_2V_Y
C
Back Side Cap
(10uF*1+4.7uF*2+2.2uF*2)
PC929 1
2 22U_0603_6.3V6M
PC907 1
2 22U_0603_6.3V6M
PC930 1
2 22U_0603_6.3V6M
PC908 1
2 10U_0603_6.3V6M
PC909 1
PC910 1
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
PC911 1
PC912 1
2 2.2U_0402_6.3V6M
2 2.2U_0402_6.3V6M
+
+SOC_VCC
Package Edge Cap
(22uF*3)
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+
PC901 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+SOC_VNN
Package Edge Cap
(22uF*3)
Back Side Cap
(1uF*3)
PC920 1
PC921 1
PC922 1
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
PC923 1
PC924 1
PC925 1
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
@ PC926 1
@ PC927 1
@ PC928 1
C
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
Deciphered Date
2014/09/25
Title
CPU/GFX capacitor
Bay Trail M LA-B511P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Sheet
Thursday, March 13, 2014
1
34
Rev
1.0
of
39
5
4
3
2
Version change list (P.I.R. List)
Item
D
Fixed Issue
3
4
5
6
7
8
9
Page 1 of 2
for PWR
Reason for change
Improve ripple voltage
Improve part rating
1
2
HW request
1
Use bead(L22) individ
Unify VC0/VC1 setting
Raise part rating
Prevent burn issue
Customer request
VC 0/1 controlled by sw method
Meet EC request
Rev.
PG#
Modify List
30
33
Date
Change PL602 from SH00000YE00 to SH000008800
Change PC901,PC902,PC917,PC918 from
SGA000026800 to SGA20331E10
Delete PJ501, PJ502
Change PR202, PR203, PR216
Change PR814, PR832 size from 0402 to 0603
Change PQ303, PQ304 from AO4466L to AO4406AL
Change PR211 from 100 to 0
Pop PC426
Change +1.8VALW for VGATE pull high
29
26
32
27
26
28
32
Phase
12/30
DVT
12/31
DVT
01/07
01/08
01/10
01/10
01/29
01/29
02/18
DVT
DVT
DVT
DVT
PVT
PVT
PVT
D
10
C
B
11
12
13
14
15
C
B
12
13
14
15
16
A
17
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
2014/09/25
Deciphered Date
Title
PWR_PIR
Bay Trail M LA-B511P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Sheet
Thursday, March 13, 2014
1
35
Rev
1.0
of
39
5
4
Z5W1M_DVT Power Sequence AC mode
2014-02-21
BIOS:v0.07
EC:v0.07
3
G3->S0
2
S0->S3
1
S3->S0
S0->S5
ACIN
ACIN
+3VLP
+3VLP
220us
EC_ON
1.14ms
EC_ON
D
2.14ms
+5VALW
+3VALW
SPOK
SPOK
5.84ms
+1.0VALW
+1.0VALW
6.66ms
+1.8VALW
+1.8VALW
ON/OFF
ON/OFF
11ms
EC_RSMRST#
232ms
EC_RSMRST#
PBTN_OUT#
123ms
PBTN_OUT#
EC_SLP_S4#
23.6ms
EC_SLP_S3#
23.6ms
EC_SLP_S4#
EC_SLP_S3#
204ms
SYSON
217.6ms
SYSON
C
D
+3VALW
+5VALW
2.4ms
+1.35V
3.29ms
+1.35V
3.29ms
DDR_PWROK
C
4.8ms
92.00ms
DDR_PWROK
24.9ms
VR_ON
2.52ms
22.32ms
36.20ms
VR_ON
2.40ms
10.8ms
9.00ms
+SOC_VCC
2.52ms
+SOC_VNN
+SOC_VCC
2.40ms
26.00ms
+SOC_VNN
34.00ms
2.52ms
2.52ms
VGATE
VGATE
27.7ms
27.30ms
48.8ms
40.80ms
SUSP#
140us
+1.0VS
9.50ms
1.90ms
4.6ms
1.48ms
12.4ms
2.42ms
21.70ms
2.26ms
+1.5VS
2.22ms
16.30ms
+1.8VS
+1.35VS
2.42ms
22.20ms
+1.5VS
+1.05VS
1.46ms
18.90ms
+1.35VS
+1.0VS
1.8ms
4.2ms
+1.05VS
SUSP#
31.12us
10.20ms
16.20ms
3.08ms
+1.8VS
3.04ms
56.40ms
+3VS
4.00ms
3.92ms
B
41.18ms
+5VS
30.50ms
8.1ms
+0.675VS
1.6ms
39.36ms
32ms
149.6ms
KBRST#
152.4ms
KBRST#
60.20ms
92ms
172.4ms
PMC_CORE_PWROK
PMC_CORE_PWROK
60.20ms
93ms
172.4ms
DDR_CORE_PWROK
20.4ms
DDR_CORE_PWROK
B
+5VS
8.16ms
5.00ms
+0.675VS
+3VS
50.7ms
116ms
99.4ms
SUSP#
8.8ms
PMC_PLTRST#
PMC_PLTRST#
44.3ms
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/9/25
Deciphered Date
2014/09/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
Date:
5
4
3
2
Power Sequence
Bay Trail M LA-B511P
Document Number
Thursday, March 13, 2014
Sheet
1
36
Rev
1.0
of
39
5
4
3
2
Version Change List ( P. I. R. List )
Item Page#
1
Title
P.08
Date
12/17
Request
Owner
Page 1
Issue Description
HW
1
Solution Description
SLP_S3# leak voltage
Rev.
Change Q21 direction
0.2
D
D
2
C
P.09
12/17
HW
GPIO_S0_SC_56 pull down no vedio.
Touch screen and touch pad SMbus net fail
Pop R53, unpop R55
Change Q2.1 to SOC_I2C5_CLK
Change Q3.1 to SOC_I2C2_CLK
NO support CPU Thermal sensor
Unpop U28
0.2
3
P.14
1/6
HW
U9 DP to LVDS chip old symbol
Link CIS for SA00007A300
0.2
4
P.18
1/6
HW
U14 Lid switch old symbol
Link CIS for SA000079D00
0.2
5
P.19
1/6
HW
Vendor request to meet Acer spec
Change R188,R192 from 47ohm to 60.4ohm
0.2
ESD
ESD test Fail
Add C277,C278,L19,L20 for RING2 & SLEEVE
Change D9 pin2.3 name to RING2_L & SLEEVE_L
HW
0 ohm R-short
6
R13,R71,R72,R118,R119,R120,R121,R122,
R123,R124,R125,R34,R36,R200,R254,R255,
R172,R187,R193,R167,R168,R169,R170,
R187,R193,R107,R108,R212
C
P.6,8,11,15,
16,17,19,22
1/6
7
P.17
1/6
HW
Change LAN power
Unpop U19,C188
Pop R160,R200
change R200.2 from LAN_PWR_EN to LAN_GPO
Change C204,C205 from 12pF to 10pF
0.2
8
P.22
1/6
HW
Add EC GPIO
Board ID
Add LAN_GPO for U22.pin106
Change R211 to 12K
0.2
9
P.15
1/6
ESD
Add D13
0.2
0.2
B
B
10
P.21
11
P.19
12
13
1/6
HW
Change USB HUB to GL850S
Delete U18,R152~R157,C182~C187,Y3
Add U29,R259~R263,C279~C287,Y5
1/6
HW
BOM
Change C215,C273 from SE107105ML0 to SE080105K80
0.2
P.8
1/6
HW
P.13
1/7
EMI
Change R34.2 from TS_INT#_CPU to SOC_TS_INT#
Change R36.2 from TP_INT#_CPU to SOC_TP_INT#
P.23
1/7
0.2
Add L21,L22 for EMI
0.2
Change net name to +1.35V_L
C91~C102,R77,R75,(JDIMM1 pin75,76,81,82,87,88,
93,94,99,100,105,106,111,112,117,118,123,124)
A
14
0.2
HW
Add U30,C288,C289,R264 for +3V_TP
Change JTP1.8,R233.2,R225.2,R227.2 to +3V_TP
Compal Secret Data
Security Classification
Issued Date
2011/08/31
2012/08/31
Deciphered Date
Title
A
0.2
Compal Electronics, Inc.
EE P.I.R (1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
37
of
39
5
4
3
2
Version Change List ( P. I. R. List )
Item Page#
15
Title
P.24
Date
01/07
Request
Owner
Page 2
Issue Description
HW
1
BOM
Solution Description
Rev.
Change U24,U26 to SA00006FD00
0.2
D
D
16
P.9,23
01/08
HW
BOM
17
P.8,15,17
19,22
01/08
HW
BOM
18
P.23
01/08
HW
BOM
Delete TP@ BOM structure ==>
C255,Q11,R223,R225,R227,R230,R63,R64,Q3
R-short==>R34,R36,R200,R254,R255,R172,R187,
0.2
R193,R167,R168,R169,R170,R187,R193,R107,R108,
R212,R150,R151,R248,R249
Pop U30,C288,C289
Unpop R264
Pop U30,C288,C289
Unpop R264
P.08
C
0.2
0.2
19
P.23
P.22
01/08
HW
Change U30.3 from SYSON to TP_PWR_EN
Add U22.98 TP_PWR_EN
0.2
20
P.21
01/08
ME
JUSB2 Link CIS symbol ==> ACES_51524-0140N-001 0.2
21
P.21
01/13
HW
USB2.0 port0
USB2.0 port1
22
P.9,14
01/14
HW
Change RP10,RP11 to 2.2K_0804_8P4R
0.2
23
P.15
01/14
HW
BOM
ETS@ BOM structure ==>
0.2
24
P.21
01/16
HW
BOM
BOM structure==>Add U16,R257 to TPM@
0.2
25
P.09
02/18
HW
BOM
For +1.8VS abnormal voltage
Pop R28
0.3
26
P.20
02/18
HW
0.3
27
P.24
02/18
HW
For HP
Change
Change
For TP
Change
Change
28
P.23
02/18
HW
29
P.25
02/18
HW
30
P.24
02/18
HW
conn.
USB3.0
USB HUB
C
0.2
R101,R102,R113,R114
B
A
B
pop noise
R188,R192 to 0ohm
R187,R193 to 60.4ohm
0.3
R205,R206 to +3V_TP
JTP1 pin define
For Board ID
Pop R219
Change R221 to 15K
For +1.0 VS
Pop C268, Change R242 to 1K
unpop SW2
Compal Secret Data
Security Classification
Issued Date
2011/08/31
2012/08/31
Deciphered Date
Title
0.3
A
0.3
0.3
Compal Electronics, Inc.
EE P.I.R (2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
38
of
39
5
4
3
2
Version Change List ( P. I. R. List )
Item Page#
31
Title
P.20,24
Date
02/21
Request
Owner
1
Page 2
Issue Description
Solution Description
Rev.
蓋蓋蓋
ME
JKB2,JBL1,JDMIC1
.
Change footprint to XXXX-S
D
0.3
D
32
P.9,21,22,23
02/21
HW
R-short R40,R96,R143,R142,R259,R198,R199,R220 0.3
32
P.9
02/21
HW
Add JCMOS2
0.3
33
P.24
02/21
ME
測Chang
測 R231,R233 to 100 ohm
0.3
Change R232,R234 to 470 ohm
34
P.22
02/24
HW
Change USB HUB to GL850G
Add U31,R265,R266,R267
Delete U29,R262
0.3
35
P.09
02/25
HW
32.768KHz
Change C17,C18 to 18pF
0.3
C
C
36
P.17,20,25
02/26
HW
Change Q9,Q17,Q18 from SB00000DH00
to SB00000ZU00
0.3
37
P.16
03/12
HW
R-short R88
1.0
38
P.23
03/13
HW
For Board ID
Change R221 from 15K to 20K
1.0
39
P.24
03/13
HW
Change SW1 from DBG@ to @
1.0
B
B
A
A
Compal Secret Data
Security Classification
Issued Date
2011/08/31
2012/08/31
Deciphered Date
Title
Compal Electronics, Inc.
EE P.I.R (2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
Bay Trail M LA-B511P
Date:
5
4
3
2
Thursday, March 13, 2014
Sheet
1
39
of
39
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising