data sheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30500
VR5000TM
64-BIT MICROPROCESSOR
DESCRIPTION
The µPD30500 (VR5000) is a high-performance, 64-bit RISC (Reduced Instruction Set Computer) type microprocessor employing the RISC architecture developed by MIPSTM Technologies Inc.
The instructions of the VR5000 are compatible with those of the VR3000TM series and VR4000TM series and higher,
and completely compatible with those of the VR10000TM. Therefore, present applications can be used as they are.
Detailed functions are descrided in the following manual. Be sure to read the manual when
designing your system.
• VR5000 User’s Manual (U11761E)
FEATURES
• Employs 64-bit MIPS-based RISC architecture
• High-speed processing
·
2-way super scalar 5-stage pipeline
·
5.5 SPECint95, 5.5 SPECfp95, 282 MIPS
• High-speed translation buffer mechanism (TLB) (48 entries)
• Address space
Physical : 36 bits
Virtual
: 40 bits
• Floating-point unit (FPU)
·
Sum-of-products operation instruction added
·
Higher operation performance than VR4000 series
• Primary cache memory (instruction/data: 32K bytes each)
• Secondary cache controller
• Operating frequency
Internal : 250 MHz MAX.
External : 125 MHz MAX.
·
External/internal multiple selectable from two to eight
• Instruction set compatible with VR3000 and VR4000 series and higher (conforms to MIPS I, II, III, and IV)
• Supply voltage: 3.3 V ±5%
APPLICATIONS
• High-performance embedded systems
• Multimedia systems
• Entry-class computers
• Image processing systems
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Document No. U12031EJ2V0DS00 (2nd edition)
Date Published May 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
1997
©
© MIPS Technologies Inc. 1997
µPD30500
ORDERING INFORMATION
Part number
Maximum operating frequency (MHz)
µPD30500RJ-150
223-pin ceramic PGA (48 × 48 mm)
150
µPD30500RJ-180
223-pin ceramic PGA (48 × 48 mm)
180
µPD30500RJ-200
223-pin ceramic PGA (48 × 48 mm)
200
µPD30500RJ-250Note
223-pin ceramic PGA (48 × 48 mm)
250
µPD30500S2-150
272-pin plastic BGA (29 × 29 mm)
150
µPD30500S2-180
272-pin plastic BGA (29 × 29 mm)
180
µPD30500S2-200
272-pin plastic BGA (29 × 29 mm)
200
µPD30500S2-250Note
272-pin plastic BGA (29 × 29 mm)
250
Note
2
Package
Under development
Data Sheet U12031EJ2V0DS00
µPD30500
PIN CONFIGURATION (Top View)
• 223-pin ceramic PGA (48 × 48 mm) (Bottom View)
µPD30500RJ-150
µPD30500RJ-180
µPD30500RJ-200
µPD30500RJ-250Note
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V
Note
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Under development
Data Sheet U12031EJ2V0DS00
3
µPD30500
No.
4
Name
No.
Name
No.
Name
No.
Name
No.
Name
No.
Name
A2
VDD
C5
SysADC6
E18
VDD
K17
GNDP
R6
SysAD51
U9
SysAD63
A3
GND
C6
SysAD16
F1
VDD
K18
GND
R7
SysAD55
U10
SysAD13
A4
VDD
C7
SysAD50
F2
Reserved
L1
GND
R8
SysAD27
U11
SysAD11
A5
GND
C8
SysAD22
F3
ScValid
L2
SysCmd8
R9
SysAD31
U12
SysAD9
A6
GND
C9
SysAD24
F4
Int1
L3
SysCmd7
R10
SysAD43
U13
SysAD37
A7
VDD
C10
SysAD28
F15
ScDCE0
L4
SysCmd5
R11
SysAD39
U14
SysAD3
A8
GND
C11
SysAD62
F16
ScCWE0
L15
ScLine12
R12
SysAD35
U15
ScWord0
A9
VDD
C12
SysAD44
F17
ScTDE
L16
ScLine14
R13
SysAD1
U16
VDD
A10
GND
C13
SysAD10
F18
GND
L17
ScLine15
R14
ScWord1
U17
GND
A11
VDD
C14
SysAD38
G1
GND
L18
VDD
R15
ScLine0
U18
GND
A12
GND
C15
SysAD4
G2
Reserved
M1
VDD
R16
ScLine3
V1
GND
A13
VDD
C16
SysAD34
G3
Reserved
M2
SysCmd6
R17
ScLine6
V2
GND
A14
GND
C17
SysAD2
G4
Reserved
M3
SysCmd4
R18
GND
V3
VDD
A15
GND
C18
GND
G15
ScCLR
M4
SysCmd1
T1
GND
V4
GND
A16
VDD
D1
GND
G16
ScTCE
M15
ScLine8
T2
SysAD15
V5
GND
A17
GND
D2
Int3
G17
Modeln
M16
ScLine10
T3
SysAD47
V6
VDD
A18
GND
D3
Int5
G18
VDD
M17
ScLine13
T4
SysAD17
V7
GND
B1
GND
D4
Release
H1
VDD
M18
GND
T5
SysAD19
V8
VDD
B2
GND
D5
VDD
H2
Reserved
N1
GND
T6
SysAD23
V9
GND
B3
VDD
D6
SysADC2
H3
Reserved
N2
SysCmd3
T7
SysAD57
V10
VDD
B4
SysADC4
D7
SysAD48
H4
Reserved
N3
SysCmd2
T8
SysAD29
V11
GND
B5
SysADC0
D8
SysAD52
H15
VDDOk
N4
SysADC7
T9
VDD
V12
VDD
B6
SysAD18
D9
SysAD56
H16
ModeClock N15
ScLine5
T10
SysAD45
V13
GND
B7
SysAD20
D10
SysAD60
H17
SysClock
N16
ScLine7
T11
SysAD41
V14
VDD
B8
SysAD54
D11
SysAD14
H18
GND
N17
ScLine11
T12
SysAD7
V15
GND
B9
SysAD26
D12
SysAD42
J1
GND
N18
VDD
T13
SysAD5
V16
GND
B10
SysAD58
D13
SysAD8
J2
WrRdy
P1
VDD
T14
SysAD33
V17
VDD
B11
SysAD30
D14
SysAD36
J3
Validln
P2
SysCmd0
T15
Reset
V18
GND
B12
SysAD46
D15
ColdReset
J4
ExtRqst
P3
SysCmdP
T16
ScLine1
B13
SysAD12
D16
SysAD0
J15
Reserved
P4
SysADC1
T17
VDD
B14
SysAD40
D17
ScTOE
J16
Reserved
P15
ScLine2
T18
VDD
B15
SysAD6
D18
VDD
J17
Reserved
P16
ScLine4
U1
VDD
B16
GND
E1
GND
J18
VDD
P17
ScLine9
U2
VDD
B17
VDD
E2
Int0
K1
VDD
P18
GND
U3
GND
B18
VDD
E3
Int2
K2
ScMatch
R1
VDD
U4
SysAD21
C1
VDD
E4
Int4
K3
RdRdy
R2
SysADC5
U5
SysAD53
C2
VDD
E15
SysAD32
K4
ScDOE
R3
SysADC3
U6
SysAD25
C3
ValidOut
E16
ScDCE1
K15
Reserved
R4
BigEndian
U7
SysAD59
C4
NMI
E17
ScCWE1
K16
VDDP
R5
SysAD49
U8
SysAD61
Data Sheet U12031EJ2V0DS00
µPD30500
• 272-pin plastic BGA (29 × 29 mm)
µPD30500S2-150
µPD30500S2-180
µPD30500S2-200
µPD30500S2-250Note
Bottom View
Top View
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AA Y W V U T R P N M L K J H G F E D C B A
A B C D E F G H J K L M N P R T U V W Y AA
Index mark
Note
Under development
Data Sheet U12031EJ2V0DS00
5
µPD30500
No.
6
Name
No.
Name
No.
Name
SysAD8
No.
Name
VDD
GND
SysAD17
Y2
VDD
U20
SysAD49
Y3
VDD
U21
GND
Y4
Release
Int3
ScDCE1
C6
ScDCE0
F2
SysAD38
SysAD6
M1
SysAD26
M2
SysAD56
A3
GND
C7
ScCWE0
A4
SysAD32
C8
ScTCE
F4
GND
GND
SysAD24
V1
VDD
VDD
V2
VDD
Y6
Int2
V3
VDD
Y7
ScValid
V4
GND
Y8
Reserved
Reserved
A5
GND
C9
Modeln
A6
ScCWE1
C10
Reserved
F19
SysAD1
SysAD33
M18
VDD
M19
SysAD29
M4
VDD
Y5
F18
M3
Name
U19
C5
VDD
L21
No.
U18
GND
A2
F3
Name
SysAD63
A1
L20
No.
Y1
F1
A7
GND
C11
GNDP
F20
A8
VDDOk
C12
Reserved
F21
SysAD3
GND
M20
SysAD61
V5
NMI
Y9
M21
SysAD31
V6
GND
Y10
Reserved
ExtRqst
A9
GND
C13
ScLine13
G1
A10
SysClock
C14
ScLine11
G2
SysAD10
SysAD40
GND
V7
VDD
Y11
SysAD54
V8
VDD
Y12
RdRdy
V9
GND
Y13
SysCmd8
V10
VDD
Y14
SysCmd5
SysCmd3
A11
GND
C15
ScLine8
G3
A12
ScLine15
C16
ScLine5
G4
VDD
VDD
N3
SysAD22
N4
GND
N1
N2
A13
GND
C17
ScLine4
G18
A14
ScLine12
C18
ScLine0
G19
SysAD35
SysAD5
N18
GND
V11
VDD
Y15
N19
SysAD27
V12
VDD
Y16
SysCmd0
SysCmdP
A15
GND
C19
Reset
G20
A16
ScLine7
C20
VDD
G21
GND
SysAD42
N20
SysAD59
V13
GND
Y17
N21
GND
V14
VDD
Y18
SysADC1
SysAD15
A17
GND
C21
GND
H1
A18
ScLine2
D1
VDD
H2
SysAD44
SysAD12
P1
SysAD50
V15
VDD
Y19
P2
SysAD52
V16
GND
Y20
VDD
VDD
A19
GND
D2
VDD
H3
A20
VDD
D3
VDD
H4
VDD
VDD
P3
SysAD20
V17
VDD
Y21
P4
VDD
V18
GND
AA1
GND
VDD
A21
GND
D4
GND
H18
B1
VDD
D5
VDD
H19
SysAD7
SysAD39
P18
VDD
V19
VDD
AA2
P19
SysAD25
V20
VDD
AA3
GND
ValidOut
B2
VDD
D6
GND
H20
B3
VDD
D7
VDD
H21
SysAD37
GND
P20
SysAD57
V21
VDD
AA4
P21
SysAD55
W1
GND
AA5
GND
Int0
B4
SysAD2
D8
VDD
J1
B5
SysAD0
D9
GND
J2
SysAD46
SysAD14
GND
W2
VDD
AA6
SysAD18
W3
VDD
AA7
GND
W4
VDD
AA8
Reserved
W5
Int5
AA9
GND
W6
Int4
AA10
WrRdy
W7
Int1
AA11
GND
ScMatch
B6
ScTOE
D10
VDD
J3
B7
ScCLR
D11
VDDP
J4
GND
VDD
J18
GND
R3
SysAD48
GND
J19
SysAD9
R4
VDD
SysAD41
R18
VDD
R19
SysAD53
B8
ScTDE
D12
B9
ModeClock D13
R1
R2
B10
Reserved
D14
VDD
J20
B11
Reserved
D15
VDD
J21
GND
SysAD60
R20
SysAD23
W8
Reserved
AA12
R21
GND
W9
Reserved
AA13
GND
SysCmd6
B12
NC
D16
GND
K1
B13
ScLine14
D17
VDD
K2
SysAD30
SysAD62
T1
SysAD16
W10
Reserved
AA14
T2
SysADC0
W11
Validln
AA15
GND
SysCmd2
B14
ScLine10
D18
GND
K3
B15
ScLine9
D19
VDD
K4
VDD
VDD
T3
SysADC2
W12
ScDOE
AA16
T4
GND
W13
SysCmd7
AA17
GND
SysADC3
B16
ScLine6
D20
VDD
K18
B17
ScLine3
D21
VDD
K19
SysAD11
SysAD43
T18
GND
W14
SysCmd4
AA18
T19
SysAD19
W15
SysCmd1
AA19
GND
VDD
GND
B18
ScLine1
E1
GND
K20
B19
VDD
E2
SysAD36
K21
SysAD13
GND
T20
SysAD51
W16
SysADC7
AA20
AA21
B20
VDD
E3
SysAD4
L1
B21
VDD
E4
VDD
L2
SysAD58
T21
SysAD21
W17
SysADC5
SysAD28
U1
GND
W18
SysAD47
BigEndian
C1
GND
E18
VDD
L3
C2
VDD
E19
ScWord1
L4
VDD
U2
SysADC4
W19
VDD
U3
SysADC6
W20
VDD
SysAD45
VDD
W21
GND
C3
ColdReset
E20
ScWord0
L18
C4
SysAD34
E21
GND
L19
U4
Data Sheet U12031EJ2V0DS00
µPD30500
PIN NAMES
BigEndian
:
Endian Mode Select
ColdReset
:
Cold Reset
ExtRqst
:
External Request
GND
:
Ground
GNDP
:
Quiet GND for PLL
Int (0:5)
:
Interrupt Request
ModeClock
:
Boot Mode Clock
Modeln
:
Boot Mode Data In
NC
:
No Connection
NMI
:
Non-maskable Interrupt Request
RdRdy
:
Read Ready
Release
:
Release Interface
Reset
:
Reset
ScCLR
:
Secondary Cache Block Clear
ScCWE (0:1)
:
Secondary Cache Write Enable
ScDCE (0:1)
:
Data RAM Chip Enable
ScDOE
:
Data RAM Output Enable
ScLine (0:15)
:
Secondary Cache Line Index
ScMatch
:
Secondary Cache Tag Match
ScTCE
:
Secondary Cache Tag RAM Chip Enable
ScTDE
:
Secondary Cache Tag RAM Data Enable
ScTOE
:
Secondary Cache Tag RAM Output Enable
ScValid
:
Secondary Cache Valid
ScWord (0:1)
:
Secondary Cache Word Index
SysAD (0:63)
:
System Address/Data Bus
SysADC (0:7)
:
System Address/Data Check Bus
SysClock
:
System Clock
SysCmd (0:8)
:
System Command/Data Identifier
SysCmdP
:
System Command/Data Identifier Bus Parity
Validln
:
Valid Input
ValidOut
:
Valid Output
V DD
:
Power Supply
V DDOk
:
V DD is OK
V DDP
:
Quiet V DD for PLL
WrRdy
:
Write Ready
Data Sheet U12031EJ2V0DS00
7
µPD30500
INTERNAL BLOCK DIAGRAM
Data, address
Control
System interface
SysClock
Clock
generator
Instruction cache
Data cache
CP0
TLB
Execution unit
Instruction address
Pipeline control
8
Data Sheet U12031EJ2V0DS00
Floating-point unit
µPD30500
TABLE OF CONTENTS
1. PIN FUNCTIONS ............................................................................................................................
10
2. INTERNAL BLOCK ........................................................................................................................
12
3. INTERNAL ARCHITECTURE .........................................................................................................
14
3.1
3.2
PIPELINE ................................................................................................................................................
CPU REGISTER .....................................................................................................................................
14
15
3.3
SYSTEM CONTROL COPROCESSOR (CP0) .......................................................................................
3.3.1 CPU Registers .............................................................................................................................
16
16
3.4
3.5
DATA FORMAT AND ADDRESSING ....................................................................................................
VIRTUAL MEMORY ...............................................................................................................................
18
20
3.5.1
3.5.2
Virtual Address Space .................................................................................................................
Address Conversion ....................................................................................................................
20
23
CACHES .................................................................................................................................................
EXCEPTION PROCESSING ...................................................................................................................
25
26
4. FPU INTERNAL ARCHITECTURE ................................................................................................
28
3.6
3.7
4.1
4.2
INTERNAL FUNCTION BLOCK .............................................................................................................
FPU REGISTERS ...................................................................................................................................
28
29
4.3
DATA FORMATS ....................................................................................................................................
30
5. INTERFACES ..................................................................................................................................
31
5.1
SYSTEM INTERFACE ............................................................................................................................
5.1.1 System Interface Requests .........................................................................................................
31
31
5.1.2
5.1.3
Control of Data Transfer Rate .....................................................................................................
Clock Interface ............................................................................................................................
32
33
SECONDARY CACHE INTERFACE ......................................................................................................
SETTING OF BOOT MODE ....................................................................................................................
34
35
6. INTERNAL/EXTERNAL CONTROL FUNCTIONS ........................................................................
37
5.2
5.3
6.1
RESET FUNCTION .................................................................................................................................
6.1.1 Power-ON Reset and Cold Reset ...............................................................................................
37
37
6.2
6.1.2 Warm Reset ................................................................................................................................
INTERRUPT FUNCTIONS ......................................................................................................................
37
37
6.3
STANDBY MODE ...................................................................................................................................
38
7. INSTRUCTION SET ........................................................................................................................
39
7.1
INSTRUCTION FORMAT .......................................................................................................................
39
7.2
7.3
LIST OF CPU INSTRUCTION SET ........................................................................................................
LIST OF FPU INSTRUCTION SET ........................................................................................................
39
45
7.4
DELAY OF INSTRUCTION .....................................................................................................................
48
8. ELECTRICAL SPECIFICATIONS ..................................................................................................
51
9. PACKAGE DRAWING ....................................................................................................................
58
10. RECOMMENDED SOLDERING CONDITIONS ..............................................................................
60
APPENDIX DIFFERENCES BETWEEN THE VR5000 AND VR4310TM ...............................................
61
Data Sheet U12031EJ2V0DS00
9
µPD30500
1.
PIN FUNCTIONS
Pin Name
I/O
SysAD (0:63)
I/O
System address/data bus.
64-bit bus for communication between processor, secondary cache and external agent.
SysADC (0:7)
I/O
System address/data check bus.
8-bit bus including check bits for the SysAD bus.
SysCmd (0:8)
I/O
System command/data ID bus.
9-bit bus for communication of commands and data identifiers between processor
and external agent.
SysCmdP
I/O
System command/data ID bus parity.
1-bit even number parity bit for the SysCmd bus.
ValidIn
Input
ValidOut
Output
ExtRqst
Input
Function
Valid in.
Signal indicating that external agent has transmitted valid address or data onto
SysAD bus and valid command or data identifier onto SysCmd bus.
Valid out.
Signal indicating that processor has transmitted valid address or data onto SysAD
bus and valid command or data identifier onto SysCmd bus.
External request.
Signal used by external agent to request for its use by system interface.
Release
Output
Interface release.
Signal indicating that the processor has released the system interface to the slave state.
WrRdy
Output
Write ready.
Signal indicating that the external agent can accept a processor write request.
RdRdy
Input
ScCLR
Output
Secondary cache block clear.
Clears all the valid bits of the tag RAM.
ScCWE (0:1)
Output
Secondary cache write enable.
Read ready.
Signal indicating that external agent can accept a processor read request.
Write enable signal for the secondary cache RAM.
ScDCE (0:1)
ScDOE
ScLine (0:15)
ScMatch
Output
Input
Output
Input
Data RAM chip select.
Chip select signal for secondary cache RAM.
Data RAM output enable.
Data output enable signal from the external agent.
Secondary cache line index.
Cache line index output of the secondary cache.
Secondary cache tag match.
Tag match signal from secondary cache tag RAM.
ScTCE
Output
Secondary cache tag RAM chip select.
Chip select signal of the secondary cache tag RAM.
ScTDE
Output
Secondary cache tag RAM data enable.
Data enable signal from the secondary cache tag RAM.
10
Data Sheet U12031EJ2V0DS00
µPD30500
Pin Name
ScTOE
I/O
Output
Function
Secondary cache tag RAM output enable.
Output enable signal from the secondary cache tag RAM.
ScWord (0:1)
I/O
Secondary cache word index.
Signal indicating that the double word of the secondary cache index is correct.
ScValid
I/O
Secondary cache valid.
Signal indicating that the data of the secondary cache is valid.
Int (0:5)
Input
Interrupt.
General-purpose processor interrupt requests whose input statuses can be confirmed by
bits 15 through 10 of cause register.
NMI
Input
Non-maskable interrupt.
Interrupt request that cannot be masked.
ColdReset
Input
Cold reset.
Signal initializing the internal status of the processor. Inactivate this signal in synchronization with SysClock.
Reset
Input
Reset.
Signal generating a reset exception, without initializing the internal status of the processor.
Inactivate this signal in synchronization with SysClock.
SysClock
Input
System clock.
Clock input signal to processor.
BigEndian
Input
Endian mode setting.
This signal sets the endian mode of the system interface.
When setting the endian mode with this signal, specify little endian with the data from the
ModeIn pin that is input at reset.
To set the endian mode with the data from the ModeIn pin, fix this signal to 0.
ModeClock
Output
BigEndian
Bit 8 of boot mode
Mode
1
1
0
0
1
0
1
0
—
Big endian
Big endian
Little endian
Boot mode clock.
Successive boot mode data clock output resulting from dividing SysClock by 256.
Modeln
Input
Boot mode data input.
Input of initialization bit stream.
VDDOk
Input
VDD is valid.
Signal indicating that the voltage supplied to the VR5000 is 3.135 V or higher for 100 ms,
and that that status is stabilized. When VDDOk is asserted active, the VR5000 starts an
initialization sequence.
VDDP
–
PLL VDD.
Power supply for internal PLL.
GNDP
–
PLL GND.
Ground for internal PLL.
VDD
–
Positive power supply pin.
GND
–
Ground pin.
Data Sheet U12031EJ2V0DS00
11
µPD30500
2.
INTERNAL BLOCK
(1) Integer operation unit
Executes integer operation instruction. This unit is provided with the following:
• 64-bit register file
• 64-bit integer data bus
• High-speed multiplier
(2) Floating-point unit
This unit executes floating-point operation instructions, and is provided with the following:
• 64-bit register file
• 64-bit mantissa data bus
• 12-bit exponent data bus
• High-speed multiplier
• High-speed divider/square root unit
(3) Coprocessor 0 (CP0)
This coprocessor is provided with the following:
• Exception processing unit
• Memory management unit
The memory management unit converts virtual addresses into physical addresses and checks memory access
between different memory segments (kernel, supervisor, and user).
TLB (translation lookaside buffer) converts virtual addresses into physical addresses.
The VR5000 supports seven types of page size, in a range of 4K bytes to 16M bytes in 4 × increments, with VSIZE
(virtual address) = 40 and PSIZE = (physical address) = 36. TLB has 48 entries. Each entry is mapped to an
even/odd page of a page frame number.
The exception processing unit is provided with system control coprocessor registers.
(4) Pipeline control
The pipeline is controlled and appropriate processing is executed in the following cases:
•
•
•
•
Occurrence of cache miss
Flash buffer full
Multi-cycle instruction
Occurrence of system exception, etc.
(5) Instruction address
The execution address of the next instruction to be fetched is calculated.
For this purpose, the following units are provided:
• PC incrementer
• Branch address adder
• Conditional branch address selector
12
Data Sheet U12031EJ2V0DS00
µPD30500
(6) Instruction cache
The instruction cache have 32-Kbyte capacity and employs the following methods:
• 2-way set associative
• Virtual index address
• Physical tag cache
No hardware is provided to check generation of cache alias due to virtual address.
The cache data interface is 64 bits wide.
Cache parity is supported.
(7) Data cache
The data cache have 32-Kbyte capacity and employs the following methods:
• 2-way set associative
• Virtual index address
• Physical tag, write back cache
Cache parity is supported.
(8) System interface
This interface enables the processor to access external resources to satisfy internal requests.
The system interface consists of a 64-bit multiplexed address/data bus, byte parity, interrupt request signal, and
control signal.
(9) Clock generator
Generates PClock based on an input clock (MasterClock).
The frequency ratio of PClock and SysClock is set by input from the ModeIn pin at power-ON reset/cold reset.
To suppress skewing of the input clock and internal clock, a phased lock loop (PLL) is used.
Data Sheet U12031EJ2V0DS00
13
µPD30500
3. INTERNAL ARCHITECTURE
The V R5000 has one pipeline for integer operation and another pipeline for floating-point operation. These
two pipelines operate independently of each other (super scalar).
As a result, up to two instructions can be executed at the same time.
3.1 PIPELINE
Each instruction consists of the following five stages. Each stage is divided into two phases.
(1) I
instruction fetch
(2) R
register fetch
(3) A
execution
(4) D
data fetch
(5) W
write back
The V R5000 is provided with a 2-way super scalar 5-stage pipeline. Although it takes five clocks to execute
each instruction, paralleling is implemented at instruction level. PClock, which is the pipeline clock, operates
at a frequency 2, 3, 4, 5, 6, 7, or 8 times higher than that of the master clock, and the multiple is specified by
input from ModeIn pin on reset.
The outline of the pipeline is described below.
Figure 3-1. 2-Way Super Scalar 5-Stage Pipeline of VR5000
PClock
Integer operation pipeline
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
Floating-point operation pipeline
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
1I
2I
1R 2R 1A 2A 1D 2D 1W 2W
Current
CPU
cycle
14
Data Sheet U12031EJ2V0DS00
µPD30500
3.2 CPU REGISTER
The V R 5000’s CPU registers are shown in Figure 3-2. The bit widths of these registers are determined by
the operation mode of the processor (32 bits in 32-bit mode; 64 bits in 64-bit mode).
Among the 32 general-purpose registers, the following two registers have special meanings.
• Register r0: The content is always 0. Register r0 can be coded as the instruction’s target register to discard
the operation result.
When the value 0 is required, this register can be used as the source register.
• Register r31: Refers to the link register for the JAL and JALR instructions. Therefore, be sure not to use register
r31 for other instructions.
Two multiplication and division registers (HI, LO) store integer multiplication results as well as the quotients
(LO) and remainders (HI) from integer division.
The load link register is for synchronizing the processors on a multiprocessor system. However, this has no
meaning for the V R5000, which does not support multiprocessor systems. The register is defined here for the
purpose of maintaining compatibility with other VR series processors.
Figure 3-2. CPU Register
General-purpose registers
63
0
r0 = 0
Multiplication and division registers
63
0
HI
r1
r2
·
·
·
·
·
·
·
63
0
LO
Program counter
63
0
r29
PC
r30
r31 (link address)
Load link register
0
LLbit
A program status word (PSW) is not provided. However, its functions are provided by the status register and
the cause register incorporated in the system control processor (CP0).
Data Sheet U12031EJ2V0DS00
15
µPD30500
3.3
SYSTEM CONTROL COPROCESSOR (CP0)
The CP0 register/CP0 instruction accesses the TLB and cache. Moreover, operation of the mode using the
processor, exception, and interrupt processing are also controlled by CP0.
3.3.1 CPU Registers
All the CP0 registers of the V R5000 that can be used are listed below. Writing or reading an unused register
(RFU) is undefined.
Figure 3-3. CP0 Registers and TLB
Registers used by memory management system
Registers used for exception processing
Entry Lo0
2*
Entry Hi
10*
Index
0*
Context
4*
BadVAddr
8*
Random
1*
Count
9*
Compare
11*
Page mask
5*
Status
12*
Cause
13*
Wired
6*
EPC
14*
X Context
20*
PRld
15*
ECC
26*
Cache error
27*
Entry Lo1
3*
31
TLB
(“Safety”) entry
0 127/255
0
Config
16*
LLAddr
17*
Remark
16
Tag Hi
29*
Tag Lo
28*
“ * ” denotes a register number.
Data Sheet U12031EJ2V0DS00
Error EPC
30*
µPD30500
Table 3-1. CP0 Registers
Number
Register
Description
0
Index
Programmable pointer to TLB entry
1
Random
Random pointer to TLB entry
2
Entry Lo0
Second half of TLB entry for even VPN
3
Entry Lo1
Second half of TLB entry for odd VPN
4
Context
Pointer to PTE table
5
Page mask
TLB page mask
6
Wired
Number of wired TLB entries
7
—
RFU (Reserved for Future Use)
8
BadVAddr
Virtual address at which error occurs last
9
Count
Timer count
10
Entry Hi
First half of TLB entry
11
Compare
Timer comparison
12
Status
Status register
13
Cause
Cause of last exception
14
EPC
Exception program counter
15
PRId
Processor revision identifier
16
Config
Configuration register
17
LLAddr
Address of LL instruction
—
RFU
X context
Pointer to virtual PTE table of kernel in 64-bit mode
—
RFU
26
ECC
Check and correction of parity error of the primary chche
27
Cache error
Index and status field of cache error
28
Tag Lo
Cache register, low
29
Tag Hi
Cache register, high (reserved register)
30
Error EPC
Error exception program counter
31
—
RFU
18, 19
20
21 to 25
Data Sheet U12031EJ2V0DS00
17
µPD30500
3.4 DATA FORMAT AND ADDRESSING
The V R 5000 uses the following four types of data formats.
• Double word (64 bits)
• Word (32 bits)
• Half-word (16 bits)
• Byte (8 bits)
When the data format is double-word, word, or half-word, the alignment of bytes can be set to either big endian
or little endian with the configuration register BE bit.
Figure 3-4. Byte Address in Word: Big Endian
12
13
14
15
Word
address
12
8
9
10
11
8
4
5
6
7
4
0
1
2
3
0
31
Higher
address
Lower
address
24 23
16 15
8
7
0
Remarks 1. The most significant byte is at the lowest address.
2. The word is addressed at the highest address.
Figure 3-5. Byte Address in Word: Little Endian
15
14
13
12
Word
address
12
11
10
9
8
8
7
6
5
4
4
3
2
1
0
0
31
Higher
address
Lower
address
24 23
16 15
8
Remarks 1. The least significant byte is at the lowest address.
2. The word is addressed at the lowest address.
18
Data Sheet U12031EJ2V0DS00
7
0
µPD30500
Figure 3-6. Byte Address in Double-Word: Big Endian
Word
Half word
63
Higher
address
Lower
address
32 31
Byte
16 15
8 7
0
Double-word
address
16
17
18
19
20
21
22
23
16
8
9
10
11
12
13
14
15
8
0
1
2
3
4
5
6
7
0
Remarks 1. The most significant byte is at the lowest address.
2. The word is addressed at the highest address.
Figure 3-7. Byte Address in Double-Word: Little Endian
Word
Half word
63
Higher
address
Lower
address
32 31
Byte
16 15
8 7
0
Double-word
address
23
22
21
20
19
18
17
16
16
15
14
13
12
11
10
9
8
8
7
6
5
4
3
2
1
0
0
Remarks 1. The least significant byte is at the lowest address.
2. The word is addressed at the lowest address.
Data Sheet U12031EJ2V0DS00
19
µPD30500
3.5 VIRTUAL MEMORY
3.5.1 Virtual Address Space
The V R5000 has two operation modes: 32-bit and 64-bit modes. It also has three operating modes: user,
supervisor, and kernel. The figures below show the virtual address spaces in each operating mode.
Figure 3-8. User Mode Address Space
32 bitsNote
64 bits
0×FFFF FFFF
0×FFFF FFFF FFFF FFFF
Address error
Address error
0×8000 0000
0×7FFF FFFF
0×0000 0100 0000 0000
0×0000 00FF FFFF FFFF
with 2G-byte
TLB mapping
0×0000 0000
Note
with 1T-byte
TLB mapping
useg
0×0000 0000 0000 0000
In the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. For details, refer to VR5000
User’s Manual.
20
xuseg
Data Sheet U12031EJ2V0DS00
µPD30500
Figure 3-9. Supervisor Mode Address Space
32 bitsNote
64 bits
0×FFFF FFFF FFFF FFFF
0×FFFF FFFF
Address error
Address error
0×FFFF FFFF E000 FFFF
0×FFFF FFFF DFFF FFFF
0×E000 0000
0×DFFF FFFF
with 0.5G-byte
TLB mapping
with 0.5G-byte
TLB mapping
sseg
csseg
0×FFFF FFFF C000 0000
0×FFFF FFFF BFFF FFFF
0×C000 0000
0×BFFF FFFF
Address error
0×4000 0100 0000 0000
0×4000 00FF FFFF FFFF
Address error
with 1T-byte
TLB mapping
xsseg
0×4000 0000 0000 0000
0×3FFF FFFF FFFF FFFF
0×8000 0000
0×7FFF FFFF
Address error
0×0000 0100 0000 0000
0×0000 00FF FFFF FFFF
with 2G-byte
TLB mapping
with 1T-byte
TLB mapping
suseg
0×0000 0000
Note
xsuseg
0×0000 0000 0000 0000
In the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. For details, refer to VR5000
User’s Manual.
Data Sheet U12031EJ2V0DS00
21
µPD30500
Figure 3-10. Kernel Mode Address Space
32 bitsNote
64 bits
0×FFFF FFFF FFFF FFFF
0×FFFF FFFF
with 0.5G-byte
TLB mapping
kseg3
0×E000 0000
0×DFFF FFFF
ksseg
0×C000 0000
0×BFFF FFFF
ckseg3
with 0.5G-byte
TLB mapping
cksseg
without 0.5G-byte
TLB mapping,
cache disabled
ckseg1
without 0.5G-byte
TLB mapping,
cache enabled
ckseg0
0×FFFF FFFF E 0 0 0 0 0 0 0
0×FFFF FFFF DFFF FFFF
0×FFFF FFFF C000 0 0 0 0
0×FFFF FFFF BFFF FFFF
with 0.5G-byte
TLB mapping
with 0.5G-byte
TLB mapping
0×FFFF FFFF A000 0 0 0 0
0×FFFF FFFF 9FFF FFFF
0×FFFF FFFF 8000 0 0 0 0
0×FFFF FFFF 7FFF FFFF
Address error
without 0.5G-byte
TLB mapping,
cache disabled
kseg1
0×C000 00FF 8000 0 0 0 0
0×C000 00FF 7FFF FFFF
with TLB
mapping
0×A000 0000
0×9FFF FFFF
0×C000 0 0 0 0 0 0 0 0 0 0 0 0
0×BFFF FFFF FFFF FFFF
without 0.5G-byte
TLB mapping,
cache enabled
kseg0
0×8000 0000 0000 0000
0×7FFF FFFF FFFF FFFF
without TLB mapping
(For details, refer to
Figure 3-11.)
xkseg
xkphys
Address error
0×8000 0000
0×7FFF FFFF
0×4000 0100 0000 0000
0×4000 00FF FFFF FFFF
0×4000 0000 0000 0000
0×3FFF FFFF FFFF FFFF
with 2G-byte
TLB mapping
kuseg
with 1T-byte
TLB mapping
xksseg
Address error
0×0000 0 1 0 0 0 0 0 0 0 0 0 0
0×0000 00FF FFFF FFFF
0×0000 0000
Note
0×0000 0000 0000 0000
xkuseg
In the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. For details, refer to VR5000
User’s Manual.
22
with 1T-byte
TLB mapping
Data Sheet U12031EJ2V0DS00
µPD30500
Figure 3-11. Details of xkphys Area
0xBFFF FFFF FFFF FFFF
Address error
0x9800 0010 0000 0000
0 x 9 8 0 0 000F FFFF FFFF
0x9800 0000 0000 0000
0 x 9 7 F F FFFF FFFF FFFF
With 64G bytes
w/o TLB mapping
cache used
Address error
0x9000 0010 0000 0000
0 x 9 0 0 0 000F FFFF FFFF
0x9000 0000 0000 0000
0 x 8 F F F FFFF FFFF FFFF
With 64G bytes
w/o TLB mapping
cache disabled
Address error
0x8800 0010 0000 0000
0 x 8 8 0 0 000F FFFF FFFF
0 x 8 8 0 0 0000 0000 0000
0 x 8 8 F F FFFF FFFF FFFF
With 64G bytes
w/o TLB mapping
cache used
Address error
0 x 8 0 0 0 0010 0000 0000
0 x 8 0 0 0 000F FFFF FFFF
0 x 8 0 0 0 0000 0000 0000
With 64G bytes
w/o TLB mapping
cache used
3.5.2 Address Conversion
Conversion from virtual addresses to physical addresses is performed per page by the built-in TLB
(Translation Lookaside Buffer). The TLB, which is based on a full-associative configuration, has 64 entries on
the virtual address side and 48 entries on the physical address side. The page size can be varied between
4 KB and 16 MB.
In case no TLB entry is hit, a TLB mismatch exception occurs in 32-bit mode; and an XTLB mismatch exception
in 64-bit mode. Use software to reshuffle the TLB contents.
The address conversion is shown below diagramatically.
Data Sheet U12031EJ2V0DS00
23
µPD30500
Figure 3-12. Overview of Address Conversion
y+8
y + 1y
ASID
x+1 x x–1
VPN
0
Virtual address
offset
<1> A virtual address page number (VPN)
is compared with VPN in TLB.
<1>
31
<2> If the two VPNs coincide, a page frame
number (PFN) indicating the higher bits
of a physical address is output to the selector.
<3> If the lowest bit of VPN is 0, an even page is
selected; if the bit is 1, an odd page is selected.
The selected page is output to the higher bits
of the physical address.
0
<4> The offset is output to the lower bits of the physical
bit not via TLB.
<2>
TLB
Selector
x = 12, 14, 16, 18, 20, 22, 24
y = 31 (in 32-bit mode)
63 (in 64-bit mode)
<3>
<4>
Physical
address
35
x
x–1
0
Reading and writing of TLB entries is performed by loading/storing between the TLB entry specified by the
index register or the random register, and the entry Hi, entry Lo1, entry Lo0, and page mask registers.
Figure 3-13. Overview of TLB Operation
Page mask register
Entry Hi register
Entry Lo1 register Entry Lo0 register
Index register
Random register
24
Data Sheet U12031EJ2V0DS00
µPD30500
3.6 CACHES
(1) Instruction cache
The features of the instruction cache are listed below.
• Built-in cache memory
• Capacity: 32 KB
• 2-way set associative method
• Virtual index address
• Physical tag check
(2) Data cache
The features of the data cache are listed below.
• Built-in cache memory
• Capacity: 32 KB
• Write back
• 2-way set associative method
• Virtual index address
• Physical tag check
Data Sheet U12031EJ2V0DS00
25
µPD30500
3.7 EXCEPTION PROCESSING
If an exception is detected, interrupts are inhibited, the operating mode is changed to kernel mode, and a
jump is made to the specified exception handler.
In the case that an exception has occurred, the EPC register retains the restart address for restarting the
execution. The restart address is the address of the instruction that was the cause of the exception, or, in the
case where the instruction was being executed in the branch delay slot, the address of the immediately
preceding branch instruction. On reset, when the NMI occurs, the restart address is retained in the error EPC
register.
Table 3-2. Types of Exceptions
Exception
Abbreviation
Description
Reset
–
Aborts instruction execution and executes a handler on the reset vector.
The internal status is undefined, except some bits of the status and config registers.
Soft reset
–
Aborts instruction execution and executes a handler on the reset vector. The internal
status before soft reset is retained.
NMI
–
Non-maskable interrupt request by the external agent.
Cache error
CE
Occurs when a parity error of system bus or cache is detected.
TLB unmatch
TLBL/TLBS
Occurs if the operating mode is the 32-bit mode and the number of TLB entries
matching the referenced address runs short.
XTLB unmatch
TLBL/TLBS
Occurs if the operating mode is 64-bit mode and the number of TLB entries matching
the referenced address runs short.
TLB invalid
TLBL/TLBS
Occurs if the TLB entry matching the referenced virtual address is invalid.
TLB change
Mod
Occurs when the matching TLB entry is valid but write is disabled (D bit = 0) when a
virtual address is written.
Bus error
IBE/DBE
Occurs if an external agent inputs data accompanied with an error indication to the
CPU due to an abnormality in the external system such as bus time out, or abnormality of address or access type.
Address error
AdEL/AdES
Occurs if an attempt is made to execute the LH, SH/LW/SW, LD, or SD instruction to
the half word/word/double word not at the half word/word/double word boundary, or to
reference a virtual address that cannot be accessed.
Integer overflow
Ov
Occurs if 2’s complement overflow occurs as a result of addition or subtraction.
Trap
Tr
Occurs if the trap condition is true.
System call
Sys
Occurs when the SYSCALL instruction is executed.
Breakpoint
Bp
Occurs when the BREAK instruction is executed.
Reserved
instruction
RI
Occurs when an instruction whose op code (bits 31-26) is undefined, or the
SPECIAL instruction whose op code (bits 5-0) is undefined is executed.
Coprocessor
unusable
CpU
Occurs if the coprocessor instruction is executed when the corresponding
coprocessor use enable bit is not set.
Floating point
FPE
Occurs if a floating-point operation exception occurs in the floating-point operation
coprocessor and when the corresponding enable bit is set.
Interrupt
Int
Occurs when one of the eight interrupt sources becomes active.
The exception vectors and their offset values in the 64-bit and 32-bit modes are shown in the tables below.
26
Data Sheet U12031EJ2V0DS00
µPD30500
Table 3-3. Base Address of Exception Vector in 64-Bit Mode
Vector Base Address
Vector Offset
Cold reset, software reset, NMI
0xFFFF FFFF BFC0 0000
(BEV bit is automatically set to 1.)
0x0000
TLB unmatch, EXL = 0
0xFFFF FFFF 8000 0000 (BEV = 0)
0x0000
XTLB unmatch, EXL = 0
0xFFFF FFFF BFC0 0200 (BEV = 1)
0x0080
Others
0x0180
Table 3-4. Base Address of Exception Vector in 32-Bit Mode
Vector Base Address
Vector Offset
Cold reset, software reset, NMI
0xBFC0 0000
(BEV bit is automatically set to 1.)
0x0000
TLB unmatch, EXL = 0
0x8000 0000 (BEV = 0
0x0000
XTLB unmatch, EXL = 0
0xBFC0 0200 (BEV = 1)
0x0080
Others
0x0180
Data Sheet U12031EJ2V0DS00
27
µPD30500
4.
FPU INTERNAL ARCHITECTURE
4.1 INTERNAL FUNCTION BLOCK
Figure 4-1 shows the internal block of the FPU.
The FPU conforms to “IEEE2 Floating-Point Operation Standard” of ANSI/IEEE Standard 754-1985.
Figure 4-1. Internal Block of FPU
VR5000
internal data bus
64
FP control register
64
64
FP pipeline control
FP addition
+
FP subtraction
+
FP conversion
FP
multiplication
64
64
64
64
64
64
64
FP register file
28
Data Sheet U12031EJ2V0DS00
FP division
+
FP square root
µPD30500
4.2 FPU REGISTERS
(1) Floating-point general-purpose registers (FGR)
These are the 32 physical general-purpose registers that can be accessed directly. The bit length varies
depending on the contents of the status register FR bit.
(2) Floating-point registers (FPR)
These are the logical 64-bit registers, that hold floating-point values while floating-point arithmetic is being
performed. Their number varies depending on the contents of the status register FR bit.
(3) Floating-point control registers (FCR)
The following two FCR registers are provided.
(a) Control/status register (FCR31)
This register controls and monitors exceptions, holds the arithmetic comparison results, and sets the
rounding mode.
(b) Processor/revision register (FCR0)
Holds the FPU’s revision information.
Data Sheet U12031EJ2V0DS00
29
µPD30500
Figure 4-2. FPU Registers
(a) FGR and FPR
(i) When FR bit = 0
Floating-point register
(FPR)
(ii) When FR bit = 1
Floating-point
general-purpose register (FGR)
31
0
Floating-point register
Floating-point
(FPR)
general-purpose register (FGR)
63
0
Lower
FGR0
FPR0
FGR0
Higher
FGR1
FPR1
FGR1
Lower
FGR2
FPR2
FGR2
Higher
FGR3
FPR3
FGR3
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
Lower
FGR28
FPR28
FGR28
Higher
FGR29
FPR29
FGR29
Lower
FGR30
FPR30
FGR30
Higher
FGR31
FPR31
FGR31
FPR0
FPR2
·
·
·
·
·
·
FPR28
FPR30
(b) FCR
(i) Control/status register (FCR31)
31
0
(ii) Processor/revision register (FCR0)
31
0
4.3 DATA FORMATS
(1) Floating-point format
The FPU supports 32-bit (single precision) and 64-bits (double precision) IEEE754 floating-point arithmetic.
(2) Fixed-point format
Fixed-point values are computed in 2’s compliment format.
30
Data Sheet U12031EJ2V0DS00
µPD30500
5.
INTERFACES
5.1 SYSTEM INTERFACE
The processor’s input/output timings are as follows:
• The processor output starts to change at the rising edge of SClock.
• The processor input is latched at the trailing edge of SClock.
There are the following two system interface buses.
• SysAD (0:63): This bus is for address and data transfer.
• SysCmd (0:7): This bus is for command and data identifier transfer.
The SysAD and SysCmd buses are bidirectional and driven by the processor or an external agent. Depending on
the direction, they are placed in either of the following two statuses.
• Master status: The bus is driven by the processor, because a processor request is issued.
• Slave status: The bus is driven by an external agent, because an external request is issued.
Depending on the information included in the SysAD bus, two cycles occur as follows.
• Address cycle: The SysAD bus contains a valid address.
• Data cycle: The SysAD bus contains valid data.
The interface control signals are briefly described below.
• ValidIn :
Activate this signal when an external agent is in the master status and the SysAD and SysCmd
• ValidOut :
This signal is activated when the processor is in the master status and the SysAD and SysCmd
buses are valid.
buses are valid.
• ExtRqst :
Activate this signal when an external agent requests the right to use the interface.
• Release :
This signal is activated when the processor places the system interface in the slave status.
• WrRdy
:
Activate this signal when an external agent becomes capable of accepting the processor write
• RdRdy
:
request.
Activate this signal when an external agent becomes capable of accepting the processor read
request.
5.1.1 System Interface Requests
The following requests are supported by the system interface.
Request
Outline
Data Unit
Processor read request
Read request to main memory or I/O
1 to 8 bytes (single);
Processor write request
Write request to main memory or I/O
8 words (block)
External write request
Interrupt request from the system bus
2 words
As an example of the system interface request protocol, Figure 5-1 shows the timing between a processor block
read request and the response.
Data Sheet U12031EJ2V0DS00
31
µPD30500
Figure 5-1. Processor Block Read Request and Subsequent Read Response
Master
SysCycle
Processor
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
<12>
SysClock (Input)
SysAD (0 : 63) (I/O)
Addr
SysCmd (0 : 8) (I/O)
Write NData NData NData NEOD
Data0 Data1 Data2 Data3
ValidOut (Output)
WrRdy (Input)
Remark
L
The numbers in this figure are not fixed.
5.1.2 Control of Data Transfer Rate
The system interface of the VR5000 can transfer word data in one cycle. However, the rate at which data is
transferred to the processor is determined by the data transfer capability of the external agent.
The external agent can transfer data to the processor at any transfer rate. The processor decodes the contents
of the SysCmd bus, including a data identifier, in a cycle in which the ValidIn signal is active and the data is valid.
The processor continues receiving the data until it detects the last data transfer.
The transfer rate at which data is to be transferred from the processor to the external agent is set by input from
the ModeIn pin at reset. The pattern of the data transfer rate is expressed by a combination of symbols “D” and “X”,
where “D” indicates the data transfer cycle, and “X” indicates an unused cycle. This transfer pattern indicates an
appropriate data transfer rate by a data cycle and unused cycle.
Example DXX: Transfers 4-word data every 3 cycles
In the VR5000, there are nine data transfer rates. For details, refer to Table 5-1 Boot Mode.
Figure 5-2 shows the timing of a processor block read request followed by a read response where the transfer
pattern is DD×.
Figure 5-2. Processor Block Read Request Followed by Read Response
Processor
Master
SysCycle
<1>
<2>
<3>
External Agent
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
<12>
<13>
SysClock (Input)
SysAD (0 : 63) (I/O)
Addr
Data0 Data1
Data2 Data3
SysCmd (0 : 8) (I/O)
Read
NData NData
NData NEOD
ValidOut (Output)
ValidIn (Input)
ExtRqst (Input)
H
Release (Output)
Remarks 1. The numbers in the figure are not fixed.
2. The number of clocks at the portion omitted is undefined.
32
Data Sheet U12031EJ2V0DS00
<14>
µPD30500
5.1.3 Clock Interface
The clock signals used by the VR5000 are described below.
(1) SysClock (input)
The VR5000’s internal clock is all generated and operate based on the SysClock.
(2) PClock (internal)
This is the basic clock for pipeline operation. All the internal circuits use this clock.
The multiplication rate from SysClock to PClock is set by input from the ModeIn pin at power-ON reset/cold reset.
The multiplication rate is selected from an integer multiple of 2 to 8.
Figure 5-3. Clock Interface
SysClock
PLL
System
interfaceNote
PClock
Internal device
Note
The frequency of the system interface is the same as SysClock.
Data Sheet U12031EJ2V0DS00
33
µPD30500
5.2 SECONDARY CACHE INTERFACE
The VR5000 has a secondary cache control circuit and an external secondary cache can be connected.
The secondary cache interface consists of a 64-bit address/data bus that is also used as an external bus, a 17bit tag bus, and SRAM control signals.
The secondary cache interface control signals are briefly explained below.
• ScCLR
: This signal is activated when the processor invalidates the cache.
• ScCWE (0:1) : This signal is activated when the processor writes data to the cache.
• ScDCE (0:1) : This signal is activated when the processor accesses the data RAM of the cache.
• ScDOE
: Activate this signal when the external agent enables the CPU and secondary cache to output
data.
• ScLine (0:15) : The processor uses these signals to output cache line index.
• ScMatch
: The external agent must activate this signal when a hit occurs in the secondary cache.
• ScTCE
: This signal is activated when the processor accesses the tag RAM.
• ScTDE
: This signal is activated when the processor reads the data of the tag to the tag RAM.
• ScTOE
: This signal is activated when the processor enables output of the data of the tag.
• ScWord (0:1) : This is a bus used by the processor or external agent to determine the double word of a cache
index.
• ScValid
: This signal is activated by the processor or external agent to probe a cache tag.
(1) Read cycle parameter
The read cycle is started when the external bus is driven and when ScTCE, ScTDE, and ScDCE are activated.
(2) Write cycle parameter
The write cycle is started when the external bus is driven and when ScTCE, ScTDE, and ScCWE are activated.
ScDCE is activated one cycle after.
34
Data Sheet U12031EJ2V0DS00
µPD30500
5.3 SETTING OF BOOT MODE
The basic mode of the processor is initialized when a 256-bit initialization bit stream is read from the ModeIn pin
at power-ON reset or cold reset.
The first rising edge of ModeClock is generated 256SysClock cycles after VDDOk has been activated. After that,
the processor reads the initialization bit stream at the rising edge of ModeClock.
Table 5-1 shows the correspondence between the serial bit of the initialization bit stream and mode setting.
Table 5-1. Boot Mode (1/2)
Serial Bit
0
1:4
Mode Setting
RFU: Fixed to 0.
XmitDatPat: Specifies system interface data rate for block write only.
0
: DDDD
1
: DD×DD×
2
: DD××DD××
3
: D×D×D×D×
4
: DD×××DD×××
5
: DD××××DD××××
6
: D××D××D××D××
7
: DD××××××DD××××××
8
: D×××D×××D×××D×××
9-15 : RFU
5:7
SysCkRatio: Division ratio between PClock and SysClock.
0 : 2 divisions
1 : 3 divisions
2 : 4 divisions
3 : 5 divisions
4 : 6 divisions
5 : 7 divisions
6 : 8 divisions
7 : RFU
8
EndBit: Specifies byte ordering.
0 : Little endian ordering
1 : Big endian ordering
9 : 10
Non-Block Write: Determines processing mode of non-block write.
0 : VR4x00 compatible
1 : RFU
2 : Pipeline write
3 : Write re-issuance
11
TmrIntEn: Disables timer interrupt.
0 : Enables timer interrupt.
1 : Disables timer interrupt.
Data Sheet U12031EJ2V0DS00
35
µPD30500
Table 5-1. Boot Mode (2/2)
Serial Bit
12
Mode Setting
Enables secondary cache.
0 : Disables secondary cache.
1 : Enables secondary cache.
13:14
DrvOut: Output driver slew rate.
0 : 67%
1 : 50% (lowest)
2 : 100% (highest)
3 : 83%
15
16:17
RFU : Fixed to 0.
Secondary cache size.
0: 512K bytes
1: 1M bytes
2: 2M bytes
3: RFU
36
18:19
RFU: Fixed to 0.
20
RFU: Fixed to 1.
21:32
RFU: Fixed to 0.
33
RFU: Fixed to 1.
34:36
RFU: Fixed to 0.
37
RFU: Fixed to 1.
38:255
RFU: Fixed to 0.
Data Sheet U12031EJ2V0DS00
µPD30500
6. INTERNAL/EXTERNAL CONTROL FUNCTIONS
6.1 RESET FUNCTION
Reset can be executed in three ways: power-ON reset, cold reset, and warm reset.
Cold reset and warm reset is reset with power supplied.
The internal status of the processor is initialized by reset. At warm reset, however, only the system interface and
the contents of the cache memory become undefined, and the other internal statuses are not initialized and the status
immediately before reset is retained.
6.1.1 Power-ON Reset and Cold Reset
Power-ON reset or cold reset is executed when both the ColdReset and Reset signals are asserted. Data of 256
bits input from the ModeIn pin is received during reset, and the internal status of the processor is initialized (for the
setting, refer to 5.3 SETTING OF BOOT MODE).
6.1.2 Warm Reset
Warm reset is executed when the Reset signal is asserted. No initial status is input from the ModeIn pin, and the
status immediately before reset is retained.
6.2 INTERRUPT FUNCTIONS
There are two major categories of interrupt requests as follows:
• Maskable interrupt requests
• Non-maskable interrupt (NMI) requests
(1) Maskable interrupt requests
These interrupts undergo mask control. The mask processing is performed by the status register. (Each interrupt
can be handled individually, or interrupts can be handled as a group.)
There is no priority among interrupts.
(a) Hardware interrupt request (6 sources)
When an external write request or Int(0:5) signals are activated, IP2 through IP7 of the cause register are
set, and the interrupt requests are accepted.
The IP7 bit is set if the timer interrupt request becomes active when the timer interrupt request is enabled.
If this bit is set, however, which of Int5 input or timer interrupt request is responsible for the setting cannot
be identified.
(b) Software interrupt request (2 sources)
Accepted by setting the cause register IP0 and IP1 bits.
(c) Timer interrupt request (1 source)
If the value of the count register becomes equal to that of the compare register, the cause register IP7 bit
is set and the interrupt is accepted.
Whether the timer interrupt request is used is determined by input from the ModeIn pin at power-ON reset
or cold reset.
If the Int5 signal is active even while the timer interrupt request is enabled, the IP7 bit is set. If this bit is
set, however, which of Int5 input or timer interrupt request is responsible for the setting cannot be identified.
Data Sheet U12031EJ2V0DS00
37
µPD30500
(2) NMI request (1 source)
This interrupt request does not undergo mask control. The interrupt can be accepted by activating the external
write request or NMI signal.
6.3 STANDBY MODE
Standby mode is used to reduce the internal power consumption while the CPU is in the standby state.
Execute the WAIT instruction to enter the standby mode. If the SysAD bus is in the idle state when the execution
of the WAIT instruction is completed up to the W stage, the internal clock is shut down and the pipeline is stopped.
However, the PLL, internal timer, clock for interrupt requests and reset input (Int (5:0), NMI, ExtRqst, Reset,
ColdReset), and output clock (ModeClock) continue operating. If the SysAD bus is not in the idle state when the WAIT
instruction completes up to the W stage, the WAIT instruction is treated as NOP and the standby mode is not entered.
To resume from the standby mode, generate an interrupt request (activate Int (5:0), NMI, or ExtRqst) or reset
(activate Reset or ColdReset). The standby mode is terminated when a timer interrupt request is generated in the
processor.
38
Data Sheet U12031EJ2V0DS00
µPD30500
7.
INSTRUCTION SET
The VR5000’s instructions consist of 1 word (32 bits) located on a word boundary. The instruction format has three
types as shown in Figure 7-1. Decoding of instructions is simplified by having only three format types. Complicated
and infrequently used operations and addressing modes are realized by compilers.
7.1 INSTRUCTION FORMAT
VR5000’s instruction formats are as shown below.
Figure 7-1. CPU Instruction Formats
I-type (Immediate format)
31
26 25
op
21 20
rs
16 15
0
rt
immediate
J-type (Jump format)
26 25
31
0
op
target
R-type (Register format)
31
26 25
op
21 20
rs
16 15
rt
11 10
rd
6
sa
op
6-bit instruction code
rs
5-bit source register specifier
rt
5-bit target (source/destination) register, or branch condition
immediate
16-bit immediate value, branch displacement, or address displacement
target
26-bit unconditional branch target address
rd
5-bit destination register specifier
sa
5-bit shift quantity
funct
6-bit function field
cc
Floating-point condition code
tf
1-bit truth value
5
0
funct
7.2 LIST OF CPU INSTRUCTION SET
The VR5000’s CPU instructions are classified into two categories: the instruction set (ISA: Instruction Set
Architecture) common to all VR series processors and the instruction set (extended ISA) executed on the VR4000
series. The instruction set is listed below.
Data Sheet U12031EJ2V0DS00
39
µPD30500
Table 7-1. CPU Instruction Set: MIPS I (1/2)
Instructions
Description
Load/store instruction
op
Format
base
rt
offset
LB
Load Byte
LB
rt, offset (base)
LBU
Load Byte Unsigned
LBU
rt, offset (base)
LH
Load Halfword
LH
rt, offset (base)
LHU
Load Halfword Unsigned
LHU
rt, offset (base)
LW
Load Word
LW
rt, offset (base)
LWL
Load Word Left
LWL
rt, offset (base)
LWR
Load Word Right
LWR
rt, offset (base)
SB
Store Byte
SB
rt, offset (base)
SH
Store Halfword
SH
rt, offset (base)
SW
Store Word
SW
rt, offset (base)
SWL
Store Word Left
SWL
rt, offset (base)
SWR
Store Word Right
SWR
rt, offset (base)
ALU immediate instruction
op
rs
rt
offset
ADDI
Add Immediate
ADDI
rt, rs, immediate
ADDIU
Add Immediate Unsigned
ADDIU
rt, rs, immediate
SLTI
Set On Less Than Immediate
SLTI
rt, rs, immediate
SLTIU
Set On Less Than Immediate Unsigned
SLTIU
rt, rs, immediate
ANDI
And Immediate
ANDI
rt, rs, immediate
ORI
Or Immediate
ORI
rt, rs, immediate
XORI
Exclusive Or Immediate
XORI
rt, rs, immediate
LUI
Load Upper Immediate
LUI
rt, immediate
3-operand type instruction
op
rs
rt
rd
sa
funct
ADD
Add
ADD
rd, rs, rt
ADDU
Add Unsigned
ADDU
rd, rs, rt
SUB
Subtract
SUB
rd, rs, rt
SUBU
Subtract Unsigned
SUBU
rd, rs, rt
SLT
Set On Less Than
SLT
rd, rs, rt
SLTU
Set On Less Than Unsigned
SLTU
rd, rs, rt
AND
And
AND
rd, rs, rt
OR
Or
OR
rd, rs, rt
XOR
Exclusive Or
XOR
rd, rs, rt
NOR
Nor
NOR
rd, rs, rt
Shift instruction
op
rs
rt
rd
sa
funct
SLL
Shift Left Logical
SLL
rd, rt, sa
SRL
Shift Right Logical
SRL
rd, rt, sa
SRA
Shift Right Arithmetic
SRA
rd, rt, sa
SLLV
Shift Left Logical Variable
SLLV
rd, rt, rs
SRLV
Shift Right Logical Variable
SRLV
rd, rt, rs
SRAV
Shift Right Arithmetic Variable
SRAV
rd, rt, rs
40
Data Sheet U12031EJ2V0DS00
µPD30500
Table 7-1. CPU Instruction Set: MIPS I (2/2)
Instructions
Description
Multiplication/division instruction
Format
op
rs
rt
rd
sa
funct
MULT
Multiply
MULT
rs, rt
MULTU
Multiply Unsigned
MULTU
rs, rt
DIV
Divide
DIV
rs, rt
DIVU
Divide Unsigned
DIVU
rs, rt
MFHI
Move From HI
MFHI
rd
MFLO
Move From LO
MFLO
rd
MTHI
Move To HI
MTHI
rs
MTLO
Move To LO
MTLO
rs
Jump instruction (1)
op
target
J
Jump
J
target
JAL
Jump And Link
JAL
target
Jump instruction (2)
op
rs
rt
rd
sa
funct
JR
Jump Register
JR
rs
JALR
Jump And Link Register
JALR
rs
JALR
rs, rd
Branch instruction (1)
op
rs
rt
offset
BEQ
Branch On Equal
BEQ
rs, rt, offset
BNE
Branch On Not Equal
BNE
rs, rt, offset
BLEZ
Branch On Less Than Or Equal To Zero
BLEZ
rs, offset
BGTZ
Branch On Greater Than Zero
BGTZ
rs, offset
Branch instruction (2)
REGIMM
rs
sub
offset
BLTZ
Branch On Less Than Zero
BLTZ
rs, offset
BGEZ
Branch On Greater Than Or Equal to Zero
BGEZ
rs, offset
BLTZAL
Branch On Less Than Zero And Link
BLTZAL
rs, offset
BGEZAL
Brandh On Greater Than Or Equal To Zero And Link
BGEZAL
rs, offset
Special instruction
SPECIAL
rs
rt
rd
sa
SYSCALL
System Call
SYSCALL
BREAK
Breakpoint
BREAK
Coprocessor instruction (1)
op
base
rt
funct
offset
LWCz
Load Word To Coprocessor z
LWCz
rt, offset (base)
SWCz
Store Word From Coprocessor z
SWCz
rt, offset (base)
Coprocessor instruction (2)
COPz
COPz
CO
Coprocessor z Operation
Data Sheet U12031EJ2V0DS00
cofun
COPz
cofun
41
µPD30500
Table 7-2. CPU Instruction Set: MIPS II
Instructions
Description
Load/store instruction
op
Format
base
rt
offset
LL
Load Linked
LL
rt, offset (base)
SC
Store Conditional
SC
rt, offset (base)
Branch instruction (1)
op
rs
rt
offset
BEQL
Branch On Equal Likely
BEQL
rs, rt, offset
BNEL
Branch On Not Equal Likely
BNEL
rs, rt, offset
BLEZL
Branch On Less Than Or Equal To Zero Likely
BLEZL
rs, offset
BGTZL
Branch On Greater Than Zero Likely
BGTZL
rs, offset
Branch instruction (2)
REGIMM
rs
sub
offset
BLTZL
Branch On Less Than Zero Likely
BLTZL
rs, offset
BGEZL
Branch On Greater Than Or Equal To Zero Likely
BGEZL
rs, offset
BLTZALL
Branch On Less Than Zero And Link Likely
BLTZALL
rs, offset
BGEZALL
Branch On Greater Than Or Equal To Zero And Link Likely
BGEZALL
rs, offset
Exception instruction
SPECIAL
rs
rt
rd
sa
funct
TGE
Trap If Greater Than Or Equal
TGE
rs, rt
TGEU
Trap If Greater Than Or Equal Unsigned
TGEU
rs, rt
TLT
Trap If Less Than
TLT
rs, rt
TLTU
Trap If Less Than Unsigned
TLTU
rs, rt
TEQ
Trap If Equal
TEQ
rs, rt
TNE
Trap If Not Equal
TNE
rs, rt
Exception immediate instruction
REGIMM
rs
sub
immediate
TGEI
Trap If Greater Than Or Equal Immediate
TGEI
rs, immediate
TGEIU
Trap If Greater Than Or Equal Immediate Unsigned
TGEIU
rs, immediate
TLTI
Trap If Less Than Immediate
TLTI
rs, immediate
TLTIU
Trap If Less Than Immediate Unsigned
TLTIU
rs, immediate
TEQI
Trap If Equal Immediate
TEQI
rs, immediate
TNEI
Trap If Not Equal Immediate
TNEI
rs, immediate
Special instruction
SYNC
Coprocessor instruction
SPECIAL
rs
rt
Synchronize
rd
sa
funct
SYNC
op
base
rt
offset
LDCz
Load Doubleword To Coprocessor z
LDCz
rt, offset (base)
SDCz
Store Doubleword From Coprocessor z
SDCz
rt, offset (base)
42
Data Sheet U12031EJ2V0DS00
µPD30500
Table 7-3. CPU Instruction Set: MIPS III
Instructions
Description
Load/store instruction
op
Format
base
rt
offset
LD
Load Doubleword
LD
rt, offset (base)
LDL
Load Doubleword Left
LDL
rt, offset (base)
LDR
Load Dolubleword Right
LDR
rt, offset (base)
LLD
Load Linked Doubleword
LLD
rt, offset (base)
LWU
Load Word Unsigned
LWU
rt, offset (base)
SCD
Store Conditional Doubleword
SCD
rt, offset (base)
SD
Store Doubleword
SD
rt, offset (base)
SDL
Store Doubleword Left
SDL
rt, offset (base)
SDR
Store Doubleword Right
SDR
rt, offset (base)
ALU immediate instruction
op
rs
rt
immediate
DADDI
Doubleword Add Immediate
DADDI
rt, rs, immediate
DADDIU
Doubleword Add Immediate Unsigned
DADDIU
rt, rs, immediate
3-operand type instruciton
op
rs
rt
rd
sa
funct
DADD
Doubleword Add
DADD
rd, rs, rt
DADDU
Doubleword Add Unsigned
DADDU
rd, rs, rt
DSUB
Doubleword Subtract
DSUB
rd, rs, rt
DSUBU
Doubleword Subtract Unsigned
DSUBU
rd, rs, rt
Shift instruction
op
rs
rt
rd
sa
funct
DSLL
Doubleword Shift Left Logical
DSLL
rd, rt, sa
DSRL
Doubleword Shift Right Logical
DSRL
rd, rt, sa
DSRA
Doubleword Shift Right Arithmetic
DSRA
rd, rt, sa
DSLLV
Doubleword Shift Left Logical Variable
DSLLV
rd, rt, rs
DSRLV
Doubleword Shift Right Logical Variable
DSRLV
rd, rt, rs
DSRAV
Doubleword Shift Right Arithmetic Variable
DSRAV
rd, rt, rs
DSLL32
Doubleword Shift Left Logical +32
DSLL32
rd, rt, sa
DSRL32
Doubleword Shift Right Logical +32
DSRL32
rd, rt, sa
DSRA32
Doubleword Shift Right Arithmetic +32
DSRA32
rd, rt, sa
Multiplication/division instruction
op
rs
rt
rd
sa
funct
DMULT
Doubleword Multiply
DMULT
rs, rt
DMULTU
Doubleword Multiply Unsigned
DMULTU
rs, rt
DDIV
Doubleword Divide
DDIV
rs, rt
DDIVU
Doubleword Divide Unsigned
DDIVU
rs, rt
Data Sheet U12031EJ2V0DS00
43
µPD30500
Table 7-4. CPU Instruction Set: MIPS IV
Instructions
Description
3-operand type instruction
op
Format
rs
rt
rd
sa
funct
MOVN
Move Conditional On Not Zero
MOVN
rd, rs, rt
MOVZ
Move Conditional On Zero
MOVZ
rd, rs, rt
Prefetch instruction
PREFNote
Note
44
op
base
hint
Prefetch
offset
PREF
This instruction is treated as a NOP instruction by the VR5000.
Data Sheet U12031EJ2V0DS00
hint, offset (base)
µPD30500
7.3 LIST OF FPU INSTRUCTION SET
All FPU instructrions are 32 bits and are aligned on word boundaries.
Tables 7-5 through 7-8 show the FPU instruction set.
Table 7-5. FPU Instruction Set: MIPS I
Instructions
Description
Load/store instruction
op
Format
base
ft
offset
LWC1
Load Word To FPU
LWC1
ft, offset (base)
SWC1
Store Word From FPU
SWC1
ft, offset (base)
Transfer instruction
COP1
sub
rt
fs
0
MTC1
Move Word To FPU
MTC1
rt, fs
MFC1
Move Word From FPU
MFC1
rt, fs
CTC1
Move Control Word To FPU
CTC1
rt, fs
CFC1
Move Control Word From FPU
CFC1
rt, fs
Conversion instruction
COP1
fmt
0
fs
fd
funct
CVT. S. fmt
Floating-point Convert To Single Floating-point Format
CVT. S. fmt
fd, fs
CVT. D. fmt
Floating-point Convert To Double Floating-point Format
CVT. D. fmt
fd, fs
CVT. W. fmt
Floating-point Convert To Single Fixed-point Format
CVT. W. fmt
fd, fs
Arithmetic operation instruction
COP1
fmt
ft
fs
fd
funct
ADD. fmt
Floating-point Add
ADD. fmt
fd, fs, ft
SUB. fmt
Floating-point Subtract
SUB. fmt
fd, fs, ft
MUL. fmt
Floating-point Multiply
MUL. fmt
fd, fs, ft
DIV. fmt
Floating-point Divide
DIV. fmt
fd, fs, ft
ABS. fmt
Floating-point Absolute Value
ABS. fmt
fd, fs
MOV. fmt
Floating-point Move
MOV. fmt
fd, fs
NEG. fmt
Floating-point Negate
NEG. fmt
fd, fs
Compare instruction
C. cond. fmt
COP1
fmt
ft
fs
Floating-point Compare
FPU branch instruction
cc
0
funct
C. cond. fmt
COP1
BC
cc
0
cc, fs, ft
offset
BC1T
Branch On FPU True
BC1T
cc, offset
BC1F
Bfranch On FPU False
BC1F
cc, offset
Data Sheet U12031EJ2V0DS00
45
µPD30500
Table 7-6. FPU Instruction Set: MIPS II
Instructions
Description
Load/store instruction
op
Format
base
ft
offset
LDC1
Load Doubleword To FPU
LDC1
ft, offset (base)
SDC1
Store Doubleword From FPU
SDC1
ft, offset (base)
Conversion instruction
COP1
fmt
0
fs
fd
funct
ROUND. W. fmt
Floating-point Round To Single Fixed-point Format
ROUND. W. fmt
fd, fs
TRUNC. W. fmt
Floating-point Truncate To Single Fixed-point Format
TRUNC. W. fmt
fd, fs
CEIL. W. fmt
Floating-point Ceiling To Single Fixed-point Format
CEIL. W. fmt
fd, fs
FLOOR. W. fmt
Floating-point Floor To Single Fixed-point Format
FLOOR. W. fmt
fd, fs
Arithmetic operation instruction
SQRT. fmt
COP1
fmt
ft
fs
Floating-point Square Root
fd
funct
SQRT. fmt
FPU branch instruction
COP1
BC
cc
0
fd, fs
offset
BC1TL
Branch On FPU True Likely
BC1TL
cc, offset
BC1FL
Branch On FPU False Likely
BC1FL
cc, offset
Table 7-7. FPU Instruction Set: MIPS III
Instructions
Description
Transfer instruction
COP1
Format
sub
rt
fs
0
DMTC1
Doubleword Move To FPU
DMTC1
rt, fs
DMFC1
Doubleword Move From FPU
DMFC1
rt, fs
Conversion instruction
COP1
fmt
0
fs
fd
funct
CVT. S. fmt
Floating-point Convert To Single Floating-point Format
CVT. S. fmt
fd, fs
CVT. D. fmt
Floating-point Convert To Double Floating-point Format
CVT. D. fmt
fd, fs
CVT. L. fmt
Floating-point Convert To Long Fixed-point Format
CVT. L. fmt
fd, fs
ROUND. L. fmt
Floating-point Round To Long Fixed-point Format
ROUND. L. fmt
fd, fs
TRUNC. L. fmt
Floating-point Truncate To Long Fixed-point Format
TRUNC. L. fmt
fd, fs
CEIL. L. fmt
Floating-point Ceiling To Long Fixed-point Format
CEIL. L. fmt
fd, fs
FLOOR. L. fmt
Floating-point Floor To Long Fixed-point Format
FLOOR. L. fmt
fd, fs
46
Data Sheet U12031EJ2V0DS00
µPD30500
Table 7-8. FPU Instruction Set: MIPS IV
Instructions
Description
Load index instruction
op
Format
base
index
0
fd
funct
LWXC1
Load Word Indexed To Floating-point
LWXC1
fd, index (base)
LDXC1
Load Doubleword Indexed To Floating-point
LDXC1
fd, index (base)
Store index instruction
op
base
index
fs
0
funct
SWXC1
Store Word Indexed From Floating-point
SWXC1
fs, index (base)
SDXC1
Store Doubleword indexed From Floating-point
SDXC1
fs, index (base)
Conversion instruction
COP1
fmt
0
fs
fd
funct
RECIP. fmt
Reciprocal Approximation
RECIP. fmt
fd, fs
RSQRT. fmt
Reciprocal Square Root Approximation
RSQRT. fmt
fd, fs
Arithmetic operation instruction (1)
COP1
fmt
ft
fs
fd
funct
MSUB. fmt
Floating-point Multiply Subtract
MSUB. fmt
fd, fr, fs, ft
NMSUB. fmt
Floating-point Negative Multiply Subtract
NMSUB. fmt
fd, fr, fs, ft
MADD. fmt
Floating-point Multiply Add
MADD. fmt
fd, fr, fs, ft
NMADD. fmt
Floating-point Negative Multiply Add
NMADD. fmt fd, fr, fs, ft
MOVN. fmt
Floating-point Move Conditional On Not Zero
MOVN. fmt
fd, fs, rt
MOVZ. fmt
Floating-point Move Conditional On Zero
MOVZ. fmt
fd, fs, rt
Arithmetic operation instruction (2)
COP1
fmt
cc
0
fs
fd
funct
MOVF. fmt
Floating-point Move Conditional On FPU False
MOVF. fmt
fd, fs, cc
MOVT. fmt
Floating-point Move Conditional On FPU True
MOVT. fmt
fd, fs, cc
Compare instruction
C. cond. fmt
COP1
fmt
ft
fs
Floating-point Compare
FPU branch instruction
cc
0
funct
C. cond. fmt
COP1
BC
cc
0
cc, fs, ft
offset
BC1T
Branch On FPU True
BC1T
cc, offset
BC1F
Branch On FPU False
BC1F
cc, offset
BC1TL
Branch On FPU True Likely
BC1TL
cc, offset
BC1FL
Branch On FPU False Likely
BC1FL
cc, offset
Conditional transfer instruction
op
rs
cc
tf
rd
funct
MOVF
Move Conditional On FPU False
MOVF
rd, rs, cc
MOVT
Move Conditional On FPU True
MOVT
rd, rs, cc
Prefetch instruction
PREFXNote
Note
op
base
index
Prefetch Indexed
hint
0
PREFX
funct
hint, index (base)
This instruction is treated as a NOP instruction by the VR5000.
Data Sheet U12031EJ2V0DS00
47
µPD30500
7.4
DELAY OF INSTRUCTION
Table 7-9 shows the delay of the integer operation instruction.
For the details of each instruction, refer to VR5000 User’s Manual.
Table 7-9. Integer Operation Instruction Delay
Pipeline Clock Cycle
Instruction Type
48
Delay
Delay if same instruction is repeated
MULT
5
4
MULTU
5
4
DIV
36
36
DIVU
36
36
DMULT
9
8
DMULTU
9
8
DDIV
68
68
DDIVU
68
68
Data Sheet U12031EJ2V0DS00
µPD30500
Table 7-10. Floating-Point Instruction Delay (1/2)
Instruction Type
Pipeline Clock Cycle
Single
Double
Delay
Delay if same
instruction is
repeated
ADD. fmt
4
SUB. fmt
Word
Delay
Delay if same
instruction is
repeated
1
4
4
1
MSUB. fmt
4
NMSUB. fmt
MUL. fmt
Long word
Delay
Delay if same
instruction is
repeated
Delay
Delay if same
instruction is
repeated
1
—
—
—
—
4
1
—
—
—
—
1
5
2
—
—
—
—
4
1
5
2
—
—
—
—
4
1
5
2
—
—
—
—
MADD. fmt
4
1
5
2
—
—
—
—
NMADD. fmt
4
1
5
2
—
—
—
—
DIV. fmt
21
19
36
34
—
—
—
—
SQRT. fmt
21
19
36
34
—
—
—
—
ABS. fmt
1
1
1
1
—
—
—
—
MOV. fmt
1
1
1
1
—
—
—
—
MOVN. fmt
1
1
1
1
—
—
—
—
MOVZ. fmt
1
1
1
1
—
—
—
—
NEG. fmt
1
1
1
1
—
—
—
—
MOVF. fmt
1
1
1
1
—
—
—
—
MOVT. fmt
1
1
1
1
—
—
—
—
3Note 2
CVT. S. fmt
—
—
4
1
6
3
6Note 2
CVT. D. fmt
4
1
—
—
4
1
4Note 2
1Note 2
CVT. L. fmt
4
1
4
1
—
—
—
—
4
1
4
1
—
—
—
—
4
1
4
1
—
—
—
—
ROUND. W. fmt
4
1
4
1
—
—
—
—
TRUNC. L. fmt
4
1
4
1
—
—
—
—
TRUNC. W. fmt
4
1
4
1
—
—
—
—
CEIL. L. fmt
4
1
4
1
—
—
—
—
CEIL. W. fmt
4
1
4
1
—
—
—
—
FLOOR. L. fmt
4
1
4
1
—
—
—
—
FLOOR. W. fmt
4
1
4
1
—
—
—
—
RECIP. fmt
21
19
36
34
—
—
—
—
RSQRT. fmt
38
36
68
66
—
—
—
—
C. cond. fmt
1
1
1
1
—
—
—
—
BC1T
1
1
1
1
—
—
—
—
BC1F
1
1
1
1
—
—
—
—
BC1TL
1
1
1
1
—
—
—
—
BC1FL
1
1
1
1
—
—
—
—
LWC1
2
1
2
1
—
—
—
—
CVT. W. fmt
ROUND. L.
fmtNote 1
Notes 1. Trapped if the length is 53 bits or longer.
2. Trapped if the length is 52 bits or longer.
Data Sheet U12031EJ2V0DS00
49
µPD30500
Table 7-10. Floating-Point Instruction Delay (2/2)
Instruction Type
Pipeline Clock Cycle
Single
Double
Delay
Delay if same
instruction is
repeated
LDC1
2
LWXC1
Word
Delay
Delay if same
instruction is
repeated
1
2
3
2
LDXC1
3
SWC1
SDC1
Long word
Delay
Delay if same
instruction is
repeated
Delay
Delay if same
instruction is
repeated
1
—
—
—
—
3
2
—
—
—
—
2
3
2
—
—
—
—
2
1
2
1
—
—
—
—
2
1
2
1
—
—
—
—
SWXC1
3
2
3
2
—
—
—
—
SDXC1
3
2
3
2
—
—
—
—
MTC1
2
1
2
1
—
—
—
—
MFC1
2
1
2
1
—
—
—
—
CTC1
6
3
6
3
—
—
—
—
CFC1
2
1
2
1
—
—
—
—
DMTC1
2
1
2
1
—
—
—
—
DMFC1
2
1
2
1
—
—
—
—
MOVF
1
1
1
1
—
—
—
—
MOVT
1
1
1
1
—
—
—
—
PREFXNote
—
—
—
—
—
—
—
—
Note
50
Trapped if the length is 53 bits or longer.
Data Sheet U12031EJ2V0DS00
µPD30500
8.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Supply voltage
VDD
Input voltageNote
VI
Condition
Pulse of less than 10 ns
Operating case temperature
TC
Storage temperature
Tstg
Note
Rating
Unit
–0.5 to +4.0
V
–0.5 to VDD + 0.3
V
–1.5 to VDD + 0.3
V
0 to +70
°C
PGA package
–65 to +150
°C
BGA package
–40 to +125
°C
The upper limit of the input voltage (VDD + 0.3) is +4.0 V.
Cautions 1. Do not short circuit two or more outputs at the same time.
2. The quality of the product may be degraded if the absolute maximum rating of even one of
the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore,
specify the values which if exceeded may physically damage the product. Use the product
never exceeding these ratings.
The specifications and conditions shown in the following DC Characteristics and AC
Characteristics are the range within which the product can normally operate and the quality
can be guaranteed.
DC Characteristics (TC = 0 to +70 °C, VDD = 3.3 V ±5 %)
Parameter
Symbol
Condition
High-level output voltage
VOH
VDD = MIN., IOH = –4 mA
Low-level output voltage
VOL
VDD = MIN., IOL = 4 mA
MAX.
2.4
Unit
V
0.4
V
2.0
VDD + 0.3
V
–0.5
+0.8
V
–1.5
+0.8
V
VIHC
0.8 × VDD
VDD + 0.3
V
VILC
–0.5
0.2 × VDD
V
–1.5
0.2 × VDD
V
150 MHz
2.16
A
180 MHz
2.54
A
200 MHz
2.8
A
250 MHz (PGA package)
2.9
A
250 MHz (BGA package)
3.47
A
0.25
A
High-level input
voltageNote 1
VIH
Low-level input
voltageNote 1
VIL
High-level input
voltageNote 2
Low-level input
voltageNote 2
Pulse of less than 10 ns
Pulse of less than 10 ns
Supply current
MIN.
IDD
Normal
operation
Standby
Input leakage current
ILI
–5
+5
µA
Input/output leakage current
ILIO
–5
+5
µA
Notes 1. Not applied to the SysClock pin.
2. Applied to the SysClock pin only.
Remark The operating supply current is almost proportional to the operating clock frequency.
Data Sheet U12031EJ2V0DS00
51
µPD30500
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
CIn
5
pF
Output capacitance
Cout
7
pF
MAX.
Unit
AC Characteristics (TC = 0 to +70 °C, VDD = 3.3 ±5 %)
Clock parameter
Parameter
Symbol
Condition
MIN.
System clock high-level width
tCH
3.0
ns
System clock low-level width
tCL
3.0
ns
System clock frequencyNote 1, 2
System clock cycle
System clock jitter
tCP
tji
150 MHz
20
75
MHz
180 MHz
20
90
MHz
200 MHz
20
100
MHz
250 MHz
20
125
MHz
150 MHz
13.3
50
ns
180 MHz
11.1
50
ns
200 MHz
10
50
ns
250 MHz
8
50
ns
System clock frequency > 66 MHz
±125
ps
System clock frequency ≤ 66 MHz
±250
ps
System clock rise time
tCR
2.0
ns
System clock fall time
tCF
2.0
ns
Mode clock cycle
tMOC
256 × tCP
Notes 1. The operation of the VR5000 is guaranteed only when the PLL is operating
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.
52
Data Sheet U12031EJ2V0DS00
ns
µPD30500
System Interface Parameter
Parameter
Data output hold time
Symbol
tDM
Condition
MIN.
MAX.
Unit
Modebit (14 : 13) = 10
1.0
ns
Modebit (14 : 13) = 11
1.1
ns
Modebit (14 : 13) = 00
1.3
ns
Modebit (14 : 13) = 01
1.3
ns
Data output delay time
tDO
Data input setup time
tDS
1.6
5.0
ns
ns
Data input hold time
tDH
0.5
ns
Boot Mode Interface Parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
More data setup time
tMDS
tCP × 0.35
ns
Mode data hold time
tMDH
tCP × 0.35
ns
Load Coefficient
Parameter
Load coefficient
Symbol
Condition
CLD
Data Sheet U12031EJ2V0DS00
MIN.
MAX.
Unit
1.5
ns/25 pF
53
µPD30500
Test Condition
SysClock
50 %
tDO
tDM
All output pins
50 %
Test Load
All output pins
DUT
CL = 50 pF
Timing Chart
Clock timing
tCP
tCH
80 %
SysClock
50 %
20 %
tCL
tCR
Mode clock timing
tMOC
ModeClock
54
50 %
Data Sheet U12031EJ2V0DS00
tCF
µPD30500
Clock jitter
tji
tji
SysClock
50 %
System interface edge timing
SysClock
tDO
tDH
tDM
SysAD (0 : 63), SysADC (0 : 7),
SysCmd (0 : 8), SysCmdP,
ScLine (0 : 15), ScWord (0 : 1), ScTCE, ScValid
tDS
Output
Output
Input
tDO
tDM
ValidOut, Release, ScCLR,
ScCWE (0 : 1), ScDCE (0 : 1),
ScTDE, ScTOE
Output
Output
tDS
tDH
ValidIn, ExtRqst, RdRdy,
WrRdy, ScDOE, ScMatch,
Int (0 : 5), NMI
Input
Boot mode interface edge timing
ModeClock
tMDS
tMDH
ModeIn
Input
Data Sheet U12031EJ2V0DS00
55
µPD30500
Clocking relations
Cycle
1
2
3
4
SysClock
(input)
PClock
(output)
tDO
tDM
SysAD Driven
(output)
Data
Data
SysAD Received
(input)
Data
Data
Data
Data
Data
Data
tDS
tDH
Reset Timing
Power-on reset timing
VDD
SysClock
VDDOk
≥ 100 ms
≥ 64 K SysClock
256 SysClock
ModeClock
Undefined
tMDS
ModeIn
tMDH
bit0
bit1
bit255
tDS
ColdReset
tDS
Reset
56
Data Sheet U12031EJ2V0DS00
≥ 64 SysClock
µPD30500
Cold reset timing
3.3 V
VDD
SysClock
≥ 64 K SysClock
≥ 64 SysClock
VDDOk
256 SysClock
ModeClock
Undefined
tMDS
tMDH
bit0
ModeIn
bit1
bit255
tDS
≥ 64 SysClock
ColdReset
tDS
Reset
Warm reset timing
3.3 V
VDD
SysClock
≥ 64 SysClock
VDDOk
ColdReset
tDS
tDS
Reset
Data Sheet U12031EJ2V0DS00
57
µPD30500
9. PACKAGE DRAWING
223 PIN CERAMIC PGA
A
< Bottom View >
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
T S RQP NM L K J HG F E DC B A
Index Mark
J
I
F
K
L
φM
E
M
H
G
NOTE
Each lead centerline is located within φ 0.254(φ 0.010 inch) of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
47.24±0.25
INCHES
1.860±0.010
D
E
F
47.24±0.25
2.03
2.54(T.P.)
1.860±0.010
0.080
0.100(T.P.)
G
3.30±0.2
0.130±0.008
H
0.50 MIN.
0.019 MIN.
I
2.82
0.111
0.157 MAX.
J
3.98 MAX.
K
φ 1.27±0.2
0.050±0.008
L
φ 0.46±0.05
φ 0.018±0.002
M
0.254
0.010
X223RJ-100A-1
58
Data Sheet U12031EJ2V0DS00
µPD30500
272 PIN PLASTIC BGA (29x29)
B
A
A
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
AA Y W V U T R P N M L K J H G F E D C B A
Index mark
Z
J
Y
G
S
H
detail of A part
A
K
L
S
F
E
φ M M S A B *2
φP
M S *3
N
NOTES
millimeter.
1. Controlling dimension
∗ 2. Each ball centerline is located within φ 0.30 mm of
its true position (T.P.) at maximum material condition.
∗ 3. Each ball centerline is located within φ 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
29.00±0.20
1.142 +0.008
−0.009
D
29.00±0.20
1.142 +0.008
−0.009
E
1.80
0.071
F
1.27 (T.P.)
0.050 (T.P.)
G
0.60±0.10
0.024 +0.004
−0.005
H
0.90
0.035
J
1.50±0.20
0.059±0.008
K
0.15
0.006
L
φ 0.75±0.15
φ 0.030 +0.006
−0.007
M
0.30
0.012
N
0.25 MIN.
0.009 MIN.
P
0.10
0.004
Y
C1.5
0.059
Z
C0.5
0.020
S272S2-C6-2
Data Sheet U12031EJ2V0DS00
59
µPD30500
10. RECOMMENDED SOLDERING CONDITIONS
Soldering this product under the following soldering conditions is recommended.
For the details of the recommended soldering conditions, refer to Information Document Semiconductor
Device Mounting Technology Manual (C10535E).
For the soldering methods and recommended other than those recommended, consult NEC.
Table 10-1. Soldering Conditions of Surface Mount Type
µPD30500S2-150
: 272-pin plastic BGA (29 × 29 mm)
µPD30500S2-180
: 272-pin plastic BGA (29 × 29 mm)
µPD30500S2-200
: 272-pin plastic BGA (29 × 29 mm)
µPD30500S2-250Note 1: 272-pin plastic BGA (29 × 29 mm)
Soldering Method
Soldering Conditions
Recommended
Conditions Symbol
Infrared reflow
Package peak temperature: 235 °C, Time: 30 sec max. (210 °C min.),
Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is
necessary at 125 °C for 10 hours)
IR35-103-3
VPS
Package peak temperature: 215 °C, Time: 25 to 40 sec max. (200 °C min.),
Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is
necessary at 125 °C for 10 hours)
VP15-103-3
Partial heating
Pin temperature: 300 °C max., Time: 3 sec max. (per device side)
—
Notes 1. Under development
2. Number of days in storage after the dry pack has been opened. The storage conditions are at 25 °C, 65% RH
MAX.
Caution
Do not use two or more soldering methods in combination (except partial heating).
Table 10-2. Soldering Conditions of Insertion Type
µPD30500RJ-150
: 223-pin ceramic PGA (48 × 48 mm)
µPD30500RJ-180
: 223-pin ceramic PGA (48 × 48 mm)
µPD30500RJ-200
: 223-pin ceramic PGA (48 × 48 mm)
µPD30500RJ-250Note : 223-pin ceramic PGA (48 × 48 mm)
Soldering Method
Soldering Conditions
Wave soldering
(Pin only)
Solder bath temperature: 260 °C max., Time: 10 sec max.,
Partial heating
Pin temperature: 300 °C max., Time: 3 sec max. (Per pin)
Note
Under development
Caution
60
Wave soldering is only for the lead part in order that jet solder cannot contact with the chip directly.
Data Sheet U12031EJ2V0DS00
µPD30500
APPENDIX
DIFFERENCES BETWEEN THE VR5000 AND VR4310TM
Item
Operating frequency
VR5000
VR4310
Internal
250 MHz MAX.
167 MHz MAX.
External
125 MHz MAX.
83.3 MHz MAX.
2-way super scalar 5-stage
pipeline
5-stage pipeline
Primary instruction cache
32K bytes
16K bytes
Primary data cache
32K bytes
8K bytes
Secondary cache interface
Provided
None
Data protection
Byte parity
None
Write data transfer rate
9 types (DDDD/DD×DD×/
DD××DD××/D×D×D×D×/
DD×××DD×××/DD××××DD××××/
D××D××D××D××/
DD××××××DD××××××/D×××D×××)
2 types (D/D××)
Initialization pin at reset
ModeIn (dedicated serial pin)
DivMode (0:2)
Status after last data write
Access ends
Last data retained when transfer
rate is set
Corresponding instruction
MIPS I, II, III, IV instruction sets
MIPS I, II, III instruction sets
JTAG interface
None
Provided
SyncOut-SyncIn bus
None
Provided
2, 3, 4, 5, 6, 7, 8
1.5, 2, 2.5, 3, 4, 5, 6
Division ratio of internal to
bus
2, 3, 4, 5, 6, 7, 8
1.5, 2, 2.5, 3, 4, 5, 6
Clock output
None
TClock
Pipline does not operate.
Pipeline/system bus operates
at power of 1/4 of normal
Pipeline
Cache
System bus
Integer operation unit
Clock interface
Multiplication ratio of input
to internal
Low-power mode
operation.
PRId register
Imp = 0×23
Data Sheet U12031EJ2V0DS00
Imp = 0×0B
61
µPD30500
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation.
Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V DD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Note that this document is not designated as ‘preliminary’, while some of the related documents are
preliminary versions.
V R3000, V R4000, V R 4310, V R 5000, V R10000, and V R Series are trademarks of NEC Corp.
MIPS is a trademark of MIPS Technologies Inc.
62
Data Sheet U12031EJ2V0DS00
µPD30500
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12031EJ2V0DS00
63
µPD30500
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
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