Texas Instruments TMS320C33 (Rev. F) User's Guide

TMS320C3x
User’s Guide
Literature Number: SPRU031F
2558539-9761 revision L
March 2004
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Preface
About This Manual
This user’s guide serves as an applications reference book for the TMS320C3x
generation of digital signal processors (DSPs). These include the TMS320C30,
TMS320C31, TMS320LC31, TMS320C32, and TMS320VC33. Throughout the
book, all references to ’C3x refer collectively to the ’C30, ’C31/VC33, ’LC31 and
’C32.
This book provides information to assist managers and hardware/software
engineers in application development. It includes example code and hardware connections for various applications.
The guide shows how to use the instructions set, the architecture, and the ’C3x
interface. It presents examples for frequently used applications and discusses
more involved examples and applications. It also defines the principles involved
in many applications and gives the corresponding assembly language code for
instructional purposes and for immediate use. Whenever the detailed explanation
of the underlying theory is too extensive to be included in this manual, appropriate
references are given for further information.
Notational Conventions
This document uses the following conventions.
- Program listings, program examples, and interactive displays are shown in
a special typeface. Examples use a bold version of the special
typeface for emphasis; interactive displays use a bold version of the
special typeface to distinguish commands that you enter from items that the
system displays (such as prompts, command output, error messages, etc.).
Here is a sample program listing:
0011
0012
0013
0014
0005
0005
0005
0006
0001
0003
0006
.field
.field
.field
.even
1, 2
3, 4
6, 3
iii
Notational Conventions
Here is an example of a system prompt and a command that you might
enter:
C:
csr −a /user/ti/simuboard/utilities
- In syntax descriptions, the instruction, command, or directive is in bold
typeface and parameters are in an italic typeface. Portions of a syntax that
are in bold must be entered as shown; portions of a syntax that are in italics
describe the type of information that must be entered. Here is an example
of a directive syntax:
.asect ”section name”, address
The directive .asect has two parameters, indicated by section name and
address. When you use .asect, the first parameter is an actual section
name, enclosed in double quotes; the second parameter is an address.
- Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
do not enter the brackets themselves. Here is an example of an instruction
that has an optional parameter:
LALK 16-bit constant [, shift]
The LALK instruction has two parameters. The first parameter, 16-bit
constant, is required. The second parameter, shift, is optional. As this syntax
shows, if you use the optional second parameter, you must precede it with a
comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).
- Braces ( { and } ) indicate a list. The symbol | (read as or) separates items
within the list. Here is an example of a list:
{ * | *+ | *− }
This provides three choices: *, *+, or *−.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
- Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this directive is:
.byte value1 [, ... , valuen ]
This syntax shows that .byte has at least one value parameter, but you
may supply additional value parameters, separated by commas.
iv
Information About Cautions / Related Documentation from Texas Instruments
Information About Cautions
This book contains cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
The information in a caution is provided for your protection. Please read each
caution carefully.
Related Documentation From Texas Instruments
The following books describe the TMS320 floating-point devices and related
support tools. To obtain a copy of any of these TI documents, call the Texas
Instruments Literature Response Center as indicated in the section If You
Need Assistance… on page vi. When ordering, please identify the book by its
title and literature number.
TMS320C3x General Purpose Applications User’s Guide (literature number
SPRU194) provides information to assist you in application development
for the TMS320C3x generation of digital signal processors (DSPs). It
includes example code and hardware connections for various appliances.
It also defines the principles involved in many applications and gives the
corresponding assembly language code for instructional purposes and for
immediate use.
TMS320C3x/C4x Assembly Language Tools User’s Guide (literature
number SPRU035) describes the assembly language tools (assembler,
linker, and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic
debugging directives for the ’C3x and ’C4x generations of devices.
TMS320C3x/C4x Optimizing C Compiler User’s Guide (literature number
SPRU034) describes the TMS320 floating-point C compiler. This C compiler
accepts ANSI standard C source code and produces TMS320 assembly
language source code for the ’C3x and ’C4x generations of devices.
Read This First
v
Related Documentation from Texas Instruments / References
TMS320C3x C Source Debugger User’s Guide (literature number
SPRU053) tells you how to invoke the ’C3x emulator, evaluation module,
and simulator versions of the C source debugger interface. This book
discusses various aspects of the debugger interface, including window
management, command entry, code execution, data management, and
breakpoints. It also includes a tutorial that introduces basic debugger
functionality.
TMS320 DSP Development Support Reference Guide (literature number
SPRU011) describes the TMS320 family of digital signal processors and
the tools that support these devices. Included are code-generation tools
(compilers, assemblers, linkers, etc.) and system integration and debug
tools (simulators, emulators, evaluation modules, etc.). Also covered are
available documentation, seminars, the university program, and factory
repair and exchange.
TMS320 Third-Party Support Reference Guide (literature number
SPRU052) alphabetically lists over 100 third parties that provide various
products that serve the family of TMS320 digital signal processors. A
myriad of products and applications are offered—software and hardware
development tools, speech recognition, image processing, noise cancellation, modems, etc.
References
The publications in the following reference list contain useful information
regarding functions, operations, and applications of digital signal processing
(DSP). These books also provide other references to many useful technical
papers. The reference list is organized into categories of general DSP, speech,
image processing, and digital control theory and is alphabetized by author.
- General Digital Signal Processing
Antoniou, Andreas, Digital Filters: Analysis and Design. New York, NY:
McGraw-Hill Company, Inc., 1979.
Bateman, A., and Yates, W., Digital Signal Processing Design. Salt Lake
City, Utah: W. H. Freeman and Company, 1990.
Brigham, E. Oran, The Fast Fourier Transform. Englewood Cliffs, NJ:
Prentice-Hall, Inc., 1974.
Burrus, C.S., and Parks, T.W., DFT/FFT and Convolution Algorithms. New
York, NY: John Wiley and Sons, Inc., 1984.
Chassaing, R., and Horning, D., Digital Signal Processing with the
TMS320C25. New York, NY: John Wiley and Sons, Inc., 1990.
Digital Signal Processing Applications with the TMS320 Family, Vol. I. Texas Instruments, 1986; Prentice-Hall, Inc., 1987.
vi
References
Digital Signal Processing Applications with the TMS320 Family, Vol. III.
Texas Instruments, 1990; Prentice-Hall, Inc., 1990.
Gold, Bernard, and Rader, C.M., Digital Processing of Signals. New York,
NY: McGraw-Hill Company, Inc., 1969.
Hamming, R.W., Digital Filters. Englewood Cliffs, NJ: Prentice-Hall, Inc.,
1977.
Hutchins, B., and Parks, T., A Digital Signal Processing Laboratory Using
the TMS320C25. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990.
IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing.
New York, NY: IEEE Press, 1979.
Jackson, Leland B., Digital Filters and Signal Processing. Hingham, MA:
Kluwer Academic Publishers, 1986.
Jones, D.L., and Parks, T.W., A Digital Signal Processing Laboratory Using
the TMS32010. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987.
Lim, Jae, and Oppenheim, Alan V. (Editors), Advanced Topics in Signal
Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988.
Morris, L. Robert, Digital Signal Processing Software. Ottawa, Canada:
Carleton University, 1983.
Oppenheim, Alan V. (Editor), Applications of Digital Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.
Oppenheim, Alan V., and Schafer, R.W., Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975.
Oppenheim, Alan V., and Schafer, R.W., Discrete-Time Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1989.
Oppenheim, Alan V., and Willsky, A.N., with Young, I.T., Signals and
Systems. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.
Parks, T.W., and Burrus, C.S., Digital Filter Design. New York, NY: John Wiley
and Sons, Inc., 1987.
Rabiner, Lawrence R., and Gold, Bernard, Theory and Application of Digital
Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975.
Treichler, J.R., Johnson, Jr., C.R., and Larimore, M.G., Theory and Design
of Adaptive Filters. New York, NY: John Wiley and Sons, Inc., 1987.
- Speech
Gray, A.H., and Markel, J.D., Linear Prediction of Speech. New York, NY:
Springer-Verlag, 1976.
Jayant, N.S., and Noll, Peter, Digital Coding of Waveforms. Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1984.
Papamichalis, Panos, Practical Approaches to Speech Coding. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987.
Read This First
vii
References
Parsons, Thomas., Voice and Speech Processing. New York, NY:
McGraw Hill Company, Inc., 1987.
Rabiner, Lawrence R., and Schafer, R.W., Digital Processing of Speech
Signals. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.
Shaughnessy, Douglas., Speech Communication. Reading, MA: AddisonWesley, 1987.
- Image Processing
Andrews, H.C., and Hunt, B.R., Digital Image Restoration. Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1977.
Gonzales, Rafael C., and Wintz, Paul, Digital Image Processing. Reading,
MA: Addison-Wesley Publishing Company, Inc., 1977.
Pratt, William K., Digital Image Processing. New York, NY: John Wiley and
Sons, 1978.
- Multirate DSP
Crochiere, R.E., and Rabiner, L.R., Multirate Digital Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.
Vaidyanathan, P.P., Multirate Systems and Filter Banks. Englewood Cliffs,
NJ: Prentice-Hall, Inc.
- Digital Control Theory
Dote, Y., Servo Motor and Motion Control Using Digital Signal Processors.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990.
Jacquot, R., Modern Digital Control Systems. New York, NY: Marcel Dekker,
Inc., 1981.
Katz, P., Digital Control Using Microprocessors. Englewood Cliffs, NJ:
Prentice-Hall, Inc., 1981.
Kuo, B.C., Digital Control Systems. New York, NY: Holt, Reinholt and
Winston, Inc., 1980.
Moroney, P., Issues in the Implementation of Digital Feedback Compensators. Cambridge, MA: The MIT Press, 1983.
Phillips, C., and Nagle, H., Digital Control System Analysis and Design.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984.
- Adaptive Signal Processing
Haykin, S., Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice-Hall,
Inc., 1991.
Widrow, B., and Stearns, S.D. Adaptive Signal Processing. Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1985.
viii
References
- Array Signal Processing
Haykin, S., Justice, J.H., Owsley, N.L., Yen, J.L., and Kak, A.C. Array Signal
Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985.
Hudson, J.E. Adaptive Array Principles. New York, NY: John Wiley and
Sons, 1981.
Monzingo, R.A., and Miller, J.W. Introduction to Adaptive Arrays. New York,
NY: John Wiley and Sons, 1980.
Read This First
ix
If You Need Assistance
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x
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Read This First
xi
xii
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
A general description of the TMS320C30, TMS320C31, TMS320C32, and TMS320VC33, their
key features, and typical applications.
1.1
1.2
2
TMS320C3x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 TMS320C3x Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 TMS320C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 TMS320C31/VC33 and TMS320LC31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 TMS320C32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-3
1-3
1-3
1-4
1-7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Functional block diagram, ’C3x design description, hardware components, device operation,
and instruction set summary.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.1 Floating-Point/Integer Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.2 Arithmetic Logic Unit (ALU) and Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3 Auxiliary Register Arithmetic Units (ARAUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
CPU Primary Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Other Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.5.1 RAM, ROM, and Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.5.2 Memory Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Internal Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.7.1 TMS320C32 16- and 32-Bit Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.7.2 TMS320C32 8-, 16-, and 32-Bit Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.9.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.9.2 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
TMS320C30, TMS320C31/VC33, and TMS320C32 Differences . . . . . . . . . . . . . . . . . 2-26
xiii
Contents
3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Description of the registers in the CPU register file.
3.1
3.2
3.3
4
Memory and the Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Description of memory maps with explanation of instruction cache architecture, algorithm,
and control bits.
4.1
4.2
4.3
5
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.1 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.2 Peripheral Bus Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Reset/Interrupt/Trap Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3.1 Instruction-Cache Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3.2 Instruction-Cache Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.3.3 Cache Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Data Formats and Floating-Point Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Description of signed and unsigned integer and floating-point formats. Discussion of floatingpoint multiplication, addition, subtraction, normalization, rounding, and conversions.
5.1
5.2
5.3
xiv
CPU Multiport Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1 Extended-Precision Registers (R7−R0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.1.2 Auxiliary Registers (AR7−AR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.3 Data-Page Pointer (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.4 Index Registers (IR0, IR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.5 Block Size (BK) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.6 System-Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.7 Status (ST) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.1.8 CPU/DMA Interrupt-Enable (IE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.9 CPU Interrupt Flag (IF) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.1.10 I/O Flag (IOF) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.1.11 Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers . . . . . . . . . . . . . 3-17
Other Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.2.1 Program-Counter (PC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.2.2 Instruction Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Reserved Bits and Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Integer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Short-Integer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Single-Precision Integer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsigned-Integer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Short Unsigned-Integer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Single-Precision Unsigned-Integer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-Point Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Short Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 TMS320C32 Short Floating-Point Format for External 16-Bit Data . . . . . . . . .
5-2
5-2
5-2
5-3
5-3
5-3
5-4
5-5
5-6
Contents
5.3.3
5.3.4
5.3.5
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
6
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Operation, encoding, and implementation of addressing modes; format descriptions;
system stack management.
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
Single-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Extended-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Determining the Decimal Equivalent of a TMS320C3x
Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3.6 Conversion Between Floating-Point Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Floating-Point Conversion (IEEE Std. 754) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.4.1 Converting IEEE Format to 2s-Complement TMS320C3x
Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format
to IEEE Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Floating-Point Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Floating-Point Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
Normalization Using the NORM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Rounding (RND Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
Floating-Point to Integer Conversion (FIX Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Integer to Floating-Point Conversion (FLOAT Instruction) . . . . . . . . . . . . . . . . . . . . . . . 5-43
Fast Logarithms on a Floating-Point Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.11.1 Example of Fast Logarithm on a Floating-Point Device . . . . . . . . . . . . . . . . . . 5-45
5.11.2 Points to Consider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
Addressing Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
PC-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools . . . . 6-28
System and User Stack Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.10.1 System-Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.10.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.10.3 Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Program Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Software control of program flow with repeat modes and branching; interlocked operations;
reset and interrupts.
7.1
Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Repeat-Mode Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 Repeat-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 RPTB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
7-2
7-3
7-3
7-4
xv
Contents
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Discussion of the pipeline of operations on the TMS320C3x
8.1
8.2
8.3
8.4
8.5
xvi
7.1.4 RPTS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.1.5 Repeat-Mode Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.1.6 RC Register Value After Repeat Mode Completes . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.1.7 Nested Block Repeats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Delayed Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Calls, Traps, and Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Interlocked Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.4.1 Interrupting Interlocked Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.4.2 Using Interlocked Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.4.3 Pipeline Effects of Interlocked Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.6.1 TMS320C30 and TMS320C31/VC33 Interrupt Vector Table . . . . . . . . . . . . . . 7-26
7.6.2 TMS320C32 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
7.6.3 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
7.6.4 CPU Interrupt Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
7.6.5 Interrupt Flag Register Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
7.6.6 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
7.6.7 CPU Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
7.6.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
7.7.1 DMA Interrupt Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
7.7.2 DMA Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39
7.7.3 CPU/DMA Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
7.7.4 TMS320C3x Interrupt Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41
7.7.5 TMS320C30 Interrupt Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
7.8.1 Initialization of Traps and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
7.8.2 Operation of Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
7.9.1 IDLE2 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
7.9.2 LOPOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
Pipeline Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Pipeline Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2.1 Branch Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2.2 Register Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.2.3 Memory Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Resolving Register Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Memory Access for Maximum Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
Clocking Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.5.1 Program Fetches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.5.2 Data Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Contents
9
TMS320C30 and TMS320C31/VC33 External-Memory Interface . . . . . . . . . . . . . . . . . . . . . . 9-1
Description of primary and expansion interfaces for the ’C30 and ’C31/VC33; external interface
timing diagrams; programmable wait-states and bank switching.
9.1
9.2
9.3
9.4
9.5
9.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.1
TMS320C30 Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.2
TMS320C31/VC33 Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Memory Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.1
Primary-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.2
Expansion-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Programmable Bank Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
External Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.6.1
Primary-Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.6.2
Expansion-Bus I/O Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.6.3
Hold Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
10 TMS320C32 Enhanced External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Description of primary and expansion interfaces for the ’C32; external interface timing
diagrams; programmable wait-states and bank switching.
10.1
10.2
TMS320C32 Memory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
TMS320C32 Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.1 External Memory Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.2 Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3 Data Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.1 External Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.2 Using Physical Memory Width and Data-Type Size Fields . . . . . . . . . . . . . 10-13
10.4 Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5 Programmable Bank Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.6 32-Bit-Wide Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.7 16-Bit-Wide Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.8 8-Bit-Wide Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.9 External Ready Timing Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38
10.10 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
10.10.1 STRB0 and STRB1 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
10.10.2 IOSTRB Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42
10.10.3 Inactive Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51
11 Using the TMS320C31/VC33 and TMS320C32 Boot Loaders . . . . . . . . . . . . . . . . . . . . . . . 11-1
Description of the boot loader operations for the ’C31/VC33 and ’C32.
11.1
TMS320C31/VC33 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.1 TMS320C31/VC33 Boot-Loader Description . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.2 TMS320C31/VC33 Boot-Loader Mode Selection . . . . . . . . . . . . . . . . . . . . . . 11-2
Contents
xvii
Contents
11.2
11.1.3 TMS320C31/VC33 Boot-Loading Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.1.4 TMS320C31/VC33 Boot Data Stream Structure . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.1.5 Interrupt and Trap-Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.1.6 TMS320C31/VC33 Boot-Loader Precautions . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
TMS320C32 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.2.1 TMS320C32 Boot-Loader Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.2.2 TMS320C32 Boot-Loader Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.2.3 TMS320C32 Boot-Loading Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.2.4 TMS320C32 Boot Data Stream Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.2.5 Boot-Loader Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
11.2.6 TMS320C32 Boot-Loader Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
12 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Description of the DMA controller, timers, and serial ports.
12.1
12.2
12.3
xviii
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.1.1 Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.1.2 Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.1.3 Timer Global-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.1.4 Timer-Period and Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.1.5 Timer Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.1.6 Timer Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.1.7 Using TCLKx as General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.1.8 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.1.9 Timer Initialization/Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.2.1 Serial-Port Global-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.2.2 FSX/DX/CLKX Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
12.2.3 FSR/DR/CLKR Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12.2.4 Receive/Transmit Timer-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
12.2.5 Receive/Transmit Timer-Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12.2.6 Receive/Transmit Timer-Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.2.7 Data-Transmit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.2.8 Data-Receive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.2.9 Serial-Port Operation Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12.2.10 Serial-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
12.2.11 Serial-Port Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.2.12 Serial-Port Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
12.2.13 Serial-Port Initialization/Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41
12.2.14 TMS320C3x Serial-Port Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . 12-41
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48
12.3.1 DMA Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48
12.3.2 DMA Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50
12.3.3 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51
12.3.4 CPU/DMA Interrupt-Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59
Contents
12.3.5
12.3.6
12.3.7
12.3.8
12.3.9
12.3.10
12.3.11
TMS320C32 DMA Internal Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . . .
CPU and DMA Controller Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Memory Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Initialization/Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hints for DMA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-62
12-63
12-64
12-67
12-73
12-73
12-74
13 Assembly Language Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Functional listing of instructions. Condition codes defined. Alphabetized individual instruction
set with examples.
13.1
13.2
13.3
13.4
13.5
13.6
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.1 Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.2 2-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.1.3 3-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.1.4 Program-Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.1.5 Low-Power Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.1.6 Interlocked-Operations Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.1.7 Parallel-Operations Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.1.8 Illegal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Parallel Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
Group Addressing Mode Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
13.4.1 General Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
13.4.2 3-Operand Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24
13.4.3 Parallel Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
13.4.4 Conditional-Branch Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27
Condition Codes and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
Individual Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13.6.1 Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13.6.2 Optional Assembler Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.6.3 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37
A
Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
List of the opcode fields for the TMS320C3x instructions.
B
TMS320C31/VC33 Boot Loader Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
C
TMS320C32 Boot Loader Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1 Boot-Loader Source Code Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C.2 Boot-Loader Source Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
D
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
Contents
xix
Figures
1−1
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
2−10
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
3−10
3−11
3−12
4−1
4−2
4−3
4−4
4−5
4−6
4−7
4−8
4−9
4−10
4−11
4−12
xx
TMS320C3x Devices Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
TMS320C30 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TMS320C31/VC33 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
TMS320C32 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Memory Organization of the TMS320C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Memory Organization of the TMS320C31/VC33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Memory Organization of the TMS320C32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
TMS320C32-Supported Data Types and Sizes and External Memory Widths . . . . . . . . 2-20
Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Extended-Precision Register Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Extended-Precision Register Integer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Status Register (TMS320C30 andTMS320C31/VC33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Status Register (TMS320C32 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
CPU/DMA Interrupt-Enable (IE) Register (TMS320C30 and TMS320C31/VC33) . . . . . . 3-9
CPU/DMA Interrupt-Enable (IE) Register (TMS320C32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TMS320C30 CPU Interrupt Flag (IF) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
TMS320C31/VC33 CPU Interrupt Flag (IF) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
TMS320C32 CPU Interrupt Flag (IF) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Effective Base Address of the Interrupt-Trap Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Interrupt and Trap Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
I/O Flag (IOF) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
TMS320C30 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
TMS320C31/VC33 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
TMS320C32 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
TMS320C30 Peripheral Bus Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
TMS320C31/VC33 Peripheral Bus Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . 4-11
TMS320C32 Peripheral Bus Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Reset, Interrupt, and Trap Vector Locations for the TMS320C30
Microprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Reset, Interrupt, and Trap Vector Locations for theTMS320C31/VC33
Microprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Interrupt and Trap Branch Instructions for the TMS320C31/VC33 Microcomputer Mode 4-17
Interrupt and Trap Vector Locations for TMS320C32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Address Partitioning for Cache Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Instruction-Cache Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Figures
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
5−10
5−11
5−12
5−13
5−14
5−15
5−16
5−17
5−18
5−19
5−20
5−21
5−22
5−23
6−1
6−2
6−3
6−4
6−5
6−6
6−7
6−8
6−9
6−10
6−11
7−1
7−2
7−3
7−4
7−5
7−6
7−7
Short-Integer Format and Sign-Extension of Short Integers . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Single-Precision Integer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Short Unsigned-Integer Format and Zero Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Single-Precision Unsigned-Integer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
General Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Short Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
TMS320C32 Short Floating-Point Format for External 16-Bit Data . . . . . . . . . . . . . . . . . . . 5-6
Single-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Extended-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Converting from Short Floating-Point Format to Single-Precision
Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Converting from Short Floating-Point Format to Extended-Precision
Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Converting from Single-Precision Floating-Point Format to Extended-Precision
Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Converting from Extended-Precision Floating-Point Format to Single-Precision
Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
IEEE Single-Precision Std. 754 Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
TMS320C3x Single-Precision 2s-Complement Floating-Point Format . . . . . . . . . . . . . . . 5-15
Flowchart for Floating-Point Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Flowchart for Floating-Point Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Flowchart for NORM Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Flowchart for Floating-Point Rounding by the RND Instruction . . . . . . . . . . . . . . . . . . . . . 5-40
Flowchart for Floating-Point to Integer Conversion by FIX Instruction . . . . . . . . . . . . . . . 5-42
Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction . . . . . . . . . . . . 5-43
Tabulated Values for Mantissa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
Fast Logarithm for FFT Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Indirect Addressing Operand Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Encoding for 24-Bit PC-Relative Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Logical and Physical Representation of Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Logical and Physical Representation of Circular Buffer after Writing Three Values . . . . 6-21
Logical and Physical Representation of Circular Buffer after Writing Eight Values . . . . . 6-22
Circular Buffer Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Data Structure for FIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
System Stack Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Implementations of High-to-Low Memory Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
Implementations of Low-to-High Memory Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
CALL Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Multiple TMS320C3xs Sharing Global Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Zero-Logic Interconnect of TMS320C3x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Effective Base Address of the Interrupt-Trap-Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
IF Register Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Interrupt Logic Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Contents
xxi
Figures
7−8
7−9
7−10
7−11
7−12
7−13
7−14
8−1
8−2
8−3
8−4
8−5
8−6
8−7
9−1
9−2
9−3
9−4
9−5
9−6
9−7
9−8
9−9
9−10
9−11
9−12
9−13
9−14
9−15
9−16
9−17
9−18
9−19
9−20
9−21
9−22
9−23
9−24
9−25
9−26
10−1
10−2
10−3
10−4
xxii
DMA Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39
Parallel CPU and DMA Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Flow of Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
IDLE2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50
Interrupt Response Timing After IDLE2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
LOPOWER Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
MAXSPEED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
TMS320C3x Pipeline Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Minor Clock Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
2-Operand Instruction Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
3-Operand Instruction Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Multiply or CPU Operation With a Parallel Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Two Parallel Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Parallel Multiplies and Adds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
Memory-Mapped External Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Primary-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Expansion-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
BNKCMP Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Bank-Switching Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Read-Read-Write for (M)STRB = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Write-Write-Read for (M)STRB = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Use of Wait States for Read for (M)STRB = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Use of Wait States for Write for (M)STRB = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Read and Write for IOSTRB = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Read With One Wait State for IOSTRB = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
Write With One Wait State for IOSTRB = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
Memory Read and I/O Write for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
Memory Read and I/O Read for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Memory Write and I/O Write for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
Memory Write and I/O Read for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
I/O Write and Memory Write for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
I/O Write and Memory Read for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
I/O Read and Memory Write for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
I/O Read and Memory Read for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
I/O Write and I/O Read for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
I/O Write and I/O Write for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
I/O Read and I/O Read for Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
Inactive Bus States for IOSTRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
Inactive Bus States for STRB and MSTRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
HOLD and HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
Memory Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Memory-Mapped External Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
STRB0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Figures
10−5
10−6
10−7
10−8
10−9
10−10
10−11
10−12
10−13
10−14
10−15
10−16
10−17
10−18
10−19
10−20
10−21
10−22
10−23
10−24
10−25
10−26
10−27
10−28
10−29
10−30
10−31
10−32
10−33
10−34
10−35
10−36
10−37
10−38
10−39
10−40
10−41
10−42
11−1
11−2
11−3
11−4
STRB1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
IOSTRB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
STRB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
BNKCMP Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
Bank-Switching Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
TMS320C32 External Memory Interface for 32-Bit SRAMs . . . . . . . . . . . . . . . . . . . . . . . 10-20
Functional Diagram for 8-Bit Data-Type Size and 32-Bit External-Memory . . . . . . . . . . . . . . . .
Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
Functional Diagram for 16-Bit Data-Type Size and 32-Bit External-Memory . . . . . . . . . . . . .
Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
Functional Diagram for 32-Bit Data Size and 32-Bit External-Memory Width . . . . . . . . 10-24
External-Memory Interface for 16-Bit SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
Functional Diagram for 8-Bit Data-Type Size and 16-Bit External-Memory Width . . . . 10-27
Functional Diagram for 16-Bit Data-Type Size and 16-Bit External-Memory Width . . . . . 10-29
Functional Diagram for 32-Bit Data-Type Size and 16-Bit External-Memory Width . . . . . 10-30
External Memory Interface for 8-Bit SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
Functional Diagram for 8-Bit Data-Type Size and 8-Bit External-Memory Width . . . . . . 10-33
Functional Diagram for 16-Bit Data-Type Size and 8-Bit External-Memory Width . . . . 10-34
Functional Diagram for 32-Bit Data-Type Size and 8-Bit External-Memory Width . . . . 10-36
RDY Timing for Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38
Read-Read-Write Sequence for STRBx Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
Write-Write-Read Sequence for STRBx Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
One Wait-State Read Sequence for STRBx Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41
One Wait-State Write Sequence for STRBx Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42
Zero Wait-State Read and Write Sequence for IOSTRB Active . . . . . . . . . . . . . . . . . . . . 10-43
One Wait-State Read Sequence for IOSTRB Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44
One Wait-State Write Sequence for IOSTRB Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44
STRBx Read and IOSTRB Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45
STRBx Read and IOSTRB Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45
STRBx Write and IOSTRB Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-46
STRBx Write and IOSTRB Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-46
IOSTRB Write and STRBx Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
IOSTRB Write and STRBx Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48
IOSTRB Read and STRBx Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48
IOSTRB Read and STRBx Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-49
IOSTRB Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-50
IOSTRB Write and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-50
IOSTRB Read and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51
Inactive Bus States Following IOSTRB Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51
Inactive Bus States Following STRBx Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52
TMS320C31/VC33 Boot-Loader Mode-Selection Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Boot-Loader Memory-Load Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Boot-Loader Serial-Port Load-Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
TMS320C32 Boot-Loader Mode-Selection Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Contents
xxiii
Figures
11−5
11−6
11−7
11−8
12−1
12−2
12−3
12−4
12−5
12−6
12−7
12−8
12−9
12−10
12−11
12−12
12−13
12−14
12−15
12−16
12−17
12−18
12−19
12−20
12−21
12−22
12−23
12−24
12−25
12−26
12−27
12−28
12−29
12−30
12−31
12−32
12−33
12−34
12−35
12−36
12−37
12−38
12−39
12−40
xxiv
Boot-Loader Serial-Port Load Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Boot-Loader Memory-Load Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Handshake Data-Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
External Memory Interface for Source Data Stream Memory Boot Load . . . . . . . . . . . . 11-23
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Memory-Mapped Timer Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Timer Global-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Timer Configuration with CLKSRC = 1 and FUNC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Timer Configuration with CLKSRC = 1 and FUNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Timer Configuration with CLKSRC = 0 and FUNC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Timer Configuration with CLKSRC = 0 and FUNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
TCLK as an Input (I/O = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
TCLK as an Output (I/O = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Serial Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
Memory-Mapped Locations for the Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
Serial-Port Global-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
FSX/DX/CLKX Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
FSR/DR/CLKR Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
Receive/Transmit Timer-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
Receive/Transmit Timer-Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
Receive/Transmit Timer-Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
Transmit Buffer Shift Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
Receive Buffer Shift Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
Serial-Port Clocking in I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
Serial-Port Clocking in Serial-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
Data Word Format in Handshake Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
Single 0 Sent as an Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
Direct Connection Using Handshake Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
Fixed Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
Fixed Standard Mode With Back-to-Back Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
Fixed Continuous Mode Without Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal . . . . . . . . . . . . . . . . 12-39
Variable Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
Variable Standard Mode With Back-to-Back Frame Syncs . . . . . . . . . . . . . . . . . . . . . . . . 12-40
Variable Continuous Mode Without Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41
TMS320C3x Zero-Glue-Logic Interface to TLC320C4x Example . . . . . . . . . . . . . . . . . . 12-45
DMA Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51
Memory-Mapped Locations for DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52
TMS320C30 and TMS320C31/VC33 DMA Global-Control Register . . . . . . . . . . . . . . . . 12-53
TMS320C32 DMA0 Global-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53
TMS320C32 DMA1 Global-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53
DMA Controller Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57
Transfer-Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59
Figures
12−41
12−42
12−43
12−44
12−45
12−46
12−47
12−48
12−49
13−1
13−2
13−3
13−4
13−5
13−6
C−1
TMS320C30 and TMS320C31/VC33 CPU/DMA Interrupt-Enable Register . . . . . . . . . . 12-60
TMS320C32 CPU/DMA Interrupt-Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60
Mechanism for No DMA Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65
Mechanism for DMA Source Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-66
Mechanism for DMA Destination Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-66
Mechanism for DMA Source and Destination Synchronization . . . . . . . . . . . . . . . . . . . . 12-67
DMA Timing When Destination is On Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-69
DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus . . . . . . . . . . 12-70
DMA Timing When Destination is an IOSTRB Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-72
Encoding for General Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
Encoding for 3-Operand Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
Encoding for Parallel Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
Encoding for Extended Parallel Addressing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
Encoding for Conditional-Branch Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
Boot-Loader Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Contents
xxv
Tables
1−1
1−2
2−1
2−2
3−1
3−2
3−3
3−4
3−5
4−1
5−1
5−2
5−3
6−1
6−2
6−3
7−1
7−2
7−3
7−4
7−5
7−6
7−7
7−8
7−9
7−10
8−1
8−2
9−1
9−2
9−3
9−4
9−5
9−6
10−1
xxvi
TMS320C30, TMS320C31/VC33, TMS320LC31, and TMS320C32 Comparison . . . . . . 1-5
Typical Applications of the TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Primary CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Feature Set Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
IE Bits and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
IF Bits and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
IOF Bits and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Combined Effect of the CE and CF Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Converting IEEE Format to 2s-Complement Floating-Point Format . . . . . . . . . . . . . . . . . 5-15
Converting 2s-Complement Floating-Point Format to IEEE Format . . . . . . . . . . . . . . . . . 5-21
Squaring Operation of F0 = 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
CPU Register Address/Assembler Syntax and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Index Steps and Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Repeat-Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Interlocked Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
TMS320C3x Pin Operation at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Reset, Interrupt, and Trap-Vector Locations for the TMS320C30/TMS320C31/VC33
Microprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Reset, Interrupt, and Trap-Branch Locations for the TMS320C31/VC33
Microcomputer Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
Interrupt and Trap-Vector Locations for the TMS320C32 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
Reset and Interrupt Vector Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Pipeline Operation with PUSH ST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
Pipeline Operation with Load Followed by Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
One Program Fetch and One Data Access for Maximum Performance . . . . . . . . . . . . . . 8-22
One Program Fetch and Two Data Accesses for Maximum Performance . . . . . . . . . . . . 8-23
Primary Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Expansion Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Primary-Bus Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Expansion-Bus Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Wait-State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
BNKCMP and Bank Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
STRB0, STRB1, and IOSTRB Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Tables
10−2
10−3
10−4
10−5
10−6
10−7
10−8
10−9
10−10
10−11
10−12
10−13
10−14
10−15
10−16
11−1
11−2
11−3
11−4
11−5
11−6
11−7
11−8
12−1
12−2
12−3
12−4
12−5
12−6
12−7
12−8
13−1
13−2
13−3
13−4
13−5
13−6
13−7
13−8
13−9
13−10
13−11
13−12
13−13
13−14
A−1
Data-Access Sequence for a Memory Configuration with Two Banks . . . . . . . . . . . . . . . 10-14
Wait-State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
BNKCMP and Bank Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-Type Size . . . . . . . . . . . . 10-21
Example of 8-Bit Data-Type Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
Strobe Byte-Enable for 32-Bit-Wide Memory With 16-Bit Data-Type Size . . . . . . . . . . . 10-22
Example of 16-Bit Data-Type Size and 32-Bit-Wide External Memory . . . . . . . . . . . . . . 10-23
Example of 32-Bit-Wide Memory With 32-Bit Data-Type Size . . . . . . . . . . . . . . . . . . . . . 10-25
Strobe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bit Data-Type Size . . . . 10-27
Example of 8-Bit Data-Type Size and 16-Bit-Wide External Memory . . . . . . . . . . . . . . . 10-28
Example of 16-Bit-Wide Memory With 16-Bit Data-Type Size . . . . . . . . . . . . . . . . . . . . . 10-29
Example of 16-Bit-Wide Memory With 32-Bit Data-Type Size . . . . . . . . . . . . . . . . . . . . . 10-31
Example of 8-Bit-Wide Memory With 8-Bit Data-Type Size . . . . . . . . . . . . . . . . . . . . . . . . 10-33
Example of 8-Bit-Wide Memory With 16-Bit Data-Type Size . . . . . . . . . . . . . . . . . . . . . . . 10-35
Example of 32-Bit Data-Type Size and 8-Bit-Wide Memory . . . . . . . . . . . . . . . . . . . . . . . 10-37
Boot-Loader Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Source Data Stream Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Byte-Wide Configured Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
16-Bit-Wide Configured Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
32-Bit-Wide Configured Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
TMS320C31/VC33 Interrupt and Trap Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Boot-Loader Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Source Data Stream Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Timer Global-Control Register Bits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Serial-Port Global-Control Register Bits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
FSX/DX/CLKX Port-Control Register Bits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
FSR/DR/CLKR Port-Control Register Bits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
Receive/Transmit Timer-Control Register Register Bits Summary . . . . . . . . . . . . . . . . . 12-25
DMA Global-Control Register Bits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54
CPU/DMA Interrupt-Enable Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61
TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules . . . . . . . . . . . . . . . . . . . . . . 12-64
Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
2-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
3-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Program-Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Low-Power Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Interlocked-Operations Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Parallel Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Parallel Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
Output Value Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
Condition Codes and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
Instruction Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33
CPU Register Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36
TMS320C3x Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Contents
xxvii
Examples
4−1
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
5−10
5−11
5−12
5−13
5−14
5−15
5−16
5−17
6−1
6−2
6−3
6−4
6−5
6−6
6−7
6−8
6−9
6−10
6−11
6−12
6−13
6−14
6−15
6−16
6−17
6−18
xxviii
Pipeline Effects of Modifying the Cache Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Positive Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Negative Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Fractional Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
IEEE-to-TMS320C3x Conversion (Fast Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
IEEE-to-TMS320C3x Conversion (Complete Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
TMS320C3x-to-IEEE Conversion (Fast Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
TMS320C3x-to-IEEE Conversion (Complete Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Floating-Point Multiply (Both Mantissas = −2.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Floating-Point Multiply (Both Mantissas = 1.5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Floating-Point Multiply (Both Mantissas = 1.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Floating-Point Multiply Between Positive and Negative Numbers . . . . . . . . . . . . . . . . . . . 5-31
Floating-Point Multiply by 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Floating-Point Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
Floating-Point Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Floating-Point Addition With a 32-Bit Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Floating-Point Addition/Subtraction With Floating-Point 0 . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
NORM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Auxiliary Register Indirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Indirect Addressing With Predisplacement Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Indirect Addressing With Predisplacement Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Indirect Addressing With Predisplacement Add and Modify . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Indirect Addressing With Predisplacement Subtract and Modify . . . . . . . . . . . . . . . . . . . . 6-10
Indirect Addressing With Postdisplacement Add and Modify . . . . . . . . . . . . . . . . . . . . . . . 6-11
Indirect Addressing With Postdisplacement Subtract and Modify . . . . . . . . . . . . . . . . . . . 6-11
Indirect Addressing With Postdisplacement Add and Circular Modify . . . . . . . . . . . . . . . . 6-12
Indirect Addressing With Postdisplacement Subtract and Circular Modify . . . . . . . . . . . . 6-12
Indirect Addressing With Preindex Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Indirect Addressing With Preindex Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Indirect Addressing With Preindex Add and Modify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Indirect Addressing With Preindex Subtract and Modify . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Indirect Addressing With Postindex Add and Modify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Indirect Addressing With Postindex Subtract and Modify . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Indirect Addressing With Postindex Add and Circular Modify . . . . . . . . . . . . . . . . . . . . . . . 6-16
Indirect Addressing With Postindex Subtract and Circular Modify . . . . . . . . . . . . . . . . . . . 6-16
Examples
6−19
6−20
6−21
6−22
6−23
6−24
6−25
6−26
7−1
7−2
7−3
7−4
7−5
7−6
7−7
7−8
7−9
7−10
7−11
7−12
7−13
7−14
7−15
8−1
8−2
8−3
8−4
8−5
8−6
8−7
8−8
8−9
8−10
8−11
8−12
8−13
8−14
8−15
8−16
8−17
8−18
12−1
12−2
Indirect Addressing With Postindex Add and Bit-Reversed Modify . . . . . . . . . . . . . . . . . . 6-17
Short-Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Long-Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
PC-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Examples of Formula 2K > R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
FIR Filter Code Using Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Repeat-Mode Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
RPTB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Incorrectly Placed Standard Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Incorrectly Placed Delayed Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Pipeline Conflict in an RPTB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Incorrectly Placed Delayed Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Delayed Branch Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Busy-Waiting Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Multiprocessor Counter Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Implementation of V(S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Implementation of P(S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Code to Synchronize Two TMS320C3x Devices at the Software Level . . . . . . . . . . . . . . 7-19
Pipeline Delay of XF Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Incorrect Use of Interlocked Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Pending Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43
Standard Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Delayed Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Write to an AR Followed by an AR for Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
A Read of ARs Followed by ARs for Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Program Wait Until CPU Data Access Completes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Program Wait Due to Multicycle Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Multicycle Program Memory Fetches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Single Store Followed by Two Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Parallel Store Followed by Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
Interlocked Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Busy External Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
Multicycle Data Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Conditional Calls and Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
Address Generation Update of an AR Followed by an AR for Address Generation . . . . 8-19
Write to an AR Followed by an AR for Address Generation Without
a Pipeline Conflict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict . . . . . . . . . . 8-21
Dummy sr2 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
Operand Swapping Alternative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Timer Output Generation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
Maximum Frequency Timer Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Contents
xxix
Examples
12−3
12−4
12−5
12−6
12−7
12−8
12−9
12−10
xxx
Serial-Port Register Setup #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Port Register Setup #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Port Register Setup #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Transfer With Serial Port Transmit Polling Method . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320C3x Zero-Glue-Logic Interface to Burr Brown A/D and D/A . . . . . . . . . . . . . . . .
Array Initialization With DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Transfer With Serial-Port Receive Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Transfer With Serial-Port Transmit Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-42
12-43
12-43
12-44
12-46
12-75
12-76
12-77
Chapter 1
The TMS320C3x generation of digital signal processors (DSPs) are highperformance CMOS 32-bit floating-point devices in the TMS320 family of
single-chip DSPs.
The ’C3x generation integrates both system control and math-intensive functions
on a single controller. This system integration allows fast, easy data movement
and high-speed numeric processing performance. Extensive internal busing and
a powerful DSP instruction set provide the devices with the speed and flexibility
to execute at up to 60 million floating-point operations per second (MFLOPS).
The devices also feature a high degree of on-chip parallelism that allows users
to perform up to 11 operations in a single instruction.
Topic
Page
1.1
TMS320C3x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1-1
TMS320C3x Devices
1.1 TMS320C3x Devices
The ’C3x family consists of three members: the ’C30, ’C31, ’C32, and ’VC33.
The ’C30, ’C31, ’C32, and ’VC33 can perform parallel multiply and arithmetic
logic unit (ALU) operations on integer or floating-point data in a single cycle.
The processors also possess the following features for high performance and
ease of use:
Note: VC33
The TMS320VC33 is logically and functionally a superset of the TMS320C31
making nearly all literature and documentation for the TMS320C31 applica−
ble. However, the electrical characteristics are different and are covered in
detail in the TMS320VC33 data sheet (literature number SPRS087).
- General-purpose register file
- Program cache
- Dedicated auxiliary register arithmetic units (ARAU)
- Internal dual-access memories
- One direct memory access (DMA) channel (a two-channel DMA on the
TMS320C32) supporting concurrent I/O
- Short machine-cycle time
General-purpose applications are greatly enhanced by the large address
space, multiprocessor interface, internally and externally generated wait states,
two external interface ports (one on the ’C31 and the ’C32) two timers, two serial
ports (one on the ’C31, ’VC33, and the ’C32), and multiple-interrupt structure.
The ’C3x supports a wide variety of system applications from host processor to
dedicated coprocessor.
High-level language is implemented more easily through a register-based architecture, large address space, powerful addressing modes, flexible instruction
set, and well-supported floating-point arithmetic.
Figure 1−1 shows a block diagram of ’C3x devices.
1-2
TMS320C3x Devices
Figure 1−1. TMS320C3x Devices Block Diagram
-
./0/
50 *"%&'
7
7
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6
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78
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7
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6
TMS320C3x Key Specifications
The key specifications of the ’C3x devices include the following:
-
1.1.2
Performance up to 60 MFLOPS
Highly efficient C language engine
Large address space: 16M words 32 bits
Fast memory management with on-chip DMA
Industry-exclusive 3-V versions available on some devices
TMS320C30
The ’C30 is the first member of the ’C3x generation. It differs from the
’C31/VC33 and ’C32 by offering 4K ROM, 2K RAM, a second serial port, and
a second external bus.
1.1.3
TMS320C31 and TMS320LC31
The ’C31 and ’LC31 are the second members of the ’C3x generation. They are
low-cost 32-bit floating-point DSPs which have a boot-loader program, 2K RAM,
single external port, single serial port, and are available in 3.3-V operation
(’LC31).
Introduction
1-3
TMS320C3x Devices
1.1.4
TMS320C32
The ’C32 is the newest member of the ’C3x generation. They are enhanced
versions of the ’C3x family and the lowest cost floating-point processors on the
market today. These enhancements include a variable-width memory interface, two-channel DMA coprocessor with configurable priorities, flexible boot
loader, and a relocatable interrupt vector table.
1.1.5
TMS320VC33
The .VC33 is the fourth member of the .C3x generation. This is a low−cost
32−bit floating-point DSPs which has a boot-loader program, 34K RAM, single
external port, single serial port, and is fabricated in an ultra−low power
(3.3−V/1.8−V) CMOS process.
1-4
60
33
60
50
40
(3.3 V)
33
60
33
40
50
50
75
27
40
40
50
33
50
60
27
40
75
Freq
(MHz)
’LC31
(5 V)
’C31
(5 V)
’C30
Device
Name
Cycle
Time
(ns)
2K
2K
2K
2K
2K
2K
2K
2K
2K
2K
2K
RAM
Boot loader
Boot loader
Boot loader
Boot loader
Boot loader
Boot loader
Boot loader
4K
4K
4K
4K
ROM
On-Chip
64
64
64
64
64
64
64
64
64
64
64
Cache
Memory (words)
1
16M 32
1
1
16M 32
1
16M 32
16M 32
1
16M 32
1
1
16M 32
16M 32
2
16M 32
8K 32
2
16M 32
8K 32
2
2
16M 32
8K 32
16M 32
8K 32
Serial
Parallel
Off-Chip
1
1
1
1
1
1
1
1
1
1
1
DMA
Channels
Peripherals
2
2
2
2
2
2
2
2
2
2
2
Timers
132 PQFP
132 PQFP
132 PQFP
132 PQFP
132 PQFP
132 PQFP
132 PQFP
181 PGA
208 PQFP
181 PGA
208 PQFP
181 PGA
181 PGA
Package
Type
Table 1−1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison
0° to 85° (commercial)
0° to 85° (commercial)
0° to 85° (commercial)
−40° to 125° (extended)
0° to 85° (commercial)
−40° to 125° (extended)
0° to 85° (commercial)
−40° to 125° (extended)
−55° to 125° (military)
0° to 85° (commercial)
−40° to 125° (extended)
−55° to 125° (military)
0° to 85° (commercial)
−55° to 125° (military)
0° to 85° (commercial)
0° to 85° (commercial)
0° to 85° (commercial)
−55° to 125° (military)
0° to 85° (commercial)
Temperature
TMS320C3x Devices
Introduction
1-5
1-6
(5 V)
’C32
Device
Name
40
60
33
40
50
Freq
(MHz)
50
Cycle
Time
(ns)
512
512
512
RAM
Boot loader
Boot loader
Boot loader
ROM
On-Chip
64
64
64
Cache
Memory (words)
16M 32/16/8
1
1
1
16M 32/16/8
16M 32/16/8
Serial
Parallel
Off-Chip
2
2
2
DMA
Channels
Peripherals
2
2
2
Timers
144 PQFP
144 PQFP
144 PQFP
Package
Type
Temperature
0° to 85° (commercial)
0° to 85° (commercial)
−40° to 125° (extended)
−55° to 125° (military)
0° to 85° (commercial)
−40° to 125° (extended)
Table 1−1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison (Continued)
TMS320C3x Devices
Typical Applications
1.2 Typical Applications
The TMS320 family’s versatility, realtime performance, and multiple functions
offer flexible design approaches in a variety of applications, which are shown
in Table 1−2.
Table 1−2. Typical Applications of the TMS320 Family
General-Purpose DSP
Graphics/Imaging
Instrumentation
Digital filtering
Convolution
Correlation
Hilbert transforms
Fast Fourier transforms
Adaptive filtering
Windowing
Waveform generation
3-D transformations rendering
Robot vision
Image transmission/compression
Pattern recognition
Image enhancement
Homomorphic processing
Workstations
Animation/digital map
Bar-code scanners
Spectrum analysis
Function generation
Pattern matching
Seismic processing
Transient analysis
Digital filtering
Phase-locked loops
Voice/Speech
Control
Military
Voice mail
Speech vocoding
Speech recognition
Speaker verification
Speech enhancement
Speech synthesis
Text-to-speech
Neural networks
Disk control
Servo control
Robot control
Laser printer control
Engine control
Motor control
Kalman filtering
Secure communications
Radar processing
Sonar processing
Image processing
Navigation
Missile guidance
Radio frequency modems
Sensor fusion
Telecommunications
Automotive
Echo cancellation
ADPCM transcoders
Digital PBXs
Line repeaters
Channel multiplexing
Modems
Adaptive equalizers
DTMF encoding/decoding
Data encryption
FAX
Cellular telephones
Speaker phones
Digital speech
Interpolation (DSI)
X.25 packet switching
Video conferencing
Spread spectrum
Communications
Engine control
Vibration analysis
Antiskid brakes
Anticollision
Adaptive ride control
Global positioning
Navigation
Voice commands
Digital radio
Cellular telephones
Consumer
Industrial
Medical
Radar detectors
Power tools
Digital audio/TV
Music synthesizer
Toys and games
Solid-state answering
Machines
Robotics
Numeric control
Security access
Power line monitors
Visual inspection
Lathe control
CAM
Hearing aids
Patient monitoring
Ultrasound equipment
Diagnostic tools
Prosthetics
Fetal monitors
MR imaging
Introduction
Introduction
1-7
1-8
Chapter 2
This chapter provides an architectural overview of the ’C3x processor. It includes
a discussion of the CPU, memory interface, boot loader, peripherals, and direct
memory access (DMA) of the ’C3x processor.
Topic
Page
2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3
CPU Primary Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4
Other Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.5
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.6
Internal Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.7
External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.9
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.10 Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.11 TMS320C30, TMS320C31/VC33, and TMS320C32 Differences . . . . 2-26
2-1
Overview
2.1 Overview
The ’C3x architecture responds to system demands that are based on sophisticated arithmetic algorithms that emphasize both hardware and software solutions. High performance is achieved through the precision and wide dynamic
range of the floating-point units, large on-chip memory, a high degree of parallelism, and the DMA controller.
Note: VC33
The TMS320VC33 is logically and functionally a superset of the TMS320C31
making nearly all literature and documentation for the TMS320C31 applica−
ble. However, the electrical characteristics are different and are covered in
detail in the TMS320VC33 data sheet (literature number SPRS087).
Figure 2−1 through Figure 2−3 show functional block diagrams of the ’C30,
’C31/VC33, and ’C32 architectures, respectively.
2-2
Overview
Figure 2−1. TMS320C30 Block Diagram
32
RAM
block 1
(1K × 32)
RAM
block 0
(1K × 32)
Cache
(64 × 32)
24
24
32
24
ÉÉÉ
ÉÉÉ
ROM
block
(4K × 32)
32
24
ÉÉÉ
ÉÉÉÉÉ
É
ÉÉÉÉÉ
É
ÉÉ
32
XRDY
MSTRB
IOSTRB
XR/W
XD31−XD0
XA12−XA0
PDATA bus
DDATA bus
Multiplexer
RDY
HOLD
HOLDA
STRB
R/W
D31−D0
A23−A0
Multiplexer
PADDR bus
DADDR1 bus
DADDR2 bus
DMADATA bus
DMAADDR bus
32
24
32
24
24
32
Serial port 0
24
Port-control
register
DMA controller
R/X timer
register
Global-control
register
Data-transmit
register
Multiplexer
Destinationaddress
register
REG1
Transfercounter
register
REGISTER2
REGISTER 1
CPU1
REG2
32
32
40
40
32-bit
barrel
shifter
ALU
Multiplier
40
40
40
Extendedprecision
registers
(R7−R0)
40
32
40
BK
ARAU1
24
Auxiliary
registers
(AR0−AR7)
R/Xtimer
register
Data-transmit
register
FSX1
DX1
CLKX1
FSR1
DR1
CLKR1
Data-receive
register
Timer0
Global-control
register
TCLK0
Timer-counter
register
32
32
Other
registers
(12)
Global-control
register
Timer-period
register
32
DDATA bus − data data bus
Port-control
register
24
Legend:
PADDR bus − program address bus
Serial port 1
Timer1
24
24
32
32
PDATA bus − program data bus
40
ÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
Timer-period
register
DISP0, IR0, IR1
ARAU0
Data-receive
register
Peripheral Address Bus
CPU1
CPU2
Controller
RESET
INT3−0
IACK
MC/MP
XF(1,0)
VDD(3-0)
IODVDD(1,0)
ADVDD(1,0)
PDVDD
DDVDD(1,0)
MDVDD
VSS(3-0)
DVSS(3−0)
CVSS(1,0)
IVSS
VBBP
SUBS
X1
X2/CLKIN
H1
H3
EMU6-0
RSV10−0
SHZ
Source-address
register
Peripheral Data Bus
IR
PC
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
TCLK1
Timer-counter
register
32
Port control
Primary
DADDR1 bus − data address 1 bus
DADDR2 bus − data address 2 bus
Expansion
Architectural Overview
2-3
Overview
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
Figure 2−2. TMS320C31 Block Diagram
RAM
block 0
(1K × 32)
Cache
(64 × 32)
32
24
RAM
block 1
(1K × 32)
32
24
24
Boot
loader
32
24
PDATA bus
32
PADDR bus
Multiplexer
MUX
STRB
R/W
Multiplexer
RDY
HOLD
HOLDA
DDATA bus
DADDR1 bus
DADDR2 bus
D31− D0
A23 − A0
DMADATA bus
DMAADDR bus
32
24
24
32
32
24
24
DMA controller
Serial port 0
Serial-port control
register
Global-control
register
Multiplexer
IR
Destinationaddress
register
REG1
Transfercounter
register
REG2
REG1
CPU1
REG2
Controller
VSS(24 − 0)
CPU2
32
32
40
40
32-bit
barrel
shifter
Multiplier
SHZ
X1
X2 / CLKIN
40
H1
H3
EMU(3 − 0)
40
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Data-receive
register
Timer0
Global-control
register
ALU
40
32
Data-transmit
register
Peripheral Address Bus
INT(3 − 0)
IACK
MCBL / MP
XF(1,0)
VDD(19 − 0)
Source-address
register
CPU1
Peripheral Data Bus
PC
RESET
Receive/transmit
timer register
40
Extendedprecision
registers
(R7−R0)
40
40
Timer-period
register
TCLK0
Timer-counter
register
Timer1
DISP0, IR0, IR1
Global-control
register
ARAU0
BK
ARAU1
24
24
Legend:
PDATA bus − program data bus
24
32
32
Auxiliary
registers
(AR0 − AR7)
DDATA bus − data data bus
32
DADDR1 bus − data address 1 bus
32
2-4
Other
registers
(12)
Timer-counter
register
24
Port Control
32
PADDR bus − program address bus
DADDR2 bus − data address 2 bus
Timer-period
register
32
Primary STRBcontrol register
TCLK1
Overview
Figure 2−3. TMS320C32 Block Diagram
RAM
block 0
(256 × 32)
Program
cache
(64 × 32)
24
32 24
RAM
block 1
(256 × 32)
32
24
32
ÉÉÉ
ÉÉÉ
Boot
ROM
24
32
32
PC
24
PADDR bus
Multiplexer
DDATA bus
DADDR1 bus
DADDR2 bus
External
memory
interface
DMADATA bus
Controller
DMAADDR bus
Multiplexer
DMA controller
STRB0 control reg.
DMA channel 0
Source-address register
Destination-address register
Transfer-counter rregister
REG2
REG1
32
40
Multiplier
40
40
40
32
Source-address register
Destination register
40
32-bit
barrel
shifter
ALU
Transfer-counter
40
Extendedprecision
registers
(R0−R7)
40
ARAU0
32
32
BK
40
IOSTRB control reg.
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
Serial port
Serial-port
control register
Receive/transmit
(R/X) timer register
Data-transmit
register
Timer0
ARAU1
Timer-period
register
24
Timer-counter
register
Auxiliary
registers
(AR0−AR7)
Other
registers
(12)
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Data-receive
register
Global-control
register
DISP0, IR0, IR1
24
24
32
32
IOSTRB
DMA channel 1
Global-control register
REG2
32
STRB1 control reg.
Peripheral address bus
CPU1
CPU2
REG1
CPU1
STRB1
Global-control register
Multiplexer
STRB0_B3/A−1
STRB0_B2/A−2
STRB0_B1
STRB0_B0
STRB1_B3/A−1
STRB1_B2/A−2
STRB1_B1
STRB1_B0
IOSTRB
STRB0
Peripheral data bus
RESET
INT(3-0)
IACK
XF(1,0)
H1
H3
MCBL / MP
CLKIN
CVSS(6-0)
DVSS(6-0)
IVSS(3-9)
DVDD(11-3)
VDDL(7-0)
VSSL(5-0)
VSUBS
SHZ
EMU0−3
A23 − A0
D31 − D0
R/W
RDY
HOLD
HOLDA
PRGW
PDATA bus
IR
24
Timer1
32
Global-control
register
32
Timer-period
register
TCLK0
TCLK1
Timer-counter
register
Legend:
PDATA bus − program data bus
PADDR bus − program address bus
DDATA bus − data data bus
DADDR1 bus − data address 1 bus
DADDR2 bus − data address 2 bus
Architectural Overview
2-5
Central Processing Unit (CPU)
2.2 Central Processing Unit (CPU)
The ’C3x devices (’C30, ’C31/VC33, and ’C32) have a register-based CPU architecture. The CPU consists of the following components:
-
Floating-point/integer multiplier
Arithmetic logic unit (ALU)
32-bit barrel shifter
Internal buses (CPU1/CPU2 and REG1/REG2)
Auxiliary register arithmetic units (ARAUs)
CPU register file
Figure 2−4 shows a diagram of the various CPU components.
2-6
Central Processing Unit (CPU)
Figure 2−4. Central Processing Unit (CPU)
DADDR1 bus
DADDR2 bus
DDATA bus
Multiplexer
CPU1 bus
CPU2 bus
REG1 bus
REG2 bus
REG1 bus
CPU1 bus
DADDR2 bus
DADDR1 bus
REG2 bus
32
32
Multiplier
40
40
32-bit barrel
shifter
ALU
40
40
Extendedprecision
registers
(R0−R7)
40
32
40
40
40
Disp†, IR0, IR1
ARAU0
24
24
32
32
32
32
BK ARAU1
24
Auxiliary
registers
(AR0−AR7)
Other
registers
(12)
24
32
32
† Disp = an 8-bit integer displacement carried in a program-control instruction
Architectural Overview
2-7
Central Processing Unit (CPU)
2.2.1
Floating-Point/Integer Multiplier
The multiplier performs single-cycle multiplications on 24-bit integer and 32-bit
floating-point values. The ’C3x implementation of floating-point arithmetic allows
for floating-point or fixed-point operations at speeds up to 33-ns per instruction
cycle. To gain even higher throughput, you can use parallel instructions to perform
a multiply and an ALU operation in a single cycle.
When the multiplier performs floating-point multiplication, the inputs are 32-bit
floating-point numbers, and the result is a 40-bit floating-point number. When
the multiplier performs integer multiplication, the input data is 24 bits and yields
a 32-bit result. See Chapter 5, Data Formats and Floating-Point Operation, for
detailed information.
2.2.2
Arithmetic Logic Unit (ALU) and Internal Buses
The ALU performs single-cycle operations on 32-bit integer, 32-bit logical,
and 40-bit floating-point data, including single-cycle integer and floatingpoint conversions. Results of the ALU are always maintained in 32-bit integer
or 40-bit floating-point formats. The barrel shifter is used to shift up to 32 bits
left or right in a single cycle. See Chapter 5, Data Formats and Floating-Point
Operation, for detailed information.
Four internal buses, CPU1, CPU2, REG1, and REG2 carry two operands from
memory and two operands from the register file, allowing parallel multiplies
and adds/subtracts on four integer or floating-point operands in a single cycle.
2.2.3
Auxiliary Register Arithmetic Units (ARAUs)
Two auxiliary register arithmetic units (ARAU0 and ARAU1) can generate two
addresses in a single cycle. The ARAUs operate in parallel with the multiplier
and ALU. They support addressing with displacements, index registers (IR0 and
IR1), and circular and bit-reversed addressing. See Chapter 6, Addressing
Modes, for more information.
2-8
CPU Primary Register File
2.3 CPU Primary Register File
The ’C3x provides 28 registers in a multiport register file that is tightly coupled
to the CPU. Table 2−1 lists the register names and functions.
All of the primary registers can be operated upon by the multiplier and ALU and
can be used as general-purpose registers. The registers also have some special
functions. For example, the eight extended-precision registers are especially
suited for maintaining extended-precision floating-point results. The eight auxiliary
registers support a variety of indirect addressing modes and can be used as
general-purpose 32-bit integer and logical registers. The remaining registers
provide such system functions as addressing, stack management, processor
status, interrupts, and block repeat. See Chapter 3, CPU Registers, for more
information.
Table 2−1. Primary CPU Registers
Register
Name
Assigned Function
R0
Section
Page
Extended-precision register 0
3.1.1
3-3
R1
Extended-precision register 1
3.1.1
3-3
R2
Extended-precision register 2
3.1.1
3-3
R3
Extended-precision register 3
3.1.1
3-3
R4
Extended-precision register 4
3.1.1
3-3
R5
Extended-precision register 5
3.1.1
3-3
R6
Extended-precision register 6
3.1.1
3-3
R7
Extended-precision register 7
3.1.1
3-3
AR0
Auxiliary register 0
3.1.2
3-4
AR1
Auxiliary register 1
3.1.2
3-4
AR2
Auxiliary register 2
3.1.2
3-4
AR3
Auxiliary register 3
3.1.2
3-4
AR4
Auxiliary register 4
3.1.2
3-4
AR5
Auxiliary register 5
3.1.2
3-4
AR6
Auxiliary register 6
3.1.2
3-4
AR7
Auxiliary register 7
3.1.2
3-4
DP
Data-page pointer
3.1.3
3-4
IR0
Index register 0
3.1.4
3-4
Architectural Overview
2-9
CPU Primary Register File
Table 2−1. Primary CPU Registers (Continued)
Register
Name
Assigned Function
IR1
Section
Page
Index register 1
3.1.4
3-4
BK
Block-size register
3.1.5
3-4
SP
System-stack pointer
3.1.6
3-4
ST
Status register
3.1.7
3-5
IE
CPU/DMA interrupt-enable register
3.1.8
3-9
IF
CPU interrupt flag
3.1.9
3-11
IOF
I/O flag
3.1.10
3-16
RS
Repeat start-address
3.1.11
3-17
RE
Repeat end-address
3.1.11
3-17
RC
Repeat counter
3.1.11
3-17
The extended-precision registers (R7−R0) can store and support operations
on 32-bit integers and 40-bit floating-point numbers. Any instruction that assumes
the operands are floating-point numbers uses bits 39−0. If the operands are
either signed or unsigned integers, only bits 31−0 are used; bits 39−32 remain
unchanged. This is true for all shift operations. See Chapter 5, Data Formats and
Floating-Point Operation, for extended-precision register formats for floatingpoint and integer numbers.
The 32-bit auxiliary registers (AR7−AR0) are accessed by the CPU and
modified by the two ARAUs. The primary function of the auxiliary registers is
the generation of 24-bit addresses. They also can be used as loop counters
or as 32-bit general-purpose registers that are modified by the multiplier and
ALU. See Chapter 6, Addressing Modes, for detailed information and examples
of the use of auxiliary registers in addressing.
The data-page pointer (DP) is a 32-bit register. The eight least significant bits
(LSBs) of the data-page pointer are used by the direct addressing mode as a
pointer to the page of data being addressed. Data pages are 64K words long,
with a total of 256 pages.
The 32-bit index registers (IR0, IR1) contain the value used by the ARAU to
compute an indexed address. See Chapter 6, Addressing Modes, for examples
of the use of index registers in addressing.
2-10
CPU Primary Register File
The ARAU uses the 32-bit block size register (BK) in circular addressing to
specify the data block size.
The system-stack pointer (SP) is a 32-bit register that contains the address
of the top of the system stack. The SP always points to the last element pushed
onto the stack. A push performs a preincrement; a pop performs a postdecrement of the system-stack pointer. The SP is manipulated by interrupts, traps,
calls, returns, and the PUSH and POP instructions. See Section 6.10, System
and User Stack Management, on page 6-29, for more information.
The status register (ST) contains global information relating to the state of the
CPU. Operations usually set the condition flags of the status register according
to whether the result is 0, negative, etc. These include register load and store
operations as well as arithmetic and logical functions. When the status register
is loaded, however, a bit-for-bit replacement is performed with the contents of
the source operand, regardless of the state of any bits in the source operand.
Following a load, the contents of the status register are identical to the contents
of the source operand. This allows the status register to be easily saved and
restored. See Table 3−2 on page 3-6 for a list and definitions of the status register bits.
The CPU/DMA interrupt-enable register (IE) is a 32-bit register. The CPU
interrupt-enable bits are in locations 10−0. The DMA interrupt-enable bits are
in locations 26−16. A 1 in a CPU/DMA interrupt-enable register bit enables the
corresponding interrupt. A 0 disables the corresponding interrupt. See Section 3.1.8 on page 3-9 for more information.
The CPU interrupt flag register (IF) is also a 32-bit register. A 1 in a CPU
interrupt flag register bit indicates that the corresponding interrupt is set. A
0 indicates that the corresponding interrupt is not set. See Section 3.1.9 on
page 3-11 for more information.
The I/O flag register (IOF) controls the function of the dedicated external pins,
XF0 and XF1. These pins may be configured for input or output and may also
be read from and written to. See Section 3.1.10 on page 3-16 for more information.
The repeat-counter (RC) is a 32-bit register that specifies the number of times
to repeat a block of code when performing a block repeat. When the processor
is operating in the repeat mode, the 32-bit repeat start-address register (RS)
contains the starting address of the block of program memory to repeat, and
the 32-bit repeat end-address register (RE) contains the ending address of the
block to repeat.
Architectural Overview
2-11
Other Registers
2.4 Other Registers
The program-counter (PC) is a 32-bit register containing the address of the
next instruction to fetch. Although the PC is not part of the CPU register file,
it is a register that can be modified by instructions that modify the program flow.
The instruction register (IR) is a 32-bit register that holds the instruction opcode
during the decode phase of the instruction. This register is used by the instruction
decode control circuitry and is not accessible to the CPU.
2-12
Memory Organization
2.5 Memory Organization
The total memory space of the ’C3x is 16M (million) 32-bit words. Program,
data, and I/O space are contained within this 16M-word address space, allowing
the storage of tables, coefficients, program code, or data in either RAM or
ROM. In this way, memory usage is maximized and memory space allocated
as desired.
2.5.1
RAM, ROM, and Cache
Figure 2−5 shows how the memory is organized on the ’C30. RAM blocks 0
and 1 are each 1K 32 bits. The ROM block, available only on the ’C30, is
4K 32 bits. Each RAM and ROM block is capable of supporting two CPU
accesses in a single cycle.
Figure 2−6 shows how the memory is organized on the ’C31/VC33. RAM
blocks 0 and 1 are each 1K 32 bits and support two accesses in a single
cycle. The VC33 has two additional 16K RAM blocks bringing the total on−chip
memory to 34K words (see the TMS320VC33 Data Sheet, literature number
SPRS087). A boot loader allows the loading of program and data at reset from
8-, 16-, 32-bit-wide memories or serial port.
Figure 2−7 shows how the memory is organized on the ’C32. RAM blocks 0
and 1 are each 256 32 bits and support two accesses in a single cycle. A
boot loader allows the loading of program and data at reset from 1-, 2-, 4-, 8-,
16-, and 32-bit-wide memories or serial port. The ’C32 enhanced external
memory interface provides the flexibility to address 8-, 16-, or 32-bit data independently of the external memory width. The external memory width can be 8-, 16-,
or 32-bits wide.
The ’C3x’s separate program, data, and DMA buses allow for parallel program
fetches, data reads and writes, and DMA operations. For example, the CPU can
access two data values in one RAM block and perform an external program
fetch in parallel with the DMA controller loading another RAM block, all within
a single cycle.
Architectural Overview
2-13
Memory Organization
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
Figure 2−5. Memory Organization of the TMS320C30
Cache
(64 32)
32
24
RAM
block 0
(1K 32)
24
RAM
block 1
(1K 32)
32
24
ROM block
(4K 32)
24
32
32
PDATA bus
XRDY
MSTRB
IOSTRB
XR/W
XD31−XD0
XA12−XA0
DDATA bus
DADDR2 bus
DMADATA bus
Program counter/
instruction register
32
24
CPU
24
32
24
DMA
controller
Peripheral bus
DADDR1 bus
DMAADDR bus
32
24
2-14
Multiplexer
Multiplexer
PADDR bus
RDY
HOLD
HOLDA
STRB
R/W
D31−D0
A23−A0
Memory Organization
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
Figure 2−6. Memory Organization of the TMS320C31/VC33
Cache
(64 32)
32
24
RAM
block 0
(1K 32)
24
RAM
block 1
(1K 32)
32
24
32
24
32
Boot ROM
24
32
PDATA bus
DDATA bus
DADDR1 bus
DADDR2 bus
DMADATA bus
DMAADDR bus
32
24
Program counter/
instruction register
CPU
24
32
24
Peripheral bus
Multiplexer
Multiplexer
PADDR bus
RDY
HOLD
HOLDA
STRB
R/W
D31−D0
A23−A0
DMA
controller
Architectural Overview
2-15
Memory Organization
Figure 2−7. Memory Organization of the TMS320C32
Cache
(64 32)
32
24
RAM
block 1
(256 32)
32
24
32
24
Boot ROM
24
32
32
PDATA bus
PADDR bus
DDATA bus
DADDR1 bus
DADDR2 bus
DMADATA bus
DMAADDR bus
32
24
Program counter/
instruction register
CPU
24
32
24
Peripheral bus
Multiplexer
Enhanced
external
memory
interface
Multiplexer
A23 −A0
D31 −D0
R/W
HOLD
HOLDA
PRGW
STRB0_B3/A-1
STRB0_B2/A-2
STRB0_B1
STRB0_B0
STRB1_B3/A-1
STRB1_B2/A-2
STRB1_B1
STRB1_B0
IOSTRB
24
RAM
block 0
(256 32)
DMA
controller
A 64 32-bit instruction cache is provided to store often-repeated sections
of code, which greatly reduces the number of off-chip accesses. This allows
for code to be stored off chip in slower, lower-cost memories. The external
buses are also freed for use by the DMA, external memory fetches, or other
devices in the system.
See Chapter 4, Memory and the Instruction Cache, for more information.
2-16
Memory Organization
2.5.2
Memory Addressing Modes
The ’C3x supports a base set of general-purpose instructions as well as arithmeticintensive instructions that are particularly suited for digital signal processing and
other numeric-intensive applications. See Chapter 6, Addressing Modes, for more
information.
Four groups of addressing modes are provided on the ’C3x. Each group uses
two or more of several different addressing types. The following list shows the
addressing modes with their addressing types.
- General instruction addressing modes:
J
Register. The operand is a CPU register.
J
Short immediate. The operand is a 16-bit (short) or 24-bit (long) immediate value.
J
Direct. The operand is the contents of a 24-bit address formed by
concatenating the 8 bits of data-page pointer and a 16-bit operand.
J
Indirect. An auxiliary register indicates the address of the operand.
- 3-operand instruction addressing modes:
J
Register. Same as for general addressing mode.
J
Indirect. Same as for general addressing mode.
- Parallel instruction addressing modes:
J
Register. The operand is an extended-precision register.
J
Indirect. Same as for general addressing mode.
- Branch instruction addressing modes:
J
Register. Same as for general addressing mode.
J
PC-relative. A signed 16-bit displacement or a 24-bit displacement is
added to the PC.
Architectural Overview
2-17
Internal Bus Operation
2.6 Internal Bus Operation
Much of the ’C3x’s high performance is due to internal busing and parallelism.
Separate buses allow for parallel program fetches, data accesses, and DMA
accesses:
- Program buses: PADDR and PDATA
- Data buses: DADDR1, DADDR2, and DDATA
- DMA buses: DMAADDR and DMADATA
These buses connect all of the physical spaces (on-chip memory, off-chip
memory, and on-chip peripherals) supported by the ’C3x. Figure 2−5,
Figure 2−6, and Figure 2−7 show these internal buses and their connections
to on-chip and off-chip memory blocks.
The program counter (PC) is connected to the 24-bit program address bus
(PADDR). The instruction register (IR) is connected to the 32-bit program data
bus (PDATA). These buses can fetch a single instruction word every machine
cycle.
The 24-bit data address buses (DADDR1 and DADDR2) and the 32-bit data
data bus (DDATA) support two data-memory accesses every machine cycle.
The DDATA bus carries data to the CPU over the CPU1 and CPU2 buses. The
CPU1 and CPU2 buses can carry two data-memory operands to the multiplier,
ALU, and register file every machine cycle. Also internal to the CPU are register
buses REG1 and REG2, which can carry two data values from the register file
to the multiplier and ALU every machine cycle. Figure 2−4 shows the buses
internal to the CPU section of the processor.
The DMA controller is supported with a 24-bit address bus (DMAADDR) and
a 32-bit data bus (DMADATA). These buses allow the DMA to perform memory
accesses in parallel with the memory accesses occurring from the data and
program buses.
2-18
External Memory Interface
2.7 External Memory Interface
The ’C30 provides two external interfaces: the primary bus and the expansion
bus. The ’C31/VC33 provides one external interface: the primary bus. The ’C32
provides one enhanced external interface with three independent multi-function
strobes. These buses consist of a 32-bit data bus and a set of control signals. The
primary and enhanced memory buses have a 24-bit address bus, whereas the
expansion bus has a 13-bit address bus. These buses address external program/
data memory or I/O space. The buses also have external RDY signals for waitstate generation. You can insert additional wait states under software control.
Chapter 9, External Memory Interface, covers external bus operation.
The ’C3x family was designed for 32-bit instructions and 32-bit data operations.
This architecture has many advantages, including a high degree of parallelism
and provisions for a C compiler. However, the ’C30 and ’C31/VC33 require a
32-bit-wide external memory even when the data requires only 8- or 16-bit-wide
memories. The ’C32 enhanced external memory interface overcomes this limitation by providing the flexibility to address 8-, 16-, or 32-bit data independently
of the external memory width. In this way, the chip count and the size of external
memory is reduced. The number of memory chips can be further reduced by
the ’C32’s ability to allow code execution from 16- or 32-bit-wide memories. The
’C32 memory interface also reduces the total amount of RAM by allowing the
physical data memory to be 8, 16, or 32 bits wide. Internally, the ’C32 has a
32-bit architecture. So you can treat the ’C32 as a 32-bit device regardless of
the physical external memory width. The external memory interface handles the
conversion between external memory width and ’C32 internal 32-bit architecture.
2.7.1
TMS320C32 16- and 32-Bit Program Memory
The ’C32 executes code from either 16- or 32-bit-wide memories. When
connected to 32-bit memories, ‘C32 program execution is identical to that
of the ’C31/VC33. When connected to 16-bit zero wait-state memory, the
’C32 takes two instruction cycles to fetch a single 32-bit instruction. During
the first cycle, the ’C32 fetches the lower 16 bits. During the second cycle,
the ’C32 fetches the upper 16 bits and concatenates them with the previously fetched lower 16 bits. This process occurs entirely within the memory interface and is transparent to you. An external pin, PRGW, dictates the external program memory width.
Architectural Overview
2-19
External Memory Interface
2.7.2
TMS320C32 8-, 16-, and 32-Bit Data Memory
The ’C32 external memory interface can load and store 8-, 16-, or 32-bit quantities into external memory and convert them into an internally-equivalent 32-bit
representation. The external memory interface accomplishes this without
changing the CPU instruction set. Figure 2−8 shows the supported external
memory widths, data types and sizes for zero wait-state memory and the associated cycle count.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2−8. TMS320C32-Supported Data Types and Sizes and External Memory Widths
Memory Width
8
16
32
Data
8
1-cycle read
1-cycle read
1-cycle read
Type
16
2-cycle read
1-cycle read
1-cycle read
Size
32
4-cycle read
2-cycle read
1-cycle read
To access 8-, 16-, or 32-bit data quantities (types) from 8-, 16-, or 32-bit-wide
memory, the memory interface uses either strobe STRB0 or STRB1, depending
on the address location within the memory map. Each strobe consists of four pins
for byte enables and/or additional addresses. For a 32-bit memory interface, all
four pins are used as strobe byte-enable pins. These strobe byte-enable pins
select one or more bytes of the external memory. For a 16-bit memory interface,
the ’C32 uses one of these pins as an additional address pin, while using two
pins as strobe byte-enable pins. For an 8-bit memory interface, the ’C32 uses
two of these pins as additional address pins while using one pin as strobe pin.
The ’C32 manipulates the behavior of these pins according to the contents of
the bus control registers (one control register per strobe). By setting a few bit
fields in this register, you indicate the data-type size and external memory width.
2-20
Interrupts
2.8 Interrupts
The ’C3x supports four external interrupts (INT3−INT0), a number of internal
interrupts, and a nonmaskable external RESET signal. These can be used to
interrupt either the DMA or the CPU. When the CPU responds to the interrupt,
the IACK pin can be used to signal an external interrupt acknowledge. Section
7.5, Reset Operation, on page 7-21 covers RESET and interrupt processing.
The ’C30 and ’C31 external interrupts are level-triggered. To reduce external
logic and simplify the interface, the ’C32 external interrupts are edge- and levelor level-only triggered. The triggering is user-selectable through a bit in the
status register. The VC33 external interrupts are either edge or level−trig−
gered depending upon the state of the external EDGEMODE pin. See Section 3.1.7, Status Register (ST), for more information.
Two external I/O flags, XF0 and XF1, can be configured as input or output pins
under software control. These pins are also used by the interlocked operations
of the ’C3x. The interlocked-operations instruction group supports multiprocessor communication. See Section 7.4, Interlocked Operations, on page 7-13 for
examples.
Architectural Overview
2-21
Peripherals
2.9 Peripherals
All ’C3x peripherals are controlled through memory-mapped registers on a dedicated peripheral bus. This peripheral bus is composed of a 32-bit data bus and
a 24-bit address bus. This peripheral bus permits straightforward communication to the peripherals. The ’C3x peripherals include two timers and two serial
ports (only one serial port and one DMA coprocessor are available on the
’C31/VC33 and one serial port and two DMA coprocessor channels on the
’C32). Figure 2−9 shows these peripherals with their associated buses and signals. See Chapter 12, Peripherals, for more information.
Figure 2−9. Peripheral Modules
Serial port 0
Port-control register
FSX0
DX0
R/X timer register
Memory
space
Data-transmit register
CLKX0
FSR0
DR0
Data-receive register
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
CLKR0
Serial port 1
Port-control register
R/X timer register
Peripheral address bus
Peripheral data bus
Data-transmit register
Data-receive register
FSX1
DX1
CLKX1
FSR1
DR1
CLKR1
Timer0
Global-control register
Timer-period register
TCLK0
Timer-counter register
Timer1
Global-control register
TCLK1
Timer-period register
2-22
ÉÉÉ
ÉÉÉ
Timer-counter register
Available on ’C30
Peripherals
2.9.1
Timers
The two timer modules are general-purpose 32-bit timer/event counters with
two signaling modes and internal or external clocking. They can signal internally
to the ’C3x or externally to the outside world at specified intervals or they can
count external events. Each timer has an I/O pin that can be used as an input
clock to the timer, as an output signal driven by the timer, or as a general-purpose
I/O pin. See Chapter 12, Peripherals, for more information about timers.
2.9.2
Serial Ports
The bidirectional serial ports (two on ’C30, one each on the ’C31/VC33 and ’C32)
are totally independent. They are identical to a complementary set of control registers that control each port. Each serial port can be configured to transfer 8, 16,
24, or 32 bits of data per word. The clock for each serial port can originate either
internally or externally. An internally generated divide-down clock is provided.
The pins are configurable as general-purpose I/O pins. The serial ports can also
be configured as timers. A special handshake mode allows ’C3x devices to
communicate over their serial ports with guaranteed synchronization.
Architectural Overview
2-23
Direct Memory Access (DMA)
2.10 Direct Memory Access (DMA)
The on-chip DMA controller can read from or write to any location in the
memory map without interfering with the CPU operation. The ’C3x can interface to slow, external memories and peripherals without reducing throughput
to the CPU. The DMA controller contains its own address generators, source
and destination registers, and transfer counter. Dedicated DMA address and
data buses minimize conflicts between the CPU and the DMA controller. A
DMA operation consists of a block or single-word transfer to or from memory.
See Section 12.3, DMA Controller, on page 12-48 for more information.
Figure 2−10 shows the DMA controller and its associated buses.
The ’C30 and ’C31/VC33 DMA coprocessors have one channel, while the ’C32
DMA coprocessor has two channels. Each channel of the ’C32 DMA coprocessor is equivalent to the ’C30/31 DMA with the addition of user-configurable priorities. Because the DMA and CPU have distinct buses on the ’C3x devices, they
can operate independently of each other. However, when the CPU and DMA
access the same on-chip or external resources, the bandwidth can be exceeded
and priorities must be established. The ’C30 and ’C31/VC33 assign highest
priority to the CPU. The ’C32 DMA coprocessor provides more flexibility by allowing you to choose one of the following priorities:
- CPU:
For all resource conflicts, the CPU has priority over the DMA.
- DMA:
For all resource conflicts, the DMA has priority over the CPU.
- Rotating: When the CPU and DMA have a resource conflict during con-
secutive instruction cycles, the CPU is granted priority. On the following
cycle, the DMA is granted priority. Alternate access continues as long as
the CPU and DMA requests conflict in consecutive instruction cycles.
The DMA/CPU priority is configured by the DMA PRI bit fields of the corresponding
DMA global-control register. See Section 12.3, DMA Controller, on page 12-48 for
a complete description.
2-24
Direct Memory Access (DMA)
Figure 2−10. DMA Controller
DMADATA bus
Global-control register
Source-address register
Peripheral address bus
DMA controller
Peripheral data bus
DMAADDR bus
Destination-address register
Transfer-counter register
Architectural Overview
2-25
TMS320C30, TMS320C31/VC33, and TMS320C32 Differences
2.11 TMS320C30, TMS320C31/VC33, and TMS320C32 Differences
Table 2−2 shows the major differences between the ’C32, ’C31/VC33, and the
’C30 devices.
2-26
TMS320C30, TMS320C31/VC33, and TMS320C32 Differences
Table 2−2. Feature Set Comparison
Feature
’C30
’C31/VC33
’C32
External bus
Two buses:
One bus:
One bus:
-
Primary bus:
32-bit data
24-bit address
STRB active for
0h−7FFFFFh and
80A000h−FFFFFFh
32-bit data
24-bit address
STRB active 0h−7FFFFFh
and 80A000h−FFFFFFh
-
32-bit data
24-bit address
STRB0 active for
0h−7FFFFFh and
880000h−8FFFFFh;
-
-
Expansion bus:
32-bit data
13-bit address
MSTRB active for
800000h−801FFFh
IOSTRB active for
804000h−805FFFh
8-, 16-, 32-bit data in
8-, 16-, 32-bit-wide
memory
STRB1 active for
900000h−FFFFFFh;
-
8-, 16-, 32-bit data in
8-, 16-, 32- bit-wide
memory
IOSTRB active for
810000h−82FFFFh
ROM
4k
No
No
Boot loader
No
Yes
Yes
On-chip RAM
2k
address:
809800h−809FFFh
2k
address:
809800h−809FFFh
512
address:
87FE00h−87FFFFh
DMA
1 channel
CPU greater priority than
DMA
1 channel
CPU greater priority than
DMA
2 channels
Configurable priorities
Serial ports
2
1
1
Timers
2
2
2
Interrupts
Level-triggered
Level-triggered
Level-triggered or combination of edge- and
level-triggered
Interrupt vector
table
Fixed 0−3Fh
Microprocessor: 0−3Fh
fixed
Boot loader:
809C1h−809FFFh fixed
Relocatable
Package
208 PQFP
181 PGA
132 PQFP
144 PQFP
Voltage
5V
5 V and 3.3 V
5V
Temperature
0° to 85°C (commercial)
–40 to 125°C (extended)
−55 125°C (military)
0° to 85°C (commercial)
–40 to 125°C (extended)
−55 125°C (military)
0° to 85°C (commercial)
–40 to 125°C (extended)
−55 125°C (military)
Architectural Overview
2-27
2-28
Chapter 3
The central processing unit (CPU) register file contains 28 registers that can
be operated on by the multiplier and arithmetic logic unit (ALU). Included in the
register file are the auxiliary registers, extended-precision registers, and index
registers.
Three registers in the ’C32 CPU register file have been modified to support new
features (2-channel DMAs, program execution from 16-bit memory width, etc.)
The registers modified in the ’C32 are: the status (ST) register, interrupt-enable
(IE) register, and interrupt flag (IF) register.
Topic
Page
3.1
CPU Multiport Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Other Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.3
Reserved Bits and Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3-1
CPU Multiport Register File
3.1 CPU Multiport Register File
The ’C3x provides 28 registers in a multiport register file that is tightly coupled to
the CPU. The program counter (PC) is not included in the 28 registers. All of these
registers can be operated on by the multiplier and the ALU and can be used as
general-purpose 32-bit registers.
Table 3−1 lists the registers’ names and assigned functions of the ’C3x.
Table 3−1. CPU Registers
Register
Symbol
3-2
Register
Machine
Value (hex)
Assigned Function Name
Section
Page
R0
00
Extended-precision register 0
3.1.1
3-3
R1
01
Extended-precision register 1
3.1.1
3-3
R2
02
Extended-precision register 2
3.1.1
3-3
R3
03
Extended-precision register 3
3.1.1
3-3
R4
04
Extended-precision register 4
3.1.1
3-3
R5
05
Extended-precision register 5
3.1.1
3-3
R6
06
Extended-precision register 6
3.1.1
3-3
R7
07
Extended-precision register 7
3.1.1
3-3
AR0
08
Auxiliary register 0
3.1.2
3-4
AR1
09
Auxiliary register 1
3.1.2
3-4
AR2
0A
Auxiliary register 2
3.1.2
3-4
AR3
0B
Auxiliary register 3
3.1.2
3-4
AR4
0C
Auxiliary register 4
3.1.2
3-4
AR5
0D
Auxiliary register 5
3.1.2
3-4
AR6
0E
Auxiliary register 6
3.1.2
3-4
AR7
0F
Auxiliary register 7
3.1.2
3-4
DP
10
Data-page pointer
3.1.3
3-4
IR0
11
Index register 0
3.1.4
3-4
IR1
12
Index register 1
3.1.4
3-4
BK
13
Block-size register
3.1.5
3-4
SP
14
System-stack pointer
3.1.6
3-4
ST
15
Status register
3.1.7
3-5
IE
16
CPU/DMA interrupt-enable
3.1.8
3-9
IF
17
CPU interrupt flags
3.1.9
3-11
IOF
18
I/O flags
3.1.10
3-16
RS
19
Repeat start-address
3.1.11
3-17
RE
1A
Repeat end-address
3.1.11
3-17
RC
1B
Repeat counter
3.1.11
3-17
CPU Multiport Register File
The registers also have some special functions for which they are particularly
appropriate. For example, the eight extended-precision registers are especially
suited for maintaining extended-precision floating-point results. The eight auxiliary
registers support a variety of indirect addressing modes and can be used as
general-purpose 32-bit integer and logical registers. The remaining registers
provide system functions, such as addressing, stack management, processor
status, interrupts, and block repeat. See Chapter 6, Addressing Modes, for more
information.
3.1.1
Extended-Precision Registers (R7−R0)
The eight extended-precision registers (R7−R0) can store and support operations
on 32-bit integer and 40-bit floating-point numbers. These registers consist of two
separate and distinct regions:
- Bits 39−32: dedicated to storage of the exponent (e) of the floating-point
number.
- Bits 31−0: store the mantissa of the floating-point number:
J
J
Bit 31: sign bit (s)
Bits 30−0: the fraction (f)
Any instruction that assumes the operands are floating-point numbers uses
bits 39−0. Figure 3−1 illustrates the storage of 40-bit floating-point numbers
in the extended-precision registers.
Figure 3−1. Extended-Precision Register Floating-Point Format
39
32 31
Exponent
30
0
Sign
Fraction
Mantissa
For integer operations, bits 31−0 of the extended-precision registers contain
the integer (signed or unsigned). Any instruction that assumes the operands
are either signed or unsigned integers uses only bits 31−0. Bits 39−32 remain
unchanged. This is true for all shift operations. The storage of 32-bit integers
in the extended-precision registers is shown in Figure 3−2.
Figure 3−2. Extended-Precision Register Integer Format
39
32 31
Unchanged
0
Signed or unsigned integer
CPU Registers
3-3
CPU Multiport Register File
3.1.2
Auxiliary Registers (AR7−AR0)
The CPU can access the eight 32-bit auxiliary registers (AR7−AR0), and the
two auxiliary register arithmetic units (ARAUs) can modify them. The primary
function of the auxiliary registers is the generation of 24-bit addresses. However,
they can also operate as loop counters in indirect addressing or as 32-bit generalpurpose registers that can be modified by the multiplier and ALU. See Chapter 6, Addressing Modes, for more information.
3.1.3
Data-Page Pointer (DP)
The data-page pointer (DP) is a 32-bit register that is loaded using the load data
page (LDP) instruction (see Chapter 13, Assembly Language Instructions). The
eight LSBs of the data-page pointer are used by the direct addressing mode as a
pointer to the page of data being addressed (see Section 6.3, Direct Addressing,
on page 6-4). Data pages are 64K-words long, with a total of 256 pages. Bits 31−8
are reserved; you must always keep these set to 0 (cleared).
3.1.4
Index Registers (IR0, IR1)
The 32-bit index registers (IR0 and IR1) are used by the ARAU for indexing
the address. See Chapter 6, Addressing Modes, for more information.
3.1.5
Block Size (BK) Register
The 32-bit block size register (BK) is used by the ARAU in circular addressing to
specify the data block size. See Section 6.7, Circular Addressing, on page 6-21
for more information.
3.1.6
System-Stack Pointer (SP)
The system-stack pointer (SP) is a 32-bit register that contains the address of the
top of the system stack. The SP always points to the last element pushed onto
the stack. The SP is manipulated by interrupts, traps, calls, returns, and the
PUSH, PUSHF, POP, and POPF instructions. Stack pushes and pops perform
preincrements and postdecrements on all 32 bits of the SP. However, only the
24 LSBs are used as an address. See Section 6.10, System and User Stack
Management, on page 6-29 for more information.
3-4
CPU Multiport Register File
3.1.7
Status (ST) Register
The status (ST) register contains global information about the state of the CPU.
Operations usually set the condition flags of the status register according to
whether the result is 0, negative, etc. This includes register load and store
operations as well as arithmetic and logical functions. However, when the
status register is loaded, the contents of the source operand replace the ST’s
contents bit for bit, regardless of the state of any bits in the source operand.
Following an ST load, the contents of the status register are identical to the
contents of the source operand. This allows the status register to be saved
easily and restored. At system reset, a 0 is written to this register.
Figure 3−3 shows the format of the status register for the ’C30 and ’C31/VC33
devices. Figure 3−4 shows the format of the status register for the ’C32 device.
Table 3−2 describes the status register bits, their names, and their functions.
Figure 3−3. Status Register (TMS320C30 andTMS320C31/VC33)
31 − 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
xx
xx
xx
GIE
CC
CE
CF
xx
RM
OVM
LUF
LV
UF
N
Z
V
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
R/W R/W R/W
1) xx = reserved bit, read as 0
2) R = read, W = write
Figure 3−4. Status Register (TMS320C32 Only)
31 − 16
xx
Notes:
15
PRGW
status
14
INT
config
R
R/W
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GIE
CC
CE
CF
xx
RM
OVM
LUF
LV
UF
N
Z
V
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W R/W
1) xx = reserved bit, read as 0
2) R = read, W = write
CPU Registers
3-5
CPU Multiport Register File
Table 3−2. Status Register Bits
Bit Name
Reset Value
Name
Description
C
0
Carry flag
Carry condition flag
V
0
Overflow flag
Overflow condition flag
Z
0
Zero flag
Zero condition flag
N
0
Negative flag
Negative condition flag
UF
0
Floating-point underflow flag
Floating-point underflow condition flag
LV
0
Latched overflow flag
Latched overflow condition flag
LUF
0
Latched floating-point
underflow flag
Latched floating-point underflow condition flag
OVM
0
Overflow mode flag
Overflow mode flag
The overflow mode flag affects only integer operations.
If OVM = 0, the overflow mode is turned off and integer
results that overflow are treated in no special way.
If OVM = 1, integer results overflowing in the positive
direction are set to the most positive, 2s-complement
number (7FFF FFFFh), and integer results overflowing
in the negative direction are set to the most negative
32-bit, 2s-complement number (8000 0000h).
RM
0
Repeat mode flag
Repeat mode flag
If RM = 1, the PC is modified in either the repeat-block
or repeat-single mode.
CE
0
Cache enable
CE enables or disables the instruction cache.
Set CE = 1 to enable the cache, allowing the cache to
be used according to the least recently used (LRU)
stack manipulation.
Set CE = 0 to disable the cache, preventing cache
updates or modifications (no cache fetches can be
made). Cache clearing (CC = 1) is allowed when
CE = 0.
Note:
3-6
If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset.
CPU Multiport Register File
Table 3−2. Status Register Bits (Continued)
Bit Name
CF
Reset Value
0
Name
Description
Cache freeze
Enables or disables the instruction cache
Set CF = 1 to freeze the cache (cache is not updated),
including LRU stack manipulation. If the cache is
enabled (CE = 1), fetches from the cache are allowed,
but modification of the cache contents is not allowed.
Cache clearing (CC = 1) is allowed. At reset, this bit
is cleared to 0, but it is set to 1 after reset.
When CF = 0, the cache is automatically updated by
instruction fetches from external memory. Also, when
CF = 0, cache clearing (CC = 1) is allowed.
The following table summarizes the CE and CF bits:
CE
CF
0
0
Cache not enabled
0
1
Cache not enabled
1
0
Cache enabled and not frozen
1
1
Cache enabled but frozen
(cache read only)
Effect
CC
0
Cache clear
CC = 1 invalidates all entries in the cache. This bit is
always cleared after it is written to, and is always read
as 0. At reset, 0 is written to this bit.
GIE
0
Global interrupt-enable
If GIE = 1, the CPU responds to an enabled interrupt.
If GIE = 0, the CPU does not respond to an enabled
interrupt.
INT config
0
Interrupt configuration
(‘C32 only)
Sets the external interrupt signals INT3 − INT0 for levelor edge-triggered interrupts.
INT Config
Note:
Effect
0
All the external interrupts (INT3 − INT0)
are configured as level-triggered
interrupts. Multiple interrupts may be
triggered when the signal is active for
a long period of time.
1
All the external interrupts (INT3 − INT0)
are configured as edge-triggered interrupts. Edge and duration are required
for all interrupts to be recognized.
If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset.
CPU Registers
3-7
CPU Multiport Register File
Table 3−2. Status Register Bits (Continued)
Bit Name
Reset Value
Name
Description
PRGW
Dependent
on PRGW
pin level
Program width status
(‘C32 only)
Indicates the status of the external input PRGW pin.
When the signal of the PRGW pin is high, the PRGW
status bit is set to 1, indicating a 16-bit memory width.
The ‘C32 performs two fetches to retrieve a single 32-bit
instruction word. The PRGW bit is a read-only bit, and
can have the following values:
PRG
Note:
3-8
Effect
0
Instruction fetches use one 32-bit external program memory read.
1
Instruction fetches use two 16-bit external program memory reads.
If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset.
CPU Multiport Register File
3.1.8
CPU/DMA Interrupt-Enable (IE) Register
The CPU/DMA interrupt-enable (IE) register of the ’C30, ’C31/VC33, and ’C32
are 32-bit registers (see Figure 3−5 and Figure 3−6). The CPU interrupt-enable
bits are in locations 10−0 for ’C30 and ’C31/VC33 devices, and 11−0 for ’C32
devices. The direct memory access (DMA) interrupt-enable bits are in locations
26−16 for ‘C30 and ‘C31/VC33 devices, and 31−16 for ’C32 devices. A 1 in a
CPU/DMA IE bit enables the corresponding interrupt. A 0 disables the corresponding interrupt. At reset, 0 is written to this register.
Table 3−3 describes the interrupt-enable register bits, their names, and their
functions.
Figure 3−5. CPU/DMA Interrupt-Enable (IE) Register
(TMS320C30 and TMS320C31/VC33)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
xx
xx
xx
xx
xx
EDINT
(DMA)
ETINT1
(DMA)
ETINT0
(DMA)
ERINT1
(DMA)
EXINT1
(DMA)
ERINT0
(DMA)
EXINT0
(DMA)
EINT3
(DMA)
EINT2
(DMA)
EINT1
(DMA)
EINT0
(DMA)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
5
4
3
2
1
0
EINT3
(CPU)
EINT2
(CPU)
EINT1
(CPU)
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
xx
xx
xx
xx
xx
EDINT
(CPU)
ETINT1
(CPU)
ETINT0
(CPU)
ERINT1
(CPU)
EXINT1
(CPU)
R/W
R/W
R/W
R/W
R/W
Notes:
ERINT0
(CPU)
R/W
EXINT0
(CPU)
R/W
17
16
EINT0
(CPU)
R/W
1) xx = reserved bit, read as 0
2) R = read, W = write
Figure 3−6. CPU/DMA Interrupt-Enable (IE) Register (TMS320C32)
31
30
EINT3
(DMA1)
EINT2
(DMA1)
R/W
R/W
15
xx
29
28
EINT1 EINT0
(DMA1) (DMA1)
R/W
R/W
27
26
25
EDINT0
(DMA1)
EDINT1
(DMA0)
ETINT1
(DMA0)
R/W
R/W
R/W
24
23
22
21
20
ETINT0
(DMA0)
ETINT1
(DMA1)
ETINT0
(DMA1)
ERINT0
(DMA1)
EXINT0
(DMA0)
R/W
R/W
R/W
14
13
12
11
10
9
8
7
xx
xx
xx
EDINT1
(CPU)
EDINT0
(CPU)
ETINT1
(CPU)
ETINT0
(CPU)
xx
R/W
Notes:
R/W
R/W
R/W
6
5
xx
R/W
ERINT0
(CPU)
R/W
R/W
4
EXINT0
(CPU)
R/W
19
R/W
18
17
16
EINT0
EINT3 EINT2 EINT1
(DMA0) (DMA0) (DMA0) (DMA0)
R/W
R/W
R/W
3
2
1
EINT3
(CPU)
EINT2
(CPU)
EINT1
(CPU)
R/W
R/W
R/W
R/W
0
EINT0
(CPU)
R/W
1) xx = reserved bit, read as 0
2) R = read, W = write
CPU Registers
3-9
CPU Multiport Register File
Table 3−3. IE Bits and Functions
Abbreviation
3-10
Reset
Value Description
EINT0 (CPU)
0
CPU external interrupt 0 enable
EINT1 (CPU)
0
CPU external interrupt 1 enable
EINT2 (CPU)
0
CPU external interrupt 2 enable
EINT3 (CPU)
0
CPU external interrupt 3 enable
EXINT0 (CPU)
0
CPU serial port 0 transmit interrupt enable
ERINT0 (CPU)
0
CPU serial port 0 receive interrupt enable
EXINT1 (CPU)
0
CPU serial port 1 transmit interrupt enable (’C30 only)
ERINT1 (CPU)
0
CPU serial port 1 receive interrupt enable (’C30 only)
ETINT0 (CPU)
0
CPU timer0 interrupt enable
ETINT1 (CPU)
0
CPU timer1 interrupt enable
EDINT (CPU)
0
CPU DMA controller interrupt enable
(’C30 and ’C31/VC33 only)
EDINT0 (CPU)
0
CPU DMA0 controller interrupt enable (’C32 only)
EDINT1 (CPU)
0
CPU DMA1 controller interrupt enable (’C32 only)
EINT0 (DMA)
0
DMA external interrupt 0 enable (’C30 and ’C31/VC33
only)
EINT1 (DMA)
0
DMA external interrupt 1 enable (’C30 and ’C31/VC33
only)
EINT2 (DMA)
0
DMA external interrupt 2 enable (’C30 and ’C31/VC33
only)
EINT3 (DMA)
0
DMA external interrupt 3 enable (’C30 and ’C31/VC33
only)
EINT0 (DMA0)
0
DMA0 external interrupt 0 enable (’C32 only)
EINT1 (DMA0)
0
DMA0 external interrupt 1 enable (’C32 only)
EINT2 (DMA0)
0
DMA0 external interrupt 2 enable (’C32 only)
EINT3 (DMA0)
0
DMA0 external interrupt 3 enable (’C32 only)
EXINT0 (DMA)
0
DMA serial port 0 transmit interrupt enable
(’C30 and ’C31/VC33 only)
ERINT0 (DMA)
0
DMA serial port 0 receive interrupt enable
(’C30 and ’C31/VC33 only)
EXINT1 (DMA)
0
DMA serial port 1 transmit interrupt enable (’C30 only)
CPU Multiport Register File
Table 3−3. IE Bits and Functions(Continued)
Abbreviation
3.1.9
Reset
Value Description
ERINT1 (DMA)
0
DMA serial port 1 receive interrupt enable (’C30 only)
EXINT0 (DMA0)
0
DMA0 serial port 1 transmit interrupt enable (’C32 only)
ERINT0 (DMA1)
0
DMA1 serial port 1 receive interrupt enable (’C32 only)
ETINT0 (DMA)
0
DMA timer0 interrupt enable (’C30 and ’C31/VC33)
ETINT1 (DMA)
0
DMA timer1 interrupt enable (’C30 and ’C31/VC33 only)
ETINT0 (DMA0)
0
DMA0 timer1 interrupt enable (’C32 only)
ETINT1 (DMA0)
0
DMA0 timer1 interrupt enable (’C32 only)
ETINT0 (DMA1)
0
DMA1 timer0 interrupt enable (’C32 only)
ETINT1 (DMA1)
0
DMA1 timer1 interrupt enable (’C32 only)
EDINT (DMA)
0
DMA controller interrupt enable (’C30 and ’C31/VC33
only)
EDINT1 (DMA0)
0
DMA0-DMA1 controller interrupt enable (’C32 only)
EDINT0 (DMA1)
0
DMA1-DMA0 controller interrupt enable (’C32 only)
EINT0 (DMA1)
0
DMA1 external interrupt 0 enable (’C32 only)
EINT1 (DMA1)
0
DMA1 external interrupt 1 enable (’C32 only)
EINT2 (DMA1)
0
DMA1 external interrupt 2 enable (’C32 only)
EINT3 (DMA1)
0
DMA1 external interrupt 2 enable (’C32 only)
CPU Interrupt Flag (IF) Register
Figure 3−7, Figure 3−8, and Figure 3−9 show the 32-bit CPU interrupt flag registers (IF) for the ‘C30, ‘C31/VC33, and ‘C32 devices, respectively. A 1 in a CPU
IF register bit indicates that the corresponding interrupt is set. The IF bits are
set to 1 when an interrupt occurs. They may also be set to 1 through software
to cause an interrupt. A 0 indicates that the corresponding interrupt is not set.
If a 0 is written to an IF register bit, the corresponding interrupt is cleared. At reset, 0 is written to this register. Table 3−4 describes the interrupt flag register
bits, their names, and their functions.
CPU Registers
3-11
CPU Multiport Register File
Figure 3−7. TMS320C30 CPU Interrupt Flag (IF) Register
31−16
15−12
11
10
9
xx
yy
yy
DINT
TINT1
R/W
R/W
R/W
Notes:
8
7
6
5
TINT0 RINT1 XINT1 RINT0
R/W
R/W
R/W
R/W
4
3
2
1
0
XINT0
INT3
INT2
INT1
INT0
R/W
R/W
R/W
R/W
R/W
1) xx = reserved bit, read as 0
2) yy = reserved bit, set to 0 at reset; can store value
3) R = read, W = write
Figure 3−8. TMS320C31/VC33 CPU Interrupt Flag (IF) Register
31−16
15−12
11
10
9
8
xx
yy
yy
DINT
TINT1
TINT0
R/W
R/W
R/W
Notes:
7
6
5
4
3
2
1
0
XINT0
INT3
INT2
INT1
INT0
R/W
R/W
R/W
R/W
R/W
5
4
3
2
1
0
xx
xx
RINT0
R/W
R/W
R/W
1) xx = reserved bit, read as 0
2) yy = reserved bit, set to 0 at reset
3) R = read, W = write
Figure 3−9. TMS320C32 CPU Interrupt Flag (IF) Register
31−16
15−12
11
10
9
8
ITTP
xx
DINT1
DINT0
TINT1
TINT0
R/W
R/W
R/W
R/W
Notes:
1) xx = reserved bit, read as 0
2) R = read, W = write
3-12
7
6
xx
xx
RINT0
XINT0
INT3
INT2
INT1
INT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPU Multiport Register File
Table 3−4. IF Bits and Functions
Bit
Name
Reset
Value
INT0
0
External interrupt 0 flag
INT1
0
External interrupt 1 flag
INT2
0
External interrupt 2 flag
INT3
0
External interrupt 3 flag
XINT0
0
Serial port 0 transmit flag
RINT0
0
Serial port 0 receive flag
XINT1
0
Serial port 1 transmit flag (‘C30 only)
RINT1
0
Serial port 1 receive interrupt flag (‘C30 only)
TINT0
0
Timer 0 interrupt flag
TINT1
0
Timer 1 interrupt flag
DINT
0
DMA channel interrupt flag (‘C30 and ‘C31/VC33 only)
DINT0
0
DMA0 channel interrupt flag (‘C32 only)
DINT1
0
DMA1 channel interrupt flag (‘C32 only)
ITTP
0
Interrupt-trap table pointer (see Section 3.1.9.1)
Function
Allows the relocation of interrupt and trap vector tables (‘C32 only)
Note:
If a load of the interrupt flag (IF) register occurs simultaneously with a set of a flag by an
interrupt pulse, the loading of the flag has higher priority and overwrites the value of the
interrupt flag register.
CPU Registers
3-13
CPU Multiport Register File
3.1.9.1
Interrupt-Trap Table Pointer (ITTP)
Similar to the rest of the ‘C3x device family, the ’C32’s reset vector location
remains at address 0. However, the interrupt and trap vectors are relocatable.
This is achieved by the interrupt-trap table pointer (ITTP) bit field in the CPU
interrupt flag register, shown in Figure 3−9. The ITTP bit field dictates the
starting location (base) of the interrupt-trap vector table. This base address
is formed by left shifting by eight bits the value of the ITTP bit field. This shifted
value is called the effective base address and is referenced as EA[ITTP], as
shown in Figure 3−10. Therefore, the location of an interrupt or trap vector
is given by the addition of the effective base address formed by the ITTP bit
field (EA[ITTP]) and the offset of the interrupt or trap vector in the interrupttrap vector table, as shown in Figure 3−11. For example, if the ITTP contains
the value 100h, the serial port transmit interrupt vector is located at 10005h.
Note that the vectors stored in the interrupt-trap vector table are the addresses
of the start of the respective interrupt and trap routines. Furthermore, the
interrupt-trap vector table must lie on a 256-word boundary, since the eight
LSBs of the effective base address of the interrupt-trap vector table are 0.
See Section 7.6, Interrupts, on page 7-26 for more information on interrupt
vector tables.
Figure 3−10. Effective Base Address of the Interrupt-Trap Vector Table
23
EA[ITTP] =
3-14
8
Bits 31 −16 of the CPU interrupt flag register
7
0
00000000
CPU Multiport Register File
Figure 3−11.Interrupt and Trap Vector Locations
EA (ITTP) + 00h
Reserved
EA (ITTP) + 01h
INT0
EA (ITTP) + 02h
INT1
EA (ITTP) + 03h
INT2
EA (ITTP) + 04h
INT3
EA (ITTP) + 05h
XINT0
EA (ITTP) + 06h
RINT0
EA (ITTP) + 07h
Reserved
EA (ITTP) + 08h
Reserved
EA (ITTP) + 09h
TINT0
EA (ITTP) + 0Ah
TINT1
EA (ITTP) + 0Bh
DINT0
EA (ITTP) + 0Ch
DINT1
EA (ITTP) + 0Dh
Reserved
EA (ITTP) + 1Fh
EA (ITTP) + 20h
TRAP0
.
.
.
.
EA (ITTP) + 3Bh
TRAP27
EA (ITTP) + 3Ch
TRAP28 (reserved)
EA (ITTP) + 3Dh
TRAP29 (reserved)
EA (ITTP) + 3Eh
TRAP30 (reserved)
EA (ITTP) + 3Fh
TRAP31 (reserved)
CPU Registers
3-15
CPU Multiport Register File
3.1.10 I/O Flag (IOF) Register
The I/O flag (IOF) register is shown in Figure 3−12 and controls the function
of the dedicated external pins, XF0 and XF1. These pins can be configured for
input or output. The pins can also be read from and written to. At reset, 0 is
written to this register. Table 3−5 describes the I/O flags register bits, their
names, and their functions.
Figure 3−12. I/O Flag (IOF) Register
31−16
15−12
11−8
7
xx
xx
xx
INXF1
6
R
Notes:
5
OUTXF1 I/OXF1
R/W
4
3
2
1
0
xx
INXF0
OUTXF0
I/OXF0
xx
R
R/W
R/W
R/W
1) xx = reserved bit, read as 0
2) R = read, W = write
Table 3−5. IOF Bits and Functions
Bit Name
I/OXF0
Reset
Value
0
Function
If 0, XF0 is configured a general-purpose input pin.
If 1, XF0 is configured a general-purpose output pin.
OUTXF0
0
Data output on XF0.
INXF0
0
Data input on XF0. A write has no effect.
I/OXF1
0
If 0, XF1 is configured a general-purpose input pin.
If 1, XF1 is configured a general-purpose output pin.
3-16
OUTXF1
0
Data output on XF1.
INXF1
0
Data input on XF1. A write has no effect.
CPU Multiport Register File
3.1.11 Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers
The repeat-counter (RC) register is a 32-bit register that specifies the number
of times a block of code is to be repeated when a block repeat is performed.
If RC contains the number n, the loop is executed n + 1 times.
The 32-bit repeat start-address (RS) register contains the starting address of
the program-memory block to be repeated when the CPU is operating in the
repeat mode.
The 32-bit repeat end-address (RE) register contains the ending address of
the program-memory block to be repeated when the CPU is operating in the
repeat mode.
Note: RE < RS
If RE< RS and the block mode is enabled, the code between RE and RS is
bypassed when the program counter encounters the repeat end (RE) address.
CPU Registers
3-17
Other Registers
3.2 Other Registers
3.2.1
Program-Counter (PC) Register
The program counter (PC) is a 32-bit register containing the address of the
next instruction fetch. While the program-counter register is not part of the
CPU register file, it can be modified by instructions that modify the program
flow.
3.2.2
Instruction Register (IR)
The instruction register (IR) is a 32-bit register that holds the instruction opcode during the decode phase of the instruction. This register is used by the
instruction decode control circuitry and is not accessible to the CPU.
3-18
Reserved Bits and Compatibility
3.3 Reserved Bits and Compatibility
To retain compatibility with future members of the ’C3x family of microprocessors,
reserved bits that are read as 0 must be written as 0. You must not modify the
current value of a reserved bit that has an undefined value. In other cases, you
should maintain the reserved bits as specified.
CPU Registers
3-19
3-20
Chapter 4
!" The ’C3x provides a total memory space of 16M (million) 32-bit words that contain
program, data, and I/O space. Two RAM blocks of 1K 32 bits each (available
on the ’C30 and ’C31) or two RAM blocks of 256 32 bits (available on the ’C32)
and a ROM block of 4K 32 bits (available only on the ’C30) or boot loader
(available on the ’C31 and the ’C32) permit two CPU accesses in a single cycle.
The VC33 contains four RAM blocks totaling 34K words plus an internal bootloader identical to the C31 bootloader.
A 64 32-bit instruction cache stores often-repeated sections of code, greatly
reducing the number of off-chip accesses and allowing code to be stored off-chip
in slower, lower-cost memories.
Note: VC33
The TMS320VC33 is logically and functionally a superset of the TMS320C31
making nearly all literature and documentation for the TMS320C31 applica−
ble. However, the electrical characteristics are different and are covered in
detail in the TMS320VC33 data sheet (literature number SPRS087).
Topic
Page
4.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2
Reset/Interrupt/Trap Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.3
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4-1
Memory
4.1 Memory
The ’C3x accesses a total memory space of 16M (million) 32-bit words of program, data, and I/O space and allows tables, coefficients, program code, or
data to be stored in either RAM or ROM. In this way, you can maximize memory
usage and allocate memory space as desired.
RAM blocks 0 and 1 are each 1K 32 bits on the ’C30 and ’C31/VC33. The
ROM block is 4K 32 bits on the ’C30. The ’C31/VC33 and ’C32 have a boot
ROM. By manipulating one external pin (MC/MP or MCBL/MP), you can configure the first 1000h words of memory to address the on-chip ROM or external
RAM. Each on-chip RAM and ROM block can support two CPU accesses in a
single cycle. The separate program buses, data buses, and DMA buses allow for
parallel program fetches, data reads/writes, and DMA operations, which are covered in Chapter 11, Peripherals.
4.1.1
Memory Maps
The following sections describe the memory maps for the ’C30, ’C31/VC33,
and ’C32.
4.1.1.1
TMS320C30 Memory Map
The memory map depends on whether the processor is running in microprocessor mode (MC/MP = 0) or microcomputer mode (MC/MP = 1). The
memory maps for these modes are similar (see Figure 4−1 on page 4-4).
Locations 800000h−801FFFh are mapped to the expansion bus. When this
region is accessed, MSTRB is active. Locations 802000h−803FFFh are
reserved. Locations 804000h−805FFFh are mapped to the expansion bus.
When this region is accessed, IOSTRB is active. Locations 806000h−
807FFFh are reserved. All of the memory-mapped peripheral bus registers
are in locations 808000h−8097FFh. In both modes, RAM block 0 is located
at addresses 809800h−809BFFh, and RAM block 1 is located at addresses
809C00h−809FFFh. Locations 80A000h−0FFFFFFh are accessed over the
external memory port (STRB active).
- Microprocessor Mode
In microprocessor mode, the 4K on-chip ROM is not mapped into the ’C3x
memory map. Locations 0h−03Fh consist of interrupt vector, trap vector,
and reserved locations, all of which are accessed over the external memory
port (STRB active) (see Figure 4−1 on page 4-4). Locations
040h−7FFFFFh are also accessed over the external memory port.
4-2
Memory
- Microcomputer Mode
In microcomputer mode, the 4K on-chip ROM is mapped into locations
0h−0FFFh. There are 192 locations (0h−0BFh) within this block for interrupt
vectors, trap vectors, and a reserved space (’C30). Locations 1000h−
7FFFFFh are accessed over the external memory port (STRB active).
Section 4.1.2, Peripheral Bus Memory Map, on page 4-9 describes the peripheral
memory maps in greater detail and Section 4.2, Reset/Interrupt/Trap Vector Map,
on page 4-14 provides the vector locations for reset, interrupts, and traps.
Be careful! Access to a reserved area produces unpredictable
results.
Memory and the Instruction Cache
4-3
Memory
Figure 4−1. TMS320C30 Memory Maps
0h
03Fh
040h
Reset, interrupt, trap vectors,
and reserved locations (64)
(external STRB active)
801FFFh
802000h
Reset, interrupt, trap vectors,
and reserved locations (192)
0BFh
0C0h
External
STRB active
(8.192M words)
7FFFFFh
800000h
0h
Expansion bus
MSTRB active
(8K words)
0FFFh
1000h
7FFFFFh
800000h
801FFFh
802000h
805FFFh
806000h
Expansion bus
IOSTRB active
(8K words)
803FFFh
804000h
805FFFh
806000h
Peripheral bus
memory-mapped
registers
(Internal)
(6K words internal)
Peripheral bus
memory-mapped
registers
(6K words internal)
8097FFh
809800h
8097FFh
809800h
RAM block 0
(1K words internal)
RAM block 0
(1K words internal)
809BFFh
809C00h
809BFFh
809C00h
RAM block 1
(1K words internal)
External
STRB active
(7.96M words)
Microprocessor mode
4-4
Expansion bus
IOSTRB active
(8K words)
807FFFh
808000h
807FFFh
808000h
FFFFFFh
Expansion bus
MSTRB active
(8K words)
Reserved
(8K words)
Reserved
(8K words)
809FFFh
80A000h
External
STRB active
(8.188M words)
Reserved
(8K words)
Reserved
(8K words)
803FFFh
804000h
ROM
(Internal)
809FFFh
80A000h
FFFFFFh
RAM block 1
(1K words internal)
External
STRB active
(7.96M words)
Microcomputer mode
Memory
4.1.1.2
TMS320C31/VC33 Memory Map
The memory map depends on whether the processor is running in microprocessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The
memory maps for these modes are similar (see Figure 4−2 on page 4-6).
Locations 800000h−807FFFh are reserved. All of the memory-mapped
peripheral bus registers are in locations 808000h−8097FFh. In both modes,
RAM block 0 is located at addresses 809800h−809BFFh, and RAM block 1 is
located at addresses 809C00h−809FFFh. Locations 80A000h−0FFFFFFh
are accessed over the external memory port (STRB active).
- Microprocessor Mode
In microprocessor mode, the boot loader is not mapped into the ’C3x
memory map. Locations 0h−03Fh consist of interrupt vector, trap vector,
and reserved locations, all of which are accessed over the external
memory port (STRB active) (see Figure 4−2 on page 4-6). Locations
040h−7FFFFFh are also accessed over the external memory port.
- Microcomputer Mode
In microcomputer mode, the boot loader ROM is mapped into locations
0h−0FFFh. The last 63 words (809FC1h to 809FFFh) of internal RAM
Block 1 are used for interrupt and trap branches (see Figure 4−2 on page
4-6). Locations 1000h−7FFFFFh are accessed over the external
memory port (STRB active).
Section 4.1.2, Peripheral Bus Memory Map, on page 4-9 describes the
peripheral memory maps in greater detail and Section 4.2, Reset/Interrupt/
Trap Vector Map, on page 4-14 provides the vector locations for reset, interrupts, and traps.
Be careful! Access to a reserved area produces unpredictable
results.
Memory and the Instruction Cache
4-5
Memory
Figure 4−2. TMS320C31/VC33 Memory Maps
0h
03Fh
040h
Reset, interrupt, trap vectors,
and reserved locations (64)
(external STRB active)
External
STRB active
(8.192M words)
0h
Reserved for bootloader operations†
0FFFh
1000h
400000h
Boot 1
Boot 2
7FFFFFh
800000h
7FFFFFh
800000h
Reserved
(32K words)
Reserved
(32K words)
807FFFh
808000h
807FFFh
808000h
8097FFh
809800h
External
STRB
active
(8.188M words)
Peripheral bus
memory-mapped
registers
(6K words internal)
8097FFh
809800h
Peripheral bus
memory-mapped
registers
(6K words internal)
RAM block 0
(1K words internal)
RAM block 0
(1K words internal)
809BFFh
809C00h
809BFFh
809C00h
RAM block 1
(1K − 63 words internal)
RAM block 1
(1K words internal)
809FFFh
80A000h
809FC0h
809FC1h
809FFFh
80A000h
External
STRB active
(7.96M words)
FFFFFFh
FFF000h
FFFFFFh
Microprocessor mode
User program interrupt
and trap branches
(63 words internal)
Boot 3
External
STRB
active
(7.96M words)
Microcomputer/boot-loader mode
† See Section 3.1.3, Data-Page Pointer (DP), on page 3-4 for more information.
4-6
Memory
4.1.1.3
TMS320C32 Memory Map
The memory map depends on whether the processor is running in microprocessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The
memory maps for these modes are similar (see Figure 4−3 on page 4-8).
Locations 800000h−807FFFh, 809800h−80FFFh, and 830000H−87FDFFh are
reserved. Locations 810000h−82FFFFh are mapped to the external bus with
IOSTRB active. All of the memory-mapped peripheral bus registers are in locations 808000h−8097FFh. In both modes, RAM block 0 is located at addresses
87FE00h−87FEFFh, and RAM block 1 is located at addresses 87FF00h−
87FFFFh. Locations 900000h−FFFFFFh are mapped to the external bus with
STRB1 active.
Unlike the fixed interrupt-trap vector table location of the ’C30 and ’C31/VC33
devices, the ’C32 has a user-relocatable interrupt-trap vector table. The interrupt-trap vector table must start on a 256-word boundary. The starting location
is programmed through the interrupt-trap table pointer (ITTP) bit field in the CPU
interrupt flag (IF) register. See Section 3.1.9.1, Interrupt-Trap Table Pointer
(ITTP), on page 3-14.
- Microprocessor Mode
In microprocessor mode, the boot loader is not mapped into the ’C3x memory
map. Locations 0h−7FFFFFFh are accessed over the external memory port
(STRB0 active) with location 0h containing the reset vector.
- Microcomputer Mode
In microcomputer mode, the on-chip boot loader ROM is mapped into
locations 0h−0FFFh. Locations 1000h−7FFFFFh are accessed over the
external memory port (STRB0 active).
The ’C32 boot loader has additional modes over the ’C31/VC33 boot loader to handle the data types, sizes, and memory widths supported by the external memory
interface. The memory boot load supports data transfer with and without handshaking. The handshake mode allows synchronous program transfer by using
two pins as data-acknowledge and data-ready signals.
See Section 4.1.2, Peripheral Bus Memory Map, on page 4-9 and Section 4.2,
Reset/Interrupt/Trap Vector Map, on page 4-14 for more information.
Be careful! Access to a reserved area produces unpredictable
results.
Memory and the Instruction Cache
4-7
Memory
Figure 4−3. TMS320C32 Memory Maps
0h
0h
Reset-vector location
0FFFh
1000h
External memory
STRB0 active
(8.192M words)
External memory
STRB0 active
(8.188M words)
Reserved
(32K words)
Reserved
(32K words)
8097FFh
809800h
Peripheral bus
memory-mapped registers
(6K words internal)
807FFFh
808000h
8097FFh
809800h
Reserved
(26K words)
87FDFFh
87FE00h
87FEFFh
87FF00h
87FFFFh
880000h
8FFFFFh
900000h
RAM block 0
(256 words internal)
RAM block 1
(256 words internal)
External memory
STRB0 active
(512K words)
External memory
STRB1 active
(7.168M words)
Microprocessor mode
4-8
82FFFFh
830000h
87FDFFh
87FE00h
87FEFFh
87FF00h
87FFFFh
880000h
8FFFFFh
900000h
900001h
FFFFFFh
FFFFFFh
Boot 2
External memory
IOSTRB active (128K)
(128K words)
External memory
IOSTRB active (128K)
(128K words)
Reserved
(319.5K words)
Peripheral bus
memory-mapped registers
(6K words internal)
Reserved
(26K words)
80FFFFh
810000h
810001h
80FFFFh
810000h
82FFFFh
830000h
Boot 1
1001h
7FFFFFh
800000h
7FFFFFh
800000h
807FFFh
808000h
Reserved for
boot-loader operations
Reserved
(319.5K words)
RAM block 0
(256 words internal)
RAM block 1
(256 words internal)
External memory
STRB0 active
(512K words)
Boot 3
External memory
STRB1 active
(7.168M words)
Microcomputer/boot-loadermode
Memory
4.1.2
Peripheral Bus Memory Map
The following sections describe the peripherial bus memory maps for the ’C30,
’C31/VC33, and ’C32.
4.1.2.1
TMS320C30 Peripheral Bus Memory Map
The ’C30 memory-mapped peripheral registers are located starting at address
808000h. Figure 4−4 on page 4-10 shows the peripheral bus memory map. The
shaded blocks are reserved.
Memory and the Instruction Cache
4-9
Memory
Figure 4−4. TMS320C30 Peripheral Bus Memory-Mapped Registers
4-10
808000h
DMA global control
808004h
DMA source address
808006h
DMA destination address
808008h
DMA transfer counter
808020h
Timer 0 global control
808024h
Timer 0 counter
808028h
Timer 0 period
808030h
Timer 1 global control
808034h
Timer 1 counter
808038h
Timer 1 period register
808040h
Serial port 0 global control
808042h
FSX/DX/CLKX serial port 0 control
808043h
FSR/DR/CLKR serial port 0 control
808044h
Serial port 0 R/X timer control
808045h
Serial port 0 R/X timer counter
808046h
Serial port 0 R/X timer period
808048h
Serial port 0 data transmit
80804Ch
Serial port 0 data receive
808050h
Serial port 1 global control
808052h
FSX/DX/CLKX serial port 1 control
808053h
FSR/DR/CLKR serial port 1 control
808054h
Serial port 1 R/X timer control
808055h
Serial port 1 R/X timer counter
808056h
Serial port 1 R/X timer period
808058h
Serial port 1 data transmit
80805Ch
Serial port 1 data receive
808060h
Expansion-buscontrol
808064h
Primary-bus control
Memory
4.1.2.2
TMS320C31/VC33 Peripheral Bus Memory Map
The ’C31/VC33 memory-mapped peripheral registers are located starting at
address 808000h. Figure 4−5 shows the peripheral bus memory map. The
shaded blocks are reserved.
Figure 4−5. TMS320C31/VC33 Peripheral Bus Memory-Mapped Registers
808000h
DMA global control
808004h
DMA source address
808006h
DMA destination address
808008h
DMA transfer counter
808020h
Timer 0 global control
808024h
Timer 0 counter
808028h
Timer 0 period
808030h
Timer 1 global control
808034h
Timer 1 counter
808038h
Timer 1 period register
808040h
Serial port global control
808042h
FSX/DX/CLKX serial port control
808043h
FSR/DR/CLKR serial port control
808044h
Serial port R/X timer control
808045h
Serial port R/X timer counter
808046h
Serial port R/X timer period
808048h
Serial port data transmit
80804Ch
Serial port data receive
808064h
Primary-bus control
Memory and the Instruction Cache
4-11
Memory
4.1.2.3
TMS320C32 Peripheral Bus Memory Map
The ’C32’s memory-mapped peripheral and external-bus control registers are
located starting at address 808000h, as shown in Figure 4−6 on page 4-13. The
shaded blocks are reserved.
4-12
Memory
Figure 4−6. TMS320C32 Peripheral Bus Memory-Mapped Registers
808000h
DMA 0 global control
808004h
DMA 0 source address
808006h
DMA 0 destination address
808008h
DMA 0 transfer counter
808010h
DMA 1 global control
808014h
DMA 1 source address
808016h
DMA 1 destination address
808018h
DMA 1 transfer counter
808020h
Timer 0 global control
808024h
Timer 0 counter
808028h
Timer 0 period
808030h
Timer 1 global control
808034h
Timer 1 counter
808038h
Timer 1 period register
808040h
Serial port global control
808042h
FSX/DX/CLKX serial port control
808043h
FSR/DR/CLKR serial port control
808044h
Serial port R/X timer control
808045h
Serial port R/X timer counter
808046h
Serial port R/X timer period
808048h
Serial port data transmit
80804Ch
Serial port data receive
808060h
IOSTRB bus control
808064h
STRB0 bus control
808068h
8097FFh
STRB1 bus control
Memory and the Instruction Cache
4-13
Reset/Interrupt/Trap Vector Map
4.2 Reset/Interrupt/Trap Vector Map
The addresses for the reset, interrupt, and trap vectors are 00h−3Fh, as shown
in Figure 4−7 and Figure 4−8. The reset vector contains the address of the reset
routine.
- ’C30 and ’C31/VC33 Microprocessor and Microcomputer Modes
In the microprocessor mode of the ’C30 and ’C31/VC33 and the microcomputer mode of the ’C30, the reset interrupt and trap vectors stored in
locations 0h−3Fh are the addresses of the starts of the respective reset,
interrupt, and trap routines. For example, at reset, the content of memory
location 00h (reset vector) is loaded into the PC, and execution begins
from that address (see Figure 4−8 on page 4-16).
- ’C31/VC33 Microcomputer/Boot-Loader Mode
In the microcomputer/boot-loader mode of the ’C31/VC33, the interrupt
and trap vectors stored in locations 809FC1h−809FFFh are branch instructions to the start of the respective interrupt and trap routines (see
Figure 4−9 on page 4-17).
- ’C32 Microprocessor and Microcomputer/Boot-Loader Mode
The ’C32 has a user-relocatable interrupt-trap vector table. The interrupttrap vector table must start on a 256-word boundary. The starting location is
programmed through the interrupt-trap table pointer (ITTP) bit field in the
CPU interrupt flag (IF) register. See Section 3.1.9.1, Interrupt-Trap Table
Pointer (ITTP), on page 3-14. The reset vector is stored at location 0h in
microprocessor mode.
4-14
Reset/Interrupt/Trap Vector Map
Figure 4−7. Reset, Interrupt, and Trap Vector Locations for the TMS320C30
Microprocessor Mode
00h
RESET
01h
INT0
02h
INT1
03h
INT2
04h
INT3
05h
XINT0
06h
RINT0
07h
XINT1
08h
RINT1
09h
TINT0
0Ah
TINT1
0Bh
DINT
0Ch
Reserved
1Fh
20h
TRAP 0
D
D
D
3Bh
TRAP 27
3Ch
TRAP 28 (reserved)
3Dh
TRAP 29 (reserved)
3Eh
TRAP 30 (reserved)
3Fh
TRAP 31 (reserved)
Note: Traps 28−31
Traps 28−31 are reserved; do not use them.
Memory and the Instruction Cache
4-15
Reset/Interrupt/Trap Vector Map
Figure 4−8. Reset, Interrupt, and Trap Vector Locations for theTMS320C31/VC33
Microprocessor Mode
00h
RESET
01h
INT0
02h
INT1
03h
INT2
04h
INT3
05h
XINT0
06h
RINT0
07h
XINT1 (Reserved)
08h
RINT1 (Reserved)
09h
TINT0
0Ah
TINT1
0Bh
DINT
0Ch
1Fh
20h
Reserved
TRAP 0
•
•
•
3Bh
TRAP 27
3Ch
TRAP 28 (reserved)
3Dh
TRAP 29 (reserved)
3Eh
TRAP 30 (reserved)
3Fh
TRAP 31 (reserved)
Note: Traps 28−31
Traps 28−31 are reserved; do not use them.
4-16
Reset/Interrupt/Trap Vector Map
Figure 4−9. Interrupt and Trap Branch Instructions for the TMS320C31/VC33
Microcomputer Mode
809FC1h
INT0
809FC2h
INT1
809FC3h
INT2
809FC4h
INT3
809FC5h
XINT0
809FC6h
RINT0
809FC7h
XINT1 (reserved)
809FC8h
RINT1 (reserved)
809FC9h
TINT0
809FCAh
TINT1
809FCBh
DINT
809FCCh
809FDFh
Reserved
809FE0h
TRAP 0
809FE1h
TRAP 1
•
•
•
809FFBh
TRAP 27
809FFCh
TRAP 28 (reserved)
809FFDh
TRAP 29 (reserved)
809FFEh
TRAP 30 (reserved)
809FFFh
TRAP 31 (reserved)
Note: Traps 28−31
Traps 28−31 are reserved; do not use them.
Unlike the ’C31/VC33’s microprocessor mode, the ’C31/VC33 microcomputer/boot loader mode uses a dual-vectoring scheme to service interrupts and
trap requests. In this dual vectoring scheme, a branch instruction rather than
a vector address is used.
Memory and the Instruction Cache
4-17
Reset/Interrupt/Trap Vector Map
Figure 4−10. Interrupt and Trap Vector Locations for TMS320C32
EA (ITTP) + 00h
Reserved
EA (ITTP) + 01h
INT0
EA (ITTP) + 02h
INT1
EA (ITTP) + 03h
INT2
EA (ITTP) + 04h
INT3
EA (ITTP) + 05h
XINT0
EA (ITTP) + 06h
RINT0
EA (ITTP) + 07h
Reserved
EA (ITTP) + 08h
Reserved
EA (ITTP) + 09h
TINT0
EA (ITTP) + 0Ah
TINT1
EA (ITTP) + 0Bh
DINT0
EA (ITTP) + 0Ch
DINT1
EA (ITTP) + 0Dh
Reserved
EA (ITTP) + 1Fh
EA (ITTP) + 20h
TRAP0
.
.
.
.
EA (ITTP) + 3Bh
TRAP27
EA (ITTP) + 3Ch
TRAP28 (reserved)
EA (ITTP) + 3Dh
TRAP29 (reserved)
EA (ITTP) + 3Eh
TRAP30 (reserved)
EA (ITTP) + 3Fh
TRAP31 (reserved)
Note: Traps 28−31
Traps 28−31 are reserved; do not use them.
4-18
Instruction Cache
4.3 Instruction Cache
A 64 × 32-bit instruction cache speeds instruction fetches and lowers system
cost by caching program fetches from external memory. The instruction cache
allows the use of slow, external memories while still achieving single-cycle access
performances. This reduces the number of off-chip accesses necessary and
allows code to be stored off-chip in slower, lower-cost memories. The cache
also frees external buses from program fetches so that they can be used by
the DMA or other system elements.
The cache can operate automatically, with no user intervention. Subsection
4.3.2 describes a form of the least recently used (LRU) cache update algorithm.
4.3.1
Instruction-Cache Architecture
The instruction cache (see Figure 4−12) contains 64 32-bit words of RAM; it
is divided into two 32-word segments. A 19-bit segment start address (SSA)
register is associated with each segment. For each word in the cache, there
is a corresponding single bit-present (P) flag.
When the CPU requests an instruction word from external memory, the cache
algorithm checks to determine if the word is already contained in the instruction
cache. Figure 4−11 shows how the cache-control algorithm partitions an
instruction address. The algorithm uses the19 most significant bits (MSBs) of
the instruction address to select the segment; the five least significant bits
(LSBs) define the address of the instruction word within the pertinent segment.
The algorithm compares the 19 MSBs of the instruction address with the two
SSA registers. If there is a match, the algorithm checks the relevant P flag. The
P flag indicates if a word within a particular segment is already present in cache
memory:
- P = 1: the word is already present in cache memory
- P = 0: the location cache is invalid
Figure 4−11.Address Partitioning for Cache Control Algorithm
23
5 4
Segment start address
(SSA)
0
Instruction word
address within segment
If there is no match, one of the segments must be replaced by the new data. The
segment replaced in this circumstance is determined by the LRU algorithm. The
LRU stack (see Figure 4−12) is maintained for this purpose.
Memory and the Instruction Cache
4-19
Instruction Cache
Figure 4−12. Instruction-Cache Architecture
Segment start
address registers
P
flags
Segment words
0
Segment word 0
1
Segment word 1
LRU
Stack
MRU segment number
SSA register 0
19
LRU segment number
Segment 0
30
Segment word 30
31
Segment word 31
32
SSA register 1
0
Segment word 0
1
Segment word 1
Segment 1
30
Segment word 30
31
Segment word 31
The LRU stack determines which of the two segments qualifies as the least
recently used after each access to the cache. Each time a segment is accessed,
its segment number is removed from the LRU stack and pushed onto the top
of the LRU stack. Therefore, the number at the top of the stack is the most recently used (MRU) segment number, and the number at the bottom of the stack
is the least recently used segment number.
At reset, the LRU stack is initialized with 0 at the top and 1 at the bottom. All
P flags in the instruction cache are cleared.
When a replacement is necessary, the LRU segment is selected for replacement. Also, the 32 P flags for the segment to be replaced are set to 0, and the
segment’s SSA register is replaced with the 19 MSBs of the instruction address.
4-20
Instruction Cache
4.3.2
Instruction-Cache Algorithm
When the ’C3x requests an instruction word from external memory, one of two
possible actions occurs: a cache hit or a cache miss.
- Cache Hit. The cache contains the requested instruction, and the following
actions occur:
J
The instruction word is read from the cache.
J
The number of the segment containing the word is removed from the
LRU stack and pushed to the top of the LRU stack (if it is not already at
the top), thus moving the other segment number to the bottom of the
stack.
- Cache Miss. The cache does not contain the instruction. There are two
types of cache misses:
J
J
Subsegment miss. The segment address register matches the instruction address, but the relevant P flag is not set. The following actions
occur in parallel:
H
The instruction word is read from memory and copied into the cache.
H
The number of the segment containing the word is removed from
the LRU stack and pushed to the top of the LRU stack (if it is not
already at the top), thus moving the other segment number to the
bottom of the stack.
H
The relevant P flag is set.
Segment miss. Neither of the segment addresses matches the instruction address. The following actions occur in parallel:
H
The LRU segment is selected for replacement. The P flags for all
32 words are cleared.
H
The SSA register for the selected segment is loaded with the
19 MSBs of the address of the requested instruction word.
H
The instruction word is fetched and copied into the cache. It goes
into the appropriate word of the LRU segment. The P flag for that
word is set to 1.
H
The number of the segment containing the instruction word is
removed from the LRU stack and pushed to the top of the LRU
stack, thus moving the other segment number to the bottom of
the stack.
Memory and the Instruction Cache
4-21
Instruction Cache
Only instructions may be fetched from the program cache. All reads and writes
of data in memory bypass the cache. Program fetches from internal memory
do not modify the cache and do not generate cache hits or misses. The program cache is a single-access memory block. Dummy program fetches (for
example, those following a branch) are treated by the cache as valid program
fetches and can generate cache misses and cache updates.
Notes: Using Self-Modifying Code
Be careful when using self-modifying code. If an instruction resides in the
cache and the corresponding location in primary memory is modified, the
copy of the instruction in the cache is not modified.
You can use the cache more efficiently by aligning program code on 32-word
address boundaries. Do this with the .align directive when coding assembly
language.
4.3.3
Cache Control Bits
Three cache control bits are located in the CPU status register:
- Cache Clear Bit (CC). Set CC = 1 to invalidate all entries in the cache. This
bit is always cleared after it is written to; it is always read as a 0. At reset,
the cache is cleared, and 0 is written to this bit.
- Cache Enable Bit (CE). Set CE = 1 to enable the cache, allowing the
cache to be used according to the LRU cache algorithm. Set CE = 0 to disable the cache; this prevents cache update modifications (thus, no cache
fetches can be made). At reset, 0 is written to this bit. Cache clearing (CC
= 1) is allowed when CE = 0.
- Cache Freeze Bit (CF). Set CF = 1 to freeze both the cache and LRU
stack manipulation. If the cache is enabled (CE = 1) and the cache is
frozen (CF = 1), fetches from the cache are allowed, but modification of
cache contents is not allowed. Cache clearing (CC = 1) is allowed when
CF = 1 or CF = 0. At reset, this CF bit is cleared to 0.
Table 4−1 shows the combined effect of the CE and CF.
4-22
Instruction Cache
Table 4−1. Combined Effect of the CE and CF Bits
CE
CF
Effect
0
0
Cache not enabled
0
1
Cache not enabled
1
0
Cache enabled and not frozen
1
1
Cache enabled and frozen
When the CE or CF bits of the CPU status register are modified, the following
four instructions may or may not be fetched from the cache or external memory
(see Example 4−1).
When the CC bit of the CPU status register is modified, the following five instructions may or may not be fetched from the cache before the cache is cleared (see
Example 4−1).
Example 4−1. Pipeline Effects of Modifying the Cache Control Bits
Pipeline Operation
Cycle
n
Instructions may
be fetched before
cache cleared.
Fetch
Decode
Read
Execute
Instructions may
be fetched before
cache is enabled
or frozen.
LDI 1000h, ST
n+1
LDI 1h, R1
LDI 1000h, ST
n+2
LDI 2h, R2
LDI 1h, R1
LDI 1000h, ST
n+3
LDI 3h, R3
LDI 2h, R2
LDI 1h, R1
LDI 1000h, ST
n+4
LDI 4h, R4
LDI 3h, R3
LDI 2h, R2
LDI 1h, R1
n+5
LDI 5h, R5
LDI 4h, R4
LDI 3h, R3
LDI 2h, R2
LDI 5h, R5
LDI 4h, R4
LDI 3h, R3
LDI 5h, R5
LDI 4h, R4
n+6
n+7
n+8
Cache cleared
LDI 5h, R5
Memory and the Instruction Cache
4-23
4-24
Chapter 5
#
$
In the ’C3x architecture, data is organized into three fundamental types: integer,
unsigned integer, and floating-point. The terms integer and signed integer are
equivalent. The ’C3x supports short and single-precision formats for signed and
unsigned integers. It also supports short, single-precision, and extendedprecision formats for floating-point data.
Floating-point operations make fast, trouble-free, accurate, and precise computations. Specifically, the ’C3x implementation of floating-point arithmetic facilitates floating-point operations at integer speeds, while preventing problems with
overflow, operand alignment, and other burdensome tasks that are common in
integer operations.
This chapter discusses data formats and floating-point operations supported
in the ’C3x.
Topic
Page
5.1
Integer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2
Unsigned-Integer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3
Floating-Point Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.4
Floating-Point Conversion (IEEE Std. 754) . . . . . . . . . . . . . . . . . . . . . 5-14
5.5
Floating-Point Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.6
Floating-Point Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.7
Normalization Using the NORM Instruction . . . . . . . . . . . . . . . . . . . . . 5-37
5.8
Rounding (RND Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5.9
Floating-Point to Integer Conversion (FIX Instruction) . . . . . . . . . . . 5-41
5.10 Integer to Floating-Point Conversion (FLOAT Instruction) . . . . . . . 5-43
5.11 Fast Logarithms on a Floating-Point Device . . . . . . . . . . . . . . . . . . . . 5-44
5-1
Integer Formats
5.1 Integer Formats
The ’C3x supports two integer formats: a 16-bit short-integer format and a
32-bit single-precision integer format.
Note:
When extended-precision registers are used as integer operands, only bits
31−0 are used; bits 39−32 remain unchanged.
5.1.1
Short-Integer Format
The short-integer format is a 16-bit 2s-complement integer format for immediateinteger operands. For those instructions that assume integer operands, this
format is sign-extended to 32 bits (see Figure 5−1). The range of an integer
si, represented in the short-integer format, is −215 ≤ si ≤ 215 − 1. In Figure 5−1,
s = signed bit.
Figure 5−1. Short-Integer Format and Sign-Extension of Short Integers
15
0
s
Short-integer format
31
16 15
s s s s s s s s s s s s s s s s
0
s
Sign-extension of a short integer
5.1.2
Single-Precision Integer Format
In the single-precision integer format, the integer is represented in 2s-complement notation. The range of an integer sp, represented in the single-precision
integer format, is −231 ≤ sp ≤ 231 − 1. Figure 5−2 shows the single-precision
integer format.
Figure 5−2. Single-Precision Integer Format
31
0
s
5-2
Unsigned-Integer Formats
5.2 Unsigned-Integer Formats
The ’C3x supports two unsigned-integer formats: a 16-bit short format and a
32-bit single-precision format.
Note:
In extended-precision registers, the unsigned-integer operands use only bits
31−0; bits 39−32 remain unchanged.
5.2.1
Short Unsigned-Integer Format
Figure 5−3 shows the16-bit, short, unsigned-integer format for immediate
unsigned-integer operands. For those instructions which assume unsignedinteger operands, this format is zero filled to 32 bits. The range of a short
unsigned integer is 0 ≤ si ≤ 216.
Figure 5−3. Short Unsigned-Integer Format and Zero Fill
15
0
Short unsigned-integer format
31
16 15
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Zero fill of a short unsigned integer
5.2.2
Single-Precision Unsigned-Integer Format
In the single-precision unsigned-integer format, the number is represented as
a 32-bit value, as shown in Figure 5−4. The range of a single-precision unsigned
integer is 0 ≤ sp ≤ 232.
Figure 5−4. Single-Precision Unsigned-Integer Format
31
0
Data Formats and Floating-Point Operation
5-3
Floating-Point Formats
5.3 Floating-Point Formats
The ’C3x supports four floating-point formats:
- A short floating-point format for immediate floating-point operands, consisting
of a 4-bit exponent, a sign bit, and an 11-bit fraction
- (’C32 only) A short floating-point format for use with 16-bit floating-point
data types, consisting of a 2s-complement, 8-bit exponent field, a sign bit,
and a 7-bit fraction
- A single-precision floating-point format by an 8-bit exponent field, a sign
bit, and a 23-bit fraction
- An extended-precision floating-point format consisting of an 8-bit exponent
field, a sign bit, and a 31-bit fraction.
All ’C3x floating-point formats consist of three fields: an exponent field (e), a
single-bit sign field (s), and a fraction field (f). The sign field and fraction field
may be considered as one unit and referred to as the mantissa field (man).
Figure 5−5. General Floating-Point Format
Exponent
Sign
Fraction
Mantissa
The general equation for calculating the value in a floating-point number is:
x ss.f 2 2 e
In the equation, s is the value of the sign bit, s is the inverse of the value of the
sign bit, f is the binary value of the fraction field, and e is the decimal equivalent
of the exponent field.
The mantissa represents a normalized 2s-complement number. In a normalized
representation, a most significant nonsign bit is implied, thus providing an additional bit of precision. The implied sign bit is used as follows:
- If s = 0, then the leading two bits of the mantissa are 01.
- If s = 1, then the leading two bits of the mantissa are 10.
If the sign bit, s, is equal to 0, the mantissa becomes 01.f2, where f is the binary
representation of the fraction field. If s is 1, the mantissa becomes 10.f2, where f
is the binary representation of the fraction field.
For example, if f = 000000000012 and s = 0, the value of the mantissa (man)
is 01.000000000012. If s = 1 for the same value of f, the value of man is
10.000000000012.
5-4
Floating-Point Formats
The exponent field is a 2s-complement number that determines the factor of 2
by which the number is multiplied. Essentially, the exponent field shifts the
binary point in the mantissa. If the exponent is positive, then the binary point is
shifted to the right. If the exponent is negative, then the binary point is shifted
to the left.
For example, if man = 01.000000000012 and the e = 1110, then the binary point
is shifted 11 places to the right, producing the number: 01000000000012,
which is equal to 2049 decimal.
5.3.1
Short Floating-Point Format
In the short floating-point format, floating-point numbers are represented by a
2s-complement, 4-bit exponent field (e) and a 2s-complement, 12-bit mantissa
field (man) with an implied most significant nonsign bit (see Figure 5−6).
Figure 5−6. Short Floating-Point Format
15
12
Exponent
11 10
0
Sign
Fraction
Mantissa
Operations are performed with an implied binary point between bits 11 and 10.
When the implied most significant nonsign bit is made explicit, it is located to the
immediate left of the binary point. The floating-point 2s-complement number x
in the short floating-point format is given by the following:
x = 01.f × 2e
x = 10.f × 2e
x = 0
if s = 0
if s = 1
if e = −8
You must use the following reserved values to represent 0 in the short floatingpoint format:
e = −8
s = 0
f = 0
Data Formats and Floating-Point Operation
5-5
Floating-Point Formats
The following examples illustrate the range and precision of the short floatingpoint format:
Most positive:
Least positive:
Least negative:
Most negative:
5.3.2
x = (2 − 2 −11) × 27 = 2.5594 × 102
x = 1 × 2 −7 = 7.8125 × 10−3
x = (−1−2 −11) × 2 −7 = −7.8163 × 10−3
x = −2 × 27 = −2.5600 × 102
TMS320C32 Short Floating-Point Format for External 16-Bit Data
To facilitate the handling of 16-bit floating-point data types, the ‘C32 uses a new
short floating-point format for external 16-bit data types. Note that the following
short floating-point format is used only in external 16-bit floating-point data
access. This format is different than the 16-bit immediate short floating-point
data format used in the ‘C32’s instruction set.
In the short floating-point format for external 16-bit data-type size, floating-point
numbers are represented by a 2s-complement, 8-bit exponent field (e), a sign bit
(s), and an 8-bit mantissa field (man) with an implied most significant nonsign bit.
Figure 5−7. TMS320C32 Short Floating-Point Format for External 16-Bit Data
15
8
Exponent
76
Sign
0
Fraction
Mantissa
Operations are performed with an implied binary point between bits 7 and 6.
When the implied most significant nonsign bit is made explicit, it is located to the
immediate left of the binary point. The floating-point 2s-complement number x
in the short floating-point format is given by:
x = 01.f × 2e
x = 10.f × 2e
x = 0
if s = 0
if s = 1
if e = −128
You must use the following reserved values to represent 0 in the ‘C32 short
floating-point format for external 16-bit data:
e = −128
s = 0
f = 0
5-6
Floating-Point Formats
The following examples illustrate the range and precision of the ‘C32 short
floating-point format for external 16-bit data:
Most positive:
Least positive
Least negative:
Most negative:
x = (2−2−8) 2127 = 3.3961775 1038
x = 1 2−127 = 5.8774717541 10−39
x = (−1−2−8) 2−127 = −5.9004306 10−39
x = (−2 2127) = −3.4028236 1038
Note that the floating-point instructions (such as LDF, MPYF, ADDF) and the
integer instructions (such as LDI, MPYI, ADDI) produce different results when
accessing the same memory location. The integer load instructions store the
value in the LSBs of the ‘C32’s registers. A bit field in the strobe control register
controls sign extension or zero fill of the MSBs of the integer value. On the other
hand, the floating-point load instructions store the value in the MSBs of the
‘C32’s registers. For example:
If AR1 = 4000h, R1 = 00 0000 0000h, the value stored at memory location
4000h is 0180h, and STRB0 is configured for a physical memory size and data
type size of 16 bits.
The result of: ADDI *AR1,R1
is R1 = 00 0000 0180h, while
The result of: ADDF *AR1,R1 is R1 = 01 C0000000h (= − 3.0), since
− 4.0 + 1.0 = − 3.0
5.3.3
Single-Precision Floating-Point Format
In the single-precision format, the floating-point number is represented by an
8-bit exponent field (e ) and a 2s-complement 24-bit mantissa field (man) with
an implied most significant nonsign bit (see Figure 5−8).
Figure 5−8. Single-Precision Floating-Point Format
31
24 23
Exponent
22
Sign
0
Fraction
Mantissa
Operations are performed with an implied binary point between bits 23 and 22.
When the implied most significant nonsign bit is made explicit, it is located to
the immediate left of the binary point. The floating-point number x is given by
the following:
x = 01.f × 2e
x = 10.f × 2e
x = 0
if s = 0
if s = 1
if e = −128
Data Formats and Floating-Point Operation
5-7
Floating-Point Formats
You must use the following reserved values to represent 0 in the single-precision
floating-point format:
e = − 128
s = 0
f = 0
The following examples illustrate the range and precision of the single-precision
floating-point format:
5.3.4
Most positive:
x = (2 − 2 −23) × 2127 = 3.4028234 × 1038
Least positive:
x = 1 × 2 −127 = 5.8774717 × 10−39
Least negative:
x = (−1−2 −23) × 2 −127 = − 5.8774724 × 10−39
Most negative:
x = −2 × 2127 = − 3.4028236 × 1038
Extended-Precision Floating-Point Format
In the extended-precision format, the floating-point number is represented by
an 8-bit exponent field (e ) and a 32-bit mantissa field (man) with an implied
most significant nonsign bit (see Figure 5−9).
Figure 5−9. Extended-Precision Floating-Point Format
39
32 31 30
Exponent
Sign
0
Fraction
Mantissa
Operations are performed with an implied binary point between bits 31 and 30.
When the implied most significant nonsign bit is made explicit, it is located to
the immediate left of the binary point. The floating-point number x is given by
the following:
x = 01.f × 2e
x = 10.f × 2e
x = 0
if s = 0
if s = 1
if e = −128
You must use the following reserved values to represent 0 in the extendedprecision floating-point format:
e = −128
s = 0
f = 0
5-8
Floating-Point Formats
The following examples illustrate the range and precision of the extendedprecision floating-point format:
5.3.5
Most positive:
x = (2 − 2 −23) × 2127 = 3.4028234 × 1038
Least positive:
x = 1 × 2 −127 = 5.8774717541 × 1038
Least negative:
x = (−1−2 −31) × 2 −127 = − 5.8774717569 × 10−39
Most negative:
x = −2 × 2127 = − 3.4028236691 × 1038
Determining the Decimal Equivalent of a TMS320C3x Floating-Point Format
To convert a ‘C3x floating-point number to its decimal equivalent, follow these
steps:
Step 1: Convert the exponent field to its decimal representation.
The exponent field is a 2s-complement number. To convert a 2scomplement number, look at the MSB. If it is 0, then convert the
binary number to a decimal number. If the MSB is 1, then complement the binary number, add 1 to the result, and then convert this
binary number to a decimal number.
Step 2: Convert the mantissa field to its decimal representation.
The mantissa field is represented as a sign-mantissa number with an
implied 1 and an implied binary point between the sign bit and the fraction field. If the sign bit is cleared (s = 0), form the mantissa by writing
01, and appending the bits in the fraction field after the binary point.
For example, if f = 101000000002, then man = 01.101000000002:
s
Fraction
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rewrite the mantissa as:
Mantissa
0
1
.
1
0
1
0
0
If the sign bit is set (s = 1), form the mantissa by writing 10 and appending the
bits in the fraction field after the binary point. For example, if f = 101000000002,
then man = 10.101000000002.
s
1
Fraction
1
0
1
0
0
0
0
0
0
0
Data Formats and Floating-Point Operation
0
5-9
Floating-Point Formats
Rewrite the mantissa as:
Mantissa
1
0
.
1
0
1
0
0
0
0
0
0
0
0
Step 3: Shift the decimal point of the mantissa according to the value of the
exponent.
If the exponent is positive, shift the binary point to the right by the value
of the exponent. If the exponent is negative, shift the binary point to
the left.
For example, if e = 210 and the man = 01.110000000002, then the
shifted mantissa becomes 0111.0000000002, which is equivalent to
7 in decimal.
If, on the other hand, e = −210 and man = 01.100000000002, then the
shifted mantissa becomes 0.01100000000002, which is equivalent
to 3/8 in decimal.
The following examples illustrate how you can obtain the equivalent
floating-point value of a number in ‘C3x floating-point format. Each
of the examples uses the single-precision floating-point format.
Example 5−1. Positive Number
0
2
4
0
0
0
0
0
0000 0010 0100 0000 0000 0000 0000 0000
Exponent =
Sign
=
Fraction =
0000 00102 = 2
0
.100002
Value
01.12 × 22 = 01102. = 6
=
Fraction
Implied
Sign
5-10
Hex value
Binary value
Floating-Point Formats
Example 5−2. Negative Number
0
1
C
0
0
0
0
0
0000 0001 1100 0000 0000 0000 0000 0000
Exponent =
Sign
=
Fraction =
0000 00012 = 1
1
.100002
Value
10.12 × 21 = 1012. = −3
=
Hex value
Binary value
Fraction
Implied
Sign
Example 5−3. Fractional Number
F
B
4
0
0
0
0
0
1111 1011 0100 0000 0000 0000 0000 0000
Hex value
Binary value
Exponent =
Sign
=
Fraction =
1111 10112 = −5
0
.100002
Value
01.12 × 2−5 = .0000112 = 3/64
=
2−5
2−6
Fraction
Implied
Sign
Data Formats and Floating-Point Operation
5-11
Floating-Point Formats
5.3.6
Conversion Between Floating-Point Formats
Floating-point operations assume several different formats for inputs and outputs. These formats often require conversion from one floating-point format to
another (for example, short floating-point format to extended-precision floatingpoint format). Format conversions occur automatically in hardware, with no
overhead, as a part of the floating-point operations. Examples of the four conversions are shown in Figure 5−10 through Figure 5−13. When a floating-point
format 0 is converted to a greater-precision format, it is always converted to a
valid representation of 0 in that format. In Figure 5−10 through Figure 5−13,
s = sign bit of the exponent, y = short mantissa, and x = short exponent.
Figure 5−10. Converting from Short Floating-Point Format to Single-Precision
Floating-Point Format
15
s
12
x
x
x
11
10
0
y
y
y
Short floating-point format
31
27
24
s s s s s x x x
23
22
12
11
0
y
y
y
0
0
Single-precision floating-point format
In this format, the exponent field is sign extended, and the 12 LSBs of the mantissa
field are filled with 0s.
Figure 5−11. Converting from Short Floating-Point Format to Extended-Precision
Floating-Point Format
15
12
s
x
x
x
11
10
0
y
y
y
Short floating-point format
32
31
30
s s s s s x x x
y
y
39
35
20 19
y
0
0
0
Extended-precision floating-point format
The exponent field in this format is sign extended, and the 20 LSBs of the mantissa
field are filled with 0s.
5-12
Floating-Point Formats
Figure 5−12. Converting from Single-Precision Floating-Point Format
to Extended-Precision Floating-Point Format
31
x
24 23 22
0
x
y
y
y
Single-precision floating-point format
39
32 31 30
8
7
0
x
x
y
0
0
8
7
0
y
z
z
y
y
Extended-precision floating-point format
The 8 LSBs of the mantissa field are filled with 0s.
Figure 5−13. Converting from Extended-Precision Floating-Point Format
to Single-Precision Floating-Point Format
39
x
32 31 30
x
y
y
Extended-precision floating-point format
31
24 23 22
0
x
x
y
y
y
Single-precision floating-point format
The 8 LSBs of the mantissa field are truncated.
Data Formats and Floating-Point Operation
5-13
Floating-Point Conversion (IEEE Std. 754)
5.4 Floating-Point Conversion (IEEE Std. 754)
The ‘C3x floating-point format is not compatible with the IEEE standard 754
format. The IEEE floating-point format uses sign-magnitude notation for the
mantissa, and the exponent is biased by 127. In a 32-bit word representing a
floating-point number, the first bit is the sign bit. The next eight bits correspond
to the exponent, which is expressed in an offset-by-127 format (the actual exponent is e −127). The next 23 bits represent the absolute value of the mantissa
with the most significant 1 implied. The binary point follows this most significant
1. In other words, the mantissa actually has 24 bits (see Figure 5−14). There are
several special cases, summarized below.
These are the values of the represented numbers in the IEEE floating-point
format:
x = (−1)s x 2e−127 x (01.f)
if 0 < e < 255
Figure 5−14. IEEE Single-Precision Std. 754 Floating-Point Format
30
31
23
s
22
0
e
f
mantissa
The following five cases define the value v of a number expressed in the IEEE
format:
1)
If
e = 255
and f ≠ 0,
then
v = NaN
2)
If
e = 255
and f = 0,
then
v = (−1)s infinite
3)
If
0 < e < 255,
then
v = (−1)s × 2 e −127(1.f )
4)
If
e=0
and f ≠ 0,
then
v = (−1)s × 2−126(0.f )
5)
If
e=0
and f = 0,
then
v = (−1)s × 0
where:
s = sign bit
e = the exponent field
f = the fraction field
NaN = not a number
For the above five representations, e is treated as an unsigned integer. Case
1 generates NaN (not an number) and is primarily used for software signaling.
Case 4 represents a denormalized number. Case 5 represents positive and
negative 0.
5-14
Floating-Point Conversion (IEEE Std. 754)
Figure 5−15. TMS320C3x Single-Precision 2s-Complement Floating-Point Format
31
24
22
0
s
e
Note:
23
f
Same format as for the ’C4x
In comparison, Figure 5−15 shows the the ‘C3x 2s-complement floating-point
format. In this format, two cases can be used to define value v of a number:
1)
If
e = −128
then v = 0
2)
If
e ≠ −128
then v = ss.f2 2 e
where:
s = sign bit
e = the exponent field
f = the fraction field
For this representation, e is treated as a 2s-complement integer. The fraction
and sign bit form a normalized 2s-complement mantissa.
Note: Differentiating Symbols for IEEE and TMS320C3x Formats
To differentiate between the symbols that define these two formats, all IEEE
fields are subscripted with an IEEE (for example, eIEEE, sIEEE, and so forth).
Similarly, all 2s-complement fields are subscripted with 2 (that is, e2, s2, f2).
5.4.1
Converting IEEE Format to 2s-Complement TMS320C3x Floating-Point Format
The most common conversion is the IEEE-to-2s-complement format. This
conversion is done according to rules in Table 5−1.
Table 5−1. Converting IEEE Format to 2s-Complement Floating-Point Format
If these values are present
Description
Case
max neg 1
1
max pos 1
zero
eIEEE
sIEEE
fIEEE
255
1
2
255
3
Then these values equal
e2
s2
f2
any
7Fh
1
00 0000h
0
any
7Fh
0
7F FFFFh
0 < eIEEE < 255
0
fIEEE
eIEEE −7Fh
0
fIEEE
4
0 < eIEEE < 255
1
≠0
eIEEE −7Fh
1
f IEEE + 1†
5
0 < eIEEE <255
1
0
eIEEE −80h
1
0
6
0
any
any
80h
0
00 0000h
† f IEEE = 1s complement of fIEEE
Data Formats and Floating-Point Operation
5-15
Floating-Point Conversion (IEEE Std. 754)
Case 1 maps the IEEE positive NaNs and positive infinity to the single-precision 2s-complement most positive number. Overflow is also signaled to allow
you to check for these special cases.
Case 2 maps the IEEE negative NaNs and negative infinity to the singleprecision 2s-complement most negative number. Overflow is also signaled
to allow you to check for these special cases.
Case 3 maps the IEEE positive normalized numbers to the identical value in
the 2s-complement positive number.
Case 4 maps the IEEE negative normalized numbers with a nonzero fraction
to the identical value in the 2s-complement negative number.
Case 5 maps the IEEE negative normalized numbers with a 0 fraction to the
identical value in the 2s-complement negative number.
Case 6 maps the IEEE positive and negative denormalized numbers and positive
and negative 0s to a 2s-complement 0.
Based on these definitions of the formats, two versions of the conversion routines
were developed. One version handles the complete definition of the formats. The
other ignores some of the special cases (typically the ones that are rarely used),
but it has the benefit of executing faster than the complete conversion. For this
discussion, the two versions are referred to as the complete version and the fast
version, respectively.
5-16
Floating-Point Conversion (IEEE Std. 754)
5.4.1.1
IEEE-to-TMS320C3x Floating-Point Format Conversion
Example 5−4 shows the fast conversion from IEEE to ’C3x floating-point format.
It properly handles the general case when 0 < e < 255, and also handles 0s (that
is, e = 0 and f = 0). The other special cases (denormalized, infinity, and NaN)
are not treated and, if present, will give erroneous results.
The fast version of the IEEE-to ’C3x conversion routine was originally developed
by Keith Henry of Apollo Computer, Inc. The other routines were based on this
initial input.
Example 5−4. IEEE-to-TMS320C3x Conversion (Fast Version)
*
*
*
*
*
*
*
*
*
*
*
*
TITLE IEEE TO TMS320C3x CONVERSION (FAST VERSION)
SUBROUTINE FMIEEE
FUNCTION: CONVERSION BETWEEN THE IEEE FORMAT AND THE
TMS320C3x FLOATING-POINT FORMAT. THE NUMBER TO
BE CONVERTED IS IN THE LOWER 32 BITS OF R0.
THE RESULT IS STORED IN THE UPPER 32 BITS OF R0.
UPON ENTERING THE ROUTINE, AR1 POINTS TO THE
FOLLOWING TABLE:
*
*
*
*
*
*
(0) 0xFF800000 <−− AR1
(1) 0xFF000000
(2) 0x7F000000
(3) 0x80000000
(4) 0x81000000
*
ARGUMENT
ASSIGNMENTS:
*
ARGUMENT
|
*
−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
*
*
R0
AR1
*
*
*
*
REGISTERS USED AS INPUT: R0, AR1
REGISTERS MODIFIED: R0, R1
REGISTER CONTAINING RESULT: R0
|
|
FUNCTION
NUMBER TO BE CONVERTED
POINTER TO TABLE WITH CONSTANTS
Data Formats and Floating-Point Operation
5-17
Floating-Point Conversion (IEEE Std. 754)
Example 5−4.IEEE-to-TMS320C3x Conversion (Fast Version) (Continued)
*
*
*
*
NOTE: SINCE THE STACK POINTER SP IS USED, MAKE SURE TO
INITIALIZE IT IN THE CALLING PROGRAM.
*
*
CYCLES: 12 (WORST CASE) WORDS: 12
.global FMIEEE
*
FMIEEE
*
NEG
AND3
BND
ADDI
R0,*AR1,R1
NEG
R0,R1
LDIZ
SUBI
PUSH
POPF
RETS
*+AR1(1),R1
*+AR1(2),R1
R1
R0
PUSH
POPF
NEGF
RETS
R1
R0
R0,R0
;
;
;
;
;
;
Replace fraction with 0
Test sign
Shift sign
and exponent inserting 0
If all 0, generate C30 0
Unbias exponent
; Load this as a flt. pt. number
; Load this as a flt. pt. number
; Negate if orig. sign is negative
Example 5−5 shows the complete conversion between IEEE and ’C3x formats.
In addition to the general case and the 0s, it handles the special cases as follows:
- If NaN (e = 255, f < > 0), the number is returned intact.
- If infinity (e = 255, f = 0), the output is saturated to the most positive or nega-
tive number, respectively.
- If denormalized (e = 0, f< >0), two cases are considered. If the MSB of f is
1, the number is converted to ’C3x format. Otherwise an underflow occurs,
and the number is set to 0.
5-18
Floating-Point Conversion (IEEE Std. 754)
Example 5−5. IEEE-to-TMS320C3x Conversion (Complete Version)
*
*
*
*
*
TITLE IEEE TO TMS320C3x CONVERSION (COMPLETE VERSION)
*
*
*
*
*
*
*
*
FUNCTION: CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x
FLOATING-POINT FORMAT. THE NUMBER TO BE CONVERTED
IS IN THE LOWER 32 BITS OF R0. THE RESULT IS STORED
IN THE UPPER 32 BITS OF R0.
*
*
*
*
*
*
*
*
*
*
(0) 0xFF800000 <−− AR1
(1) 0xFF000000
(2) 0x7F000000
(3) 0x80000000
(4) 0x81000000
(5) 0x7F800000
(6) 0x00400000
(7) 0x007FFFFF
(8) 0x7F7FFFFF
*
ARGUMENT
*
*
*
*
*
ARGUMENT | FUNCTION
−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
R0
| NUMBER TO BE CONVERTED
AR1
| POINTER TO TABLE WITH CONSTANTS
*
*
*
*
REGISTERS USED AS INPUT: R0, AR1
REGISTERS MODIFIED: R0, R1
REGISTER CONTAINING RESULT: R0
*
*
*
*
*
*
NOTE: SINCE THE STACK POINTER SP IS USED, MAKE SURE TO
INITIALIZE IT IN THE CALLING PROGRAM.
SUBROUTINE FMIEEE1
UPON ENTERING THE ROUTINE, AR1 POINTS TO THE FOLLOWING TABLE:
ASSIGNMENTS:
CYCLES: 23 (WORST CASE)
.global
FMIEEE1
*
FMIEEE1
LDI
R0,R1
AND
*+AR1(5),R1
BZ
UNNORM
*
XOR
*+AR1(5),R1
BNZ
NORMAL
WORDS: 34
;
;
If e = 0, number is either 0 or
denormalized
;
If e < 255, use regular routine
Data Formats and Floating-Point Operation
5-19
Floating-Point Conversion (IEEE Std. 754)
Example 5−5.IEEE-to-TMS320C3x Conversion (Complete Version) (Continued)
*
HANDLE NaN AND INFINITY
TSTB
*+AR1(7),R0
RETSNZ
LDI
R0,R0
*
Return if NaN
LDFGT
*+AR1(8),R0
;
;
If positive, infinity =
most positive number
LDFN
RETS
*+AR1(5),R0
;
;
If negative, infinity =
most negative number RETS
HANDLE 0s AND UNNORMALIZED NUMBERS
UNNORM
NEG1
TSTB
LDFZ
RETSZ
*+AR1(6),R0
*+AR1(3),R0
;
;
;
Is the MSB of f equal to 1?
If not, force the number to 0
and return
XOR
BND
LSH
*+AR1(6),R0
NEG1
1,R0
;
If MSB of f = 1, make it 0
SUBI
PUSH
POPF
RETS
POPF
NEGF
RETS
*+AR1(2),R0
R0
R0
;
;
;
Eliminate sign bit
& line up mantissa
Make e = −127
;
Put number in floating point format
;
If negative, negate R0
;
;
;
;
Replace fraction with 0
Test sign
Shift sign and exponent inserting 0
Unbias exponent
;
Load this as a flt. pt. number
;
;
Load this as a flt. pt. number
Negate if original sign negative
R0
R0,R0
*
HANDLE THE REGULAR CASES
*
NORMAL
AND3
R0,*AR1,R1
BND
NEG
ADDI
R0,R1
SUBI
*+AR1(2),R1
PUSH
R1
POPF
R0
RETS
NEG
5-20
;
POPF
NEGF
RETS
R0
R0,R0
Floating-Point Conversion (IEEE Std. 754)
5.4.2
Converting 2s-Complement TMS320C3x Floating-Point Format to IEEE Format
This conversion is performed according to the following table:
Table 5−2. Converting 2s-Complement Floating-Point Format to IEEE Format
If these values are present
Case
†
e2
s2
Then these values equal
f2
eIEEE
sIEEE
fIEEE
1
−128
00h
0
00 0000h
2
−127
00h
0
00 0000h
3
−126≤ e2 ≤127
0
e2 +7Fh
0
f2
4
−126≤ e2 ≤127
1
≠0
e2 +7Fh
0
f 2 +1†
5
−126≤ e2 ≤127
1
0
e2 +80h
1
00 0000h
6
127
1
0
FFh
1
00 0000h
f2 = 2s-complement of f2 .
Case 1 maps a 2s-complement 0 to a positive IEEE 0.
Case 2 maps the 2s-complement numbers that are too small to be represented as normalized IEEE numbers to a positive IEEE 0.
Case 3 maps the positive 2s-complement numbers that are not covered by
case 2 into the identically valued IEEE number.
Case 4 maps the negative 2s-complement numbers with a nonzero fraction
that are not covered in case 2 into the identically valued IEEE number.
Case 5 maps all the negative 2s-complement numbers with a 0 fraction, except
for the most negative 2s-complement number and those that are not covered
in case 2, into the identically valued IEEE number.
Case 6 maps the most negative 2s-complement number to the IEEE negative
infinity.
Data Formats and Floating-Point Operation
5-21
Floating-Point Conversion (IEEE Std. 754)
5.4.2.1
TMS320C3x-to-IEEE Floating-Point Format Conversion
The vast majority of the numbers represented by the ’C3x floating-point format
are covered by the general IEEE format and the representation of 0s. The only
special case is e = −127 in the ’C3x format; this corresponds to a denormalized
number in IEEE format. It is ignored in the fast version, while it is treated properly
in the complete version. Example 5−6 shows the fast version, and Example 5−7
shows the complete version of the ’C3x-to-IEEE conversion.
Example 5−6. TMS320C3x-to-IEEE Conversion (Fast Version)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
5-22
TITLE TMS320C3x TO IEEE CONVERSION (FAST VERSION)
SUBROUTINE TOIEEE
FUNCTION: CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE
FLOATING-POINT FORMAT. THE NUMBER TO BE CONVERTED
IS IN THE UPPER 32 BITS OF R0. THE RESULT WILL BE IN
THE LOWER 32 BITS OF R0.
UPON ENTERING THE ROUTINE, AR1 POINTS TO THE FOLLOWING TABLE:
(0) 0xFF800000 <−− AR1
(1) 0xFF000000
(2) 0x7F000000
(3) 0x80000000
(4) 0x81000000
*
ARGUMENT
ASSIGNMENTS:
*
ARGUMENT
|
*
−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
*
*
R0
AR1
*
*
*
*
REGISTERS USED AS INPUT: R0, AR1
REGISTERS MODIFIED: R0
REGISTER CONTAINING RESULT: R0
*
*
*
*
NOTE: SINCE THE STACK POINTER ‘SP’ IS USED, MAKE SURE TO
INITIALIZE IT IN THE CALLING PROGRAM.
|
|
FUNCTION
NUMBER TO BE CONVERTED
POINTER TO TABLE WITH CONSTANTS
Floating-Point Conversion (IEEE Std. 754)
Example 5−6.TMS320C3x-to-IEEE Conversion (Fast Version) (Continued)
*
*
CYCLES: 14 (WORST CASE)
.global
*
TOIEEE
NEG
WORDS: 15
TOIEEE
LDF
LDFZ
BND
ABSF
LSH
PUSHF
POP
ADDI
LSH
RETS
R0,R0
*+AR1(4),R0
NEG
R0
1,R0
R0
R0
*+AR1(2),R0
−1,R0
;
;
;
;
;
Determine the sign of the number
If 0, load appropriate number
Branch to NEG if negative (delayed)
Take the absolute value of the number
Eliminate the sign bit in R0
;
;
;
Place number in lower 32 bits of R0
Add exponent bias (127)
Add the positive sign
POP
R0
ADDI
LSH
ADDI
RETS
*+AR1(2),R0
−1,R0
*+AR1(3),R0
;
;
;
;
;
Place number in lower 32 bits
of R0
Add exponent bias (127)
Make space for the sign
Add the negative sign
Data Formats and Floating-Point Operation
5-23
Floating-Point Conversion (IEEE Std. 754)
Example 5−7. TMS320C3x-to-IEEE Conversion (Complete Version)
*
*
*
*
*
*
*
*
*
*
*
*
*
TITLE TMS320C3x TO IEEE CONVERSION (COMPLETE VERSION)
SUBROUTINE TOIEEE1
FUNCTION: CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE
FLOATING-POINT FORMAT. THE NUMBER TO BE CONVERTED
IS IN THE UPPER 32 BITS OF R0. THE RESULT WILL BE
IN THE LOWER 32 BITS OF R0.
*
*
UPON ENTERING THE ROUTINE, AR1 POINTS TO THE FOLLOWING TABLE:
*
*
(0) 0xFF800000 <−− AR1
(1) 0xFF000000
(2) 0x7F000000
(3) 0x80000000
(4) 0x81000000
(5) 0x7F800000
(6) 0x00400000
(7) 0x007FFFFF
(8) 0x7F7FFFFF
*
*
*
*
*
*
*
*
ARGUMENT
*
*
*
*
*
ARGUMENT | FUNCTION
−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
R0
| NUMBER TO BE CONVERTED
AR1
| POINTER TO TABLE WITH CONSTANTS
*
*
*
*
REGISTERS USED AS INPUT: R0, AR1
REGISTERS MODIFIED: R0
REGISTER CONTAINING RESULT: R0
*
*
*
*
NOTE: SINCE THE STACK POINTER ’SP’ IS USED, MAKE SURE TO
INITIALIZE IT IN THE CALLING PROGRAM.
*
*
CYCLES: 31 (WORST CASE)
.global
5-24
ASSIGNMENTS:
TOIEEE1
WORDS: 25
Floating-Point Conversion (IEEE Std. 754)
Example 5−7.TMS320C3x-to-IEEE Conversion (Complete Version) (Continued)
*
TOIEEE1
CONT
NEG
LDF
LDFZ
BND
ABSF
R0,R0
*+AR1(4),R0
NEG
R0
LSH
PUSHF
POP
ADDI
LSH
1,R0
R0
R0
*+AR1(2),R0
−1,R0
TSTB
RETSNZ
TSTB
RETSZ
PUSH
POPF
LSH
PUSHF
POP
ADDI
RETS
*+AR1(5),R0
POP
BRD
ADDI
LSH
ADDI
RETS
;
;
;
;
;
;
Determine the sign of the number
If 0, load appropriate number
Branch to NEG if negative (delayed)
Take the absolute value
of the number
Eliminate the sign bit in R0
;
;
;
Place number in lower 32 bits of R0
Add exponent bias (127)
Add the positive sign
;
If e > 0, return
;
If e = 0 & f = 0, return
;
Shift f right by one bit
;
Add 1 to the MSB of f
;
Place number in lower 32 bits of R0
;
;
;
Add exponent bias (127)
Make space for the sign
Add the negative sign
*+AR1(7),R0
R0
R0
−1,R0
R0
R0
*+AR1(6),R0
R0
CONT
*+ARI(2),R0
−1,R0
*+AR1(3),R0
Data Formats and Floating-Point Operation
5-25
Floating-Point Multiplication
5.5 Floating-Point Multiplication
A floating-point number α can be written in floating-point format as in the following
formula, where α(man) is the mantissa and α(exp) is the exponent:
α = α(man) × 2α(exp)
The product of α and b is c, defined as:
c = α × b = α(man) × b(man) × 2(α(exp) + b (exp))
thus:
c(man) = α(man) × b(man)
c(exp) = α(exp) + b(exp)
During floating-point multiplication, source operands are in the single-precision
floating-point format. If the source operands are in short floating-point format,
they are converted to single-precision floating-point format. If the source operands are in extended-precision floating-point format, they are truncated to
single-precision format. These conversions occur automatically in hardware
with no overhead. All results of floating-point multiplications are in the extendedprecision format. These multiplications occur in a single cycle.
Figure 5−16 is a flowchart that shows the steps involved in floating-point multiplication. Each step is labelled with a number in parenthesis.
- In step 1, the 24-bit source operand mantissas are multiplied, producing
a 50-bit result c(man). (Input and output data are always represented as
normalized numbers.)
- In step 2, the exponents, α(exp) and b(exp), are added, yielding c(exp).
- Step 3 checks for whether c(man) in extended-precision format is equal to
0. If c(man) is 0, step 7 sets c(exp) to −128, thus yielding the representation
for 0.
- Steps 4 and 5 normalize the result.
- If a right shift of 1 is necessary, then in step 8, c(man) is right-shifted one
bit, thus adding 1 to c(exp).
- If a right shift of 2 is necessary, then in step 9, c(man) is right-shifted two
bits, thus adding 2 to c(exp). Step 6 occurs when the result is normalized.
- In step 10, c(man) is set in the extended-precision floating-point format.
- Steps 11 through 16 check for special cases of c(exp).
5-26
Floating-Point Multiplication
- If c(exp) has overflowed (step 11) in the positive direction, then step 14
sets c(exp) to the most positive extended-precision format value. If c(exp)
has overflowed in the negative direction, then step 14 sets c(exp) to the
most negative extended-precision format value.
- If c(exp) has underflowed (step 12), then step 15 sets c to 0; that is,
c(man) = 0 and c(exp) = −128.
Data Formats and Floating-Point Operation
5-27
Floating-Point Multiplication
Figure 5−16. Flowchart for Floating-Point Multiplication
α(man)
α(exp)
b(man)
b(exp)
(1)
(2)
Multiply mantissas
Add exponents
c(man) = α(man) x b(man)
(50-bit result)
c(exp) = α(exp) + b(exp)
Test for special cases of c(man)
(3)
c(man) = 0
(4)
Right shift 1
to normalize
(7)
c(exp) =− 128
(5)
Right shift 2
to normalize
(8)
(6)
No shift
to normalize
(9)
c(man) > > 1
and
c(exp) = c(exp) + 1
c(man) > > 2
and
c(exp) = c(exp) + 2
Dispose of extra bits
(10)
Put c(man) in extended precision floating-point format
Test for special cases of c(exp)
(11)
c(exp) overflow
(14)
If c(man) > 0,
set c(exp) to most
positive value
(12)
c(exp) underflow
c(exp) = −128
(13)
c(exp) in range
(15)
c(man) = 0
If c(man) < 0,
set c(exp) to most
negative value
Set c to final result
c=αxb
5-28
(16)
Floating-Point Multiplication
Example 5−8 through Example 5−12 illustrate how floating-point multiplication
is performed on the ’C3x. For these examples, the implied most significant
nonsign bit is made explicit.
Example 5−8. Floating-Point Multiply (Both Mantissas = −2.0)
Let:
α = −2.0 × 2α(exp) = 10.00000000000000000000000 × 2α(exp)
b = −2.0 × 2 b(exp) = 10.00000000000000000000000 × 2 b(exp)
Where:
α and b are both represented in binary form according to the normalized
single-precision floating-point format.
Then:
10.00000000000000000000000 × 2α(exp)
× 10.00000000000000000000000 × 2 b(exp)
0100.000000000000000000000000000000000000000000000 × 2 (α(exp) + b(exp))
To place this number in the proper normalized format, it is necessary to shift
the mantissa two places to the right and add 2 to the exponent. This yields:
10.00000000000000000000000 × 2α(exp)
× 10.00000000000000000000000 × 2 b(exp)
0100.0000000000000000000000000000000000000000000000 × 2 (α(exp) + b(exp))
In floating-point multiplication, the exponent of the result may overflow. This can
occur when the exponents are initially added or when the exponent is modified
during normalization.
Data Formats and Floating-Point Operation
5-29
Floating-Point Multiplication
Example 5−9. Floating-Point Multiply (Both Mantissas = 1.5)
Let:
α = 1.5 × 2α(exp) = 01.0000000000000000000000 × 2α(exp)
b = 1.5 × 2 b(exp) = 01.0000000000000000000000 × 2 b(exp)
Where:
a and b are both represented in binary form according to the single-precision floating-point format.
Then:
10.00000000000000000000000 × 2α(exp)
x 10.00000000000000000000000 × 2 b(exp)
01.0000000000000000000000000000000000000000000000 × 2 (α(exp) + b(exp) + 2)
To place this number in the proper normalized format, it is necessary to shift
the mantissa one place to the right and add 1 to the exponent. This yields:
01.0000000000000000000000 × 2α(exp)
× 01.0000000000000000000000 × 2 b(exp)
01. 00100000000000000000000000000000000000000000000 × 2 (α(exp) + b(exp) + 1)
Example 5−10. Floating-Point Multiply (Both Mantissas = 1.0)
Let:
α = 1.0 × 2α(exp) = 01.00000000000000000000000 × 2α(exp)
b = 1.0 × 2 b(exp) = 01.00000000000000000000000 × 2 b(exp)
Where:
a and b are both represented in binary form according to the single-precision floating-point format.
Then:
01.00000000000000000000000 × 2α(exp)
× 01.00000000000000000000000 × 2 b(exp)
0001.0000000000000000000000000000000000000000000000 y 2 (a(exp) + b(exp))
This number is in the proper normalized format. Therefore, no shift of the
mantissa or modification of the exponent is necessary.
The previous examples show cases where the product of two normalized
numbers can be normalized with a shift of 0, 1, or 2. The floating-point format
of the ‘C3x makes this possible.
5-30
Floating-Point Multiplication
Example 5−11. Floating-Point Multiply Between Positive and Negative Numbers
Let:
α = 1.0 x 2α(exp) = 01.00000000000000000000000 x 2α(exp)
b = −2.0 x 2 b(exp) = 10.00000000000000000000000 x 2 b(exp)
Then:
01.00000000000000000000000 × 2α(exp)
x 10.00000000000000000000000 × 2 b(exp)
1110.0000000000000000000000000000000000000000000000 × 2 (α(exp) + b(exp))
The result is:
c = −2.0 x 2(α(exp) + b(exp))
Example 5−12. Floating-Point Multiply by 0
All multiplications by a floating-point 0 yield a result of 0 (f = 0, s = 0, and
exp = −128).
Data Formats and Floating-Point Operation
5-31
Floating-Point Addition and Subtraction
5.6 Floating-Point Addition and Subtraction
In floating-point addition and subtraction, two floating-point numbers α and b
can be defined as:
α = α(man) × 2 α(exp)
b = b(man) × 2 b(exp)
The sum (or difference) of α and b can be defined as:
c = α±b
= (α(man) ± (b(man) × 2 −(α(exp) − b(exp))) × 2 α(exp), if α(exp) ≥ b(exp)
= (α(man) × 2 −(b(exp) −α(exp))) ± b(man)) × 2 b(exp), if α(exp) < b(exp)
Figure 5−17 shows the flowchart for floating-point addition. Because this flowchart assumes signed data, it is also appropriate for floating-point subtraction.
In this figure, it is assumed that α(exp) ≤ b(exp).
- In step 1, the source exponents, α(exp) and b(exp), are compared, and
c(exp) is set equal to the largest of the two source exponents.
- In step 2, d is set to the difference of the two exponents.
- In step 3, the mantissa with the smallest exponent, in this case α(man),
is right-shifted d bits to align the mantissas.
- In step 4, after the mantissas have been aligned, they are added.
- In steps 5 through 7, a check for a special case of c(man). If c(man) is 0
(step 5), then c(exp) is set to its most negative value (step 8) to yield the
correct representation of 0. If c(man) has overflowed c (step 6), then in
step 9 c(man) is right-shifted one bit and 1 is added to c(exp). In step 10,
the result is normalized.
- Steps 11 through 13 check for special cases of c(exp). If c(exp) has over-
flowed (step 11) in the positive direction, then step 14 sets c(exp) to the
most positive extended-precision format value. If c(exp) has overflowed
(step 11) in the negative direction, then step 14 sets c(exp) to the most
negative extended-precision format value. If c(exp) has underflowed (step
12), then step 15 sets c to 0; that is, c(man) = 0 and c(exp) = −128. If no
overflow or underflow occurred, then c is not modified.
5-32
Floating-Point Addition and Subtraction
Figure 5−17. Flowchart for Floating-Point Addition
α(man)
α(exp)
b(man)
b(exp)
(1)
Compare exponents
If α(exp) < = b(exp)
c(exp) = b(exp)
else
c(exp) = α(exp)
(Assume for simplicity
that α(exp) < = b(exp))
(3)
Align mantissas
α(man) = α(man) > > d
Discard LSBs to keep
α(man) in extendedprecision floatingpoint format
(2)
Subtract exponents
d = b(exp) − α(exp)
Add mantissas
(4)
c (man) = α(man) + b(man)
Test for special cases of c(man)
(6)
(5)
c(man) = 0
Overflow of c(man)
(7)
k = # of leading
non-significant
sign bits
(9)
c(man) = c(man) > > 1
c(exp) = c(exp) + 1
Discard LSBs to keep in
extended-precision
floating-point format
(8)
(10)
c(man) < < k
c(exp) = c(exp) − k
c(exp) = −128
Test for special cases of c(exp)
(14)
(11)
c(exp) overflow
(12)
c(exp) underflow
If c(man) > 0,
set c to most
positive value
set c to 0
c(exp) = −128
(13)
c(exp) in range
(15)
c(man) = 0
If c(man) < 0,
set c to most
negative value
(16)
Set c to final result
c=α+b
Data Formats and Floating-Point Operation
5-33
Floating-Point Addition and Subtraction
The following examples describe the floating-point addition and subtraction
operations. It is assumed that the data is in the extended-precision floatingpoint format.
Example 5−13. Floating-Point Addition
In the case of two normalized numbers to be summed, let
α = 1.5 = 01.1000000000000000000000000000000 × 20
b = 0.5 = 01.0000000000000000000000000000000 × 2 −1
It is necessary to shift b to the right by 1 so that α and b have the same exponent.
This yields:
b = 0.5 = 00.1000000000000000000000000000000 × 20
Then:
01.10000000000000000000000000000000 × 2
+00.10000000000000000000000000000000 × 20
010.00000000000000000000000000000000 × 20
As in the case of multiplication, it is necessary to shift the binary point one place
to the left and add 1 to the exponent. This yields:
01.1000000000000000000000000000000 × 20
± 00.1000000000000000000000000000000 × 20
01.0000000000000000000000000000000 × 21
5-34
Floating-Point Addition and Subtraction
Example 5−14. Floating-Point Subtraction
A subtraction is performed in this example. Let:
α = 01.0000000000000000000000000000001 × 20
b = 01.0000000000000000000000000000000 × 20
The operation performed is α −b. The mantissas are already aligned because
the two numbers have the same exponent. The result is a large cancellation
of the upper bits, as shown below.
01.0000000000000000000000000000001 × 20
−01.0000000000000000000000000000000 × 20
00.0000000000000000000000000000001 × 20
The result must be normalized. In this case, a left shift of 31 is required. The
exponent of the result is modified accordingly. The result is:
01.0000000000000000000000000000001 × 20
− 01.0000000000000000000000000000000 × 20
01.0000000000000000000000000000000 × 2 −31
Example 5−15. Floating-Point Addition With a 32-Bit Shift
This example illustrates a situation where a full 32-bit shift is necessary to
normalize the result. Let:
α = 01.1111111111111111111111111111111 × 2127
b = 10.0000000000000000000000000000000 × 2127
The operation to be performed is α + b.
01.1111111111111111111111111111111 × 2127
+ 10.0000000000000000000000000000000 × 2127
11.1111111111111111111111111111111 × 2127
Normalizing the result requires a left shift of 32 and a subtraction of 32 from
the exponent. The result is:
01.1111111111111111111111111111111 × 2127
+ 10.0000000000000000000000000000000 × 2127
11.1111111111111111111111111111111 × 2127
Data Formats and Floating-Point Operation
5-35
Floating-Point Addition and Subtraction
Example 5−16. Floating-Point Addition/Subtraction With Floating-Point 0
When floating-point addition and subtraction are performed with a floatingpoint 0, the following identities are satisfied:
α ± 0 = α (α ≠ 0)
0 ±0 = 0
0 − α = −α (α ≠ 0)
5-36
Normalization Using the NORM Instruction
5.7 Normalization Using the NORM Instruction
The NORM instruction normalizes an extended-precision floating-point number
that is assumed to be unnormalized (see Example 5−17). Since the number is
assumed to be unnormalized, no implied most significant nonsign bit is assumed.
The NORM instruction:
1) Locates the most significant nonsign bit of the floating-point number
2) Left shifts to normalize the number
3) Adjusts the exponent
Example 5−17. NORM Instruction
Assume that an extended-precision register contains the value:
man = 00000000000000000001000000000001, exp = 0
When the normalization is performed on a number assumed to be unnormalized,
the binary point is assumed to be:
man = 0.0000000000000000001000000000001, exp = 0
This number is then sign-extended one bit so that the mantissa contains 33 bits:
man = 00.0000000000000000001000000000001, exp = 0
The intermediate result after the most significant nonsign bit is located and the
shift performed is:
man = 01.0000000000010000000000000000000, exp = −19
The final 32-bit value output after removing the redundant bit is:
man = 00000000000010000000000000000000, exp = −19
The NORM instruction is useful for counting the number of leading 0s or leading
1s in a 32-bit field. If the exponent is initially 0, the absolute value of the final
value of the exponent is the number of leading 1s or 0s. This instruction is also
useful for manipulating unnormalized floating-point numbers.
Given the extended-precision floating-point value a to be normalized, the
normalization, norm ( ), is performed as shown in Figure 5−18.
Data Formats and Floating-Point Operation
5-37
Normalization Using the NORM Instruction
Figure 5−18. Flowchart for NORM Instruction Operation
α
Test for special cases of c (man)
(1)
α ( man) = 0
(2)
Leading nonsignificant sign bits
k = # of leading
nonsignificant
sign bits
(3)
c(exp) = −128
(4)
Sign-extended α(man) 1 bit
c (man) = α(man) < < k
c (exp) = α(exp) − k
Remove most significant nonsign bit
Test for special cases of c (exp)
(6)
c (exp)
underflow
(8)
(9)
c (exp) = −128
No change to c (man)
Set c to final result
c = norm(α)
5-38
(7)
c (exp) in
range
(5)
Rounding (RND Instruction)
5.8 Rounding (RND Instruction)
The RND instruction rounds a number from the extended-precision floatingpoint format to the single-precision floating-point format. Rounding is similar to
floating-point addition. Given the number a to be rounded, the following operation is performed first.
c = α(man) × 2α(exp) + (1 × 2α(exp) −24)
Next, a conversion from extended-precision floating-point to single-precision
floating-point format is performed. Given the extended-precision floating-point
value, the rounding, rnd( ), is performed as shown in Figure 5−19.
Note:
RND, src, dst—where (src) = 0—does not set the 0 conditions flag (bit 2 in
the status register). Instead, it sets the underflow condition flag (bit 4 in the
status register). When required, check for the underflow condition instead of
the 0 condition.
Data Formats and Floating-Point Operation
5-39
Rounding (RND Instruction)
Figure 5−19. Flowchart for Floating-Point Rounding by the RND Instruction
α
1×2
α(exp) − 24
Add α(man) and 1/2 of LSB
c ( man) = α ( man) + 2− 24
Test for special cases of c(man)
c (man) = 0
Overflow of c (man)
c (exp) = −128
c (man) = c (man) < < 1
c (exp) = α (exp) + 1
No special case
Test for special cases of c (exp)
c (exp) overflow
c (exp) in range
If c (man) > 0,
set c to most positive
single-precision value
If c (man) < 0,
set c to most negative
single-precision value
Set eight LSBs of c(man) to 0
c = rnd(α)
5-40
Floating-Point to Integer Conversion (FIX Instruction)
5.9 Floating-Point to Integer Conversion (FIX Instruction)
Using the FIX instruction, you can convert an extended-precision floatingpoint number to a single-precision integer in a single cycle. The floating-point
to integer conversion of the value x is referred to here as fix(x). The conversion
does not overflow if a, the number to be converted, is in the range:
−231 ≤ α ≤ 231 − 1
First, you must be certain that
α(exp) ≤ 30
If these bounds are not met, an overflow occurs. If an overflow occurs in the
positive direction, the output is the most positive integer. If an overflow occurs
in the negative direction, the output is the most negative integer. If α(exp) is
within the valid range, then α(man), with implied bit included, is sign-extended
and right-shifted (rs) by the amount
rs = 31 − α(exp)
This right shift (rs) shifts out those bits corresponding to the fractional part of
the mantissa. For example:
If 0 ≤ × < 1, then fix(x) = 0
If −1 ≤ × < 0, then fix(x) = −1
Figure 5−20 shows the flowchart for the floating-point-to-integer conversion.
Data Formats and Floating-Point Operation
5-41
Floating-Point to Integer Conversion (FIX Instruction)
Figure 5−20. Flowchart for Floating-Point to Integer Conversion by FIX Instruction
α
Test for special cases of α(exp)
α(exp) > 30
α(exp) in range
rs = 31 − α(exp)
Overflow
Shift
If α(man) > 0,
c = most positive integer
c = α(man) > > rs
If α(man) < 0,
c = most negative integer
Set c to final result
c = fix(α)
5-42
Integer to Floating-Point Conversion (FLOAT Instruction)
5.10 Integer to Floating-Point Conversion (FLOAT Instruction)
Integer to floating-point conversion, using the FLOAT instruction, allows
single-precision integers to be converted to extended-precision floating-point
numbers. The flowchart for this conversion is shown in Figure 5−21.
Figure 5−21. Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction
α
c (man) = α
c (exp) = 30
Test for special cases of c (man)
Leading nonsignificant
sign bits
c (man) = 0
k = # leading
nonsignificant
sign bits
c (exp) = −128
c (man) = c (man) < < k
c (exp) = 30 − k
Remove most significant nonsign bit
Set c to final result
c = float (α)
Data Formats and Floating-Point Operation
5-43
Fast Logarithms on a Floating-Point Device
5.11 Fast Logarithms on a Floating-Point Device
The following TMS320C30/C40 function calculates the log base two of a number
in about half the time of conventional algorithms. Furthermore, the method can
easily be scaled for faster execution if less accuracy is desired. The method is
efficient because the algorithm uses the floating-point multipliers’ exponent/normalization hardware in a unique way. The following is a proof of the algorithm.
The value of a floating point number X is given by:
X = 2^EXP_old * mant_old
Since the bit fields used to store the exponent and mantissa are actually integer, the exponent is already in log2 (log base 2) form. In fact, the exponent is
nothing more than a normalizing shift value. By converting both sides of the
first equation to a logarithm, the logarithm of the value becomes the sum of the
exponent and mantissa in log form:
log2(X) = EXP_old + log2(mant_old) (Log base two)
Since EXP is in the exponent register, no calculation is needed and the value
can be used directly as an integer. To extract the value of the exponent, PUSH,
POP, and masking operations are used. The remaining mantissa conversion
is done by first forcing the exponent bits to zero using an LDE 1.0 instruction.
This causes the exponent term 2^EXP to equal 1.0, leaving 1.0 <= Value < 2.0.
Then, by using the following identity, the logarithm of the mantissa can be extracted from the final results exponent. If the value (mant_old) is repeatedly
squared, the sequence becomes:
X_new = mant_old^N
where:
1.0 X_new < 2^N
N = 1,2,4,8,16...
Since the hardware multiplier restructures the new value (X_new) during each
squaring operation, X_new is represented by a new exponent (EXP_new) and
mantissa (mant_new):
X_new = 2^EXP_New * mant_new
By then applying familiar logarithm rules, we find that EXP_new holds the logarithm of Old_mant. This is best shown by setting the previous two equations
equal to each other and taking the logarithm of both sides:
mant_old^N = 2^EXP_new * mant_new
N=1,2,4,8,16...
5-44
Fast Logarithms on a Floating-Point Device
N * log2(mant_old) = EXP_new + log2(mant_new)
log2(mant_old) = EXP_new/N + log2(mant_new)/N
This last equation shows that the logarithm of mant_old is indeed related to
EXP_new. And as shown earlier, EXP_new can be separated from the new
mantissa and used as the logarithm of the original mantissa.
We also need to consider the divisor N, which is defined to be the series 1, 2,
4, 8, 16... , and EXP_new is an integer. The division by N becomes a shift for
each squaring operation. What remains is to concatenate the bits of EXP_new
to EXP_old and then repeat the process until the desired accuracy is achieved.
5.11.1 Example of Fast Logarithm on a Floating-Point Device
Consider a mantissa value of 1.5 and an exponent value of 0 (giving an exponent multiplier 2^0, or 1.0). The TMS320C30/C40 extended register bit pattern
for the algorithm sequence is shown below.
Table 5−3. Squaring Operation of F0 = 1.5
Squaring Operation of F0 = 1.5
Exp
S
Mantissa
00000000
0
1000000000000000000000000000000
X
=1.5
Exp=0
00000001
0
0010000000000000000000000000000
X^2
=2.25
Exp=1
00000010
0
0100010000000000000000000000000
X^4
=5.0625
Exp=2
00000100
0
1001101000010000000000000000000
X^8
=25.628906
Exp=4
00100100
0
0100100001101011101000001000000
X^16
=656.84083
Exp=9
00010010
0
1010010101010011111101110011111
X^32
=431.43988−E3
Exp=18
00100101
0
0101101010110110101000010101001
X^64
=186.14037−E9
Exp=37
01001010
0
1101010110010010001010101100011
X^128
=34.648238−E21
Exp=74
XXXXXXXX
S
MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Exp
S
Mantissa
Hand-calculated value of log2(1.5)
log2(1.5) = 0.58496250 = 1001010 111000000
xxxxxxx− first 7 bits (exponent)
mmm− quick 3 bits (mantissa)
If you compare the hand-calculated value and the binary representation of
log2(1.5), you find that the sequence of bits in the exponent (seven bits worth)
Data Formats and Floating-Point Operation
5-45
Fast Logarithms on a Floating-Point Device
are equivalent to the seven MSBs of the logarithm. If the exponent could hold
all the bits needed for full accuracy, then it would be possible to continue the operation for all 24 bits of the mantissa. Since there are only eight bits in the exponent and the MSBs are used for negative values, only seven iterations are possible before the exponent must be off-loaded and reinitialized to zero.
By concatenating EXP_new to the previous exponent, longer strings of bits can
be built for greater accuracy. The process is then repeated until the desired accuracy is achieved. Also remember that the original numbers exponent, which represents the whole number part of the result, becomes the eight MSBs of the final
result.
Another technique is to look at the three MSBs of the mantissa and apply a
roundup from the fourth bit. Those same MSBs can be used as a quick extension of the exponent (logarithm). To visualize this, consider the following tabulated values and graph.
1.0
1.000
1.250
1.500
1.7500
1.999
log2(Mant)
0.000
0.322
0.585
0.807
0.999
Fraction
Mant
0.585
0.5
0.0
1.0
1.5
2.0
Mantissa
Figure 5−22. Tabulated Values for Mantissa
Note:
The fractional part is the same at the endpoints.
In the middle, only a slight bowing exists which can either be ignored or optionally
rounded for better accuracy. The maximum actually occurs at a mantissa value
of
1
ln(2.0)
or 1.442695. The value of log2(mant) at that point is 0.52876637, giving a maximum error of 0.086071.
5-46
Fast Logarithms on a Floating-Point Device
When finished, the bits representing the finished logarithm are in a fixed-point
notation and need to be scaled. This is done by using the FLOAT instruction followed by a multiplication by a constant scaling factor. If the final result needs to
be in any other base, the scaling factor is simply adjusted for that base.
5.11.2 Points to Consider
The round-off accuracy of the first three squaring operations affect the final
result if >21 mantissa bits are desired. A RND instruction placed after the first
three MPYF R0,R0 instructions remedy this, but adds to the cycle count.
When the input value approaches 1.0, the result is driven close to zero and
accuracy suffers. In this case, an input range comparison and a branch to a
McLauren series expansion is used as a solution with minimal degradation in
speed. This is because the power series converges quickly for input values
close to 1.0.
If you only need to calculate a visual quality logarithm, such as in spectrum
analysis, the logarithm can often be calculated in one cycle. In this case the
mantissa is substituted directly into the fractional bits of the logarithm giving
a maximum error of 0.086 (about 3.5 bits). The one cycle arises from the need
to remove the 2’s compliment sign bit in the ’C3x’s mantissa.
Data Formats and Floating-Point Operation
5-47
Fast Logarithms on a Floating-Point Device
Figure 5−23. Fast Logarithm for FFT Displays
**************************************************************** *
*
FAST Logarithm for FFT displays
*
*
>>>> NEED ONLY ADD ONE INSTRUCTION IN MANY CASES <<<<
*
******************************************************************
||
MPYF
MYPF
ADDF
ASH
||
REAL,REAL,R0
IMAG,IMAG,R1
R1,R0
−1,R0
;
; calculate the magnitude
; Note: sign bit is zero
;
; <−One instruction logarithm!
STR
R0,OUT
;
scaled externally in DAC
||
||
;
**********************************************************************
* _log_E.asm
DEVICE: TMS320C30
*
**********************************************************************
.global_log_E
_log_E:POP
AR1
; return address −> AR1
POPF
R0
; X −> R0
LDF
R0,R1
; use R1 to accumulate answer
LDI
2,RC
; repeat 3x
RPTB
loop
;
ASH
7,R1
;
LDE
1.0,R0
; EXP = 0
MPYF
R0,R0
; mant^2
MPYF
R0,R0
; mant^4
MPYF
R0,R0
; mant^8
MPYF
R0,R0
; mant^16
MPYF
R0,R0
; mant^32
MPYF
R0,R0
; mant^64
MPYF
R0,R0
; mant^128
PUSHF R1
; PUSH EXP and Mantissa (sign is now data!)
POP
R0
; POP as ianteger (EXP+FRACTION)
BD
AR1
;
FLOAT R0
; convert EXP+FRACTION to float
MPYF
@CONST,R0
; scale the result by 2^−24 and change base
ADDI
1,SP
; restore stack pointer
.data
CONST_ADR:
.word CONST
CONST
.long
0e7317219h
;;Base e hand calc w/1 lsb round
.end
5-48
Chapter 6
!
The ’C3x supports five groups of powerful addressing modes. Six types of
addressing that allow data access from memory, registers, and the instruction
word can be used within the groups. This chapter describes the operation,
encoding, and implementation of the addressing modes. It also discusses the
management of system stacks, queues, and dequeues in memory.
Topic
Page
6.1
Addressing Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2
Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4
Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.5
Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.6
PC-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.7
Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.8
Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.9
Aligning Buffers With the TMS320 Floating-Point
DSP Assembly Language Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
6.10 System and User Stack Management . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6-1
Addressing Types
6.1 Addressing Types
You can access data from memory, registers, and the instruction word by using
five types of addressing:
- Register addressing . A CPU register contains the operand.
- Direct addressing . The data address is formed by concatenating the
eight least significant bits (LSBs) of the data-page (DP) register and the
16 LSBs of the instruction.
- Indirect addressing . An auxiliary register contains the address of the
operand.
- Immediate addressing. The operand is a 16-bit or 24-bit immediate value.
- PC-relative addressing. A 16-bit or 24-bit displacement to the program
counter (PC).
Two specialized modes are available for use in filters, FFTs, and DSP algorithms:
- Circular addressing . An auxiliary register is incremented/decremented
with regards to a circular buffer boundary.
- Bit-reverse address ing. An auxiliary register is transferred to its bit-
reversed representation that contains the address of the operand.
6-2
Register Addressing
6.2 Register Addressing
In register addressing, a CPU register contains the operand, as shown in this
example:
ABSF
R1
; R1 = |R1|
The syntax for the CPU registers, the assembler syntax, and the assigned
function for those registers are listed in Table 6−1.
Table 6−1. CPU Register Address/Assembler Syntax and Function
Register Name
Machine Address
Assigned Function
R0
00h
Extended-precision register 0
R1
01h
Extended-precision register 1
R2
02h
Extended-precision register 2
R3
03h
Extended-precision register 3
R4
04h
Extended-precision register 4
R5
05h
Extended-precision register 5
R6
06h
Extended-precision register 6
R7
07h
Extended-precision register 7
AR0
08h
Auxiliary register 0
AR1
09h
Auxiliary register 1
AR2
0Ah
Auxiliary register 2
AR3
0Bh
Auxiliary register 3
AR4
0Ch
Auxiliary register 4
AR5
0Dh
Auxiliary register 5
AR6
0Eh
Auxiliary register 6
AR7
0FH
Auxiliary register 7
DP
10h
Data-page pointer
IR0
11h
Index register 0
IR1
12h
Index register 1
BK
13h
Block-size register
SP
14h
Active stack pointer
ST
15h
Status register
IE
16h
CPU/DMA interrupt-enable
IF
17h
CPU interrupt flags
IOF
18h
I/O flags
RS
19h
Repeat start address
RE
1Ah
Repeat end address
RC
1Bh
Repeat counter
Addressing Modes
6-3
Direct Addressing
6.3 Direct Addressing
In direct addressing, the data address is formed by the concatenation of the
eight LSBs of the data-page pointer (DP) with the 16 LSBs of the instruction
word (expr). This results in 256 pages (64K words per page), allowing you to
access a large address space without requiring a change of the page pointer.
The syntax and operation for direct addressing are:
Syntax:
@expr
Operation:
address = DP concatenated with expr
Figure 6−1 shows the formation of the data address. Example 6−1 is an instruction example with data before and after instruction execution.
Figure 6−1. Direct Addressing
31
16
expr
8
31
DP
x
(Datapage pointer)
0
15
Instruction
word
x...x
7
page
x
31
0
24
0...0
0
23
0
address
0
0
31
operand
Example 6−1. Direct Addressing
ADDI
@0BCDEh,R7
Before Instruction
After Instruction
R7
00 0000 0000
R7
00 1234 5678
DP
8A
DP
8A
8ABCDEh
1234 5678
8ABCDEh
1234 5678
Data memory
6-4
Indirect Addressing
6.4 Indirect Addressing
Indirect addressing specifies the address of an operand in memory through the
contents of an auxiliary register, optional displacements, and index registers as
shown in Example 6−2. Only the 24 LSBs of the auxiliary registers and index
registers are used in indirect addressing. The auxiliary register arithmetic units
(ARAUs) perform the unsigned arithmetic on these lower 24 bits. The upper
eight bits are unmodified.
Example 6−2. Auxiliary Register Indirect
An auxiliary register (ARn) contains the address of the operand to be fetched.
Operation:
operand address = ARn
Assembler Syntax:
*ARn
Modification Field:
11000
ARn
31
24
x
x
23
0
Address
31
0
Operand
The flexibility of indirect addressing is possible because the ARAUs on the
’C3x modify auxiliary registers in parallel with operations within the main CPU.
Indirect addressing is specified by a 5-bit field in the instruction word, referred
to as the mod field (shown in Table 6−2). A displacement is either an explicit
unsigned 8-bit integer contained in the instruction word or an implicit displacement of 1. Two index registers, IR0 and IR1, can also be used in indirect
addressing, enabling the use of 24-bit indirect displacement. In some cases,
an addressing scheme using circular or bit-reversed addressing is optional.
Generating addresses in circular addressing is discussed in Section 6.7 on
page 6-21; bit-reversed addressing is discussed in Section 6.8 on page 6-26.
Table 6−2 lists the various kinds of indirect addressing, along with the value
of the modification (mod) field, assembler syntax, operation, and function for
each. The succeeding 17 examples show the operation for each kind of indirect addressing. Figure 6−3 on page 6-20 shows the format in the instruction
encoding.
Addressing Modes
6-5
Indirect Addressing
Figure 6−2. Indirect Addressing Operand Encoding
MSB
LSB
mod
ARn
5 bits
3 bits
disp
0, 5, or 8 bits
Note: Auxiliary Register
The auxiliary register (ARn) is encoded in the instruction word according to its
binary representation n (for example, AR3 is encoded as 112), not its register
machine address (shown in Table 6−1).
6-6
Indirect Addressing
Table 6−2. Indirect Addressing
(a) Indirect addressing with displacement
Mod Field
Syntax
Operation
Description
00000
*+ARn(disp)
addr = ARn + disp
With predisplacement add
00001
*−ARn(disp)
addr = ARn − disp
With predisplacement subtract
00010
*++ARn(disp)
addr = ARn + disp
ARn = ARn + disp
With predisplacement add and modify
00011
*−−ARn(disp)
addr = ARn − disp
ARn = ARn − disp
With predisplacement subtract and modify
00100
*ARn++(disp)
addr = ARn
ARn = ARn + disp
With postdisplacement add and modify
00101
*ARn −−(disp)
addr = ARn
ARn = ARn − disp
With postdisplacement subtract and modify
00110
*ARn++(disp)%
addr = ARn
ARn = circ(ARn + disp)
With postdisplacement add and circular modify
00111
*ARn−−(disp)%
addr = ARn
ARn = circ(ARn − disp)
With postdisplacement subtract and circular modify
(b) Indirect addressing with index register IR0
Mod Field
Syntax
Operation
Description
01000
*+ARn(IR0)
addr = ARn + IR0
With preindex (IR0) add
01001
*−ARn(IR0)
addr = ARn − IR0
With preindex (IR0) subtract
01010
*++ARn(IR0)
addr = ARn + IR0
ARn = ARn + IR0
With preindex (IR0) add and modify
01011
* −−ARn(IR0)
addr = ARn − IR0
ARn = ARn − IR0
With preindex (IR0) subtract and modify
01100
*ARn++(IR0)
addr = ARn
ARn = ARn + IR0
With postindex (IR0) add and modify
01101
*ARn −−(IR0)
addr= ARn
ARn = ARn − IR0
With postindex (IR0) subtract and modify
01110
*ARn++(IR0)%
addr = ARn
ARn = circ(ARn + IR0)
With postindex (IR0) add and circular modify
01111
*ARn −−(IR0)%
addr = ARn
ARn = circ(ARn − IR0)
With postindex (IR0) subtract and circular modify
Legend:
addr
ARn
circ( )
disp
memory address
auxiliary registers AR0−AR7
address in circular addressing
displacement
++
−−
%
IRn
add and modify
subtract and modify
where circular addressing is performed
index register IR0 or IR1
Addressing Modes
6-7
Indirect Addressing
Table 6−2. Indirect Addressing (Continued)
(c) Indirect addressing with index register IR1
Mod Field
Syntax
Operation
Description
10000
*+ ARn(IR1)
addr = ARn + IR1
With preindex (IR1) add
10001
* −ARn(IR1)
addr = ARn − IR1
With preindex (IR1) subtract
10010
* ++ ARn(IR1)
addr = ARn + IR1
ARn = ARn + IR1
With preindex (IR1) add and modify
10011
* −−ARn(IR1)
addr = ARn − IR1
ARn = ARn − IR1
With preindex (IR1) subtract and modify
10100
* ARn ++ (IR1)
addr = ARn
ARn = ARn + IR1
With postindex (IR1) add and modify
10101
*ARn −−(IR1)
addr = ARn
ARn = ARn − IR1
With postindex (IR1) subtract and modify
10110
* ARn ++ (IR1)%
addr = ARn
ARn = circ(ARn + IR1)
With postindex (IR1) add and circular modify
10111
* ARn −−(IR1)%
addr = ARn
ARn = circ(ARn − IR1)
With postindex (IR1) subtract and circular modify
(d) Indirect addressing (special cases)
Mod Field
Syntax
Operation
Description
11000
*ARn
addr = ARn
Indirect
11001
*ARn ++ (IR0)B
addr = ARn
With postindex (IR0) add
ARn = B(ARn + IR0)
and bit-reversed modify
Legend:
addr
ARn
B
B()
memory address
auxiliary registers AR0−AR7
where bit-reversed addressing is performed
bit-reversed address
circ( )
++
−−
%
IRn
address in circular addressing
add and modify by 1
subtract and modify by 1
where circular addressing is performed
index register IR0 or IR1
Example 6−3 through Example 6−19 show the operation for each type of indirect
addressing.
6-8
Indirect Addressing
Example 6−3. Indirect Addressing With Predisplacement Add
The address of the operand to fetch is the sum of an auxiliary register (ARn) and
the displacement (disp). The displacement is either an 8-bit unsigned integer
contained in the instruction word or an implied value of 1.
Operation:
operand address = ARn + disp
Assembler Syntax:
*+ARn(disp)
Modification Field:
00000
ARn
31
24 23
x
x
31
disp
0
Address
8
0
0...0
7
0
(+)
Integer
0
31
0
Operand
Example 6−4. Indirect Addressing With Predisplacement Subtract
The address of the operand to fetch is the contents of an auxiliary register
(ARn) minus the displacement (disp). The displacement is either an 8-bit
unsigned integer contained in the instruction word or an implied value of 1.
Operation:
operand address = ARn − disp
Assembler Syntax:
*−ARn(disp)
Modification Field:
00001
ARn
31
24 23
x
x
31
disp
0
0...0
0
Address
8
7
0
Integer
0
(−)
0
31
Operand
Addressing Modes
6-9
Indirect Addressing
Example 6−5. Indirect Addressing With Predisplacement Add and Modify
The address of the operand to fetch is the sum of an auxiliary register (ARn) and
the displacement (disp). The displacement is either an 8-bit unsigned integer
contained in the instruction word or an implied value of 1. After the data is
fetched, the auxiliary register is updated with the address generated.
Operation:
operand address = ARn + disp
ARn = ARn + disp
Assembler Syntax:
*++ARn (disp)
Modification Field:
00010
ARn
31
24 23
x
x
31
disp
0
0...0
0
Address
8
7
0
0
Integer
(+)
0
31
Operand
Example 6−6. Indirect Addressing With Predisplacement Subtract and Modify
The address of the operand to fetch is the contents of an auxiliary register
(ARn) minus the displacement (disp). The displacement is either an 8-bit
unsigned integer contained in the instruction word or an implied value of 1.
After the data is fetched, the auxiliary register is updated with the address
generated.
Operation:
operand address = ARn − disp
ARn = ARn − disp
Assembler Syntax:
*−−ARn(disp)
Modification Field:
00011
ARn
31
24 23
x
x
31
disp
0
0...0
0
Address
8
7
0
Integer
(−)
0
31
Operand
6-10
0
Indirect Addressing
Example 6−7. Indirect Addressing With Postdisplacement Add and Modify
The address of the operand to fetch is the contents of an auxiliary register (ARn).
After the operand is fetched, the displacement (disp) is added to the auxiliary
register. The displacement is either an 8-bit unsigned integer contained in the
instruction word or an implied value of 1.
Operation:
operand address = ARn
ARn = ARn + disp
Assembler Syntax:
*ARn ++ (disp)
Modification Field:
00100
ARn
31
24 23
x
x
31
disp
0
0...0
0
Address
8
7
0
0
Integer
(+)
31
0
Operand
Example 6−8. Indirect Addressing With Postdisplacement Subtract and Modify
The address of the operand to fetch is the contents of an auxiliary register
(ARn). After the operand is fetched, the displacement (disp) is subtracted from
the auxiliary register. The displacement is either an 8-bit unsigned integer
contained in the instruction word or an implied value of 1.
Operation:
operand address = ARn
ARn = ARn − disp
Assembler Syntax:
*ARn −−(disp)
Modification Field:
00101
ARn
31
24 23
x
x
31
disp
0
0...0
0
Address
8
7
0
0
Integer
(−)
0
31
Operand
Addressing Modes
6-11
Indirect Addressing
Example 6−9. Indirect Addressing With Postdisplacement Add and Circular Modify
The address of the operand to fetch is the contents of an auxiliary register
(ARn). After the operand is fetched, the displacement (disp) is added to the
contents of the auxiliary register using circular addressing. This result is used
to update the auxiliary register. The displacement is either an 8-bit unsigned
integer contained in the instruction word or an implied value of 1.
Operation:
operand address = ARn
ARn = circ(ARn + disp)
Assembler Syntax:
*ARn ++ (disp)%
Modification Field:
00110
ARn
31
24 23
x
x
Address
31
disp
0
0
8
0
0...0
7
0
(%)
Integer
(+)
0
31
Operand
Example 6−10. Indirect Addressing With Postdisplacement Subtract and Circular Modify
The address of the operand to fetch is the contents of an auxiliary register
(ARn). After the operand is fetched, the displacement (disp) is subtracted from
the contents of the auxiliary register using circular addressing. This result is
used to update the auxiliary register. The displacement is either an 8-bit
unsigned integer contained in the instruction word or an implied value of 1.
Operation:
operand address = ARn
ARn = circ(AR n − disp)
Assembler Syntax:
*ARn −−(disp)%
Modification Field:
00111
ARn
31
24
x
x
31
disp
0
0...0
0
23
Address
8
7
0
Integer
(%)
(−)
0
31
Operand
6-12
0
Indirect Addressing
Example 6−11. Indirect Addressing With Preindex Add
The address of the operand to fetch is the sum of an auxiliary register (ARn)
and an index register (IR0 or IR1).
Operation:
operand address = ARn + IRm
Assembler Syntax:
*+ARn(IRm)
Modification Field:
01000
10000
31
24 23
x
x
ARn
IRm
31
24 23
x
x
if m = 0
if m = 1
0
Address
0
Index
(+)
31
0
Operand
Example 6−12. Indirect Addressing With Preindex Subtract
The address of the operand to fetch is the difference of an auxiliary register
(ARn) and an index register (IR0 or IR1).
Operation:
operand address = ARn − IRm
Assembler Syntax:
*−ARn(IRm)
Modification Field:
01001
10001
31
ARn
IRm
31
24 23
x
x
x
if m = 0
if m = 1
24 23
0
x
Address
0
Index
(−)
0
31
Operand
Addressing Modes
6-13
Indirect Addressing
Example 6−13. Indirect Addressing With Preindex Add and Modify
The address of the operand to fetch is the sum of an auxiliary register (ARn) and
an index register (IR0 or IR1). After the data is fetched, the auxiliary register is
updated with the generated address.
Operation:
operand address = ARn + IRm
ARn = ARn + IRm
Assembler Syntax:
*++ARn(IRm)
Modification Field:
01010
10010
ARn
31
IRm
if m = 0
if m = 1
31
24 23
x
x
0
Address
0
24 23
x
(+)
Index
x
0
31
Operand
Example 6−14. Indirect Addressing With Preindex Subtract and Modify
The address of the operand to fetch is the difference between an auxiliary register
(ARn) and an index register (IR0 or IR1). The resulting address becomes the new
contents of the auxiliary register.
Operation:
operand address = ARn − IRm
ARn = ARn − IRm
Assembler Syntax:
*−−ARn(IRm)
Modification Field:
01011
10011
31
ARn
IRm
x
31
24 23
x
x
if m = 0
if m = 1
24 23
0
x
Address
0
Index
(−)
0
31
Operand
6-14
Indirect Addressing
Example 6−15. Indirect Addressing With Postindex Add and Modify
The address of the operand to fetch is the contents of an auxiliary register
(ARn). After the operand is fetched, the index register (IR0 or IR1) is added
to the auxiliary register.
Operation:
operand address = ARn
ARn = ARn + IRm
Assembler Syntax:
*ARn ++ (IRm)
Modification Field:
01100
10100
31
x
ARn
24 23
0
x
Address
24 23
x
0
x
(+)
31
IRm
if m = 0
if m = 1
Index
31
0
Operand
Example 6−16. Indirect Addressing With Postindex Subtract and Modify
The address of the operand to fetch is the contents of an auxiliary register (ARn).
After the operand is fetched, the index register (IR0 or IR1) is subtracted from
the auxiliary register.
Operation:
operand address = ARn
ARn = ARn − IRm
Assembler Syntax:
*ARn −−(IRm)
Modification Field:
01101
10101
ARn
IRm
x
31
24 23
x
x
0
Address
24 23
0
x
Index
(−)
31
if m = 0
if m = 1
0
31
Operand
Addressing Modes
6-15
Indirect Addressing
Example 6−17. Indirect Addressing With Postindex Add and Circular Modify
The address of the operand to fetch is the contents of an auxiliary register
(ARn). After the operand is fetched, the index register (IR0 or IR1) is added
to the auxiliary register. This value is evaluated using circular addressing and
replaces the contents of the auxiliary register.
Operation:
operand address = ARn
ARn = circ(ARn + IRm)
Assembler Syntax:
*ARn ++ (IRm)%
Modification Field:
01110
10110
if m = 0
if m = 1
31
24 23
x
x
ARn
31
IRm
0
Address
24 23
x
0
Index
x
(%)
(+)
0
31
Operand
Example 6−18. Indirect Addressing With Postindex Subtract and Circular Modify
The address of the operand to fetch is the contents of an auxiliary register (ARn).
After the operand is fetched, the index register (IR0 or IR1) is subtracted from the
auxiliary register. This result is evaluated using circular addressing and replaces
the contents of the auxiliary register.
Operation:
operand address = ARn
ARn = circ(ARn − IRm)
Assembler Syntax:
*ARn −− (IRm)%
Modification Field:
01111
10111
if m = 0
if m = 1
31
24 23
x
x
ARn
31
IRm
x
0
Address
24 23
0
x
Index
(−)
0
31
Operand
6-16
(%)
Indirect Addressing
Example 6−19. Indirect Addressing With Postindex Add and Bit-Reversed Modify
The address of the operand to fetch is the contents of an auxiliary register
(ARn). After the operand is fetched, the index register (IR0) is added to the
auxiliary register. This addition is performed with a reverse-carry propagation
and can be used to yield a bit-reversed (B) address. This value replaces the
contents of the auxiliary register.
Operation:
operand address = ARn
ARn = B(ARn + IR0)
Assembler Syntax:
*ARn++(IR0)B
Modification Field:
11001
ARn
IRm
31
24 23
x
x
31
24 23
x
x
0
Address
0
(B)
(+)
Index
31
0
Operand
Addressing Modes
6-17
Immediate Addressing
6.5 Immediate Addressing
In immediate addressing, the operand is a 16-bit (short) or 24-bit (long) immediate
value contained in the 16 or 24 LSBs of the instruction word (expr). Depending
on the data types assumed for the instruction, the short-immediate operand can
be a 2s-complement integer, an unsigned integer, or a floating-point number. This
is the syntax for this mode:
Syntax:
expr
Example 6−20 illustrates an instruction example with data before and after the
instruction is executed.
Example 6−20. Short-Immediate Addressing
SUBI 1,R0
Before Instruction
R0
00 0000 0000
After Instruction
R0
00 FFFF FFFF
In long-immediate addressing, the operand is a 24-bit unsigned immediate
value contained in the 24 LSBs of the instruction word (expr). This is the syntax
for this mode:
Syntax:
expr
Example 6−21 illustrates an instruction example with data from before and after
the instruction is executed.
Example 6−21. Long-Immediate Addressing
BR 8000h
Before Instruction
PC
6-18
0000
After Instruction
PC
8000
PC-Relative Addressing
6.6 PC-Relative Addressing
Program counter (PC)-relative addressing is used for branching. It adds the
contents of the 16 or 24 LSBs of the instruction word to the PC register. The
assembler takes the src (a label or address) specified by the user and generates
a displacement. If the branch is a standard branch, this displacement is equal to
[label − (instruction address +1)]. If the branch is a delayed branch, this displacement is equal to [label − (instruction address+3)].
The displacement is stored as a 16-bit or 24-bit signed integer in the LSBs of
the instruction word. The displacement is added to the PC during the pipeline
decode phase. Notice that because the PC is incremented by 1 in the fetch
phase, the displacement is added to this incremented PC value.
Syntax:
expr (src)
Example 6−22 illustrates an example with data from before and after the
instruction is executed.
Example 6−22. PC-Relative Addressing
BU
NEWPC
; pc=1001h, NEWPC label = 1005h, displacement = 3
Before Instruction
After Instruction
decode phase:
execution phase:
PC
1002
PC
1005
The 24-bit addressing mode encodes the program-control instructions (for
example, BR, BRD, CALL, RPTB, and RPTBD). Depending on the instruction, the new PC value is derived by adding a 24-bit signed value in the
instruction word with the present PC value. Bit 24 determines the type of
branch (D = 0 for a standard branch or D = 1 for a delayed branch). Some of
the instructions are encoded in Figure 6−3.
Addressing Modes
6-19
PC-Relative Addressing
Figure 6−3. Encoding for 24-Bit PC-Relative Addressing Mode
(a) BR, BRD: unconditional branches (standard and delayed)
31
0
25 24 23
1 1 0 0 0 0 0
0
Displacement
(b) CALL: unconditional subroutine call
31
0
24 23
1 1 0 0 0 1 0
0
Displacement
(c) RPTB: repeat block
31
0
6-20
25 24 23
1 1 0 0 1 0 0
0
Displacement
Circular Addressing
6.7 Circular Addressing
Many DSP algorithms, such as convolution and correlation, require a circular
buffer in memory. In convolution and correlation, the circular buffer acts as a
sliding window that contains the most recent data to process. As new data is
brought in, the new data overwrites the oldest data by increasing the pointer
to the data through the buffer in counter-clockwise fashion. When the pointer
accesses the end of the buffer, the device sets the pointer to the beginning of
the buffer. For example, Figure 6−4a shows a circular buffer that holds six values.
Figure 6−4b shows how this buffer is implemented in the ’C3x memory space.
Figure 6−5 shows this buffer after writing three values. Figure 6−6 shows this
buffer after writing eight values.
Figure 6−4. Logical and Physical Representation of Circular Buffer
a) Logical representation
Start
b)
End
Physical representation
Start
End
Figure 6−5. Logical and Physical Representation of Circular Buffer after Writing Three Values
b) Physical representation
a) Logical representation
Start
End
Start
value0
value1
value0
value2
value1
value2
End
Addressing Modes
6-21
Circular Addressing
Figure 6−6. Logical and Physical Representation of Circular Buffer after Writing Eight Values
a) Logical representation
b) Physical representation
Start
End
value6
Start
value6
value7
value5
value2
value7
value2
value4
value3
value4
value3
End
value5
To implement a circular buffer in the ’C3x, the following criteria must be satisfied (more than one circular buffer can be implemented on the ’C3x as long as
the size of the buffers are identical):
- Specify the size of the circular buffer (R) by storing the length of the buffer
in the block-size register (BK). The size of the buffer must be less than or
equal to 64K (16 bits).
- Align the start of the buffer to a K-bit boundary (that is, the K LSBs of the
starting address of the circular buffer must be 0) by satisfying the following
formula:
2K > R
where:
R = length of circular buffer
K = number of 0s in the LSBs of the circular buffer starting address
Example 6−23. Examples of Formula 2 K > R
Length of Buffer
6-22
BK Register Value
Starting Address of Buffer
31
31
XXXXXXXXXXXXXXXXXXX000002
32
32
XXXXXXXXXXXXXXXXXX0000002
1024
1024
XXXXXXXXXXXXX000000000002
Circular Addressing
In circular addressing, index refers to the K LSBs (from the K-bit boundary criteria)
of the auxiliary register selected, and step is the quantity being added to or
subtracted from the auxiliary register. Follow these two rules when you use circular addressing:
- The step used must be less than or equal to the block size. The step size
is treated as an unsigned integer. If an index register (IR) is used as a step
increment or decrement, it is also treated as an unsigned integer.
- The first time the circular queue is addressed, the auxiliary register must
be pointing to an element in the circular queue.
The algorithm for circular addressing is as follows:
If 0 ≤ index + step < BK:
index = index + step.
Else if index + step ≥ BK:
index = index + step − BK.
Else if index + step < 0:
index = index + step + BK.
Figure 6−7 shows how the circular buffer is implemented and illustrates the
relationship of the quantities generated and the elements in the circular buffer.
Figure 6−7. Circular Buffer Implementation
Address
31
K K−1
H...H
Effective base (EB)
Data
0
Top of circular buffer
→
0...0
MSBs of ARn
Element 1
K K−1
31
H...H
L...L
MSBs of ARn
LSBs of ARn
Auxiliary register (ARn)
K K−1
31
H...H
Element 0
LSBs BK
0
→
0
Element (K LSBs of ARn)
Last element
→
Last element + 1
MSBs of ARn
Example 6−24 shows circular addressing operation. Assuming that all ARs
are four bits, let AR0 = 0000 and BK = 0110 (block size of 6). Example 6−24
shows a sequence of modifications and the resulting value of AR0.
Example 6−24 also shows how the pointer steps through the circular queue
with a variety of step sizes (both incrementing and decrementing).
Addressing Modes
6-23
Circular Addressing
Example 6−24. Circular Addressing
*AR0 ++ (5)%
*AR0 ++ (2)%
*AR0 − −(3)%
*AR0++(6)%
*AR0 − −%
*AR0
;
;
;
;
;
;
AR0
AR0
AR0
AR0
AR0
AR0
=
=
=
=
=
=
0
5
1
4
4
3
Value
(0 value)
(1st value)
(2nd value)
(3rd value)
(4th value)
(5th value)
Data
Address
0
→
Element 0
0
2nd
→
Element 1
1
Element 2
2
5th
→
Element 3
3
4th, 3rd
→
Element 4
4
1st
→
Element 5 (last element)
5
6
Last element + 1
Circular addressing is especially useful for the implementation of FIR filters.
Figure 6−8 shows one possible data structure for FIR filters. Note that the initial value of AR0 points to h(N −1), and the initial value of AR1 points to x(0).
Circular addressing is used in the ’C3x code for the FIR filter shown in
Example 6−25.
Figure 6−8. Data Structure for FIR Filters
AR0
6-24
→
Impulse response
Input samples
h(N −1)
x(N −1)
h(N −2)
x(N −2)
.
.
.
.
.
.
h(2)
x(2)
h(1)
x(1)
h(0)
x(0)
←
AR1
Circular Addressing
Example 6−25. FIR Filter Code Using Circular Addressing
*
H
*
X
Impulse Response
.sect ”Impulse_Resp”
.float 1.0
.float 0.99
.float 0.95
.
.
.
.float 0.1
Input Buffer
.usect ”Input_Buf”,128
.data
HADDR .word H
XADDR .word X
N
.word 128
*
*
*
TOP
*
*
*
||
Initialization
LDP
LDI
LDI
HADDR
@N,BK
@HADDR,AR0
LDI
@XADDR,AR1
LDF
STF
IN,R3
R3,*AR1++%
LDF
LDF
0,R0
0,R2
;
;
;
;
;
Load block size.
Load pointer to impulse re−
sponse.
Load pointer to bottom of
input sample buffer.
;Read input sample.
;Store with other samples,
;and point to top of buffer.
;Initialize R0.
;Initialize R2.
Filter
RPTS
MPYF3
ADDF3
ADDF
N −1
;Repeat next instruction.
*AR0++%,*AR1++%,R0
R0,R2,R2
;Multiply and accumulate.
R0,R2
;Last product accumulated.
STF
B
R2,Y
TOP
*
;Save result.
;Repeat.
Addressing Modes
6-25
Bit-Reversed Addressing
6.8 Bit-Reversed Addressing
The ’C3x can implement fast Fourier transforms (FFT) with bit-reversed addressing. Whenever data in increasing sequence order is transformed by an
FFT, the resulting data is presented in bit-reversed order. To recover this data
in the correct order, certain memory locations must be swapped. By using the
bit-reversed addressing mode, swapping data is unnecessary. The data is accessed by the CPU in bit-reversed order rather than sequentially. For correct
bit-reversed access, the base address of bit-reversed access, the base address must be located on a boundary given by the size of the FFT table. Similar
to circular addressing, the base address of bit-reversed addressing must follow this criteria.
- Base address must be aligned to a K-bit boundary (that is, the K LSBs of
the starting address of the buffer/table must be 0) as follows:
2K > R
where:
R = length of table/buffer
K = number of 0s in the LSBs of the buffer/table starting address
- Size of the buffer/table must be less than or equal to 64K (16 bits)
The CPU bit-reversed operation can be illustrated by assuming an FFT table
of size 2n. When real and imaginary data are stored in separate arrays, the n
LSBs of the base address must be 0, and IR0 must be equal to 2n−1 (half of
the FFT size). When real and imaginary data are stored in consecutive
memory locations (Real0, Imaginary0, Real1, Imaginary1, Real2, Imaginary2,
etc.), the n+1 LSBs of the base address must be 0, and IR0 must be equal to
2n (FFT size).
For CPU bit-reversed addressing, one auxiliary register points to the physical
location of data. Adding IR0 (in bit-reversed addressing) to this auxiliary register
performs a reverse-carry propagation. IR0 is treated as an unsigned integer.
To illustrate bit-reversed addressing, assume 8-bit auxiliary registers. Let AR2
contain the value 0110 0000 (96). This is the base address of the data in
memory assuming a 16-entry table. Let IR0 contain the value 0000 1000 (8).
Example 6−26 shows a sequence of modifications of AR2 and the resulting
values of AR2.
6-26
Bit-Reversed Addressing
Example 6−26. Bit-Reversed Addressing
*AR2++(IR0)B
*AR2++(IR0)B
*AR2++(IR0)B
*AR2++(IR0)B
*AR2++(IR0)B
*AR2++(IR0)B
*AR2++(IR0)B
*AR2
;
;
;
;
;
;
;
;
AR2=
AR2=
AR2=
AR2=
AR2=
AR2=
AR2=
AR2=
0110
0110
0110
0110
0110
0110
0110
0110
0000
1000
0100
1100
0010
1010
0110
1110
(0th
(1st
(2nd
(3rd
(4th
(5th
(6th
(7th
value)
value)
value)
value)
value)
value)
value)
value)
Table 6−3 shows the relationship of the index steps and the four LSBs of AR2.
You can find the four LSBs by reversing the bit pattern of the steps.
Table 6−3. Index Steps and Bit-Reversed Addressing
Step
Bit Pattern
Bit-Reversed
Pattern
Bit-Reversed
Step
0
0000
0000
0
1
0001
1000
8
2
0010
0100
4
3
0011
1100
12
4
0100
0010
2
5
0101
1010
10
6
0110
0110
6
7
0111
1110
14
8
1000
0001
1
9
1001
1001
9
10
1010
0101
5
11
1011
1101
13
12
1100
0011
3
13
1101
1011
11
14
1110
0111
7
15
1111
1111
15
Addressing Modes
6-27
Aligning
Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools
6.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly
Language Tools
To align buffers to a K-bit boundary, you can use the .sect or .usect assembly
directives to define a section in conjunction with the align memory allocation
parameter of the sections directive of the linker command file. For the FIR filter
of Example 6−25 with a length of 32, the linker command file is:
MEMORY
{
RAM origin = 0h, length = 1000h
}
SECTIONS
{
.text: > RAM
Impulse_Resp ALIGN(64): > RAM
Input_Buf
ALIGN(64): > RAM
}
6-28
System and User Stack Management
6.10 System and User Stack Management
The ’C3x provides a dedicated system-stack pointer (SP) for building stacks
in memory. The auxiliary registers can also be used to build a variety of more
general linear lists. This section discusses the implementation of the following
types of linear lists:
- Stack
The stack is a linear list for which all insertions and deletions are made at
one end of the list.
- Queue
The queue is a linear list for which all insertions are made at one end of the
list and all deletions are made at the other end.
- Dequeue
The dequeue is a double-ended queue linear list for which insertions and
deletions are made at either end of the list.
6.10.1 System-Stack Pointer
The system-stack pointer (SP) is a 32-bit register that contains the address of
the top of the system stack. The system stack fills from low-memory address
to high-memory address (see Figure 6−9). The SP always points to the last
element pushed onto the stack. A push performs a preincrement, and a pop
performs a postdecrement of the system-stack pointer.
The program counter is pushed onto the system stack on subroutine calls,
traps, and interrupts. It is popped from the system stack on returns. The system stack can be pushed and popped using the PUSH, POP, PUSHF, and
POPF instructions.
Figure 6−9. System Stack Configuration
Low memory
Bottom of stack
.
.
.
SP
→
Top of stack
(Free)
High memory
Addressing Modes
6-29
System and User Stack Management
6.10.2 Stacks
Stacks can be built from low to high memory or high to low memory. Two cases
for each type of stack are shown. Stacks can be built using the preincrement/
decrement and postincrement/decrement modes of modifying the auxiliary
registers (AR). Stack growth from high-to-low memory can be implemented in
two ways:
CASE 1: Stores to memory using *− −ARn to push data onto the stack and
reads from memory using *ARn ++ to pop data off the stack.
CASE 2: Stores to memory using *ARn − −to push data onto the stack and
reads from memory using * ++ ARn to pop data off the stack.
Figure 6−10 illustrates these two cases. The only difference is that in case 1,
the AR always points to the top of the stack, and in case 2, the AR always points
to the next free location on the stack.
Figure 6−10. Implementations of High-to-Low Memory Stacks
Case 1
Low memory
(Free)
ARn
→
Top of stack
Case 2
Low memory
ARn
→
(Free)
Top of stack
Bottom of stack
Bottom of stack
High memory
High memory
Stack growth from low-to-high memory can be implemented in two ways:
CASE 3: Stores to memory using *++ ARn to push data onto the stack and
reads from memory using *ARn − −to pop data off the stack.
CASE 4: Stores to memory using *ARn ++ to push data onto the stack and
reads from memory using *− −ARn to pop data off the stack.
Figure 6−11 shows these two cases. In case 3, the AR always points to the top
of the stack. In case 4, the AR always points to the next free location on the stack.
6-30
System and User Stack Management
Figure 6−11.Implementations of Low-to-High Memory Stacks
ARn
→
Case 3
Low memory
Case 4
Low memory
Bottom of stack
.
.
.
Bottom of stack
.
.
.
Top of stack
(Free)
High memory
Top of stack
ARn
→
(Free)
High memory
6.10.3 Queues
A queue is like a FIFO. The implementation of queues is based on the manipulation of auxiliary registers. Two auxiliary registers are used: one to mark the
front of the queue from which data is popped (or dequeued) and the other to
mark the rear of the queue where data is pushed. With proper management
of the auxiliary registers, the queue can also be circular. (A queue is circular
when the rear pointer is allowed to point to the beginning of the queue memory
after it has pointed to the end of the queue memory.)
Addressing Modes
6-31
6-32
Chapter 7
The TMS320C3x provides a complete set of constructs that facilitate software
and hardware control of the program flow. Software control includes repeats,
branches, calls, traps, and returns. Hardware control includes reset operation,
interrupts, and power management. You can select the constructs best suited
for your particular application.
Topic
Page
7.1
Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2
Delayed Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3
Calls, Traps, and Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.4
Interlocked Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.5
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.7
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
7.8
Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
7.9
Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
7-1
Repeat Modes
7.1 Repeat Modes
The repeat modes of the ’C3x can implement zero-overhead looping. For many
algorithms, most execution time is spent in an inner kernel of code. Using the
repeat modes allows these time-critical sections of code to be executed in the
shortest possible time.
The ’C3x provides two instructions to support zero-overhead looping:
- RPTB (repeat a block of code). RPTB repeats execution of a block of code
a specified number of times.
- RPTS (repeat a single instruction). RPTS fetches a single instruction once
and then repeats its execution a number of times. Since the instruction is
fetched only once, bus traffic is minimized.
RPTB and RPTS are 4-cycle instructions. These four cycles of overhead occur
during the initial execution of the loop. All subsequent executions of the loop
have no overhead (0 cycle).
Three registers (RS, RE, and RC) control the updating of the program-counter
(PC) when it is modified in a repeat mode. Table 7−1 describes these registers.
Table 7−1. Repeat-Mode Registers
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Register
RS
RE
RC
Function
Repeat start-address register. Holds the address of the first instruction
of the block of code to be repeated.
Repeat end-address register. Holds the address of the last instruction
of the block of code to be repeated. RERS (see subsection 7.1.2).
Repeat-counter register. Contains 1 less than the number of times
the block remains to be repeated. For example, to execute a block
n times, load n − 1 into RC.
Correct operation of the repeat modes requires that all of the above registers
must be initialized correctly. RPTB and RPTS perform this initialization in
slightly different ways.
7-2
Repeat Modes
7.1.1
Repeat-Mode Control Bits
Two bits are important to the operation of RPTB and RPTS:
- RM bit. The repeat-mode (RM) flag bit in the status register specifies
whether the processor is running in the repeat mode.
J
J
RM = 0: Fetches are not made in repeat mode.
RM = 1: Fetches are made in repeat mode.
- S bit. The S bit is internal to the processor and cannot be programmed,
but this bit is necessary to fully describe the operation of RPTB and RPTS.
J
If RM = 1 and S = 0, RPTB is executing. Program fetches occur from
memory.
J If RM = 1 and S = 1, RPTS is executing. After the first fetch from
memory, program fetches occur from the instruction register.
7.1.2
Repeat-Mode Operation
Information in the repeat-mode registers and associated control bits controls
the modification of the PC during repeat-mode fetches. The repeat modes
compare the contents of the RE register (repeat-end-address register) with the
PC after the execution of each instruction. If they match and the repeat counter
(RC) is nonnegative, the RC is decremented; the PC is loaded with the repeatstart-address, and the processing continues. The fetches and appropriate
status bits are modified as necessary. Note that the RC is never modified
when the RM flag is 0.
The repeat counter should be loaded with a value 1 less than the number of
times to execute the block; for example, an RC value of 4 executes the block
five times. The detailed algorithm for the update of the PC is shown in
Example 7−1.
Note: Maximum Number of Repeats
1) The maximum number of repeats occurs when RC = 8000 0000h. This
results in 8000 0001h repetitions. The minimum number of repeats occurs
when RC = 0. This results in one repetition.
2) RE must be greater than or equal to RS (RE ≥ RS). Otherwise, the code
does not repeat even though the RM bit remains set to 1.
3) By writing a 0 into the repeat counter or writing 0 into the RM bit of the
status register, you can stop the repeating of the loop before completion.
Program Flow Control
7-3
Repeat Modes
Example 7−1. Repeat-Mode Control Algorithm
if RM == 1
if S == 1
if first time through
fetch instruction from memory
else
fetch instruction from IR
RC − 1 → RC
if RC < 0
0 → ST(RM)
0 → S
PC + 1 → PC
else if S == 0
fetch instruction from memory
if PC == RE
RC − 1 → RC
if RC ≥ 0
RS → PC
else if RC < 0
0 → ST(RM)
0 → S
PC + 1 → PC
7.1.3
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
If in repeat mode (RPTB or RPTS)
If RPTS
If this is the first fetch
Fetch instruction from memory
If not the first fetch
Fetch instruction from IR
Decrement RC
If RC is negative
Repeat single mode completed
Turn off repeat-mode bit
Clear S
Increment PC
If RPTB
Fetch instruction from memory
If this is the end of the block
Decrement RC
If RC is not negative
Set PC to start of block
If RC is negative
Turn off repeat mode bits
Clear S
Increment PC
RPTB Instruction
The RPTB instruction repeats a block of code a specified number of times.
The number of times to repeat the block is the RC (repeat count) register value
plus 1. Because the execution of RPTB does not load the RC, you must load this
register yourself. The RC register must be loaded before the RPTB instruction is
executed. A typical setup of the block repeat operation is shown in Example 7−2.
Example 7−2. RPTB Operation
LDI 15,RC
RPTB ENDLOOP
STLOOP
.
.
.
ENDLOOP
7-4
;
;
;
;
Load repeat counter with 15
Execute the block of code
from STLOOP to ENDLOOP 16
times
Repeat Modes
All block repeats initiated by RPTB can be interrupted. When RPTB src
(source) instruction executes, it performs the following sequence:
1) Load the start address of the block into repeat-start-address register (RS).
This is the next address following the instruction:
RS z PC (program-counter) of RPTB + 1
2) Load the end address of the block into repeat-end-address register (RE).
- In PC-relative mode, the end address is the 24-bit src operand plus
RS:
RE z src + PC of RPTB + 1
- In register mode, the end address is the contents of the src register:
RE z src register
3) Set the status register to indicate the repeat-mode operation.
RM z 1
4) Indicate repeat-mode operation by clearing the S bit.
Sz0
Note:
You can stop the loop from repeating before its completion by writing a 0 to
the repeat counter or writing a 0 to the RM bit of the status register.
7.1.4
RPTS Instruction
An RPTS src instruction repeats the instruction following the RPTS (src + 1)
times. Repeats of a single instruction initiated by RPTS are not interruptible,
because the RPTS fetches the instruction word only once and then keeps it
in the instruction register for reuse. An interrupt in this situation would cause
the instruction word to be lost. Refetching the instruction word from the instruction
register reduces memory accesses and, in effect, acts as a one-word program
cache. If you need a single instruction that is repeatable and interruptible, you can
use the RPTB instruction.
When RPTS src is executed, the following sequence of operations occurs:
1)
2)
3)
4)
5)
PC + 1 → RS
PC + 1 → RE
1 → RM status register bit
1 → S bit
src → RC (repeat count register)
Program Flow Control
7-5
Repeat Modes
The RPTS instruction loads all registers and mode bits necessary for the operation of the single-instruction repeat mode. Step 1 loads the start address of the
block into RS. Step 2 loads the end address into the RE (end address of the
block). Since this is a repeat of a single instruction, the start address and the end
address are the same. Step 3 sets the status register to indicate the repeat
mode of operation. Step 4 indicates that this is the repeat single-instruction
mode of operation. Step 5 loads src into RC.
7.1.5
Repeat-Mode Restrictions
Because the block-repeat modes modify the program counter, no other
instruction can modify the program counter at the same time. Two rules apply:
Rule 1: The last instruction in the block (or the only instruction in a block of
size 1) cannot be a Bcond, BR, DBcond, CALL, CALLcond, TRAPcond, RETIcond, RETScond, IDLE, RPTB, or RPTS. Example 7−3
shows an incorrectly placed standard branch.
Rule 2: None of the last four instructions from the bottom of the block (or the
only instruction in a block of size 1) can be a BcondD, BRD, or
DBcondD. Example 7−4 shows an incorrectly placed delayed
branch.
If either of these rules is violated, the PC is undefined.
Example 7−3. Incorrectly Placed Standard Branch
LDI
RPTB
15,RC
ENDLOOP
;
;
;
;
BR
OOPS
; This branch violates rule 1
STLOOP
.
.
.
ENDLOOP
7-6
Load repeat counter with 15
Execute the block of code
from STLOOP to ENDLOOP 16
times
Repeat Modes
Example 7−4. Incorrectly Placed Delayed Branch
LDI
RPTB
15,RC
ENDLOOP
;
;
;
;
.
.
.
BRD
ADDF
MPYF
SUBF
OOPS
; This branch violates rule 2
STLOOP
ENDLOOP
7.1.6
Load repeat counter with 15
Execute block of code
from STLOOP to ENDLOOP 16
times
RC Register Value After Repeat Mode Completes
For the RPTB instruction, the RC register normally decrements to 0000 0000h
unless the block size is 1; in which case, it decrements to FFFF FFFFh. However,
if the RPTB instruction using a block size of 1 has a pipeline conflict in the instruction being executed, the RC register decrements to 0000 0000h. Example 7−5
illustrates a pipeline conflict. See Chapter 8 for pipeline information.
RPTS normally decrements the RC register to FFFF FFFFh. However, if the
RPTS has a pipeline conflict on the last cycle, the RC register decrements to
0000 0000h.
Note: Number of Repetitions
In any case, the number of repetitions is always RC + 1.
Example 7−5. Pipeline Conflict in an RPTB Instruction
EDC
ENDLOOP
.word 40000000h
LDP
EDC
LDI
@EDC,AR0
LDI
15,RC
RPTB
ENDLOOP
LDI
*AR0,R0
; The program is located in 4000000Fh
;
;
;
;
;
;
;
Load repeat counter with 15
Execute block of code
The *AR0 read conflicts with
the instruction fetching
Then RC decrements to 0
If cache is enabled, RC decrements
to FFFF FFFFh
Program Flow Control
7-7
Repeat Modes
7.1.7
Nested Block Repeats
Block repeats (RPTB) can be nested. Since the registers RS, RE, RC, and
ST control the repeat-mode status, these registers must be saved and restored
in order to nest block repeats. For example, if you write an interrupt service routine
that requires the use of RPTB, it is possible that the interrupt associated with the
routine may occur during another block repeat. The interrupt service routine can
check the RM bit to determine whether the block repeat mode is active. If this RM
is set, the interrupt routine must save ST, RS, RE, and RC, in that order. The interrupt routine can then perform a block repeat. Before returning to the interrupted
routine, the interrupt routine must restore RC, RE, RS, and ST, in that order. If the
RM bit is not set, you do not need to save and restore these registers.
Note: Saving/Restoring Registers in Correct Order
The order in which the registers are saved/restored is important to guarantee
correct operation. The ST register must be restored last, after the RC, RE,
and RS registers. ST must be restored after restoring RC, because the RM
bit cannot be set to 1 if the RC register is 0 or −1. For this reason, if you
execute a POP ST instruction (with ST (RM bit) = 1) while RC = 0, the POP
instruction recovers all the ST register bits but not the RM bit that stays at 0
(repeat mode disabled). Also, RS and RE must be correctly set before you
activate the repeat mode.
The RPTS instruction can be used in a block repeat loop if the proper registers
are saved.
Because the program counter is modified at the end of the loop according to the
contents of registers RS, RE, and RC, no operation should attempt to modify
the repeat counter or the program-counter to a different value at the end of the
loop. It takes four cycles in the pipeline to save and restore these registers.
Hence, sometimes, it may be more economical to implement a nested loop by
the more traditional method of using a register as a counter and then using a
delayed branch or a decrement and branch-delayed instructions, rather than
using nested repeat blocks. Often implementing the outer loop as a counter and
the inner loop as RPTB instruction produces the fastest execution.
7-8
Delayed Branches
7.2 Delayed Branches
The ’C3x offers three main types of branching: standard, delayed, and conditional delayed.
Standard branches empty the pipeline before performing the branch, ensuring
correct management of the program counter and resulting in a ’C3x branch
taking four cycles. Included in this class are repeats, calls, returns, and traps.
Delayed branches on the ’C3x do not empty the pipeline, but rather execute
the next three instructions before the program counter is modified by the
branch. This results in a branch that requires only a single cycle, making the
speed of the delayed branch very close to that of the optimal block repeat
modes of the ’C3x. However, unlike block-repeat modes, delayed branches
may be used in situations other than looping. Every delayed branch has a standard branch counterpart that is used when a delayed branch cannot be used.
The delayed branches of the ’C3x are Bcond D, BRD, and DBcond D.
Conditional delayed branches use the conditions that exist at the end of the
instruction immediately preceding the delayed branch. They do not depend on
the instructions following the delayed branch. The condition flags are set by a
previous instruction only when the destination register is one of the extendedprecision registers (R0−R7) or when one of the compare instructions (CMPF,
CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed. Delayed branches
guarantee that the next three instructions will execute, regardless of other
pipeline conflicts.
When a delayed branch is fetched, it remains pending until the three subsequent
instructions are executed. The following instructions cannot be used in the three
instructions after a delayed branch (see Example 7−6):
Bcond
BcondD
BR
BRD
CALL
CALLcond
DBcond
DBcondD
IDLE
IDLE2
RETIcond
RETScond
RPTB
RPTS
TRAPcond
Delayed branches disable interrupts until the completion of the three instructions that follow the delayed branch regardless of whether the branch is or is
not performed.
Note: Incorrect Use of Delayed Branches
If delayed branches are used incorrectly, the PC is undefined.
Program Flow Control
7-9
Delayed Branches
Example 7−6. Incorrectly Placed Delayed Branches
B1:
B2:
BD
NOP
NOP
B
NOP
NOP
NOP
.
.
.
L1
L2
; This branch is incorrectly placed.
For faster execution, it might still be advantageous to use a delayed branch
followed by NOP instructions by trading increased program size for faster
speed. This is shown in Example 7−7 where a NOP takes the place of the third
unused instruction after the delayed branch.
Example 7−7. Delayed Branch Execution
*
TITLE DELAYED BRANCH EXECUTION
.
.
.
.
LDF* +AR1(5),R2 ; Load contents of memory to R2
BGED
SKIP
; If loaded number >=0, branch
; (delayed)
LDFN
R2,R1
; If loaded number <0, load it to R1
SUBF
3.0,R1
; Subtract 3 from R1
NOP
; Dummy operation to complete delayed
; branch
MPYF
1.5,R1
; Continue here if loaded number <0
.
.
.
SKIP
LDF
R1,R3
; Continue here if loaded number >=0
7-10
Calls, Traps, and Returns
7.3 Calls, Traps, and Returns
Calls and traps provide a means of executing a subroutine or function while
providing a return to the calling routine.
The CALL, CALLcond, and TRAPcond instructions store the value of the PC
on the stack before changing the PC’s contents. The RETScond or RETIcond
instructions use the value on the stack to return execution from traps and calls.
CALL is a 4-cycle instruction, while CALLcond and TRAPcond are 5-cycle
instruction.
- The CALL instruction places the next PC value on the stack and places
the src (source) operand into the PC. The src is a 24-bit immediate value.
Figure 7−1 shows CALL response timing.
- The CALLcond instruction is similar to the CALL instruction except for two
differences:
J
It executes only if a specific condition is true (the 20 conditions—
including unconditional—are listed in Table 13−12 on page 13-30).
J
The src is either a PC-relative displacement or is in register-addressing mode.
The condition flags are set by a previous instruction only when the destination
register is one of the extended-precision registers (R0−R7) or when one of
the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3)
is executed.
- The TRAPcond instruction also executes only if a specific condition is true
(same conditions as for the CALLcond instruction). When executing, the
following actions occur:
1) Interrupts are disabled with 0 written to bit GIE of the ST.
2) The next PC value is stored on the stack.
3) The specified vector is retrieved from the trap-vector table and is loaded
into the PC. The vector address corresponds to the trap number in the
instruction.
Using the RETIcond to return reenables interrupts by setting the bit field of
the status register.
- RETScond returns execution from any of the above three instructions by
popping the top of the stack to the PC. For RETScond to execute, the
specified condition must be true. The conditions are the same as for the
CALLcond instruction.
Program Flow Control
7-11
Calls, Traps, and Returns
- RETIcond returns from traps or calls like the RETScond, with the addition
that RETIcond also sets the GIE bit of the status register, which enables
all interrupts whose enabling bit is set to 1. The conditions for RETIcond
are the same as for the CALLcond instruction.
Functionally, calls and traps accomplish the same task — a subfunction is
called and executed, and control is then returned to the calling function. Traps
offer two advantages over calls:
- Interrupts are automatically disabled when a trap is executed. This allows
critical code to execute without risk of being interrupted. Traps are generally
terminated with a RETIcond instruction to reenable interrupts.
- You can use traps to indirectly call functions. This is particularly benefi-
cial when a kernel of code contains the basic subfunctions to be used by
applications. In this case, you can modify the functions in the kernel and
relocate them without recompiling each application.
Figure 7−1. CALL Response Timing
Fetch CALL
Decode CALL
Read CALL
Execute CALL
(store PC
on stack)
Fetch first
subroutine
instruction
Vector address
First instruction
address
H3
H1
ADDR
Data
7-12
PC
Inst 1
Interlocked Operations
7.4 Interlocked Operations
One of the most common parallel processing configurations is the sharing of
global memory by multiple processors. For multiple processors to access this
global memory and share data in a coherent manner, some sort of arbitration
or handshaking is necessary. This requirement for arbitration is the purpose
of the ’C3x interlocked operations.
The ’C3x provides a flexible means of multiprocessor support with five instructions, referred to as interlocked operations. Through the use of external signals,
these instructions provide powerful synchronization mechanisms. They also
guarantee the integrity of the communication and result in a high-speed operation. The interlocked-operation instruction group is listed in Table 7−2.
Table 7−2. Interlocked Operations
Mnemonic
Description
Operation
LDFI
Load floating-point value into a register,
interlocked
Signal interlocked
src → dst
LDII
Load integer into a register, interlocked
Signal interlocked
src → dst
SIGI
Signal, interlocked
Signal interlocked
Clear interlock
STFI
Store floating-point value to memory,
interlocked
Clear interlock
src → dst
STII
Store integer to memory, interlocked
Clear interlock
src → dst
The interlocked operations use the two external flag pins, XF0 and XF1. XF0
must be configured as an output pin; XF1 is an input pin. When configured in
this manner:
- XF0 signals an interlock operation request
- XF1 acts as an acknowledge signal for the requested interlocked operation.
In this mode, XF0 and XF1 are treated as active-low signals.
The external timing for the interlocked loads and stores is the same as for
standard loads and stores. The interlocked loads and stores may be extended
like standard accesses by using the appropriate ready signal (RDYint or
XRDYint). (RDYint and XRDYint are a combination of external ready input and
software wait states. see Chapter 9, External Memory Interface, for more
information on ready generation.)
Program Flow Control
7-13
Interlocked Operations
The LDFI and LDII instructions perform the following actions:
1) Simultaneously set XF0 to 0 and begin a read cycle. The timing of XF0 is
similar to that of the address bus during a read cycle.
2) Execute an LDF or LDI instruction and extend the read cycle until XF1
is set to 0 and a ready (RDYint or XRDYint) is signaled. The read cycle
completes one H1/H3 cycle after the XF1 signal is detected.
3) Leave XF0 set to 0 and end the read cycle.
Note: Timing Diagrams for LDFI and LDII
The timing diagrams for LDFI and LDII shown on the data sheets depict a 0
wait state read cycle. Since the read cycle is extended for one H1/H3 cycle
after XF1 signal is detected, the data sheets show the XF1 signal sampled
one H1/H3 cycle before setting the XF0 signal low.
For the sequence of steps described here, the read cycle finishes one H1/H3
cycle after the XF1 signal is detected.
The read/write operation is identical to any other read/write cycle except for
the special use of XF0 and XF1. The src operand for LDFI and LDII is always
a direct or indirect memory address. XF0 is set to 0 only if the src is located
off chip; that is, STRB, STRB0, STRB1, MSTRB, or IOSTRB is active, or the
src is one of the on-chip peripherals. If on-chip memory is accessed, then XF0
is not asserted, and the operation executes as an LDF or LDI from internal
memory.
The STFI and STII instructions perform the following operations:
1) Simultaneously set XF0 to 1 and begin a write cycle. The timing of XF0 is
similar to that of the address bus during a write cycle.
2) Execute an STF or STI instruction and extend the write cycle until a ready
(RDYint or XRDYint) is signaled.
As in the case for LDFI and LDII, the dst of STFI and STII affects XF0. If dst
is located off chip (STRB, STRB0, STRB1, MSTRB, or IOSTRB is active) or
the dst is one of the on-chip peripherals, XF0 is set to 1. If on-chip memory is
accessed, then XF0 is not asserted and the operation executes as an STF or
STI to internal memory.
The SIGI instruction functions as follows:
1) Sets XF0 to 0
2) Idles until one H1/H3 cycle after XF1 is set to 0
3) Sets XF0 to 1 and ends the operation
7-14
Interlocked Operations
Note: Timing Diagrams for SIGI
The timing diagrams for SIGI shown in the data sheets depict a zero wait
state condition. Since the device idles until one cycle after XF1 is signaled,
the data sheets show the XF1 signal sampled one H1/H3 cycle before setting
the XF0 signal low.
For the sequence of steps described here, the device idles past one H1/H3
cycle after the XF1 signal is detected.
7.4.1
Interrupting Interlocked Operations
While the LDFI, LDII, and SIGI instructions are waiting for XF1 to be set to 0,
you can interrupt them. LDFI and LDII require a ready signal (RDYint or
XRDYint) in order to be interrupted. Because interrupts are taken on bus-cycle
boundaries (see Section 7.6 on page 7-26), an interrupt may be taken any time
after a valid ready. If the interrupted LDFI or LDII consists of a multicycle load,
the load stops and an unknown value might be loaded into the register.
Interrupting an LDFI, LDII, or SIGI instruction allows you to implement
protection mechanisms against deadlock conditions by interrupting an
interlocked load that has taken too long. Upon return from the interrupt, the
next instruction is executed. The STFI and STII instructions are not
interruptible. Since the STFI and STII instructions complete when ready is
signaled, the delay until an interrupt can occur is the same as for any other
instruction.
7.4.2
Using Interlocked Operations
Note: Incorrect Use of Interlock Instructions
Do not place an STFI or STII back-to-back with an LDFI, LDII, or SIGI instruction
as follows:
STFI
LDFI
R1,*AR1 ;
*AR1, R2 ; Incorrect use of interlock instructions
See Section 7.4.3, Pipeline Effects of Interlocked Instructions, on page 7-19.
Interlocked operations can be used to implement a busy-waiting loop, to manipulate a multiprocessor counter, to implement a simple semaphore mechanism, or
to perform synchronization between two ’C3x devices. The following examples
illustrate the usefulness of the interlocked operations instructions.
Program Flow Control
7-15
Interlocked Operations
Example 7−8 shows the implementation of a busy-waiting loop. If location
LOCK is the interlock for a critical section of code, and a nonzero means the
lock is busy, the algorithm for a busy-waiting loop can be used as shown.
Example 7−8. Busy-Waiting Loop
L1:
LDI
LDII
1,R0
@LOCK,R1
STII
R0,@LOCK
BNZ
L1
;
;
;
;
;
;
Put 1 into R0
Interlocked operation begun
Contents of LOCK → R1
Put R0 (= 1) into LOCK, XF0 = 1
Interlocked operation ended
Keep trying until LOCK = 0
Example 7−9 shows how a location COUNT may contain a count of the number
of times a particular operation must be performed. This operation may be performed by any processor in the system. If the count is 0, the processor waits
until it is nonzero before beginning processing. The example also shows the
algorithm for modifying COUNT correctly.
Example 7−9. Multiprocessor Counter Manipulation
CT:
OR
4,IOF
LDII
@COUNT,R1
BZ CT
SUBI
STII
1,R1
R1,@COUNT
;
;
;
;
;
;
;
;
XF0 = 1
Interlocked operation ended
Interlocked operation begun
Contents of COUNT → R1
If COUNT = 0, keep trying
Decrement R1 (= COUNT)
Update COUNT, XF0 = 1
Interlocked operation ended
Figure 7−2 illustrates multiple ’C3x devices sharing global memory and using the
interlocked instructions as in Example 7−10, Example 7−11, and Example 7−12.
7-16
Interlocked Operations
Figure 7−2. Multiple TMS320C3xs Sharing Global Memory
CTRL
DATA
ADDR
Global memory
Arbitration logic
Lock, count, or S
XF0
XF1
’C3x #1
(X)A
(X)D
CTRL
Local
memory
(X)A
(X)D
CTRL
XF0
XF1
’C3x #2
Local
memory
Sometimes it may be necessary for several processors to access some
shared data or other common resources. The portion of code that must access
the shared data is called a critical section.
To ease the programming of critical sections, semaphores may be used.
Semaphores are variables that can take only nonnegative integer values. Two
primitive, indivisible operations are defined on semaphores (with S being a
semaphore):
V(S):
P(S):
S + 1 → S
P: if (S == 0), go to P
else S − 1 → S
Indivisibility of V(S) and P(S) means that when these processes access and
modify the semaphore S; they are the only processes doing so.
To enter a critical section, a P operation is performed on a common semaphore,
say S (S is initialized to 1). The first processor performing P(S) will be able to enter
its critical section. All other processors are blocked because S has become 0.
After leaving its critical section, the processor performs a V(S), thus allowing
another processor to execute P(S) successfully.
Program Flow Control
7-17
Interlocked Operations
The ’C3x code for V(S) is shown in Example 7−10; code for P(S) is shown in
Example 7−11. Compare the code in Example 7−11 to the code in Example 7−9,
which does not use semaphores.
Example 7−10. Implementation of V(S)
V: LDII
@S,R0
ADDI
STII
1,R0
R0,@S
;
;
;
;
Interlocked read of S begins (XFO = 0)
Contents of S → R0
Increment R0 (= S)
Update S, end interlock (XF0 = 0)
Example 7−11. Implementation of P(S)
P: OR
NOP
LDII
BZ
SUBI
STII
4,IOF ;
;
;
;
@S,R0 ;
;
P
;
1,R0
;
R0,@S ;
End interlock (XF0 = 1)
Avoid potential pipeline conflicts when
executing out of cache, on-chip memory
or zero wait-state memory
Interlocked read of S begins
Contents of S → R0
If S = 0, go to P and try again
Decrement R0 (= S)
Update S, end interlock (XF0 = 1)
The SIGI operation can synchronize, at an instruction level, multiple ’C3xs.
Consider two processors connected as shown in Figure 7−3. The code for the
two processors is shown in Example 7−12.
Figure 7−3. Zero-Logic Interconnect of TMS320C3x Devices
’C3x #1
’C3x #2
XF0
XF1
XF1
XF0
Processor #1 runs until it executes the SIGI. It then waits until processor #2
executes a SIGI. At this point, the two processors are synchronized and continue
execution.
7-18
Interlocked Operations
Example 7−12. Code to Synchronize Two TMS320C3x Devices at the Software Level
Time
Code for ’C3x #1
Code for ’C3x #2
O
SIGI
(WAIT)
Synchronization occurs
SIGI
N
7.4.3
Pipeline Effects of Interlocked Instructions
Before performing an interlocked instruction, the XF0 pin must be configured as
an output pin and the XF1 pin must be configured as an input pin through the
IOF register (see subsection 3.1.10, I/O Flag Register (IOF), on page 3-16).
After the XF0 and XF1 pins are configured, no interlocked instruction can occur
in the following two instructions.
Program Flow Control
7-19
Interlocked Operations
Example 7−13. Pipeline Delay of XF Pin Configuration
Pipeline Operation
PC
n
XF1 sampled
Decode
Fetch
Read
Execute
XF0 set as an
output pin and
XF1 set as an
input pin
LDI 2h, IOF
n+1
NOP
LDI 2h, IOF
n+2
NOP
NOP
LDI 2h, IOF
n+3
LDII *AR1, R1
NOP
NOP
LDI 2h, IOF
LDII *AR1, R1
NOP
NOP
LDII *AR1, R1
NOP
n+4
n+5
n+6
LDII *AR1, R1
XF0 driven low
and XF1 sampled
STFI and STII instructions drive the XF0 pin high during its execution phase.
LDFI, LDII, and SIGI instructions sample the XF1 pin during its decode phase
while driving the XF0 pin low during its read phase. Therefore, do not use an
LDFI, LDII, or SIGI instruction immediately after an STFI or STII instruction
(see Example 7−14).
Example 7−14. Incorrect Use of Interlocked Instructions
Pipeline Operation
PC
XF1 pin
sampled
n
STFI R1, *AR1
n+1
LDFI *AR1, R2
n+2
Decode
Fetch
LDFI *AR1, R2
7-20
STFI R1, *AR1
LDFI *AR1, R2
XF0 pin
driven low
Execute
XF0 pin
driven high
STFI R1, *AR1
n+3
n+4
Read
STFI R1, *AR1
LDFI *AR1, R2
Reset Operation
7.5 Reset Operation
The ’C3x supports a nonmaskable external reset signal (RESET), which is
used to perform system reset. This section discusses the reset operation.
At start-up, the state of the ’C3x processor is undefined. You can use the RESET
signal to place the processor in a known state. This signal must be asserted low
for ten or more H1 clock cycles to guarantee a system reset. H1 is an output
clock signal generated by the ’C3x. (Check the datasheet for your device for the
specific signal descriptions and electrical characteristics.)
Reset affects the other pins on the device in either a synchronous or asynchronous manner. The synchronous reset is gated by the ’C3x’s internal clocks. The
asynchronous reset directly affects the pins and is faster than the synchronous
reset. Table 7−3 shows the state of the ’C3x’s pins after RESET = 0. Each pin is
described according to whether the pin is reset synchronously or asynchronously.
Table 7−3. TMS320C3x Pin Operation at Reset
Device
Signal
Operation at Reset
‘C30
‘C31/
VC33
‘C32
Primary Bus Interface Signals
D31 −D0
Synchronous reset; placed in high-impedance state
n
n
n
A23 −A0
Synchronous reset; placed in high-impedance state
n
n
n
R/W
Synchronous reset; deasserted by going to a high level
n
n
n
IOSTRB
Synchronous reset; deasserted by going to a high level
n
STRB0_B3/A−1
Synchronous reset; deasserted by going to a high level
n
STRB0_B2/A−2
Synchronous reset; deasserted by going to a high level
n
STRB0_B1
Synchronous reset; deasserted by going to a high level
n
STRB0_B0
Synchronous reset; deasserted by going to a high level
n
STRB1_B3/A−1
Synchronous reset; deasserted by going to a high level
n
STRB1_B2/A−2
Synchronous reset; deasserted by going to a high level
n
STRB1_B1
Synchronous reset; deasserted by going to a high level
n
STRB1_B0
Synchronous reset; deasserted by going to a high level
n
STRB
Synchronous reset; deasserted by going to a high level
n
n
RDY
Reset has no effect
n
n
n
HOLD
Reset has no effect
n
n
n
n
Program Flow Control
7-21
Reset Operation
Table 7−3. TMS320C3x Pin Operation at Reset (Continued)
Device
Signal
Operation at Reset
‘C30
‘C31/
VC33
‘C32
HOLDA
Reset has no effect
n
n
n
PRGW
Reset has no effect
n
Expansion Bus Interface
XD31 −XD0
Synchronous reset; placed in high-impedance state
n
XA12 −XA0
Synchronous reset; placed in high-impedance state
n
XR/W
Synchronous reset; placed in high-impedance state
n
MSTRB
Synchronous reset; deasserted by going to a high level
n
XRDY
Reset has no effect
n
Control Signals
RESET
Reset input pin
n
n
n
INT3 −INT0
Reset has no effect
n
n
n
IACK
Synchronous reset; deasserted by going to a high level
n
n
n
MC/MP or MCBL/MP
Reset has no effect
n
n
n
SHZ
Reset has no effect
n
n
n
XF1−XF0
Asynchronous reset; placed in high-impedance state
n
n
n
Serial Port 0 Signals
CLKX0
Asynchronous reset; placed in high-impedance state
n
n
n
DX0
Asynchronous reset; placed in high-impedance state
n
n
n
FSX0
Asynchronous reset; placed in high-impedance state
n
n
n
CLKR0
Asynchronous reset; placed in high-impedance state
n
n
n
DR0
Asynchronous reset; placed in high-impedance state
n
n
n
FSR0
Asynchronous reset; placed in high-impedance state
n
n
n
Serial Port 1 Signals
CLKX1
Asynchronous reset; placed in high-impedance state
n
DX1
Asynchronous reset; placed in high-impedance state
n
FSX1
Asynchronous reset; placed in high-impedance state
n
7-22
Reset Operation
Table 7−3. TMS320C3x Pin Operation at Reset (Continued)
Device
‘C31/
VC33
‘C32
n
n
n
n
n
n
n
n
n
n
Signal
Operation at Reset
‘C30
CLKR1
Asynchronous reset; placed in high-impedance state
n
DR1
Asynchronous reset; placed in high-impedance state
n
FSR1
Asynchronous reset; placed in high-impedance state
n
Timer0 Signal
TCLK0
Asynchronous reset; placed in high-impedance state
Timer1 Signal
TCLK1
Asynchronous reset; placed in high-impedance state
Supply and Oscillator Signals
VDD
Reset has no effect
n
IODVDD
Reset has no effect
n
ADVDD
Reset has no effect
n
PDVDD
Reset has no effect
n
DDVDD
Reset has no effect
n
MDVDD
Reset has no effect
n
VSS
Reset has no effect
n
DVSS
Reset has no effect
n
n
CVSS
Reset has no effect
n
n
IVSS
Reset has no effect
n
n
VBBP
Reset has no effect
n
n
VSUBS
Reset has no effect
n
n
X1
Reset has no effect
n
n
X2/CLKIN
Reset has no effect
n
n
n
H1
Synchronous reset; will go to its initial state when RESET
makes a 1 to 0 transition
n
n
n
H3
Synchronous reset; will go to its initial state when RESET
makes a 1 to 0 transition
n
n
n
Program Flow Control
n
7-23
Reset Operation
Table 7−3. TMS320C3x Pin Operation at Reset (Continued)
Device
Signal
Operation at Reset
‘C30
‘C31/
VC33
‘C32
Emulation, Test, and Reserved
EMU0
Undefined
n
n
n
EMU1
Undefined
n
n
n
EMU2
Undefined
n
n
n
EMU3
Undefined
n
n
n
EMU4
Undefined
n
EMU5
Undefined
n
EMU6
Undefined
n
RSV0
Undefined
n
RSV1
Undefined
n
RSV2
Undefined
n
RSV3
Undefined
n
RSV4
Undefined
n
RSV5
Undefined
n
RSV6
Undefined
n
RSV7
Undefined
n
RSV8
Undefined
n
RSV9
Undefined
n
RSV10
Undefined
n
7-24
Reset Operation
At system reset, the following additional operations are performed:
- The peripherals are reset. This is a synchronous operation. Peripheral reset
is described in Chapter 12, Peripherals.
- The external bus control registers are reset. The reset values of the control
registers are described in Chapter 9, ’C30 and ’C31/VC33 ExternalMemory Interface.
- The following CPU registers are loaded with 0:
J
ST (CPU status register), except in the ’C32, the PRGW status bit field
is loaded with the status of the PRGW pin
J IE (CPU/DMA interrupt-enable flags)
J IF (CPU interrupt flags)
J IOF (I/O flags)
- The reset vector is read from memory location 0h. On the ’C32, this is a
32-bit data read. Once read, this value is loaded into the PC. This vector
contains the start address of the system reset routine.
- At this point, code location is dictated by the PC.
Multiple ’C3x devices, driven by the same system clock, may be reset and
synchronized. When the 1 to 0 transition of RESET occurs, the processor is
placed on a well-defined internal phase, and all of the ’C3x devices come up
on the same internal phase and all internal memory locations.
Unless otherwise specified, all registers are undefined after reset.
Program Flow Control
7-25
Interrupts
7.6 Interrupts
The ’C3x supports multiple internal and external interrupts, which can be used for
a variety of applications. Internal interrupts are generated by the DMA controller,
timers, and serial ports. Four external maskable interrupt pins include INT0 −
INT3. Interrupts are automatically prioritized allowing interrupts to occur simultaneously and serviced in a predefined order. This section discusses the operation
of these interrupts.
Additional information regarding internal interrupts can be found in Section 12.3.7, DMA and Interrupts, on page 12-65; Section 12.1.8, Timer Interrupts on page 12-13; and Section 12.2.11, Serial-Port Interrupt Sources, on
page 12-34.
7.6.1
TMS320C30 and TMS320C31/VC33 Interrupt Vector Table
Table 7−4 and Table 7−5 contain the interrupt vectors. In the microprocessor
mode of the ’C30 and the ’C31/VC33 (Table 7−4) and the microcomputer
mode of the ’C31/VC33 (Table 7−5), the interrupt vectors contain the addresses of interrupt service routines that should start executing when an interrupt
occurs. On the other hand, in the microcomputer/boot-loader mode of the
’C31/VC33, the interrupt vector contains a branch instruction to the start of the
interrupt service routine.
7-26
Interrupts
Table 7−4. Reset, Interrupt, and Trap-Vector Locations for the TMS320C30/
TMS320C31/VC33 Microprocessor Mode
Address
Name
Function
00h
RESET
External reset signal input
01h
INT0
External interrupt on the INT0 pin
02h
INT1
External interrupt on the INT1 pin
03h
INT2
External interrupt on the INT2 pin
04h
INT3
External interrupt on the INT3 pin
05h
XINT0
Internal interrupt generated when serial port
0 transmit buffer is empty
06h
RINT0
Internal interrupt generated when serial port
0 transmit buffer is full
07h
XINT1†
Internal interrupt generated when serial port
1 transmit buffer is empty
08h
RINT1†
Internal interrupt generated when serial port
1 transmit buffer is full
09h
TINT0
Internal interrupt generated by timer0
0Ah
TINT1
Internal interrupt generated by timer1
0Bh
DINT
Internal interrupt generated by DMA controller
0Ch
Reserved
•
•
•
•
•
•
1Fh
Reserved
20h
TRAP 0
Internal interrupt generated by TRAP 0
instruction
•
•
•
3Bh
TRAP 27
3Ch
TRAP 28 (reserved)
3Dh
TRAP 29 (reserved)
3Eh
TRAP 30 (reserved)
3Fh
TRAP 31 (reserved)
Internal interrupt generated by TRAP 27
instruction
† Reserved on ’C31/VC33
Program Flow Control
7-27
Interrupts
Table 7−5. Reset, Interrupt, and Trap-Branch Locations for the TMS320C31/VC33
Microcomputer Boot Mode
7-28
Address
Name
Function
809FC1
INT0
External reset signal input
809FC2
INT1
External interrupt on the INT0 pin
809FC3
INT2
External interrupt on the INT1 pin
809FC4
INT3
External interrupt on the INT2 pin
809FC5
XINT0
External interrupt on the INT3 pin
809FC6
RINT0
Internal interrupt generated when
serial port 0 transmit buffer is
empty
809FC7
XINT1 (Reserved)
809FC8
RINT1 (Reserved)
809FC9
TINT0
Internal interrupt generated by
timer0
809FCA
TINT1
Internal interrupt generated by
timer1
809FCB
DINT
Internal interrupt generated by DMA
controller
809FCC−809FDF
Reserved
809FE0
TRAP0
Internal interrupt generated by
TRAP 0 instruction
809FE1
TRAP1
Internal interrupt generated by
TRAP 1 instruction
•
•
•
•
•
•
809FFB
TRAP27
809FFC−809FFF
Reserved
Internal interrupt generated by
TRAP 27 instruction
Interrupts
7.6.2
TMS320C32 Interrupt Vector Table
Similarly to the rest of the ’C3x device family, the ’C32’s reset vector location
remains at address 0. On the other hand, the interrupt and trap vectors are
relocatable. This is achieved by a new bit field in the CPU interrupt flag register
called the interrupt-trap table pointer (ITTP), shown in Figure 3−11 on page
3-15. The ITTP bit field dictates the starting location (base) of the interrupttrap-vector table. This base address is formed by left-shifting the value of the
ITTP bit field by eight bits. This shifted value is called the effective base address
and is referenced as EA[ITTP], as shown in Figure 7−4. Therefore, the location
of an interrupt or trap vector is given by the addition of the effective base address
formed by the ITTP bit field (EA[ITTP]) and the offset of the interrupt or trap
vector in the interrupt-trap-vector table, as shown in Table 7−6. For example,
if the ITTP contains the value 100h, the serial-port transmit interrupt vector will
be located at 10005h. Note that the vectors stored in the interrupt-trap-vector
table are the addresses of the start of the respective interrupt and trap routines.
Furthermore, the interrupt-trap-vector table must lie on a 256-word boundary,
since the eight LSBs of the effective base address of the interrupt-trap-vector
table are 0.
Figure 7−4. Effective Base Address of the Interrupt-Trap-Vector Table
23
EA[ITTP] =
8
Bits 31 −16 of the CPU interrupt flag register
7
0
00000000
Program Flow Control
7-29
Interrupts
Table 7−6. Interrupt and Trap-Vector Locations for the TMS320C32
Address
Name
Function
EA[ITTP] + 00h
Reserved
EA[ITTP] + 01h
INT0
External interrupt on the INT0 pin
EA[ITTP] + 02h
INT1
External interrupt on the INT1 pin
EA[ITTP] + 03h
INT2
External interrupt on the INT2 pin
EA[ITTP] + 04h
INT3
External interrupt on the INT3 pin
EA[ITTP] + 05h
XINT0
Internal interrupt generated when serial port 0 transmit buffer
is empty
EA[ITTP] + 06h
RINT0
Internal interrupt generated when serial port 0 transmit buffer
is full
EA[ITTP] + 07h
Reserved
EA[ITTP] + 08h
Reserved
EA[ITTP] + 09h
TINT0
Internal interrupt generated by timer0
EA[ITTP] + 0Ah
TINT1
Internal interrupt generated by timer1
EA[ITTP] + 0Bh
DINT0
Internal interrupt generated by DMA channel 0
EA[ITTP] + 0Ch
DINT1
Internal interrupt generated by DMA channel 1
EA[ITTP] + 0Dh
Reserved
EA[ITTP] + 1Fh
Reserved
EA[ITTP] + 20h
TRAP 0
Internal interrupt generated by TRAP 0 instruction
•
•
•
EA[ITTP] + 3Bh
TRAP 27
EA[ITTP] + 3Ch
TRAP 28 (reserved)
EA[ITTP] + 3Dh
TRAP 29 (reserved)
EA[ITTP] + 3Eh
TRAP 30 (reserved)
EA[ITTP] + 3Fh
TRAP 31 (reserved)
7-30
Internal interrupt generated by TRAP 27 instruction
Interrupts
7.6.3
Interrupt Prioritization
When two interrupts occur in the same clock cycle or when two previously
received interrupts are waiting to be serviced, one interrupt is serviced before
the other. The CPU handles this prioritization by servicing the interrupt with the
least priority. The priority of interrupts is handled by the CPU according to the
interrupt vector table. Priority is set according to position in the table—those with
displacements closest to the base address of the table are higher in priority.
Table 7−7 shows the priorities assigned to the reset and interrupt vectors.
Table 7−7. Reset and Interrupt Vector Priorities
Reset or
Interrupt
Vector
Location
Priority
Function
RESET
0h
0
External reset signal input on the RESET pin
INT0
1h
1
External interrupt on the INT0 pin
INT1
2h
2
External interrupt on the INT1 pin
INT2
3h
3
External interrupt on the INT2 pin
INT3
4h
4
External interrupt on the INT3 pin
XINT0
5h
5
Internal interrupt generated when serial-port 0 transmit buffer is empty
RINT0
6h
6
Internal interrupt generated when serial-port 0 receive buffer is full
XINT1†
7h
7
Internal interrupt generated when serial-port 1 transmit buffer is empty
RINT1†
8h
8
Internal interrupt generated when serial-port 1 receive buffer is full
TINT0
9h
9
Internal interrupt generated by timer0
TINT1
0Ah
10
Internal interrupt generated by timer1
DINT/
DINT0
0Bh
11
Internal interrupt generated by DMA channel 0
DINT1‡
0Ch
12
Internal interrupt generated by DMA channel 1
† Reserved on ’C31/VC33 and ’C32
‡ Present on ’C32 only
Program Flow Control
7-31
Interrupts
7.6.4
CPU Interrupt Control Bits
Three CPU registers contain bits that control interrupt operation:
- Status (ST) register
The CPU global interrupt-enable bit (GIE) located in the CPU status register
(ST) controls all maskable CPU interrupts. When this bit is set to 1, the CPU
responds to an enabled interrupt. When this bit is cleared to 0, all CPU interrupts are disabled. see Section 3.1.7 on page 3-5 for more information.
- CPU/DMA interrupt-enable (IE) register
This register individually enables/disables CPU, DMA external, serial port,
and timer interrupts. See Section 3.1.8 on page 3-9 for more information.
- CPU interrupt flag (IF) register
This register contains interrupt flag bits that indicate the corresponding
interrupt is set. See Section 3.1.9 on page 3-11 for more information.
7.6.5
Interrupt Flag Register Behavior
When an external interrupt occurs, the corresponding bit of the IF register is set
to 1. When the CPU or DMA controller processes this interrupt, the corresponding
interrupt flag bit is cleared by the internal interrupt acknowledge signal. However,
for level-triggered interrupts, if INTn is still low when the interrupt acknowledge
signal occurs, the interrupt flag bit is cleared for only one cycle and then set again,
because INTn is still low. Depending on when the IF register is read, it is also
possible that this bit may be 0 even though INTn is 0. When the ’C3x is reset,
0 is written to the interrupt flag register, clearing all pending interrupts.
The interrupt flag register bits can be read from and written to under software
control. Writing a 1 to an IF register bit sets the associated interrupt flag to 1.
Similarly, writing a 0 resets the corresponding interrupt flag to 0. In this way, all
interrupts may be triggered and/or cleared through software. Since the interrupt
flags may be read, the interrupt pins may be polled in software when an interrupt-driven interface is not required.
Internal interrupts operate in a similar manner. In the IF register, the bit corresponding to an internal interrupt can be read from and written to through software.
Writing a 1 sets the interrupt latch; writing a 0 clears it. All internal interrupts are
one H1/H3 cycle in length. If any previous bit value of the IF register needs to be
preserved, a modification to IF register should be performed with logic operations
(AND, OR, etc.) directly to IF.
7-32
Interrupts
Figure 7−5. IF Register Modification
Correct
Incorrect
LDI @MASK, R0
LDI IF, R1
AND R0, IF
AND @MASK, R1
LDI R1, IF
Note: IF Register Load Priority
If a load of the IF register occurs simultaneously with a set or reset of a flag
by an interrupt pulse, the loading of the flag has higher priority and overwrites
the IF register value.
7.6.6
Interrupt Processing
The ’C3x allows the CPU and DMA coprocessor to respond to and process
interrupts in parallel. Figure 7−6 on page 7-34 shows interrupt processing
flow; for the exact sequence, see Table 7−8 on page 7-36.
For a CPU interrupt to occur, at least two conditions must be met:
- All interrupts must be enabled globally by setting the GIE bit to 0 in the status
register.
- The interrupt must be enabled by setting the corresponding bit in the
IF register.
In the CPU interrupt processing cycle (left side of Figure 7−6), the corresponding
interrupt flag in the IF register is cleared, and interrupts are globally disabled
(GIE = 0). The CPU completes all fetched instructions. The current PC is pushed
to the top of the stack. The interrupt vector is then fetched and loaded into the
PC, and the CPU starts executing the first instruction in the interrupt service
routine (ISR).
Program Flow Control
7-33
Interrupts
Figure 7−6. CPU Interrupt Processing
No
Is an enabled
interrupt set
?
Yes
If enabled,
interrupt is
a CPU interrupt
If enabled,
interrupt is
a DMA interrupt
Disable interrupts
GIE← 0
Clear interrupt flag
Clear interrupt flag
DMA proceeds according
to SYNC bits
PC → *(++SP)
DMA continues
Complete all fetched instructions
PC ← interrupt vector
CPU starts executing ISR routine
Note: CPU and DMA Interrupts
CPU interrupts are acknowledged (responded to by the CPU) on instruction
fetch boundaries only. If instruction fetches are halted because of pipeline
conflicts or execution of RPTS loops, CPU interrupts are not acknowledged
until the next instruction fetch.
7-34
Interrupts
If you wish to make the interrupt service routine interruptible, you can set the
GIE bit to 1 after entering the ISR.
The interrupt acknowledge (IACK) instruction can be used to signal externally that
an interrupt has been serviced. If external memory is specified in the operand,
IACK drives the IACK pin and performs a dummy read. The read is performed
from the address specified by the IACK instruction operand. IACK is typically
placed in the early portion of an ISR. However, depending on your application,
it may be better to place it at the end of the ISR or not at all.
Note the following:
- Interrupts are disabled during an RPTS and during a delayed branch (until
the three instructions following a delayed branch are completed). Interrupts
are held until after the branch.
- When an interrupt occurs, instructions currently in the decode and read
phases continue regular execution, unlike an instruction in the fetch
phase:
7.6.7
J
If the interrupt occurs in the first cycle of the fetch of an instruction, the
fetched instruction is discarded (not executed), and the address of
that instruction is pushed to the top of the system stack.
J
If the interrupt occurs after first cycle of the fetch (in the case of a multicycle fetch due to wait states), that instruction is executed, and the
address of the next instruction to be fetched is pushed to the top of
the system stack.
CPU Interrupt Latency
CPU interrupt latency, defined as the time from the acknowledgement of the
interrupt to the execution of the first ISR instruction, is at least eight cycles. This
is explained in Table 7−8 on page 7-36, where the interrupt is treated as an
instruction. It assumed that all of the instructions are single-cycle instructions.
Program Flow Control
7-35
Interrupts
Table 7−8. Interrupt Latency
Cycle
Description
Fetch
Decode
Read
Execute
1
Recognize interrupt in single-cycle fetched
(prog a + 1) instruction
prog a + 1
prog a
prog a−1
prog a−2
2
Clear GIE bit. Clear interrupt flag
—
interrupt
prog a
prog a−1
3
Read the interrupt vector table
—
—
interrupt
prog a
4
Store return address to stack
—
—
—
interrupt
5
Pipeline begins to fill with ISR instruction
isr1
—
—
—
6
Pipeline continues to fill with ISR instruction
isr2
isr1
—
—
7
Pipeline continues to fill with ISR instruction
isr3
isr2
isr1
—
8
Execute first instruction of interrupt service routine
isr4
isr3
isr2
isr1
7.6.8
External Interrupts
The four external maskable interrupt pins INT0−INT3 are enabled at the IF register (Section 3.1.9, CPU Interrupt Flag (IF) Register, on page 3-11) and are synchronized internally. They are sampled on the falling edge of H1 and passed
through a series of H1/H3 latches internally. These latches require the interrupt
signal to be held low for at least one H1/H3 clock cycle to be recognized by the
‘C3x. Once synchronized, the interrupt input sets the corresponding interrupt
flag register (IF) bit if the interrupt is active.
Figure 7−7 shows a functional diagram of the logic used to implement external
interrupt inputs.
7-36
Interrupts
Figure 7−7. Interrupt Logic Functional Diagram
Internal interrupt
set signal
EINTn(CPU)
GIE(CPU)
Interrupt
flag (n)
INTn
H1
DQ
D Q
D Q
CLK
CLK
CLK
H3
H1
Internal
interrupt
processor
Set Q
To
control
section
RESET
Internal interrupt
clear/acknowledge
signal
EINTn(DMA)
These interrupts are prioritized by the selection of one over the other if both
come on the same clock cycle (INT0 the highest, INT1 next, etc.). When an
interrupt is taken, the status register ST(GIE) bit is reset to 0, disabling any other
incoming interrupt. This prevents any other interrupt (INT0 − INT3) from assuming
program control until the ST(GIE) bit is set back to 1. On a return from an interrupt
routine, the RETI and RETIcond instructions set the ST(GIE) bit to 1.
On the ‘C30 and ‘C31/VC33, external interrupts are level triggered. On the
‘C32, external interrupts are edge or level triggered, depending on the INT
config bit field of the status register.
For an edge-triggered interrupt to be detected by the ’C32 the external pin
must transition from 1 to 0. And then, it needs to be held low for at least one
H1/H3 cycle (but it could be held low longer).
For a level-triggered interrupt to be detected by the ’C3x, the external pin must
be held low for between one and two cycles (1 low-pulse width 2). If the
interrupt is held low for more than two cycles, more than one interrupt might
be recognized. There is no need to provide an edge in this case.
Program Flow Control
7-37
DMA Interrupts
7.7 DMA Interrupts
Interrupts can also trigger DMA read and write operations. This is called
DMA synchronization. The DMA interrupt processing cycle is similar to that of
the CPU. After the pertinent interrupt flag is cleared, the DMA coprocessor
proceeds according to the status of the SYNC bits in the DMA coprocessor
global-control register.
If the interrupt in the CPU/DMA interrupt-enable (IE) register is enabled, the
interrupt controller automatically latches the interrupt and saves it for future
DMA use. The interrupt controller latches the interrupt, clears the flag in the IF
register, and informs the data that an interrupt has occurred. The DMA then proceeds with the transfer according to the previously configured CPU/DMA priority. Even if the DMA has not been started, the interrupt latch occurs, and the flag
is cleared, except when the start bits in the DMA control register have the reset
value 002 in START bits. DMA reset clears the interrupt internal latch.
7.7.1
DMA Interrupt Control Bits
Two registers contain bits used to control DMA interrupt operation:
- CPU/DMA interrupt-enable register (IE). All DMA interrupts are controlled
by the most significant 16 bits in the IE register and by the SYNC bits of
the DMA channel control registers (see Section 12.3.3, DMA Registers,
on page 12-51). The DMA interrupts are not dependent upon ST(GIE) and
are local to the DMA.
- The DMA channel control register. Each DMA coprocessor channel uses
a channel control register to determine its mode of operation. This register
is shown in Section 12.3.3.
The IE is broken into several subfields that determine which interrupts can be
used to control the synchronization for each DMA channel. For example, the bits
in each of these fields allow you to select whether a DMA channel is synchronized to a port, a timer, or an external interrupt pin. Note that the ’C32 has two
DMA channels while the ’C30 and ’C31/VC33 have a single DMA channel.
See Section 3.1.8, CPU/DMA Interrupt-Enable Register (IE), on page 3-9, for
a description of the IE.
7-38
DMA Interrupts
7.7.2
DMA Interrupt Processing
Figure 7−8 shows the general flow of interrupt processing by the DMA
coprocessor.
Figure 7−8. DMA Interrupt Processing
No
Is an enabled
interrupt set
?
Yes
If enabled in the IE
register, the interrupt Is
a DMA interrupt
Clear interrupt flag
DMA proceeds according
to DMA control register
SYNC bits
DMA continues
For more information about DMA interrupts, see Section 12.3.7, DMA Interrupts
on page 12-65.
Program Flow Control
7-39
DMA Interrupts
7.7.3
CPU/DMA Interaction
If the DMA is not using interrupts for synchronization of transfers, it is not
affected by the processing of the CPU interrupts. Detected interrupts are
responded to by the CPU and DMA on instruction fetch boundaries only.
Since instruction fetches are halted due to pipeline conflicts or when executing
instructions in an RPTS loop, interrupts are not responded to until instruction
fetching continues. It is therefore possible to interrupt the CPU and DMA simultaneously with the same or different interrupts and, in effect, synchronize their
activities. For example, it may be necessary to cause a high-priority DMA
transfer that avoids bus conflicts with the CPU (that is, a transfer that makes
the DMA higher priority than the CPU). This may be accomplished by using
an interrupt that causes the CPU to trap to an interrupt routine that contains
an IDLE instruction. Then, if the same interrupt is used to synchronize DMA
transfers, the DMA transfer counter can be used to generate an interrupt and
thus return control to the CPU following the DMA transfer.
Since the DMA and CPU share the same set of interrupt flags, the DMA may
clear an interrupt flag before the CPU can respond to it. For example, if the
CPU interrupts are disabled, the DMA can respond to interrupts and thus clear
the associated interrupt flags. Figure 7−9 shows the sequence of events in the
interrupt processing for both the CPU and DMA controllers.
Figure 7−9. Parallel CPU and DMA Interrupt Processing
Interrupt
CPU
No
Does
GIE=1 and
is the interrupt
enabled in the
IE register?
Yes
Process the CPU interrupt
as shown in Figure 7−6.
7-40
DMA coprocessor
No
Is the
interrupt enabled
in the IE
register?
Yes
Process the DMA interrupt
as shown in Figure 7−8.
DMA Interrupts
7.7.4
TMS320C3x Interrupt Considerations
Give careful consideration to ’C3x interrupts, especially if you make modifications
to the status register when the global interrupt-enable (GIE) bit is set. This can
result in the GIE bit being erroneously set or reset as described in the following
paragraphs.
The GIE bit field of the status register is set to 0 (reset) by an interrupt. If a load
of the status register occurs simultaneously with a CPU interrupt pulse trying
to reset GIE, GIE will be reset.
Also, resetting GIE by an interrupt or TRAP instruction can cause a processing
error if any code, following within two cycles of the interrupt recognition, attempts
to read or modify the status register. For example, if the status register is being
pushed onto the stack, it will be stored incorrectly if an interrupt was acknowledged
two cycles before the store instruction.
When an interrupt signal is recognized, the ’C3x continues executing the
instructions already in the read and decode phases in the pipeline. However,
because the interrupt is acknowledged, the GIE bit is reset to 0, and the store
instruction already in the pipeline will store the wrong status register value.
For example, if the program is like this:
...
NOP
interrupt recognized −−>LDI
MPYI
PUSH
...
POP
...
@V_ADDR,AR1
*AR1, R0
ST
ST
the PUSH ST instruction will save the ST contents in memory, which includes
GIE = 0. Since the device is expected to have GIE = 1, the POP ST instruction
will put the wrong status register value into the ST (see Table 7−9).
Program Flow Control
7-41
DMA Interrupts
Table 7−9. Pipeline Operation with PUSH ST
Cycle
Description
Fetch
Decode
Read
1
NOP
2
LDI
NOP
3
MPYI
LDI
NOP
Execute
4
Read location V_ADDR
PUSH
MPYI
LDI
NOP
5
Load AR1; recognize interrupt
−
PUSH
MPYI
LDI
6
Clear GIE bit; clear interrupt flag; read SP
Interrupt
PUSH
MPYI
7
Read interrupt vector table; save ST in stack
Interrupt
PUSH
8
Store return address on stack
Interrupt
The following example shows setting the GIE bit by a load instruction that is
immediately followed by an interrupt:
...
; GIE = 1
LDI 02000h, ST ; GIE = 0
interrupt recognized −−>MPYI *AR1, R0 ;
ADD
*AR0, R1
In this example, the load of the status register or interrupt-flag register overwrites
the reset of the GIE bit by the interrupt (see Table 7−10).
Table 7−10. Pipeline Operation with Load Followed by Interrupt
Cycle
Description
Fetch
1
Decode
Read
Execute
LDI
2
Interrupt recognized
3
Interrupt resets GIE bit, clears interrupt flag,
reads SP
4
GIE set by load instruction; interrupt vector table
read and ST saved on stack
5
Store return address on stack
6
Fetch first instruction of ISR with GIE = 1
−
LDI
interrupt
LDI
interrupt
LDI
interrupt
ISR
A similar situation may occur if the GIE bit = 1 and an instruction executes that
is intended to modify the other status bits and leave the GIE bit set. In the above
example, this erroneous setting would occur if the interrupt were recognized two
cycles before the POP ST instruction. In that case, the interrupt would clear the
GIE bit, but the execution of the POP instruction would set the GIE bit. Since the
interrupt has been recognized, the interrupt service routine will be entered with
interrupts enabled, rather than disabled as expected.
7-42
DMA Interrupts
One solution is to use an instruction that is uninterruptible such as RPTS as
follows to set the GIE:
RPTS
AND
0
2000h, ST
; Set GIE=1
Use the following to reset the GIE:
RPTS
AND
0
0DFFFh, ST
; Set GIE=0
Another alternative incorporates the following code fragment, which protects
against modifying or saving the status register by disabling interrupts through
the interrupt-enable register:
PUSH
LDI
NOP
NOP
AND
POP
; Save IE register • Added instructions to
; Clear IE register
avoid pipeline problems
• 2 NOPs or useful instructions
;
;
0DFFFh, ST ; Set GIE = 0
• Instruction that reads or
IE
;
writes to ST register.
;
Added instruction
;
to avoid pipeline
;
problems.
IE
0, IE
In summary, the next three instructions immediately following an instruction
that clears the GIE bit might be interrupted. Also, the next three instructions
immediately following an instruction that sets the GIE bit might not be interrupted
even if there is a pending interrupt (see Example 7−15). Similarly, the next three
instructions immediately following an instruction that clears an interrupt-enable
mask might be interrupted. Furthermore, the next three instructions immediately
following an instruction that sets an interrupt flag might be executed before the
interrupt occurs.
Example 7−15. Pending Interrupt
LDI
LDI
LDI
MPYI
ADDI
0h, ST
; set GIE = 0
1h, R1
2h, R2
*AR1, R0 ; interrupts still enabled
*AR1,R1
; interrupts disabled here
Program Flow Control
7-43
DMA Interrupts
7.7.5
TMS320C30 Interrupt Considerations
The ’C30 silicon revisions earlier than 4.0 have two unique exceptions to the
interrupt operation. This does not apply to ’C30 silicon revision 4.0 or greater,
any ’C31/VC33 silicon, or any ’C32 silicon.
On ’C30 silicon revisions earlier than 4.0:
- The status register global interrupt-enable (GIE) bit may be erroneously
reset to 0 (disabled setting) if all of the following conditions are true:
J
A conditional trap instruction (TRAPcond) has been fetched
J
The condition for the trap is false.
J
A pipeline conflict has occurred, resulting in a delay in the decode or
read phase of the instruction.
During the decode phase of a conditional trap, interrupts are temporarily
disabled to ensure that the trap executes before a subsequent interrupt. If a
pipeline conflict occurs and causes a delay in execution of the conditional
trap, the interrupt disabled condition may become the last known condition of
the GIE bit. If the trap condition is false, interrupts are permanently disabled
until the GIE bit is intentionally set. The condition is not present when the trap
condition is true, because normal operation of the instruction causes the GIE
to be reset, and standard coding practice sets the GIE to 1 before the trap
routine is exited. Several instruction sequences that cause pipeline conflicts
have been found:
J
LDI
TRAPcond
mem,SP
n
J
LDI
NOP
TRAPcond
mem,SP
J
STI
TRAPcond
SP,mem
n
J
STI
LDI
||LDI
TRAPcond
Rx,*ARy
*ARx,Ry
*ARz,Rw
n
n
Other similar conditions may also cause a delay in the execution. The
following solution is recommended to avoid or rectify the problem:
7-44
DMA Interrupts
Insert two NOP instructions immediately before the TRAPcond instruction.
One NOP is insufficient in some cases, as illustrated in the second bulleted
item, above. This eliminates the opportunity for any pipeline conflicts in the
immediately preceding instructions and enables the conditional trap
instruction to execute without delays.
- Asynchronous accesses to the interrupt flag register (IF) can cause the
’C30 silicon revision prior to 4.0 to fail to recognize and service an interrupt. This may occur when an interrupt is generated and is ready to be
latched into the IF register on the same cycle that the IF is being written
to by the CPU. Note that logic operations (AND, OR, XOR) may write to
the IF register.
The logic of ’C30 silicon revision earlier than 4.0 currently gives the CPU
write priority; consequently, the asserted interrupt might be lost. This is
true if the asserted interrupt was generated internally (for example, a direct
memory access (DMA) interrupt). This situation arises as a result of a decision to poll certain interrupts or a desire to clear pending interrupts due to a
long pulse width. In the case of a long pulse width, the interrupt may be
generated after the CPU responds to the interrupt and attempts to automatically clear it by the interrupt vector process.
The recommended solution is to avoid using the interrupt polling technique,
and to design the external interrupt inputs to have pulse widths between
1 and 2 instruction cycles. The alternative to strict polling is to periodically
enable and disable the interrupts that would be polled, allowing the normal
interrupt vectoring to take place; this automatically clears the interrupt flag
without affecting other interrupts. If you must clear a pending interrupt, you
should use a memory location to indicate that the interrupt is invalid. The
interrupt service routine can read that location, clear it (if the pending interrupt is invalid), and return immediately. The following code fragments
show how to handle a dummy interrupt due to a long interrupt pulse:
Program Flow Control
7-45
DMA Interrupts
ISR_n:
PUSH
PUSH
PUSH
LDI
LDI
BNN
STI
POP
POP
POP
RETI
ISR_n_START: .
.
.
LDI
AND
BNZ
LDI
LDI
STI
ISR_n_END:
POP
POP
POP
RETI
7-46
ST
DP
R0
0, DP
@DUMMY_INT, R0
ISR_n_START
DP, @DUMMY_INT
R0
DP
ST
INT_Fn, R0
IF, R0
ISR_n_END
0, DP
0FFFFh, R0
R0, @DUMMY_INT
R0
DP
ST
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Save registers
Clear Data-page Pointer
If DUMMY_INT is 0 or positive,
go to ISR_n_START
Set DUMMY_INT = 0
Housekeeping, return from interrupt
Normal interrupt service routine
Code goes here
If ones in IF reg match
INT_Fn, exit ISR
Otherwise clear
DP and set
DUMMY_INT negative & exit
;
; Exit ISR
;
;
Traps
7.8 Traps
A trap is the equivalent of a software-triggered interrupt. In the ’C3x, traps and
interrupts are treated identically, except in the way in which they are triggered.
7.8.1
Initialization of Traps and Interrupts
Traps and interrupts are triggered differently in the ’C3x:
- Traps are always triggered by a software mechanism, by the TRAPcond
(conditional trap) instructions.
- Interrupts are always triggered by hardware events (for example, by exter-
nal interrupts, DMA interrupts, or serial-port interrupts).
The GIE bit in the ST register and the mask bits in the IE do not apply to traps.
7.8.2
Operation of Traps
Figure 7−10 shows the general flow of traps which is similar to interrupts.
Figure 7−10. Flow of Traps
Trap executed
(TRAPcond)
(1)
(2)
0
GIE
Trap or interrupt service routine
Return executed
(RETIcond)
(3)
1
GIE
Program Flow Control
7-47
Traps
The RETIcond instruction manipulates the status flags as shown in block (3)
in Figure 7−10. RETIcond provides a return from a trap or interrupt.
The ’C3x supports 32 different traps. When a TRAPcond n instruction is
executed, the ’C3x jumps to the address stored in the memory location pointed
to by the corresponding trap-vector table pointer. The location of the trap-vector
table is shown in Table 7−4 on page 7-27 (’C30/’C31/VC33 microprocessor
mode), Table 7−5 (’C31/VC33 microcomputer boot mode) on page 7-28, and
Table 7−6 on page 7-30 for the ’C32.
7-48
Power Management Modes
7.9 Power Management Modes
The following ’C3x devices have been enhanced by the addition of two powerdown modes: IDLE2 and LOPOWER:
-
7.9.1
’C30 silicon version 7.0 or greater
’LC31
’C31 silicon revision 5.0 or greater
’C32
’VC33
IDLE2 Power-Down Mode
The H1 instruction clock is held high until one of the four external interrupts is
asserted. In IDLE2 mode, the ’C3x devices supporting these modes behave as
follows:
- No instructions are executed.
- The CPU, peripherals, and internal memory retain their previous states.
- The external bus output pins are idle:
J
The address lines remain in their previous states.
J
The data lines are in the high-impedance state.
J
The output control signals are in their inactive state.
J
If a multicycle read or write does not preceed the IDLE2 opcode, that
access will be forzen onto the bus until IDLE2 is exited. This can be
advantageous for low power applications since the bus is frozen in an
active state. That is, the device pins are not floating, and therefore do
not require pullup or pulldowns.
- When the device is in the functional (nonemulation) mode, the clocks stop
with H1 high and H3 low (see Figure 7−11).
- The devices remain in IDLE2 until one of the four external interrupts
(INT3−INT0) is asserted for at least one H1 cycle. When one of the four
interrupts is asserted, the clocks start after a delay of one H1 cycle. When
the clocks restart, they may be in the opposite phase (that is, H1 may be
high if H3 was high before the clocks were stopped; H3 may be low if H1
was previously low). The H1 and H3 clocks remain 180 degrees out of
phase with each other (see Figure 7−12).
- During IDLE2 operations, the CPU recognizes one of the four external
interrupts if it is asserted for more than one H1 cycle. To avoid generating
Program Flow Control
7-49
Power Management Modes
multiple false interrupts in level-triggered mode, the interrupt must be
asserted for fewer than three H1 cycles.
- The interrupt service routine (ISR) must have been set up before placing
the device in IDLE2 mode, because the instruction following the IDLE2
instruction is not executed until the RETI (return from interrupt) instruction
is executed.
- When the device is in emulation mode, the H1 and H3 clocks continue to
run normally and the CPU operates as if an IDLE instruction was
executed. The clocks continue to run for correct operation of the emulator.
Delayed Branch
For correct device operation, the three instructions following a
delayed branch should not include either IDLE or IDLE2 instructions.
Figure 7−11.IDLE2 Timing
CLKIN
Idle 2 execution
H3
H1
ADDR
Data
7-50
Power Management Modes
Figure 7−12. Interrupt Response Timing After IDLE2 Operation
Clocks driven
Fetch first
instruction of
service routing
Interrupt vector
read
CLKIN
H3
H1
INT3 to
INT0
INT3 to
INT0 Flag
ADDR
Vector address
1st address
Data
7.9.2
LOPOWER
In the LOPOWER (low-power) mode, the CPU continues to execute instructions,
and the DMA can continue to perform transfers, but at a reduced clock rate of
CLKIN frequency divided by 16.
A ’C31/VC33 with a CLKIN frequency of 32 MHz performs identically to a
2 MHz ’C31/VC33 with an instruction cycle time of 1,000 ns.
During the read phase of the . . .
The ’C31/VC33 and ’C32 . . .
LOPOWER instruction (Figure 7−13)
Slow to 1/16 of full-speed operation.
MAXSPEED instruction (Figure 7−14)
Resume full-speed operation.
Program Flow Control
7-51
Power Management Modes
Figure 7−13. LOPOWER Timing
CLKIN
LOPOWER read
H3
H1
32 CLKIN
Figure 7−14. MAXSPEED Timing
CLKIN
MAXSPEED read
H3
H1
32 CLKIN
7-52
Chapter 8
Two characteristics of the’C3x that contribute to its high performance are:
- Pipelining
- Concurrent I/O and CPU operation
The following four functional units control ’C3x operation:
-
Fetch
Decode
Read
Execute
Pipelining is the overlapping or parallel operations of the fetch, decode, read,
and execute levels of a basic instruction.
The DMA controller decreases pipeline interference and enhances the CPU’s
computational throughput by performing input/output operations.
Topic
Page
8.1
Pipeline Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2
Pipeline Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3
Resolving Register Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.4
Memory Access for Maximum Performance . . . . . . . . . . . . . . . . . . . . 8-22
8.5
Clocking Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Pipeline Operation
8-1
Pipeline Structure
8.1 Pipeline Structure
The following list describes the four major units of the ‘C3x pipeline structure and
their functions:
Fetch unit (F)
Fetches the instruction words from memory
and updates the program counter (PC).
Decode unit (D)
Decodes the instruction word and performs
address generation. Also, the decode unit controls
modification of the ARn registers in the indirect
addressing mode and of the stack pointer when
PUSH to/POP from the stack occurs.
Read unit (R)
If required, reads the operands from memory.
Execute unit (E)
If required, reads the operands from the register
file, performs the necessary operation, and writes
results to the register file. If required, results of
previous operations are written to memory.
All instruction executions perform these four basic functions: fetch, decode, read,
and execute. Figure 8−1 illustrates these four levels of the pipeline structure. The
levels are indexed according to instruction and execution cycle. In the figure, perfect overlap in the pipeline, where all four units operate in parallel, occurs at cycle
(m). Levels about to be executed are at m +1, and those just previously executed
are at m−1. The ‘C3x pipeline controller supports a high-speed processing rate
of one execution per cycle. It also manages pipeline conflicts so that they are
transparent to you. You do not need to take any special precautions to ensure
correct operation.
Figure 8−1. TMS320C3x Pipeline Structure
CYCLE
Fetch
Decode
Read
Execute
m−3
W
—
—
—
m−2
X
W
—
—
m−1
Y
X
W
—
m
Z
Y
X
W
m+1
—
Z
Y
X
m+2
—
—
Z
Y
m+3
—
—
—
Z
Note:
8-2
W, X, Y, Z = Instruction representations
Perfect
overlap
Pipeline Structure
For ‘C30 and ‘C31/VC33, priorities from highest to lowest have been assigned
to each of the functional units of the pipeline and to the DMA controller as follows:
-
Execute (highest)
Read
Decode
Fetch
DMA (lowest)
Despite the DMA controller’s low priority, you can minimize or even eliminate
conflicts with the CPU through suitable data structuring because the DMA controller has its own data and address buses.
In the ‘C32, the DMA has configurable priorities. Therefore, priorities from
highest to lowest have been assigned to each of the functioned units of the
pipeline and to the DMA controller as follows:
-
DMA (if configured with highest priority)
Execute
Read
Decode
Fetch
DMA (if configured with lowest priority)
A pipeline conflict occurs when an instruction is being processed, and is ready
to pass to the next higher pipeline level while that level is not ready to accept
a new input. In this case, the lower priority unit waits until the higher priority unit
completes executing the current function.
Pipeline Operation
8-3
Pipeline Conflicts
8.2 Pipeline Conflicts
Pipeline conflicts in the ’C3x can be grouped into the following categories:
Branch conflicts
Branch conflicts involve most of those instructions or
operations that read and/or modify the PC.
Register conflicts
Register conflicts involve delays that can occur when
reading from, or writing to, registers that are used for
address generation.
Memory conflicts
Memory conflicts occur when the internal units of the
’C3x compete for memory resources.
Each of these three types, including examples, is discussed in the following
subsections. In these examples, when data is refetched or an operation is
repeated, the symbol representing the stage of the pipeline is appended with
a number. For example, if a fetch is performed again, the instruction mnemonic
is repeated. When an access is detained for multiple cycles because the unit
is not ready, the symbol RDY indicates that a unit is not ready and RDY indicates that a unit is ready. If the particular unit does not perform a function, the
nop label is placed in that stage of the pipeline.
8.2.1
Branch Conflicts
The first class of pipeline conflicts occurs with standard (nondelayed)
branches, that is, BR, Bcond, DBcond, CALL, IDLE, RPTB, RPTS, RETIcond,
RETScond, interrupts, and reset. Conflicts arise with these instructions and
operations because, during their execution, the pipeline is used only for the
completion of the operation; other information fetched into the pipeline is discarded or refetched, or the pipeline is inactive. This is referred to as flushing
the pipeline. Flushing the pipeline is necessary in these cases to ensure that
portions of succeeding instructions do not inadvertently get partially executed.
TRAP cond and CALLcond are classified differently from the other types of
branches and are considered later.
Example 8−1 shows the code and pipeline operation for a standard branch.
Note: Dummy Fetch
In this example, one dummy fetch (an MPYF instruction) is performed before
the branch is decoded. After the branch address is available, a new fetch (an
OR instruction) is performed.
8-4
Pipeline Conflicts
Example 8−1. Standard Branch
BR
MPYF
ADD
SUBF
AND
THREE
.
.
.
THREE OR
STI
.
.
.
;
;
;
;
;
Unconditional branch
Not executed
Not executed
Not executed
Not executed
; Fetched after BR is taken
Pipeline Operation
PC
Fetch
Decode
Read
Execute
BR
—
—
—
n+1
MPYF
BR
—
—
n+1
(nop)
(nop)
BR
—
n+1
(nop)
(nop)
(nop)
BR
OR
(nop)
(nop)
(nop)
STI
OR
(nop)
(nop)
n
3
Fetch held for
new PC value
3
PC
Note:
Both RPTS and RPTB flush the pipeline, allowing the RS, RE, and RC registers
to be loaded at the proper time. If these registers are loaded without the use of
RPTS or RPTB, no flushing of the pipeline occurs. Thus, RS, RE, and RC can
be used as general-purpose 32-bit registers without pipeline conflicts. When
RPTB is nested because of nested interrupts, it may be necessary to load and
store these registers directly while using the repeat modes. Since up to four
instructions can be fetched before entering the repeat mode, you should follow
loads by a branch to flush the pipeline. If the RC is changing when an instruction is loading it, the direct load takes priority over the modification made by
the repeat mode logic.
Delayed branches are implemented to ensure the fetching of the next three
instructions. The delayed branches include BRD, BcondD, and DBcondD.
Example 8−2 shows the code and pipeline operation for a delayed branch.
Pipeline Operation
8-5
Pipeline Conflicts
Example 8−2. Delayed Branch
BRD
MPYF
ADD
SUBF
AND
.
.
.
THREE MPYF
.
.
.
THREE
;
;
;
;
;
Unconditional delayed branch
Executed
Executed
Executed
Not executed
; Fetched after SUBF is fetched
Pipeline Operation
Fetch
Decode
Read
Execute
BRD
—
—
—
n+1
MPYF
BRD
—
—
n+2
ADDF
MPYF
BRD
—
n+3
SUBF
ADDF
MPYF
BRD
3
MPYF
SUBF
ADDF
MPYF
PC
n
8.2.2
No
execute
delay
3
PC
Register Conflicts
Register conflicts involve reading or writing registers used for addressing.
These conflicts occur when the pertinent register is not ready to be used. Some
conditions under which you can avoid register conflicts are discussed in Section 8.3 on page 8-19.
The registers comprise the following three functional groups:
Group 1
This group includes auxiliary registers (AR0−AR7), index
registers (IR0, IR1), and block-size register (BK).
Group 2
This group includes the data-page pointer (DP).
Group 3
This group includes the system-stack pointer (SP).
If an instruction writes to one of these three groups, the decode unit cannot use
any register within that particular group until the write is complete, that is, until
the instruction execution is completed. In Example 8−3, an auxiliary register
8-6
Pipeline Conflicts
is loaded, and a different auxiliary register is used on the next instruction. Since
the decode stage needs the result of the write to the auxiliary register, the
decode of this second instruction is delayed two cycles. Every time the decode
is delayed, a refetch of the program word is performed; the ADDF is fetched
three times. Since these are actual refetches, they can cause not only conflicts
with the DMA controller but also cache hits and misses.
A post-/preincrement/decrement of an AR register in an instruction is not
considered a write to a register. A write is in the form of an LDF, LDI, LDII, or
DB instruction.
Example 8−3. Write to an AR Followed by an AR for Address Generation
NEXT
LDI
7,AR2
MPYF *AR2,R0
ADDF
FLOAT
; 7 → AR2
; Decode delayed 2 cycles
Pipeline Operation
Fetch
Decode
Read
Execute
LDI
—
—
—
n+1
MPYF
LDI
—
—
n+2
ADDF
MPYF
LDI
—
n+2
ADDF
MPYF
(nop)
LDI 7,AR2
n+2
ADDF
MPYF
(nop)
(nop)
n+3
FLOAT
ADDF
MPYF
(nop)
PC
n
Decode/address
generation held
until AR write is
completed
ARs written
The case for reads of these groups is similar to the cases for writes. If an
instruction must read a member of one of these groups, the use of that particular
group by the decode for the following instruction is delayed until the read is
complete. The registers are read at the start of the execute cycle and require only
a one-cycle delay of the following decode. For four registers (IR0, IR1, BK, or DP),
there is no delay. For all other registers, including the SP, the delay occurs.
Note that an address generation through the use of an AR register (*ARn,
*++ARn, *−ARn, etc.) in an instruction is not considered a read.
Pipeline Operation
8-7
Pipeline Conflicts
In Example 8−4, two auxiliary registers are added together, with the result going
to an extended-precision register. The next instruction uses a different auxiliary
register as an address register.
Example 8−4. A Read of ARs Followed by ARs for Address Generation
NEXT
ADDI AR0,AR1,R1
MPYF *++AR2,R0
ADDF
FLOAT
; AR0+AR1 → R1
; Decode delayed one cycle
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
ADDI
—
—
—
n+1
MPYF
ADDI
—
—
n+2
ADDF
MPYF
ADDI
—
n+2
ADDF
MYPF
(nop)
ADDI AR0,AR1,R0
n+3
FLOAT
ADDF
MPYF
(nop)
Decode/address
generation held
until AR is read
ARs read
Note:
Loop counter auxiliary registers for the decrement and branch (DBR) instructions are regarded in the same way as they are for addressing. The operation
shown in Example 8−3 and Example 8−4 also can occur for this instruction.
8.2.3
Memory Conflicts
Memory conflicts can occur when the memory bandwidth of a physical memory
space is exceeded. For example, RAM blocks 0 and 1 and the ROM block can
support only two accesses per cycle. The external interface can support only
one access per cycle. Section 8.4, Memory Access for Maximum Performance,
on page 8-22 contains some conditions under which you can avoid memory
conflicts.
8-8
Pipeline Conflicts
Memory pipeline conflicts consist of the following four types:
Program wait
A program fetch is prevented from beginning.
Program fetch Incomplete A program fetch has begun but is not yet
complete.
Execute only
An instruction sequence requires three CPU
data accesses in a single cycle.
Hold everything
A primary or expansion bus operation must
complete before another one can proceed.
These four types of memory conflicts are illustrated in examples and discussed
in the paragraphs that follow.
8.2.3.1
Program Wait
Two conditions can prevent the program fetch from beginning:
- The start of a CPU data access when:
J
Two CPU data accesses are made to an internal RAM or ROM block,
and a program fetch from the same block is necessary.
J
One of the external ports is starting a CPU data access, and a program
fetch from the same port is necessary.
- A multicycle CPU data access or DMA data access over the external bus
is needed.
Example 8−5 illustrates a program wait until a CPU data access completes.
In this case, *AR0 and *AR1 are both pointing to data in RAM block 0, and the
MPYF instruction will be fetched from RAM block 0. This results in the conflict
shown in Example 8−5. Because more than two accesses can be made to
RAM block 0 in a single cycle, the program fetch cannot begin and must wait
until the CPU data accesses are complete.
Pipeline Operation
8-9
Pipeline Conflicts
Example 8−5. Program Wait Until CPU Data Access Completes
ADDF3 *AR0,*AR1,R0
FIX
MPYF
ADDF3
NEGB
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
ADDF3
—
—
—
n+1
FIX
ADDF3
—
—
n+2
(wait)
FIX
ADDF3
—
n+2
MPYF
(nop)
FIX
ADDF3
n+3
ADDF3
MPYF
(nop)
FIX
n+4
NEGB
ADDF3
MPYF
(nop)
Fetch held
until data
access
completes
Data
accessed
Example 8−6 shows a program wait due to a multicycle data-data access or
a multicycle DMA access. The ADDF, MPYF, and SUBF are fetched from some
portion in memory other than the external port the DMA requires. The DMA
begins a multicycle access. The program fetch corresponding to the CALL is
made to the same external port that the DMA is using.
Either of two cases may produce this situation:
- One of the following two memory boundaries is crossed:
J
J
From internal memory to external memory
From one external port to another
- Code that has been cached is executed, and the instruction prior to the
ADDF is one of the following (conditional or unconditional):
J
J
A delayed branch instruction
A delayed decrement and branch instruction
Even though the DMA has the lowest priority on ’C30 and ’C31/VC33 or when configured as such in the ’C32, multicycle access cannot be aborted. The program
fetch must wait until the DMA access completes.
8-10
Pipeline Conflicts
Example 8−6. Program Wait Due to Multicycle Access
ADDF
MPY
SUBF
CALL
;
;
;
;
code
code
code
code
in
in
in
in
internal
internal
internal
external
memory
memory
memory
memory
Pipeline Operation
8.2.3.2
PC
Fetch
Decode
Read
Execute
n
ADDF
—
—
—
n+1
MPYF
ADDF
—
—
n+2
SUBF
MPYF
ADDF
—
n+3
(wait)
SUBF
MPYF
ADDF
n+3
CALL
(nop)
SUBF
MPYF
n+4
—
CALL
(nop)
SUBF
2-cycle DMA
access
Program Fetch Incomplete
A program fetch incomplete occurs when an instruction fetch takes more than
one cycle to complete because of wait states. In Example 8−7, the MPYF and
ADDF are fetched from memory that supports single-cycle accesses. The
SUBF is fetched from memory requiring one wait state. One example that
demonstrates this conflict is a fetch across a bank boundary on the primary
port. See Section 9.5 on page 9-12.
Pipeline Operation
8-11
Pipeline Conflicts
Example 8−7. Multicycle Program Memory Fetches
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
MPYF
—
—
—
n+1
ADDF
MPYF
—
—
n+2 RDY
SUBF
ADDF
MPYF
—
n+2 RDY
SUBF
(nop)
ADDF
MPYF
n+3
ADDI
SUBF
(nop)
ADDF
Note:
8.2.3.3
1 wait state
required
PC = program counter
Execute Only
The execute-only type of memory pipeline conflict occurs when performing an
interlocked load or when a sequence of instructions requires three CPU data
accesses in a single cycle. There are two cases in which this occurs:
- An instruction performs a store and is followed by an instruction that
performs two memory reads.
- An instruction performs two stores and is followed by an instruction that
performs at least one memory read.
- An interlocked load (LDII or LDFI) instruction is performed, and XF1 = 1.
The first case is shown in Example 8−8. Since this sequence requires three
data memory accesses and only two are available, only the execute phase of
the pipeline is allowed to proceed. The dual reads required by the LDF || LDF
are delayed one cycle. In this case, a refetch of the next instruction can occur.
8-12
Pipeline Conflicts
Example 8−8. Single Store Followed by Two Reads

STFR
LDF
LDF
; R0 → *AR1
; *AR2 → R1 in parallel with
; *AR3 → R2
0,*AR1
*AR2,R1
*AR3,R2
Pipeline Operation
Fetch
Decode
Read
Execute
STF
—
—
—
n+1
LDF LDF
STF
—
—
n+2
W
LDF LDF
STF
—
n+3
X
W
LDF LDF
STF
n+4
X
W
LDF LDF
(nop)
n+4
Y
X
W
LDF LDF
PC
n
Note:
Write must
complete
before the
two reads can
complete
2 reads
performed
W, X, Y = Instruction representations
Pipeline Operation
8-13
Pipeline Conflicts
Example 8−9 shows a parallel store followed by a single load or read. Since
two parallel stores are required, the next CPU data-memory read must wait
one cycle before beginning. One program-memory refetch can occur.
Example 8−9. Parallel Store Followed by Single Read

STF
STF
ADDF
IACK
ASH
R0,*AR0
R2,*AR1
@SUM,R1
;
;
;
R0 → *AR0 in parallel with
R2 → *AR1
R1 + @SUM → R1
Pipeline Operation
Fetch
Decode
Read
Execute
STF STF
—
—
—
n+1
ADDF
STF STF
—
—
n+2
IACK
ADDF
STF STF
—
n+3
ASH
IACK
ADDF
STF STF
n+4
ASH
IACK
ADDF
(nop)
n+4
—
ASH
IACK
ADDF
PC
n
Read must wait
until the writes are
completed
Writes
performed
The final case involves an interlocked load (LDII or LDFI) instruction and XF1 = 1.
Since the interlocked loads use the XF1 pin as an acknowledge that the read
can complete, the loads might need to extend the read cycle, as shown in
Example 8−10. A program refetch can occur.
8-14
Pipeline Conflicts
Example 8−10. Interlocked Load
NOT
LDII
2
ADDI
CMPI
R1,R0
300h,AR
*AR2,R2
R0,R2
Pipeline Operation
XF1
Fetch
Decode
Read
Execute
n
1
NOT
—
—
—
n+1
1
LDII
NOT
—
—
n+2
1
ADDI
LDII
NOT
—
n+3
1
CMPI
ADDI
LDII
NOT
n+3
1
—
CMPI
ADDI
LDII
n+4
0
—
CMPI
ADDI
LDII
PC
8.2.3.4
XF1 = 1,
read must wait
XF1 = 0,
read operation
is complete
Hold Everything
Three situations result in hold-everything memory pipeline conflicts:
- A CPU data load or store cannot be performed because an external port
is busy.
- An external load takes more than one cycle.
- Conditional calls and traps, which take one more cycle than conditional
branches, are processed.
The first type of hold-everything conflict occurs when one of the external ports
is busy because an access has started, but is not complete. In Example 8−11,
the first store is a 2-cycle store. The CPU writes the data to an external port.
The port control then takes two cycles to complete the data-data write. The
LDF is a read over the same external port. Since the store is not complete, the
CPU continues to attempt LDF until the port is available.
Pipeline Operation
8-15
Pipeline Conflicts
Example 8−11. Busy External Port
STF
LDF
R0,@DMA1
@DMA2,R0
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
STF
—
—
—
n+1
LDF
STF
—
—
n+2
W
LDF
STF
—
n+2
W
LDF
(nop)
STF
n+2
W
LDF
(nop)
n+3
X
W
LDF
(nop)
n+4
Y
X
W
LDF
Note:
2-cycle external bus
write access
(nop)
W, X, Y = Instruction representations
The second type of hold-everything conflict involves multicycle data reads.
The read has begun and continues until completed. In Example 8−12, the LDF
is performed from an external memory that requires several cycles to access.
8-16
Pipeline Conflicts
Example 8−12. Multicycle Data Reads
LDF
@DMA,R0
Pipeline Operation
PC
Fetch
Decode
Read
Execute
LDF
—
—
—
n+1
I
LDF
—
—
n+2
J
I
LDF
—
n+3
K(dummy)
I
LDF
—
n+3
K2
J
I
LDF
n
Note:
2-cycle external bus
read access
I, J, K = Instruction representations
The final type of hold-everything conflict deals with conditional calls (CALLcond)
and traps (TRAPcond), which are different from other branch instructions.
Whereas other branch instructions are conditional loads, the conditional calls
and traps are conditional stores, which take one more cycle to complete than
conditional branches (see Example 8−13). The added cycle pushes the return
address after the call condition is evaluated.
Pipeline Operation
8-17
Pipeline Conflicts
Example 8−13. Conditional Calls and Traps
Pipeline Operation
Fetch
Decode
Read
Execute
CALLcond
—
—
—
n+1
I
CALLcond
—
—
n+1
(nop)
(nop)
CALLcond
—
n+1
(nop)
(nop)
(nop)
CALLcond
n+1
(nop)
(nop)
(nop)
CALLcond
I
(nop)
(nop)
(nop)
PC
n
n+2/CALLaddr
Note:
8-18
I = Instruction representation
PC store
cycle
Resolving Register Conflicts
8.3 Resolving Register Conflicts
If the auxiliary registers (AR7−AR0), the index registers (IR1−IR0), data-page
pointer (DP), or stack pointer (SP) are accessed for any reason other than
address generation, pipeline conflicts associated with the next memory access
can occur. The pipeline conflicts and delays are presented in Section 8.2 on
page 8-4.
Example 8−14, Example 8−15, and Example 8−16 demonstrate some common
uses of these registers that do not produce a conflict or ways that you can avoid
the conflict.
Example 8−14. Address Generation Update of an AR Followed by an AR for Address
Generation
LDF
MPYF
ADDF
FIX
MPYF
ADDF
7.0,R0
; 7.0 → R0
*++AR0(IR1),R0
*AR2,R0
Pipeline Operation
Fetch
Decode
Read
Execute
n
LDF
—
—
—
n+1
MYPF
LDF
—
—
n+2
ADDF
MYPF
LDF
—
n+3
FIX
ADDF
MYPF
LDF
n+4
MPYF
FIX
ADDF
MYPF
n+5
ADDF
MYPF
FIX
ADDF
PC
Note:
ARs read
W, X, Y, Z = Instruction representations
Pipeline Operation
8-19
Resolving Register Conflicts
Example 8−15. Write to an AR Followed by an AR for Address Generation Without a
Pipeline Conflict
LDI
MPYF
ADDF
MPYF
SUBF
STF
@TABLE,AR2
@VALUE,R1
R2,R1
*AR2++,R1
Pipeline Operation
Fetch
Decode
Read
Execute
LDI
—
—
—
n+1
MYPF
LDI
—
—
n+2
ADDF
MYPF
LDI
—
n+3
MYPF
ADDF
MYPF
LDI
n+4
SUBF
MYPF
ADDF
MYPF
n+5
STF
SUBF
MYPF
ADDF
PC
n
AR2 written
AR2 read
8-20
Resolving Register Conflicts
Example 8−16. Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict
LDP
POP
LDF
LDI
PUSHF
PUSH
TABLE_ADDR
R0
*−AR3(2),R1
@TABLE_ADDR,AR0
R6
R4
Pipeline Operation
Fetch
Decode
Read
Execute
n
LDP
—
—
—
n+1
POP
LDP
—
—
n+2
LDF
POP
LDP
—
n+3
LDI
LDF
POP
LDP
n+4
PUSHF
LDI
LDF
POP
n+5
PUSH
PUSHF
LDI
LDF
PC
DP written
DP read
Pipeline Operation
8-21
Memory Access for Maximum Performance
8.4 Memory Access for Maximum Performance
If program fetches and data accesses are performed so that the resources
being used cannot provide the necessary bandwidth, the pipeline is stalled
until the data accesses are complete. Certain configurations of program fetch
and data accesses yield conditions under which the ’C3x can achieve
maximum throughput.
Table 8−1 shows how many accesses can be performed from the different
memory spaces when it is necessary to do a program fetch and a single data
access and still achieve maximum performance (one cycle). Four cases
achieve 1-cycle maximization.
Table 8−1. One Program Fetch and One Data Access for Maximum Performance
Expansion Bus†
or
Peripheral Accesses
Case No.
Primary
Bus
Accesses
1
1
1
—
2
1
—
1
3
—
2 from any combination of
internal memory
—
4
—
1
1
Accesses From Dual
Access Internal Memory
† The expansion bus is available only on the ’C30.
Table 8−2 shows how many accesses can be performed from the different
memory spaces when it is necessary to do a program fetch and two data
accesses and still achieve maximum performance (one cycle). Six conditions
achieve this maximization.
8-22
Memory Access for Maximum Performance
Table 8−2. One Program Fetch and Two Data Accesses for Maximum Performance
Primary Bus
Accesses
Accesses From Dual-Access
Internal Memory
Expansion† Or
Peripheral Bus
Accesses
1
1
2 from any combination of internal memory
—
2
1 program
1 data
1 data
3
1 data
1 data
1 program
4
1 data
1 program, 1 data
1 DMA
5
—
2 from same internal memory block and 1 from
a different internal memory block
—
6
—
3 from different internal memory blocks
—
7
—
2 from any combination of internal memory
1
8
1 program
2 data
1 DMA
9
1 DMA
2 data
1 program
Case No.
† The expansion bus is available only on the ’C30.
Pipeline Operation
8-23
Clocking Memory Accesses
8.5 Clocking Memory Accesses
This section discusses the role of internal clock phases (H1 and H3) and how
the ’C3x handles multiple-memory accesses. The previous section discusses
the interaction between sequences of instructions; this section discusses the
flow of data on an individual instruction basis.
Each major clock period of 33.3 ns is composed of two minor clock periods of
16.67 ns, labeled H3 and H1. The active clock period for H3 and H1 is the time
when that signal is high. See Figure 8−2.
Figure 8−2. Minor Clock Periods
Major clock period
H1
minor
clock period
H1
H3
minor
clock period
H3
The precise operation of memory reads and writes can be defined according
to these minor clock periods. The types of memory operations that can occur
are program fetches, data loads and stores, and DMA accesses.
8.5.1
Program Fetches
Internal program fetches are always performed during H3 unless a single data
store must occur at the same time due to another instruction in the pipeline. In that
case, the program fetch occurs during H1 and the data store occurs during H3.
External program fetches always start at the beginning of H3 with the address
being presented on the external bus. At the end of H1, the fetches are completed
with the latching of the instruction word.
8.5.2
Data Loads and Stores
Four types of instructions perform loads, memory reads, and stores:
-
8-24
2-operand instructions
3-operand instructions
Multiplier/ALU operation with store instructions
Parallel multiply and add instructions
Clocking Memory Accesses
See Chapter 6, Addressing Modes, for more information.
As discussed in Chapter 7, the number of bus cycles for external memory
accesses differs in some cases from the number of CPU execution cycles. For
external reads, the number of bus cycles and CPU execution cycles is identical.
For external writes, there are always at least two bus cycles, but unless there
is a port-access conflict, there is only one CPU execution cycle. In the following
examples, any difference in the number of bus cycles and CPU cycles is noted.
8.5.2.1
2-Operand Instruction Memory Accesses
All instructions whose bits 31−29 are 000 or 010 (see Figure 8−3) are 2-operand
instructions. In the case of a data read, bits 15−0 represent the src operand.
Internal data reads are always performed during H1. External data reads always
start at the beginning of H3 with the address presented on the external bus; they
complete with the latching of the data word at the end of H1.
In the case of a data store, bits 15−0 represent the dst operand. Internal data
stores are performed during H3. External data stores always start at the
beginning of H3 with the address and data being presented on the external bus.
Figure 8−3. 2-Operand Instruction Word
31
0 X 0
8.5.2.2
24 23
Operation
16 15
G
8 7
dst(src)
0
src(dst)
3-Operand Instruction Memory Reads
All instructions whose bits 31−29 are 001 (see Figure 8−4) are 3-operand
instructions. The source operands, src1 and src2, come from either registers
or memory. When one or more of the source operands are from memory, these
instructions are always memory reads.
Figure 8−4. 3-Operand Instruction Word
31
0 0 1
24 23
Operation
16 15
T
dst
8 7
src1
0
src2
If only one of the source operands is from memory (either src1 or src2) and is
located in internal memory, the data is read during H1. If the single memory
source operand is in external memory, the read starts at the beginning of H3,
with the address presented on the external bus, and completes with the latching
of the data word at the end of H1.
Pipeline Operation
8-25
Clocking Memory Accesses
If both source operands are to be fetched from memory, then memory reads
can occur in several ways:
- If both operands are located in internal memory, the src1 read is performed
during H3 and the src2 read during H1, completing two memory reads in
a single cycle.
- If src1 is in internal memory and src2 is in external memory, the src2 access
begins at the start of H3 and latches at the end of H1. At the same time, the
src1 access to internal memory is performed during H3. Again, two memory
reads are completed in a single cycle.
- If src1 is in external memory and src2 is in internal memory, two cycles are
necessary to complete the two reads. In the first cycle, both operands are
addressed. Since src1 takes an entire cycle to be read and latched from
external memory, the internal operation on src2 cannot be completed until
the second cycle. Ordering the operands so that src1 is located internally
is necessary to achieve single-cycle execution.
- If src1 and src2 are both from external memory, two cycles are required to
complete the two reads. In the first cycle, the src1 access is performed and
loaded on the next H3; in the second cycle, the src2 access is performed
and loaded on that cycle’s H1.
If src2 is in external memory and src1 is in on-chip or external memory and is
immediately preceded by a single store instruction to external memory, a
dummy src2 read can occur between the execution of the store instruction and
the src2 read, regardless of which memory space is accessed (STRB, MSTRB,
or IOSTRB). The dummy read can cause an externally interfaced FIFO address
pointer to be incremented prematurely, thereby causing the loss of FIFO data.
Example 8−17 illustrates how the dummy read can occur. Example 8−18 offers
an alternative code segment that suppresses the dummy read. In the alternative
code segment, the dummy read is eliminated by swapping the order of the
source operands.
8-26
Clocking Memory Accesses
Example 8−17. Dummy sr2 Read
STI
ADDI3
R0,*AR6
*AR1,*AR3,R0
; AR6 points to MSTRB space
; AR3 points to on-chip RAM (src1)
; AR1 points to MSTRB space (src2)
H1
H3
Pipeline Operation
PC
n
n+1
n+2
Fetch
Decode
Read
Execute
STI
ADDI3
STI
ADDI3
STI
n+3
—
STI
n+4
—
—
n+5
ADDI3
—
n+6
—
—
n+7
ADDI3
—
n+8
ADDI3
R0, *AR6 until the
store is complete
2-cycle dummy
load of src2
actual read of
src2 and src1
Two cycles are required for the MSTRB store. Two additional cycles are required
for the dummy MSTRB read of *AR3 (because a read follows a write). One cycle
is required for an actual MSTRB read of *AR3.
Pipeline Operation
8-27
Clocking Memory Accesses
Example 8−18. Operand Swapping Alternative
Switch the operands of the 3-operand instruction so that the internal read is
performed first.
STI
ADDI3
R0,*AR6
*AR3,*AR1,R0
; AR6 points to MSTRB space
; AR3 points to on-chip RAM (src2)
; AR1 points to MSTRB space (src1)
H1
H3
Pipeline Operation
PC
n
n+1
n+2
n+3
Fetch
Decode
Read
Execute
STI
ADDI3
STI
ADDI3
STI
—
STI
2-cycle store
n+4
—
—
n+5
ADDI3
—
n+6
—
—
n+7
—
ADDI3
n+8
8-28
The read of src2 cannot start
until the store is complete
2-cycle read of src1 and src2
ADDI3
Clocking Memory Accesses
8.5.2.3
Operations with Parallel Stores
The next class of instructions includes every instruction that has a store in parallel
with another instruction. Bits 31 and 30 for these instructions are equal to 1 1.
The instruction word format for operations that perform a multiply or ALU operation in parallel with a store is shown in Figure 8−5. If the store operation to dst2
is external or internal, it is performed during H3. Two bus cycles are required for
external stores, but only one CPU cycle is necessary to complete the write.
If the memory read operation is external, it starts at the beginning of H3 and
latches at the end of H1. If the memory read operation is internal, it is
performed during H1. Note that memory reads are performed by the CPU
during the read (R) phase of the pipeline, and stores are performed during the
execute (E) phase.
Figure 8−5. Multiply or CPU Operation With a Parallel Store
31
24 23
1 1 Operation
P
d1 d2
16 15
src1
src2
8 7
0
src4
src3
The instruction word format for instructions that have parallel stores to memory
is shown in Figure 8−6. If both destination operands, dst1 and dst2, are located
in internal memory, dst1 is stored during H3 and dst2 during H1, thus completing
two memory stores in a single cycle.
Figure 8−6. Two Parallel Stores
24 23
31
1 1
ST||ST
src2
16 15
0 0 0
src1
8 7
dst1
0
dst2
- If dst1 is in external memory and dst2 is in internal memory, the dst1 store
begins at the start of H3. The dst2 store to internal memory is performed
during H1. Two bus cycles are required for the external store, but only one
CPU cycle is necessary to complete the write. Again, two memory stores
are completed in a single cycle.
- If dst1 is in internal memory and dst2 is in external memory, an additional bus
cycle is necessary to complete the dst2 store. Only one CPU cycle is necessary to complete the write, but the port access requires three bus cycles. In
the first cycle, the internal dst1 store is performed during H3, and dst2 is written to the port during H1. During the next cycle, the dst2 store is performed
on the external bus, beginning in H3, and executes as normal through the
following cycle.
Pipeline Operation
8-29
Clocking Memory Accesses
- If dst1 and dst2 are both written to external memory, a single CPU cycle
is still all that is necessary to complete the stores. In this case, four bus
cycles are required.
1) In the first cycle, both dst1 and dst2 are written to the port, and the external-bus access for dst1 begins.
a) The store for dst1 is completed on the second cycle.
b) The store for dst2 begins on the third external-bus cycle.
c) The store for dst2 is completed on the fourth external-bus cycle.
8.5.2.4
Parallel Multiplies and Adds
Memory addressing for parallel multiplies and adds is similar to that for 3-operand
instructions. The parallel multiplies and adds include all instructions with bits
31−30 = 10 (see Figure 8−7).
Figure 8−7. Parallel Multiplies and Adds
31
24 23
1 0 Operation
P
d1 d2
16 15
src1
src2
8 7
src3
0
src4
For these operations, src3 and src4 are both located in memory. If both operands
are located in internal memory, src3 is performed during H3, and src4 is performed during H1, thus completing two memory reads in a single cycle.
- If src3 is in internal memory and src4 is in external memory, the src4 access
begins at the start of H3 and latches at the end of H1. At the same time, the
src3 access to internal memory is performed during H3. Again, two memory
reads are completed in a single cycle.
- If src3 is in external memory and src4 is in internal memory, two cycles
are necessary to complete the two reads. In the first cycle, the internal src4
access is performed. During the H3 of the next cycle, the src3 access is
performed.
- If src3 and src4 are both from external memory, two cycles are necessary
to complete the two reads. In the first cycle, the src3 access is performed;
in the second cycle, the src4 access is performed.
8-30
Chapter 9
!%&'(&( !%&'(&)*+&&
$!",
This chapter describes the ’C30 and ’C31/VC33 external-memory interface.
See Chapter 10, Enhanced External-Memory Interface, for detailed information on the ’C32 external bus operation.
Memories and external peripheral devices are accessible through two external
interfaces on the ’C30:
- Primary bus
- Expansion bus
On the ’C31/VC33, one bus, the primary bus, is available to access external
memories and peripheral devices. You can control wait-state generation, permitting access to slower memories and peripherals, by manipulating memorymapped control registers associated with the interfaces and by using an external
input signal.
Note: VC33
The TMS320VC33 is logically and functionally a superset of the TMS320C31
making nearly all literature and documentation for the TMS320C31 applica−
ble. However, the electrical characteristics are different and are covered in
detail in the TMS320VC33 data sheet (literature number SPRS087).
Topic
Page
9.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2
Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3
Memory Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.4
Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.5
Programmable Bank Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.6
External Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9-1
Overview
9.1 Overview
The ’C30 provides two external interfaces: the primary bus and the expansion
bus. The TMS320C31/VC33 provides one external interface: the primary bus.
The primary bus consists of a 32-bit data bus, a 24-bit address bus, and a set
of control signals. The expansion bus consists of a 32-bit data bus, a 13-bit
address bus, and a set of control signals. Each interface has the following
features:
- Separate configurations controlled by memory-mapped external interface
control registers
- Hold request and acknowledge signal for putting the external memory inter-
face signals in high impedance mode and preventing the processor from
accessing the external bus
- Selectable wait state that can be controlled through software, hardware,
or combination of software and hardware
- Unified memory space for data, program, and I/O access
9-2
Memory Interface Signals
9.2 Memory Interface Signals
This section describes the differences between the ’C30 and ’C31/VC33
memory interface signals.
9.2.1
TMS320C30 Memory Interface Signals
The TMS320C30 has two sets of control signals as follows:
- Primary bus control signals: STRB, R/W, HOLD, HOLDA, RDY
Table 9−1 lists and describes the signals.
- Expansion bus control signals: MSTRB, IOSTRB, XR/W, XRDY
Table 9−2 lists and describes the expansion bus control signals.
Access is determined by an active strobe signal (STRB, MSTRB, or IOSTRB).
When a primary bus access is performed, STRB is low. The expansion bus of
the ’C30 supports two types of accesses:
- Memory access signaled by MSTRB low. The timing for an MSTRB access
is the same as that of the STRB access on the primary bus.
- External peripheral device access is signaled by IOSTRB low.
Each of the buses (primary and expansion) has an associated control register.
These registers are memory-mapped as shown in Figure 9−1.
9.2.2
TMS320C31/VC33 Memory Interface Signals
The TMS320C31/VC33 has one set of control signals:
- Primary bus control signals: STRB, R/W, HOLD, HOLDA, RDY
STRB is low when an external bus access is performed. The primary bus
control register controls its behavior (see Section 9.3).
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-3
Memory Interface Signals
Table 9−1. Primary Bus Interface Signals
Value
After Reset
Signal
Type†
STRB
O/Z
Primary interface access strobe
1
1
R/W
O/Z
Specifies memory read (active high) or write
(active low) mode
1
1
HOLD
HOLDA
I
Description
Hold external memory interface
NA‡
O/Z
Hold acknowledge for external memory interface
1
I
Indicates external primary interface is ready to
be accessed
NA‡
A (23−0)
O/Z
Primary address bus. When the primary bus
address lines are not in high-impedance state
due to HOLD signal, they keep in the last external primary bus access.
HI
D (31−0)
I/O/Z
Primary data bus. These signals go to highimpedance between write accesses.
HIZ
RDY
† I Input
O Output
Z High impedance
‡ NA means not affected.
9-4
Idle Status
Ignored
1
Ignored
Address of last external
bus access
HIZ
Memory Interface Signals
Table 9−2. Expansion Bus Interface Signals
Value
After Reset
Signal
Type†
MSTRB
O/Z
Expansion bus memory access strobe
1
1
IOSTRB
O/Z
Expansion bus peripheral-access strobe
1
1
XR/W
O/Z
Specifies memory (active high) or write (active
low) mode
1
1
XRDY
I
Indicates external expansion interface is ready
to be accessed
NA‡
XA (12−0)
O
Expansion address bus. When the expansion
bus address lines are not in high-impedance
state due to HOLD signal, they keep the last
external expansion bus access.
HI
XD (31−0)
I/O/Z
Expansion data bus. These signals go to highimpedance between write accesses.
HIZ
Description
Idle Status
Ignored
Address of last external
expansion bus access
HIZ
† I Input
O Output
Z High impedance
‡ NA means not affected.
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-5
Memory Interface Signals
Figure 9−1. Memory-Mapped External Interface Control Registers
Peripheral
Address
9-6
808060h
Expansion-bus control (’C30 only)
808061h
Reserved
808062h
Reserved
808063h
Reserved
808064h
Primary-bus control
(’C30, ’C31/VC33)
808065h
Reserved
808066h
Reserved
808067h
Reserved
808068h
Reserved
808069h
Reserved
80806Ah
Reserved
80806Bh
Reserved
80806Ch
Reserved
80806Dh
Reserved
80806Fh
Reserved
Memory Interface Control Registers
9.3 Memory Interface Control Registers
Two memory interface control registers, the primary-bus control register and
the expansion-bus control register, are described in this section.
9.3.1
Primary-Bus Control Register
The primary bus control register is a 32-bit register that contains the control bits
for the primary bus (see Figure 9−2). Table 9−3 describes the register bits with
the bit names and functions.
Figure 9−2. Primary-Bus Control Register
31−16
xx
Notes:
15−13
12
11
xx
10
9
8
7
6
5
4
3
2
1
0
BNKCMP
WTCNT
SWW
HIZ
NOHOLD
HOLDST
R/W
R/W
R/W
R/W
R/W
R
1) xx = reserved bit, read as 0
2) R = read, W = write
Note:
After changing the bit fields of the primary-bus control register, up to three
instructions are fetched before the primary bus is reconfigured because the
configuration change is performed in the execute stage of the pipeline.
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-7
Memory Interface Control Registers
Table 9−3. Primary-Bus Control Register Bits
Abbreviation
Reset Value
Name
Description
HOLDST
0
Hold status bit
This bit signals whether the port is being
held (HOLDST = 1) or is not being held
(HOLDST = 0). This status bit is valid
whether the port has been held through
hardware or software.
NOHOLD
0
Port hold signal
NOHOLD allows or disallows the port to be
held by an external HOLD signal. When
NOHOLD = 1, the ’C3x takes over the
external bus and controls it, regardless of
serviced or pending requests by external
devices. No hold acknowledge (HOLDA) is
asserted when a HOLD signal is received. It
is asserted if an internal hold is generated
(HIZ = 1).
HIZ
0
Internal hold
When set (HIZ = 1), the port is put in hold
mode. This is equivalent to the external
HOLD signal. By forcing a high-impedance
condition, the ’C3x can relinquish the external-memory port through software. HOLDA
goes low when the port is placed in the highimpedance state.
SWW
11
Software wait mode
In conjunction with WTCNT, this 2-bit field
defines the mode of wait-state generation.
(See Table 9−5.)
WTCNT
111
Software wait mode
This three-bit field specifies the number of
cycles to use when in software wait mode for
the generation of internal wait states. The
range is 0 (WTCNT = 0 0 0) to 7 (WTCNT=1
1 1) H1/H3 cycles. (See Section 9.4.)
Bank compare
This 5-bit field specifies the number of MSBs
of the address to be used to define the bank
size. (See Table 9−6.)
BNKCMP
9-8
10000
Memory Interface Control Registers
9.3.2
Expansion-Bus Control Register
The expansion-bus control register is a 32-bit register that contains control bits
for the expansion bus (see Figure 9−3 and Table 9−4).
Figure 9−3. Expansion-Bus Control Register
31−16
15−12
11−8
xx
xx
xx
Notes:
7
6
5
4
3
WTCNT
SWW
R/W
R/W
2
xx
1
0
xx
xx
1) xx = reserved bit, read as 0
2) R = read, W = write
Table 9−4. Expansion-Bus Control Register Bits
Abbreviation
Reset Value
Name
Description
SWW
11
Software wait mode
In conjunction with the WTCNT, 2-bit field
defines the mode of wait-state generation.
(See Table 9−5.)
WTCNT
111
Software wait mode
This 3-bit field specifies the number of cycles
to use when in software wait mode for the
generation of internal wait state. The range is
0 (WTCNT = 0 0 0) to 7 (WTCNT = 1) H1/H3
cycles. (See Section 9.4.)
Note:
After changing the bit fields of the expansion-bus control register, up to three
instructions are fetched before the expansion bus is reconfigured because
the configuration change is performed in the execute stage of the pipeline.
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-9
Programmable Wait States
9.4 Programmable Wait States
The ’C3x has its own internal software-configurable ready-generation capability
for each strobe. This software wait-state generator is controlled by configuring
two bit fields in the primary or expansion bus interface control registers.
Use the WTCNT field to specify the number of software wait-states to generate
and use the SWW field to select one of the following four modes of wait-state
generation:
- External RDY wait states are generated solely by the external RDY line
ignoring software wait states.
- WTCNT-generated RDYwtcnt wait states are generated solely by the soft-
ware wait-state generator ignoring external RDY signals.
- Logical-AND of RDY and RDYwtcnt wait states are generated with a logical
AND of internal and external ready signals. Both signals must occur.
- Logical-OR of RDY and RDYwtcnt wait states are generated with a logical
OR of internal and external ready signals. Either signal can generate the
ready signal.
The four modes are used to generate the internal ready signal, RDYint, that
controls accesses. As long as RDYint = 1, the current external access is
delayed. When RDYint = 0, the current access completes. Since the use of
programmable wait states for both external interfaces is identical, only the
primary bus interface is described in the following paragraphs.
RDYwtcnt is an internally-generated ready signal. When an external access is
begun, the value in WTCNT is loaded into a counter. WTCNT can be any value
from 0 through 7. The counter is decremented every H1/H3 clock cycle until
it becomes 0. Once the counter is set to 0, it remains set to 0 until the next
access. While the counter is nonzero, RDYwtcnt = 1. While the counter is 0,
RDYwtcnt = 0.
Table 9−5 shows the truth table for each value of SWW and the different
combinations of RDY, RDYwtcnt, and RDYint.
Note:
At reset, the ’C3x is programmed with seven wait states for each external
memory access. These wait states are inserted to ensure the system can
function with slow memories. To maximize system performance when accessing external memories, you need to decrease the number of wait states.
After changing the wait states, up to three instructions are fetched before the
change in the wait state occurs.
9-10
Programmable Wait States
Table 9−5. Wait-State Generation
Inputs
Output
SWW Bit Field
/RDYext
/RDYwtcnt
/RDYint
00
0
x
0
1
x
1
x
0
0
x
1
1
0
0
0
0
1
0
1
0
0
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
01
10
11
Functional Description
Wait until external RDY is signaled
Wait until internal wait state generator
counts down to 0
Wait until first signal: external RDY or the
internal wait state generator (logical OR)
Wait until both external RDY is signaled
and wait state generator counts down to
0 (logical AND)
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-11
Programmable Bank Switching
9.5 Programmable Bank Switching
Programmable bank switching allows you to switch between external memory
banks without having to insert wait states externally due to memories that require
several cycles to turn off. Bank switching is implemented on the primary bus only.
The size of a bank is determined by the number of bits specified by the BNKCMP
field of the primary bus control register. For example, if BNKCMP = 16, the 16
MSBs of the address are used to define a bank (see Figure 9−4). Since
addresses are 24 bits, the bank size is specified by the eight LSBs, yielding a
bank size of 256 words. If BNKCMP ≥ 16, only the 16 MSBs are compared. Bank
sizes from 28 = 256 to 224 = 16M are allowed. Table 9−6 summarizes the relationship between BNKCMP, the address bits used to define a bank, and the resulting
bank size.
Figure 9−4. BNKCMP Example
24-bit address
23
8 7
Number of bits to compare
0
Defines bank size
Table 9−6. BNKCMP and Bank Size
9-12
BNKCMP
MSBs Defining a Bank
Bank Size (32-Bit Words)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001−11111
None
23
23−22
23−21
23−20
23−19
23−18
23−17
23−16
23−15
23−14
23−13
23−12
23−11
23−10
23−9
23−8
Reserved
224 = 16M
223 = 8M
222 = 4M
221 = 2M
220 = 1M
219 = 512K
218 = 256K
217 = 128K
216 = 64K
215 = 32K
214 = 16K
213 = 8K
212 = 4K
211 = 2K
210 = 1K
29 = 512
28 = 256
Undefined
Programmable Bank Switching
The ’C3x has an internal register that contains the MSBs (as defined by the
BNKCMP field) of the last address used for a read or write over the primary interface. At reset, the register bits are set to 0. If the MSBs of the address being used
for the current primary interface read do not match those contained in this
internal register, a read cycle is not asserted for one H1/H3 clock cycle. During
this extra clock cycle, the address bus switches over to the new address, but
STRB is inactive (high). The contents of the internal register are replaced with
the MSBs being used for the current read of the current address. If the MSBs
of the address being used for the current read match the bits in the register, a
normal read cycle takes place.
If repeated reads are performed from the same memory bank, no extra cycles
are inserted. When a read is performed from a different memory bank, an extra
cycle is inserted. This feature can be disabled by setting BNKCMP to 0. The
insertion of the extra cycle occurs only when a read is performed. The
changing of the MSBs in the internal register occurs for all reads and writes
over the primary interface.
Figure 9−5 shows the addition of an inactive cycle when switches between
banks of memory occur.
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-13
Programmable Bank Switching
Figure 9−5. Bank-Switching Example
H3
H1
STRB
R/W
A
D
Read
Read
Read
RDY
Extra
cycle
Note:
After changing BNKCMP, up to three instructions are fetched before the
change in the bank size occurs.
9-14
External Memory Interface Timing
9.6 External Memory Interface Timing
This section discusses functional timing of operations on the primary bus and the
expansion bus, the two independent parallel buses or the ’C3x devices.
The parallel buses implement three mutually exclusive address spaces distinguished through the use of three separate control signals: STRB, MSTRB, and
IOSTRB. The STRB signal controls accesses on the primary bus, and the
MSTRB and IOSTRB signals control accesses on the expansion bus. Since
the two buses are independent, you can make two accesses in parallel.
With the exception of bank switching and the external HOLD function (discussed
later in this section), timing of primary bus cycles and MSTRB expansion bus
cycles are identical and are discussed collectively. The abbreviation (M)STRB is
used in references that pertain equally to STRB and MSTRB. Similarly, (X)R/W,
(X)A, (X)D, and (X)RDY are used to symbolize the equivalent primary and expansion bus signals. The IOSTRB expansion bus cycles are timed differently and are
discussed independently.
9.6.1
Primary-Bus Cycles
All bus cycles comprise integral numbers of H1 clock cycles. One H1 cycle is
defined to be from one falling edge of H1 to the next falling edge of H1. For
full-speed (zero wait-state) accesses, writes require two H1 cycles and reads
require one cycle; however, if the read follows a write, the read requires two
cycles.This applies to both the primary bus and the MSTRB expansion bus
access.
Note: Posted Write
The data written to external memory by CPU or DMA is “latched” into the bus
logic, allowing the CPU to continue with internal operation. Consequently,
writes to external memory effectively require only one cycle if no accesses to
that interface are in progress. However, if the next DMA or CPU access is to
the same external bus, the DMA or CPU waits and the write is considered a
2-cycle operation. This is normally referred to as posted-write.
The following discussions pertain to zero wait-state accesses unless otherwise
specified.
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-15
External Memory Interface Timing
The (M)STRB signal is low for the active portion of both reads and writes. The
active portion lasts one H1 cycle. Additionally, before and after the active portion
((M)STRB low) of writes only, there is a transition cycle of H1. This transition
cycle consists of the following sequence:
1) (M)STRB is high.
2) If required, (X)R/W changes state on H1 rising.
3) If required, address changes on H1 rising if the previous H1 cycle was the
active portion of a write. If the previous H1 cycle was a read, address
changes on the next H1 falling.
Figure 9−6 illustrates a read-read-write sequence for (M)STRB active and no
wait states. The data is read as late in the cycle as possible to allow maximum
access time from address valid. Although external writes require two cycles,
internally (from the perspective of the CPU and DMA) they require only one
cycle if no accesses to that interface are in progress. In the typical timing for
all external interfaces, the (X)R/W strobe does not change until (M)STRB or
IOSTRB goes inactive.
9-16
External Memory Interface Timing
Figure 9−6. Read-Read-Write for (M)STRB = 0
H3
H1
(M)STRB
(X)R/W
(X)A
(X)D
Read
Read
Write data
(X)RDY
Note:
(x) RDY is sampled low on rising edge of H1. Data is read next falling edge of H1.
Note: Back-to-Back Read Operations
(M)STRB remains low during back-to-back read operations.
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-17
External Memory Interface Timing
Figure 9−7 illustrates a write-write-read sequence for (M)STRB active and no
wait states. The address and data written are held valid approximately one-half
cycle after (M)STRB changes.
Figure 9−7. Write-Write-Read for (M)STRB = 0
H3
H1
(M)STRB
(X)R/W
(X)A
(X)D
(X)RDY
9-18
Write data
Write data
Read
External Memory Interface Timing
Figure 9−8 illustrates a read cycle with one wait state. Since (X)RDY = 1, the
read cycle is extended. (M)STRB, (X)R/W, and (X)A are also extended one
cycle. The next time (X)RDY is sampled, it is 0.
Figure 9−8. Use of Wait States for Read for (M)STRB = 0
H3
H1
(M)STRB
XR/W
(X)A
Read
(X)D
Write data
(X)RDY
Extra
cycle
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-19
External Memory Interface Timing
Figure 9−9 illustrates a write cycle with one wait state. Since initially (X)RDY = 1,
the write cycle is extended. (M)STRB, (X)R/W, and (X)A are extended one cycle.
The next time (X)RDY is sampled, it is 0.
Figure 9−9. Use of Wait States for Write for (M)STRB = 0
H3
H1
(M)STRB
(X)R/W
(X)A
(X)D
Write data
Write data
(X)RDY
Extra
cycle
9-20
External Memory Interface Timing
9.6.2
Expansion-Bus I/O Cycles
In contrast to primary bus and MSTRB cycles, IOSTRB reads and writes are
both two cycles in duration (with no wait states) and exhibit the same timing.
During these cycles, address always changes on the falling edge of H1, and
IOSTRB is low from the rising edge of the first H1 cycle to the rising edge of
the second H1 cycle. The IOSTRB signal always goes inactive (high) between
cycles, and XR/W is high for reads and low for writes.
Figure 9−10 illustrates read and write cycles when IOSTRB is active and there
are no wait states. For IOSTRB accesses, reads and writes require a minimum
of two cycles. Some off-chip peripherals might change their status bits when
read or written to. Therefore, it is important to maintain valid addresses when
communicating with these peripherals. For reads and writes when IOSTRB is
active, IOSTRB is completely framed by the address.
Figure 9−10. Read and Write for IOSTRB = 0
H3
H1
IOSTRB
XR/W
XA
XD
Read
Write data
XRDY
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-21
External Memory Interface Timing
Figure 9−11 illustrates a read with one wait state when IOSTRB is active, and
Figure 9−12 illustrates a write with one wait state when IOSTRB is active. For
each wait state added, IOSTRB, XR/W, and XA are extended one clock cycle.
Writes hold the data on the bus one additional cycle. The sampling of XRDY
is repeated each cycle.
Figure 9−11.Read With One Wait State for IOSTRB = 0
H3
H1
IOSTRB
XR/W
XA
XD
Read
XRDY
Extra
cycle
9-22
External Memory Interface Timing
Figure 9−12. Write With One Wait State for IOSTRB = 0
H3
H1
IOSTRB
XR/W
XA
XD
Write data
XRDY
Extra
cycle
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-23
External Memory Interface Timing
Figure 9−13 through Figure 9−23 illustrate the various transitions between
memory reads and writes, and I/O writes over the expansion bus.
Figure 9−13. Memory Read and I/O Write for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
XD
XRDY
9-24
Memory address
Read
I/O address
I/O write
External Memory Interface Timing
Figure 9−14. Memory Read and I/O Read for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
XD
Memory address
I/O address
Read
I/O read
XRDY
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-25
External Memory Interface Timing
Figure 9−15. Memory Write and I/O Write for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
Memory address
XD
Memory write
XRDY
9-26
I/O address
I/O write
External Memory Interface Timing
Figure 9−16. Memory Write and I/O Read for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
Memory address
XD
Memory write
I/O address
I/O read
XRDY
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-27
External Memory Interface Timing
Figure 9−17. I/O Write and Memory Write for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
I/O address
XD
I/O write
XRDY
9-28
Memory address
Memory write
External Memory Interface Timing
Figure 9−18. I/O Write and Memory Read for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
I/O address
XD
I/O write
Memory address
Read
XRDY
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-29
External Memory Interface Timing
Figure 9−19. I/O Read and Memory Write for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
XD
XRDY
9-30
I/O address
I/O read
Memory address
Memory write
External Memory Interface Timing
Figure 9−20. I/O Read and Memory Read for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
XD
I/O address
Memory address
I/O read
Read
XRDY
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-31
External Memory Interface Timing
Figure 9−21. I/O Write and I/O Read for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
XD
XRDY
9-32
I/O address
I/O write
I/O address
I/O read
External Memory Interface Timing
Figure 9−22. I/O Write and I/O Write for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
XD
I/O address
I/O write
I/O address
I/O write
XRDY
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-33
External Memory Interface Timing
Figure 9−23. I/O Read and I/O Read for Expansion Bus
H3
H1
MSTRB
IOSTRB
XR/W
XA
XD
XRDY
9-34
I/O address
I/O address
I/O read
I/O read
External Memory Interface Timing
Figure 9−24 and Figure 9−25 illustrate the signal states when a bus is inactive
(after an IOSTRB or (M)STRB access, respectively). The strobes (STRB,
MSTRB and IOSTRB) and (X)R/W) go to 1. The address is driven with last external bus access, and the ready signal (XRDY or RDY) is ignored.
Figure 9−24. Inactive Bus States for IOSTRB
H3
H1
IOSTRB
XR/W
XA
XD
XRDY
Write data
XRDY ignored
Bus inactive
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-35
External Memory Interface Timing
Figure 9−25. Inactive Bus States for STRB and MSTRB
H3
H1
(M)STRB
(X)R/W
(X)A
(X)D
(X)RDY
Write data
(X)RDY ignored
Bus inactive
9-36
External Memory Interface Timing
9.6.3
Hold Cycles
Figure 9−26 illustrates the timing for HOLD and HOLDA. HOLD is an external
asynchronous input. There is a minimum of one cycle delay from the time when
the processor recognizes HOLD = 0 until HOLDA = 0. When HOLDA = 0, the
address, data buses, and associated strobes are placed in a high-impedance
state. All accesses occurring over an interface are completed before a hold is
acknowledged.
Figure 9−26. HOLD and HOLDA Timing
H3
H1
HOLD
HOLDA
STRB
R/W
A
D
Write data
Bus
inactive
TMS320C30 and TMS320C31/VC33 External-Memory Interface
9-37
9-38
Chapter 10
!%&'(&' !"
,
The ’C32 external memory interface provides greater flexibility by improving
the ’C3x core with several new features. This chapter describes these features
and enhancements in detail.
Topic
Page
10.1 TMS320C32 Memory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2 TMS320C32 Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4 Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5 Programmable Bank Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.6 32-Bit Wide Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.7 16-Bit Wide Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.8 8-Bit Wide Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.9 External Ready Timing Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 10-38
10.10 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
10-1
TMS320C32 Memory Features
10.1 TMS320C32 Memory Features
The ’C32 external memory interface includes the following features:
- One external pin, PRGW, configures the external-program-memory width
to 16 or 32 bits.
- Two sets of memory strobes (STRB0 and STRB1) and one IOSTRB allow
zero glue-logic interface to two banks of memory and one bank of external
peripherals.
- Separate bus control registers for each strobe-control wait-state genera-
tion, external memory width, and data-type size.
- Each memory STRB handles 8-, 16- or 32-bit external data accesses
(reads and writes) to 8-, 16-, or 32-bit-wide memory.
- Multiprocessor support through the HOLD and HOLDA signals, is valid for
all the STRBs.
10-2
TMS320C32 Memory Overview
10.2 TMS320C32 Memory Overview
The following sections describe examples, control register setups, and
restrictions necessary to fully understand the operation and functionality of the
external memory interface.
10.2.1 External Memory Interface Overview
The ’C32 memory interface accesses external memory through one 24-bit
address and one 32-bit data bus that is shared by three mutually-exclusive
strobes (STRB0, STRB1, and IOSTRB). Depending on the address accessed,
the ’C32 activates one of these strobes according to the memory map shown
in Figure 4−3 on page 4-8.
STRB0 and STRB1 can access 8-, 16-, or 32-bit data from 8-, 16-, or 32-bit
wide memory. This is accomplished by four signals in each strobe:
STRBx_B3/A−1, STRBx_B2/A−2, STRBxB1, and STRBx_B0. These signals
serve as byte-enable pins to access one byte, half word, or a full word from the
external memory. The first two signals also serve as additional address pins
to perform two or four consecutive accesses in 8-bit or 16-bit-wide external
memory. The ’C32 controls the behavior of these pins through the data size
and memory width bit fields in the corresponding strobe control register, as
follows:
- Memory width (default value dependent on PRGW pin level)
J
8-bit-wide memory
H
H
H
J
16-bit-wide memory
H
H
H
J
STRBx_B3/A−1 and STRBx_B2/A−2 as address pins
STRBx_B0 as byte-enable/chip-select signal
STRBx_B1 unused
STRBx_B3/A−1 as address pin
STRBx_B1 and STRBx_B0 as byte-enable signal
STRBx_B2 unused
32-bit-wide memory
H
STRBx_B3, STRBx_B2, STRBx_B1, and STRBx_B0 as byteenable signals
- Data size
J
J
J
8-bit data, physical address = logical address shift right by 2
16-bit data, physical address = logical address shift right by 1
32-bit data, physical address = logical address
TMS320C32 Enhanced External Memory Interface
10-3
TMS320C32 Memory Overview
IOSTRB can access 32-bit data from 32-bit wide memory. It does not have the
flexibility of STRB0 and STRB1 since it is composed of a single signal:
IOSTRB. IOSTRB bus cycles are different from those of STRB0 and STRB1
and are discussed in Section 10.10. This timing difference accomodates
slower I/O peripherals.
The ’C32 memory interface parallel bus implements three mutually-exclusive
address spaces distinguished via three separate control signals as shown in
Figure 10−1. STRB0 and STRB1 support 8-, 16-, or 32-bit data access in 8-,
16-, 32-bit-wide external memory and 16-, 32-bit program access in 16-/32-bitwide external memory. IOSTRB address space supports 32-bit data/program access in 32-bit-wide external memory. Internally, the ’C32 has a 32-bit architecture,
hence, the memory interface packs and unpacks the data accessed accordingly.
Figure 10−1. Memory Address Spaces
‘C32
STRB0
8-, 16-, 32-bit data in
8-, 16-, 32-bit-wide memory
Program in 16-, 32-bit-wide memory
32-bit
CPU
PRGW pin
STRB1
8-, 16-, 32-bit data in
8-, 16-, 32-bit-wide memory
Program in 16-, 32-bit-wide memory
Strobe
control
registers
Memory
interface
IOSTRB
32-bit data in 32-bit-wide
memory
Program in 32-bit-wide memory
10.2.2 Program Memory Access
The ’C32 supports program execution from 16- or 32-bit external memory
width. The PRGW pin configures the width of the external program memory.
When this pin is pulled high, the ’C32 executes from 16-bit wide memory.
When this pin is pulled low, the ’C32 executes from 32-bit wide memory. For
16-bit wide zero wait-state memory, the ’C32 takes two instruction cycles to
fetch a single 32-bit instruction. During the first cycle the lower 16 bits of the
instruction are fetched. During the second cycle, the upper 16 bits are fetched
and concatenated with the lower 16 bits. 32-bit memory fetches are identical
to those of the ’C30 and ’C31.
10-4
TMS320C32 Memory Overview
The PRGW status bit field of the CPU status (ST) register reflects the setting
of the PRGW pin. Figure 10−2 depicts all the bit fields of the CPU status (ST)
register.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁ
Figure 10−2. Status Register
31−16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
xx
PRGW
status
INT
config
GIE
CC
CE
CF
xx
RM
OVM
LUF
LV
UF
N
Z
V
C
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1) xx = reserved bit, read as 0
The status of the PRGW pin also affects the reset value of the physical memory
width bit fields of the STRB0 and STRB1 bus-control registers. The physical
memory width is set to 32-bit memory width if the PRGW pin is logic low after
the device reset. The physical memory width is set to 16-bit memory width if
the PRGW pin is logic high after the device reset (see Section 10.3 for more
information).
The cycle before and the cycle after changing the PRGW should not
perform a program fetch over the external memory interface.
10.2.3 Data Memory Access
The ’C32 can load and store 8-, 16-, or 32-bit data quantities from and into
memory. Because the CPU has a 32-bit architecture, the device internally
handles all 8-, 16-, or 32-bit data quantities as a 32-bit value. Hence, the external
memory interface handles the conversion between 8- and 16-bit data quantities
to the internal 32-bit representation. The external memory interface also
handles the storage of 32-, 16-, or 8-bit data quantities into 32-, 16-, or 8-bit wide
memories.
10.2.3.1
8-, 16-, or 32-Bit Integers Data Types
The ’C32 supports 8-, 16- or 32-bit integer data quantities. When 8- or 16-bit
integers are read from external memory, the value is loaded into the LSBs of
the register with the MSBs sign-extended or zero-filled. The polarity of the sign
ext/zero-fill bit field of the corresponding STRB control register controls the
sign extension or zero fill (see paragraphs 10.3.1.1 and 10.3.1.2). The 32-bit
integer data access is identical to that of the ’C30 and ’C31.
TMS320C32 Enhanced External Memory Interface
10-5
TMS320C32 Memory Overview
10.2.3.2
16- or 32-Bit Floating-Point Data Types
The ’C32 supports 16- or 32-bit floating point data. For 16-bit floating-point
reads, the eight MSBs are the signed exponent and the eight LSBs are the
signed mantissa (see Section 5.3.2, ’C32 Short Floating-Point Format for
External 16-Bit Data, on page 5-6). When a 16-bit floating-point value is loaded
into a 40-bit register, the external memory interface zero fills the least significant 24 bits of the register. When a 16-bit floating-point value is used as a 32-bit
on-chip input operand, the external memory interface zero fills the 16 LSBs of
the 32-bit input operand. The 32-bit floating-point data access is identical to
that of the ’C30 and ’C31.
10-6
Configuration
10.3 Configuration
To access 8-, 16-, or 32-bit data (types) from 8-, 16-, or 32-bit wide memory, the
memory interface of the ’C32 device uses either strobe STRB0 or STRB1 with
four pins each. These pins serve as byte-enable and/or additional-address pins.
In conjunction with a shifted version of the internal address presented to the external address, the ’C32 can select a single byte from one external memory location
or combine up to four bytes from contiguous memory locations. The behavior of
these pins is controlled by the external memory width and the data type size. The
selected data size also determines the amount of internal-to-physical address
shift. You can assign these values to the ’C32 memory interface through bit fields
in the bus control registers.
10.3.1 External Interface Control Registers
The following sections describe the bus control registers used to manipulate
the byte addressability features of the ’C32. Figure 10−3 shows the external
interface control memory map.
Figure 10−3. Memory-Mapped External Interface Control Registers
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Address
Register
808060h
IOSTRB control
808061h
Reserved
808062h
Reserved
808063h
Reserved
808064h
STRB0 control
808065h
Reserved
808066h
Reserved
808067h
Reserved
808068h
STRB1 control
808069h
Reserved
.
.
.
80806Fh
Reserved
TMS320C32 Enhanced External Memory Interface
10-7
Configuration
10.3.1.1
STRB0 Control Register
The STRB0 control register (Figure 10−4) is a 32-bit register that contains the
control bits for the portion of the external bus memory space that is mapped to
STRB0. The following table lists the register bits with the bit names and functions.
At the system reset, 0F10F8h is written to the STRB0 control register if the PRGW
pin is logic low and 0710F8h is written to the STRB0 control register if the PRGW
pin is logic high.
Figure 10−4. STRB0 Control Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
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Á
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Á
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
31
28
27
24
23
xx
R/W
15
22
21
STRB
switch
STRB
config
R/W
R/W
R/W
13
12 11
xx
8
BNKCMP
19
18
17
Sign ext/ Physical memory
zero fill
width
7
R/W
R/W
5 4
3
16
Data type size
R/W
2
WTCNT
SWW
HIZ
R/W
R/W
R/W
R/W
Notes:
20
1
0
NOHOLD HOLDST
R/W
R
1) R = read, W = write
2) xx = reserved, read as 0
10.3.1.2
STRB1 Control Register
The STRB1 control register (Figure 10−5) is a 32-bit register that contains the
control bits for the portion of the external bus memory space that is mapped
to STRB1. Figure 10−5 shows the register bits with their names and functions.
At system reset, 0F10F8h is written to the STRB1 control register if the PRGW
pin is logic low and 0710F8h is written to the STRB1 control register if the
PRGW pin is logic high.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Á
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Á
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 10−5. STRB1 Control Register
31
24
xx
Notes:
23
21
20
18 17
16 15
xx
Sign ext/
zero fill
Physical
memory
width
Datatype
size
R/W
R/W
R/W
R/W
1) R = read, W = write
2) xx = reserved, read as 0
10-8
19
13
xx
12
8 7
5 4
3 2
BNKCMP
WTCNT
SWW
R/W
R/W
R/W
0
xx
Configuration
The instruction immediately preceding a change in the data-size or
memory-width bit fields should not perform a multicycle store. Do
not follow a change in the data-size or memory-width bit fields with
a store instruction. Also, do not perform a load in the next two
instructions following a change in the data-size or memory-width
bit fields
10.3.1.3
IOSTRB Control Register
The IOSTRB control register (Figure 10−6) is a 32-bit register that contains the
control bits for the portion of the external bus memory space that is mapped to
IOSTRB. Unlike the STRB0 and STRB1, there is no byte-enable signal for the
IOSTRB. The data access through the IOSTRB is always 32-bit. The following
table lists the register bits with the bit names and functions. At the system reset,
0F8h is written to the IOSTRB control register. The IOSTRB timing is identical
to the ‘C30 IOSTRB timing.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Figure 10−6. IOSTRB Control Register
31
16
xx
Notes:
15
12
xx
11
8
xx
7
5
4
3
WTCNT
SWW
R/W
R/W
2
0
xx
1) R = read, W = write
2) xx = reserved, read as 0
Note:
After changing the bit fields of the IOSTRB control register, up to three
instructions are fetched before the IOSTRB bus is reconfigured.
TMS320C32 Enhanced External Memory Interface
10-9
Configuration
Table 10−1 describes the bits in the STRBO, STRB1, and the IOSTRB control
registers.
Table 10−1. STRB0, STRB1, and IOSTRB Control Register Bits
Abbreviation
Reset
Value
Name
Description
HOLDST
0
Hold status bit
This bit signals whether the port is being held (HOLDST = 1),
or is not being held (HOLDST = 1). This status bit is valid
whether the port has been held through hardware or software. (STRB0 control register only)
NOHOLD
0
Port hold signal
NOHOLD allows or disallows the port to be held by an external HOLD signal. When NOHOLD = 1, the ’C3x takes over
the external bus and controls it, regardless of serviced or
pending requests by external devices. No hold acknowledge
(HOLDA) is asserted when a HOLD is received. However, it
is asserted if an internal hold is generated (HIZ = 1). (STRB0
control register only)
HIZ
0
Internal hold
When set (HIZ = 1), the port is put in hold mode. This is
equivalent to the external HOLD signal. By forcing the highimpedance condition, the ’C3x can relinquish the external
memory port through software. HOLDA goes low when the
port is placed in the high impendance state. (STRB0 control
register only)
SWW
11
Software wait mode
In conjunction with WTCNT, this 2-bit field defines the mode
of wait-state generation.
WTCNT
111
Software wait mode
This 3-bit field specifies the number of cycles to use when
in the software wait mode for the generation of internal wait
state. The range is 0 (WTCNT = 0 0 0) to 7 (WTCNT = 111)
H1/H3 cycles.
Bank compare
This 5-bit field specifies the number of MSBs of the address to
be used to define the bank size. (STRB0 and STRB1 control
registers only)
(STRB0 and STRB1
control registers only)
Indicates the size of the data type written in memory.
BNKCMP
Data type size
10-10
10000
11
Bit 17
Bit 16
Data Type Size
0
0
8 bit
0
1
16 bit
1
0
Reserved
1
1
32 bit
Configuration
Table 10−1. STRB0, STRB1, and IOSTRB Control Register Bits (Continued)
Abbreviation
Physical
memory width
Reset
Value
01
or
11
Name
Description
(STRB0 and STRB1
control registers only)
Indicates the size of the physical memory connected to the
device. The “reset” value depends on the status of the
PRGW pin. If the PRGW pin is logic low, the memory width
is configured to 32 bits (= 112). If the PRGW pin is logic high,
the physical memory width is configured to 16 bits (= 012).
This field can have the following values:
Bit 17
Bit 16
Data Type Size
0
0
8 bit
0
1
16 bit (reset value if PRGW = 1)
1
0
Reserved
1
1
32 bit (reset value if PRGW = 0)
Setting the physical memory width field of the STRB0 or
STRB1 control registers changes the functionality of the
STRB0 or STRB1 signals.
-
When the physical memory width field is configured to 32
bits, the corresponding STRBx_B0−STRBx_B3 signals
are configured as byte-enable pins (see Figure 10−10
on page 10-20).
-
When the physical memory width field is configured to
16 bits, the corresponding STRBx_B3/A−1 signal is
configured as an address pin while the STRBx_B0 and
STRBx_B1 signals are configured as byte-enable pins
(see Figure 10−14 on page 10-26).
-
When the physical memory width field is configured to
8 bits, the STRBx_B3/A−3 and STRBx_B2/A−2 signals
are configured as byte-enable pins (see Figure 10−18
on page 10-32).
Once an STRBx_Bx signal is configured as an address pin,
it is active for any external memory access (STRB0, STRB1,
IOSTRB, or external fetch).
TMS320C32 Enhanced External Memory Interface
10-11
Configuration
Table 10−1. STRB0, STRB1, and IOSTRB Control Register Bits (Continued)
Abbreviation
Sign ext/
zero-fill
STRB config
Reset
Value
0
0
Name
Description
(STRB0 and STRB1
control registers only)
Selects the method of converting 8- and 16-bit integer data
into 32-bit integer data when transferring data from external
memory to an internal register or memory location. This field
can have the following values:
STRB configuration
Bit 20
Physical Memory Width
0
8- or 16-bit integer reads are sign-extended to
32 bits (reset value).
1
The MSBs of 8- or 16-bit integer reads are zerofilled to make the number 32 bits.
Activates the STRB0 Bx signals when accessing data from
STRB0 or STRB1 memory spaces. This mode is useful
when accessing a single external memory bank that stores
two different data types, each mapped to a different STRB.
This field can have the following values.
Bit 21
Physical Memory Width
0
STRB0_Bx signals are active for locations
0h−7FFFFFh and 880000h−8FFFFFh.
STRB1_Bx signals are active for locations
900000h−FFFFFFh (reset value).
1
STRB0_Bx signals are active for locations
0h−7FFFFFh, 880000h−8FFFFFh and
900000h−FFFFFFh. STRB1_Bx signals are
active for locations 900000h−FFFFFFh.
A functional representation of this configuration is shown in
Figure 10−7 on page 10-13.
STRB switch
10-12
0
(STRB0 control register only)
Defines whether a single cycle is inserted between back-toback reads when crossing STRB0 or STRB1 to STRB1 to
STRB0 boundaries (switching STRBs). The extra cycle
toggles the strobe signal during back-to-back reads. Otherwise, the strobe remains low during back-to-back reads.
This field has the following values:
Bit 22
Physical Memory Width
0
Does not insert a single cycle between backto-back reads that switch from STRB0 to
STRB1 or vice-versa (reset value).
1
Inserts a single cycle between back-to-back
reads that switch from STRB0 to STRB1 or
vice-versa (reset value).
Configuration
Figure 10−7. STRB Configuration
STRB0_Bx
STRB0_Bx
STRB config
STRB1_Bx
STRB1_Bx
10.3.2 Using Physical Memory Width and Data-Type Size Fields
Consider a ’C32 connected to two banks of external memory. In this configuration, one bank is mapped to STRB0 while the other bank is mapped to STRB1.
The STRB0 bank of memory is 32 bits wide and stores 32-bit data types. The
STRB1 bank of memory is 16 bits wide and stores 16-bit data types. You can
transfer these configurations to the ’C32 by setting the physical memory width
and data-type size fields of the respective STRB0 and STRB1 control registers.
You also must clear the STRB config bit field to 0 since the banks are separate
memories. Note that ‘C32 address pins A23A22A21...A1A0 are connected to the
STRB0 memory bank address pins A23A22A21...A1A0. But ’C32 address pins
A22A21...A1A0 A−1 are connected to the STRB1 memory-bank address pins
A23A22A21...A1A0.
Executing the following code on this device results in the data-access
sequence shown in Table 10−2.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
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ÁÁ
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ÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
1)
2)
3)
4)
5)
6)
7)
8)
9)
LDI
LDI
ADDI
ADDI
ADDI
LDI
LSH
LDI
ADDI
4000h, AR1
*AR1++, R2
*AR1++, R2
*AR1++, R2
*AR1++, R2
900h, AR2
12, AR2
*AR2++, R3
*AR2, R3
;
;
;
;
;
;
;
;
;
AR1 = 4000h
R2 = *4000h and AR1 = AR1 + 1
R2 = R2 + *4001h and AR1 = AR1 + 1
R2 = R2 + *4002h and AR1 = AR1 + 1
R2 = R2 + *4003h and AR1 = AR1 + 1
AR2 = 900h
AR2 = 900000h
R3 = *900000h and AR2 = AR2 + 1
R3 = R3 + 900001h
TMS320C32 Enhanced External Memory Interface
10-13
Configuration
By setting the bit fields of the STRB0 bus control register with a physicalmemory width of 32 bits and a data type size of 32 bits, the external address
referring to the STRB0 location is identical to the internal address used by the
‘C32 CPU. Alternatively, setting the bit fields of the STRB1 bus control register
with a physical memory width of 16-bit and a data-type size of 16-bit, the address presented by the ‘C32 external pins is the internal address shifted right
by one bit with A23 driving A23 and A22. Since the STRB1 memory-bank address
pins A23A22A21...A1A0 are connected to the ‘C32 address pins A22A21...A1A0A−1,
the address seen by the STRB1 memory bank is identical to the ‘C32 CPU
internal address.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 10−2. Data-Access Sequence for a Memory Configuration with Two Banks
Internal
Address Bus
External
Address Pins
Active Strobe Byte Enable
Accessed
Data Pins
(2)
4000h
4000h
STRB0_B0 / B1 / B2 / B3
D31−0
4000h
(3)
4001h
4001h
STRB0_B0 / B1 / B2 / B3
D31−0
4001h
(4)
4002h
4002h
STRB0_B0 / B1 / B2 / B3
D31−0
4002h
(5)
4003h
4003h
STRB0_B0 / B1 / B2 / B3
D31−0
4003h
(8)
900000h
C80000h
STRB1_B0 / B1 and
STRB1_B3 / A−1 = 0
D15−0
900000h
(9)
900001h
C80001h
STRB1_B0 / B1 and
D15−0
900001h
Instruction #
STRB1_B3 / A−1 = 1
The ability of the ‘C32 device to select a single byte from a single external
memory location or combinations of bytes from several contiguous memory
locations dictates that the internal address seen by the CPU correspond to a
shifted version of the address presented to the external pins. The ’C32 external
memory interface handles this conversion automatically as long as you configure
the bus control register to match the external memory configuration present in
your hardware implementation.
As seen in Figure 2−8 on page 2-20, ’C32 handles nine different memory
access cases. The following sections discuss these cases in detail.
10-14
Programmable Wait States
10.4 Programmable Wait States
The ’C3x has its own internal software-configurable ready-generation capability
for each strobe. This software wait-state generator is controlled by configuring
two fields in the primary or expansion bus interface control registers. Use the
WTCNT field to specify the number of software wait states to generate and use
the SWW field to select one of the following four modes of wait-state generation:
- External RDY. Wait states are generated solely by the external RDY line
ignoring software wait states.
- WTCNT-generated RDYwtcnt. Wait states generated solely by the software
wait-state generator ignoring external RDY signals.
- Logical-AND of RDY and RDYwtcnt. Wait states generated with a logical
AND of internal and external ready signals. Both signals must occur.
- Logical-OR of RDY and RDYwtcnt. Wait states are generated with a logical
OR of internal and external ready signals. Either signal can generate ready.
The four modes are used to generate the internal ready signal, RDYint, that
controls accesses. As long as RDYint = 1, the current external access is
delayed. When RDYint = 0, the current access completes. Since the use of
programmable wait states for both external interfaces is identical, only the
primary bus interface is described in the following paragraphs.
RDYwtcnt is an internally generated ready signal. When an external access is
begun, the value in WTCNT is loaded into a counter. WTCNT can be any value
from 0 through 7. The counter is decremented every H1/H3 clock cycle until
it becomes 0. Once the counter is set to 0, it remains set to 0 until the next
access. While the counter is nonzero, RDYwtcnt = 1. While the counter is 0,
RDYwtcnt = 0.
Table 10−3 shows the truth table for each value of SWW and the different
combinations of RDY, RDYwtcnt, and RDYint.
Note:
At reset, the ‘C3x is programmed with seven wait states for each external
memory access. These wait states are inserted to ensure the system can function with slow memories. To maximize system performance when accessing
external memories, you need to decrease the number of wait states.
After changing wait states, up to three instructions will be fetched before the
change in the wait-state occurs.
TMS320C32 Enhanced External Memory Interface
10-15
Programmable Wait States
Table 10−3. Wait-State Generation
Inputs
Output
SWW Bit
Field
/RDYext
/RDYwtcnt
/RDYint
00
0
x
0
1
x
1
x
0
0
x
1
1
0
0
0
0
1
0
1
0
0
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
01
10
11
10-16
Functional Description
Wait until external RDY is signaled
Wait until internal wait state generator counts
down to 0
Wait until first signal: external RDY or the
internal wait state generator (logical OR)
Wait until both external RDY is signaled and
wait state generator counts down to 0 (logical
AND)
Programmable Bank Switching
10.5 Programmable Bank Switching
Programmable bank switching allows you to switch between external memory
banks without having to insert wait states externally due to memories that require
several cycles to turn off. Bank switching is implemented on STRB0 and STRB1
only.
The size of a bank is determined by the number of bits specified to be examined
on the BNKCMP field of the primary bus control register. For example, if
BNKCMP = 16, the 16 MSBs of the address are used to define a bank (see
Figure 9−4). Since addresses are 24 bits, the bank size is specified by the eight
LSBs, yielding a bank size of 256 words. If BNKCMP ≥ 16, only the 16 MSBs
are compared. Bank sizes from 28 = 256 to 224 = 16M are allowed. Table 9−6
summarizes the relationship between BNKCMP, the address bits used to define
a bank, and the resulting bank size.
Figure 10−8. BNKCMP Example
24-bit address
23
8
Number of bits to compare
7
0
Defines bank size
Table 10−4. BNKCMP and Bank Size
BNKCMP
MSBs Defining a Bank
Bank Size (32-Bit Words)
00000
None
224 = 16M
223 = 8M
222 = 4M
00001
23
00010
23−22
00011
23−21
00100
23−20
00101
23−19
00110
23−18
00111
23−17
01000
23−16
01001
23−15
01010
23−14
01011
23−13
01100
23−12
01101
23−11
221 = 2M
220 = 1M
219 = 512K
218 = 256K
217 = 128K
216 = 64K
215 = 32K
214 = 16K
213 = 8K
212 = 4K
211 = 2K
01110
23−10
01111
23−9
10000
23−8
210 = 1K
29 = 512
28 = 256
10001−11111
Reserved
Undefined
TMS320C32 Enhanced External Memory Interface
10-17
Programmable Bank Switching
The ’C3x has an internal register that contains the MSBs (as defined by the
BNKCMP field) of the last address used for a read or write over the primary interface. At reset, the register bits are set to 0. If the MSBs of the address being used
for the current primary interface read do not match those contained in this internal register, a read cycle is not asserted for one H1/H3 clock cycle. During this
extra clock cycle, the address bus switches over to the new address, but STRB
is inactive (high). The contents of the internal register are replaced with the
MSBs being used for the current read of the current address. If the MSBs of the
address being used for the current read match the bits in the register, a normal
read cycle takes place.
If repeated reads are performed from the same memory bank, no extra cycles
are inserted. When a read is performed from a different memory bank, memory
conflicts are avoided by the insertion of an extra cycle. This feature can be
disabled by setting BNKCMP to 0. The insertion of the extra cycle occurs only
when a read is performed. The changing of the MSBs in the internal register
occurs for all reads and writes over the primary interface.
Figure 9−5 shows the addition of an inactive cycle when switches between
banks of memory occur.
Figure 10−9. Bank-Switching Example
H3
H1
STRB
R/W
A
D
Read
Read
RDY
Extra
cycle
10-18
Read
Programmable Bank Switching
Note:
After changing BNKCMP, up to three instructions are fetched before the
change in bank size occurs.
TMS320C32 Enhanced External Memory Interface
10-19
32-Bit-Wide Memory Interface
10.6 32-Bit-Wide Memory Interface
The ’C32 memory interface to 32-bit-wide external memory uses STRBx_B3
through STRBx_B0 pins as strobe-byte-enable pins as shown in Figure 10−10.
In this manner, the ’C32 can read from, or write to, a single 32-, 16-, or 8-bit value
from the external 32-bit-wide memory.
Figure 10−10. TMS320C32 External Memory Interface for 32-Bit SRAMs
’C32
AXX
AXX
AXX
AXX
AXX
R/W
WE
WE
WE
WE
CS
CS
CS
CS
I/O(7-0)
I/O(7-0)
I/O(7-0)
I/O(7-0)
STRBx_B3
STRBx_B2
STRBx_B1
STRBx_B0
D(31-24)
D(23-16)
D(15-8)
D(7-0)
Case 1: 32-Bit-Wide Memory With 8-Bit Data-Type Size
When the data-type size is 8 bits, the ’C32 shifts the internal address two bits
to the right before presenting it to the external-address pins. In this shift, the
memory interface copies the value of the internal-address A23 to the externaladdress pins A23, A22, and A21. The memory interface activates the STRBx_B3
through STRBx_B0 pins according to the value of the internal address bits A1
and A0 as shown in Table 10−5. Figure 10−11 shows a functional diagram of
the memory interface for 32-bit-wide memory with an 8-bit data-type size.
10-20
32-Bit-Wide Memory Interface
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 10−5. Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-Type Size
Internal
A1
Internal
A0
Active Strobe
Byte Enable
0
0
STRBx_B0
0
1
STRBx_B1
1
0
STRBx_B2
1
1
STRBx_B3
Figure 10−11. Functional Diagram for 8-Bit Data-Type Size and 32-Bit External-Memory
Width
’C32
Memory interface
A 23
A 22
A 23
A 22
A 21
A 21
A 20
.
.
.
A2
A1
A 20
A 19
A0
A0
A 18
.
.
.
11
10
01
00
D(31−24)
D(23−16)
D(15−8)
D(7−0)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
A21
A20
A21
A20
A21
A20
A21
A20
A19
A18
.
.
.
A0
A19
A18
.
.
.
A0
A19
A18
.
.
.
A0
CS
I/O(7−0)
CS
I/O(7−0)
CS
I/O(7−0)
A19
A18
.
.
.
A0
CS
I/O(7−0)
STRBx_B3
STRBx_B2
STRBx_B1
STRBx_B0
TMS320C32 Enhanced External Memory Interface
10-21
32-Bit-Wide Memory Interface
For example, reading from or writing to memory locations 90 4000h to
90 4004h involves the pins listed in Table 10−6.
Table 10−6. Example of 8-Bit Data-Type Size
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Internal
Address Bus
External
Address Pins
Active Strobe
Byte Enable
Accessed
Data Pins
904000h
E41000h
STRB1_B0
D7−0
904001h
E41000h
STRB1_B1
D15−8
904002h
E41000h
STRB1_B2
D23−16
904003h
E41000h
STRB1_B3
D31−24
904004h
E41001h
STRB1_B0
D7−0
Case 2: 32-Bit-Wide Memory With 16-Bit Data-Type Size
When the data-type size is 16 bits, the ’C32 shifts the internal address one bit
to the right before presenting it to the external-address pins. In this shift, the
memory interface copies the value of the internal-address A23 to the externaladdress pins A23 and A22. Also, the memory interface activates the STRBX-B3
through STRBx_B0 pins according to the value of the internal address bit A0
as shown in Table 10−7. Figure 10−12 shows a functional diagram of the
memory interface for 32-bit-wide memory with 16-bit data-type size.
Table 10−7. Strobe Byte-Enable for 32-Bit-Wide Memory With 16-Bit Data-Type Size
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
10-22
Internal A0
Active Strobe Byte Enable
0
STRBx_B1 and STRBx_B0
1
STRBx_B3 and STRBx_B2
32-Bit-Wide Memory Interface
Figure 10−12. Functional Diagram for 16-Bit Data-Type Size and 32-Bit External-Memory
Width
’C32
’C32’s core address bus
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Memory interface
A23
A22
A21
A20
.
.
.
A2
A1
A0
A23
A22
A21
A20
A19
.
.
.
A1
A0
1
0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
A22
A21
A20
A19
.
.
.
A1
A0
CS
I/O(7-0)
A22
A21
A20
A19
.
.
.
A1
A0
CS
I/O(7-0)
A22
A21
A20
A19
.
.
.
A1
A0
CS
I/O(7-0)
A22
A21
A20
A19
.
.
.
A1
A0
CS
I/O(7-0)
STRBx_B3
STRBx_B2
STRBx_B1
STRBx_B0
D(31-24)
D(23-16)
D(15-8)
D(7-0)
For example, reading or writing to memory locations 904000h to 904004h
involves the pins listed in Table 10−8.
Table 10−8. Example of 16-Bit Data-Type Size and 32-Bit-Wide External Memory
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Internal
Address Bus
External
Address Pins
Active Strobe Byte Enable
Accessed
Data Pins
904000h
C82000h
STRB1_B1 and STRB1_B0
D15 −0
904001h
C82000h
STRB1_B3 and STRB1_B2
D31 −16
904002h
C82001h
STRB1_B1 and STRB1_B0
D15 −0
904003h
C82001h
STRB1_B3 and STRB1_B2
D31 −16
904004h
C82002h
STRB1_B1 and STRB1_B0
D15 −0
TMS320C32 Enhanced External Memory Interface
10-23
32-Bit-Wide Memory Interface
Case 3: 32-Bit-Wide Memory With 32-Bit Data-Type Size
When the data size is 32 bits, the ’C32 does not shift the internal address
before presenting it to the external address pins. In this case, the memory
interface copies the value of the internal address bus to the respective externaladdress pins. Also, the memory interface activates STRBx_B3 through
STRBx_B0 pins during accesses. Figure 10−13 shows a functional diagram
of the memory interface for 32-bit-wide memory with 32-bit data size.
Figure 10−13. Functional Diagram for 32-Bit Data Size and 32-Bit External-Memory Width
’C32
’C32’s core address bus
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
Memory interface
A23
A22
A21
A20
.
.
.
A2
A1
A0
A23
A22
A21
A20
.
.
.
A2
A1
A0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
STRBx_B3
STRBx_B2
STRBx_B1
STRBx_B0
STRBx logic
10-24
D(31-24)
D(23-16)
D(15-8)
D(7-0)
A23
A22
A21
A20
.
.
.
A2
A1
A0
CS
I/O(7-0)
A23
A22
A21
A20
.
.
.
A2
A1
A0
CS
I/O(7-0)
A23
A22
A21
A20
.
.
.
A2
A1
A0
CS
I/O(7-0)
A23
A22
A21
A20
.
.
.
A2
A1
A0
CS
I/O(7-0)
32-Bit-Wide Memory Interface
For example, reading or writing to memory locations 904000h to 904004h
involves the pins listed in Table 10−9.
Table 10−9. Example of 32-Bit-Wide Memory With 32-Bit Data-Type Size
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Internal
Address Bus
External
Address Pins
904000h
904000h
STRB1_B0, STRB1_B1,
STRB1_B2, and STRB1_B3
D31−0
904001h
904001h
STRB1_B0, STRB1_B1,
STRB1_B2, and STRB1_B3
D31−0
904002h
904002h
STRB1_B0, STRB1_B1,
STRB1_B2, and STRB1_B3
D31−0
904003h
904003h
STRB1_B0, STRB1_B1,
STRB1_B2, and STRB1_B3
D31−0
904004h
904004h
STRB1_B0, STRB1_B1,
STRB1_B2, and STRB1_B3
D31−0
Active Strobe Byte Enable
TMS320C32 Enhanced External Memory Interface
Accessed
Data Pins
10-25
16-Bit-Wide Memory Interface
10.7 16-Bit-Wide Memory Interface
The ’C32 memory interface to 16-bit-wide external memory uses STRBx_B3 pin
as an additional address pin, A−1, while using STRBx_B0 and STRBx_B1 as
strobe byte-enable pins as shown in Figure 10−14. Note that the externalmemory address pins are connected to the ’C32 address pins A22A21...A1A0A−1.
In this manner, the ’C32 can read/write a single 32-, 16-, or 8-bit value from the
external 16-bit-wide memory.
Figure 10−14. External-Memory Interface for 16-Bit SRAMs
’C32
A23
A22
A21
.
.
.
A1
A0
STRBx_B3/A−1
R/W
STRBx_B2
STRBx_B1
STRBx_B0
D(31-24)
D(23-16)
D(15-8)
D(7-0)
A23
A22
.
.
.
A2
A1
A0
WE
CS
I/O(7-0)
A23
A22
.
.
.
A2
A1
A0
WE
CS
I/O(7-0)
Case 4: 16-Bit-Wide Memory With 8-Bit Data-Type Size
When the data type size is 8 bits, the ’C32 shifts the internal address two bits
to the right before presenting it to the external-address pins. In this shift, the
memory interface copies the value of the internal-address A23 to the externaladdress pins A23, A22, and A21. The memory interface also copies the value
of the internal-address A1 to the external STRBx_B3/ A−1 pin. Furthermore, the
memory interface activates the STRBx_B1 and STRBx_B0 pins according to
the value of the internal address bit A0 as shown in Table 10−10. Figure 10−15
shows a functional diagram of the memory interface for 16-bit-wide memory
with 8-bit data-type size.
10-26
16-Bit-Wide Memory Interface
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 10−10. Strobe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bit Data-Type Size
Internal A0
Active Strobe Byte Enable
0
STRBx_B0
1
STRBx_B1
Figure 10−15. Functional Diagram for 8-Bit Data-Type Size and 16-Bit External-Memory Width
’C32
’C32’s core address bus
Memory interface
1
A23
A22
A21
A20
A19
A18
.
.
.
A0
STRBx_B3/A–1
STRBx_B1
0
STRBx_B0
A23
A22
A21
A20
.
.
.
A2
A1
A0
A22
A21
A20
A19
.
.
.
A1
A0
CS
I/O(7-0)
A22
A21
A20
A19
.
.
.
A1
A0
CS
I/O(7-0)
D(15-8)
D(7-0)
For example, reading or writing to memory locations 4000h to 4004h involves
the pins listed in Table 10−11.
TMS320C32 Enhanced External Memory Interface
10-27
16-Bit-Wide Memory Interface
Table 10−11. Example of 8-Bit Data-Type Size and 16-Bit-Wide External Memory
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Internal
Address Bus
External
Address Pins
4000h
1000h
0
STRB0_B0
D7 −0
4001h
1000h
0
STRB0_B1
D15 −8
4002h
1000h
1
STRB0_B0
D7 −0
4003h
1000h
1
STRB0_B1
D15 −8
4004h
1001h
0
STRB0_B0
D7 −0
STRB0_B3/A−1
Active Strobe Byte Enable
Accessed
Data Pins
Case 5: 16-Bit-Wide Memory With 16-Bit Data-Type Size
When the data-type size is 16 bits, the ’C32 shifts the internal address one bit
to the right before presenting it to the external address pins. In this shift, the
memory interface copies the value of the internal-address A23 to the externaladdress pins A23 and A22. Also, the memory interface copies the value of the
internal-address A1 to the external STRBx_B3/ A−1 pin. Moreover, the memory
interface activates the STRBx_B1 and STRBx_B0 during accesses.
Figure 10−16 shows a functional diagram of the memory interface for 16-bitwide memory with 16-bit data-type size.
10-28
16-Bit-Wide Memory Interface
Figure 10−16. Functional Diagram for 16-Bit Data-Type Size and 16-Bit External-Memory
Width
’C32
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
’C32’s core address bus
Memory interface
A23
A22
A21
A20
.
.
.
A2
A1
A0
A23
A22
A21
A20
A19
.
.
.
A1
A0
STRBx_B3/A–1
ÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
A23
A22
A21
A20
.
.
.
A2
A1
A0
CS
I/O(7-0)
A23
A22
A21
A20
.
.
.
A2
A1
A0
CS
I/O(7-0)
STRBx_B1
STRBx_B0
STRBx logic
D(15-8)
D(7-0)
For example, reading or writing to memory locations 4000h to 4004h involves
the pins listed in Table 10−12.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 10−12. Example of 16-Bit-Wide Memory With 16-Bit Data-Type Size
Internal
Address Bus
External
Address Pins
STRB0_B3 / A−1
Active Strobe Byte Enable
Accessed
Data Pins
4000h
2000h
0
STRB0_B0 and STRB0_B1
D15−0
4001h
2000h
1
STRB0_B0 and STRB0_B1
D15−0
4002h
2001h
0
STRB0_B0 and STRB0_B1
D15−0
4003h
2001h
1
STRB0_B0 and STRB0_B1
D15−0
4004h
2002h
0
STRB0_B0 and STRB0_B1
D15−0
TMS320C32 Enhanced External Memory Interface
10-29
16-Bit-Wide Memory Interface
Case 6: 16-Bit-Wide Memory with 32-Bit Data-Type Size
When the data type size is 32 bits, the ’C32 does not shift the internal address
before presenting it to the external address pins. In this case, the memory
interface copies the value of the internal address bus to the respective external
address pins. The memory interface also toggles STRBx_B3/ A−1 twice to
perform two 16-bit memory accesses. In the consecutive memory accesses,
the memory interface activates STRBx_B1 and STRBx_B0. In summary, the
memory interface seems to add one wait state to the 32-bit data access.
Figure 10−17 depicts a functional diagram of the memory interface for 16-bit
wide memory with 32-bit data type size.
Figure 10−17. Functional Diagram for 32-Bit Data-Type Size and 16-Bit External-Memory
Width
’C32
’C32’s core address bus
Memory interface
A23
A22
A21
A20
.
.
.
A2
A1
A0
toggle
A23
A22
A21
A20
.
.
.
A2
A1
A0
STRBx_B3/A–1
A24
A23
A22
A21
.
.
.
A3
A2
A1
A0
CS
I/O(7-0)
A24
A23
A22
A21
.
.
.
A3
A2
A1
A0
CS
I/O(7-0)
STRBx_B1
STRBx_B0
STRBx logic
D(15-8)
D(7-0)
For example, reading or writing to memory locations 4000h to 4004h involves
the pins listed in Table 10−13.
10-30
16-Bit-Wide Memory Interface
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 10−13. Example of 16-Bit-Wide Memory With 32-Bit Data-Type Size
Internal
Address Bus
External
Address Pins
4000h
4001h
4002h
4003h
4004h
STRB0_B3 / A−1
Active Strobe Byte Enable
Accessed
Data Pins
4000h
0
STRB0_B0 and STRB0_B1
D15−0
4000h
1
STRB0_B0 and STRB0_B1
D15−0
4001h
0
STRB0_B0 and STRB0_B1
D15−0
4001h
1
STRB0_B0 and STRB0_B1
D15−0
4002h
0
STRB0_B0 and STRB0_B1
D15−0
4002h
1
STRB0_B0 and STRB0_B1
D15−0
4003h
0
STRB0_B0 and STRB0_B1
D15−0
4003h
1
STRB0_B0 and STRB0_B1
D15−0
4004h
0
STRB0_B0 and STRB0_B1
D15−0
4004h
1
STRB0_B0 and STRB0_B1
D15−0
TMS320C32 Enhanced External Memory Interface
10-31
8-Bit-Wide Memory Interface
10.8 8-Bit-Wide Memory Interface
’C32 memory interface to an 8-bit wide external memory uses STRBx_B3 and
STRBx_B2 pins as additional address pins, A−1 and A−2, respectively, while
using STRBx_B0 as strobe byte-enable pin as shown in Figure 10−18. The
external-memory address pins are connected to the ’C32’s address pins
A21A20...A1A0A−1A−2. In this manner, the ’C32 can read/write a single 32-, 16-,
or 8-bit value from the external 8-bit-wide memory.
Figure 10−18. External Memory Interface for 8-Bit SRAMs
’C32
A23
A22
A21
.
.
A1
A0
STRBx_B3/A−1
STRBx_B2/A−2
R/W
A23
.
.
A3
A2
A1
A0
WE
CS
I/O(7-0)
STRBx_B1
STRBx_B0
D(31-24)
D(23-16)
D(15-8)
D(7-0)
Case 7: 8-Bit-Wide Memory With 8-Bit Data-Type Size
Similarly to case 4, the ’C32 shifts the internal address two bits to the right
before presenting it to the external-address pins when the data type is 8-bit. As
in case 4, the memory interface copies the value of the internal-address A23 to
the external-address pins A23, A22, and A21. But in case 7, the memory interface
also copies the value of the internal-address A1 to the external STRBx_B3/A−1
pin and the value of A0 to the external STRBx_B2/A−2. Moreover, the memory
interface only activates the STRBx_B0 pin during the external memory access.
Figure 10−19 shows a functional diagram of the memory interface for 8-bit-wide
memory with an 8-bit data-type size.
10-32
8-Bit-Wide Memory Interface
Figure 10−19. Functional Diagram for 8-Bit Data-Type Size and 8-Bit External-Memory
Width
’C32
’C32’s core address bus
Memory interface
A23
A22
A21
A20
A19
A18
.
.
.
A0
STRBx_B3/A–1
STRBx_B2/A–2
A23
A22
A21
A20
.
.
.
A2
A1
A0
STRBx
logic
STRBx_B0
A23
A22
A21
A20
.
.
.
A2
A1
A0
CS
I/O(7-0)
D(7-0)
For example, reading or writing to memory locations A04000h to A04004h
involves the pins listed in Table 10−14.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 10−14. Example of 8-Bit-Wide Memory With 8-Bit Data-Type Size
Internal
Address Bus
External
Address Pins
Active Strobe
Byte Enable
Accessed
Data Pins
A04000h
0
STRB1_B0
D7 −0
0
1
STRB1_B0
D7 −0
E81000h
1
0
STRB1_B0
D7 −0
A04003h
E81000h
1
1
STRB1_B0
D7 −0
A04004h
E81001h
0
0
STRB1_B0
D7 −0
STRB0_B3 / A−1
STRB0_B3 / A−2
E81000h
0
A04001h
E81000h
A04002h
TMS320C32 Enhanced External Memory Interface
10-33
8-Bit-Wide Memory Interface
Case 8: 8-Bit Wide Memory With 16-Bit Data-Type Size
When the data-type size is 16 bits, the ‘C32 shifts the internal address one bit
to the right before presenting it to the external-address pins. In this shift, the
memory interface copies the value of the internal-address A23 to the externaladdress pins A23 and A22. Also, the memory interface copies the value of the
internal-address A0 to the external STRBx_B3 / A−1 pin. Furthermore, the
memory interface toggles STRBx_B2 / A−2 twice to perform two 8-bit memory
accesses. Moreover, the memory interface activates the STRBx_B0 during
accesses. In summary, the memory interface adds one wait state to the 16-bit
data access. Figure 10−20 shows a functional diagram of the memory interface for 8-bit-wide memory with 16-bit data-type size.
Figure 10−20. Functional Diagram for 16-Bit Data-Type Size and 8-Bit External-Memory
Width
’C32
’C32’s core address bus
Memory interface
A23
A22
A21
A20
.
.
.
A2
A1
A0
toggle
STRBx
logic
A23
A22
A21
A20
A19
.
.
.
A1
A0
STRBx_B3/A-1
STRBx_B2/A-2
STRBx_B0
D(7−0)
10-34
A24
A23
A22
A21
.
.
.
A3
A2
A1
A0
CS
I/O(7−0)
8-Bit-Wide Memory Interface
For example, reading or writing to memory locations A04000h to A04002h
involves the pins listed in Table 10−15.
Table 10−15. Example of 8-Bit-Wide Memory With 16-Bit Data-Type Size
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Internal
Address Bus
External
Address Pins
A04000h
Active Strobe
Byte Enable
Accessed
Data Pins
0
1
STRB1_B0
STRB1_B0
D7−0
D7−0
1
1
0
1
STRB1_B0
STRB1_B0
D7−0
D7−0
0
0
0
1
STRB1_B0
STRB1_B0
D7−0
D7−0
STRB0_B3 / A−1
STRB0_B3 / A−2
D02000h
D02000h
0
0
A04001h
D02001h
D02001h
A04002h
D02002h
D02002h
Case 9: 8-Bit-Wide Memory With 32-Bit Data-Type Size
When the data-type size is 32 bits, the ‘C32 does not shift the internal address
before presenting it to the external-address pins. In this case, the memory
interface copies the value of the internal-address bus to the respective externaladdress pins. The memory interface also toggles STRBx_B3/ A−1 and
STRBx_B2/ A−2 to perform four 8-bit memory accesses. In the consecutive
memory accesses, the memory interface activates STRBx_B0. In summary,
the memory interface adds three wait states to the 32-bit data access.
Figure 10−21 shows a functional diagram of the memory interface for 8-bitwide memory with 32-bit data-type size.
TMS320C32 Enhanced External Memory Interface
10-35
8-Bit-Wide Memory Interface
Figure 10−21. Functional Diagram for 32-Bit Data-Type Size and 8-Bit External-Memory
Width
’C32
’C32’s core address bus
Memory interface
A23
A22
A21
A20
.
.
.
A2
A1
A0
A23
A22
A21
A20
.
.
.
A1
A1
A0
STRBx
logic
toggle
toggle
STRBx_B3/A−1
STRBx_B2/A−2
STRBx_B0
A25
A24
A23
A22
.
.
.
A.4
A3
A2
A1
A0
CS
I / O(7 −0)
D(7 −0)
10-36
8-Bit-Wide Memory Interface
For example, reading or writing to memory locations A04000h to A04001h
involves the pins listed in Table 10−16.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 10−16. Example of 32-Bit Data-Type Size and 8-Bit-Wide Memory
Internal
Address Bus
External
Address Pins
A04000h
A04001h
Active Strobe
Byte Enable
Accessed
Data Pins
0
STRB1_B0
D7−0
0
1
STRB1_B0
D7−0
A04000h
1
0
STRB1_B0
D7−0
A04000h
1
1
STRB1_B0
D7−0
A04001h
0
0
STRB1_B0
D7−0
A04001h
0
1
STRB1_B0
D7−0
A04001h
1
0
STRB1_B0
D7−0
A04001h
1
1
STRB1_B0
D7−0
STRB0_B3 / A−1
STRB0_B3 / A−2
A04000h
0
A04000h
TMS320C32 Enhanced External Memory Interface
10-37
External Ready Timing Improvement
10.9 External Ready Timing Improvement
The ready (RDY) timing should relate to the H1 low signal as shown in
Figure 10−22. This is equivalent to the ’C4x ready timing, which increases the
time between valid address and the sampling of RDY. This facilitates the memory
hardware interface by allowing a longer address decode-circuit response time to
generate a ready signal.
Figure 10−22. RDY Timing for Memory Read
H3
H1
STRBx
R/W
A
D
Address
Data
tsu(RDY)
RDY
Do not change the RDY signal during its setup time [tsu(RDY)].
10-38
Bus Timing
10.10 Bus Timing
This section discusses functional timing of operations on the external memory
bus. Detailed timing specifications are contained in the TMS320C32 Data
Sheet. The timing of STRB0 and STRB1 bus cycles is identical and discussed
in subsection 10.10.1. The abbreviation STRBx is used in references that pertain equally to STRB0 and STRB1. The IOSTRB bus cycles are timed differently
and are discussed in subsection 10.10.2.
10.10.1 STRB0 and STRB1 Bus Cycles
All bus cycles comprise integral numbers of H1 clock cycles. One H1 cycle is
defined from one falling edge of H1 to the next falling edge of H1. For full speed
(zero wait-state) accesses on STRB0 and STRB1, writes take two H1 cycles
and reads take one cycle. However, if the read immediately follows a write, the
read takes two cycles. Writes to internal memory take one cycle if no other
accesses to that interface are in progress. The following discussion pertains
to zero wait-state accesses, unless otherwise specified.
The STRBx signal is low for the active portion of both reads and writes (one
H1 cycle). Additionally, before and after the active portions of writes only
(STRBx low), there is a transition of one H1 cycle. During this transition cycle
the following might occur:
- STRBx is high.
- If required, R / W changes state on the rising edge of H1.
- If required, address changes on the rising edge of H1 if the previous H1
cycle performed a write. If the previous H1 cycle performed a read,
address changes on the falling edge of H1.
Figure 10−23 illustrates a zero wait-state read-read-write sequence for STRBx
active. The data is read as late in the cycle as possible to allow for the maximum
access time from address valid. Although external writes take two cycles, writes
to internal memory take one cycle if no other accesses to that interface are in
progress. Similar to typical external interfaces, the R/W signal does not change
until STRB0 and STRB1 are deactivated.
TMS320C32 Enhanced External Memory Interface
10-39
Bus Timing
Figure 10−23. Read-Read-Write Sequence for STRBx Active
H3
H1
STRBx
R/W
A
D
Read
Read
Write
RDY
Figure 10−24 shows a zero wait-state write-write-read sequence for STRBx
active. During back-to-back writes, the data is valid when STRBx changes for the
first write, but for subsequent writes the data is valid when the address changes.
Figure 10−24. Write-Write-Read Sequence for STRBx Active
H3
H1
STRBx
R/W
A
D
RDY
10-40
Write
Write
Read
Bus Timing
Figure 10−25 shows a one wait-state read sequence and Figure 10−26 shows
the write sequence for STRBx active. On the first H1 cycle, RDY is high; therefore,
the read or write sequence is extended for one extra cycle. On the second H1
cycle, RDY is low and the read or write sequence is terminated.
Figure 10−25. One Wait-State Read Sequence for STRBx Active
H3
H1
STRBx
R/W
A
D
Read
RDY
Extra cycle
TMS320C32 Enhanced External Memory Interface
10-41
Bus Timing
Figure 10−26. One Wait-State Write Sequence for STRBx Active
H3
H1
STRBx
R/W
A
D
Write
RDY
Extra cycle
10.10.2 IOSTRB Bus Cycles
In contrast to STRB0 and STRB1 bus cycles, IOSTRB full speed (zero waitstate) reads and writes consume two H1 cycles. During these cycles, the
IOSTRB signal is low from the rising edge of the first H1 cycle to the rising edge
of the second H1 cycle. Also, the address changes on the falling edge of the
first H1 cycle and R/ W changes state on the falling edge of H1. This provides
a valid address to peripherals that may change their status bits when read or
written while IOSTRB is active. Moreover, the IOSTRB signal is high between
IOSTRB read and write cycles.
10-42
Bus Timing
Figure 10−27 illustrates a zero wait-state read and write sequence for IOSTRB
active. During writes, the data is valid when IOSTRB changes.
Figure 10−27. Zero Wait-State Read and Write Sequence for IOSTRB Active
H3
H1
IOSTRB
R/W
A
D
Read
Write
RDY
Figure 10−28 depicts a one wait-state read sequence for IOSTRB active.
Figure 10−29 shows a one wait-state write sequence for IOSTRB active. For
each wait-state added, IOSTRB, R/W, and A are extended for one extra clock
cycle. Writes hold the data on the bus for one extra clock cycle. RDY is sampled
on each extra cycle and the sequence is terminated when RDY is low.
TMS320C32 Enhanced External Memory Interface
10-43
Bus Timing
Figure 10−28. One Wait-State Read Sequence for IOSTRB Active
H3
H1
IOSTRB
R/W
A
Read
D
RDY
Extra cycle
Figure 10−29. One Wait-State Write Sequence for IOSTRB Active
H3
H1
IOSTRB
R/W
A
D
Write
RDY
Extra cycle
Figure 10−30 and Figure 10−31 illustrate the transitions between STRBx
reads and IOSTRB writes and reads, respectively. In these transitions, the address changes on the falling edge of the H1 cycle.
10-44
Bus Timing
Figure 10−30. STRBx Read and IOSTRB Write
H3
H1
STRB0,1
IOSTRB
R/W
A
D
Read
I/O Write
RDY
Figure 10−31. STRBx Read and IOSTRB Read
H3
H1
STRB0,1
IOSTRB
R/W
A
D
Read
I/O read
RDY
TMS320C32 Enhanced External Memory Interface
10-45
Bus Timing
Figure 10−32 and Figure 10−33 illustrate the transitions between STRBx
writes and IOSTRB writes and reads, respectively. In these transitions, the
address changes on the falling edge of the H3 cycle.
Figure 10−32. STRBx Write and IOSTRB Write
H3
H1
STRBx
IOSTRB
R/W
A
D
Write
I/O write
RDY
Figure 10−33. STRBx Write and IOSTRB Read
H3
H1
STRBx
IOSTRB
R/W
A
D
RDY
10-46
Write
I/O read
Bus Timing
Figure 10−34 through Figure 10−37 show the transitions between IOSTRB
writes/reads and STRBx writes/reads. In these transitions, the address
changes on the rising edge of the H3 cycle.
Figure 10−34. IOSTRB Write and STRBx Write
H3
H1
STRBx
IOSTRB
R/W
A
D
I/O write
Write
RDY
TMS320C32 Enhanced External Memory Interface
10-47
Bus Timing
Figure 10−35. IOSTRB Write and STRBx Read
H3
H1
STRBx
IOSTRB
R/W
A
D
I/O Write
Read
RDY
Figure 10−36. IOSTRB Read and STRBx Write
H3
H1
STRBx
IOSTRB
R/W
A
D
RDY
10-48
I/O read
Write
Bus Timing
Figure 10−37. IOSTRB Read and STRBx Read
H3
H1
STRBx
IOSTRB
R/W
A
D
I/O Read
Read
RDY
Figure 10−38 through Figure 10−40 illustrate the transitions between reads
and writes.
TMS320C32 Enhanced External Memory Interface
10-49
Bus Timing
Figure 10−38. IOSTRB Write and Read
H3
H1
IOSTRB
R/W
A
D
I/O write
I/O read
RDY
Figure 10−39. IOSTRB Write and Write
H3
H1
IOSTRB
R/W
A
D
RDY
10-50
I/O write
I/O write
Bus Timing
Figure 10−40. IOSTRB Read and Read
H3
H1
IOSTRB
R/W
A
D
I/O Read
I/O Read
RDY
10.10.3 Inactive Bus States
Figure 10−41 and Figure 10−42 show the signal states when a bus becomes
inactive after an IOSTRB or STRBx, respectively. The strobes (STRB0,
STRB1, IOSTRB, and R/ W) are deasserted going to a high level. The address
bus preserves the last value and the ready signal (RDY) is ignored.
Figure 10−41. Inactive Bus States Following IOSTRB Bus Cycle
H3
H1
IOSTRB
R/W
A
D
I/O Write
RDY
Bus inactive RDY ignored
TMS320C32 Enhanced External Memory Interface
10-51
Bus Timing
Figure 10−42. Inactive Bus States Following STRBx Bus Cycle
H3
H1
STRBx
R/W
A
D
I/O write
RDY
Bus inactive RDY ignored
10-52
Chapter 11
!%&'(&)*+&& !%&'(&'- .
The ’C31/VC33 and ’C32 have on-chip boot loaders that can load and execute
programs received from a host processor, standard memory devices (including EPROM), or via serial port.
Topic
Page
11.1 TMS320C31/VC33 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2 TMS320C32 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11-1
TMS320C31/VC33 Boot Loader
11.1 TMS320C31/VC33 Boot Loader
This section describes how to use the ’C31/VC33 microcomputer/boot loader
(MCBL/MP) function. This feature is unique to the ’C31/VC33 and ’C32, and is
not available on the ’C30 devices.
11.1.1 TMS320C31/VC33 Boot-Loader Description
The boot loader lets you load and execute programs that are received from a
host processor, inexpensive EPROMs, or other standard memory devices. The
programs to be loaded reside in one of three memory-mapped areas identified
as Boot 1, Boot 2, and Boot 3 (see the shaded areas of Figure 4−2 on page 4-6),
or they are received by means of the serial port.
The boot loader supports user-definable byte, half-word, and word-data formats,
as well as 32-bit fixed-burst loads from the ’C31/VC33 serial port. See Section
12.2, Serial Ports, on page 12-15 for a detailed description of the serial-port operation.
The boot-loader code starts at location 0x45 in the on-chip ROM. The source
code is supplied in Appendix B.
11.1.2 TMS320C31/VC33 Boot-Loader Mode Selection
The ’C31/VC33 boot loader functions as a memory boot loader or a serial-port
boot loader. The boot-loader function is selected by resetting the processor
while driving the MCBL/MP pin high. Use interrupt pins INT3 − INT0 to select
the boot-load operation. Figure 11−1 shows the flow of this operation, which depends on the mode selected (external memory or serial boot).
- The memory boot loader supports user-definable byte, half-word, and full-
word data formats, allowing the flexibility to load a source program from
memories having widths of 8-, 16-, or 32 bits. The source program must
reside in one of three memory locations as listed in Table 11−1.
Figure 11−2 shows the memory boot-loader flow.
- The serial-port boot loader supports 32-bit fixed-burst transfers, with
externally generated serial-port clock and frame-sync signals. The format
of the incoming data stream is similar to that of the memory boot loader,
except the source memory width and memory configuration word are
omitted. Figure 11−3 shows the serial-port boot-loader flow.
11-2
TMS320C31/VC33 Boot Loader
Table 11−1. Boot-Loader Mode Selection
INT0
INT1
INT2
INT3
Loader Mode
Memory Addresses
0
1
1
1
External memory
Boot 1 address 0x001000
1
0
1
1
External memory
Boot 2 address 0x400000
1
1
0
1
External memory
Boot 3 address 0xFFF000
1
1
1
0
32-bit serial
Serial port 0
Figure 11−1.TMS320C31/VC33 Boot-Loader Mode-Selection Flowchart
Begin
Reset
MCBL/MP = 1
Is
register
bit INT3
set?
Yes
Serial-port load
No
Is
register
bit INT0
set?
Yes
Memory load
from 1000h
Yes
Memory load
from 400000h
Yes
Memory load
from FFF000h
No
Is
register
bit INT1
set?
No
Is
register
bit INT2
set?
No
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-3
TMS320C31/VC33 Boot Loader
11.1.3 TMS320C31/VC33 Boot-Loading Sequence
The following is the sequence of events that occur during the boot load of a
source program. Table 11−2 shows the structure of the source program.
1) Select the boot loader by resetting the ’C31/VC33 while driving the
MCBL/ MP pin high and the corresponding INT3 −INT0 pin low. The
MCBL/ MP must stay high during boot loading, but can be changed anytime after boot loading has terminated. No reset is necessary when changing the INT3 −INT0 pin, as long as the ’C31/VC33 is not accessing the
overlapping memory (0h −FFFh) during this transition (see Section
11.1.6). The INT3 −INT0 pin can be driven low anytime after deasserting
the RESET pin (driven low and then high).
2) The status of the interrupt flag (IF) register’s INT3 −INT0 bit fields dictate
the boot-loading mode. The bits are polled in the order described in the
flow chart in Figure 11−1.
3) If only the IF register’s INT3 bit field is set, the boot loader configures the
serial port for 32-bit fixed-burst mode reads with an externally generated
serial-port clock and FSR. Then, it proceeds to boot load the source program from the serial port. The transferred data-bit order supplied to the
serial port must begin with the most significant bit (MSB) and end with the
least significant bit (LSB). Figure 11−3 depicts the boot-loader serial-port
flow.
4) Otherwise, the boot loader attempts a memory boot load. Figure 11−2 shows
the boot-loader memory flow. If the IF register’s INT0 bit field is set, the
source program is loaded from memory location 1000h. If the IF register’s
INT1 bit field is set, the source program is loaded from memory location
400000h. If the IF register’s INT2 bit field is set, the source program is loaded
from memory location FFF000h.
The memory boot-load source program has a header indicating the boot
memory width and memory configuration control word. This word is copied
into the STRB control register to configure the external primary bus interface.
5) After reading the header, the boot loader copies the source-program blocks.
The source-program blocks have two entries preceding the source-programblock data. The first entry in the source-program block indicates the size of
the block. A block size of zero signals the end of the source program code.
The second entry indicates the address where the block is to be loaded. The
boot loader cannot load the source program to any memory address below
1000h, unless the address decode logic is remapped.
6) The boot loader branches to the destination address of the first source
block loaded and begins program execution.
11-4
TMS320C31/VC33 Boot Loader
Figure 11−2.Boot-Loader Memory-Load Flowchart
Memory load
Branch to address
boot 1,
boot 2, or
boot 3
Determine mode
8, 16, or 32
Set memory
configuration
control word
Load block size
End of source
program code
(block size = 0)?
Yes
No
Load destination
address
Yes
Block size = 0?
No
Transfer data from
source to
destination
Block size −1
Load next block size
Branch to destination
address of first
block loaded
Begin program execution
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-5
TMS320C31/VC33 Boot Loader
Figure 11−3.Boot-Loader Serial-Port Load-Mode Flowchart
Block size = 0?
Yes
No
Wait for serial
port input
Transfer data from
serial port to
destination address
Block size −1
Block size = 0?
Yes
No
Wait for serialport input
Load destination
address
11-6
Branch to destination
address of first
block loaded
Begin program execution
TMS320C31/VC33 Boot Loader
11.1.4 TMS320C31/VC33 Boot Data Stream Structure
Table 11−2 shows the data stream structure. The data stream is composed of
a header of 1 (serial-port load) or 2 (memory load) words and one or more blocks
of source data. The boot loader uses this header to determine the physical
memory width where the source program resides (memory load) and to configure
the primary bus interface before source program boot load. The blocks of
source data have two entries in addition to the raw data. The first entry in this
block indicates the size of the block. The second entry in this block indicates the
memory address where the boot loader copies this source block. Words 5
through n of the shaded entries in Table 11−2 contain the source data for the first
block.
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-7
TMS320C31/VC33 Boot Loader
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 11−2. Source Data Stream Structure
Word†
Content
Valid Data Entries
1
Memory width (8, 16, or 32 bits) where source program resides 8h, 10h, or 20h, respectively
2
Value to set the STRB control register
3
Size of first data block. The block size is the number of 32-bit 0 ≤ size ≤ 224
words in the data block. A 0 in this entry signifies the end of the
source data stream
4
Destination address to load the first block
A valid ’C31/VC33 24-bit address
5
First word of first block
.
.
.
.
.
.
A ’C31/VC33 valid instruction or any
32-bit wide data value (LSB first)
.
.
.
n
Last word of first block
.
.
.
.
.
.
m
Size of last data block. The block size is the number of 32-bit 0 ≤ size ≤ 224
words in the data block. If the next word following this block is
not 0, another block is loaded.
See subsection 10.7
A ’C31/VC33 valid instruction or any
32-bit wide data value
.
.
.
m+1
Destination address to load the last block
A valid ’C31/VC33 24-bit address
m+2
First word of last block
A ’C31/VC33 valid instruction or any
32-bit wide data value (LSB first)
.
.
.
.
.
.
.
.
.
j
Last word of last source block
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
j+1
Zero word. If more than one source block was read, word j 0h
would be the last word of the last block. Each block consists
of header and data portions. The block’s header is shaded
darker than the block’s data section.
† Words 1 and 2 do not exist in serial-port boot load since the source program does not reside in memory.
Each source block of data can be loaded to different memory locations. Each
block specifies its own size and destination address. The last source block of
the data stream is appended with a zero word.
11-8
TMS320C31/VC33 Boot Loader
11.1.4.1 Examples of External TMS320C31/VC33 Memory Loads
Table 11−3, Table 11−4, and Table 11−5 show memory images for byte-wide,
16-bit-wide, and 32-bit-wide configured memory (see Figure 4−2 on page 4-6).
These examples assume the following:
- An INT0 signal was detected after reset was deasserted (signifying an
external memory load from boot 1).
- The source program header resides at memory location 0x1000 and
defines the following:
J
Boot memory-type EPROMs that require two wait states and SWW = 11
J
A loader destination address at the beginning of the ’C31/VC33 internal RAM block 1
J
A single block of memory that is 0x1FF in length
Table 11−3. Byte-Wide Configured Memory
Address
Value
Comments
0x1000
0x08
Memory width = 8 bits
0x1001
0x00
0x1002
0x00
0x1003
0x00
0x1004
0x58
0x1005
0x10
0x1006
0x00
0x1007
0x00
0x1008
0xFF
0x1009
0x01
0x100A
0x00
0x100B
0x00
0x100C
0x00
0x100D
0x9C
0x100E
0x80
0x100F
0x00
Memory type = SWW = 11, WCNT = 2
Program block size in words = 0x1FF
Program load starting address = 0x809C00
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-9
TMS320C31/VC33 Boot Loader
Table 11−4. 16-Bit-Wide Configured Memory
Address
Value
Comments
0x1000
0x10
Memory width = 16
0x1001
0x0000
0x1002
0x1058
0x1003
0x0000
0x1004
0x1FF
0x1005
0x0000
0x1006
0x9C00
0x1007
0x0080
Memory type = SWW = 11, WCNT = 2
Program block size in words = 0x1FF
Program load starting address = 0x809C00
Table 11−5. 32-Bit-Wide Configured Memory
Address
Value
Comments
0x1000
0x00000020
Memory width = 32
0x1001
0x00001058
Memory type = SWW = 11, WCNT = 2
0x1002
0x000001FF
Program block size in words = 0x1FF
0x1003
0x00809C00
Program load starting address = 0x809C00
After reading the header, the loader transfers 0x IFF 32-bit words, beginning at
a specified destination address 0x 809C00. Code blocks require the same
byte and half-word ordering conventions. The loader can also load multiple
code blocks at different address destinations.
After loading all code blocks, the boot loader branches to the destination address
of the first block loaded and begins program execution. Consequently, the first
code lock loaded is a start-up routine to access the other loaded programs.
It is assumed that at least one block of code is loaded when the
loader is invoked. Initial loader invocation with a block size of
0x00000000 produces unpredictable results.
11-10
TMS320C31/VC33 Boot Loader
11.1.4.2 Serial-Port Loading
Boot loads, by way of the ’C31/VC33 serial port, are selected by driving the
INT3 pin active (low) following reset. The loader automatically configures the
serial port for 32-bit fixed-burst-mode reads. It is interrupt-driven by the frame
synchronization receive (FSR) signal. You cannot change this mode for boot
loads. Your hardware must generate the serial-port clock and FSR externally.
As with memory loads, a header must precede the actual program to be loaded.
However, you need only supply the block size and destination address because
the loader and your hardware have predefined serial-port speed and data format
(that is, skip data words 0 and 1).
The transferred data-bit order must begin with the MSB and end with the LSB.
11.1.5 Interrupt and Trap-Vector Mapping
Unlike the microprocessor mode, the microcomputer/boot-loader (MCBL)
mode uses a dual-vectoring scheme to service interrupt and trap requests. Dual
vectoring was implemented to ensure code compatibility with future versions of
’C3x devices.
In a dual-vectoring scheme, branch instructions to an address, rather than
direct-interrupt vectoring, are used. The normal interrupt and trap vectors are
defined to vector to the last 63 locations in the on-chip RAM, starting at address
809FC1h. When the loader is invoked, the interrupt vector table is remapped
by the processor to the last 63 locations in RAM block 1 of the ’C31/VC33.
These locations are assumed to contain branch instructions to the interrupt
source routines.
Make sure that these locations are not inadvertently overwritten by
loaded program or data values.
Table 11−6 shows the MCBL/MP mode interrupt and trap instruction memory
maps.
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-11
TMS320C31/VC33 Boot Loader
Table 11−6. TMS320C31/VC33 Interrupt and Trap Memory Maps
11-12
Address
Description
809FC1
INT0
809FC2
INT1
809FC3
INT2
809FC4
INT3
809FC5
XINT0
809FC6
RINT0
809FC7
XINT1 (Reserved)
809FC8
RINT1 (Reserved)
809FC9
TINT0
809FCA
TINT1
809FCB
DINT0
809FCC−809FDF
Reserved
809FE0
TRAP0
809FE1
TRAP1
•
•
•
•
•
•
809FFB
TRAP27
809FFC−809FFF
Reserved
TMS320C31/VC33 Boot Loader
11.1.6 TMS320C31/VC33 Boot-Loader Precautions
The boot loader builds a one-word-deep stack, starting at location 809801h.
Avoid loading code at location 809801h.
The interrupt flags are not reset by the boot-loader function. If pending interrupts
are to be avoided when interrupts are enabled, clear the IF register before
enabling interrupts.
The MCBL/MP pin must remain high during the entire boot-loader execution,
but it can be changed subsequently at any time. The ’C31/VC33 does not need
to be reset after the MCBL/MP pin is changed. During the change, the
’C31/VC33 must not access addresses 0h−FFFh. The memory space
0h−FFFh will be mapped to external memory three clock cycles after changing
the MCBL/MP pin.
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-13
TMS320C32 Boot Loader
11.2 TMS320C32 Boot Loader
This section describes how to use the ’C32 microcomputer/boot loader
(MCBL/MP) functions.
11.2.1 TMS320C32 Boot-Loader Description
The ’C32 boot loader is an enhanced version of that found in the ’C31/VC33.
The boot loader can load and execute programs received from a host processor through standard memory devices (including EPROM), with and without
handshake, or through the serial port. The ’C32 boot loader supports 16- and
32-bit program external memory widths, as well as 8-, 16-, and 32-bit datatype sizes and external memory widths.
The programs to be loaded reside in one of three memory-mapped areas identified as Boot 1, Boot 2, and Boot 3 (see shaded areas of Figure 4−3 on page 4-6)
or they are received by means of the serial port.
The boot-loader code starts at location 0x45 in the on-chip ROM. The source
code is supplied in Appendix C.
11.2.2 TMS320C32 Boot-Loader Mode Selection
The ’C32 boot loader functions as a memory boot loader, memory boot loader
with handshake, or a serial-port boot loader. The boot-loader mode selection
is determined by the status of the INT3−INT0 pins immediately following reset.
Table 11−7 lists the boot-loader modes.
- The memory boot loader supports user-definable byte, half-word, and full-
word data formats, allowing the flexibility to load a source program from
memories having widths of 8, 16, and 32 bits with or without handshaking.
The source programs to be loaded reside in one of the three memory locations: 1000h, 810000h, and 900000h (see Table 11−7).
- The memory boot-load handshaking mode uses XF0 as a data-acknowledge
signal and XF1 as a data-ready signal.
- The serial-port boot loader supports 32-bit fixed-burst loads from the ’C32
serial port with an externally generated serial-port clock and frame sync
signals. The format is similar to that of the memory boot loader, except that
the source memory width is omitted.
11-14
TMS320C32 Boot Loader
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
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ÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
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ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 11−7. Boot-Loader Mode Selection
INT0
INT1
INT2
INT3
Boot Loader Mode
Source Program Location
0
1
1
1
External memory
Boot 1 address 1000h
1
0
1
1
External memory
Boot 2 address 81 0000h
1
1
0
1
External memory
Boot 3 address 90 0000h
1
1
1
0
32-bit fixed-burst serial
Serial Port
0
1
1
0
External memory with handshake
Boot 1 address 1000h,
XF0 and XF1 used in handshaking
1
0
1
0
External memory with handshake
Boot 2 address 81 0000h,
XF0 and XF1 used in handshaking
1
1
0
0
External memory with handshake
Boot 3 address 90 0000h,
XF0 and XF1 used in handshaking
11.2.3 TMS320C32 Boot-Loading Sequence
The following is the sequence of events that occur during the boot load of a
source program. Table 11−2 shows the structure of the source program.
1) Select the boot loader by resetting the ’C32 while driving the MCBL/MP pin
high and the corresponding INT3−INT0 pins low. The MCBL/MP must stay
high during boot loading, but can be changed anytime after boot loading has
terminated. No reset is necessary when changing the INT3−INT0 pin, as
long as the ’C32 is not accessing the overlapping memory (0h−FFFh) during
this transition. In nonhandshake mode, one of the INT3−INT0 pins can be
driven low any time after deasserting the RESET pin (driven low and then
high). While in handshake mode, two interrupt pins must be asserted before
deasserting the RESET pin.
2) The status of the IF register’s INT3−INT0 bit fields dictates the boot-loading
mode. The bits are polled in the order described in the flowchart in
Figure 11−4.
3) If only the IF register’s INT3 bit field is set, the boot loader configures the
serial port for 32-bit fixed burst mode reads with an externally generated
serial-port clock and FSR. Then, it proceeds to boot load the source program from the serial port. A header indicating the STRB0, STRB1, and
IOSTRB control registers precedes the actual program (see Table 11−2).
These header values are loaded into the corresponding locations at the
completion of the boot-load operation. The transferred data-bit order supplied to the serial port must begin with the most significant bit (MSB) and
end with the least significant bit (LSB). Figure 11−5 depicts the boot-loader
serial-port flow.
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-15
TMS320C32 Boot Loader
4) Otherwise, the boot loader attempts a memory boot load. Figure 11−6
shows the boot-loader memory flow. If the IF register’s INT0 bit field is set,
the source program is loaded from memory location 1000h. If the IF register’s INT1 bit field is set, the source program is loaded from memory location
810000h. If the IF register’s INT2 bit field is set, the source program is
loaded from memory location 900000h. After determining the memory location of the source program, the boot loader checks INT3 bit field in the IF
register. If this bit is set, all data transfers are performed with synchronous
handshake. The handshake protocol uses XF0 as a data-acknowledge and
XF1 as a data-ready signals. ’C32’s XF0 is an output pin while the XF1 is
an input pin. Figure 11−7 shows the handshake data-transfer operation.
The data-transfer operation occurs as follows:
a) The ’C32 boot loader waits until the host sets XF1 low to read in the
data. While the ’C32 waits for XF1 to drop low, the IACK pin pulses
until XF1 is low. Setting XF1 low communicates to the ’C32 that the
data is valid. The IACK pulse indicates that the ’C32 is waiting for data.
b) The boot loader sets XF0 low after reading the data value. Dropping
XF0 acknowledges to the host that the data was read.
c) The host sets XF1 high to inform the ’C32 that the data is no longer valid.
d) The ’C32 terminates the transfer by setting XF0 high.
The memory boot-load source program has a header indicating the boot
memory width and the contents of the STRB0, STRB1, and IOSTRB control
registers (see Table 11−2).
5) After reading the header, the boot loader copies the source-program
blocks. The source-program blocks have three entries preceding the
source-program-block data. The first entry in the source-program block
indicates the size of the block, the second entry indicates the address where
the block is to be loaded, while the third entry contains the destinationmemory strobe including a pointer that identifies the destination-memory
strobe (STRB0, STRB1, or IOSTRB) and a value that describes the strobe
configuration for the memory width and data-type size. If the destination
memory is internal, the third entry should contain a zero. The boot loader
cannot load the source program to any memory address below 1000h,
unless the address decode logic is remapped.
6) Once all the program blocks are loaded into their respective address locations with the given data-type sizes, the boot loader sets the IOSTRB,
STRB0, and STRB1 control registers to the values read at the beginning
of the boot-load process.
7) The boot loader branches to the destination address of the first source
block loaded and begins program execution.
11-16
TMS320C32 Boot Loader
Figure 11−4.TMS320C32 Boot-Loader Mode-Selection Flowchart
Begin
Reset
MCBL/MP = 1
Is
register bit
INT3 set?
Yes
Serial-port load
No
Is
register bit
INT1 set?
Yes
Memory load
from 81000h
Yes
Memory load
from 1000h
Yes
Memory load
from 900000h
No
Is
register bit
INT0 set?
No
Is
register bit
INT2 set?
No
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-17
TMS320C32 Boot Loader
Figure 11−5.Boot-Loader Serial-Port Load Flowchart
Serial-port load
Set up serial port for
32-bit fixed-burst mode
Wait for serial-port Input
Load block size
Wait for serial-port Input
Read IOSTRB control word
Yes
End of source
program code
(block size = 0)?
Set STRB0, STRB1, and
IOSTRB control registers
Wait for serial-port Input
No
Read STRB0 control word
Branch to destination
address of first block
loaded
Wait for serial-port input
Load destination address
Wait for serial-port Input
Begin program execution
Wait for serial-port input
Read STRB1 control word
Read destination strobe
control word
According to the destination
address, set corresponding
STRB control register datatype size field
Wait for serial-port input
Transfer one word from
serial port to destination
address
End of source
program code
(block size = 0)?
Yes
11-18
No
TMS320C32 Boot Loader
Figure 11−6.Boot-Loader Memory-Load Flowchart
Memory load
Read block size
Is
IF register
bit field INT3
set
?
No
Yes
End of source
program code
(block size = 0)?
Yes
Enable
handshake mode
No
Determine boot address:
Boot 1, Boot 2, or Boot 3
Read destination address
Read memory width:
8, 16, or 32 bits
Read destination strobe
control word
Read IOSTRB control
register
According to the destination
address, set corresponding
STRB control register to the
previously read value
Set STRB0, STRB1, and
IOSTRB control registers
to the values read at the
beginning of the load
Branch to destination
address of first block
loaded
Begin program execution
Read STRB0 control
register
Transfer data source to
destination address
Read STRB1 control
register
End of source
program code
(block size = 0)?
No
Yes
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-19
TMS320C32 Boot Loader
Figure 11−7.Handshake Data-Transfer Operation
i
ii
iii
iv
XF1
XF0
D31-0
Valid data
Valid data
IACK
11.2.4 TMS320C32 Boot Data Stream Structure
Table 11−8 shows the data stream structure. The data stream is composed of
a header of three (serial-port load) or four (memory load) words and one or
more blocks of source data. The boot loader uses this header to determine the
physical memory width where the source program resides (memory load) and
to configure the STRBs after completion of source program boot load. The
blocks of source data have three entries in addition to the raw data. The first
entry in this block indicates the size of the block. The second entry in this block
indicates the memory address where the boot loader copies this source block.
The third entry contains the destination memory strobe configuration including
memory width and data-type size. This allows the boot loader to copy and store
8-, 16-, or 32-bit data values into 8-, 16-, or 32-bit wide memory. Words 8
through n of the shaded entries in Table 11−8 contain the source data for the
first block.
11-20
TMS320C32 Boot Loader
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁ
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ÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
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ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁ
Table 11−8. Source Data Stream Structure
Word†
Content
Valid Data Entries
1
Memory width (8, 16, or 32 bits) where source program
resides
8h, 10h, or 20h, respectively
2
Value to set the IOSTRB control register at end of boot loader
process
See Section 10.7 on page 10-26
3
Value to set the STRB0 control register at end of boot loader
process
See Section 10.3.1 on page 10-7
4
Value to set the STRB1 control register at end of boot loader
process
See Section 10.6 on page 10-20
5
Size of the first data block. The block size is the number of
words in the data block (word length is specified by the datatype size). A 0 in this entry signifies the end of the source
data stream.
0 ≤ size ≤ 224
6
Destination address to load the first block
A valid ’C32 24-bit address
7
First block destination memory width and data-type size in
the format given in the Valid Data Entries column.
SSSSSS6x h‡
8
First word of first block
A ’C32 valid instruction or any 8-,
16-, or 32-bit wide data value
.
.
.
.
.
.
.
.
.
n
Last word of first block
A ’C32 valid instruction or any 8-,
16-, or 32-bit wide data value
.
.
.
.
.
.
.
.
.
m
Size of the last data block. The block size is the number of
words in the data block (word length is specified by the
data-type size). If the next word following this block is not 0,
another block is loaded.
0 ≤ size ≤ 224
Destination address to load the last block
A valid ’C32
24-bit address
m+1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
† Word 1 does not exist in serial-port boot load since the source program does not reside in memory.
‡ The SSSSSS hexadecimal digits refer to the lower 24 bits of the strobe control register. The x hexadecimal digit identifies
the strobe as follows: 0 for IOSTRB, 4 for STRB0, and 8 for STRB1. SSSSSS6xh is cleared to 0 when loading the entire field
into internal memory.
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-21
TMS320C32 Boot Loader
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 11−8. Source Data Stream Structure (Continued)
Word†
Content
Valid Data Entries
m+2
Last block destination memory width and data-type size in
the format given in the Valid Data Entries column.
SSSSSS6xh‡
m+3
First word of last block.
A ’C32 valid instruction or any 8-,
16-, or 32-bit wide data value
.
.
.
.
.
.
j
.
.
.
Last word of last source block
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
j+1
Zero word. Note that if more than one source block was read,
word j shown above would be the last word of the last block.
Each block consists of header and data portions. The block’s
header is shaded darker than the block’s data section.
0h
† Word 1 does not exist in serial-port boot load since the source program does not reside in memory.
‡ The SSSSSS hexadecimal digits refer to the lower 24 bits of the strobe control register. The x hexadecimal digit identifies
the strobe as follows: 0 for IOSTRB, 4 for STRB0, and 8 for STRB1. SSSSSS6xh is cleared to 0 when loading the entire field
into internal memory.
Each source block can be loaded into a different memory location. Each block
specifies its own size and destination address. The last source block of the
data stream is appended with a zero word. Because the ’C32’s STRBs can be
configured to support different external memory widths and data-type sizes,
each source block specifies its data-type size. The external memory width is
set when the boot loader reads the STRBx control register values in the source
data stream header.
To build a ’C32 boot data stream with the HEX30 utility provided with the
TMS320 floating-point code-generation tools, use the following steps:
- Compile/assemble code with −v32 switch using v4.7 or later of the
TMS320 floating-point C compiler/assembler. If the code-generation tools
are invoked with CL30 and −z switch, include −v32 switch in the linker
command file.
- Link as usual.
- Run Hex30 utility version 4.7 or later. The −v32 switch used in the compiler/
assembler will create a header in the COFF file, identifying it as a ’C32 for
the Hex30.
11-22
TMS320C32 Boot Loader
11.2.5 Boot-Loader Hardware Interface
The hardware interface for the memory boot load uses the STRBX_B3 through
STRBX_B0 pins as strobe byte-enable pins (see Figure 11−8). The hardware
interface is independent of the boot source memory width. This interface
is identical to the 32-bit-wide memory interface described in Case 2, in Section
10.6 on page 10-20. For 16-bit memory widths, remove the two left-most
memory devices of Figure 11−8. For 8-bit memory widths, remove all but the
right-most of the memory devices of Figure 11−8.
A2
A1
A0
CS
I/O(7-0)
A2
A1
A0
CS
I/O(7-0)
A2
A1
A0
CS
I/O(7-0)
32−bit wide EPROM
A2
A1
A0
CS
I/O(7-0)
16−bit wide EPROM
A23
A22
A21
A20
...
A23
A22
A21
A20
...
STRBX_B3
STRBX_B2
STRBX_B1
STRBX_B0
A23
A22
A21
A20
...
A2
A1
A0
A23
A22
A21
A20
...
A23
A22
A21
A20
...
’C32
8−bit wide EPROM
Figure 11−8. External Memory Interface for Source Data Stream Memory Boot Load
D(31−24)
D(23−16)
D(15−8)
D(7−0)
11.2.6 TMS320C32 Boot-Loader Precautions
The interrupt flags are not reset by the boot-loader function. If pending interrupts
are to be avoided when interrupts are enabled, clear the IF register before enabling
interrupts.
The MCBL/MP pin should remain high during the entire boot-loading execution,
but it can be changed subsequently at any time. The ’C32 does not need to be
reset after the MCBL/MP pin is changed. During the change, the ’C32 should
not access addresses Oh−FFh. The memory space Oh−FFFh is mapped to
external memory three clock cycles after changing the MCBL/MP pin.
Using the TMS320C31/VC33 and TMS320C32 Boot Loaders
11-23
TMS320C32 Boot Loader
The ’C32 boot loader uses the following peripheral memory-mapped registers
as a temporary stack:
-
Timer0 counter register (808024h)
Timer0 period register (808028h)
DMA0 source address register (808004h)
DMA0 destination address register (808006h)
DMA0 transfer counter register (808008h)
These memory-mapped registers are not reset by the boot-loading process.
Before using these peripherals, reprogram these registers with the appropriate
values.
11-24
Chapter 12
The ’C3x features two timers, a serial port (two serial ports for the ’C30), and
an on-chip direct memory access (DMA) controller (2-channel DMA controller
on the ’C32). These peripheral modules are controlled through memorymapped registers located on the dedicated peripheral bus.
The DMA controller performs input/output operations without interfering with
the operation of the CPU, making it possible to interface the ’C3x to slow, external memories and peripherals, analog-to-digital converters (A/Ds), serial
ports, and so forth, without reducing the computational throughput of the CPU.
The result is improved system performance and decreased system cost.
Topic
Page
12.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.3 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48
12-1
Timers
12.1 Timers
The ’C3x has two 32-bit general-purpose timer modules. Each timer has two
signaling modes and internal or external clocking. You can use the timer
modules to signal to the ’C3x or the external world at specified intervals or to
count external events. With an internal clock, the timer can signal an external
A/D converter to start a conversion, or it can interrupt the ’C3x DMA controller
to begin a data transfer. The timer interrupt is one of the internal interrupts.
With an external clock, the timer can count external events and interrupt the
CPU after a specified number of events. Each timer has an I/O pin that you can
use as an input clock to the timer, as an output clock signal, or as a generalpurpose I/O pin.
Each timer consists of a 32-bit counter, a comparator, an input clock selector,
a pulse generator, and supporting hardware (see Figure 12−1). A timer counts
the cycles of a timer input clock with the counter register. When that counter
register equals the value stored in the timer-period register, it resets the
counter to 0 and produces a transition in the timer output signal. The timer input
clock can be driven by either half the internal clock frequency of the ’C3x or
an external clock on TCLKx pin.
Figure 12−1. Timer Block Diagram
H1/2
Counter (32-bit)
External clock
INV
Period register (31 – 0)
32
Counter register
(31 – 0)
32
Comparator
?
Period = counter
Pulse generator
INV
TSTAT
Timer out
12-2
Timers
12.1.1 Timer Pins
Each timer has one pin associated with the timer clock signal (TCLK) pin. This
pin (TCK) is used as a general-purpose I/0 signal, as a timer output, or as an
input for an external clock for a timer. Each timer has a TCLK pin: TCLK0 is
connected to timer0, TCLK1 to timer1.
12.1.2 Timer Control Registers
Three memory-mapped registers are used by each timer:
- Global-control register
The global-control register determines the operating mode of the timer,
monitors the timer status, and controls the function of the I/O pin of the timer.
- Period register
The period register specifies the timer’s signaling frequency.
- Counter register
The counter register contains the current value of the incrementing counter.
You can increment the timer on the rising edge or the falling edge of the
input clock. The counter is zeroed and can cause an internal interrupt
whenever its value equals that in the period register. The pulse generator
generates either of two types of external clock signals: pulse or clock. The
memory map for the timer modules is shown in Figure 12−2.
Peripherals
12-3
Timers
Figure 12−2. Memory-Mapped Timer Locations
808020h
Timer0 global control†
808024h
Timer0 counter‡
808028h
Timer0 period‡
808030h
Timer1 global control†
808034h
Timer1 counter‡
808038h
Timer1 period‡
†See Section 12.1.3
‡See Section 12.1.4
12.1.3 Timer Global-Control Register
The timer global-control register is a 32-bit register that contains the global and
port control bits for the timer module. Figure 12−3 shows the format of the
timer global-control register. Bits 3 −0 are the port control bits; bits
11 −6 are the timer global-control bits. At reset, all bits are set to 0 except for
DATIN (which is set to the value read on TCLK). Table 12−1 describes the
timer global-control register bits, their names, and functions.
Figure 12−3. Timer Global-Control Register
31
16
xx
Notes:
15
12
xx
11
10
9
8
7
TSTAT
INV
R
R/W
CLKSRC
C/P
R/W
R/W
1) R = read, W = write
2) xx = reserved bit, read as 0
12-4
6
5
4
3
2
1
0
HLD
GO
xx
xx
DATIN
R/W
R/W
R
DATOUT
I/O
FUNC
R/W
R/W
R/W
Timers
Table 12−1. Timer Global-Control Register Bits Summary
Abbreviation
FUNC
Reset
Value
0
Name
Description
Function
Controls the function of TCLK.
If FUNC = 0, TCLK is configured as a general-purpose digital I/O
port.
If FUNC = 1, TCLK is configured as a timer pin.
See section 12.1.6 Timer Operation Modes on page 12-10 for a
description of the relationship between FUNC and CLKSRC.
I/O
0
Input/output
If FUNC = 0 and CLKSRC = 0, TCLK is configured as a generalpurpose I/O pin.
If I/O = 0, TCLK is configured as a general-purpose input pin.
If I/O = 1, TCLK is configured as a general-purpose output pin.
DATOUT
0
Data output
Drives TCLK when the ’C3x is in I/O port mode. You can use DATOUT as an input to the timer.
DATIN
x†
Data input
Data input on TCLK or DATOUT. A write has no effect.
GO
0
Go
Resets and starts the timer counter.
When GO = 1 and the timer is not held, the counter is zeroed and
begins incrementing on the next rising edge of the timer input clock.
The GO bit is cleared on the same rising edge.
GO = 0 has no effect on the timer.
HLD
0
Counter hold
signal
When this bit is 0, the counter is disabled and held in its current
state. If the timer is driving TCLK, the state of TCLK is also held.
The internal divide-by-2 counter is also held so that the counter can
continue where it left off when HLD is set to 1.
You can read and modify the timer registers while the timer is being
held. RESET has priority over HLD. The effect of writing to GO and
HOLD is shown below.
GO
HLD Result
0
0
All timer operations are held. No reset is performed
(reset value).
0
1
Timer proceeds from state before write.
1
0
All timer operations are held, including zeroing of the
counter. The GO bit is not cleared until the timer is
taken out of hold.
1
1
Timer resets and starts.
† x = 0 or 1 (set to value read on TCLK)
Peripherals
12-5
Timers
Table 12−1. Timer Global-Control Register Bits Summary (Continued)
Abbreviation
C/P
Reset
Value
0
Name
Clock/pulse
mode control
Description
When C/P = 1, clock mode is chosen, and the signaling of the TSTAT flag and external output has a 50%
duty cycle.
When C/P = 0, the status flag and external output
will be active for one H1 cycle during each timer
period (see Figure 12−4 on page 12-8).
CLKSRC
0
Clock source
This bit specifies the source of the timer clock.
When CLKSRC = 1, an internal clock with a frequency equal to one-half of the H1 frequency is used to
increment the counter. The INV bit has no effect on
the internal clock source.
When CLKSRC = 0, you can use an external signal
from the TCLK pin to increment the counter. The external clock is synchronized internally, thus allowing
external asynchronous clock sources that do not exceed the specified maximum allowable external
clock frequency. This is less than f(H1)/2.
See section 12.1.6, Timer Operation Modes, on
page 12-10 for a description of the relationship between FUNC and CLKSRC.
INV
0
Inverter control
bit
If an external clock source is used and INV = 1, the
external clock is inverted as it goes into the counter.
If the output of the pulse generator is routed to TCLK
and INV = 1, the output is inverted before it goes to
TCLK (see Figure 12−1 on page 12-2).
If INV = 0, no inversion is performed on the input or
output of the timer. The INV bit has no effect, regardless of its value, when TCLK is used in I/O port
mode.
TSTAT
0
Timer status bit
† x = 0 or 1 (set to value read on TCLK)
12-6
This bit indicates the status of the timer. It tracks the
output of the uninverted TCLK pin. This flag sets a
CPU interrupt on a transition from 0 to 1. A write has
no effect.
Timers
12.1.4 Timer-Period and Counter Registers
The 32-bit timer-period register is used to specify the frequency of the timer
signaling. The timer-counter register is a 32-bit register, which is reset to 0
whenever it increments to the value of the period register. Both registers are
set to 0 at reset.
Certain boundary conditions affect timer operation. These conditions are listed
below:
- When the period and counter registers are 0, the operation of the timer is
dependent upon the C/P mode selected. In pulse mode (C/P = 0), TSTAT
is set and remains set. In clock mode (C/P = 1), the width of the cycle is
2/f(H1), and the external clocks are ignored.
- When the counter register is not 0 and the period register = 0, the counter
counts, rolls over to 0, and behaves as described above.
- When the counter register is set to a value greater than the period register,
the counter may overflow when incremented. Once the counter reaches its
maximum 32-bit value (0FFFFFFFFh), it rolls over to 0 and continues.
Writes from the peripheral bus override register updates from the counter and
new status updates to the control register.
12.1.5 Timer Pulse Generation
The timer pulse generator (see Figure 12−1 on page 12-2) can generate several
external signals. You can invert these signals with the INV bit. The two basic
modes are pulse mode and clock mode, as shown in Figure 12−4. In both modes,
an internal clock source f (timer clock) has a frequency of f(H1)/2, and an externally generated clock source f (timer clock) can have a maximum frequency of
f(H1)/2.6. In pulse mode (C/P = 0), the width of the pulse is 1/f(H1).
Peripherals
12-7
Timers
Figure 12−4. Timer Timing
(a) TSTAT and timer output (INV = 0) when C/P = 0 (pulse mode)
2/f(H1)
1/f(H1)
1/f(CLKSRC)
period register/f(CLKSRC)
TINT
TINT
TINT
(b) TSTAT and timer output (INV = 0) when C/P = 1 (clock mode)
1/f(CLKSRC)
2/f(H1)
period register/f(CLKSRC)
2 x period register/f(CLKSRC)
TINT
TINT
The timer signaling is determined by the frequency of the timer input clock and
the period register. The following equations are valid with either an internal or
an external timer clock:
f(pulse mode) = f(timer clock) / period register
f(clock mode) = f(timer clock) / (2 x period register)
Note: Period register
If the period register equals 0, see Section 12.1.4.
Example 12−1 provides some examples of the TCLKx output when the period
register is set to various values and clock or pulse mode is selected.
12-8
Timers
Example 12−1. Timer Output Generation Examples
INV = 0, C/P = 0 (pulse mode)
timer period = 1
Also,
INV = 0, C/P = 1 (clock mode)
timer period = 0
(a)
2H1
H1
(b)
INV = 0, C/P = 0 (pulse mode)
timer period = 2
4H1
H1
(c)
INV = 0, C/P = 0 (pulse mode)
timer period = 3
6H1
H1
(d)
INV = 0, C/P = 1 (clock mode)
timer period = 1
4H1
2H1
(e)
INV = 0, C/P = 1 (clock mode)
timer period = 2
8H1
4H1
(f)
12H1
INV = 0, C/P = 1 (clock mode)
timer period = 3
6H1
Peripherals
12-9
Timers
12.1.6 Timer Operation Modes
The timer can receive its input and send its output in several different modes,
depending upon the setting of CLKSRC, FUNC, and I/O. The four timer modes
of operation are defined in the following sections.
12.1.6.1
CLKSRC = 1 and FUNC = 0
If CLKSRC = 1 and FUNC = 0, the timer input comes from the internal clock.
The internal clock is not affected by the INV bit in the global-control register.
In this mode, TCLK is connected to the I/O port control, and you use TCLK as
a general-purpose I/O pin (see Figure 12−5).
- If I/O = 0, TCLK is configured as a general-purpose input pin whose state
you can read in DATIN. DATOUT has no effect on TCLK or DATIN. See
Figure 12−5 (a).
- If I/O = 1, TCLK is configured as a general-purpose output pin. DATOUT
is placed on TCLK and can be read in DATIN. See Figure 12−5 (b).
Figure 12−5. Timer Configuration with CLKSRC = 1 and FUNC = 0
(b)
(a) CLKSRC=1 (internal)
FUNC=0 (I/O pin)
I/O=0 (input)
ÁÁÁÁÁ
ÁÁÁÁÁ
Timer
Input
Output
TSTAT
Internal
External
Internal
clock
ÁÁÁÁ
ÁÁÁÁ
I/O port
control
DATIN
TCLK
CLKSRC = 1 (internal)
FUNC = 0 (I/O pin)
I/O = 1 (output)
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Timer
Input
Output
Internal
Internal
clock
DATOUT
TSTAT
I/O port
control
DATIN
12-10
External
TCLK
Timers
12.1.6.2
CLKSRC = 1 and FUNC = 1
If CLKSRC = 1 and FUNC = 1 (see Figure 12−6), the timer input comes from
the internal clock, and the timer output goes to TCLK. This value can be inverted
using INV, and you can read in DATIN the value output on TCLK.
Figure 12−6. Timer Configuration with CLKSRC = 1 and FUNC = 1
Timer
In
Out
TSTAT
Internal
External
Internal
clock
TCLK
DATIN
CLKSRC = 1 (internal)
FUNC = 1 (timer pin)
12.1.6.3
CLKSRC = 0 and FUNC = 0
If CLKSRC = 0 and FUNC = 0 (see Figure 12−7), the timer is driven according
to the status of the I/O bit.
- If I/O = 0, the timer input comes from TCLK. This value can be inverted
using INV, and you can read in DATIN the value of TCLK. See
Figure 12−7 (a).
- If I/O = 1, TCLK is an output pin. Then, TCLK and the timer are both driven
by DATOUT. All 0-to-1 transitions of DATOUT increment the counter. INV
has no effect on DATOUT. You can read in DATIN the value of DATOUT.
See Figure 12−7 (b).
Figure 12−7. Timer Configuration with CLKSRC = 0 and FUNC = 0
CLKSRC = 0 (external)
FUNC = 0 (I/O pin)
I/O = 1 (output)
(b)
CLKSRC = 0 (external)
FUNC = 0 (I/O pin)
I/O = 0 (input)
(a)
Timer
Internal
TSTAT
External
TCLK
In
Out
I/O port
control
DATIN
Timer
Internal
TCLK
In
Out
TSTAT
External
I/O port
control
DATOUT
Peripherals
12-11
Timers
12.1.6.4
CLKSRC = 0 and FUNC = 1
If CLKSRC = 0 and FUNC = 1 (see Figure 12−8), TCLK drives the timer.
- If INV = 0, all 0-to-1 transitions of TCLK increment the counter.
- If INV = 1, all 1-to-0 transitions of TCLK increment the counter. You can
read in DATIN the value of TCLK.
Figure 12−8. Timer Configuration with CLKSRC = 0 and FUNC = 1
Timer
Internal
External
TCLK
In
Out
TSTAT
DATIN
CLKSRC = 0 (external)
FUNC = 1 (timer pin)
12.1.7 Using TCLKx as General-Purpose I/O Pins
When FUNC = 0, TCLKx can be used as an I/O pin. Figure 12−9 and
Figure 12−10 show how the TCLKx is connected when it is configured as a
general-purpose I/O pin. In Figure 12−9, the I/O bit equals 0 and TCLK is
configured as an input pin whose value can be read in the DATIN bit. In
Figure 12−10, the I/O bit equals 1 and TCLK is configured as an output pin that
outputs the value you wrote in the DATOUT bit.
Figure 12−9. TCLK as an Input (I/O = 0)
Internal
DATOUT (NC)
External
TCLK
DATIN
I/O = 0
FUNC = 0
Figure 12−10. TCLK as an Output (I/O = 1)
Internal
DATOUT
TCLK
DATIN
I/O = 1
FUNC = 0
12-12
External
Timers
12.1.8 Timer Interrupts
A timer interrupt is generated whenever the TSTAT bit of the timer control register
changes from a 0 to a 1. The frequency of timer interrupts depends on whether
the timer is set up in pulse mode or clock mode.
- In pulse mode, the interrupt frequency is determined by the following
equation:
f(interrupt) =
f(timer clock)
period register
where:
f(interrupt) = interrupt frequency
f(timer clock) = timer frequency
- In clock mode, the interrupt frequency is determined by the following
equation:
f(interrupt) =
f(timer clock)
2 x period register
where:
f(interrupt) = interrupt frequency
f(timer clock) = timer frequency
The timer counter is automatically reset to 0 whenever it is equal to the value
in the timer-period register. You can use the timer interrupt for either the CPU
or the DMA. Interrupt-enable control for each timer, for either the CPU or the
DMA, is found in the CPU/DMA interrupt-enable register. Refer to Section 3.1.8,
CPU/DMA Interrupt-Enable Register (IE), on page 3-9 for more information.
When a timer interrupt occurs, a change in the state of the corresponding
TCLK pin is observed if FUNC = 1 and CLKSRC = 1 in the timer global-control
register. The exact change in the state depends on the state of the C/P bit. In
pulse mode (C/P = 0), the width of the pulse change is 1/f (H1). In clock mode
(C/P = 1), the width of the pulse change is the period register divided by the
frequency of the timer input clock.
12.1.9 Timer Initialization/Reconfiguration
The timers are controlled through memory-mapped registers located on the
dedicated peripheral bus. The general procedure for initializing and/or reconfiguring the timers follows:
1) Halt the timer by clearing the GO/HLD bits of the timer global-control register.
To do this, write a 0 to the timer global-control register. Note that the timers
are halted on RESET.
Peripherals
12-13
Timers
2) Configure the timer through the timer global-control register (with GO =
HLD = 0 ), the timer-counter register, and timer-period register, if necessary.
3) Start the timer by setting the GO/HLD bits of the timer global-control register.
Example 12−2 shows how to set up the ‘C3x timer to generate the maximum
clock frequency through the TCLKx pin.
Example 12−2. Maximum Frequency Timer Clock Setup
*
Maximum Frequency Timer Clock Setup
*
.data
Timer0
TCTRL_RST
TCTRL_GD
TCNT
TPRD
12-14
.word
.word
.word
.word
.word
.text
.
.
.
LDP
LD1
LD1
ST1
LD1
ST1
LD1
ST1
LD1
ST1
LD1
ST1
808020h
301h
3C1h
0
0
Timer0
@Timer0,AR0
0,R0
R0,*AR0
@TCTRL_RST,R0
R0,*AR0
@TCNT,R0
R0,*+AR0(4)
@TPRD,R0
R0,**+AR0(8)
@TCTRL_G0,R0
R0,*AR0
; Timer global control address
; Timer counter value
; Timer-period value
; Load data page pointer
; Halt timer
; Configure timer
; Load timer counter
; Load timer period
; Start timer
Serial Ports
12.2 Serial Ports
The ’C30 has two totally independent bidirectional serial ports. Both serial ports
are identical, and there is a complementary set of control registers in each one.
Only one serial port is available on the ’C31/VC33 and the ’C32. You can configure each serial port to transfer 8, 16, 24, or 32 bits of data per word simultaneously in both directions. The clock for each serial port can originate either internally, through the serial port timer and period registers, or externally, through a
supplied clock. An internally generated clock is a divide down of the clockout frequency, f(H1). A continuous transfer mode is available, which allows the serial
port to transmit and receive any number of words without new synchronization
pulses.
Eight memory-mapped registers are provided for each serial port:
-
Global-control register
Two control registers for the six serial I/O pins
Three receive/transmit timer registers
Data-transmit register
Data-receive register
The global-control register controls the global functions of the serial port and
determines the serial-port operating mode. Two port control registers control
the functions of the six serial port pins. The transmit buffer contains the next
complete word to be transmitted. The receive buffer contains the last complete
word received. Three additional registers are associated with the transmit/
receive sections of the serial-port timer. A serial-port block diagram is shown
in Figure 12−11 on page 12-16, and the memory map of the serial ports is
shown in Figure 12−12 on page 12-17.
Peripherals
12-15
Serial Ports
Figure 12−11. Serial Port Block Diagram
Receive Section
Receive
timer (16)
RINT
Transmit Section
CLKR
TSTAT
CLKR
Receive Clock
CLKX
TSTAT
CLKX
FSR
FSR
Transmit
timer (16)
XINT
FSX
FSX
Bit counter
(8/16/24/32)
Bit counter
(8/16/24/32)
RSR
(32)
XSR
(32)
Load
control
Load
control
Load
DX
DR
DX
DR
DX
DRR
(32)
12-16
Load
DXR
(32)
Serial Ports
Figure 12−12. Memory-Mapped Locations for the Serial Ports
808040h
808042h
Serial-port 0 global control{
Serial port 0 FSX/DX/CLKX control‡
808043h
Serial port 0 FSR/DR/CLKR control§
808044h
Serial port 0 R/X timer control¶
808045h
Serial port 0 R/X timer counter#
808046h
Serial port 0 R/X timer periodk
808048h
Serial port 0 data transmitl
80804Ch
Serial port 0 data receivej
808050h
Serial-port 1 global control{
808052h
Serial port 1 FSX/DX/CLKX control‡
808053h
Serial port 1 FSR/DR/CLKR control§
808054h
Serial port 1 R/X timer control¶
808055h
Serial port 1 R/X timer counter#
808056h
Serial port 1 R/X timer periodk
808058h
Serial port 1 data transmitl
80805Ch
Serial port 1 data receivej
Note: Serial port1 locations are reserved on the ’C31/VC33 and ’C32.
† See Figure 12−13.
‡ See Figure 12−14.
§ See Figure 12−15.
¶ See Figure 12−16.
# See Figure 12−17.
|| See Figure 12−18.
k See Figure 12−19.
h See Figure 12−20.
12.2.1 Serial-Port Global-Control Register
The serial-port global-control register is a 32-bit register that contains the globalcontrol bits for the serial port. The register is shown in Figure 12−13. Table 12−2
shows the register bits, bit names, and bit functions.
Peripherals
12-17
Serial Ports
Figure 12−13. Serial-Port Global-Control Register
31
30
29
28
27
26
xx
xx
xx
xx
RRESET
R/W
15
14
13
25
24
XRESET
RINT
R/W
R/W
12
11
10
23
22
RTINT
XINT
XTINT
R/W
R/W
R/W
9
21
8
7
6
XCLK
SRCE
R/W
DRP
DXP
CLKRP
CLKXP
RFSM
XFSM
RVAREN
XVAREN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
19
R/W
R/W
18
RLEN
R/W
RCLK
SRCE
20
5
HS
R/W
XLEN
R/W
17
16
FSRP
FSXP
R/W
R/W
4
3
2
1
0
RSR
FULL
XSR
EMPTY
FSXOUT
XRDY
RRDY
R
R
R/W
R
R
1) R = read, W = write
2) xx = reserved bit, read as 0
Table 12−2. Serial-Port Global-Control Register Bits Summary
Abbreviation
RRDY
Reset
Value
0
Name
Description
Receive ready flag
If RRDY = 1, the receive buffer has new data and is ready to
be read. A three H1/H3 cycle delay occurs from the loading
of DRR to RRDY = 1. The rising edge of this signal sets RINT.
If RRDY = 0, the receive buffer does not have new data since
the last read. RRDY = 0 at reset and after the receive buffer is
read.
XRDY
1
Transmit ready flag
If XRDY = 1, the transmit buffer has written the last bit of data
to the shifter and is ready for a new word. A three H1/H3 cycle
delay occurs from the loading of the transmit shifter until
XRDY is set to 1. The rising edge of this signal sets XINT.
If XRDY = 0, the transmit buffer has not written the last bit of
data to the transmit shifter and is not ready for a new word.
FSXOUT
XSREMPTY
0
Transmit frame sync
configuration
FSXOUT = 0 configures the FSX pin as an input.
Transmit-shift
register empty flag
If XSREMPTY = 0, the transmit-shift register is empty.
FSXOUT = 1 configures the FSX pin as an output.
If XSREMPTY = 1, the transmit-shift register is not empty.
Reset or XRESET causes this bit to = 0.
RSRFULL
0
Receive-shift register
full flag
If RSRFULL = 1, an overrun of the receiver has occurred. In
continuous mode, RSRFULL is set to 1 when both RSR and
DRR are full. In noncontinuous mode, RSRFULL is set to 1
when RSR and DRR are full and a new FSR is received. A read
causes this bit to be set to 0. This bit can be set to 0 only by a
system reset, a serial-port receive reset (RRESET = 1), or a
read. When the receiver tries to set RSRFULL to 1 at the same
time that the global register is read, the receiver dominates,
and RSRFULL is set to 1.
If RSRFULL = 0, no overrun of the receiver has occurred.
12-18
Serial Ports
Table 12−2. Serial-Port Global-Control Register Bits Summary (Continued)
Abbreviation
HS
Reset
Value
0
Name
Description
Handshake
If HS = 1, the handshake mode is enabled.
If HS = 0, the handshake mode is disabled.
XCLK SRCE
RCLK SRCE
XVAREN
0
0
0
Transmit clock
source
If XCLK SRCE = 1, the internal transmit clock is used.
Receive clock
source
If RCLK SRCE = 1, the internal receive clock is used.
Transmit data rate
mode
Specifies a fixed or variable data rate mode when transmitting.
If XCLK SRCE = 0, the external transmit clock is used.
If RCLK SRCE = 0, the external receive clock is used.
With a fixed data rate, FSX is active for at least one XCLK
cycle and then goes inactive before transmission begins.
With variable data rate, FSX is active while all bits are being
transmitted. When you use an external FSX and variable data
rate signaling, the DX pin is driven by the transmitter when
FSX is held active or when a word is being shifted out.
RVAREN
0
Receive data rate
mode
Specifies a fixed or variable data rate mode when receiving.
If RVAREN = 0 (fixed data rate), FSX is active for at least one
RCLK cycle and then goes inactive before reception begins.
If RVAREN = 1 (controlled data rate), FSX is active while all
bits are being received.
XFSM
0
Transmit frame
sync mode
Configures the port for continuous mode operation or standard
mode operation.
If XFSM = 1 (continuous mode), only the first word of a block
generates a sync pulse, and the rest are transmitted continuously
to the end of the block.
If XFSM = 0 (standard mode), each word has an associated
sync pulse.
RFSM
0
Receive frame
sync mode
Configures the port for continuous mode operation or standard
mode operation.
If RFSM = 1 (continuous mode), only the first word of a block
generates a sync pulse, and the rest are received continuously
to the end of the block.
If RFSM = 0 (standard mode), each word received has an
associated sync pulse.
CLKXP
CLKX polarity
If CLKXP = 0, CLKX is active high.
If CLKXP = 1, CLKX is active low.
Peripherals
12-19
Serial Ports
Table 12−2. Serial-Port Global-Control Register Bits Summary (Continued)
Abbreviation
CLKRP
Reset
Value
0
Name
Description
CLKR polarity
If CLKRP = 0, CLKR is active (high).
If CLKRP = 1, CLKR is active (low).
DXP
0
DX polarity
If DXP = 0, DX is active (high).
If DXP = 1, DX is active (low).
DRP
0
DR polarity
If DRP = 0, DR is active (high).
If DRP = 1, DR is active (low).
FSXP
0
FSX polarity
If FSXP = 0, FSX is active (high).
If FSXP = 1, FSX is active (low).
FSRP
0
FSR polarity
If FSRP = 0, FSR is active (high).
If FSRP = 1, FSR is active (low).
XLEN
RLEN
XTINT
XINT
00
00
0
0
Transmit word length
Receive word length
These two bits define the word length of serial data transmitted. All data is assumed to be right justified in the transmit
buffer when fewer than 32 bits are specified.
0 0 — 8 bits
1 0 — 24 bits
0 1 — 16 bits
1 1 — 32 bits
These two bits define the word length of serial data received.
All data is right justified in the receive buffer.
0 0 — 8 bits
1 0 — 24 bits
0 1 — 16 bits
1 1 — 32 bits
Transmit timer
interrupt enable
If XTINT = 0, the transmit timer interrupt is disabled.
Transmit interrupt
enable
If XINT = 0, the transmit interrupt is disabled.
If XTINT = 1, the transmit timer interrupt is enabled.
If XINT = 1, the transmit interrupt is enabled.
Note: The CPU receive flag XINT and the serial-port-to-DMA
interrupt (EXINT0 in the IE register) is the OR of the enabled
transmit timer interrupt and the enabled transmit interrupt.
RTINT
12-20
0
Receive timer
interrupt enable
If RTINT = 0, the receive timer interrupt is disabled.
If RTINT = 1, the receive timer interrupt is enabled.
Serial Ports
Table 12−2. Serial-Port Global-Control Register Bits Summary (Continued)
Abbreviation
RINT
Reset
Value
0
Name
Description
Receive interrupt
enable
If RINT = 0, the receive interrupt is disabled.
If RINT = 1, the receive interrupt is enabled.
Note: The CPU receive interrupt flag RINT and the serialport-to-DMA interrupt (ERINT0 in the IE register) are the OR
of the enabled receive timer interrupt and the enabled receive
interrupt.
XRESET
0
Transmit reset
If XRESET = 0, the transmit side of the serial port is reset.
To take the transmit side of the serial port out of reset, set
XRESET to 1.
Do not set XRESET to 1 until at least three cycles after RESET
goes inactive. This applies only to system reset. Setting XRESET
to 0 does not change the contents of any of the serial-port control
registers. It places the transmitter in a state corresponding to the
beginning of a frame of data. Resetting the transmitter generates
a transmit interrupt. Reset this bit during the time the mode of the
transmitter is set. You can toggle XFSM without resetting the
global-control register.
RRESET
0
Receive reset
If RRESET = 0, the receive side of the serial port is reset.
To take the receive side of the serial port out of reset, set RRESET to 1.
Do not set RRESET to 1 until at least three cycles after RESET
goes inactive. This applies only to system reset. Setting RRESET
to 0 does not change the contents of any of the serial-port control
registers. It places the receiver in a state corresponding to the
beginning of a frame of data. Reset this bit at the same time that
the mode of the receiver is set. You can toggle without resetting
the global-control register.
Peripherals
12-21
Serial Ports
12.2.2 FSX/DX/CLKX Port-Control Register
This 32-bit port-control register controls the function of the serial port FSX, DX,
and CLKX pins. The register is shown in Figure 12−14. Table 12−3 shows the
register bits, bit names, and bit functions.
Figure 12−14. FSX/DX/CLKX Port-Control Register
31−16
15−12
11
10
9
8
7
6
5
4
3
2
1
0
xx
xx
FSX
DATIN
FSX
DATOUT
FSX
I/O
FSX
FUNC
DX
DATIN
DX
DATOUT
DX
I/O
DX
FUNC
CLKX
DATIN
CLKX
DATOUT
CLKX
I/O
CLKX
FUNC
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Notes:
1) R = read, W = write.
2) xx = reserved bit, read as 0.
Table 12−3. FSX/DX/CLKX Port-Control Register Bits Summary
Abbreviation
Reset
Value
CLKX FUNC
0
Name
Clock transmit
function
Description
Controls the function of CLKX.
If CLKX FUNC = 0, CLKX is configured as a general-purpose
digital I/O port.
If CLKX FUNC = 1, CLKX is configured as a serial port pin.
CLKX I/O
0
Clock transmit
input/output
mode
If CLKX I/O = 0, CLKX is configured as a general-purpose input
pin.
If CLKX I/O = 1, CLKX is configured as a general-purpose output
pin.
CLKX DATOUT
0
Clock transmit
data ouput
Data output on CLKX when configured as general-purpose
output.
CLKX DATIN
x†
Clock transmit
data input
Data input on CLKX when configured as general-purpose input.
A write has no effect.
DX FUNC
0
DX function
DXFUNC controls the function of DX.
If DXFUNC = 0, DX is configured as a general-purpose digital
I/O port.
If DXFUNC = 1, DX is configured as a serial port pin.
DX I/O
DX DATOUT
† x = 0 or 1
12-22
0
0
DX input/output
mode
DX data output
If DX I/O = 0, DX is configured as a general-purpose input pin.
If DX I/O = 1, DX is configured as a general-purpose output pin.
Data output on DX when configured as general-purpose output.
Serial Ports
Table 12−3. FSX/DX/CLKX Port-Control Register Bits Summary (Continued)
Abbreviation
Reset
Value
Name
Description
DX DATIN
x†
DX data input
Data input on DX when configured as general-purpose input.
A write has no effect.
FSX FUNC
0
FSX function
Controls the function of FSX.
If FSX FUNC = 0, FSX is configured as a general-purpose digital
I/O port.
If FSX FUNC = 1, FSX is configured as a serial port pin.
0
FSX I/O
FSX input/output
mode
If FSX I/O = 0, FSX is configured as a general-purpose input
pin.
If FSX I/O = 1, FSX is configured as a general-purpose output
pin.
FSX DATOUT
0
FSX data output
Data output on FSX when configured as general-purpose output.
FSX DATIN
x†
FSX data input
Data input on FSX when configured as general-purpose input.
A write has no effect.
† x = 0 or 1
12.2.3 FSR/DR/CLKR Port-Control Register
This 32-bit port-control register is controlled by the function of the FSR, DR,
and CLKR pins. At reset, all bits are set to 0. The register is shown in
Figure 12−15. Table 12−4 shows the register bits, bit names, and bit functions.
Figure 12−15. FSR/DR/CLKR Port-Control Register
31
16
xx
15
12
xx
11
FSR
DATIN
R
Notes:
10
9
8
FSR
DATOUT
FSR
I/O
FSR
FUNC
R/W
R/W
R/W
7
DR
DATIN
R
6
5
4
DR
DATOUT
DR
I/O
DR
FUNC
R/W
R/W
R/W
3
2
CLKR
DATIN
CLKR
DATOUT
R
R/W
1
CLKR
I/O
R/W
0
CLKR
FUNC
R/W
1) R = read, W = write
2) xx = reserved bit, read as 0
Peripherals
12-23
Serial Ports
Table 12−4. FSR/DR/CLKR Port-Control Register Bits Summary
Abbreviation
Reset
Value
CLKR FUNC
0
Name
Description
Clock receive
function
Controls the function of CLKR.
If CLKR FUNC = 0, CLKR is configured as a general-purpose
digital I/O port.
If CLKR FUNC = 1, CLKR is configured as a serial port pin.
CLKR I/O
0
Clock receive
input/output
mode
If CLKR I/O = 0, CLKR is configured as a general-purpose input
pin.
If CLKR I/O = 1, CLKR is configured as a general-purpose output
pin.
CLKR DATOUT
0
Clock receive
data output
Data output on CLKR when configured as general-purpose
output.
CLKR DATIN
x†
Clock receive
data input
Data input on CLKR when configured as general-purpose input.
A write has no effect.
DR FUNC
0
DR function
Controls the function of DR.
If DR FUNC = 0, DR is configured as a general-purpose digital
I/O port.
If DR FUNC = 1, DR is configured as a serial port pin.
DR I/O
0
DR input/output
mode
If DR I/O = 0, DR is configured as a general-purpose input pin.
If DR I/O = 1, DR is configured as a general-purpose output pin.
DR DATOUT
0
DR data output
Data output on DR when configured as general-purpose output.
DR DATIN
x†
DR data input
Data input on DR when configured as general-purpose input.
A write has no effect.
FSR FUNC
0
FSR function
FSR FUNC controls the function of FSR.
If FSR FUNC = 0, FSR is configured as a general-purpose digital
I/O port.
If FSR FUNC = 1, FSR is configured as a serial port pin.
FSR I/O
0
FSR input/output
mode
If FSR I/O = 0, FSR is configured as a general-purpose input
pin.
If FSR I/O = 1, FSR is configured as a general-purpose output
pin.
FSR DATOUT
† x = 0 or 1.
12-24
0
FSR data output
Data output on FSR when configured as general-purpose output.
Serial Ports
Table 12−4. FSR/DR/CLKR Port-Control Register Bits Summary (Continued)
Abbreviation
Reset
Value
x†
FSR DATIN
Name
Description
FSR data input
Data input on FSR when configured as general-purpose input.
A write has no effect.
† x = 0 or 1.
12.2.4 Receive/Transmit Timer-Control Register
A 32-bit receive/transmit timer-control register contains the control bits for the
timer module. At reset, all bits are set to 0. Figure 12−16 shows the register.
Bits 5−0 control the transmitter timer. Bits 11 −6 control the receiver timer. The
serial port receive/transmit timer function is similar to timer module operation.
It can be considered a 16-bit-wide timer. Table 12−5 describes the register
bits, bit names, and bit functions.
Figure 12−16. Receive/Transmit Timer-Control Register
31
16
xx
15
12
xx
11
10
9
8
7
6
5
RSTAT
xx
RCLKSRC
RC/P
RHLD
RGO
XSTAT
R/W
R/W
R/W
R/W
R
Notes:
R
4
xx
2
3
XCLKSRC
R/W
XC/P
R/W
1
0
XHLD
XGO
R/W
R/W
1) R = read, W = write
2) xx = reserved bit, read as 0
Table 12−5. Receive/Transmit Timer-Control Register Register Bits Summary
Abbreviation
XGO
Reset
Value
0
Name
Function
Transmit timer counter
restart
Resets and restarts the transmit timer counter.
If XGO = 1 and the timer is not held, the counter is zeroed
and begins incrementing on the next rising edge of the timer
input clock.
The XGO bit is cleared on the same rising edge. Writing 0
to XGO has no effect on the transmit timer.
XHLD
0
Transmit counter hold
signal
If XHLD = 0, the counter is disabled and held in its current
state.
If XHLD = 1, the internal divide-by-two counter is also held so
that the counter continues where it left off.
Peripherals
12-25
Serial Ports
Table 12−5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued)
Abbreviation
XC/P
Reset
Value
0
Name
Function
Transmit clock/pulse
mode control
When XC/P = 1, the clock mode is chosen. The signaling of
the status flag and external output has a 50 percent duty
cycle.
When XC/P = 0, the status flag and external output are active
for one CLKOUT cycle during each timer period.
XCLKSRC
0
Transmit clock source
Specifies the source of the transmit timer clock.
When XCLKSRC = 1, an internal clock with frequency equal
to one-half the CLKOUT frequency is used to increment the
counter.
When XCLKSRC = 0, you can use an external signal from
the CLKX pin to increment the counter.
The external clock source is synchronized internally, thus
allowing for external asynchronous clock sources that do
not exceed the specified maximum allowable external clock
frequency, that is, less than f(H1)/2.6.
XTSTAT
0
Transmit timer status
Indicates the status of the transmit timer. It tracks what
would be the output of the uninverted CLKX pin.
This flag sets a CPU interrupt on a transition from 0 to 1. A
write has no effect.
RGO
0
Receive timer counter
restart
Resets and starts the receive timer counter.
When RGO is set to 1 and the timer is not held, the counter
is zeroed and begins incrementing on the next rising edge
of the timer input clock.
The RGO bit is cleared on the same rising edge. Writing 0
to RGO has no effect on the receive timer.
RHLD
0
Receive counter hold
signal
If RHLD = 0, the counter is disabled and held in its current
state.
If RHLD = 1, the internal divide-by-2 counter is also held so
that the counter will continue where it left off.
You can read and modify the timer registers while the timer
is being held. RESET has priority over RHLD.
RC/P
0
Rclock/pulse mode
control
When RC/P = 1, the clock mode is chosen. The signaling of
the status flag and external output has a 50% duty cycle.
When RC/P = 0, the status flag and external output are active
for one CLKOUT cycle during each timer period.
12-26
Serial Ports
Table 12−5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued)
Abbreviation
RCLKSRC
Reset
Value
0
Name
Function
Receive timer clock
source
Specifies the source of the receive timer clock.
When RCLKSRC = 1, an internal clock with frequency equal
to one-half the CLKOUT frequency is used to increment the
counter.
When RCLKSRC = 0, you can use an external signal from
the CLKR pin to increment the counter. The external clock
source is synchronized internally, allowing for external
asynchronous clock sources that do not exceed the specified maximum allowable external clock frequency (that is,
less than f(H1)/2.6).
RTSTAT
0
Receive timer status
Indicates the status of the receive timer. It tracks what would
be the output of the uninverted CLKR pin.
This flag sets a CPU interrupt on a transition from 0 to 1. A
write has no effect.
12.2.5 Receive/Transmit Timer-Counter Register
The receive/transmit timer-counter register is a 32-bit register (see
Figure 12−17). Bits 15−0 are the transmit timer-counter, and bits 31 −16 are
the receive timer-counter. Each counter is cleared to 0 whenever it increments
to the value of the period register (see Section 12.2.6). It is also set to 0 at reset.
Figure 12−17. Receive/Transmit Timer-Counter Register
31
16
Receive counter
0
15
Transmit counter
Note:
All bits are read/write.
Peripherals
12-27
Serial Ports
12.2.6 Receive/Transmit Timer-Period Register
The receive/transmit timer-period register is a 32-bit register (see Figure 12−18).
Bits 15−0 are the timer transmit period, and bits 31−16 are the receive period.
Each register specifies the period of the timer and is cleared to 0 at reset.
Figure 12−18. Receive/Transmit Timer-Period Register
31
16
Receive period
0
15
Transmit period
Note:
All bits are read/write.
12.2.7 Data-Transmit Register
When the data-transmit register (DXR) is loaded, the transmitter loads the word
into the transmit-shift register (XSR), and the bits are shifted out. The delay from
a write to DXR until an FSX occurs (or can be accepted) is two CLKX cycles.
The word is not loaded into the shift register until the shifter is empty. When DXR
is loaded into XSR, the XRDY bit is set, specifying that the buffer is available
to receive the next word. Four tap points within the transmit-shift register are
used to transmit the word. These tap points correspond to the four-data word
sizes and are illustrated in Figure 12−19. The shift is a left-shift (LSB to MSB)
with the data shifted out of the MSB corresponding to the appropriate tap point.
Figure 12−19. Transmit Buffer Shift Operation
← Shift direction ←
31
32-bit word tap
24 23
24-bit word tap
16 15
16-bit word tap
8
7
0
8-bit word tap
12.2.8 Data-Receive Register
When serial data is input, the receiver shifts the bits into the receive-shift register
(RSR). When the specified number of bits are shifted in, the data-receive register
(DRR) is loaded from RSR, and the RRDY status bit is set. The receiver is doublebuffered. If the DRR has not been read and the RSR is full, the receiver is frozen.
New data coming into the DR pin is ignored. The receive shifter does not write over
the DRR. The DRR must be read to allow new data in the RSR to be transferred
to the DRR. When a write to DRR occurs at the same time that an RSR-to-DRR
transfer takes place, the RSR-to-DRR transfer has priority.
12-28
Serial Ports
Data is shifted to the left (LSB to MSB). Figure 12−20 illustrates what happens
when words less than 32 bits are shifted into the serial port. In this figure, it is
assumed that an 8-bit word is being received and that the upper three bytes
of the receive buffer are originally undefined. In the first portion of the figure,
byte a has been shifted in. When byte b is shifted in, byte a is shifted to the left.
When the data-receive register is read, both bytes a and b are read.
Figure 12−20. Receive Buffer Shift Operation
← Shift direction ←
31
24 23
16
15
8
7
0
After byte a
X
X
X
a
After byte b
X
X
a
b
12.2.9 Serial-Port Operation Configurations
Several configurations are provided for the operation of the serial-port clocks
and timer. The clocks for each serial port can originate either internally or externally. Figure 12−21 shows serial-port clocking in the I/O mode (CLKXFUNC
= 0) when CLKX is either an input or an output. Figure 12−22 shows clocking
in the serial-port mode (CLKXFUNC=1). Both figures use a transmit section
for an example. The same relationship holds for a receive section.
Peripherals
12-29
Serial Ports
Figure 12−21. Serial-Port Clocking in I/O Mode
CLKX FUNC= 0 (I/O mode)
CLKX I/O = 1 (CLKX, an output)
XCLK SRC = 1 (internal CLK for timer)
CLKX FUNC= 0 (I/O mode)
CLKX I/O = 1 (CLKX, an output)
XCLK SRC = 0 (external CLK for timer)
(a)
(b)
Internal
TSTAT
Internal
clock
Timer in
External
Internal External
TSTAT
Timer in
CLKX
CLKX
XSR
XSR
DATAOUT
DATOUT
DATIN
DATIN
CLKX FUNC= 0 (I/O mode)
CLKX I/O = 0 (CLKX, an input)
XCLK SRC = 1 (internal CLK for timer)
CLKX FUNC= 0 (I/O mode)
CLKX I/O = 0 (CLKX, an input)
XCLK SRC = 0 (external CLK for timer)
(c)
(d)
Internal
Internal External
TSTAT
Timer in
XSR
DATOUT (NC)
DATIN
12-30
Internal
clock
TSTAT
External
Timer in
CLKX
XSR
CLKX
DATOUT (NC)
DATIN
Serial Ports
Figure 12−22. Serial-Port Clocking in Serial-Port Mode
CLKX FUNC= 1 (serial-port mode)
CLKX I/O = 1 (output serial-port CLK)
XCLK SRC = 0 or 1
CLKX FUNC= 1 (serial-port mode)
CLKX I/O = 0 (input serial-port CLK)
XCLK SRC = 1 (internal CLK for timer)
(a)
TSTAT
Timer
(b)
TSTAT
Timer
CLKX
XSR
DATOUT (NC)
DATIN
Internal External
Internal External
Internal
clock
Internal
clock
CLKX
XSR
DATOUT (NC)
DATIN
INV
INV
CLKX FUNC= 1 (serial-port mode)
CLKX I/O = 0 (input serial-port CLK)
XCLK SRC = 0 (external CLK for timer)
(c)
Internal
TSTAT
External
Timer
CLKX
XSR
DATOUT (NC)
DATIN
INV
12.2.10 Serial-Port Timing
The formula for calculating the frequency of the serial-port clock with an internally generated clock depends upon the operation mode of the serial-port
timers, defined as:
f (pulse mode) = f (timer clock)/period register
f (clock mode) = f (timer clock)/(2 x period register)
An internally generated clock source f (timer clock) has a maximum frequency
of f(H1)/2. An externally generated serial-port clock f (timer clock) (CLKX or
CLKR) has a maximum frequency of less than f(H1)/2.6. See section 12.1.5
on page 12-7 for information on timer pulse/clock generation.
Transmit data is clocked out on the rising edge of the selected serial-port clock.
Receive data is latched into the receive-shift register on the falling edge of the
serial-port clock. All data is received MSB first and shifted to the left. If fewer than
32 bits are received, the data received is right-justified in the receive buffer.
Peripherals
12-31
Serial Ports
The transmit ready (XRDY) signal specifies that the data-transmit register
(DXR) is available to be loaded with new data. XRDY goes active as soon as
the data is loaded into the transmit-shift register (XSR). The last word may still
be shifting out when XRDY goes active. If DXR is loaded before the last word
has completed transmission, the data bits transmitted are consecutive; that is,
the LSB of the first word immediately precedes the MSB of the second, with
all signaling valid as in two separate transmits. XRDY goes inactive when DXR
is loaded and remains inactive until the data is loaded into the shifter.
The receive ready (RRDY) signal is active as long as a new word of data is
loaded into the data-receive register and has not been read. As soon as the
data is read, the RRDY bit is turned off.
When FSX is specified as an output, the activity of the signal is determined by
the internal state of the serial port. If a fixed data rate is specified, FSX goes
active when DXR is loaded into XSR. One serial-clock cycle later FSX turns
inactive and data transmission begins. If a variable data rate is specified, the
FSX pin is activated when the data transmission begins and remains active
during the entire transmission of the word. Again, the data is transmitted one
clock cycle after it is loaded into the data-transmit register.
An input FSX in the fixed data-rate mode must go active for at least one serialclock cycle and then inactive to initiate the data transfer. The transmitter then
sends the number of bits specified by the XLEN (bit field 19, serial-port globalcontrol register) bits. In the variable data-rate mode, the transmitter begins
sending from the time FSX goes active until the number of specified bits have
been shifted out. In the variable data-rate mode, when the FSX status changes
prior to all the data bits being shifted out, the transmission completes, and the
DX pin is placed in a high-impedance state. An FSR input is exactly complementary to the FSX.
When using an external FSX, if DXR and XSR are empty, a write to DXR results
in a DXR-to-XSR transfer. This data is held in the XSR until an FSX occurs.
When the external FSX is received, the XSR begins shifting the data. If XSR is
waiting for the external FSX, a write to DXR changes DXR, but a DXR-to-XSR
transfer does not occur. XSR begins shifting when the external FSX is received,
or when it is reset using XRESET.
12-32
Serial Ports
12.2.10.1 Continuous Transmit and Receive Modes
When you choose continuous mode, consecutive writes do not generate or
expect new sync pulse signaling. Only the first word of a block begins with
an active synchronization. Thereafter, data is transmitted as long as new
data is loaded into DXR before the last word has been transmitted. As soon
as TXRDY is active and all of the data has been transmitted out of the shift
register, the DX pin is placed in a high-impedance state, and a subsequent
write to DXR initiates a new block and a new FSX.
Similarly with FSR, the receiver continues shifting in new data and loading
DRR. If the data-receive buffer is not read before the next word is shifted in,
you will lose subsequent incoming data. You can use the RFSM bit to terminate
the receive-continuous mode.
12.2.10.2 Handshake Mode
The handshake mode (HS = 1) allows for direct connection between processors.
In this mode, all data words are transmitted with a leading 1 (see Figure 12−23).
For example, in order to transmit an 8-bit word, the first bit sent is a 1, followed
by the 8-bit data word.
Once the serial port transmits a word in this mode, it does not transmit another
word until it receives a separately transmitted 0 bit. Therefore, the 1 bit that
precedes every data word is a request bit.
Figure 12−23. Data Word Format in Handshake Mode
Data word (8 bits)
DX
1
Leading 1
After a serial port receives a word that has been read from the DRR (with the
leading 1), the receiving serial port sends a single 0 to the transmitting serial
port. The single 0 bit acts as an acknowledge bit (see Figure 12−24). This
single acknowledge bit is sent every time the DRR is read, even if the DRR
does not contain new data.
Figure 12−24. Single 0 Sent as an Acknowledge Bit
DX
0
Single 0
Peripherals
12-33
Serial Ports
When the serial port is placed in the handshake mode, the insertion and deletion
of a leading 1 for transmitted data, the sending of a 0 for acknowledgement of
received data, and the waiting for this acknowledge bit are all performed automatically. Using this scheme, it is simple to connect processors with no external
hardware and to guarantee secure communication. Figure 12−25 is a typical
configuration.
In the handshake mode, FSX is automatically configured as an output. Continuous mode is automatically disabled. After a system reset or XRESET, the
transmitter is always permitted to transmit. The transmitter and receiver must
be reset when entering the handshake mode.
Figure 12−25. Direct Connection Using Handshake Mode
’C3x #1
’C3x #2
CLKX
FSX
DX
CLKR
FSR
DR
CLKR
FSR
DR
CLKX
FSX
DX
12.2.11 Serial-Port Interrupt Sources
A serial port has the following interrupt sources:
- Transmit-timer interrupt. The rising edge of XTSTAT causes a single-
cycle interrupt pulse to occur. When XTINT is 0, this interrupt pulse is
disabled.
- Receive-timer interrupt. The rising edge of RTSTAT causes a single-
cycle interrupt pulse to occur. When RTINT is 0, this interrupt pulse is
disabled.
- Transmitter-interrupt. Occurs immediately following a DXR-to-XSR
transfer. The transmitter interrupt is a single-cycle pulse. When the serialport global-control register bit XINT is 0, this interrupt pulse is disabled.
- Receiver-interrupt. Occurs immediately following an RSR-to-DRR trans-
fer. The receiver interrupt is a single-cycle pulse. When the serial-port
global-control register bit RINT is 0, this interrupt pulse is disabled.
The transmit-timer interrupt pulse is ORed with the transmitter interrupt pulse
to create the CPU-transmit interrupt flag XINT. The receive-timer interrupt pulse
is ORed with the receiver interrupt pulse to create the CPU receive-interrupt flag
RINT.
12-34
Serial Ports
12.2.12 Serial-Port Functional Operation
The following paragraphs and figures illustrate the functional timing of the
various serial-port modes of operation. The timing descriptions are presented
with the assumption that all signal polarities are configured to be positive (that
is, CLKXP = CLKRP = DXP = DRP = FSXP = FSRP = 0). Logical timing, in situations where one or more of these polarities are inverted, is the same except
with respect to the opposite polarity reference points (that is, rising vs. falling
edges, etc.).
These discussions pertain to the numerous operating modes and configurations
of the serial-port logic. When it is necessary to switch operating modes or
change configurations of the serial port, you should do so only when XRESET
or RRESET are asserted (low), as appropriate. When transmit configurations
are modified, XRESET should be low, and when receive configurations are
modified, RRESET should be low. When you use handshake mode, however,
since the transmitter and receiver are interrelated, you should make any configuration changes with XRESET and RRESET both low.
All of the serial-port operating configurations can be classified in two categories:
fixed data-rate timing and variable data-rate timing. Both categories support
operation in either burst or continuous mode.
Burst-mode operation with variable data-rate timing is similar to burst-mode
operation with fixed data-rate timing. With variable data-rate timing, however,
FSX/R and data timing differ slightly at the beginning and end of transfers.
Specifically, there are three major differences between fixed and variable datarate timing:
- FSX/R pulses typically last for the entire transfer interval in variable data-
rate timing operation, although FSR and external FSX are ignored after
the first bit transferred. FSX/R pulses in fixed data-rate mode typically last
only one CLKX/R cycle but can last longer.
- With variable data-rate timing, data transfer begins during the CLKX/R
cycle in which FSX/R occurs. With fixed data-rate timing, data transfer begins in the CLKX/R cycle following FSX/R.
- With variable data-rate timing, frame sync inputs are ignored until the end
of the last bit transferred. With fixed data-rate timing, frame sync inputs are
ignored until the beginning of the last bit transferred.
The following paragraphs discuss fixed and variable data-rate operation and all
of their variations.
Peripherals
12-35
Serial Ports
12.2.12.1 Fixed Data-Rate Timing Operation
Fixed data-rate serial-port transfers can occur in two varieties: burst mode and
continuous mode. In burst mode, transfers of single words are separated by
periods of inactivity on the serial port. In continuous mode, there are no gaps
between successive word transfers; the first bit of a new word is transferred
on the next CLKX/R pulse following the last bit of the previous word. This occurs
continuously until the process is terminated. The following variations are
included in fixed data-rate timing operations.
- Fixed Burst Mode
In burst mode with fixed data-rate timing, FSX/FSR pulses initiate transfers,
and each transfer involves a single word. With an internally generated FSX
(see Figure 12−26), transmission is initiated by loading DXR. In this mode,
there is a delay of approximately 2.5 CLKX cycles (depending on CLKX and
H1 frequencies) from the time DXR is loaded until FSX occurs. With an
external FSX, the FSX pulse initiates the transfer, and the 2.5-cycle delay
effectively becomes a setup requirement for loading DXR with respect to
FSX. In this case, you must load DXR no later than three CLKX cycles before
FSX occurs. Once the XSR is loaded from the DXR, an XINT is generated.
Figure 12−26. Fixed Burst Mode
CLKX/R
R/XVAREN = 0
R/XFSM = 0
FSR/FSX (external)
FSX (internal)
DX/DR
A1
DXR loaded
XINT
AN
RINT
In receive operations, once a transfer is initiated, FSR is ignored until the
last bit. For burst-mode transfers, FSR must be low during the last bit, or
another transfer will be initiated. After a full word has been received and
transferred to the DRR, an RINT is generated.
- Fixed Standard Mode
In fixed data-rate mode, you can perform continuous transfers even if
R/XFSM = 0, as long as properly timed frame synchronization is provided,
or as long as DXR is reloaded each cycle with an internally generated FSX
(see Figure 12−27).
12-36
Serial Ports
Figure 12−27. Fixed Standard Mode With Back-to-Back Frame Sync
CLKX/R
FSX (Internal)
R/XVAREN = 0
R/XFSM = 0
FSR/FSX (External)
DR/DX
A1
DXR loaded
with A
XINT
DXR loaded
with B
AN
B1
XINT
RINT
Load DXR with C
read DRR
BN
C1
XINT
RINT
Load DXR with
Dread DRR
For receive operations and with externally generated FSX, once transfers
have begun, frame sync pulses are required only during the last bit transferred to initiate another contiguous transfer. Otherwise, frame sync inputs
are ignored. Continuous transfers occur if the frame sync is held high. With
an internally generated FSX, there is a delay of approximately 2.5 CLKX
cycles from the time DXR is loaded until FSX occurs. This delay occurs
each time DXR is loaded; therefore, during continuous transmission, the
instruction that loads DXR must be executed by the N−3 bit for an N-bit
transmission. Since delays due to pipelining vary, you should incorporate
a conservative margin of safety in allowing for this delay.
Once the process begins, an XINT and an RINT are generated at the beginning of each transfer. The XINT indicates that the XSR has been loaded from
DXR and can be used to cause DXR to be reloaded. To maintain continuous
transmission in fixed rate mode with frame sync, especially with an internally
generated FSX, DXR must be reloaded early in the ongoing transfer.
The RINT indicates that a full word has been received and transferred into
the DRR; RINT indicates an appropriate time to read DRR.
Continuous transfers are terminated by discontinuing frame sync pulses
or, in the case of an internally-generated FSX, not reloading DXR.
- Fixed Continuous Mode
You can accomplish continuous serial-port transfers, without the use of
frame sync pulses, if R/XFSM is set to 1. In this mode, operation of the serial
port is similar to continuous operation with frame sync, except that a frame
sync pulse is involved only in the first word transferred, and no further frame
sync pulses are used. Following the first word transferred (see
Figure 12−28), no internal frame sync pulses are generated, and frame
Peripherals
12-37
Serial Ports
sync inputs are ignored. Additionally, you should set R/XFSM prior to or
during the first word transferred; you must set R/XFSM no later than the
transfer of the N−1 bit of the first word, except for transmit operations. For
transmit operations in the fixed data-rate mode, XFSM must be set no later
than the N−2 bit. You must clear R/XFSM no later than the N−1 bit to be
recognized in the current cycle.
Figure 12−28. Fixed Continuous Mode Without Frame Sync
R/XVAREN = 0
R/XFSM = 1
CLKX/R
FSR/FSX (external)
FSX (internal)
DR/DX
A1
XINT
AN
Set
R/XFSM
B1
XINT
RINT
BN
C1
XINT
RINT
DXR loaded
DXR loaded
Load DXR
read DRR
Load DXR
read DRR
The timing of RINT and XINT and data transfers to and from DXR and
DRR, respectively, are the same as in fixed data-rate standard mode with
back-to-back frame syncs. This mode of operation also exhibits the same
delay of 2.5 CLKX cycles after DXR is loaded before an internal FSX is
generated. As in the case of continuous operation in fixed data-rate mode
with frame sync, you must reload DXR no later than transmission of the
N−3 bit.
- Enabling or Disabling Frame Syncs in Fixed Mode
When you use continuous operation in fixed data-rate mode, you can set
and clear R/XFSM as desired, even during active transfers, to enable or
disable the use of frame sync pulses as dictated by system requirements.
Under most conditions, changing the state of R/XFSM occurs during the
transfer in which the R/XFSM change was made, provided the change
was made early enough in the transfer. For transmit operations with internal FSX in fixed data-rate mode, however, a 1-word delay occurs before
frame sync pulse generation resumes when clearing XFSM to 0 (see
Figure 12−29). In this case, one additional word is transferred before the
next FSX pulse is generated. The clearing of XFSM is recognized during
the transmission of the word currently being transmitted as long as XFSM
is cleared no later than the N−1 bit. The setting of XFSM is recognized as
long as XFSM is set no later than the N−2 bit.
12-38
Serial Ports
Figure 12−29. Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal
1st word
2nd word
3rd word
4th word
5th word
CLKX
FSX
(internal)
DX
A1
LOAD DXR
AN
SET XFSM
B1
BN
C1
CN
D1
DN E1
EN
F1
FN
RESET XFSM
12.2.12.2 Variable Data-Rate Timing Operation
The following variations are included in variable data-rate timing operations.
- Variable Burst Mode
In burst mode with variable data-rate timing, FSX/FSR pulse lasts for the
entire duration of transfer. With an internally generated FSX (see
Figure 12−30), transmission is initiated by loading DXR. In this mode there
is a delay of approximately 3.5 CLKX cycles (depending on CLKX and H1
freqency) from the time DXR is loaded until FSX occurs. With an external
FSX, the FSX pulse initiates the transfer and the 3.5-cycle delay effectively
becomes a setup requirement for loading DXR with respect to FSX. Therefore, in this case, you must load DXR no later than four CLKX cycles before
FSX occurs. Once the XSR is loaded from the DXR, an XINT is generated.
Figure 12−30. Variable Burst Mode
R/XVAREN = 1
R/XFSM = 0
CLKX/R
FSR/FSX (external)
FSX (internal)
DX/DR
DXR loaded
A1
XINT
AN
RINT
Peripherals
12-39
Serial Ports
- Variable Standard Mode
When you transmit continuously in variable data-rate mode with frame sync,
timing is the same as for fixed data-rate mode, except for the differences
between these two modes as described in Section 12.2.12 Serial-Port
Functional Operation, on page 12-35. The only other exception is that you
must reload DXR no later than the N−4 bit to maintain continuous operation of the variable data-rate mode (see Figure 12−31); you must reload
DXR no later than the N−3 bit to maintain continuous operation of the fixed
data-rate mode.
Figure 12−31. Variable Standard Mode With Back-to-Back Frame Syncs
R/XVAREN = 1
R/XFSM = 0
CLKX/R
FSR/FSX (External)
FSX (Internal)
DX/DR
A1
DXR
Loaded
with A
XINT
Load DSR
with B
AN
B1
XINT
RINT
Load DXR with C
Read DRR
BN
C1
C2
XINT
RINT
Load DXR with D
Read DRR
Continuous operation in variable data-rate mode without frame sync (see
Figure 12−32) is similar to continuous operation without frame sync in
fixed data-rate mode (see Figure 12−28). As with variable data-rate standard mode with back-to-back frame syncs, you must reload DXR no later
than the N−4 bit to maintain continuous operation. Additionally, when
R/XFSM is set or cleared in the variable data-rate mode, you must make
the modification no later than the N−1 bit for the result to be affected in the
current transfer.
12-40
Serial Ports
Figure 12−32. Variable Continuous Mode Without Frame Sync
R/XVAREN = 1
R/XFSM = 1
CLKX/R
FSR/FSX (external)
FSX (internal)
DX/DR
A1
AN
B1
BN
C1
C2
XINT
DXR loaded
with A
Set
R/XFS
M
DXR loaded
with B
XINT
RINT
Load DXR with C
read DRR
XINT
RINT
Load DXR with D
read DRR
12.2.13 Serial-Port Initialization/Reconfiguration
The serial ports are controlled through memory-mapped registers on the dedicated peripheral bus. A general procedure for initializing and/or reconfiguring
the serial ports follows.
1) Halt the serial port by clearing the XRESET and/or RRESET bits of the serialport global-control register. To do this, write a 0 to the serial-port globalcontrol register. The serial ports are halted on RESET.
2) Configure the serial port via the serial-port global-control register (with
XRESET = RRESET = 0) and the FSX/DX/CLKX and FSR/DR/CLKR portcontrol registers. If necessary, configure the receive/transmit registers;
timer control (with XHLD = RHLD = 0), timer counter, and timer period.
Refer to section 12.2.14 for more information.
3) Start the serial-port operation by setting the XRESET and RRESET bits
of the serial-port global-control register and the XHLD and RHLD bits of
the serial-port receive/transmit timer-control register, if necessary.
12.2.14 TMS320C3x Serial-Port Interface Examples
In addition to the examples presented in this section, you can find DMA/serial
port initialization examples in Example 12−9 and Example 12−10 on pages
12-78 and 12-79, respectively.
Peripherals
12-41
Serial Ports
12.2.14.1 Handshake Mode Example
When using the handshake mode, the transmit (FSX/DS/CLKX) and receive
(FSR/DR/CLKR) signals transmit and receive data, respectively. Even if the
’C3x serial port is receiving data only with handshake mode, the transmit signals
are still needed to transmit the acknowledge signal. Example 12−3 shows the
serial-port register setup for the ’C3x serial-port handshake communication, as
shown in Figure 12−25 on page 12-34.
Example 12−3. Serial-Port Register Setup #1
Global control
Transmit port control
Receive port control
S_port timer control
S_port timer count
S_port timer period
Note:
=
=
=
=
=
≥
011x0x0xxxx00000000xx01100100b,
0111h
0111h
0Fh
0h
01h (if two C3xs have the same system clock).
x = user-configurable
Since FSX is set as an output and continuous mode is disabled when handshake mode is selected, follow these steps:
1) Set the XFSM and RFSM bits to 0 and the FSXOUT bit to 1 in the globalcontrol register.
2) Set the XRESET, RRESET, and HS bits to 1 in order to start the handshake
communication.
3) Set the polarity of the serial-port pins active (high) for simplification.
4) Although the CLKX/CLKR can be set as either input or output, set the
CLKX as output and the CLKR as input.
The rest of the bits are user-configurable as long as both serial ports have
consistent setup.
You need the serial-port timer only if the CLKX or CLKR is configured as an
output. Since only the CLKX is configured as an output, set the timer control
register to 0Fh. When you use the serial-port timer, set the serial timer register
to the proper value for the clock speed. The serial-port timer clock speed setup
is similar to the ’C3x timer. Refer to Section 12.1, Timers, on page 12-2 for
detailed information on timer clock generation.
The maximum clock frequency for serial transfers is f(CLKIN)/4 if the internal
clock is used and f(CLKIN)/5.2 if an external clock is used. If two ’C3xs have
the same system clock, the timer-period register should be set equal to or
greater than 1, which makes the clock frequency equal to f(CLKIN)/8.
12-42
Serial Ports
Example 12−4 and Example 12−5 are serial-port register setups for the above
case. (Assume two ’C3xs have the same system clock.)
Example 12−4. Serial-Port Register Setup #1
Global control
Transmit port control
Receive port control
S_port timer control
S_port timer count
S_port timer period
=
=
=
=
=
≥
0EBC0064h; 32 bits, fixed data rate, burst mode,
0111h ; FSX (output), CLKX (output) = F(CLKIN)/8
0111h ; CLKR (input), handshake mode, transmit
0Fh ; and receive interrupt is enabled.
0h
01h
Example 12−5. Serial-Port Register Setup #2
Global control
Transmit port control
Receive port control
S_port timer control
S_port timer count
S_port timer period
=
=
=
=
=
≥
0C000364h; 8 bits, variable data rate, burst mode,
0111h; FSX (output), CLKX (output) = f(CLKIN)/24
0111h ; CLKR (input), handshake mode, transmit
0Fh ; and receive interrupt is disabled.
0h
01h
Since the data has a leading 1 and the acknowledge signal is a 0 in the handshake mode, the ’C3x serial port can distinguish between the data and the
acknowledge signal. Even if the ’C3x serial port receives the data before the
acknowledge signal, the data is not misinterpreted as the acknowledge signal
and lost. Additionally, the acknowledge signal is not generated until the data
is read from the data-receive register (DRR); the ’C3x does not transmit the
data and the acknowledge signal simultaneously.
12.2.14.2 CPU Transfer With Serial Port Transmit Polling Method
Example 12−6 sets up the CPU to transfer data (128 words) from an array buffer
to the serial port 0 output register when the previous value stored in the serialport output register has been sent. Serial port 0 is initialized to transmit 32-bit
data words with an internally generated frame sync and a bit-transfer rate of
8H1 cycles/bit.
Peripherals
12-43
Serial Ports
Example 12−6. CPU Transfer With Serial Port Transmit Polling Method
* TITLE: CPU TRANSFER WITH SERIAL-PORT TRANSMIT POLLING METHOD
*
.GLOBAL START
.DATA
SOURCE
.WORD _ARRAY
.BSS _ARRAY,128
; DATA ARRAY LOCATED IN .BSS SECTION
; THE UNDERSCORE USED IS JUST TO MAKE IT
; ACCESSIBLE FROM C (OPTIONAL)
SPORT
.WORD 808040H
; SERIAL-PORT GLOBAL CONTROL REG ADDRESS
SPRESET .WORD 008C0044
; SERIAL-PORT RESET
SGCCTRL .WORD 048C0044H
; SERIAL-PORT GLOBAL CONTROL REG INITIALIZATION
SXCTRL
.WORD 111H
; SERIAL-PORT TX PORT CONTROL REG INITIALIZATION
STCTRL
.WORD 00FH
; SERIAL-PORT TIMER CONTROL REG INITIALIZATION
STPERIOD .WORD 00000002h
; SERIAL-PORT TIMER PERIOD
RESET
.WORD 0H
; SERIAL-PORT TIMER RESET VALUE
.TEXT
START
LDP RESET
; LOAD DATA PAGE POINTER
ANDN 10H,IE
; DISABLE SERIAL-PORT TRANSMIT INTERRUPT TO CPU
* SERIAL PORT INITIALIZATION
LDI @SPORT,AR1
LDI @RESET,R0
LDI 4,IR0
STI R0,*+AR1(IR0)
LDI @SPRESET,R0
STI R0,*AR1
LDI @SXCTRL,R0
STI R0,*+AR1(3)
LDI @STPERIOD,R0
STI R0,*+AR1(6)
LDI @STCTRL,R0
STI R0,*+AR1(4)
LDI @SGCCTRL,R0
STI R0,*AR1
; SERIAL-PORT TIMER RESET
; SERIAL-PORT RESET
; SERIAL-PORT TX CONTROL REG INITIALIZATON
; SERIAL−PORT TIMER PERIOD INITIALIZATION
; SERIAL-PORT TIMER CONTROL REG INITIALIZATION
; SERIAL-PORT GLOBAL CONTROL REG INITIALIZATION
* CPU WRITES THE FIRST WORD
LDI @SOURCE,AR0
LDI *AR0++,R1
STI R1,*+AR1(8)
* CPU WRITES 127 WORDS TO THE SERIAL PORT OUTPUT REG
LDI 8,IR0
LDI 2,R0
LDI 126,RC
RPTB LOOP
WAIT
AND *AR1,R0,R2
BZ WAIT
LOOP
STI R1,*+AR1(IR0)
|| LDI *++AR0(1),R1
BU $
.END
12-44
; WAIT UNTIL XRDY BIT = 1
Serial Ports
12.2.14.3 DMA Transfer With Serial Port Interrupt
Example 12−8 and Example 12−9 of Section 12.3.11 on page 12-76 use the
DMA synchronized to serial port interrupts to transfer data (128 words) from
an array buffer to the serial port0 output register.
12.2.14.4 Serial Analog Interface Chips Interface Example
The TLC320C4x analog interface chips (AIC) from Texas Instruments offer a
zero-glue-logic interface to the ’C3x family of DSPs. The interface is shown in
Figure 12−33 as an example of the ’C3x serial-port configuration and operation.
Figure 12−33. TMS320C3x Zero-Glue-Logic Interface to TLC320C4x Example
TMS320C3x
XF0
CLKR0
CLKX0
FSR0
DR0
FSX0
DX0
TCLK0
TLC320C4x
RESET
SCLK
FSR
DR
FSX
DX
MCLK
WORD
VCC
OUT+
OUT−
Analog
Out
IN+
IN−
Analog
In
GND
The ’C3x resets the AIC through the external pin XF0. It also generates the
master clock for the AIC through the timer 0 output pin, TCLK0. (Precise selection of a sample rate may require the use of an external oscillator rather than
the TCLK0 output to drive the AIC MCLK input.) In turn, the AIC generates the
CLKR0 and CLKX0 shift clocks as well as the FSR0 and FSX0 frame synchronization signals.
A typical use of the AIC requires an 8-kHz sample rate of the analog signal.
If the clock input frequency to the ’C3x device is 30 MHz, you should load the
following values into the serial port and timer registers.
Serial Port:
Port global-control register
FSX/DX/CLKX port-control register
FSR/DR/CLKR port-control register
0E970300h
00000111h
00000111h
Timer:
Timer global-control register
Timer-period register
000002C1h
00000001h
Peripherals
12-45
Serial Ports
12.2.14.5 Serial Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Interface Example
The DSP201/2 and DSP101/2 family of D/As and A/Ds from Burr Brown also
offer a zero-glue-logic interface to the ’C3x family of DSPs. The interface is
shown in Example 12−7. This interface is used as an example of the ’C3x serial
port configuration and operation.
Example 12−7. TMS320C3x Zero-Glue-Logic Interface to Burr Brown A/D and D/A
Burr Brown DSP102 A/D
CASC
Burr Brown DSP202 D/A
+5 V
+5 V
CASC
’C3x
XCLK
± 2.75 V
VINA
SOUTA
SYNC
± 2.75 V
1 MΩ
XCLK
DR0
SINA
DX0
SYNC
FSX0
SSF
CONV
VOUTA
±3V
VOUTB
±3V
SINB
FSR0
VINB
OSC0
OSC1
CLKR0 CLKX0
+5 V
+5 V
+5 V
TCLK0
SSF
SWL
CONV
12.29 MHz
22 pF
22 pF
The DSP102 A/D is interfaced to the ’C3x serial-port receive side; the DSP202
D/A is interfaced to the transmit side. The A/Ds and D/As are hard-wired to run
in cascade mode. In this mode, when the ’C3x initiates a convert command to
the A/D via the TCLK0 pin, both analog inputs are converted into two 16-bit
words, which are concatenated to form one 32-bit word.
1) The A/D signals the ’C3x via the A/D’s SYNC signal (connected to the
FSR0 pin) that serial data is to be transmitted.
2) The 32-bit word is then serially transmitted, MSB first, out the SOUTA serial
pin of the DSP102 to the DR0 pin of the ’C3x serial port.
3) The ’C3x is programmed to drive the analog interface bit clock from the
CLKX0 pin of the ’C3x.
12-46
Serial Ports
4) The bit clock drives both the A/D’s and D/A’s XCLK input.
5) The ’C3x transmit clock also acts as the input clock on the receive side of
the ’C3x serial port.
6) Since the receive clock is synchronous to the internal clock of the ’C3x, the
receive clock can run at full speed (that is, f(H1)/2).
Similarly, on receiving a convert command, the pipelined D/A converts the last
word received from the ’C3x and signals the ’C3x via the SYNC signal (connected
to the ’C3x FSX0 pin) to begin transmitting a 32-bit word representing the two
channels of data to be converted. The data transmitted from the ’C3x DX0 pin is
input to both the SINA and SINB inputs of the D/A as shown in Example 12−7.
The ’C3x is set up to transfer bits at the maximum rate of about 8 Mbps, with a
dual-channel sample rate of about 44.1 kHz. Assuming a 32-MHz CLKIN, you
can configure this standard-mode fixed-data-rate signaling interface by setting
the registers as described below:
Serial Port:
Port global-control register
FSX/DX/CLKX port-control register
FSR/DR/CLKR port-control register
Receive/transmit timer-control register
0EBC0040h
00000111h
00000111h
0000000Fh
Timer:
Timer global-control register
Timer-period register
000002C1h
000000B5h
Peripherals
12-47
DMA Controller
12.3 DMA Controller
The DMA controller is a programmable peripheral that transfers blocks of data
to any location in the memory map without interfering with CPU operation. The
’C3x can interface to slow, external memories and peripherals without reducing
throughput to the CPU. The ’C3x DMA controller features are:
- Transfers to and from anywhere in the processor’s memory map. For
example, transfers can be made to and from on-chip memory, off-chip
memory, and on-chip serial ports.
- One DMA channel for memory-to-memory transfers in ‘C30 and
‘C31/VC33. Two DMA channels for memory-to-memory transfers in ‘C32.
- Concurrent CPU and DMA controller operation with DMA transfers at the
same rate as the CPU (supported by separate internal DMA address and
data buses).
- Source and destination-address registers with auto increment/decrement.
- Synchronization of data transfers via external and internal interrupts.
12.3.1 DMA Functional Description
The DMA controller supports one (‘C30 and ‘C31/VC33) or two (‘C32) DMA channels that perform transfers to and from anywhere in the ‘C3x memory map.
Each DMA channel is controlled by four registers that are mapped in the ‘C3x
peripheral address space, as shown in Figure 12−35. The major DMA registers
are described in Section 12.3.3.
The DMA controller has dedicated on-chip address and data buses (see
Figure 2−5 through Figure 2−7 on pages 2-14 through 2-16 for a block diagram of the peripherals of the ‘C3x). All accesses made by the DMA channels
are arbitrated in the DMA controller and take place over these dedicated
buses. The DMA channels transfer data in a sequential time-slice fashion,
rather than simultaneously, because they share common buses.
The DMA channels can run constantly or can be triggered by external (INT3−0)
or internal (on-chip timers and serial ports) interrupts.
12-48
DMA Controller
12.3.1.1
TMS320C30 and TMS320C31/VC33 DMA Controller
The ’C30 and ’C31/VC33 have an on-chip direct memory access (DMA) controller that reduces the need for the CPU to perform input/output functions. The
DMA controller can perform input/output operations without interfering with the
operation of the CPU. Therefore, it is possible to interface the ’C30 and
’C31/VC33 to slow external memories and peripherals (A/Ds, serial ports, etc.)
without reducing the computational throughput of the CPU. The result is improved system performance and decreased system cost.
12.3.1.2
TMS320C32 Two-Channel DMA Controller
The ’C32 has an improved DMA that supports two channels and configurable
priorities. The next sections discuss the new features.
The ’C32 has a two-channel (channel 0 and channel 1) DMA instead of a onechannel DMA as in the ’C30/’C31/VC33 devices. The ’C32’s DMA functions
similarly to that of the ’C30/’C31/VC33 DMA but with the addition of DMA/CPU
priority scheme and inter-DMA priority mode. Although the ’C32 CPU supports
both floating-point and integer data access with different data size from the external memory, the ’C32’s DMA transfer is strictly an integer data transfer. The
integer data access of the ’C32 DMA is the same as the CPU integer data access
— 32-bit internal and data size conversion at the external memory interface port.
Peripherals
12-49
DMA Controller
12.3.2 DMA Basic Operation
If a block of data is to be transferred from one region in memory to another region
in memory (as shown in Figure 12−34), the following sequence is performed:
DMA Registers Initialization
1) The source-address register of a DMA channel is loaded with the address
of the memory location to read from.
2) The destination-address register of the same DMA channel is loaded with
the address of the memory location to write to.
3) The transfer counter is loaded with the number of words to be transferred.
4) The DMA channel control register is loaded with the appropriate modes
to synchronize the DMA controller reads and writes with interrupts.
DMA Start
5) The DMA controller is started through the DMA START field in the DMA
channel control register.
Word Transfers
6) The DMA channel reads a word from the source-address register and
writes it to a temporary register within the DMA channel.
7) After a read by the DMA channel, the source-address register is incremented, decremented, or unchanged depending on the INCSRC or
DECSRC bit fields of DMA channel control register.
8) After the read operation completes, the DMA channel writes the temporary
register value to the destination-address pointed to by the destinationaddress register.
9) After the destination-address has been fetched, the transfer-counter register is decremented and the destination-address register is incremented,
decremented, or unchanged, depending on the INCDST or DECDST bit
fields of the DMA channel control register.
10) During every data write, the transfer counter is decremented. The block
transfer terminates when the transfer counter reaches zero and the write
of the last transfer is completed. The DMA channel sets the transfer-counter
interrupt (TCINT) flag in the DMA channel control register.
12-50
DMA Controller
After the completion of a block transfer, the DMA controller can be programmed
to do several things:
- Stop until reprogrammed (TC = 1)
- Continue transferring data (TC = 0)
- Generate an interrupt to signal the CPU that the block transfer is complete
(TCINT = 1)
The DMA can be stopped by setting the START bits to 00, 01, or 10. When the
DMA is restarted (START = 11), it completes any pending transfer.
Figure 12−34. DMA Basic Operation
External or Internal
memory
DMA
channel
Memory pointed to by DMA
source-address register
Temporary register
External or Internal
memory
Memory pointed to by DMA
destination-address register
12.3.3 DMA Registers
Each DMA channel has four registers designated as follows:
- Control register: contains the status and mode information about the
associated DMA channel
- Source-address register: contains the memory address of data to be
read
- Destination-address register: contains the memory address where data
is written
- Transfer-counter register: contains the block size to move
After reset, the control register, the transfer counter, and the auxiliary transfercounter registers are set to 0s and the other registers are undefined.
Figure 12−36 shows these registers for ’C30 and ’C31/VC33. Figure 12−37
shows these registers for ’C32.
The format of the DMA-channel control register is shown in Figure 12−35. The
text following the figure describes the functions of each field in the register.
Peripherals
12-51
DMA Controller
At reset, each DMA-channel control register is set to 0. This makes the DMA
channels lower-priority than the CPU, sets up the source address and destination
address to be calculated through linear addressing, and configures the DMA
channel in the unified mode.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 12−35. Memory-Mapped Locations for DMA Channels
Address
Register
808000h
DMA 0 global control
808004h
DMA 0 source address
808006h
DMA 0 destination address
808008h
DMA 0 transfer counter
808010h
DMA 1 global control†
808014h
DMA 1 source address†
808016h
DMA 1 destination address†
808018h
DMA 1 transfer counter†
† ’C32 only
12-52
DMA Controller
12.3.3.1 DMA Global-Control Register
The global-control register controls the state in which the DMA controller
operates. This register also indicates the status of the DMA, which changes
every cycle. Source and destination addresses can be incremented, decremented, or synchronized using specified global-control register bits. At system
reset, all bits in the DMA control register are cleared to 0. Figure 12−36 shows
the global-control registers for the ’C30 and ’C31/VC33 devices. Figure 12−37
and Figure 12−38 show the global-control registers for the ’C32. Table 12−6
shows the register bits, bit names, and bit functions.
Figure 12−36. TMS320C30 and TMS320C31/VC33 DMA Global-Control Register
15 14
31
xx
12
xx
11
10
TCINT
R/W
Notes:
9
8
TC
SYNC
R/W
R/W
7
6
DECDST INCDST
R/W
5
4
DECSRC
INCSRC
R/W
R/W
3
2
1
0
STAT
START
R
R/W
R/W
1) R = read, W = write
2) xx = reserved bit, read as 0
Figure 12−37. TMS320C32 DMA0 Global-Control Register
31
15
xx
Notes:
14
11
10
PRIORITY
MODE
13
DMAO
PRI
12
TCINT
TC
9
SYNC
8
7
DECDST
INCDST
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
5
4
3
2
1
0
INCSRC
STAT
START
R/W
R/W
R
R/W
5
4
DECSRC
INCSRC
R/W
R/W
DECSRC
1) R = read, W = write
2) xx = reserved bit, read as 0
Figure 12−38. TMS320C32 DMA1 Global-Control Register
31
15
xx
14
xx
13
12
DMA1
PRI
11
TCINT
R/W
Notes:
R/W
10
9
8
7
TC
SYNC
DECDST
R/W
R/W
R/W
6
INCDST
R/W
3
2
STAT
R
1
0
START
R/W
1) R = read, W = write
2) xx = reserved bit, read as 0
Peripherals
12-53
DMA Controller
Table 12−6. DMA Global-Control Register Bits Summary
Abbreviation
START
Reset
Value
00
Name
Description
DMA start control
Controls the state in which the DMA starts and stops. The
DMA may be stopped without any loss of data.
The following table summarizes the START bits and DMA
operation:
Bit 1
Bit 0
Function
0
0
DMA read or write cycles in progress are
completed; any data read is ignored. Any
pending read or write is cancelled. The
DMA is reset so that when it starts, a new
transaction begins; that is, a read is performed (Reset value).
0
1
If a read or write has begun, it is completed
before it stops. If a read or write has not
begun, no read or write is started.
1
0
If a DMA transfer has begun, the entire
transfer is complete (including both read
and write operations) before stopping. If a
transfer has not begun, none is started.
1
1
DMA starts from reset or restarts from the
previous state.
When the DMA completes a transfer, the START bits remain
in 11 (base 2). The DMA starts when the START bits are set
to 11 and one of the following conditions applies:
STAT
00
DMA status
-
The transfer counter is set to a value different from 0x0.
-
The TC bit is set to 0.
Indicates the status of the DMA and changes every cycle.
The following table summarizes the STAT bits and DMA status.
12-54
Bit 3
Bit 2
Function
0
0
The DMA is being held between DMA
transfer (between a write and a read). This
is the value at reset.
0
1
DMA is being held in the middle of a DMA
transfer (between a read and a write).
1
0
Reserved.
1
1
DMA busy. DMA is performing a read or
write or waiting for a source or destination
synchronization interrupt.
DMA Controller
Table 12−6. DMA Global-Control Register Bits Summary (Continued)
Abbreviation
Reset
Value
Name
Description
INCSRC
0
DMA source address
increment mode
If INCSRC = 1, the source address is incremented after every
read.
DECSRC
0
DMA source address
decrement mode
If DECSRC = 1, the source address is decremented after
every read.
If INCSRC = DECSRC, the source address is not modified
after a read.
INCDST
0
DMA destination
address increment
mode
If INCDST = 1, the destination address is incremented after
every write.
DECDST
0
DMA destination
address decrement
mode
If DECDST = 1, the destination address is decremented after
every write.
DMA synchronization
mode
Determines the timing synchronization between the events
initiating the source and destination transfers.
SYNC
0
If INCDST = DECDST, the destination address is not modified
after a write.
The following table summarizes the SYNC bits and DMA
synchronization.
TC
0
DMA transfer mode
Bit 9
Bit 8
Function
0
0
No synchronization. Enabled interrupts
are ignored (reset value).
0
1
Source synchronization. A read is performed when an enabled interrupt occurs.
1
0
Destination synchronization. A write is performed when an enabled interrupt occurs.
1
1
Source and destination synchronization. A
read is performed when an enabled interrupt
occurs. A write is then performed when the
next enabled interrupt occurs.
Affects the operation of the transfer counter.
If TC = 0, transfers are not terminated when the transfer
counter becomes 0.
If TC = 1, transfers are terminated when the transfer
counter becomes 0.
TCINT
0
DMA transfer counter
interrupt mode
If TCINT = 1, the DMA interrupt is set when the transfer
counter makes a transition to 0.
If TCINT = 0, the DMA interrupt is not set when the transfer
counter makes a transition to 0.
Peripherals
12-55
DMA Controller
Table 12−6. DMA Global-Control Register Bits Summary (Continued)
Abbreviation
DMA0 PRI
Reset
Value
Name
Description
00
CPU/DMA channel 0
priority mode
(on the DMA0 control register) (’C32 only)
00
CPU/DMA channel 1
priority mode
(on the DMA1 control register) (‘C32 only)
DMA1 PRI
Configures CPU/DMA controller priority. (See Section 12.3.6
on page 12-64).
The following table explains the DMA PRI bits and CPU/
DMA priorities.
Bit 13 Bit 12 Function
PRIORITY
MODE
0
DMA channels priority
mode
0
0
DMA has lower priority than the CPU
access. If the DMA channel and the CPU
are requesting the same resource, the
CPU has priority (reset value).
0
1
Reserved.
1
0
Rotating arbitration, which sets priorities
be tween the CPU and DMA channel by
alternating their accesses (but not exactly
equally). Priority rotates between the CPU
and DMA accesses when they conflict
during consecutive instruction cycles.
1
1
DMA has higher priority than the CPU
access. Ift he DMA channel and the CPU
are requesting the same resource, the
DMA has priority.
If PRIORITY MODE = 0, fixed priority for the two DMA channels. DMA channel 0 always has priority over DMA channel 1.
If priority mode = 1, rotating priority for the two DMA channels.
DMA channel 0 has priority after the device is reset. After
reset, the last channel serviced has the lowest priority. The arbitration is performed at DMA service boundaries, that is,
after either a DMA read or DMA write.
See Section 12.3.5 on page 12-62 for more information.
12-56
DMA Controller
12.3.3.2
Destination-Address and Source-Address Registers
The DMA destination-address and source-address registers are 24-bit registers
whose contents specify destination and source addresses. As specified by
control bits DECSRC, INCSRC, DECDST, and INCDST of the DMA globalcontrol register, these registers are incremented, decremented, or remain
unchanged at the end of the corresponding memory access; that is, the source
register for a read and the destination register for a write (see Figure 12−39).
On system reset, 0 is written to these registers.
Figure 12−39. DMA Controller Address Generation
DMA
address
bus
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
0
1
−1
DMA source-address register
INCSRC
DECSRC
DMA source-address
generator
DMA
address
bus
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
0
1
−1
DMA destination-address register
INCDST
DECDST
DMA destination-address
generator
Peripherals
12-57
DMA Controller
12.3.3.3
Transfer-Counter Register
The transfer-counter register is a 24-bit register that contains the number of
words to be transmitted. Figure 12−40 shows the transfer-counter operation.
It is controlled by a 24-bit counter that decrements at the beginning of a DMA
memory write. In this way, it can control the size of a block of data transferred.
The transfer-counter register is set to 0 at system reset. When the TCINT bit
of the DMA global-control register is set, the transfer-counter register causes
a DMA interrupt flag to be set when 0 is reached.
The counter is decremented after completing the destination-address fetch.
The interrupt is generated after the transfer counter is decremented and after
the completion of the write of the last transfer.
The decrementer checks whether the transfer counter equals 0 after the decrement is performed. As a result, if the counter register has a value of 1, then the
DMA channel can be halted after only one transfer is performed. Thus, by setting the transfer counter to 1, the DMA channel transfers the minimum possible
number of words (1 time). The value of the transfer counter is treated as an unsigned integer. Transfers can be halted when a 0 value is detected after a decrement. If the DMA controller channel is not halted after the transfer reaches zero,
the counter continues decrementing below 0. Thus, by setting the transfer
counter to 0, the DMA channel transfers the maximum possible number of
words (100 0000h times).
12-58
DMA Controller
Figure 12−40. Transfer-Counter Operation
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Transfer-counter register
Decrementer
Compare
to 0
?
No
Yes
Is
TCINT=1
?
No
Yes
DMA interrupt generated
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
No
Is
TC=1
?
Yes
Halt
12.3.4 CPU/DMA Interrupt-Enable Register
The CPU/DMA interrupt-enable register (IE) is a 32-bit register located in the
CPU register file. The CPU interrupt-enable bits are in locations 10−1. The DMA
interrupt-enable bits are in locations 26−16. A 1 in a CPU/DMA interrupt-enable
register bit enables the corresponding interrupt. A 0 disables the corresponding
interrupt. At reset, 0 is written to this register.
Figure 12−41 shows the CPU/DMA interrupt-enable registers for the ‘C30 and
‘C31/VC33. Figure 12−42 shows the CPU/DMA interrupt-enable register for the
‘C32. Table 12−7 describes the register bits, bit names, and bit functions.
Peripherals
12-59
DMA Controller
Figure 12−41. TMS320C30 and TMS320C31/VC33 CPU/DMA
Interrupt-Enable Register
31 30 29 28 27
xx
xx
xx xx xx
26
25
24
23
22
21
20
19
18
17
16
EDINT
(DMA)
ETINT1
(DMA)
ETINT0
(DMA)
ERINT1
(DMA)
EXINT1
(DMA)
ERINT0
(DMA)
EXINT0
(DMA)
EINT3
(DMA)
EINT2
(DMA)
EINT1
(DMA)
EINT0
(DMA)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15 14 13 12 11
xx
xx
Notes:
xx xx xx
10
9
8
7
6
5
4
3
2
1
0
EDINT
(CPU)
ETINT1
(CPU)
ETINT0
(CPU)
ERINT1
(CPU)
EXINT1
(CPU)
ERINT0
(CPU)
EXINT0
(CPU)
EINT3
(CPU)
EINT2
(CPU)
EINT1
(CPU)
EINT0
(CPU)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1) R = read, W = write
2) xx = reserved bit, read as 0
Figure 12−42. TMS320C32 CPU/DMA Interrupt-Enable Register
31
30
29
28
27
23
22
21
20
EINT3
EINT2
EINT1
EINT0
EDINT0
EDINT1 ETINT1 ETINT0
ETINT1
ETINT0
ERINT0
EXINT0
EINT3
EINT2
(DMA1)
(DMA1)
(DMA1)
(DMA0)
(DMA1)
(DMA1)
(DMA1)
(DMA0)
(DMA0)
(DMA0)
R/W
R/W
R/W
R/W
15
14
xx
xx
(DMA1) (DMA1)
R/W
13
xx
R/W
12
xx
26
R/W
R/W
11
EDINT1
(CPU)
10
EDINT0
(CPU)
R/W
Notes:
1) R = read, W = write
2) xx = reserved bit, read as 0
12-60
R/W
25
24
(DMA0) (DMA0)
R/W
9
R/W
8
ETINT1
(CPU)
ETINT0
(CPU)
R/W
R/W
R/W
7
xx
R/W
6
xx
R/W
R/W
5
4
ERINT0 EXINT0
(CPU)
(CPU)
R/W
R/W
19
3
18
17
EINT1
16
EINT0
(DMA0) (DMA0)
R/W
R/W
2
1
0
EINT3
(CPU)
EINT2
(CPU)
EINT1
(CPU)
EINT0
(CPU)
R/W
R/W
R/W
R/W
DMA Controller
Table 12−7. CPU/DMA Interrupt-Enable Register Bits
Abbreviation
Reset
Value Description
EINT0 (CPU)
0
CPU external interrupt 0 enable
EINT1 (CPU)
0
CPU external interrupt 1 enable
EINT2 (CPU)
0
CPU external interrupt 2 enable
EINT3 (CPU)
0
CPU external interrupt 3 enable
EXINT0 (CPU)
0
CPU serial port 0 transmit interrupt enable
ERINT0 (CPU)
0
CPU serial port 0 receive interrupt enable
EXINT1 (CPU)
0
CPU serial port 1 transmit interrupt enable (’C30 only)
ERINT1 (CPU)
0
CPU serial port 1 receive interrupt enable (’C30 only)
ETINT0 (CPU)
0
CPU timer0 interrupt enable
ETINT1 (CPU)
0
CPU timer1 interrupt enable
EDINT (CPU)
0
CPU DMA controller interrupt enable (’C30 and
’C31/VC33 only)
EDINT0 (CPU)
0
CPU DMA0 controller interrupt enable (’C32 only)
EDINT1 (CPU)
0
CPU DMA1 controller interrupt enable (’C32 only)
EINT0 (DMA)
0
DMA external interrupt 0 enable (’C30 and ’C31/VC33
only)
EINT1 (DMA)
0
DMA external interrupt 1 enable (’C30 and ’C31/VC33
only)
EINT2 (DMA)
0
DMA external interrupt 2 enable (’C30 and ’C31/VC33
only)
EINT3 (DMA)
0
DMA external interrupt 3 enable (’C30 and ’C31/VC33
only)
EINT0 (DMA0)
0
DMA0 external interrupt 0 enable (’C32 only)
EINT1 (DMA0)
0
DMA0 external interrupt 1 enable (’C32 only)
EINT2 (DMA0)
0
DMA0 external interrupt 2 enable (’C32 only)
EINT3 (DMA0)
0
DMA0 external interrupt 3 enable (’C32 only)
EXINT0 (DMA)
0
DMA serial port 0 transmit interrupt enable
(’C30 and ’C31/VC33 only)
ERINT0 (DMA)
0
DMA serial port 0 receive interrupt enable
(’C30 and ’C31/VC33 only)
EXINT1 (DMA)
0
DMA serial port 1 transmit interrupt enable (’C30 only)
Peripherals
12-61
DMA Controller
Table 12−7. CPU/DMA Interrupt-Enable Register Bits (Continued)
Abbreviation
Reset
Value Description
ERINT1 (DMA)
0
DMA serial port 1 receive interrupt enable (’C30 only)
EXINT0 (DMA0)
0
DMA0 serial port 1 transmit interrupt enable (’C32 only)
ERINT0 (DMA1)
0
DMA1 serial port 1 receive interrupt enable (’C32 only)
ETINT0 (DMA)
0
DMA timer0 interrupt enable (’C30 and ’C31/VC33)
ETINT1 (DMA)
0
DMA timer1 interrupt enable (’C30 and ’C31/VC33 only)
ETINT0 (DMA0)
0
DMA0 timer1 interrupt enable (’C32 only)
ETINT1 (DMA0)
0
DMA0 timer1 interrupt enable (’C32 only)
ETINT0 (DMA1)
0
DMA1 timer0 interrupt enable (’C32 only)
ETINT1 (DMA1)
0
DMA1 timer1 interrupt enable (’C32 only)
EDINT (DMA)
0
DMA controller interrupt enable (’C30 and ’C31/VC33)
EDINT1 (DMA0)
0
DMA0-DMA1 controller interrupt enable (’C32 only)
EDINT0 (DMA1)
0
DMA1-DMA0 controller interrupt enable (’C32 only)
EINT0 (DMA1)
0
DMA1 external interrupt 0 enable (’C32 only)
EINT1 (DMA1)
0
DMA1 external interrupt 1 enable (’C32 only)
EINT2 (DMA1)
0
DMA1 external interrupt 2 enable (’C32 only)
EINT3 (DMA1)
0
DMA1 external interrupt 2 enable (’C32 only)
12.3.5 TMS320C32 DMA Internal Priority Schemes
Because all accesses made by the two DMA channels take place over one
common internal DMA data and address bus, a priority scheme for bus arbitration is required. Within the DMA controller, two priority schemes are used to
designate which channel is serviced next:
- A fixed priority scheme with channel 0 always having the highest priority
and channel 1 the lowest
- A rotating priority scheme that places the most recently serviced channel
at the bottom of the priority list (default setup after reset)
12.3.5.1 Fixed Priority Scheme
This scheme provides a fixed (unchanging) priority for each channel as follows:
12-62
DMA Controller
Priority
Channel
Highest
0
Lowest
1
To select fixed priority, set the PRIORITY MODE bit (bit 14) of channel 0’s
DMA-channel control register to 1.
Peripherals
12-63
DMA Controller
12.3.5.2 Rotating Priority Scheme
In a rotating priority scheme, the last channel serviced becomes the lowest
priority channel. The other channel sequentially rotates through the priority list
with the lowest channel next to the last-serviced channel becoming the highest
priority on the following request. The priority rotates every time the channel
most recently granted priority completes its access. At system reset, the
channels are ordered from highest to lowest priority (0, 1).
To select this scheme, set the PRIORITY MODE bit (bit 14) of channel 0’s DMA
control register to 0.
12.3.6 CPU and DMA Controller Arbitration
The DMA controller transfers data on its own internal buses. Arbitration is necessary only when a resource conflict exists between the DMA controller and the
CPU. The arbitration causes no delay. When there is no conflict, the CPU and
DMA controller accesses proceed in parallel.
All arbitration between the CPU and the DMA controller is on an access basis.
DMA controller internal memory access starts during H3 (see Section 8.5,
Clocking Memory Access, for more information).
When the CPU and DMA controllers request the same resource, priority is
determined as follows:
- For the ‘C30 and ‘C31/VC33, the CPU always has higher priority, thus the
DMA must wait until the CPU frees the resource.
- For the ‘C32, the DMA channel’s DMA PRI bits (bits 12 and 13 of the channel
control register) define the arbitration rules (as shown in Table 12−8). The
CPU has higher priority than the DMA when DMA PRI = 002; it has lower
priority than the DMA when DMA PRI = 112. They rotate priority when DMA
PRI = 012.
12-64
DMA Controller
Table 12−8.TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules
DMA PRI
(Bits 13−12)
Description
00
DMA access is lower priority than the CPU access. If the DMA
channel and the CPU request the same resource, then the CPU
has priority. (DMA PRI bits are set to 002 at reset.)
01
This setting selects rotating arbitration, which sets priorities between
the CPU and DMA channel by alternating their accesses, but not
exactly equally. Priority rotates between CPU and DMA accesses
when they conflict during consecutive instruction cycles. The first
time the DMA channel and the CPU request the same resource,
the CPU has priority. If, in the following instruction cycle, the DMA
controller and the CPU again request the same resource, the DMA
has priority. Alternate access continues as long as the CPU and
DMA requests conflict in consecutive instruction cycles. When
there is no conflict in a previous instruction cycle, the CPU has
priority.
10
Reserved
11
DMA access is higher priority than the CPU access. If the DMA
channel and the CPU request the same resource, the DMA has
priority.
12.3.7 DMA and Interrupts
The DMA controller uses interrupts in the following way:
- It can send interrupts to the CPU or other DMA channel when a block
transfer finishes. See the TCINT bit field in the DMA global-control register
(Figure 12−36, Figure 12−37, or Figure 12−38 on page 12-53). The
EDINT bit field (’C30 and ’C31/VC33) or the EDINT0 and EDINT1 bit fields
(’C32) in the interrupt-enable register must be set to allow the CPU to be
interrupted by the DMA.
- It can receive interrupts from the external interrupt pins (INT3 −0), the
timers, the serial ports, or other DMA channel.
This section explains how the DMA receives interrupts. This process is called
synchronization.
All of the interrupts that the DMA controller receives are detected by the CPU
interrupt controller and latched by the CPU in the appropriate interrupt-flag
register.
Peripherals
12-65
DMA Controller
The DMA and the CPU can respond to the same interrupt if the CPU is not
involved in any pipeline conflict or in any instruction that halts instruction fetching.
Refer to section 7.6.2, Interrupt Vector Table and Prioritization, on page 7-29 for
more details. It is also possible for different DMA channels to respond to the same
interrupt. If the same interrupt is selected for source and destination synchronization, both read and write cycles are enabled with a single incoming interrupt.
12.3.7.1
Interrupts and Synchronization of DMA Channels
You can use interrupts to synchronize DMA channels. This section describes
the following four synchronization mechanisms:
- No synchronization (SYNC = 0 0)
When SYNC = 0 0, no synchronization is performed. The DMA performs
reads and writes whenever there are no conflicts. All interrupts are ignored
and are considered to be globally disabled. However, no bits in the DMA
interrupt-enable register are changed. Figure 12−43 shows the synchronization mechanism when SYNC = 0 0.
Figure 12−43. Mechanism for No DMA Synchronization
Start
DMA channel performs a read
DMA channel performs a write
Go to start
- Source synchronization (SYNC = 0 1)
When SYNC = 0 1, the DMA is synchronized to the source (see
Figure 12−44). A read is not performed until an interrupt is received by the
DMA. Then all DMA interrupts are disabled globally. However, no bits in
the DMA interrupt-enable register are changed.
12-66
DMA Controller
Figure 12−44. Mechanism for DMA Source Synchronization
Start
Idle until enabled interrupt is received
Disable DMA interrupts globally
Clear corresponding IF bit
DMA channel performs a read
Enable DMA interrupts globally
DMA channel performs a write
Go to start
- Destination synchronization (SYNC = 1 0)
When SYNC = 1 0, the DMA is synchronized to the destination. First, all
interrupts are ignored until the read is complete. Though the DMA interrupts
are considered globally disabled, no bits in the DMA interrupt-enable register are changed. A write is not performed until an interrupt is received by the
DMA, while the read is performed without waiting for the interrupt.
Figure 12−45 shows the synchronization mechanism when SYNC = 1 0.
Figure 12−45. Mechanism for DMA Destination Synchronization
Start
DMA channel performs a read
Idle until enabled interrupt is received
Disable DMA interrupts globally
Clear corresponding IF bit
DMA channel performs a write
DMA interrupts are enabled globally
Go to start
Peripherals
12-67
DMA Controller
- Source and destination synchronization (SYNC = 1 1)
When SYNC = 1 1, the DMA is synchronized to both the source and
destination. A read is performed when an interrupt is received. Then, a
write is performed on the following interrupt. Figure 12−46 shows source
and destination synchronization when SYNC = 1 1.
Figure 12−46. Mechanism for DMA Source and Destination Synchronization
Start
Idle until enabled interrupt is received
Disable DMA interrupts globally
Clear corresponding IF bit
DMA channel performs a read
Enable DMA interrupts globally
Idle until enabled interrupt is received
Disable DMA interrupts globally
Clear corresponding IF bit
DMA channel performs a write
Enable DMA interrupts globally
Go to start
12.3.8 DMA Memory Transfer Timing
The ’C30 and ’C31/VC33 devices provide one DMA channel, while the ’C32
device provides two DMA channels. The maximum data transfer rate that the
’C3x DMA sustains is one word every two cycles. In the ’C32, the two DMA
channels transfer data in a sequential time-slice fashion, rather than simultaneously, because the two channels share one common set of busses.
12-68
DMA Controller
The data transfer rate for a DMA channel (assuming a single-channel access
with no conflicts between CPU or other DMA channels) is as follows:
- On-chip memory and peripheral
J
J
DMA read:
DMA write:
One cycle
One cycle
- External memory (STRB, STRB0, STRB1, MSTRB)
J
DMA read:
Two cycles (one cycle external read followed by one
cycle load of internal DMA register)
J
DMA write:
Two cycles (identical to CPU write)
- External memory (IOSTRB)
J
DMA read:
Three cycles (two-cycle external read followed by one
cycle load of internal DMA register)
J
DMA write:
Two cycles (identical to CPU write)
If the DMA started and is transferring data over either external bus, do not
modify the bus-control register associated with that bus. If you must modify the
bus-control register (see Chapter 9 or 10), stop the DMA, make the modification, and then restart the DMA. Failure to do this may produce an unexpected
zero-wait-state bus access.
DMA memory transfer timing can be very complicated, especially if bus resource
conflicts occur. However, some rules help you calculate the transfer timing for
certain DMA setups. For simplification, the following section focuses on a singlechannel DMA memory transfer timing with no conflict with the CPU or other
DMA channels. You can obtain the actual DMA transfer timing by combining the
calculations for single-channel DMA transfer timing with those for bus resource
conflict situations.
12.3.8.1
Single DMA Memory Transfer Timing
When the DMA memory transfer has no conflict with the CPU or any other
DMA channels, the number of cycles of a DMA transfer depends on whether
the source and destination location are designated as on-chip memory,
peripheral, or external ports. When the external port is used, the DMA transfer
speed is affected by two factors: the external bus wait state and the read/write
conflict (for example, if a write is followed by a read, the read takes one extra
half-cycle. See Figure 12−48 footnote on page 12-72). Figure 12−47 through
Figure 12−49 show the number of cycles a DMA transfer requires from different
sources to different destinations. Entries in the table represent the number of
cycles required to do the T transfers, assuming that there are no pipeline conflicts.
A timing diagram for the DMA transfers accompanies each figure.
Peripherals
12-69
Legend:
T
= Number of transfers
Cr = Source-read wait states
Cw = Destination-write wait states
R
= Single-cycle reads
Destination on chip
Source IOSTRB bus
Destination on chip
W
Rn
Wn
I
Source STRB, STRB0, STRB1, MSTRB bus
=
=
=
=
R1
R1
Cr
W1
2
3
R1
R1
R2
Cr
R1
I
W2
4
Single-cycle writes
Multicycle reads
Multicycle writes
Internal register cycle
R1
R1
Source on chip
Destination on chip
1
R1
Cycles (H1)
I
W1
R3
5
W1
R2
W3
6
Figure 12−47. DMA Timing When Destination is On Chip
7
R2
R2
R4
Cr
R2
R2
W4
8
9
R2
I
R5
Cr
R2
W2
W5
10
11
I
R3
R6
Cr
W2
R3
W6
12
13
R3
R3
R7
R3
I
W7
14
15
R3
Cr
W3
R8
R3
16
I
17
W3
18
(3 + Cr + 1) T
(2 + Cr +1) T
(1 + 1) T
Rate
DMA Controller
Peripherals
12-71
12-72
R1
Cr
R1
W1
R2
W1
W2
6
W
Rn
Wn
I
W1
R2
=
=
=
=
8
W1
Cr
R2
R2
I
R2
W3
10
Cr
W2
R3
R2
W3
R4
11
Single-cycle writes
Multicycle reads
Multicycle writes
Internal register cycle
W1 W1
Cw
R2
9
W2
Cw
W2
Cw
W1
W2
R3
7
† Write followed by read incurs in one extra half-cycle.
Legend:
T
= Number of transfers
Cr = Source-read wait states
Cw = Destination-write wait states
R
= Single-cycle reads
Destination
STRB bus
R1
I
5
W1
Cw
W1
4
I
R1
Cr
R1
W1
R2
3
(’C30 only)
Source
IOSTRB
R1
W1
2
W1
R1
R1
1
Destination
STRB,
STRB0,
STRB1
bus
Source
STRB,
STRB0,
STRB1
bus
Destination
STRB,
STRB0,
STRB1,
MSTRB
bus
Source
on chip
Cycles
(H1)
W2
R3
I
13
W3
Cr
R3
W2
W4
14
W2 W2
Cw
R3
W2
Cw
W3
12
I
16
W2
W3
R4
17
W4
W3
R4
Cw
W4
Cw
W2
W4
R5
15
R4
19
W3 W3
Cw
R4
Cr
...
...
18
(3 + Cr + 2 + Cw) + (2 + Cw + max[1, Cr − Cw + 1])
(T−1)
(3.5 + Cr + 2 + Cw) T + .5 (T − 1){
(2 + Cr + 2 + Cw) T + 0.5 (T − 1){
(1 + 2 + Cw) T
Rate
Figure 12−48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus
DMA Controller
1
Cr
Cw
I
W1
I
5
6
W1
W
Rn
Wn
I
Cr
=
=
=
=
8
I
10
W2
R2
11
W2
R3
R2
Single-cycle writes
Multicycle reads
Multicycle writes
Internal register cycle
W1
R2
9
W1
Cw
W1
Cw
W1
R2
W1
7
† Write followed by read incurs in one extra half-cycle.
Legend:
T
= Number of transfers
Cr = Source-read wait states
Cw = Destination-write wait states
R
= Single-cycle reads
Destination
MSTRB
bus
R1
4
R1
R2
R1
3
R1
(’C30 only)
Source
STRB bus
R1
2
R1
W1
R1
Destination
STRB0,
STRB1, or
MSTRB
bus
Source
IOSTRB
bus
Cycles
(H1)
Cr
W2
R3
Cw
W2
R3
13
R2
Cw
R2
12
I
I
14
W3
W2
15
W3
W2
16
W3
Cw
W3
18
W2
Cw
W2
17
(2 + Cr + 2 + Cw) + (2 + Cw + max[1, Cr − Cw + 1])
(T−1)
(3 + Cr + 2 + Cw) T + 0.5 (T − 1)†
Rate
Figure 12−48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued)
DMA Controller
Peripherals
12-73
12-74
R1
R1
R1
W1
2
Cr
Cr
R1
R1
W1
R2
3
W
Rn
Wn
I
I
I
=
=
=
=
5
W1
W1
W1
R2
W2
6
Cr
R2
W1
9
R2
I
W2
Cw
W1
Cw
W1
8
W2
Cw
W1
R2
W2
R3
7
Single-cycle writes
Multicycle reads
Multicycle writes
Internal register cycle
W1
W1
Cw
W1
4
† Write followed by read incurs in one extra cycle.
Legend:
T
= Number of transfers
Cr = Source-read wait states
Cw = Destination-write wait states
R
= Single-cycle reads
Destination IOSTRB
Source STRB0, STRB1,
MSTRB bus
Destination IOSTRB bus
(’C30 only)
Source STRB bus
R1
R1
Source on chip
Destination IOSTRB
1
Cycles (H1)
R2
W2
W3
10
Cr
R2
W2
R3
W3
R4
11
I
Cr
R3
W2
W2
Cw
W2
R3
13
W3
Cw
W3
12
Figure 12−49. DMA Timing When Destination is an IOSTRB Bus
W2
I
W4
14
16
W2
W3
17
W4
18
W3
Cw
W3
Cw
W4
Cw
W2
W3
W4
R5
15
(2 + Cr + 2 + Cw) T + (T−1){
(2 + Cr + 2 + Cw) + (2 + Cw +
max (1, Cr − Cw + 1)) (T − 1)
1 + (2 + Cw) T
Rate
DMA Controller
DMA Controller
12.3.9 DMA Initialization/Reconfiguration
You can control the DMA through memory-mapped registers located on the
dedicated peripheral bus. Following is the general procedure for initializing
and/or reconfiguring the DMA:
1) Halt the DMA by clearing the START bits of the DMA global-control register.
You can do this by writing a 0 to the DMA global-control register. The DMA
is halted on RESET.
2) Configure the DMA through the DMA global-control register (with
START = 00), as well as the DMA source, destination, and transfercounter registers, if necessary. Refer to Section 12.3.11 on page 12-76
for more information.
3) Start the DMA by setting the START bits of the DMA global-control register
as necessary.
12.3.10 Hints for DMA Programming
The following hints help you to improve your DMA programming and avoid unexpected results:
- Reset the DMA register before starting it. This clears any previously
latched interrupt that may no longer exist.
- In the event of a CPU-DMA access conflict, the CPU always prevails. Care-
fully allocate the different sections of the program in memory for faster
execution. If a CPU program access conflicts with a DMA access, enabling
the cache helps if the program is located in external memory. DMA on-chip
access happens during the H3 phase.
Note: Expansion and Peripheral Buses
The expansion and peripheral buses cannot be accessed simultaneously
because they are multiplexed into a common port (see Figure 2−1 on
page 2-3). This might increase CPU-DMA access conflicts.
- Ensure that each interrupt is received when you use interrupt synchroniza-
tion; otherwise, the DMA will never complete the block transfer.
- Use read/write synchronization when reading from or writing to serial ports
to guarantee data validity.
The following are indications that the DMA has finished a set of transfers:
- The DINT bit in the IF register is set to 1 (interrupt polling). This requires
that you set the TCINT bit in the DMA control register first. This interruptpolling method does not cause any additional CPU-DMA access conflict.
Peripherals
12-75
DMA Controller
- The transfer counter has a zero value. However, the transfer counter is
decremented after the DMA read operation finishes (not after the write
operation). Nevertheless, a transfer counter with a 0 value can be used as
an indication of a transfer completion.
- The STAT bits in the DMA channel-control register are set to 002. You can
poll the DMA channel-control register for this value. However, because the
DMA registers are memory-mapped into the peripheral bus address
space, this option can cause further CPU/DMA access conflicts.
12.3.11 DMA Programming Examples
Example 12−8, Example 12−9, and Example 12−10 illustrate initialization
procedures for the DMA.
When linking the examples, you should allocate section memory addresses
carefully to avoid CPU-DMA conflict. In the C3x, the CPU always prevails in
cases of conflict. In the event of a CPU program/DMA data conflict, cache
enabling helps if the .text section is in external memory. For example, when
linking the code in Example 12−8, Example 12−9, and Example 12−10, the
.text section can be allocated into RAM0, .data into RAM1, and .bss into
RAM1, where RAM0 corresponds to on-chip RAM block 0 and RAM1 corresponds to on-chip RAM block 1.
In Example 12−8, the DMA initializes a 128-element array to 0. The DMA
sends an interrupt to the CPU after the transfer is completed. This program assumes previous initialization of the CPU interrupt-vector table (specifically the
DMA-to-CPU interrupt). The program initializes the ST and IE registers for
interrupt processing.
12-76
DMA Controller
Example 12−8. Array Initialization With DMA
* TITLE: ARRAY INITIALIZATION WITH DMA
*
.GLOBAL START
.DATA
DMA
.WORD 808000H
; DMA GLOBAL-CONTROL REG ADDRESS
RESET
.WORD 0C40H
; DMA GLOBAL-CONTROL REG RESET VALUE
CONTROL .WORD 0C43H
; DMA GLOBAL-CONTROL REG INITIALIZATION
SOURCE .WORD ZERO
; DATA SOURCE ADDRESS
DESTIN .WORD _ARRAY
; DATA DESTINATION ADDRESS
COUNT
.WORD 128
; NUMBER OF WORDS TO TRANSFER
ZERO
.FLOAT 0.0
; ARRAY INITIALIZATION VALUE 0.0 = 0x80000000
.BSS _ARRAY,128
; DATA ARRAY LOCATED IN .BSS SECTION
.TEXT
START
LDP DMA
LDI @DMA,AR0
LDI @RESET,R0
STI R0,*AR0
LDI @SOURCE,R0
STI R0,*+AR0(4)
LDI @DESTIN,R0
STI R0,*+AR0(6)
LDI @COUNT,R0
STI R0,*+AR0(8)
OR 400H,IE
OR 2000H,ST
LDI @CONTROL,R0
STI R0,*AR0
BU $
.END
; LOAD DATA PAGE POINTER
; POINT TO DMA GLOBAL CONTROL REGISTER
; RESET DMA
; INITIALIZE DMA SOURCE-ADDRESS REGISTER
; INITIALIZE DMA DESTINATION-ADDRESS REGISTER
; INITIALIZE DMA TRANSFER COUNTER REGISTER
;
;
;
;
ENABLE INTERRUPT FROM DMA TO CPU
ENABLE CPU INTERRUPTS GLOBALLY
INITIALIZE DMA GLOBAL CONTROL REGISTER
START DMA TRANSFER
Example 12−9 sets up the DMA to transfer data (128 words) from the serial
port 0 input register to an array buffer with serial port receive interrupt (RINT0).
The DMA sends an interrupt to the CPU when the data transfer completes.
Serial port 0 is initialized to receive 32-bit data words with an internally generated
receive-bit clock and a bit-transfer rate of 8H1 cycles/bit.
This program assumes previous initialization of the CPU interrupt vector table
(specifically the DMA-to-CPU interrupt). The serial port interrupt directly affects
only the DMA; no CPU serial-port interrupt-vector setting is required.
Peripherals
12-77
DMA Controller
Example 12−9. DMA Transfer With Serial-Port Receive Interrupt
* TITLE DMA TRANSFER WITH SERIAL
*
.GLOBAL START
.DATA
DMA
.WORD 808000H
CONTROL
.WORD 0D43H
SOURCE
.WORD 80804CH
DESTIN
.WORD _ARRAY
COUNT
.WORD 128
IEVAL
.WORD 00200400H
RESET1
.WORD 0D40H
PORT RECEIVE INTERRUPT
; DMA GLOBAL-CONTROL REG ADDRESS
; DMA GLOBAL-CONTROL REG INITIALIZATION
; DATA SOURCE-ADDRESS: SERIAL PORT INPUT REG
; DATA DESTINATION ADDRESS
; NUMBER OF WORDS TO TRANSFER
; IE REGISTER VALUE
; DMA RESET
.BSS
_ARRAY,128
; DATA ARRAY LOCATED IN .BSS SECTION
; THE UNDERSCORE USED IS JUST TO MAKE IT
; ACCESSIBLE FROM C (OPTIONAL)
SPORT
SGCCTRL
SRCTRL
STCTRL
STPERIOD
SPRESET
RESET
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.TEXT
808040H
0A300080H
111H
3C0H
00020000H
01300080H
0H
;
;
;
;
;
START
LDP DMA
SERIAL-PORT GLOBAL-CONTROL REG ADDRESS
SERIAL-PORT GLOBAL-CONTROL REG INITIALIZATION
SERIAL-PORT RX PORT CONTROL REG INITIALIZATION
SERIAL-PORT TIMER-CONTROL REG INITIALIZATION
SERIAL-PORT TIMER PERIOD
; SERIAL-PORT RESET
; SERIAL-PORT TIMER RESET
; LOAD DATA PAGE POINTER
* DMA INITIALIZATION
LDI
LDI
LDI
STI
LDI
STI
LDI
STI
LDI
STI
LDI
STI
LDI
STI
OR
OR
LDI
STI
@DMA,AR0
@SPORT,AR1
@RESET,R0
R0,*+AR1(4)
@RESET1,R0
R0,*AR0
@SPRESET,R0
R0,*AR1
@SOURCE,R0
R0,*+AR0(4)
@DESTIN,R0
R0,*+AR0(6)
@COUNT,R0
R0,*+AR0(8)
@IEVAL,IE
2000H,ST
@CONTROL,R0
R0,*AR0
; POINT TO DMA GLOBAL CONTROL REGISTER
; RESET SPORT TIMER
; RESET DMA
; RESET SPORT
; INITIALIZE DMA SOURCE-ADDRESS REGISTER
; INITIALIZE DMA DESTINATION-ADDRESS REGISTER
; INITIALIZE DMA TRANSFER COUNTER REGISTER
;
;
;
;
ENABLE INTERRUPTS
ENABLE CPU INTERRUPTS GLOBALLY
INITIALIZE DMA GLOBAL CONTROL REGISTER
START DMA TRANSFER
* SERIAL PORT INITIALIZATION
LDI @SRCTRL,R0
STI R0,*+AR1(3)
LDI @STPERIOD,R0
STI R0,*+AR1(6)
LDI @STCTRL,R0
STI R0,*+AR1(4)
LDI @SGCCTRL,R0
STI R0,*AR1
BU $
.END
12-78
; SERIAL-PORT RECEIVE CONTROL REG INITIALIZATION
; SERIAL-PORT TIMER-PERIOD INITIALIZATION
; SERIAL-PORT TIMER CONTROL REG INITIALIZATION
; SERIAL-PORT GLOBAL CONTROL REG INITIALIZATION
DMA Controller
Example 12−10 sets up the DMA to transfer data (128 words) from an array
buffer to the serial port 0 output register with serial port transmit interrupt XINT0.
The DMA sends an interrupt to the CPU when the data transfer completes.
Serial port 0 is initialized to transmit 32-bit data words with an internally generated frame sync and a bit-transfer rate of 8(H1) cycles/bit. The receive-bit
clock is internally generated and equal in frequency to one-half of the ’C3x H1
frequency.
This program assumes previous initialization of the CPU interrupt-vector table
(specifically the DMA-to-CPU interrupt). The serial-port interrupt directly affects
only the DMA; no CPU serial-port interrupt-vector setting is required.
Note: Serial-Port Transmit Synchronization
The DMA uses serial-port transmit interrupt XINT0 to synchronize transfers.
Because the XINT0 is generated when the transmit buffer has written the last
bit of data to the shifter, an initial CPU write to the serial port is required to
trigger XINT0 to enable the first DMA transfer.
Example 12−10.
DMA Transfer With Serial-Port Transmit Interrupt
* TITLE: DMA TRANSFER WITH SERIAL PORT TRANSMIT INTERRUPT
*
.GLOBAL START
.DATA
DMA
.WORD 808000H
; DMA GLOBAL-CONTROL REG ADDRESS
CONTROL
.WORD 0E13H
; DMA GLOBAL-CONTROL REG INITIALIZATION
SOURCE
.WORD (_ARRAY+1)
; DATA SOURCE ADDRESS
DESTIN
.WORD 80804CH
; DATA DESTIN ADDRESS: SERIAL-PORT OUTPUT REG
COUNT
.WORD 127
; NUMBER OF WORDS TO TRANSFER =(MSG LENGHT−1)
IEVAL
.WORD 00100400H
; IE REGISTER VALUE
.BSS
_ARRAY,128
; DATA ARRAY LOCATED IN .BSS SECTION
; THE UNDERSCORE USED IS JUST TO MAKE IT
; ACCESSIBLE FROM C (OPTIONAL)
RESET1
.WORD 0E10H
; DMA RESET
SPORT
.WORD 808040H
; SERIAL-PORT GLOBAL−CONTROL REG ADDRESS
SGCCTRL
.WORD 048C0044H
; SERIAL-PORT GLOBAL-CONTROL REG INITIALIZATION
SXCTRL
.WORD 111H
; SERIAL-PORT TX PORT CONTROL REG INITIALIZATION
STCTRL
.WORD 00FH
; SERIAL-PORT TIMER CONTROL REG INITIALIZATION
STPERIOD .WORD 00000002H
; SERIAL-PORT TIMER PERIOD
SPRESET
.WORD 00880044H
; SERIAL-PORT RESET
RESET
.WORD 0H
; SERIAL-PORT TIMER RESET
.TEXT
START
LDP DMA
; LOAD DATA PAGE POINTER
Peripherals
12-79
DMA Controller
Example 12−10. DMA Transfer With Serial-Port Transmit Interrupt (Continued)
* DMA INITIALIZATION
LDI @DMA,AR0
LDI @SPORT,AR1
LDI @RESET,R0
STI R0,*+AR1(4)
STI R0,*AR0
STI R0,*AR1
LDI @SOURCE,R0
STI R0,*+AR0(4)
LDI @DESTIN,R0
STI R0,*+AR0(6)
LDI @COUNT,R0
STI R0,*+AR0(8)
OR @IEVAL,IE
OR 2000H,ST
LDI @CONTROL,R0
STI R0,*AR0
; POINT TO DMA GLOBAL CONTROL REGISTER
;
;
;
;
RESET SPORT TIMER
RESET DMA
RESET SPORT
INITIALIZE DMA SOURCE-ADDRESS REGISTER
; INITIALIZE DMA DESTINATION-ADDRESS REGISTER
; INITIALIZE DMA TRANSFER COUNTER REGISTER
;
;
;
;
ENABLE INTERRUPT FROM DMA TO CPU
ENABLE CPU INTERRUPTS GLOBALLY
INITIALIZE DMA GLOBAL CONTROL REGISTER
START DMA TRANSFER
* SERIAL PORT INITIALIZATION
LDI @SXCTRL,R0
STI R0,*+AR1(2)
LDI @STPERIOD,R0
STI R0,*+AR1(6)
LDI @STCTRL,R0
STI R0,*+AR1(4)
LDI @SGCCTRL,R0
STI R0,*AR1
; SERIAL-PORT TX CONTROL REG INITIALIZATION
; SERIAL−PORT TIMER-PERIOD INITIALIZATION
; SERIAL-PORT TIMER-CONTROL REG INITIALIZATION
; SERIAL-PORT GLOBAL-CONTROL REG INITIALIZATION
* CPU WRITES THE FIRST WORD (TRIGGERING EVENT −−−> XINT IS GENERATED)
LDI @SOURCE,AR0
LDI *−AR0(1),R0
STI R0,*+AR1(8)
BU $
.END
Other examples are as follows:
- Transfer a 256-word block of data from off-chip memory to on-chip
memory and generate an interrupt on completion. Maintain the memory
order.
DMA source address:
DMA destination address:
DMA transfer counter:
DMA global control:
CPU/DMA interrupt enable (IE):
12-80
800000h
809800h
00000100h
00000C53h
00000400h
DMA Controller
- Transfer a 128-word block of data from on-chip memory to off-chip
memory and generate an interrupt on completion. Invert the memory order; the highest addressed member of the block is to become the lowest
addressed member.
DMA source address:
DMA destination address:
DMA transfer counter:
DMA global control:
CPU/DMA interrupt-enable (IE):
809800h
800000h
00000080h
00000C93h
00000400h
- Transfer a 200-word block of data from the serial-port 0 receive register
to on-chip memory and generate an interrupt on completion. Synchronize
the transfer with the serial-port 0 receive interrupt.
DMA source address:
DMA destination address:
DMA transfer counter:
DMA global control:
CPU/DMA interrupt-enable (IE):
80804Ch
809C00h
000000C8h
00000D43h
00200400h
- Transfer a 200-word block of data from off-chip memory to the serial-port 0
transmit register and generate an interrupt on completion. Synchronize with
the serial-port 0 transmit interrupt.
DMA source address:
DMA destination address:
DMA transfer counter:
DMA global control:
CPU/DMA interrupt-enable (IE):
809C00h
808048h
000000C8h
00000E13h
00400400h
- Transfer data continuously between the serial-port 0 receive register and
the serial-port 0 transmit register to create a digital loop back. Synchronize
with the serial-port 0 receive and transmit interrupts.
DMA source address:
DMA destination address:
DMA transfer counter:
DMA global control:
CPU/DMA interrupt-enable (IE):
80804Ch
808048h
00000000h
00000303h
00300000h
Peripherals
12-81
12-82
Chapter 13
".
The ’C3x assembly language instruction set supports numeric-intensive, signalprocessing, and general-purpose applications. (The addressing modes used with
the instructions are described in Chapter 5.)
The ’C3x instruction set can also use one of 20 condition codes with any of the
10 conditional instructions, such as LDFcond. This chapter defines the condition
codes and flags.
The assembler allows optional syntax forms to simplify the assembly language
for special-case instructions. These optional forms are listed and explained.
Each of the individual instructions is described and listed in alphabetical order
(see subsection 13.6.2, Optional Assembler Syntax, on page 13-34). Example
instructions demonstrate the special format and explain its content.
This chapter discusses these topics:
Topic
Page
13.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.3 Parallel Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.4 Group Addressing Mode Instruction Encoding . . . . . . . . . . . . . . . . 13-20
13.5 Condition Codes and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.6 Individual Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13-1
mnemonic
Running Title—Attribute Reference
13.1 Instruction Set
The ’C3x instruction set is well suited to digital signal processing and other
numeric-intensive applications. All instructions are a single machine word
long, and most instructions require one cycle to execute. In addition to multiply
and accumulate instructions, the ’C3x possesses a full complement of generalpurpose instructions.
The instruction set contains 113 instructions organized into the following functional groups:
-
Load and store
2-operand arithmetic/logical
3-operand arithmetic/logical
Program control
Interlocked operations
Parallel operations
Each of these groups is discussed in the following subsections.
13.1.1 Load and Store Instructions
The ’C3x supports 13 load and store instructions (see Table 13−1). These
instructions can:
- Load a word from memory into a register
- Store a word from a register into memory
- Manipulate data on the system stack
Two of these instructions can load data conditionally. This is useful for locating
the maximum or minimum value in a data set. See Section 13.5 on page 13-28
for detailed information on condition codes.
Table 13−1. Load and Store Instructions
Instruction
Description
Instruction
Description
LDE
Load floating-point exponent
POP
Pop integer from stack
LDF
Load floating-point value
POPF
Pop floating-point value from stack
LDFcond
Load floating-point value
conditionally
PUSH
Push integer on stack
LDI
Load integer
PUSHF
Push floating-point value on stack
LDIcond
Load integer conditionally
STF
Store floating-point value
LDM
Load floating-point mantissa
STI
Store integer
LDP
Load data page pointer
13-2
Instruction Set
mnemonic
13.1.2 2-Operand Instructions
The ’C3x supports 35 2-operand arithmetic and logical instructions. The two
operands are the source and destination. The source operand can be a memory
word, a register, or a part of the instruction word. The destination operand is
always a register.
As shown in Table 13−2, these instructions provide integer, floating-point or
logical operations, and multiprecision arithmetic.
Table 13−2. 2-Operand Instructions
Instruction
Description
Instruction
Description
ABSF
Absolute value of a floatingpoint number
NORM
Normalize floating-point value
ABSI
Absolute value of an integer
NOT
Bitwise-logical complement
ADDC†
Add integers with carry
OR†
Bitwise-logical OR
ADDF†
Add floating-point values
RND
Round floating-point value
ADDI†
Add integers
ROL
Rotate left
AND†
Bitwise-logical AND
ROLC
Rotate left through carry
ANDN†
Bitwise-logical AND with
ROR
Rotate right
complement
ASH†
Arithmetic shift
RORC
Rotate right through carry
CMPF†
Compare floating-point values
SUBB†
Subtract integers with borrow
CMPI†
Compare integers
SUBC
Subtract integers conditionally
FIX
Convert floating-point value to
integer
SUBF†
Subtract floating-point values
FLOAT
Convert integer to floating-point
value
SUBI†
Subtract integer
LSH†
Logical shift
SUBRB
Subtract reverse integer with
borrow
MPYF†
Multiply floating-point values
SUBRF
Subtract reverse floating-point
value
MPYI†
Multiply integers
SUBRI
Subtract reverse integer
NEGB
Negate integer with borrow
TSTB†
Test bit fields
NEGF
Negate floating-point value
XOR†
Bitwise-exclusive OR
NEGI
Negate integer
† 2- and 3-operand versions
Assembly Language Instructions
13-3
mnemonic
Instruction Set
13.1.3 3-Operand Instructions
Whereas 2-operand instructions have a single source operand (or shift count)
and a destination operand, 3-operand instructions can have two source operands
(or one source operand and a count operand) and a destination operand. A source
operand can be a memory word or a register. The destination of a 3-operand
instruction is always a register.
Table 13−3 lists the instructions that have 3-operand versions. You can omit
the 3 in the mnemonic from 3-operand instructions (see subsection 13.6.2 on
page 13-34).
Table 13−3. 3-Operand Instructions
Instruction
Description
Instruction
Description
ADDC3
Add with carry
MPYF3
Multiply floating-point values
ADDF3
Add floating-point values
MPYI3
Multiply integers
ADDI3
Add integers
OR3
Bitwise-logical OR
AND3
Bitwise-logical AND
SUBB3
Subtract integers with borrow
ANDN3
Bitwise-logical AND with complement
SUBF3
Subtract floating-point values
ASH3
Arithmetic shift
SUBI3
Subtract integers
CMPF3
Compare floating-point values
TSTB3
Test bit fields
CMPI3
Compare integers
XOR3
Bitwise-exclusive OR
LSH3
Logical shift
13.1.4 Program-Control Instructions
The program-control instruction group consists of all of those instructions (17)
that affect program flow. The repeat mode allows repetition of a block of code
(RPTB) or of a single line of code (RPTS). Both standard and delayed
(single-cycle) branching are supported. Several program-control instructions
can perform conditional operations. (See Section 13.5 on page 13-28
for detailed information on condition codes.) Table 13−4 lists the programcontrol instructions.
13-4
Instruction Set
mnemonic
Table 13−4. Program-Control Instructions
Instruction
Description
Instruction
Description
Bcond
Branch conditionally (standard)
IDLE
Idle until interrupt
BcondD
Branch conditionally (delayed)
NOP
No operation
BR
Branch unconditionally (standard)
RETIcond
Return from interrupt conditionally
BRD
Branch unconditionally (delayed)
RETScond
Return from subroutine conditionally
CALL
Call subroutine
RPTB
Repeat block of instructions
CALLcond
Call subroutine conditionally
RPTS
Repeat single instruction
DBcond
Decrement and branch conditionally
(standard)
SWI
Software interrupt
DBcondD
Decrement and branch conditionally
(delayed)
TRAPcond
Trap conditionally
IACK
Interrupt acknowledge
13.1.5 Low-Power Control Instructions
The low-power control instruction group consists of three instructions that affect
the low-power modes. The low-power idle (IDLE2) instruction allows extremely
low-power mode. The divide-clock-by-16 (LOPOWER) instruction reduces the
rate of the input clock frequency. The restore-clock-to-regular-speed
(MAXSPEED) instruction causes the resumption of full-speed operation.
Table 13−5 lists the low-power control instructions.
Table 13−5. Low-Power Control Instructions
Instruction
Description
Instruction
Description
IDLE2
Low-power idle
MAXSPEED
Restore clock to regular speed
LOPOWER
Divide clock by 16
13.1.6 Interlocked-Operations Instructions
The five interlocked-operations instructions (Table 13−6) support multiprocessor communication and the use of external signals to allow for powerful
synchronization mechanisms. They also ensure the integrity of the communication and result in a high-speed operation. Refer to Chapter 7 for examples
of the use of interlocked instructions.
Assembly Language Instructions
13-5
mnemonic
Instruction Set
Table 13−6. Interlocked-Operations Instructions
Instruction
Description
Instruction
Description
LDFI
Load floating-point value, interlocked
STFI
Store floating-point value, interlocked
LDII
Load integer, interlocked
STII
Store integer, interlocked
SIGI
Signal, interlocked
13.1.7 Parallel-Operations Instructions
The 13 parallel-operations instructions make a high degree of parallelism
possible. Some of the ’C3x instructions can occur in pairs that are executed
in parallel. These instructions offer the following features:
- Parallel loading of registers
- Parallel arithmetic operations
- Arithmetic/logical instructions used in parallel with a store instruction
Each instruction in a pair is entered as a separate source statement. The second
instruction in the pair must be preceded by two vertical bars (||). Table 13−7 lists
the valid instruction pairs.
Table 13−7. Parallel Instructions
(a) Parallel arithmetic with store instructions
Mnemonic
13-6
Description
||
ABSF
STF
Absolute value of a floating-point number and store floatingpoint value
ABSI
STI
Absolute value of an integer and store integer
||
ADDF3
STF
Add floating-point values and store floating-point value
||
ADDI3
STI
Add integers and store integer
||
AND3
STI
Bitwise-logical AND and store integer
||
ASH3
STI
Arithmetic shift and store integer
||
FIX
STI
Convert floating-point to integer and store integer
||
Instruction Set
mnemonic
Table 13−7. Parallel Instructions (Continued)
(a) Parallel arithmetic with store instructions (Continued)
Mnemonic
Description
||
FLOAT
STF
Convert integer to floating-point value and store floatingpoint value
LDF
STF
Load floating-point value and store floating-point value
||
LDI
STI
Load integer and store integer
||
LSH3
STI
Logical shift and store integer
||
MPYF3
STF
Multiply floating-point values and store floating-point value
||
MPYI3
STI
Multiply integer and store integer
||
NEGF
STF
Negate floating-point value and store floating-point value
||
NEGI
STI
Negate integer and store integer
||
NOT
STI
Complement value and store integer
||
OR3
STI
Bitwise-logical OR value and store integer
||
STF
STF
Store floating-point values
||
STI
STI
Store integers
||
SUBF3
STF
Subtract floating-point value and store floating-point value
||
SUBI3
STI
Subtract integer and store integer
||
XOR3
STI
Bitwise-exclusive OR values and store integer
||
Assembly Language Instructions
13-7
mnemonic
Instruction Set
Table 13−7. Parallel Instructions (Continued)
(b) Parallel load instructions
Mnemonic
Description
LDF
LDF
Load floating-point value
||
LDI
LDI
Load integer
||
(c) Parallel multiply and add/subtract instructions
Mnemonic
Description
MPYF3
ADDF3
Multiply and add floating-point value
||
MPYF3
SUBF3
Multiply and subtract floating-point value
||
MPYI3
ADDI3
Multiply and add integer
||
MPYI3
SUBI3
Multiply and subtract integer
||
These parallel instructions have been enhanced on the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
These devices support greater combinations of operands by also allowing the
use of any CPU register whenever an indirect operand is required. The particular
instruction description details the operand combination.
To support these new modes, you need to invoke the TMS320 floating-point
code generation tools (version 5.0 or later) with the following switches:
- C Compiler
J
J
‘C31:
‘C32:
CL30
CL30
−v31
−v32
−gsrev6
−gsrev2
- Assembler
J
J
13-8
‘C31:
‘C32:
asm30
asm30
−v31
−v32
−msrev6
−msrev2
Running Title—Attribute Reference
mnemonic
13.1.8 Illegal Instructions
The ’C3x has no illegal instruction-detection mechanism. Fetching an illegal
(undefined) opcode can cause the execution of an undefined operation. Proper
use of the TI TMS320 floating-point software tools will not generate an illegal
opcode. Only the following conditions can cause the generation of an illegal
opcode:
- Misuse of the tools
- An error in the ROM code
- Defective RAM
Chapter Title—Attribute Reference
13-9
mnemonic
Instruction Set Summary
13.2 Instruction Set Summary
Table 13−8 lists the ’C3x instruction set in alphabetical order. Each table entry
provides the instruction mnemonic, description, and operation.
Table 13−8. Instruction Set Summary
Mnemonic
Description
Operation
ABSF
Absolute value of a floating-point number
|src| → Rn
ABSI
Absolute value of an integer
|src| → Dreg
ADDC
Add integers with carry
src + Dreg + C → Dreg
ADDC3
Add integers with carry (3-operand)
src1 + src2 + C → Dreg
ADDF
Add floating-point values
src + Rn → Rn
ADDF3
Add floating-point values (3-operand)
src1 + src2 → Rn
ADDI
Add integers
src + Dreg → Dreg
ADDI3
Add integers (3 operand)
src1 + src2 + → Dreg
AND
Bitwise-logical AND
Dreg AND src → Dreg
AND3
Bitwise-logical AND (3-operand)
src1 AND src2 → Dreg
ANDN
Bitwise-logical AND with complement
Dreg AND src → Dreg
ANDN3
Bitwise-logical ANDN (3-operand)
src1 AND src2 → Dreg
ASH
Arithmetic shift
If count ≥ 0:
(Shifted Dreg left by count) → Dreg
Else:
(Shifted Dreg right by |count|) → Dreg
ASH3
Arithmetic shift (3-operand)
If count ≥ 0:
(Shifted src left by count) → Dreg
Else:
(Shifted src right by |count|) → Dreg
Legend:
13-10
ARn
C
Csrc
count
cond
Daddr
Dreg
GIE
N
PC
RC
auxiliary register n (AR7−AR0)
carry bit
conditional-branch addressing modes
shift value (general addressing modes)
condition code
destination memory address
register address (any register)
global interrupt enable register
any trap vector 0−27
program counter
repeat counter register
RE
RM
Rn
RS
SP
Sreg
ST
src
src1
src2
TOS
repeat interrupt register
repeat mode bit
register address (R7−R0)
repeat start register
stack pointer
register address (any register)
status register
general addressing modes
3-operand addressing modes
3-operand addressing modes
top of stack
Instruction Set Summary
mnemonic
Table 13−8. Instruction Set Summary (Continued)
Mnemonic
Description
Operation
Bcond
Branch conditionally (standard)
If cond = true:
If Csrc is a register, Csrc → PC
If Csrc is a value, Csrc + PC → PC
Else, PC + 1 → PC
BcondD
Branch conditionally (delayed)
If cond = true:
If Csrc is a register, Csrc → PC
If Csrc is a value, Csrc + PC + 3 → PC
Else, PC + 1 → PC
BR
Branch unconditionally (standard)
Value → PC
BRD
Branch unconditionally (delayed)
Value → PC
CALL
Call subroutine
PC + 1 → TOS
Value → PC
CALLcond
Call subroutine conditionally
If cond = true:
PC + 1 → TOS
If Csrc is a register, Csrc → PC
If Csrc is a value, Csrc + PC → PC
Else, PC + 1 → PC
CMPF
Compare floating-point values
Set flags on Rn − src
CMPF3
Compare floating-point values
Set flags on src1 − src2
(3-operand)
CMPI
Compare integers
Set flags on Dreg − src
CMPI3
Compare integers (3-operand)
Set flags on src1 − src2
Legend:
ARn
C
Csrc
count
cond
Daddr
Dreg
GIE
N
PC
RC
auxiliary register n (AR7−AR0)
carry bit
conditional-branch addressing modes
shift value (general addressing modes)
condition code
destination memory address
register address (any register)
global interrupt enable register
any trap vector 0−27
program counter
repeat counter register
RE
RM
Rn
RS
SP
Sreg
ST
src
src1
src2
TOS
repeat interrupt register
repeat mode bit
register address (R7−R0)
repeat start register
stack pointer
register address (any register)
status register
general addressing modes
3-operand addressing modes
3-operand addressing modes
top of stack
Assembly Language Instructions
13-11
mnemonic
Instruction Set Summary
Table 13−8. Instruction Set Summary (Continued)
Mnemonic
Description
Operation
DBcond
Decrement and branch conditionally
ARn − 1 → ARn
(standard)
If cond = true and ARn ≥ 0:
If Csrc is a register, Csrc → PC
If Csrc is a value, Csrc + PC + 1 → PC
Else, PC + 1 → PC
DBcondD
Decrement and branch conditionally
(delayed)
ARn − 1 → ARn
If cond = true and ARn ≥ 0:
If Csrc is a register, Csrc → PC
If Csrc is a value, Csrc + PC + 3 → PC
Else, PC + 1 → PC
FIX
Convert floating-point value to integer
Fix (src) → Dreg
FLOAT
Convert integer to floating-point value
Float(src) → Rn
IACK
Interrupt acknowledge
Dummy read of src
IACK toggled low, then high
IDLE
Idle until interrupt
PC + 1 → PC
Idle until next interrupt
IDLE2
Low-power idle
Idle until next interrupt stopping internal clocks
LDE
Load floating-point exponent
src(exponent) → Rn(exponent)
LDF
Load floating-point value
src → Rn
LDFcond
Load floating-point value conditionally
If cond = true, src → Rn
Else, Rn is not changed
LDFI
Load floating-point value, interlocked
Signal interlocked operation src → Rn
LDI
Load integer
src → Dreg
Legend:
13-12
ARn
C
Csrc
count
cond
Daddr
Dreg
GIE
N
PC
RC
auxiliary register n (AR7−AR0)
carry bit
conditional-branch addressing modes
shift value (general addressing modes)
condition code
destination memory address
register address (any register)
global interrupt enable register
any trap vector 0−27
program counter
repeat counter register
RE
RM
Rn
RS
SP
Sreg
ST
src
src1
src2
TOS
repeat interrupt register
repeat mode bit
register address (R7−R0)
repeat start register
stack pointer
register address (any register)
status register
general addressing modes
3-operand addressing modes
3-operand addressing modes
top of stack
Instruction Set Summary
mnemonic
Table 13−8. Instruction Set Summary (Continued)
Mnemonic
Description
Operation
LDIcond
Load integer conditionally
If cond = true, src → Dreg
Else, Dreg is not changed
LDII
Load integer, interlocked
Signal interlocked operation src → Dreg
LDM
Load floating-point mantissa
src (mantissa) → Rn (mantissa)
LDP
Load data page pointer
src → data page pointer
LOPOWER
Divide clock by 16
H1/16 → H1
LSH
Logical shift
If count ≥ 0:
(Dreg left-shifted by count) → Dreg
Else:
(Dreg right-shifted by |count|) → Dreg
LSH3
Logical shift (3-operand)
If count ≥ 0:
(src left-shifted by count) → Dreg
Else:
(src right-shifted by |count|) → Dreg
MAXSPEED
Restore clock to regular speed
H1/16 → H1
MPYF
Multiply floating-point values
src × Rn → Rn
MPYF3
Multiply floating-point value (3-operand)
src1 × src2 → Rn
MPYI
Multiply integers
src × Dreg → Dreg
MPYI3
Multiply integers (3-operand)
src1 × src2 → Dreg
NEGB
Negate integer with borrow
0 − src − C → Dreg
NEGF
Negate floating-point value
0 − src → Rn
NEGI
Negate integer
0 − src → Dreg
Legend:
ARn
C
Csrc
count
cond
Daddr
Dreg
GIE
N
PC
RC
auxiliary register n (AR7−AR0)
carry bit
conditional-branch addressing modes
shift value (general addressing modes)
condition code
destination memory address
register address (any register)
global interrupt enable register
any trap vector 0−27
program counter
repeat counter register
RE
RM
Rn
RS
SP
Sreg
ST
src
src1
src2
TOS
repeat interrupt register
repeat mode bit
register address (R7−R0)
repeat start register
stack pointer
register address (any register)
status register
general addressing modes
3-operand addressing modes
3-operand addressing modes
top of stack
Assembly Language Instructions
13-13
mnemonic
Instruction Set Summary
Table 13−8. Instruction Set Summary (Continued)
Mnemonic
Description
Operation
NOP
No operation
Modify ARn if specified
NORM
Normalize floating-point value
Normalize (src) → Rn
NOT
Bitwise-logical complement
src → Dreg
OR
Bitwise-logical OR
Dreg OR src → Dreg
OR3
Bitwise-logical OR (3-operand)
src1 OR src2 → Dreg
POP
Pop integer from stack
*SP−− → Dreg
POPF
Pop floating-point value from stack
*SP−− → Rn
PUSH
Push integer on stack
Sreg → *++ SP
PUSHF
Push floating-point value on stack
Rn → *++ SP
RETIcond
Return from interrupt conditionally
If cond = true or missing:
*SP−− → PC
1 → ST (GIE)
Else, continue
RETScond
Return from subroutine conditionally
If cond = true or missing:
*SP−− → PC
Else, continue
RND
Round floating-point value
Round (src) → Rn
ROL
Rotate left
Dreg rotated left 1 bit → Dreg
ROLC
Rotate left through carry
Dreg rotated left 1 bit through carry → Dreg
ROR
Rotate right
Dreg rotated right 1 bit → Dreg
RORC
Rotate right through carry
Dreg rotated right 1 bit through carry → Dreg
Legend:
13-14
ARn
C
Csrc
count
cond
Daddr
Dreg
GIE
N
PC
RC
auxiliary register n (AR7−AR0)
carry bit
conditional-branch addressing modes
shift value (general addressing modes)
condition code
destination memory address
register address (any register)
global interrupt enable register
any trap vector 0−27
program counter
repeat counter register
RE
RM
Rn
RS
SP
Sreg
ST
src
src1
src2
TOS
repeat interrupt register
repeat mode bit
register address (R7−R0)
repeat start register
stack pointer
register address (any register)
status register
general addressing modes
3-operand addressing modes
3-operand addressing modes
top of stack
Instruction Set Summary
mnemonic
Table 13−8. Instruction Set Summary (Continued)
Mnemonic
Description
Operation
RPTB
Repeat block of instructions
src → RE
1 → ST (RM)
Next PC → RS
RPTS
Repeat single instruction
src → RC
1 → ST (RM)
Next PC → RS
Next PC → RE
SIGI
Signal, interlocked
Signal interlocked operation
Wait for interlock acknowledge
Clear interlock
STF
Store floating-point value
Rn → Daddr
STFI
Store floating-point value, interlocked
Rn → Daddr
Signal end of interlocked operation
STI
Store integer
Sreg → Daddr
STII
Store integer, interlocked
Sreg → Daddr
Signal end of interlocked operation
SUBB
Subtract integers with borrow
Dreg − src − C → Dreg
SUBB3
Subtract integers with borrow (3-operand)
src1 − src2 − C → Dreg
SUBC
Subtract integers conditionally
If Dreg − src ≥ 0:
[(Dreg − src) << 1] OR 1 → Dreg
Else, Dreg << 1 → Dreg
SUBF
Subtract floating-point values
Rn − src → Rn
SUBF3
Subtract floating-point values (3-operand)
src1 − src2 → Rn
Legend:
ARn
C
Csrc
count
cond
Daddr
Dreg
GIE
N
PC
RC
auxiliary register n (AR7−AR0)
carry bit
conditional-branch addressing modes
shift value (general addressing modes)
condition code
destination memory address
register address (any register)
global interrupt enable register
any trap vector 0−27
program counter
repeat counter register
RE
RM
Rn
RS
SP
Sreg
ST
src
src1
src2
TOS
repeat interrupt register
repeat mode bit
register address (R7−R0)
repeat start register
stack pointer
register address (any register)
status register
general addressing modes
3-operand addressing modes
3-operand addressing modes
top of stack
Assembly Language Instructions
13-15
mnemonic
Instruction Set Summary
Table 13−8. Instruction Set Summary (Continued)
Mnemonic
Description
Operation
SUBI
Subtract integers
Dreg − src → Dreg
SUBI3
Subtract integers (3-operand)
src1 − src2 → Dreg
SUBRB
Subtract reverse integer with borrow
src − Dreg − C → Dreg
SUBRF
Subtract reverse floating-point value
src − Rn → Rn
SUBRI
Subtract reverse integer
src − Dreg → Dreg
SWI
Software interrupt
Perform emulator interrupt sequence
TRAPcond
Trap conditionally
If cond = true or missing:
Next PC → * ++ SP
Trap vector N → PC
0 → ST (GIE)
Else, continue
TSTB
Test bit fields
Dreg AND src
TSTB3
Test bit fields (3-operand)
src1 AND src2
XOR
Bitwise-exclusive OR
Dreg XOR src → Dreg
XOR3
Bitwise-exclusive OR (3-operand)
src1 XOR src2 → Dreg
Legend:
13-16
ARn
C
Csrc
count
cond
Daddr
Dreg
GIE
N
PC
RC
auxiliary register n (AR7−AR0)
carry bit
conditional-branch addressing modes
shift value (general addressing modes)
condition code
destination memory address
register address (any register)
global interrupt enable register
any trap vector 0−27
program counter
repeat counter register
RE
RM
Rn
RS
SP
Sreg
ST
src
src1
src2
TOS
repeat interrupt register
repeat mode bit
register address (R7−R0)
repeat start register
stack pointer
register address (any register)
status register
general addressing modes
3-operand addressing modes
3-operand addressing modes
top of stack
Parallel Instruction Set Summary
mnemonic
13.3 Parallel Instruction Set Summary
Table 13−9 lists the ’C3x instruction set in alphabetical order. Each table
entry shows the instruction mnemonic, description, and operation. Refer to
Section 13.1 for a functional listing of the instructions and individual instruction descriptions.
Table 13−9. Parallel Instruction Set Summary
(a) Parallel arithmetic with store instructions
Mnemonic
ABSF
||
||
||
||
||
||
src3 → dst2
src1 + src2 → dst1
Add integer
||
STI
src3 → dst2
src1 AND src2 → dst1
Bitwise-logical AND
||
STI
ASH3
src3 → dst2
src1 + src2 → dst1
Add floating-point value
STF
AND3
src3 → dst2
|src2| → dst1
Absolute value of an integer
STI
ADDI3
||
|src2| → dst1
STF
ADDF3
||
Operation
Absolute value of a floating point
ABSI
||
Description
src3 → dst2
If count ≥ 0:
Arithmetic shift
(src2 << count) → dst1
STI
||
src3 → dst2
Else:
(src2 >> |count|) → dst1
||
FIX
||
||
count
register addr (R7−R0)
dst1
register addr (R7−R0)
dst2
indirect addr (disp = 0, 1, IR0, IR1)
op1, op2, op4, and op5
Any two of these operands must be
specified using register addr; the remaining
two must be specified using indirect.
op3
op6
src1
src2
src3
src3 → dst2
Float(src2) → dst1
Convert integer to floating-point value
STF
Legend:
Fix (src2) → dst1
||
STI
FLOAT
||
Convert floating-point value to integer
src3 → dst2
src3 → dst2
register addr (R0 or R1)
register addr (R2 or R3)
register addr (R7−R0)
indirect addr (disp = 0, 1, IR0, IR1)
register addr (R7−R0)
Architectural Overview
13-17
mnemonic
Parallel Instruction Set Summary
Table 13−9. Parallel Instruction Set Summary (Continued)
(a) Parallel arithmetic with store instructions (Continued)
Mnemonic
LDF
||
src2 → dst1
STF
||
src3 → dst2
src2 → dst1
Load integer
STI
||
LSH3
||
Operation
Load floating-point value
LDI
||
Description
src3 → dst2
If count ≥ 0:
Logical shift
src2 << count → dst1
STI
||
src3 → dst2
Else:
src2 >> |count| → dst1
||
MPYF3
||
||
||
||
||
||
13-18
src3 → dst2
src1 OR src2 → dst1
Bitwise-logical OR
||
src3 → dst2
src1 → dst1
Store floating-point value
||
src3 → dst2
src1 → dst1
Store integer
||
count
register addr (R7−R0)
dst1
register addr (R7−R0)
dst2
indirect addr (disp = 0, 1, IR0, IR1)
op1, op2, op4, and op5
Any two of these operands must be
specified using register addr; the remaining
two must be specified using indirect.
src3 → dst2
src1 → dst1
Complement
STI
Legend:
src3 → dst2
0 − src2 → dst1
Negate integer
STF
STI
||
||
STI
STF
src3 → dst2
0 − src2 → dst1
Negate floating-point value
STI
OR3
||
||
STI
NOT
src3 → dst2
src1 x src2 → dst1
Multiply integer
STF
NEGI
||
||
STI
NEGF
||
src1 x src2 → dst1
Multiply floating-point value
STF
MPYI3
src3 → dst2
op3
op6
src1
src2
src3
src3 → dst2
register addr (R0 or R1)
register addr (R2 or R3)
register addr (R7−R0)
indirect addr (disp = 0, 1, IR0, IR1)
register addr (R7−R0)
Parallel Instruction Set Summary
mnemonic
Table 13−9. Parallel Instruction Set Summary (Continued)
(a) Parallel arithmetic with store instructions (Continued)
Mnemonic
SUBF3
||
src1 − src2 → dst1
STF
||
src3 → dst2
src1 − src2 → dst1
Subtract integer
STI
||
XOR3
||
Operation
Subtract floating-point value
SUBI3
||
Description
src3 → dst2
src1 XOR src2 → dst1
Bitwise-exclusive OR
STI
||
src3 → dst2
(b) Parallel load instructions
Mnemonic
LDF
||
Operation
src2 → dst1
Load floating-point value
LDF
||
LDI
||
Description
src4 → dst2
src2 → dst1
Load integer
LDI
||
src4 → dst2
(c) Parallel multiply and add/subtract instructions
Mnemonic
MPYF3
||
||
||
||
op4 + op5 → op6
op1 x op2 → op3
Multiply and subtract integer
||
count
register addr (R7−R0)
dst1
register addr (R7−R0)
dst2
indirect addr (disp = 0, 1, IR0, IR1)
op1, op2, op4, and op5
Any two of these operands must be
specified using register addr; the remaining
two must be specified using indirect.
op4 − op5 → op6
op1 x op2 → op3
Multiply and add integer
SUBI3
Legend:
op4 + op5 → op6
op1 x op2 → op3
Multiply and subtract floating-point value
ADDI3
MPYI3
||
op1 x op2 → op3
Multiply and add floating-point value
SUBF3
MPYI3
||
Operation
ADDF3
MPYF3
||
Description
op3
op6
src1
src2
src3
op4 − op5 → op6
register addr (R0 or R1)
register addr (R2 or R3)
register addr (R7−R0)
indirect addr (disp = 0, 1, IR0, IR1)
register addr (R7−R0)
Assembly Language Instructions
13-19
mnemonic
Groups of Addressing Modes
13.4 Group Addressing Mode Instruction Encoding
The six addressing types (covered in Section 6.1, Addressing Types, on
page 6-2) form these four groups of addressing modes:
-
General addressing modes (G)
3-operand addressing modes (T)
Parallel addressing modes (P)
Conditional-branch addressing modes (B)
13.4.1 General Addressing Modes
Instructions that use the general addressing modes are general-purpose
instructions, such as ADDI, MPYF, and LSH. Such instructions usually have
this form:
dst operation src → dst
In the syntax, the destination operand is signified by dst and the source operand
by src; operation defines an operation to be performed on the operands using the
general addressing modes. Bits 31−29 are 0, indicating general addressing
mode instructions. Bits 22 and 21 specify the general addressing mode (G) field,
which defines how bits 15−0 are to be interpreted for addressing the src operand.
Options for bits 22 and 21 (G field) are as follows:
G
Mode
00
Register (all CPU registers unless specified otherwise)
01
Direct
10
Indirect
11
Immediate
If the src and dst fields contain register specifications, the value in these
fields contains the CPU register addresses as defined by Table 13−10. For
the general addressing modes, the following values of ARn are valid:
ARn, 0 ≤ n ≤ 7
13-20
Running Title—Attribute Reference
mnemonic
Figure 13−1 shows the encoding for the general addressing modes. The notation
modn indicates the modification field that goes with the ARn field. Refer to
Table 13−10 on page 13-22 for further information.
Figure 13−1. Encoding for General Addressing Modes
G
31
29
28
23
Destination
22
21
20
16
0
0
0
operation
0
0
dst
0
0
0
operation
0
1
dst
0
0
0
operation
1
0
dst
0
0
0
operation
1
1
dst
Source Operands
15
0
0
0
11
10
0 0
0
8
0 0
7
0
5
0
4
0
src
0
direct
modn
ARn
disp
immediate
Chapter Title—Attribute Reference
13-21
mnemonic
Types of Addressing
Table 13−10. Indirect Addressing
(a) Indirect addressing with displacement
Mod Field
Syntax
Operation
Description
00000
*+ARn(disp)
addr = ARn + disp
With predisplacement add
00001
*−ARn(disp)
addr = ARn − disp
With predisplacement subtract
00010
*++ARn(disp)
addr = ARn + disp
ARn = ARn + disp
With predisplacement add and modify
00011
*−−ARn(disp)
addr = ARn − disp
ARn = ARn − disp
With predisplacement subtract and modify
00100
*ARn++(disp)
addr = ARn
ARn = ARn + disp
With postdisplacement add and modify
00101
*ARn −−(disp)
addr = ARn
ARn = ARn − disp
With postdisplacement subtract and modify
00110
*ARn++(disp)%
addr = ARn
ARn = circ(ARn + disp)
With postdisplacement add and circular modify
00111
*ARn−−(disp)%
addr = ARn
ARn = circ(ARn − disp)
With postdisplacement subtract and circular modify
(b) Indirect addressing with index register IR0
Mod Field
Syntax
Operation
Description
01000
*+ARn(IR0)
addr = ARn + IR0
With preindex (IR0) add
01001
*−ARn(IR0)
addr = ARn − IR0
With preindex (IR0) subtract
01010
*++ARn(IR0)
addr = ARn + IR0
ARn = ARn + IR0
With preindex (IR0) add and modify
01011
* −−ARn(IR0)
addr = ARn − IR0
ARn = ARn − IR0
With preindex (IR0) subtract and modify
01100
*ARn++(IR0)
addr = ARn
ARn = ARn + IR0
With postindex (IR0) add and modify
01101
*ARn −−(IR0)
addr= ARn
ARn = ARn − IR0
With postindex (IR0) subtract and modify
01110
*ARn++(IR0)%
addr = ARn
ARn = circ(ARn + IR0)
With postindex (IR0) add and circular modify
01111
*ARn −−(IR0)%
addr = ARn
ARn = circ(ARn − IR0)
With postindex (IR0) subtract and circular modify
Legend:
13-22
addr
ARn
circ( )
disp
memory address
auxiliary registers AR0−AR7
address in circular addressing
displacement
++
−−
%
IRn
add and modify
subtract and modify
where circular addressing is performed
index register IR0 or IR1
Running Title—Attribute Reference
mnemonic
Table 13−10. Indirect Addressing (Continued)
(c) Indirect addressing with index register IR1
Mod Field
Syntax
Operation
Description
10000
*+ ARn(IR1)
addr = ARn + IR1
With preindex (IR1) add
10001
* −ARn(IR1)
addr = ARn − IR1
With preindex (IR1) subtract
10010
* ++ ARn(IR1)
addr = ARn + IR1
ARn = ARn + IR1
With preindex (IR1) add and modify
10011
* −−ARn(IR1)
addr = ARn − IR1
ARn = ARn − IR1
With preindex (IR1) subtract and modify
10100
* ARn ++ (IR1)
addr = ARn
ARn = ARn + IR1
With postindex (IR1) add and modify
10101
*ARn −−(IR1)
addr = ARn
ARn = ARn − IR1
With postindex (IR1) subtract and modify
10110
* ARn ++ (IR1)%
addr = ARn
ARn = circ(ARn + IR1)
With postindex (IR1) add and circular modify
10111
* ARn −−(IR1)%
addr = ARn
ARn = circ(ARn − IR1)
With postindex (IR1) subtract and circular modify
(d) Indirect addressing (special cases)
Mod Field
Syntax
Operation
Description
11000
*ARn
addr = ARn
Indirect
11001
*ARn ++ (IR0)B
addr = ARn
With postindex (IR0) add
ARn = B(ARn + IR0)
and bit-reversed modify
Legend:
addr
ARn
B
B()
memory address
auxiliary registers AR0−AR7
where bit-reversed addressing is performed
bit-reversed address
circ( )
++
%
IRn
−−
address in circular addressing
add and modify by one
where circular addressing is performed
index register IR0 or IR1
subtract and modify by one
Chapter Title—Attribute Reference
13-23
mnemonic
Groups of Addressing Modes
13.4.2 3-Operand Addressing Modes
Instructions that use the 3-operand addressing modes, such as ADDI3, LSH3,
CMPF3, or XOR3, usually have this form:
src1 operation src2 → dst
where the destination operand is signified by dst and the source operands by
src1 and src2; operation defines an operation to be performed.
Note:
The 3 can be omitted from a 3-operand instruction mnemonic.
Bits 31−29 are set to the value of 001, indicating 3-operand addressing
mode instructions. Bits 22 and 21 specify the 3-operand addressing mode
(T) field, which defines how bits 15−0 are to be interpreted for addressing
the SRC operands. Bits 15−8 define the SRC1 address; bits 7−0 define the
SRC2 address. Options for bits 22 and 21 (T) are as follows:
T
src1 addressing modes
src2 addressing modes
00
Register mode
(any CPU register)
Register mode
(any CPU register)
01
Indirect mode
(disp = 0, 1, IR0, IR1)
Register mode
(any CPU register)
10
Register mode
(any CPU register)
Indirect mode
(disp = 0, 1, IR0, IR1)
11
Indirect mode
(disp = 0, 1, IR0, IR1)
Indirect mode
(disp = 0, 1, IR0, IR1)
Figure 13−2 shows the encoding for 3-operand addressing. If the src1 and
src2 fields both modify the same auxiliary register, both addresses are correctly
generated. However, only the value created by the src1 field is saved in the
auxiliary register specified. The assembler issues a warning if you specify this
condition.
13-24
mnemonic
Groups of Addressing Modes
The following values of ARn and ARm are valid:
ARn,0 ≤ n ≤ 7
ARm,0 ≤ m ≤ 7
The notation modm or modn indicates the modification field that goes with the
ARm or ARn field, respectively. Refer to Table 13−10 on page 13-22 for further
information.
In indirect addressing of the 3-operand addressing mode, displacements (if used)
are allowed to be 0 or 1, and the index registers (IR0 and IR1) can be used. The
displacement of 1 is implied and is not explicitly coded in the instruction word.
Figure 13−2. Encoding for 3-Operand Addressing Modes
T
31
28
27
23
Destination
22
21
20
src1
16
0
0
1
operation
0
0
dst
0
0
1
operation
0
1
dst
0
0
1
operation
1
0
dst
0
0
1
operation
1
1
dst
15
0
13
src2
12
11
0 0
10
src1
modn
0
8
0 0
ARn
7
5
0
0 0
src2
0
0 0
src2
src1
modn
ARn
4
3
2
0
modn
ARn
modm
ARm
13.4.3 Parallel Addressing Modes
Instructions that use parallel addressing, indicated by || (two vertical bars), allow
the most parallelism possible. The destination operands are indicated as d1
and d2, signifying dst1 and dst2, respectively (see Figure 13−3). The source
operands, signified by src1 and src2, use the extended-precision registers.
Operation refers to the parallel operation to be performed.
Figure 13−3. Encoding for Parallel Addressing Modes
31 30
1
29
26
0 operation
25 24
23
22
P
d1
d2
21
19
src1
18
16
src2
15
11
modn
10
8
ARn
7
3
modm
2
0
ARm
The parallel addressing mode (P) field specifies how the operands are to be
used, that is, whether they are source or destination. The specific relationship between the P field and the operands is detailed in the description of the
individual parallel instructions. However, the operands are always encoded
in the same way. Bits 31 and 30 are set to the value of 10, indicating parallel
addressing mode instructions. Bits 25 and 24 specify the parallel addressing
mode (P) field, which defines how to interpret bits 21−0 for addressing the src
operands. Bits 21−19 define the src1 address, bits 18−16 define the src2
Addressing Modes
13-25
mnemonic
Groups of Addressing Modes
address, bits 15−8 the src3 address, and bits 7−0 the src 4 address. The
notations modn and modm indicate which modification field goes with which
ARn or ARm (auxiliary register) field, respectively. The following list describes
the parallel addressing operands:
src1 = Rn
src2 = Rn
d1
d2
P
src3
src4
0 ≤ n ≤ 7 (extended-precision registers R0 −R7)
0 ≤ n ≤ 7 (extended-precision registers R0−R7)
If 0, dst1 is R0. If 1, dst1 is R1.
If 0, dst2 is R2. If 1, dst2 is R3.
0≤P≤3
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
As in the 3-operand addressing mode, indirect addressing in the parallel
addressing mode allows for displacements of 0 or 1 and the use of the index
registers (IR0 and IR1). The displacement of 1 is implied and is not explicitly
coded in the instruction word.
In the encoding shown for this mode in Figure 13−3, if the src3 and src4 fields
use the same auxiliary register, both addresses are correctly generated, but
only the value created by the src3 field is saved in the auxiliary register specified.
The assembler issues a warning if you specify this condition.
The encoding of these parallel addressing modes has been extended in the
following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
These addressing mode extensions also allow the use of any CPU register whenever an indirect operand is required in src3 and/or src4 operand. Figure 13−4
shows the encoding for extended parallel addressing instructions.
Figure 13−4. Encoding for Extended Parallel Addressing Instructions
31 30
1
13-26
29
0
28
26
operation
25
24
P
23
22
d1
d2
21
19
src1
18
16
src2
15
1
13
1
1
12
src3
8
9
1
5
1
1
4
0
src4
Groups of Addressing Modes
mnemonic
13.4.4 Conditional-Branch Addressing Modes
Instructions using the conditional-branch addressing modes (Bcond, BcondD,
CALLcond, DBcond, and DBcondD) can perform a variety of conditional
operations. Bits 31−27 are set to the value of 01101, indicating conditional-branch
addressing mode instructions. Bit 26 is set to 0 or 1; 0 selects DBcond, 1 selects
Bcond. Selection of bit 25 determines the conditional-branch addressing mode
(B). If B = 0, register addressing is used; if B = 1, PC-relative addressing is used.
Bit 21 sets the type of branch: D = 0 for a standard branch or D = 1 for a delayed
branch. The condition field (cond) specifies the condition checked to determine
what action to take, that is, whether to branch (see Table 13−12 on page 13-30
for a list of condition codes). Figure 13−5 shows the encoding for conditionalbranch addressing.
Figure 13−5. Encoding for Conditional-Branch Addressing Modes
(a) DBcond (D)
31
26
25
24
22
21
20
16
0
1
1
0
1
1
B
ARn
D
cond
0
1
1
0
1
1
B
ARn
D
cond
26
25
24
15
5
4
0 0 0 0 0 0 0 0 0 0 0
0
src reg
immediate (PC relative)
(b) Bcond (D)
31
22
21
20
16
0
1
1
0
1
0
B
0 0
0
D
cond
0
1
1
0
1
0
B
0 0
0
D
cond
26
25
24
22
21
15
5
4
0 0 0 0 0 0 0 0 0 0 0
0
src reg
immediate (PC relative)
(c) CALLcond
31
20
16
0
1
1
1
0
0
B
0
0 0
0
cond
0
1
1
1
0
0
B
0
0 0
0
cond
15
5
0 0 0 0 0 0 0 0 0 0 0
4
0
src reg
immediate (PC relative)
Addressing Modes
13-27
mnemonic
Condition Codes and Flags
13.5 Condition Codes and Flags
The ’C3x provides 20 condition codes (00000−10100, excluding 01011) that
you can place in the cond field of any of the conditional instructions, such as
RETScond or LDFcond. The conditions include signed and unsigned comparisons, comparisons to 0, and comparisons based on the status of individual
condition flags. All conditional instructions can accept the suffix U to indicate
unconditional operation.
Seven condition flags provide information about properties of the result of
arithmetic and logical instructions. The condition flags are stored in the status
register (ST) and are affected by an instruction only when either of the following
two cases occurs:
- The destination register is one of the extended-precision registers
(R7−R0). (This allows for modification of the registers used for addressing
but does not affect the condition flags during computation.)
- The instruction is one of the compare instructions (CMPF, CMPF3, CMPI,
CMPI3, TSTB, or TSTB3). (This makes it possible to set the condition flags
according to the contents of any of the CPU registers.)
The condition flags are modified by most instructions when either of the preceding conditions is established and either of the following two cases occurs:
- A result is generated when the specified operation is performed to infinite
precision. This is appropriate for compare and test instructions that do not
store results in a register. It is also appropriate for arithmetic instructions
that produce underflow or overflow.
- The output is written to the destination register, as shown in Table 13−11.
This is appropriate for other instructions that modify the condition flags.
Table 13−11. Output Value Formats
Type of Operation
Output Format
Floating point
8-bit exponent, one sign bit, 31-bit fraction
Integer
32-bit integer
Logical
32-bit unsigned integer
Figure 13−6 shows the condition flags in the low-order bits of the status register.
Following the figure is a list of status register condition flags with a description
of how the flags are set by most instructions. For specific details of the effect of
a particular instruction on the condition flags, see the description of that instruction in Section 13.6, Individual Instruction Descriptions, on page 13-32.
13-28
Running Title—Attribute Reference
mnemonic
Figure 13−6. Status Register
13
16
xx
Note:
15
14
13 12 11 10 9
8
7
6
5
4
3
2
0
1
PRGW
INT
GIE CC CE CF xx RM OVM LUF LV UF N
Z
V
C
status
config
(’C32 only) (’C32 only)
R
R/W
R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W
xx = reserved bit, read as 0
R = read, W = write
LUF
Latched floating-point underflow condition flag. LUF is set whenever UF
(floating-point underflow flag) is set. LUF can be cleared only by a processor
reset or by modifying it in the status register (ST).
LV
Latched overflow conditionfFlag. LV is set whenever V (overflow condition
flag) is set. Otherwise, it is unchanged. LV can be cleared only by a processor
reset or by modifying it in the status register (ST).
UF
Floating-point underflow conditionflag. A floating-point underflow occurs
whenever the exponent of the result is less than or equal to −128. If a floatingpoint underflow occurs, UF is set, and the output value is set to 0. UF is
cleared if a floating-point underflow does not occur.
N
Negative condition flag. Logical operations assign N the state of the MSB
of the output value. For logical operations, V is set to the state of the MSB.
For integer and floating-point operations, N is set if the result is negative and
cleared otherwise. A 0 is positive.
Z
Zero condition flag. For logical, integer, and floating-point operations, Z is
set if the output is 0 and cleared otherwise.
V
Overflow condition flag. For integer operations, V is set if the result does
not fit into the format specified for the destination (that is, −2 32 ≤ result ≤ 2
32 − 1). Otherwise, V is cleared. For floating-point operations, V is set if the
exponent of the result is greater than 127; otherwise,V is cleared. Logical
operations always clear V.
C
Carry flag. When an integer addition is performed, C is set if a carry occurs
out of the bit corresponding to the MSB of the output. When an integer
subtraction is performed, C is set if a borrow occurs into the bit corresponding
to the MSB of the output. Otherwise, for integer operations, C is cleared. The
carry flag is unaffected by floating-point and logical operations. For shift
instructions, this flag is set to the last bit shifted out; for a 0 shift count, this
is set to 0.
Chapter Title—Attribute Reference
13-29
mnemonic
Condition Codes and Flags
Table 13−12 lists the condition mnemonic, code, description, and flag for each
of the 20 condition codes.
Table 13−12. Condition Codes and Flags
(a) Unconditional compares
Condition
Code
Description
Flag†
U
00000
Unconditional
Irrevelant
(b) Unsigned compares
Condition
Code
Description
Flag†
LO
LS
HI
HS
EQ
NE
00001
00010
00011
00100
00101
00110
Lower than
Lower than or same as
Higher than
Higher than or same as
Equal to
Not equal to
C
C OR Z
∼C AND ∼Z
∼C
Z
∼Z
(c) Signed compares
Condition
Code
Description
Flag†
LT
LE
GT
GE
EQ
NE
00111
01000
01001
01010
00101
00110
Less than
Less than or equal to
Greater than
Greater than or equal to
Equal to
Not equal to
N
N OR Z
∼N AND ∼Z
∼N
Z
∼Z
† ∼ = logical complement (not true condition)
13-30
Running Title—Attribute Reference
mnemonic
Table 13−12. Condition Codes and Flags (Continued)
(d) Compare to zero
Condition
Code
Description
Flag†
Z
NZ
P
N
NN
00101
00110
01001
00111
01010
Zero
Not zero
Positive
Negative
Non-negative
Z
∼Z
∼N AND ∼Z
N
∼N
(e) Compare to condition flags
Condition
Code
Description
Flag†
NN
N
NZ
Z
NV
V
NUF
UF
NC
C
NLV
LV
NLUF
LUF
ZUF
01010
00111
00110
00101
01100
01101
01110
01111
00100
00001
10000
10001
10010
10011
10100
Non-negative
Negative
Nonzero
Zero
No overflow
Overflow
No underflow
Underflow
No carry
Carry
No latched overflow
Latched overflow
No latched floating-point underflow
Latched floating-point underflow
Zero or floating-point underflow
∼N
N
∼Z
Z
∼V
V
∼UF
UF
∼C
C
∼LV
LV
∼LUF
LUF
Z OR UF
† ∼ = logical complement (not true condition)
Chapter Title—Attribute Reference
13-31
mnemonic
Individual Instructions
13.6 Individual Instructions
This section contains the individual assembly language instructions for the ’C3x.
The instructions are listed in alphabetical order. Information for each instruction
includes assembler syntax, operation, operands, encoding, description, cycles,
status bits, mode bit, and examples.
Definitions of the symbols and abbreviations, as well as optional syntax forms
allowed by the assembler, precede the individual instruction description section.
Also, an example instruction shows the special format used and explains its
content.
A functional grouping of the instructions, as well as a complete instruction set
summary, can be found in Section 13.1 on page 13-2. Appendix A lists the
opcodes for all of the instructions. Refer to Chapter 6 for information on
memory addressing. Code examples using many of the instructions are
provided in Chapter 1, Software Applications, of the TMS320C3x GeneralPurpose Applications User’s Guide.
13.6.1 Symbols and Abbreviations
Table 13−13 lists the symbols and abbreviations used in the individual instruction descriptions.
13-32
Individual Instructions
mnemonic
Table 13−13. Instruction Symbols
Symbol
Meaning
src
src1
src2
src3
src4
Source operand
Source operand 1
Source operand 2
Source operand 3
Source operand 4
dst
dst1
dst2
disp
cond
count
Destination operand
Destination operand 1
Destination operand 2
Displacement
Condition
Shift count
G
T
P
B
General addressing modes
3-operand addressing modes
Parallel addressing modes
Conditional-branch addressing modes
|x|
x→y
x(man)
x(exp)
Absolute value of x
Assign the value of x to destination y
Mantissa field (sign + fraction) of x
Exponent field of x
op1
|| op2
Operation 1 performed in parallel with operation 2
x AND y
x OR y
x XOR y
∼x
Bitwise-logical AND of x and y
Bitwise-logical OR of x and y
Bitwise-logical XOR of x and y
Bitwise-logical complement of x
x << y
x >> y
*++SP
*SP− −
Shift x to the left y bits
Shift x to the right y bits
Increment SP and use incremented SP as address
Use SP as address and decrement SP
ARn
IRn
Rn
RC
RE
RS
ST
Auxiliary register n
Index register n
Register address n
Repeat count register
Repeat end address register
Repeat start address register
Status register
Assembly Language Instructions
13-33
mnemonic
Individual Instructions
C
GIE
N
PC
RM
SP
Carry bit
Global interrupt enable bit
Trap vector
Program counter
Repeat mode flag
System stack pointer
13.6.2 Optional Assembler Syntax
The assembler allows a relaxed syntax form for some instructions. These
optional forms simplify the assembly language so that special-case syntax
can be ignored. A list of the optional syntax forms follows.
- You can omit the destination register on unary arithmetic and logical oper-
ations when the same register is used as a source. For example,
ABSI
R0,R0
can be written as
ABSI R0
Instructions affected: ABSI, ABSF, FIX, FLOAT, NEGB, NEGF, NEGI,
NORM, NOT, RND
- You can write all 3-operand instructions without the 3. For example,
ADDI3 R0,R1,R2
can be written as
ADDI R0,R1,R2
Instructions affected: ADDC3, ADDF3, ADDI3, AND3, ANDN3, ASH3,
LSH3, MPYF3, MPYI3, OR3, SUBB3, SUBF3, SUBI3, XOR3
This also applies to all of the pertinent parallel instructions.
- You can write all 3-operand comparison instructions without the 3. For
example,
CMPI3 R0,*AR0
can be written as
CMPI R0,*AR0
Instructions affected: CMPI3, CMPF3, TSTB3
- Indirect operands with an explicit 0 displacement are allowed. In 3-operand
or parallel instructions, operands with 0 displacement are automatically
converted to no-displacement mode. For example:
LDI
*+AR0(0),R1
is legal.
Also
ADDI3 *+AR0(0),R1,R2 is equivalent to ADDI3 *AR0,R1,R2
- You can write indirect operands with no displacement, in which case a
displacement of 1 is assumed. For example,
LDI *AR0++(1),R0
13-34
can be written as
LDI *AR0++,R0
mnemonic
Individual Instructions
- All conditional instructions accept the suffix U to indicate unconditional
operation. Also, you can omit the U from unconditional short branch
instructions. For example:
can be written as
BU label
B label
- You can write labels with or without a trailing colon. For example:
label0:
label1
label2:
NOP
NOP
label assembles to next source line
- Empty expressions are not allowed for the displacement in indirect mode:
LDI
is not legal.
*+AR0(),R0
- You can precede long immediate mode operands (destination of BR and
CALL) with an @ sign:
can be written as
BR label
BR @label
- You can use the LDP pseudo-op to load a register (usually DP) with the
eight most significant bits (MSBs) of a relocatable address:
LDP
or
addr,REG
LDP @addr,REG
The @ sign is optional.
If the destination register is the DP, you can omit the DP in the operand. LDP
generates an LDI instruction with an immediate operand and a special relocation type.
- You can write parallel instructions in either order. For example:
ADDI
|| STI
can be written as
STI
|| ADDI
- You can write the parallel bars indicating part 2 of a parallel instruction
anywhere on the line from column 0 to the mnemonic. For example:
ADDI
|| STI
can be written as
ADDI
|| STI
- If the second operand of a parallel instruction is the same as the third (desti-
nation register) operand, you can omit the third operand. This allows you to
write 3-operand parallel instructions that look like normal 2-operand instructions. For example,
ADDI *AR0,R2,R2
|| MPYI *AR1,R0,R0
can be written as
ADD *AR0,R2
|| MPYI *AR1,R0
Instructions affected (applies to all parallel instructions that have a register
second operand): ADDI, ADDF, AND, MPYI, MPYF, OR, SUBI, SUBF,
XOR.
Assembly Language Instructions
13-35
mnemonic
Individual Instructions
- You can write all commutative operations in parallel instructions in either
order. For example, you can write the ADDI part of a parallel instruction in
either of two ways:
ADDI
*AR0,R1,R2
or
ADDI R1,*AR0,R2
Instructions affected include: parallel instructions containing any of the
following: ADDI, ADDF, MPYI, MPYF, AND, OR, XOR.
- Use the syntax in Table 13−14 to designate CPU registers in operands.
Note the alternate notation Rn, 0 n 27, which is used to designate
any CPU register.
13-36
Running Title—Attribute Reference
mnemonic
Table 13−14. CPU Register Syntax
Assemblers
Syntax
Alternate
Register Syntax
Assigned Function
R0
R0
Extended-precision register
R1
R1
Extended-precision register
R2
R2
Extended-precision register
R3
R3
Extended-precision register
R4
R4
Extended-precision register
R5
R5
Extended-precision register
R6
R6
Extended-precision register
R7
R7
Extended-precision register
AR0
R8
Auxiliary register
AR1
R9
Auxiliary register
AR2
R10
Auxiliary register
AR3
R11
Auxiliary register
AR4
R12
Auxiliary register
AR5
R13
Auxiliary register
AR6
R14
Auxiliary register
AR7
R15
Auxiliary register
DP
R16
Data-page pointer
IR0
R17
Index register 0
IR1
R18
Index register 1
BK
R19
Block-size register
SP
R20
Active stack pointer
ST
R21
Status register
IE
R22
CPU/DMA interrupt enable
IF
R23
CPU interrupt flags
IOF
R24
I/O flags
RS
R25
Repeat start address
RE
R26
Repeat end address
RC
R27
Repeat counter
Chapter Title—Attribute Reference
13-37
mnemonic
Individual Instructions
13.6.3 Individual Instruction Descriptions
Each assembly language instruction for the ’C3x is described in this section
in alphabetical order. The description includes the assembler syntax, operation,
operands, encoding, description, cycles, status bits, mode bit, and examples.
13-38
Example Instruction
Syntax
EXAMPLE
INST src, dst
or
INST1 src2, dst1
|| INST2 src3, dst2
Each instruction begins with an assembler syntax expression. You can place
labels either before the command (instruction mnemonic) on the same line or
on the preceding line in the first column. The optional comment field that concludes the syntax is not included in the syntax expression. Space(s) are
required between each field (label, command, operand, and comment fields).
The syntax examples illustrate the common one-line syntax and the two-line
syntax used in parallel addressing. Note that the two vertical bars || that indicate
a parallel addressing pair can be placed anywhere before the mnemonic on the
second line. The first instruction in the pair can have a label, but the second
instruction cannot have a label.
Operation
|src | → dst
or
|src2 | → dst1
|| src3 → dst2
The instruction operation sequence describes the processing that occurs when
the instruction is executed. For parallel instructions, the operation sequence is
performed in parallel. Conditional effects of status-register-specified modes are
listed for such conditional instructions as Bcond.
Operands
src general-addressing modes (G):
00
01
10
11
dst
register (Rn, 0 ≤ n ≤ 27)
direct
indirect
immediate
register (Rn, 0 ≤ n ≤ 27)
or
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Operands are defined according to the addressing mode and/or the type
of addressing used. Note that indirect addressing uses displacements and
the index registers. See Chapter 6 for detailed information on addressing.
Assembly Language Instructions
13-39
EXAMPLE Example Instruction
Opcode
31
0 0 0
24 23
INST
16 15
8 7
dst
G
0
src
or
31
24 23
1 1 INST1INST2
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
Encoding examples are shown using general addressing and parallel addressing.
The instruction pair for the parallel addressing example consists of INST1 and
INST2.
Description
Instruction execution and its effect on the rest of the processor or memory contents is described. Any constraints on the operands imposed by the processor
or the assembler are discussed. The description parallels and supplements
the information given by the operation block.
Cycles
1
The digit specifies the number of cycles required to execute the instruction.
Status Bits
LUF
Latched floating-point underflow condition flag. 1 if a
floating-point underflow occurs; unchanged otherwise.
LV
Latched overflow condition flag. 1 if an integer or floating-point
overflow occurs; unchanged otherwise.
UF
Floating-point underflow condition flag. 1 if a floating-point underflow
occurs; 0 otherwise.
N
Negative condition flag. 1 if a negative result is generated; 0 otherwise. In some instructions, this flag is the MSB of the output.
Z
Zero condition flag. 1 if a 0 result is generated; 0 otherwise. For logical
and shift instructions, 1 if a 0 output is generated; 0 otherwise.
V
Overflow condition flag. 1 if an integer or floating-point overflow
occurs; 0 otherwise.
C
Carry flag. 1 if a carry or borrow occurs; 0 otherwise. For shift instructions, this flag is set to the value of the last bit shifted out; 0 for a shift
count of 0.
The seven condition flags stored in the status register (ST) are modified by the
majority of instructions only if the destination register is R7−R0. The flags provide information about the properties of the result or the output of arithmetic
or logical operations.
Mode Bit
13-40
OVM Overflow mode flag. In general, integer operations are affected by the
OVM bit value (described in Table 3−2 on page 3-6).
Example Instruction
Example
EXAMPLE
INST @98AEh,R5
Before Instruction
After Instruction
R5
07 6690 0000
R5
00 6690 1000
R5 decimal
2.30562500e+02
R5 decimal
1.80126953e+00
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UV
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8098AEh
5CDF
8098AEh
5CDF
0200h
1234
0200h
1234
Data memory
The sample code presented in the above format shows the effect of the code on
system pointers (for example, DP or SP), registers (for example, R1 or R5),
memory at specific locations, and the seven status bits. The values given for the
registers include the leading 0s to show the exponent in floating-point operations.
Decimal conversions are provided for all register and memory locations. The
seven status bits are listed in the order in which they appear in the assembler and
simulator (see Section 13.5 on page 13-28 and Table 13−12 on page 13-30 for
further information on these seven status bits).
Assembly Language Instructions
13-41
ABSF Absolute Value of Floating Point
Syntax
ABSF src, dst
Operation
|src| → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 7)
dst
Opcode
31
24 23
0 0 0 0 0 0 0 0 0
Description
16 15
G
8 7
dst
0
src
The absolute value of the src operand is loaded into the dst register. The src
and dst operands are assumed to be floating-point numbers.
An overflow occurs if src (man) = 80000000h and src (exp) = 7Fh. The result
is dst (man) = 7FFFFFFFh and dst (exp) = 7Fh.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7− R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if a floating-point overflow occurs; unchanged otherwise
0
0
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
ABSF
R4,R7
Before Instruction
13-42
After Instruction
R4
5C 8000 F971 −9.90337307e+27
R4
5C 8000 F971 −9.90337307e+27
R7
7D 2511 00AE 5.48527255e+37
R7
5C 7FFF 068F
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
9.90337307e+27
Parallel ABSF and STF
Syntax
||
ABSF src2, dst1
STF
src3, dst2
||
|src2 | → dst1
src3 → dst2
Operation
Operands
src2
dst1
src3
dst2
ABSF||STF
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 0 0 1 0 0
Description
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
A floating-point absolute value and a floating-point store are performed in parallel. All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (STF) reads from a register and the operation being performed in parallel (ABSF) writes to the same register, STF accepts
the contents of the register as input before it is modified by the ABSF.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
If src3 and dst1 point to the same register, src3 is read before the write to dst1.
An overflow occurs if src (man) = 80000000h and src (exp) = 7Fh. The result
is dst (man) = 7FFFFFFFh and dst (exp) = 7Fh.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
1 if a floating-point overflow occurs; unchanged otherwise
0
0
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
Assembly Language Instructions
13-43
ABSF||STF Parallel ABSF and STF
Mode Bit
OVM
Example
Operation is not affected by OVM bit value.
ABSF
STF

*++AR3(IR1) ,R4
R4,*− AR7(1)
Before Instruction
R4
07 33C0 0000 1.79750e+02
After Instruction
R4
05 74C0 0000
AR3
80 9800
AR3
8098AF
AR7
80 98C5
AR7
8098C5
IR1
0AF
IR1
0AF
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
6.118750e+01
Data Memory
8098AF
8098C4
58B4000 −6.118750e+01 ?$8
0
8098C4
58B4000 −6.118750e+01
733C000
1.79750e+02
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-44
Absolute Value of Integer
Syntax
ABSI src, dst
Operation
|src| → dst
Operands
src general addressing modes (G):
00
01
10
11
ABSI
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst any CPU register
Opcode
31
24 23
0 0 0 0 0 0 0 0 1
Description
16 15
G
dst
8 7
0
src
The absolute value of the src operand is loaded into the dst register. The src
and dst operands are assumed to be signed integers.
An overflow occurs if src = 80000000h. If ST(OVM) = 1, the result is
dst = 7FFFFFFFh. If ST(OVM) = 0, the result is dst = 80000000h.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7− R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
0
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-45
ABSI Absolute Value of Integer
Example 1
ABSI
or
ABSI
R0,R0
R0
Before Instruction
R0
Example 2
ABSI
00 FFFF FFCB
After Instruction
−53
R0
00 0000 0035
53
*AR1,R3
Before Instruction
After Instruction
R3
00 0000 0000
R3
00 0000 0035
AR1
00 0020
AR1
00 0020
20
0FFFFFFCB
53
Data memory
20
13-46
0FFFFFFCB −53
−53
Parallel ABSI and STI
Syntax
ABSI
|| STI
Operation
||
Operands
ABSI||STI
src2, dst1
src3, dst2
|src2 | → dst1
src3 → dst2
src2
dst1
src3
dst2
indirect
register
register
indirect
(disp = 0, 1, IR0, IR1)
(Rn1, 0 ≤ 1 ≤ 7)
(Rn2, 0 ≤ n2 ≤ 7)
(disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1 0 0 1 0 1
Description
24 23
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
An integer absolute value and an integer store are performed in parallel. All
registers are read at the beginning and loaded at the end of the execute cycle.
If one of the parallel operations (STI) reads from a register and the operation
being performed in parallel (ABSI) writes to the same register, STI accepts the
contents of the register as input before it is modified by the ABSI.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
An overflow occurs if src = 80000000h. If ST(OVM) = 1, the result is dst =
7FFFFFFFh. If ST(OVM) = 0, the result is dst = 80000000h.
Cycles
1
Assembly Language Instructions
13-47
ABSI||STI Parallel ABSI and STI
Status Bits
Mode Bit
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
0
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Example
||
ABSI
STI
*−AR5(1),R5
R1,*AR2−−(IR1)
Before Instruction
R1
00 0000 0042
After Instruction
66
R1
00 0000 0042
66
53
R5
00 0000 0000
R5
00 0000 0035
AR2
80 98FF
AR2
80 98F0
AR5
80 99E2
AR5
80 99E2
IR1
0F
IR1
0F
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
8098FF
8099E1
2 −53
0FFFFFFCB
2
8098FF
8099E1
42 −53
0FFFFFFCB
66
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-48
Add Integer With Carry
Syntax
ADDC
Operation
dst + src + C → dst
Operands
src general addressing modes (G):
ADDC
src, dst
00
01
10
11
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst any CPU register
Opcode
31
2423
0 1 0
0 0 0 0 0
1615
G
8 7
dst
0
src
Description
The sum of the dst and src operands and the carry (C) flag is loaded into the
dst register. The dst and src operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a carry occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
ADDC
R1,R5
Before Instruction
After Instruction
R1
00 FFFF 5C25
−41,947
R1
00 FFFF 5C25
−41,947
R5
00 FFFF 019E
−65,122
R5
00 FFFE 5DC4
−107,068
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Assembly Language Instructions
13-49
ADDC3 Add Integer With Carry, 3-Operand
Syntax
ADDC3
Operation
src1 + src2 + C → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
src2, src1, dst
any CPU register
indirect (disp = 0, 1, IR0, IR1)
any CPU register
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
any CPU register
any CPU register
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
dst any CPU register
Opcode
31
24 23
0 0 1 0 0 0 0 0 0
16 15
T
dst
8 7
src1
0
src2
Description
The sum of the src1 and src2 operands and the carry (C) flag is loaded into
the dst register. The src1, src2, and dst operands are assumed to be signed
integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-50
LUF
LV
U
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a carry occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Add Integer With Carry, 3-Operand
Example 1
ADDC3
or
ADDC3
ADDC3
*AR5++(IR0),R5,R2
R5,*AR5++(IR0),R2
Before Instruction
After Instruction
R2
00 0000 0000
R2
00 0000 0032
50
R5
00 0000 0066 102
R5
00 0000 0066
102
AR5
80 9908
AR5
80 9918
IR0
10
IR0
10
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
1
C
1
809908
0FFFFFFCB
Data memory
809908
Example 2
ADDC3
0FFFFFFCB −53
−53
R2, R7, R0
Before Instruction
After Instruction
R0
00 0000 0000
R2
00 0000 02BC
R7
00 0000 0F82 3970
700
R0
00 0000 123F 4671
R2
00 0000 02BC
R7
00 0000 0F82 3970
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
1
C
0
700
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Assembly Language Instructions
13-51
ADDF
Add Floating-Point Values
Syntax
ADDF src, dst
Operation
dst + src → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
2423
0 0 0 0 0 0 0 1 1
16 15
G
dst
8 7
0
src
Description
The sum of the dst and src operands is loaded into the dst register. The dst and
src operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-52
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Add Floating-Point Values
Example
ADDF
ADDF *AR4++(IR1),R5
Before Instruction
R5
AR
05 7980 0000 6.23750e+01
4809800
After Instruction
R5
09 052C 0000 5.3268750e+02
AR4
80992B
IR
112B
IR1
12B
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809800
86B2800 4.7031250e+02 809800
86B2800 4.7013250e+02
Assembly Language Instructions
13-53
ADDF3
Add Floating Point, 3-Operand
Syntax
ADDF3
Operation
src1 + src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
src2, src1, dst
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
dst
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
24 23
0 0 1 0 0 0 0 0 1
16 15
T
dst
8 7
src1
0
src2
Description
The sum of the src1 and src2 operands is loaded into the dst register. The src1,
src2, and dst operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-54
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Add Floating Point, 3-Operand
Example 1
ADDF3
or
ADDF3
R6,R5,R1
R5,R6,R1
Before Instruction
After Instruction
R1
00 0000 0000
R1
09 052C 0000 5.3268750e+02
R5
05 7980 0000 6.23750e+01
R5
05 7980 0000 6.23750e+01
R6
08 6B28 0000 4.7031250e+02 R6
LUF
0
Example 2
ADDF3
08 6B28 0000 4.7031250e+02
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
ADDF3
*+AR1(1),*AR7++(IR0),R4
Before Instruction
After Instruction
R4
00 0000 0000
R4
AR1
80 9820
AR1
80 9820
AR7
80 99FO
AR7
80 99F8
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UV
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
07 0DB2 0000 1.41695313e+02
Data memory
809821h
700F000 1.28940e+02
809821h
700F000 1.28940e+02
8099F0h
34C2000 1.27590e+01
8099F0h
34C2000 1.27590e+01
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Assembly Language Instructions
13-55
ADDF3||STF
Parallel ADDF3 and STF
Syntax
||
ADDF3
STF
src2, src1, dst1
src3, dst2
Operation
src1 + src2 → dst1
|| src3 → dst2
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 0 0 1 1 0
Description
dst1
16 15
src1
src3
8 7
dst2
0
src2
A floating-point addition and a floating-point store are performed in parallel. All
registers are read at the beginning and loaded at the end of the execute cycle.
If one of the parallel operations (STF) reads from a register and the operation
being performed in parallel (ADDF3) writes to the same register, STF accepts
as input the contents of the register before it is modified by the ADDF3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
13-56
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
Parallel ADDF3 and STF
Mode Bit
OVM
Example
||
ADDF3||STF
Operation is not affected by OVM bit value.
ADDF3
STF
*+AR3(IR1),R2,R5
R4,*AR2
Before Instruction
After Instruction
R2
07 0C80 0000
1.4050e+02
R2
07 0C80 0000
1.4050e+02
R4
05 7B40 0000
6.281250e+01
R4
05 7B40 0000
6.281250e+01
R5
00 0000 0000
R5
08 2020 0000
3.20250e+02
AR2
80 98F3
AR2
80 98F3
AR3
80 9800
AR3
80 9800
IR1
0A5
IR1
0A5
LUF
0
LUF
0
LV
0
LV
0
UF
0
UV
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8098A5h
733C000
1.79750e+02
8098F3h
57B4000
6.28125e+01
Data memory
8098A5h
733C000
8098F3h
0
1.79750e+02
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Assembly Language Instructions
13-57
ADDI Add Integer
Syntax
ADDI src, dst
Operation
dst + src → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
any CPU register
Opcode
31
24 23
0 0 0 0 0 0 1 0 0
16 15
G
8 7
dst
0
src
Description
The sum of the dst and src operands is loaded into the the dst register. The
dst and src operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a carry occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
ADDI
R3,R7
Before Instruction
R3
13-58
After Instruction
00 FFFF FFCB −53
R3
00 FFFF FFCB −53
R7
00 0000 0000
R7
35
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
53
Add Integer, 3-Operand
Syntax
ADDI3
Operation
src1 + src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
ADDI3
<src2 >,<src1 >,<dst >
any CPU register
indirect (disp = 0, 1, IR0, IR1)
any CPU register
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
dst
any CPU register
any CPU register
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
any CPU register
Opcode
31
24 23
0 0 1 0 0 0 0 1 0
16 15
T
dst
8 7
src1
0
src2
Description
The sum of the src1 and src2 operands is loaded into the dst register. The src1,
src2, and dst operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a carry occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-59
ADDl3 Add Integer, 3-Operand
Example 1
ADDI3
R4,R7,R5
Before Instruction
Example 2
ADDI3
After Instruction
R4
00 0000 00DC 220
R4
00 0000 00DC 220
R5
00 0000 0010
16
R5
00 0000 017C 380
R7
00 0000 00A0 160
R7
00 0000 00A0 160
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
*−AR3(1),*AR6−−(IR0),R2
Before Instruction
R2
00 0000 0010
After Instruction
16
R2
00 0000 6598 26,000
AR3
80 9802
AR3
80 9802
AR6
80 9930
AR6
80 9918
IR0
18
IR0
18
LUF
0
LUF
0
LV
0
LV
0
UF
0
UV
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809801
2AF8 11,000
809801
2AF8 11,000
809930
3A98 15,000
809930
3A98 15,000
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-60
Parallel ADDI3 and STI
Syntax
||
ADDI3
STI
ADDI3||STI
src2, src1, dst1
src3, dst2
Operation
src1 + src2 → dst1
|| src3 → dst2
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
2423
1 1 0 0 1 1 1
Description
dst1
16 15
src1
src3
8 7
dst2
0
src2
An integer addition and an integer store are performed in parallel. All registers
are read at the beginning and loaded at the end of the execute cycle. If one
of the parallel operations (STI) reads from a register and the operation being
performed in parallel (ADDI3) writes to the same register, STI accepts the contents of the register as input before it is modified by the ADDI3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a carry occurs; 0 otherwise
Assembly Language Instructions
13-61
ADDl3||STI Parallel ADDl3 and STI
Mode Bit
OVM
Example

Operation is affected by OVM bit value.
ADDI3
STI
*AR0−−(IR0),R5,R0
R3,*AR7
Before Instruction
R0
00 0000 0000
R3
00 0000 0035
R5
00 0000 00DC
After Instruction
R0
00 0000 0208
53
R3
00 0000 0035
53
220
R5
00 0000 00DC
220
AR0
80 992C
AR0
80 9920
AR7
80 983B
AR7
80 983B
IR0
OC
IR0
OC
LUF
0
LUF
0
LV
0
LV
0
UF
0
UV
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
520
Data memory
80992C
80983B
12C 300
0
80992C
80983B
12C 300
35
53
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-62
AND
Bitwise-Logical AND
Syntax
AND src, dst
Operands
dst AND src → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate (not sign extended)
any CPU register
Opcode
31
24 23
0 0 0 0 0 0 1 0 1
16 15
G
8 7
dst
0
src
Description
The bitwise-logical AND between the dst and src operands is loaded into the
dst register. The dst and src operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
AND
R1,R2
Before Instruction
After Instruction
R1
00 0000 0080
R1
00 0000 0080
R2
00 0000 0AFF
R2
00 0000 0080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
1
C
1
Assembly Language Instructions
13-63
AND3 Bitwise-Logical AND, 3-Operand
Syntax
AND3 src2, src1, dst
Operation
src1 AND src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
any CPU register
indirect (disp = 0, 1, IR0, IR1)
any CPU register
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
any CPU register
any CPU register
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
0 0 1 0 0 0 0 1 1
16 15
T
dst
8 7
src1
0
src2
Description
The bitwise-logical AND between the src1 and src2 operands is loaded into
the destination register. The src1, src2, and dst operands are assumed to be
unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-64
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
AND3
Bitwise-Logical AND, 3-Operand
Example 1
AND3
*AR0−−(IR0),*+AR1,R4
Before Instruction
After Instruction
R4
00 0000 0000
R4
00 0000 0020
AR0
80 98F4
AR0
80 98A4
AR1
80 9951
AR1
80 9951
IR0
50
IR0
50
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8098F4h
30
8098F4h
30
809952h
123
809952h
123
Data memory
Example 2
AND3
*−AR5,R7,R4
Before Instruction
After Instruction
R4
00 0000 0000
R4
00 0000 0002
R7
00 0000 0002
R7
00 0000 0002
AR5
80 985C
AR5
80 985C
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
0AFF
80985Bh
0AFF
Data memory
80985Bh
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Assembly Language Instructions
13-65
AND3||STI Parallel AND3 and STI
Syntax

AND3 src2, src1, dst1
STI
src3, dst2
Operation
src1 AND src2 → dst1
|| src3 → dst2
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1 0 1 0 0 0
Description
24 23
dst1
16 15
src1
src3
8 7
dst2
0
src2
A bitwise-logical AND and an integer store are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. If
one of the parallel operations (STI) reads from a register and the operation being performed in parallel (AND3) writes to the same register, STI accepts the
contents of the register as input before it is modified by the AND3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
13-66
1
Running Title—Attribute Reference
Status Bits
mnemonic
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
Chapter Title—Attribute Reference
13-67
AND3||STI Parallel AND3 and STI
Mode Bit
OVM
Example
||
Operation is not affected by OVM bit value.
AND3
STI
*+AR1(IR0),R4,R7
R3,*AR2
Before Instruction
R0
00 0000 0008
R3
00 0000 0035
R4
R7
After Instruction
R0
00 0000 0008
R3
00 0000 0035
00 0000 A323
R4
00 0000 A323
00 0000 0000
R7
00 0000 0003
53
AR1
80 99F1
AR1
80 99F1
AR2
80 983F
AR2
80 983F
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8099F9h
5C53
8099F9h
5C53
80983Fh
0
80983Fh
53
Data memory
35 53
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-68
Bitwise-Logical AND With Complement
Syntax
ANDN src, dst
Operation
dst AND ∼src → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
ANDN
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate (not sign extended)
any CPU register
Opcode
31
24 23
0 0 0 0 0 0 1 1 0
16 15
G
dst
8 7
0
src
Description
The bitwise-logical AND between the dst operand and the bitwise-logical complement (∼) of the src operand is loaded into the dst register. The dst and src
operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-69
ANDN Bitwise-Logical AND With Complement
Example
ANDN @980Ch,R2
Before Instruction
After Instruction
R2
00 0000 0C2F
R2
00 0000 042D
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
0A02
80980Ch
0A02
Data memory
80980Ch
13-70
Bitwise-Logical ANDN, 3-Operand
Syntax
ANDN3 src2, src1, dst
Operation
src1 AND ∼src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
ANDN3
any CPU register
indirect (disp = 0, 1, IR0, IR1)
any CPU register
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
dst
any CPU register
any CPU register
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IO0, IR1)
register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 1 0 0 0 1 0 0
16 15
T
dst
8 7
src1
0
src2
Description
The bitwise-logical AND between the src1 operand and the bitwise-logical
complement (∼) of the src2 operand is loaded into the dst register. The src1,
src2, and dst operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-71
ANDN3 Bitwise-Logical ANDN, 3-Operand
Example 1
ANDN3 R5,R3,R7
Before Instruction
Example 2
After Instruction
R3
00 0000 0C2F
R3
00 0000 0C2F
R5
00 0000 0A02
R5
00 0000 0A02
R7
00 0000 0000
R7
00 0000 042D
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
ANDN3 R1,*AR5++(IR0),R0
Before Instruction
R0
00 0000 0000
After Instruction
R0
00 0000 0F30
R1
00 0000 00CF
R1
00 0000 00CF
AR5
80 9825
AR5
80 982A
IR0
5
IR0
5
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
0FFF
809825h
0FFF
Data memory
809825h
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-72
Arithmetic Shift
Syntax
ASH count, dst
Operation
If (count ≥ 0):
dst << count → dst
ASH
Else:
dst >> |count | → dst
Operands
count general addressing modes (G):
00
01
10
11
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst any CPU register
Opcode
31
24 23
0 0 0 0 0 0 1 1 1
Description
16 15
G
dst
8 7
0
count
The seven LSBs of the count operand are used to generate the 2s-complement shift count of up to 32 bits.
If the count operand is greater than 0, the dst operand is left shifted by the value
of the count operand. Low-order bits that are shifted in are zero filled, and highorder bits are shifted out through the carry (C) bit.
Arithmetic left shift:
C ← dst ← 0
If the count operand is less than 0, the dst operand is right shifted by the absolute value of the count operand. The high-order bits of the dst operand are signextended as it is right shifted. Low-order bits are shifted out through the C bit.
Arithmetic right shift:
sign of dst → dst → C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count and dst operands are assumed to be signed integers.
Cycles
1
Assembly Language Instructions
13-73
ASH Arithmetic Shift
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Set to the value of the last bit shifted out; 0 for a shift count of 0
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example 1
ASH R1,R3
Before Instruction
Example 2
R1
00 0000 0010
R3
After Instruction
R1
00 0000 0010
00 000A E000
R3
00 E000 0000
LUF
0
LUF
0
LV
0
LV
1
UF
0
UF
0
N
0
N
1
16
Z
0
Z
0
V
0
V
1
C
0
C
0
ASH @98C3h,R5
Before Instruction
After Instruction
R5
00 AEC0 0001
R5
00 FFFF FFAE
DP
80
DP
80
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
1
Data memory
8098C3h
13-74
0FFE8 −24
8098C3h
0FFE8 −24
Arithmetic Shift, 3-Operand
Syntax
ASH3 count, src, dst
Operation
If (count ≥ 0):
src << count → dst
ASH3
Else:
src >> |count | → dst
Operands
count 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 27)
register (Rn2, 0 ≤ n2 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
src 3-operand addressing modes (T):
00
01
10
11
dst
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 1 0 0 0 1 0 1
Description
16 15
T
dst
8 7
src
0
count
The seven LSBs of the count operand are used to generate the 2s-complement shift count of up to 32 bits.
If the count operand is greater than 0, the src operand is left shifted by the value
of the count operand. Low-order bits that are shifted in are zero filled, and highorder bits are shifted out through the status register’s C bit.
Arithmetic left shift:
C ← src ← 0
If the count operand is less than 0, the src operand is right shifted by the absolute value of the count operand. The high-order bits of the src operand are sign
extended as they are right shifted. Low-order bits are shifted out through the
C (carry) bit.
Arithmetic right shift:
sign of src → src → C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count, src, and dst operands are assumed to be signed integers.
Cycles
1
Assembly Language Instructions
13-75
ASH3 Arithmetic Shift, 3-Operand
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Set to the value of the last bit shifted out; 0 for a shift count of 0
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example 1
ASH3
*AR3−−(1),R5,R0
Before Instruction
After Instruction
R0
00 0000 0000
R0
00 02B0 0000
R5
00 0000 02B0
R5
00 0000 02B0
AR3
80 9921
AR3
80 9920
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809921h
13-76
10
16
809921h
10 16
ASH3
Arithmetic Shift, 3-Operand
Example 2
ASH3
R1,R3,R5
Before Instruction
After Instruction
R1
00 FFFF FFF8 −8
R1
00 FFFF FFF8
R3
00 FFFF CB00
R3
00 FFFF CB00
R5
00 0000 0000
R5
00 FFFF FFCB
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
0
−8
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8.5.2 for the effects of
operand ordering on the cycle count.
Assembly Language Instructions
13-77
ASH3||STI Parallel ASH3 and STI
Syntax
||
Operation
ASH3 count, src2, dst1
STI
src3, dst2
If (count ≥ 0):
src2 << count → dst1
Else:
src2 >> |count| → dst1
|| src3 → dst2
Operands
count register (Rn1, 0 ≤ n1 ≤ 7)
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 0 1 0 0 1
Description
dst1
16 15
count
src3
8 7
dst2
0
src2
The seven LSBs of the count operand register are used to generate the 2scomplement shift count of up to 32 bits.
If the count operand is greater than 0, the src2 operand is left shifted by the
value of the count operand. Low-order bits shifted in are zero filled, and highorder bits are shifted out through the C bit.
Arithmetic left shift:
C ← src2 ← 0
If the count operand is less than 0, the src2 operand is right hifted by the absolute value of the count operand. The high-order bits of the src2 operand are
sign extended as they are right shifted. Low-order bits are shifted out through
the C bit.
13-78
Parallel ASH3 and STI
ASH3||STI
Arithmetic right shift:
sign of src2 → src2 → C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count and dst operands are assumed to be signed integers.
All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (STI) reads from a register and the operation being performed in parallel (ASH3) writes to the same register, STI accepts the contents of the register as input before it is modified by the ASH3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Set to the value of the last bit shifted out; 0 for a shift count of 0
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-79
ASH3||STI Parallel ASH3 and STI
Example
||
ASH3
STI
R1,*AR6++(IR1),R0
R5,*AR2
Before Instruction
R0
00 0000 0000
R1
00 0000 FFE8
R5
00 0000 0035
AR2
After Instruction
R0
00 FFFF FFAE
−24
R1
00 0000 FFE8 −24
53
R5
00 0000 0035
80 98A2
AR2
80 98A2
AR6
80 9900
AR6
80 998C
IR1
8C
IR1
8C
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
53
Data memory
809900h
0AE000000
809900h
0AE000000
8098A2h
0
8098A2h
35
53
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-80
Branch Conditionally (Standard)
Syntax
Bcond src
Operation
If cond is true:
If src is in register-addressing mode (Rn, 0 ≤ n ≤ 27),
src → PC.
If src is in PC-relative mode (label or address),
displacement + PC + 1 → PC.
Else, continue
Operands
src conditional-branch addressing modes (B):
0
1
Bcond
register
PC relative
Opcode
31
24 23
0 1 1 0 1 0 B 0 0 0 0
Description
16 15
cond
8 7
0
Register or displacement
Bcond signifies a standard branch that executes in four cycles. A branch is performed if the condition is true (since a pipeline flush also occurs on a true condition; see Section 8.2, Pipeline Conflicts, on page 8-4). If the src operand is expressed in register addressing mode, the contents of the specified register are
loaded into the PC. If the src operand is expressed in PC-relative mode, the
assembler generates a displacement: displacement = label − (PC of branch
instruction + 1). This displacement is stored as a 16-bit signed integer in the
16 LSBs of the branch instruction word. This displacement is added to the PC
of the branch instruction plus 1 to generate the new PC.
The ’C3x provides 20 condition codes that you can use with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7−R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-81
Bcond
Example
Branch Conditionally (Standard)
BZ R0
Before Instruction
After Instruction
R0
00 0003 FF00
R0
00 0003 FF00
PC
2B00
PC
3 FF00
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
1
Z
1
V
0
V
0
C
0
C
0
Note:
If a BZ instruction is executed immediately following a RND instruction with
a 0 operand, the branch is not performed, because the 0 flag is not set. To
circumvent this problem, execute a BZUF instead of a BZ instruction.
13-82
Branch Conditionally (Delayed)
Syntax
Bcond D src
Operation
If cond is true:
If src is in register-addressing mode (Rn, 0 ≤ n ≤ 27),
src → PC.
If src is in PC-relative mode (label or address),
displacement + PC + 3 → PC.
Else, continue
Operands
src conditional-branch addressing modes (B):
0
1
BcondD
register
PC relative
Opcode
31
24 23
0 1 1 0 1 0 B 0 0 0 1
Description
16 15
cond
8 7
0
Register or displacement
BcondD signifies a delayed branch that allows the three instructions after the
delayed branch to be fetched before the PC is modified. The effect is a singlecycle branch, and the three instructions following BcondD do not affect the
condition.
A branch is performed if the condition is true. If the src operand is expressed
in register-addressing mode, the contents of the specified register are loaded
into the PC. If the src operand is expressed in PC-relative mode, the assembler
generates a displacement: displacement = label − (PC of branch instruction
+ 3). This displacement is stored as a 16-bit signed integer in the 16 LSBs of
the branch instruction. This displacement is added to the PC of the branch instruction plus 3 to generate the new PC. The ’C3x provides 20 condition codes
that you can use with this instruction (see Table 13−12 on page 13-30 for a list
of condition mnemonics, condition codes, and flags). Condition flags are set
on the previous instruction only when the destination register is one of the extended-precision registers (R7−R0) or when one of the compare instructions
(CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-83
BcondD
Example
Branch Conditionally (Delayed)
BNZD 36 (36 = 24h)
Before Instruction
After Instruction
PC
0050
PC
0077
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Note:
Delayed branches disable interrupts until the completion of the three instructions that follow the delayed branch, regardless if the branch is or is not performed. The following instructions cannot be used in the next three instructions following a delayed branch: Bcond, BcondD, BR, BRD, CALL, CALLcond, DBcond, DBcondD, IDLE, IDLE2, RETIcond, RETScond, RPTB,
RPTS, TRAPcond.
13-84
Branch Unconditionally (Standard)
Syntax
BR src
Operation
src → PC
Operands
src long-immediate addressing mode
BR
Opcode
31
24 23
16 15
0 1 1 0 0 0 0 0
8 7
0
src
Description
BR performs a PC-relative branch that executes in four cycles, since a pipeline
flush also occurs upon execution of the branch (see Section 8.2, Pipeline Conflicts, on page 8-4). An unconditional branch is performed. The src operand is
assumed to be a 24-bit unsigned integer. Note that bit 24 = 0 for a standard
branch.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
BR 805Ch
Before Instruction
After Instruction
PC
0080
PC
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Assembly Language Instructions
805C
13-85
BRD Branch Unconditionally (Delayed)
Syntax
BRD src
Operation
src → PC
Operands
src long-immediate addressing mode
Opcode
31
24 23
16 15
0 1 1 0 0 0 0 1
Description
8 7
0
src
BRD signifies a delayed branch that allows the three instructions after the
delayed branch to be fetched before the PC is modified. The effect is a
single-cycle branch.
An unconditional branch is performed. The src operand is assumed to be a
24-bit unsigned integer. Note that bit 24 = 1 for a delayed branch.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
BRD 2Ch
Before Instruction
13-86
After Instruction
PC
001B
PC
002C
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
CALL
Call Subroutine
Syntax
CALL src
Operation
Next PC → *++SP
src → PC
Operands
src long-immediate addressing mode
Opcode
31
24 23
16 15
0 1 1 0 0 0 1 0
8 7
0
src
Description
A call is performed. The next PC value is pushed onto the system stack. The
src operand is loaded into the PC. The src operand is assumed to be a 24-bit
unsigned-immediate operand. Since the CALL instruction takes 4 cycles to
execute, the pipeline is flushed.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
CALL 123456h
Before Instruction
PC
0005
After Instruction
PC
123456
SP
809801
SP
809802
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
809802h
6
Data memory
Assembly Language Instructions
13-87
CALLcond
Call Subroutine Conditionally
Syntax
CALLcond src
Operation
If cond is true:
Next PC → *++SP
If src is in register addressing mode (Rn, 0 ≤ n ≤ 27),
src → PC.
If src is in PC-relative mode (label or address),
displacement + PC + 1 → PC.
Else, continue
Operands
src conditional-branch addressing modes (B):
0
1
register
PC relative
Opcode
31
24 23
0 1 1 1 0 0 B 0 0 0 0
Description
16 15
cond
8 7
0
Register or displacement
A call is performed if the condition is true. If the condition is true, the next PC
value is pushed onto the system stack. If the src operand is expressed in register addressing mode, the contents of the specified register are loaded into the
PC. If the src operand is expressed in PC-relative mode, the assembler generates a displacement: displacement = label − (PC of call instruction + 1). This
displacement is stored as a 16-bit signed integer in the 16 LSBs of the call instruction word. This displacement is added to the PC of the call instruction plus
1 to generate the new PC. This instruction flushes the pipeline as shown in
Example 8−13 on page 8-18.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7−R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Cycles
5
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
13-88
Call Subroutine Conditionally
Example
CALLcond
CALLNZ R5
Before Instruction
After Instruction
R5
00 0000 0789
R5
00 0000 0789
PC
0123
PC
0789
SP
809835
SP
809836
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
809836h
124
Data memory
Assembly Language Instructions
13-89
CMPF
Compare Floating-Point Value
Syntax
CMPF src, dst
Operation
dst − src
Operands
src general addressing modes (G):
00
01
10
11
dst
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
24 23
0 0 0 0 0 1 0 0 0
1615
G
dst
8 7
0
src
Description
The src operand is subtracted from the dst operand. The result is not loaded
into any register, which allows for nondestructive compares. The dst and src
operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified for all destination registers (R27 −R0).
Mode Bit
13-90
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Compare Floating-Point Value
Example
CMPF
CMPF *+AR4,R6
Before Instruction
R6
After Instruction
07 0C80 0000 1.4050e+02
R6
07 0C80 0000 1.4050e+02
AR4
80 98F2
AR4
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
1
V
0
V
0
C
0
C
0
80 98F2
Data memory
8098F3h
070C8000 1.4050e+02
8098F3h
070C8000 1.4050e+02
Assembly Language Instructions
13-91
CMPF3
Compare Floating-Point Value, 3-Operand
Syntax
CMPF3 src2, src1
Operation
src1 − src2
Operands
src1 3-operand addressing modes (T):
00
01
10
11
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
0 0 1 0 0 0 1 1 0
16 15
T
0 0 0 0 0
8 7
src1
0
src2
Description
The src2 operand is subtracted from the src1 operand. The result is not loaded
into any register, which allows for nondestructive compares. The src1 and src2
operands are assumed to be floating-point numbers. Although this instruction
has only two operands, it is designated as a 3-operand instruction because operands are specified in the 3-operand format.
Cycles
1
Status Bits
These condition flags are modified for all destination registers (R27 −R0).
Mode Bit
13-92
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Compare Floating-Point Value, 3-Operand
Example
CMPF3
*AR2,*AR3−−(1)
CMPF3
Before Instruction
After Instruction
AR2
80 9831
AR2
80 9831
AR3
80 9852
AR4
80 9851
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809831h
77A7000 2.5044e+02
809831h
77A7000 2.5044e+02
809852h
57A2000 6.253125e+01
809852h
57A2000 6.253125e+01
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Assembly Language Instructions
13-93
CMPI Compare Integer
Syntax
CMPI src, dst
Operation
dst − src
Operands
src general addressing modes (G):
00
01
10
11
dst
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0 0 0 1 0 0 1
16 15
G
8 7
0
src
dst
Description
The src operand is subtracted from the dst operand. The result is not loaded
into any register, thus allowing for nondestructive compares. The dst and src
operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified for all destination registers (R27 −R0).
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
CMPI R3,R7
Before Instruction
13-94
After Instruction
R3
00 0000 0898 2200
R3
00 0000 0898 2200
R7
00 0000 03E8 1000
R7
00 0000 03E8 1000
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
1
Compare Integer, 3-Operand
Syntax
CMPI3 src2, src1
Operation
src1 − src2
Operands
src1 3-operand addressing modes (T):
00
01
10
11
CMPI3
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 27)
register (Rn2, 0 ≤ n2 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
0 0 1 0 0 0 1 1 1
16 15
T
0 0 0 0 0
8 7
src1
0
src2
Description
The src2 operand is subtracted from the src1 operand. The result is not loaded
into any register, which allows for nondestructive compares. The src1 and src2
operands are assumed to be signed integers. Although this instruction has
only two operands, it is designated as a 3-operand instruction because operands are specified in the 3-operand format.
Cycles
1
Status Bits
These condition flags are modified for all destination registers (R27 −R0).
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-95
CMPI3
Example
Compare Integer, 3-Operand
CMPI3
R7,R4
Before Instruction
After Instruction
R4
00 0000 0898 2200
R4
00 0000 0898 2200
R7
00 0000 03E8 1000
R7
00 0000 03E8 1000
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-96
Decrement and Branch Conditionally (Standard)
Syntax
DBcond ARn, src
Operation
ARn − 1 → ARn
If cond is true and ARn ≥ 0 :
If src is in register addressing mode (Rn, 0 ≤ n ≤ 27),
src → PC.
If src is in PC-relative mode (label or address),
displacement + PC + 1 → PC.
Else, continue
Operands
src conditional-branch addressing modes (B):
0
1
DBcond
register
PC relative
ARn register (0 ≤ n ≤ 7)
Opcode
31
0 1 1 0 1 1 B
Description
24 23
ARn
16 15
0
cond
8 7
0
Register or displacement
DBcond signifies a standard branch that executes in four cycles because the
pipeline must be flushed if cond is true. The specified auxiliary register is decremented and a branch is performed if the condition is true and the specified
auxiliary register is greater than or equal to 0. The condition flags are those set
by the last previous instruction that affects the status bits.
The auxiliary register is treated as a 24-bit signed integer. The 8 MSBs are unmodified by the decrement operation. The comparison of the auxiliary register
uses only the 24 LSBs of the auxiliary register. Note that the branch condition
does not depend on the auxiliary register decrement.
If the src operand is expressed in register addressing mode, the contents of
the specified register are loaded into the PC. If the src operand is expressed
in PC-relative addressing mode, the assembler generates a displacement:
displacement = label − (PC of branch instruction + 1). This integer is stored as
a 16-bit signed integer in the 16 LSBs of the branch instruction word. This displacement is added to the PC of the branch instruction plus 1 to generate the
new PC.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R0−R7) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Assembly Language Instructions
13-97
DBcond
Decrement and Branch Conditionally (Standard)
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
CMPI
DBLT
200,R3
AR3,R2
Before Instruction
13-98
After Instruction
R2
00 0000 009F
R2
00 0000 009F
R3
00 0000 0080
R3
00 0000 0080
AR3
00 0012
AR3
00 0011
PC
005F
PC
009F
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
1
N
1
Z
0
Z
0
V
0
V
0
C
0
C
0
Decrement and Branch Conditionally (Delayed)
Syntax
DBcond D ARn, src
Operation
ARn − 1 → ARn
If cond is true and ARn ≥ 0:
If src is in register addressing mode (Rn, 0 ≤ n ≤ 27)
src → PC
If src is in PC-relative mode (label or address)
displacement + PC + 3 → PC.
DBcondD
Else, continue
Operands
src conditional-branch addressing modes (B):
0
1
register
PC relative
ARn register (0 ≤ n ≤ 7)
Opcode
31
0 1 1 0 1 1 B
Description
24 23
ARn
16 15
1
cond
8 7
0
Register or displacement
DBcond D signifies a delayed branch that allows the three instructions after
the delayed branch to be fetched before the PC is modified. The effect is a
single-cycle branch. The specified auxiliary register is decremented, and a
branch is performed if the condition is true and the specified auxiliary register
is greater than or equal to 0. The condition flags are those set by the last previous instruction that affects the status bits. The three instructions following the
DBcondD do not affect the condition.
The auxiliary register is treated as a 24-bit signed integer. The 8 MSBs are unmodified by the decrement operation. The comparison of the auxiliary register
uses only the 24 LSBs of the auxiliary register. The branch condition does not
depend on the auxiliary register decrement.
If the src operand is expressed in register-addressing mode, the contents of
the specified register are loaded into the PC. If the src is expressed in PC-relative addressing, the assembler generates a displacement: displacement = label − (PC of branch instruction + 3). This displacement is added to the PC of
the branch instruction plus 3 to generate the new PC. Note that bit 21 = 1 for
a delayed branch.
The ’C3x provides 20 condition codes that you can use with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7−R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Assembly Language Instructions
13-99
DBcondD
Decrement and Branch Conditionally (Delayed)
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
CMPI
DBZD
26h,R2
AR5, $+110h
Before Instruction
13-100
After Instruction
R2
00 0000 0026
R2
00 0000 0026
AR5
00 0067
AR5
00 0066
PC
0100
PC
0210
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
1
V
0
V
0
C
0
C
0
Floating-Point-to-Integer Conversion
Syntax
FIX src, dst
Operation
fix(src) → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
FIX
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
any CPU register
Opcode
31
24 23
0 0 0 0 0 1 0 1 0
Description
16 15
G
dst
8 7
0
src
The floating-point operand src is rounded down to the nearest integral value
less than or equal to floating-point value, and the result is loaded into the dst
register. The src operand is assumed to be a floating-point number and the dst
operand a signed integer.
The exponent field of the dst register (bits 39−32) is not modified.
Integer overflow occurs when the floating-point number is too large to be represented as a 32-bit 2s-complement integer. In the case of integer overflow, the
result is saturated in the direction of overflow.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-101
FIX
Floating-Point-to-Integer Conversion
Example
FIX
R1,R2
Before Instruction
13-102
After Instruction
R1
0A 2820 0000 1.3454e+3
R1
R2
00 0000 0000
R2
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
0A 2820 0000 13454e+3
00 0000 0541 1345
Parallel FIX and STI
Syntax
||
FIX||STI
FIX src2, dst1
STI src3, dst2
Operation
fix(src2 ) → dst1
|| src3 → dst2
Operands
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1 0 1 0 1 0
Description
24 23
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
A floating-point-to-integer conversion is performed. All registers are read at
the beginning and loaded at the end of the execute cycle. This means that, if
one of the parallel operations (STI) reads from a register, and the operation
being performed in parallel (FIX) writes to the same register, STI accepts the
contents of the register as input before it is modified by FIX.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Integer overflow occurs when the floating-point number is too large to be represented as a 32-bit 2s-complement integer. In the case of integer overflow,
the result is saturated in the direction of overflow.
Cycles
1
Assembly Language Instructions
13-103
FIX||STI Parallell FIX and STI
Status Bits
Mode Bit
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
FIX
STI
||
*++AR4(1),R1
R0,*AR2
Before Instruction
After Instruction
R0
00 0000 00DC 220
R0
00 0000 00DC 220
R1
00 0000 0000
R1
00 0000 00B3 179
AR2
80 983C
AR2
80 983C
AR4
80 98A2
AR4
80 98A3
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
8098A3h
80983Ch
733C000 1.7950e+02
0
8098A3
80983C
733C000 1.79750e+02
0DC 220
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-104
Integer-to-Floating-Point Conversion
Syntax
FLOAT src, dst
Operation
float (src) → dst
Operands
src general addressing modes (G):
00
01
10
11
FLOAT
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 7)
Opcode
31
24 23
0 0 0 0 0 1 0 1 1
16 15
G
dst
8 7
0
src
Description
The integer operand src is converted to the floating-point value equal to it; the
result is loaded into the dst register. The src operand is assumed to be a signed
integer; the dst operand is assumed to be a floating-point number.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-105
FLOAT
Example
Integer-to-Floating-Point Conversion
FLOAT *++AR2(2),R5
Before Instruction
R5
00 034C 2000 1.27578125e+01
After Instruction
R5
00 72E0 0000 1.74e+02
AR2
80 9800
AR2
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
80 9802
V
0
V
0
C
0
C
0
Data memory
809802
13-106
0AE 174
809802
0AE 174
Parallel FLOAT and STF
Syntax
||
FLOAT||STF
FLOAT src2, dst1
STF
src3, dst2
Operation
float(src2 ) → dst1
|| src3 → dst2
Operands
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
register (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
register (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 0 1 0 1 1
Description
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
An integer-to-floating-point conversion is performed. All registers are read at
the beginning and loaded at the end of the execute cycle. If one of the parallel
operations (STF) reads from a register and the operation being performed in
parallel (FLOAT) writes to the same register, then STF accepts the contents
of the register as input before it is modified by FLOAT.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-107
FLOAT||STF
Parallel FLOAT and STF
Example
||
FLOAT
STF
*+AR2(IR0),R6
R7,*AR1
Before Instruction
After Instruction
R6
00 0000 0000
R6
07 2E00 0000 1.740e+02
R7
03 4C20 0000 1.27578125e+01
R7
03 4C20 0000 1.27578125e+01
AR1
80 9933
AR1
80 9933
AR2
80 98C5
AR2
80 98C5
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
8098CD
809933
0AE 174
0
8098CD
809933
0AE 174
034C2000 1.27578125e+01
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-108
Interrupt Acknowledge
Syntax
IACK src
Operation
Perform a dummy read operation with IACK = 0.
At end of dummy read, set IACK to 1.
Operands
src general addressing modes (G):
01
10
IACK
direct
indirect
Opcode
31
24 23
0 0 0 1 1
0 1 1 0
16 15
G
0 0 0 0 0
87
0
src
Description
A dummy read operation is performed if off-chip memory is specified. IACK is
set to 0, regardless of src location, a half H1 cycle after the beginning of the
decode phase of the IACK instruction. At the first half of the H1 cycle of the
completion of the dummy read, IACK is set to 1. The IACK signal will not be
extended due to multicycle reads with wait states. This instruction can be used
to generate an external interrupt acknowledge. The IACK signal and the address can be used to signal interrupt acknowledge to external devices. The
data read by the processor is unused.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-109
IACK Interrupt Acknowledge
Example
IACK *AR5
Before Instruction
13-110
After Instruction
IACK
1
IACK
1
PC
300
PC
301
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Idle Until Interrupt
Syntax
IDLE
Operation
1 → ST(GIE)
Next PC → PC
Idle until interrupt.
Operands
None
IDLE
Opcode
31
0 0 0
24 23
16 15
87
0
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
The global-interrupt-enable bit is set, the next PC value is loaded into the PC,
and the CPU idles until an unmasked interrupt is received. When the interrupt
is received, the contents of the PC are pushed onto the active system stack,
the interrupt vector is read, and the interrupt service routine is executed.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
IDLE
; The processor idles until a reset
; or unmasked interrupt occurs.
For correct device operation, the three instructions after a delayed
branch should not be IDLE or IDLE2 instructions.
Assembly Language Instructions
13-111
IDLE2
Low-Power Idle
Syntax
IDLE2
(supported by: ’LC31, ’C32, ’C30 silicon revision 7.x or
greater, ’C31 silicon revision 5.x or greater)
Operation
1 → ST(GIE)
Next PC → PC
Idle until interrupt.
Operands
None
Opcode
31
24 23
0 0 0
Description
16 15
87
0
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
The IDLE2 instruction serves the same function as IDLE, except that it removes the functional clock input from the internal device. This allows for extremely low power mode. The PC is incremented once, and the device remains
in an idle state until one of the external interrupts (INT0−3) is asserted.
In IDLE2 mode, the ’C3x devices that support this mode behave as follows:
- The CPU, peripherals, and memory retain their previous states.
- When the device is in the functional (nonemulation) mode, the clocks stop
with H1 high and H3 low.
- The device remains in IDLE2 until one of the four external interrupts
(INT3 −INT0) is asserted for at least two H1 cycles. When one of the four
interrupts is asserted, the clocks start after a delay of one H1 cycle. The
clocks can start up in the phase opposite that in which they were stopped
(that is, H1 might start high when H3 was high before stopping, and H3
might start high when H1 was high before stopping). However, the H1 and
H3 clocks remain 180° out of phase with each other.
- During IDLE2 operation, one of the four external interrupts must be as-
serted for at least two H2 cycles to be recognized and serviced by the
CPU. For the processor to recognize only one interrupt when it restarts operation, the interrupt must be asserted for less than three cycles.
- When the device is in emulation mode, the H1 and H3 clocks continue to
run normally, and the CPU operates as if an IDLE instruction had been
executed. The clocks continue to run for correct operation of the emulator.
13-112
Low-Power Idle
IDLE2
For correct device operation, the three instructions after a delayed
branch should not be IDLE or IDLE2 instructions.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
IDLE2
; The processor idles until a reset
; or interrupt occurs.
Assembly Language Instructions
13-113
LDE Load Floating-Point Exponent
Syntax
LDE src, dst
Operation
src(exp) → dst(exp)
Operands
src general addressing modes (G):
00
01
10
11
dst
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
0 0 0
24 23
0 0 1 1 0 1
16 15
G
dst
87
0
src
Description
The exponent field of the src operand is loaded into the exponent field of the
dst register. No modification of the dst register mantissa field is made unless
the value of the exponent loaded is the reserved value of the exponent for 0
as determined by the precision of the src operand. Then the mantissa field of
the dst register is set to 0. The src and dst operands are assumed to be floating-point numbers. Immediate values are evaluated in the short floating-point
format.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
13-114
Load Floating-Point Exponent
Example
LDE
LDE R0,R5
Before Instruction
After Instruction
R0
02 0005 6F30 4.00066337e+00
R0
02 0005 6F30 4.00066337e+00
R5
0A 056F E332 1.06749648e+03
R5
02 056F E332 4.16990814e+00
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Assembly Language Instructions
13-115
LDF
Load Floating-Point Value
Syntax
LDF src, dst
Operation
src → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 7)
dst
Opcode
31
24 23
0 0 0
0 0 1 1 1 0
16 15
G
87
dst
0
src
Description
The src operand is loaded into the dst register. The dst and src operands are
assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
LDF
@9800h,R2
Before Instruction
After Instruction
R2
00 0000 0000
R2
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
01 0C52 A000 2.19254303e+00
Data memory
809800
13-116
010C52A0 2.19254303e+00
809800
010C52A0 2.19254303e+00
Load Floating-Point Value Conditionally
Syntax
LDFcond src, dst
Operation
If cond is true:
src → dst.
LDFcond
Else:
dst is unchanged.
Operands
src general addressing modes (G):
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
00
01
10
11
dst
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
24 23
0 1 0 0
Description
cond
16 15
G
dst
87
0
src
If the condition is true, the src operand is loaded into the dst register; otherwise,
the dst register is unchanged. The dst and src operands are assumed to be
floating-point numbers.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Note that an LDFU (load floating-point unconditionally) instruction is useful for loading R7−R0 without affecting condition flags. Condition flags are set on a previous instruction only when the destination register
is one of the extended-precision registers (R7−R0) or when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-117
LDFcond
Example
Load Floating-Point Value Conditionally
LDFZ
R3,R5
Before Instruction
13-118
After Instruction
R3
2C FF2C D500 1.77055560e+13
R3
2C FF2C D500 1.77055560e+13
R5
5F 0000 003E 3.96140824e+28
R5
2C FF2C D500 1.77055560e+13
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
1
Z
1
V
0
V
0
C
0
C
0
Load Floating-Point Value, Interlocked
Syntax
LDFI src, dst
Operation
Signal interlocked operation
src → dst
Operands
src general addressing modes (G):
01
10
dst
LDFI
direct
indirect (disp = 0−255, IR0, IR1)
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
0 0 0
24 23
0 0 1 1 1 1
16 15
G
dst
87
0
src
Description
The src operand is loaded into the dst register. An interlocked operation is signaled over XF0 and XF1. The src and dst operands are assumed to be floatingpoint numbers. Only direct and indirect modes are allowed. See Section 7.4,
Interlocked Operations, on page 7-13 for a detailed description.
Cycles
1 if XF1 = 0 (see Section 7.4 on page 7-13)
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-119
LDFI
Load Floating-Point Value, Interlocked
Example
LDFI *+AR2,R7
Before Instruction
After Instruction
R7
00 0000 0000
R7
05 84C0 0000
AR2
80 98F1
AR2
80 98F1
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8098F2h
584C000
−6.28125e+01
Data memory
8098F2h
13-120
584C000 −6.28125e+01
−6.28125e+01
Parallel LDF and LDF
Syntax
LDF||LDF
LDF src2, dst2
LDF src1, dst1
||
Operation
src2 → dst2
|| src1 → dst1
Operands
src1
dst1
src2
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
This instruction’s operands have been augmented on the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
dst1
src2
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
Opcode
31
24 23
1 1 0 0 0 1 0
dst2
16 15
dst1
0 0 0
87
src1
0
src2
Description
Two floating-point loads are performed in parallel. If the LDFs load the same
register, the assembler issues a warning. The result is that of LDF src2, dst2.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-121
LDF||LDF
Parallel LDF and LDF
Example
||
*−− AR1(IR0),R7
*AR7++(1),R3
LDF
LDF
Before Instruction
After Instruction
R3
00 0000 0000
R0
00 0000 0008
R7
00 0000 0000
R3
05 7B40 0000 6.281250e+01
AR1
80 985F
R7
07 0C80 0000 1.4050e+02
AR7
80 988A
AR1
80 9857
IR0
8
AR7
80 988B
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809857h
70C8000 1.4050e+02
80988Ah
57B4000 6.281250e+01 80988Ah
809857h
70C8000 1.4050e+02
57B4000 6.281250e+01
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-122
Parallel LDF and STF
Syntax
LDF||STF
LDF src2, dst1
STF src3, dst2
||
Operation
src2 → dst1
|| src3 → dst2
Operands
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented on the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 0 1 1 0 0
Description
dst1
16 15
0 0 0
src3
87
dst2
0
src2
A floating-point load and a floating-point store are performed in parallel.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-123
LDF||STF
Parallel LDF and STF
Example
*AR2−− (1),R1
R3,*AR4++(IR1)
LDF
STF
||
Before Instruction
After Instruction
R1
00 0000 0000
R1
07 0C80 0000 1.4050e+02
R3
05 7B40 0000 6.28125e+01
R3
05 7B40 0000 6.28125e+01
AR2
80 98E7
AR2
80 98E6
AR4
80 9900
AR4
80 9910
IR1
10
IR1
10
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
8098E7h
70C8000 1.4050e+02
809900h
0
8098E7h
70C8000 1.4050e+02
809900h
57B4000 6.28125e+01
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-124
Load Integer
Syntax
LDI src, dst
Operation
src → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
LDI
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
any CPU register
Opcode
31
0 0 0
24 23
0 1 0 0 0 0
16 15
G
dst
87
0
src
Description
The src operand is loaded into the dst register. The dst and src operands are
assumed to be signed integers. An alternate form of LDI, LDP, is used to load
the data-page pointer register (DP). See the LDP instruction in Section 13.6.2
Optional Assembler Syntax beginning on page 13-34.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-125
LDI
Load Integer
Example
LDI *−AR1(IR0),R5
Before Instruction
R5
After Instruction
00 0000 03C5 965
AR1
2C
R5
00 0000 0026 38
AR1
2C
IR0
5
IR0
5
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
27h
13-126
26
38
27h
26 38
Load Integer Conditionally
Syntax
LDIcond src, dst
Operation
If cond is true:
src → dst,
LDIcond
Else:
dst is unchanged.
Operands
src general addressing modes (G):
00
01
10
11
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst
any CPU register
Opcode
31
24 23
0 1 0 1
Description
cond
16 15
G
dst
87
0
src
If the condition is true, the src operand is loaded into the dst register. Otherwise, the dst register is unchanged. Regardless of the condition, a read of the
src takes place. The dst and src operands are assumed to be signed integers.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Note that an LDIU (load integer unconditionally) instruction
is useful for loading R7−R0 without affecting the condition flags. Condition
flags are set on a previous instruction only when the destination register is one
of the extended-precision registers (R7−R0) or when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-127
LDIcond
Example
Load Integer Conditionally
LDIZ *ARO++,R6
Before Instruction
R6
After Instruction
00 0000 0FE2 4,066
R6
00 0000 0FE2 4,066
AR0
80 98F0
AR0
80 98F1
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
8098F0h
027C
636
8098F0h
027C 636
Note: Auxiliary Register Arithmetic
The test condition does not affect the auxiliary register arithmetic. (AR
modification always occurs.)
13-128
Load Integer, Interlocked
Syntax
LDII src, dst
Operation
Signal interlocked operation
src → dst
Operands
src general addressing modes (G):
01
10
LDII
direct
indirect (disp = 0−255, IR0, IR1)
dst any CPU register
Opcode
31
0 0 0
24 23
0 1 0 0 0 1
16 15
G
dst
87
0
src
Description
The src operand is loaded into the dst register. An interlocked operation is signaled over XF0 and XF1. The src and dst operands are assumed to be signed
integers. Note that only the direct and indirect modes are allowed. See Section
7.4, Interlocked Operations, on page 7-13 for a detailed description.
Cycles
1 if XF = 0 (see Section 7.4 on page 7-13)
Status Bits
These condition flags are modified only if the destination register is R7− R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-129
LDII
Load Integer, Interlocked
Example
LDII @985Fh,R3
Before Instruction
After Instruction
R3
00 0000 0000
R3
00 0000 00DC
DP
80
DP
80
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
0DC
80985Fh
0DC
Data memory
80985Fh
13-130
Parallel LDI and LDI
Syntax
LDI||LDI
LDI src2, dst2
LDI src1, dst1
||
Operation
src2 → dst2
|| src1 → dst1
Operands
src1
dst1
src2
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
This instruction’s operands have been augmented on the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
dst1
src2
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
Opcode
31
24 23
1 1 0 0 0 1 1
dst2
16 15
dst1
0 0 0
87
src1
0
src2
Description
Two integer loads are performed in parallel. The assembler issues a warning
if the LDIs load the same register. The result is that of LDI src2, dst2.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-131
LDI||LDI
Parallel LDI and LDI
Example
LDI *−AR1(1),R7
LDI *AR7++(IR0),R1
||
Before Instruction
After Instruction
R1
00 0000 0000
R1
00 0000 02EE 750
R7
00 0000 0000
R7
00 0000 00FA 250
AR1
80 9826
AR1
80 9826
AR7
80 98C8
AR7
80 98D8
IR0
10
IR0
10
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809825h
0FA
250
809825h
0FA 250
8098C8h
2EE
750
8098C8h
2EE 750
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-132
Parallel LDI and STI
Syntax
LDI||STI
LDI src2, dst1
STI src3, dst2
||
Operation
src2 → dst1
|| src3 → dst2
Operands
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented on the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 0 1 1 0 1
dst1
16 15
0 0 0
src3
87
dst2
0
src2
Description
An integer load and an integer store are performed in parallel. If src2 and dst2
point to the same location, src2 is read before the dst2 is written.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-133
LDI||STI Parallel LDI and STI
Example
||
LDI *−AR1(1),R2
STI R7,*AR5++(IR0)
Before Instruction
R2
00 0000 0000
R7
00 0000 0035
AR1
After Instruction
R2
00 0000 00DC 220
R7
00 0000 0035
80 98E7
AR1
80 98E7
AR5
80 982C
AR5
80 9834
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
53
53
Data memory
8098E6h
0DC
80982Ch
0
220
8098E6h
80982Ch
0DC 220
35
53
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-134
Load Floating-Point Mantissa
Syntax
LDM src, dst
Operation
src (man) → dst (man)
Operands
src general addressing modes (G):
00
01
10
11
LDM
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 7)
dst
Opcode
31
24 23
0 0 0
0 1 0 0 1 0
16 15
G
87
dst
0
src
Description
The mantissa field of the src operand is loaded into the mantissa field of the
dst register. The dst exponent field is not modified. The src and dst operands
are assumed to be floating-point numbers. If the src operand is from memory,
the entire memory contents are loaded as the mantissa. If immediate addressing mode is used, bits 15−12 of the instruction word are forced to 0 by the assembler.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
LDM 156.75,R2 (156.75 = 071CC00000h)
Before Instruction
After Instruction
R2
00 0000 0000
R2
00 1CC0 0000
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
1.22460938e+00
Assembly Language Instructions
13-135
LDP Load Data-Page Pointer
Syntax
LDP src, DP
Operation
src → data-page pointer
Operands
src is the 8 MSBs of the absolute 24-bit source address (src).
The “DP” in the operand is optional.
Opcode
31
0 0 0
Description
24 23
16 15
87
0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0
src
This pseudo-op is an alternate form of the LDUI instruction, except that LDP
is always in the immediate addressing mode. The src operand field contains
the eight MSBs of the absolute 24-bit src address (essentially, only
bits 23 −16 of src are used). These eight bits are loaded into the eight LSBs
of the data-page pointer.
The eight LSBs of the pointer are used in direct addressing as a pointer to the
page of data being addressed. There is a total of 256 pages, each page 64K
words long. Bits 31−8 of the pointer are reserved and should be kept set to 0.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
LDP @809900h, DP
or
LDP @809900h
Before Instruction
DP
13-136
After Instruction
065
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Divide Clock by 16
Syntax
LOPOWER
Operation
H1 → H1/16
Operands
None
LOPOWER
(supported by: ’LC31 and ’C32, ’C31 silicon
revision 5.0 or greater, ’C30 silicon revision 7.0
or greater)
Opcode
31
0 0 0
Description
23
0
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
The device continues to execute instructions, but at the reduced rate of the
CLKIN frequency divided by 16 (that is, in LOPOWER mode, a ’C3x device that
supports this mode with a CLKIN frequency of 32 MHz performs in the same
way as a 2-MHz ’C3x device, which has an instruction-cycle time of 1000 ns).
This allows for low-power operation.
The ’C3x CPUs slow down during the read phase of the LOPOWER instruction. To exit the LOPOWER power-down mode, invoke the MAXSPEED
instruction (opcode = 1080 0000 h). The ’C3x resumes full-speed operation
during the read phase of the MAXSPEED instruction.
Do not run the IDLE2 instruction in the LOPOWER mode.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
LOPOWER
; The processor slows down operation to
; 1/16th of the H1 clock.
Assembly Language Instructions
13-137
LSH Logical Shift
Syntax
LSH count, dst
Operation
If count ≥ 0:
dst << count → dst
Else:
dst >> |count | → dst
Operands
count general addressing modes (G):
00
01
10
11
dst
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
any CPU register
Opcode
31
24 23
0 0 0
Description
0 1 0 0 1 1
16 15
G
dst
87
0
count
The seven LSBs of the count operand are used to generate the 2s-complement shift count. If the count operand is greater than 0, the dst operand is left
shifted by the value of the count operand. Low-order bits shifted in are zero
filled, and high-order bits are shifted out through the carry (C) bit.
Logical left shift:
C ← dst ← 0
If the count operand is less than 0, the dst is right shifted by the absolute value
of the count operand. The high-order bits of the dst operand are zero filled as
they are shifted to the right. Low-order bits are shifted out through the C bit.
Logical right shift:
0 → dst → C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count operand is assumed to be a signed integer, and the dst operand is assumed to be an unsigned integer.
13-138
Logical Shift
LSH
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Set to the value of the last bit shifted out; 0 for a shift count of 0
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example 1
LSH
R4,R7
Before Instruction
Example 2
After Instruction
R4
00 0000 0018
R4
00 0000 0018
R7
00 0000 02AC
R7
00 AC00 0000
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
1
C
0
C
0
24
24
LSH *−AR5(IR1),R5
Before Instruction
After Instruction
R5
00 12C0 0000
R5
00 0001 2C00
AR5
80 9908
AR5
80 9908
IR0
4
IR0
4
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809904h
0FFFFFFF4 −12
809904h
0FFFFFFF4 −12
Assembly Language Instructions
13-139
LSH3
Logical Shift, 3-Operand
Syntax
LSH3 count, src, dst
Operation
If count ≥ 0:
src << count → dst
Else:
src >> |count | → dst
Operands
src 3-operand addressing modes (T):
00
01
10
11
any CPU register
indirect (disp = 0, 1, IR0, IR1)
any CPU register
indirect (disp = 0, 1, IR0, IR1)
count 3-operand addressing modes (T):
00
01
10
11
dst
any CPU register
any CPU register
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 1
Description
0 0 1 0 0 0
16 15
T
dst
87
src
0
count
The seven LSBs of the count operand are used to generate the 2s-complement shift count.
If the count operand is greater than 0, a copy of the src operand is left shifted
by the value of the count operand, and the result is written to the dst. (The src
is not changed.) Low-order bits shifted in are zero filled, and high-order bits are
shifted out through the carry (C) bit.
Logical left shift:
C ← src ← 0
If the count operand is less than 0, the src operand is right shifted by the absolute value of the count operand. The high-order bits of the dst operand are 0filled as they are shifted to the right. Low-order bits are shifted out through the
C bit.
Logical right shift:
0 → src → C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count operand is assumed to be a signed integer. The src and dst operands
are assumed to be unsigned integers.
13-140
LSH3
Logical Shift, 3-Operand
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Set to the value of the last bit shifted out; 0 for a shift count of 0;
unaffected if dst is not R7−R0
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example 1
LSH3 R4,R7,R2
Before Instruction
R2
00 0000 0000
R4
00 0000 0018
After Instruction
24
R2
00 AC00 0000
R4
00 0000 0018 24
R7
00 0000 02AC
R7
00 0000 02AC
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
1
C
0
C
0
Assembly Language Instructions
13-141
LSH3
Logical Shift, 3-Operand
Example 2
LSH3 *−AR4(IR1),R5,R3
Before Instruction
After Instruction
R3
00 0000 0000
R3
00 0001 2C00
R5
00 12C0 0000
R5
00 12C0 0000
AR4
80 9908
AR4
80 9908
IR1
4
IR1
4
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809904h
0FFFFFFF4
−12
809904h
0FFFFFFF4 −12
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-142
Parallel LSH3 and STI
Syntax
LSH3
STI
||
LSH3||STI
count, src2, dst1
src3, dst2
Operation
If count ≥ 0:
src2 << count → dst1
Else:
src2 >> |count | → dst1
|| src3 → dst2
Operands
count register (Rn1, 0 ≤ n1 ≤ 7)
src1 indirect (disp = 0, 1, IR0, IR1)
dst1 register (Rn3, 0 ≤ n3 ≤ 7)
src2 register (Rn4, 0 ≤ n4 ≤ 7)
dst2 indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 0 1 1 1 0
Description
dst1
16 15
count
src3
87
dst2
0
src2
The seven LSBs of the count operand are used to generate the 2s-complement shift count.
If the count operand is greater than 0, a copy of the src2 operand is left shifted
by the value of the count operand, and the result is written to the dst1. (The
src2 is not changed.) Low-order bits shifted in are zero filled, and high-order
bits are shifted out through the carry (C) bit.
Logical left shift:
C ← src2 ← 0
If the count operand is less than 0, the src2 operand is right shifted by the absolute value of the count operand. The high-order bits of the dst operand are 0filled as they are shifted to the right. Low-order bits are shifted out through the
C bit.
Assembly Language Instructions
13-143
LSH3||STI Parallel LSH3 and STI
Logical right shift:
0 → src2 → C
If the count operand is 0, no shift is performed, and the carry bit is set to 0.
The count operand is assumed to be a 7-bit signed integer, and the src2 and
dst1 operands are assumed to be unsigned integers. All registers are read at
the beginning and loaded at the end of the execute cycle. This means that
if one of the parallel operations (STI) reads from a register and the operation
being performed in parallel (LSH3) writes to the same register, STI accepts as
input the contents of the register before it is modified by the LSH3.
If src2 and dst2 point to the same location, src2 is read before dst2 is written.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-144
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Set to the value of the last bit shifted out; 0 for a shift count of 0
OVM
Operation is affected by OVM bit value.
Parallel LSH3 and STI
Example 1
LSH3
|| STI
LSH3||STI
R2,*++AR3(1),R0
R4,*−AR5
Before Instruction
After Instruction
R0
00 0000 0000
R0
00 AC00 0000
R2
00 0000 0018
24
R2
00 0000 0018
R4
00 0000 00DC
220
R4
00 0000 00DC 220
AR3
80 98C2
AR3
80 98C3
AR5
80 98A3
AR5
80 98A3
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8098C3h
0AC
8098C3h
0AC
8098A2h
0
8098A2h
0DC 220
24
Data memory
Assembly Language Instructions
13-145
LSH3||STI Parallel LSH3 and STI
Example 2
LSH3
|| STI
R7,*AR2−− (1),R2
R0,*+AR0(1)
Before Instruction
R0
00 0000 012C
R2
00 0000 0000
After Instruction
300
R0
00 0000 012C
R2
00 0002 C000
R7
00 FFFF FFF4
R7
00 FFFF FFF4
AR0
80 98B7
AR0
80 98B7
AR2
80 9863
AR2
80 9862
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
809863h
2C000000
809863h
2C000000
8098B8h
0
8098B8h
12C
−12
300
−12
Data memory
300
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-146
Restore Clock to Regular Speed
Syntax
MAXSPEED
Operation
H1/16 → H1
Operands
None
MAXSPEED
(supported by ’C31, ’C32, ’C31 silicon revision 5.0
or greater, ’C30 silicon revision 7.0 or greater)
Opcode
31
0 0 0
23
16 15
87
0
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
Exits LOPOWER power-down mode (invoked by LOPOWER instruction with
opcode 10800001h). The ’LC31 or ’C32 resumes full-speed operation during
the read phase of the MAXSPEED instruction.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
MAXSPEED
; The processor resumes full-speed operation.
Assembly Language Instructions
13-147
MPYF Multiply Floating-Point Value
Syntax
MPYF src, dst
Operation
dst × src → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
24 23
0 0 0
0 1 0 1 0 0
16 15
G
87
dst
0
src
Description
The product of the dst and src operands is loaded into the dst register. The src
operand is assumed to be a single-precision floating-point number, and the dst
operand is an extended-precision floating-point number.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
MPYF R0,R2
Before Instruction
13-148
After Instruction
R0
07 0C80 0000 1.4050e+02
R0
07 0C80 0000 1.4050e+02
R2
03 4C20 0000 1.27578125e+01
R2
0A 600F 2000 1.79247266e+03
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
MPYF3
Multiply Floating-Point Value, 3-Operand
Syntax
MPYF3 src2, src1, dst
Operation
src1 × src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
dst
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
register (Rn, 0 ≤ n ≤ 7)
Opcode
31
0 0 1
24 23
0 0 1 0 0 1
16 15
T
dst
87
src1
0
src2
Description
The product of the src1 and src2 operands is loaded into the dst register. The
src1 and src2 operands are assumed to be single-precision floating-point
numbers, and the dst operand is an extended-precision floating-point number.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-149
MPYF3
Multiply Floating-Point Value, 3-Operand
Example 1
MPYF3 R0,R7,R1
Before Instruction
Example 2
After Instruction
R0
05 7B40 0000 6.281250e+01 R0
R1
00 0000 0000
R7
07 33C0 0000 1.79750e+02
LUF
0
05 7B40 0000 6.281250e+01
R1
0D 306A 3000 1.12905469e+04
R7
07 33C0 0000 1.79750e+02
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
MPYF3 *+AR2(IR0),R7,R2
or
MPYF3 R7,*+AR2(IR0),R2
Before Instruction
After Instruction
R2
00 0000 0000
R2
0D 09E4 A000 8.82515625e+03
R7
05 7B40 0000 6.281250e+01
R7
05 7B40 0000 6.281250e+01
AR2
80 9800
AR2
80 9800
IR0
12A
IR0
12A
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
80992Ah
70C8000 1.4050e+02
80992Ah
70C8000 1.4050e+02
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-150
Parallel MPYF3 and ADDF3
Syntax
||
MPYF3||ADDF3
MPYF3 srcA, srcB, dst1
ADDF3 srcC, srcD, dst2
Operation
srcA × srcB → dst1
|| srcC + srcD → dst2
Operands
srcA
srcB
srcC
srcD
Any two indirect (disp = 0, 1 IR0, IR1)
Any two register (0 Rn 7)
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0−255, IR0, IR1)
P
parallel addressing modes (0 ≤ P ≤ 3)
Assembly Language Instructions
13-151
MPYF3||ADDF3 Parallel MPYF3 and ADDF3
This instruction’s operands have been augmented in the following
devices:
- ’C31 silicon version 6.0 or greater
- ’C32 silicon version 2.0 or greater
srcA, srcB, srcC, srcD can be one of the following combinations:
Register
(0 Rn 7)
Indirect
(disp = 0, 1, IR0, IR1)
Any CPU Register
2
2
−
2
1
1
2
−
2
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
indirect (disp = 0, 1, IR0, IR1) or any CPU register
P
parallel addressing modes (0 ≤ P ≤ 3)
Version 4.7 or earlier of TMS320 floating-point code-generation tools
P
00
01
10
11
srcA
src4 ×
src3 ×
src1 ×
src3 ×
srcB
src3,
src1,
src2,
src1,
srcD
src1 +
src4 +
src3 +
src2 +
srcC
src2
src2
src4
src4
Version 5.0 or later
P
00
01
13-152
srcA srcB srcD
srcC
src3 × src4, src1 + src2
src3 × src1, src4 + src2
Parallel MPYF3 and ADDF3
MPYF3||ADDF3
src1 × src2, src3 + src4
src3 × src1, src2 + src4
10
11
Opcode
31
24 23
1 0 0 0 0 0
Description
P
d1 d2
16 15
src1
src2
8 7
src3
0
src4
A floating-point multiplication and a floating-point addition are performed in
parallel. All registers are read at the beginning and loaded at the end of the
execute cycle. If one of the parallel operations (MPYF3) reads from a register
and the operation being performed in parallel (ADDF3) writes to the same register, then MPYF3 accepts the contents of the register as input before it is modified by the ADDF3.
Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded as
register. The assignment of the source operands srcA − srcD to the
src1 − src4 fields varies, depending on the combination of addressing modes
used, and the P field is encoded accordingly.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1 (see Note: Cycle Count)
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
0
0
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-153
MPYF3||ADDF3 Parallel MPYF3 and ADDF3
Example
MPYF3
ADDF3
||
*AR5++(1),*−− AR1(IR0),R0
R5,R7,R3
Note: Cycle Count
One cycle if:
- src3 and src4 are in internal memory
- src3 is in internal memory and src4 is in external memory
Two cycles if:
- src3 is in external memory and src4 is in internal memory
- src3 and src4 are in external memory
For more information see Section 8.5, Clocking Memory Accesses, on page
8-24.
Before Instruction
After Instruction
R0
00 0000 0000
R0
04 6718 0000 2.88867188e+01
R3
00 0000 0000 6.281250e+01
R3
08 2020 0000 3.20250e+02
R5
07 33C0 0000
1.79750e+02
R5
07 33C0 0000 1.79750e+02
R7
07 0C80 0000
1.4050e+02
R7
07 0C80 0000 1.4050e+02
AR1
80 98A8
AR1
80 98A4
AR5
80 98C5
AR5
80 98C6
IR0
4
IR0
4
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
8098C5h
8098A4h
13-154
34C0000 1.2750e+01
1110000 2.265625e+00
8098C5h
34C0000 1.2750e+01
8098A4h
1110000 2.265625e+00
Parallel MPYF3 and STF
Syntax
||
MPYF3||STF
MPYF3 src2, src1, dst
STF
src3, dst2
Operation
src1 × src2 → dst1
|| src3 → dst2
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn3, 0 ≤ n3 ≤ 7)
register (Rn4, 0 ≤ n4 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
Description
24 23
0 1 1 1 1
dst1
16 15
src1
src3
8 7
dst2
0
src2
A floating-point multiplication and a floating-point store are performed in parallel. All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (MPYF3) writes to a register and the operation being performed in parallel (STF) reads from the same register, then
STF accepts the contents of the register as input before it is modified by the
MPYF3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Assembly Language Instructions
13-155
MPYF3||STF Parallel MPYF3 and STF
Status Bits
Mode Bit
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; 0 unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
||
MPYF3
STF
*−AR2(1),R7,R0
R3,*AR0−− (IR0)
Before Instruction
After Instruction
R0
00 0000 0000
R0
0D 09E4 A000 8.82515625e+03
R3
08 6B28 0000 4.7031250e+02
R3
08 6B28 0000 4.7031250e+02
R7
05 7B40 0000 6.281250e+01
R7
05 7B40 0000 6.281250e+01
AR0
80 9860
AR0
80 9858
AR2
80 982B
AR2
80 982B
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
80982Ah
809860h
70C8000 1.4050e+02
0
80982Ah
809860h
70C8000
1.4050e+02
86B280000 4.7031250e+02
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-156
Parallel MPYF3 and SUBF3
Syntax
||
MPYF3||SUBF3
MPYF3 srcA, srcB, dst1
SUBF3 srcC, srcD, dst2
Operation
srcA × srcB → dst1
|| srcD − srcC → dst2
Operands
srcA
srcB
srcC
srcD
Any two indirect (disp = 0, 1, IR0, IR1)
Any two register (0 Rn 7)
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
P
parallel addressing modes (0 ≤ P ≤ 3)
Assembly Language Instructions
13-157
MPYF3||ADDF3 Parallel MPYF3 and ADDF3
This instruction’s operands have been augmented in the following
devices:
- ’C31 silicon version 6.0 or greater
- ’C32 silicon version 2.0 or greater
srcA, srcB, srcC, srcD can be one of the following combinations:
Register
(0 Rn 7)
Indirect
(disp = 0, 1, IR0, IR1)
Any CPU Register
2
2
−
2
1
1
2
−
2
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
indirect (disp = 0, 1, IR0, IR1) or any CPU register
P
parallel addressing modes (0 ≤ P ≤ 3)
Version 4.7 or earlier of TMS320 floating-point code-generation tools
P
srcA srcB srcD srcC
00
01
10
11
src4 × src3, src1 − src2
src3 × src1, src4 − src2
src1 × src2, src3 − src4
src3 × src1, src2 − src4
Version 5.0 or later
13-158
P
srcA srcB srcD srcC
00
01
10
11
src3 × src4, src1 − src2
src3 × src1, src4 − src2
src1 × src2, src3 − src4
src3 × src1, src2 − src4
Parallel MPYF3 and SUBF3
MPYF3||SUBF3
Opcode
31
1 0
Description
24 23
0 0 0 1
P
d1 d2 src1
16 15
src2
8 7
src3
0
src4
A floating-point multiplication and a floating-point subtraction are performed
in parallel. All registers are read at the beginning and loaded at the end of the
execute cycle. If one of the parallel operations (MPYF3) reads from a register
and the operation being performed in parallel (SUBF3) writes to the same register, MPYF3 accepts as input the contents of the register before it is modified
by the SUBF3.
Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded register. The assignment of the source operands srcA − srcD to the src1 − src4
fields varies, depending on the combination of addressing modes used, and
the P field is encoded accordingly.
Cycles
1
Note: Cycle Count
One cycle if:
- src3 and src4 are in internal memory
- src3 is in internal memory and src4 is in external memory
Two cycles if:
- src3 is in external memory and src4 is in internal memory
- src3 and src4 are in external memory
For more information see Section 8.5, Clocking Memory Accesses, on page
8-24.
Assembly Language Instructions
13-159
MPYF3||SUBF3 Parallel MPYF3 and SUBF3
Status Bits
Mode Bit
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
0
0
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
||
or
||
MPYF3
SUBF3
R5,*++AR7(IR1),R0
R7,*AR3−− (1),R2
MPYF3
SUBF3
*++AR7(IR1), R5,R0
R7,*AR3−− (1),R2
Before Instruction
After Instruction
R0
00 0000 0000
R0
04 6718 0000 2.88867188e+01
R2
00 0000 0000
R2
05 E300 0000 −3.9250e+01
R5
03 4C00 0000 1.2750e+01
R5
03 4C00 0000
1.2750e+01
R7
07 33C0 0000 1.79750e+02
R7
07 33C0 0000
1.79750e+02
AR3
80 98B2
AR3
80 98B1
AR7
80 9904
AR7
80 990C
IR1
8
IR1
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
13-160
80990Ch
1110000 2.250e+00
80990Ch
1110000 2.250e+00
8098B2h
70C8000 1.4050e+02
8098B2h
70C8000 1.4050e+02
Multiply Integer
Syntax
MPYI src, dst
Operation
dst × src → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
MPYI
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
any CPU register
Opcode
31
0 0 0
Description
24 23
0 1 0 1 0 1
16 15
G
dst
8 7
0
src
The product of the dst and src operands is loaded into the dst register. The src
and dst operands, when read, are assumed to be 24-bit signed integers. The
result is assumed to be a 48-bit signed integer. The output to the dst register
is the 32 LSBs of the result.
Integer overflow occurs when any of the 16 MSBs of the 48-bit result differs
from the MSB of the 32-bit output value.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-161
MPYI Multiply Integer
Example
MPYI R1,R5
Before Instruction
13-162
After Instruction
R1
00 0033 C251 3,392,081
R1
00 0033 C251
3,392,081
R5
00 0078 B600 7,910,912
R5
00 E21D 9600
−501,377,536
LUF
0
LUF
0
LV
0
LV
1
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
1
C
0
C
0
Multiply Integer, 3-Operand
Syntax
MPYI3 src2, src1, dst
Operation
src1 × src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
MPYI3
any CPU register
indirect (disp = 0, 1, IR0, IR1)
any CPU register
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
dst
any CPU register
any CPU register
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
register (Rn, 0 ≤ n ≤ 27)
Opcode
31
0 0 1
Description
24 23
0 0 1 0 1 0
16 15
T
dst
8 7
src1
0
src2
The product of the src1 and src2 operands is loaded into the dst register. The
src1 and src2 operands are assumed to be 24-bit signed integers. The result
is assumed to be a signed 48-bit integer. The output to the dst register is the
32 LSBs of the result.
Integer overflow occurs when any of the 16 MSBs of the 48-bit result differs
from the MSB of the 32-bit output value.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-163
MPYI3 Multiply Integer, 3-Operand
Example 1
MPYI3 *AR4,*−AR1(1),R2
Before Instruction
After Instruction
R2
00 0000 0000
R2
00 0000 94AC
AR1
80 98F3
AR1
80 98F3
AR4
80 9850
AR4
80 9850
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
38,060
Data memory
Example 2
809850h
0AD
173
809850h
0AD
173
8098F2h
0DC
220
8098F2h
0DC
220
MPYI3
*− − AR4(IR0),R2,R7
Before Instruction
R2
00 0000 00C8
R7
AR4
After Instruction
R2
00 0000 00C8
200
00 0000 0000
R7
00 0000 2710
10,000
80 99F8
AR4
80 99F0
200
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8099F0h
32
Data memory
8099F0h
32
50
50
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-164
Parallel MPYI3 and ADDI3
Syntax
||
MPYI3
ADDI3
||
srcA × srcB → dst1
srcD + srcC → dst2
Operation
Operands
srcA
srcB
srcC
srcD
MPYI3||ADDI3
srcA, srcB, dst1
srcC, srcD, dst2
Any two indirect (disp = 0, 1, IR0, IR1)
Any two register (0 Rn 7)
srcA, srcB, srcC, srcD can be one of the following combinations:
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
P
parallel addressing modes (0 ≤ P ≤ 3)
Assembly Language Instructions
13-165
MPYI3||ADDI3 Parallel MPYI3 and ADDI3
This instruction’s operands have been augmented in the following
devices:
- ’C31 silicon version 6.0 or greater
- ’C32 silicon version 2.0 or greater
srcA, srcB, srcC, srcD can be one of the following combinations:
Register
(0 Rn 7)
Indirect
(disp = 0,1,IR0,IR1)
Any CPU Register
2
2
−
2
1
1
2
−
2
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
indirect (disp = 0, 1, IR0, IR1) or any CPU register
P
parallel addressing modes (0 ≤ P ≤ 3)
Version 4.7 or earlier of TMS320 floating-point code-generation tools
P
00
01
10
11
srcA
src4
src3
src1
src3
srcA
src3
src3
src1
src3
×
×
×
×
srcB
src3,
src1,
src2,
src1,
srcD
src1
src4
src4
src2
+
+
+
+
srcC
src2
src2
src4
src4
×
×
×
×
srcB
src4,
src1,
src2,
src1,
srcD
src1
src4
src3
src2
+
+
+
+
srcC
src2
src2
src4
src4
Version 5.0 or later
P
00
01
10
11
13-166
Parallel MPYI3 and ADDI3
MPYI3||ADDI3
Opcode
31
1 0
Description
24 23
0 0 1 0
P d1 d2
16 15
src1
src2
87
src3
0
src4
An integer multiplication and an integer addition are performed in parallel. All
registers are read at the beginning and loaded at the end of the execute cycle.
This means that if one of the parallel operations (MPYI3) reads from a register
and the operation being performed in parallel (ADDI3) writes to the same register, MPYI3 accepts the contents of the register as input before it is modified
by the ADDI3.
Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded as
register. The assignment of the source operands srcA − srcD to the
src1 − src4 fields varies, depending on the combination of addressing modes
used, and the P field is encoded accordingly. To simplify processing when the
order is not significant, the assembler may change the order of operands in
commutative operations.
Cycles
1 (see Note: Cycle Count on page 13−167)
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
0
0
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Example
||
MPYI3
ADDI3
R7,R4,R0
*−AR3,*AR5−−(1),R3
Assembly Language Instructions
13-167
MPYl3||ADDl3 Parallel MPYl3 and ADD13
Before Instruction
After Instruction
R0
00 0000 0000
R0
00 0000 07D0
R3
00 0000 0000
R3
00 0000 0000
R4
00 0000 0064
100
R4
00 0000 0064
100
R7
00 0000 0014
20
R7
00 0000 0014
20
AR3
80 981F
AR3
80 981F
AR5
80 996E
AR5
80 996D
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
2000
Data memory
80981Eh
0FFFFFFCB
−53
80981Eh
0FFFFFFCB
−53
35
53
80996Eh
35
53
80996Eh
Note: Cycle Count
One cycle if:
- src3 and src4 are in internal memory
- src3 is in internal memory and src4 is in external memory
Two cycles if:
- src3 is in external memory and src4 is in internal memory
- src3 and src4 are in external memory
For more information see Section 8.5, Clocking Memory Accesses, on page
8-24.
13-168
Parallel MPYI3 and STI
Syntax
||
MPYI3
STI
||
src1 × src2 → dst1
src3 → dst2
Operation
Operands
src1
src2
dst1
src3
dst2
MPYI3||STI
src2, src1, dst1
src3, dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn3, 0 ≤ n3 ≤ 7)
register (Rn4, 0 ≤ n4 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
Description
24 23
1 0 0 0 0
dst1
16 15
src1
src3
8 7
dst2
0
src2
An integer multiplication and an integer store are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. If
one of the parallel operations (STI) reads from a register and the operation being performed in parallel (MPYI3) writes to the same register, STI accepts as
input the contents of the register before it is modified by the MPYI3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Integer overflow occurs when any of the 16 MSBs of the 48-bit result differ from
the MSB of the 32-bit output value.
Cycles
1
Assembly Language Instructions
13-169
MPYI3||STI Parallel MPYl3 and STI
Status Bits
Mode Bit
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Example
MPYI3
STI
||
*++AR0(1),R5,R7
R2,*−AR3(1)
Before Instruction
After Instruction
R2
00 0000 00DC
220
R2
00 0000 00DC
220
R5
00 0000 0032
50
R5
00 0000 0032
50
10000
R7
00 0000 0000
R7
00 0000 2710
AR0
80 995A
AR0
80 995B
AR3
80 982F
AR3
80 982F
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
80995Bh
0C8
200
80982Eh
ODC
220
Data memory
80995Bh
0C8
80982Eh
0
200
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
13-170
Parallel MPYI3 and SUBI3
Syntax
||
MPYI3||SUBI3
MPYI3 srcA, srcB, dst1
SUBI3 srcC, srcD, dst2
Operation
srcA × srcB → dst1
|| srcD − srcC → dst2
Operands
srcA
srcB
srcC
srcD
Any two indirect (disp = 0, 1, IR0, IR1)
Any two register (0 Rn 7)
srcA, srcB, srcC, srcD can be one of the following combinations:
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
P
parallel addressing modes (0 ≤ P ≤ 3)
Assembly Language Instructions
13-171
MPYI3||SUBI3 Parallel MPYI3 and SUBI3
This instruction’s operands have been augmented in the following
devices:
- ’C31 silicon version 6.0 or greater
- ’C32 silicon version 2.0 or greater
srcA, srcB, srcC, srcD can be one of the following combinations:
Register
(0 Rn 7)
Indirect
(disp = 0, 1, IR0, IR1)
Any CPU Register
2
2
−
2
1
1
2
−
2
dst1
register (d1):
0 = R0
1 = R1
dst2
register (d2):
0 = R2
1 = R3
src1
src2
src3
src4
register (Rn, 0 ≤ n ≤ 7)
register (Rn, 0 ≤ n ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
indirect (disp = 0, 1, IR0, IR1) or any CPU register
P
parallel addressing modes (0 ≤ P ≤ 3)
Version 4.7 or earlier of TMS320 floating-point code-generation tools
P
00
01
10
11
13-172
srcA
src4
src3
src1
src3
×
×
×
×
srcB
src3,
src1,
src2,
src1,
srcD
src1
src4
src4
src2
+
+
+
+
srcC
src2
src2
src4
src4
Parallel MPYI3 and SUBI3
MPYI3||SUBI3
Version 5.0 or later
P
00
01
10
11
srcA
src3
src3
src1
src3
×
×
×
×
srcB
src4,
src1,
src2,
src1,
srcD
src1
src4
src3
src2
+
+
+
+
srcC
src2
src2
src4
src4
Opcode
31
24 23
1 0 0 0 1 1
Description
P
16 15
d1 d2 src1
src2
8 7
src3
0
src4
An integer multiplication and an integer subtraction are performed in parallel.
All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (MPYI3) reads from a register and the
operation being performed in parallel (SUBI3) writes to the same register,
MPYI3 accepts the contents of the register as input before it is modified by the
SUBI3.
Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded as register. The assignment of the source operands srcA − srcD to the src1 − src4
fields varies, depending on the combination of addressing modes used, and the
P field is encoded accordingly. To simplify processing when the order is not significant, the assembler may change the order of operands in commutative operations.
Integer overflow occurs when any of the 16 MSBs of the 48-bit result differs
from the MSB of the 32-bit output value.
Cycles
1 (see Note: Cycle Count on page 13−173)
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
1 if an integer underflow occurs; 0 otherwise
0
0
1 if an integer overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Example
||
MPYI3
SUBI3
R2,*++AR0(1),R0
*AR5−−(IR1),R4,R2
Assembly Language Instructions
13-173
MPYI3||SUBI3 Parallel MPYI3 and SUBI3
or
MPYI3
SUBI3
||
*++AR0(1),R2,R0
*AR5−−(IR1),R4,R2
Before Instruction
R0
00 0000 0000
R2
00 0000 0032
R4
After Instruction
R0
00 0000 1324
50
R2
00 0000 0320
800
00 0000 07D0 2000
R4
00 0000 07D0
2000
AR0
80 98E3
AR0
80 98E4
AR5
80 99FC
AR5
80 99F0
IR1
0C
IR1
0C
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
4900
Z
0
Z
0
V
0
V
0
C
0
C
0
98
8098E4h
62
98
4B0 1200
8099FCh
4B0
1200
Data memory
8098E4h
8099FCh
62
Note: Cycle Count
One cycle if:
- src3 and src4 are in internal memory
- src3 is in internal memory and src4 is in external memory
Two cycles if:
- src3 is in external memory and src4 is in internal memory
- src3 and src4 are in external memory
For more information see Section 8.5, Clocking Memory Accesses, on page
8-24.
13-174
Negative Integer With Borrow
Syntax
NEGB src, dst
Operation
0 − src − C → dst
Operands
src general addressing modes (G):
00
01
10
11
dst
NEGB
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
any CPU register
Opcode
31
24 23
0 0 0 0 1 0 1 1 0
16 15
8 7
dst
G
0
src
Description
The difference of the 0, src, and C operands is loaded into the dst register. The
dst and src are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
NEGB R5,R7
Before Instruction
After Instruction
R5
00 FFFF FFCB
R5
00 FFFF FFCB
−53
R7
00 0000 0000
R7
00 0000 0034
52
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
1
C
1
−53
Assembly Language Instructions
13-175
NEGF Negate Floating-Point Value
Syntax
NEGF src, dst
Operation
0 − src → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 7)
Opcode
31
0 0 0
24 23
0 1 0 1 1 1
16 15
G
dst
8 7
0
src
Description
The difference of the 0 and src operands is loaded into the dst register. The
dst and src operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-176
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Negate Floating-Point Value
Example
NEGF
NEGF *++AR3(2),R1
Before Instruction
R1
AR3
After Instruction
05 7B40 0025 6.28125006e+01
R1
07 F380 0000 −1.4050e+02
80 9800
AR3
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
80 9802
V
0
V
0
C
0
C
0
809802h
70C8000
Data memory
809802h
70C8000 1.4050e+02
Assembly Language Instructions
1.4050e+02
13-177
NEGF||STF Parallel NEGF and STF
Syntax
||
NEGF src2, dst1
STF
src3, dst2
||
0 − src2 → dst1
src3 → dst2
Operation
Operands
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
Description
24 23
1 0 0 0 1
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
A floating-point negation and a floating-point store are performed in parallel.
All registers are read at the beginning and loaded at the end of the execute
cycle. This means that if one of the parallel operations (STF) reads from a register and the operation being performed in parallel (NEGF) writes to the same
register, STF accepts the contents of the register as input before it is modified
by the NEGF.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-178
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Parallel NEGF and STF
Example
||
NEGF
STF
NEGF||STF
*AR4−−(1),R7
R2,*++AR5(1)
Before Instruction
After Instruction
R2
07 33C0 0000 1.79750e+02
R2
07 33C0 0000
R7
00 0000 0000
R7
05 84C0 0000 −6.281250e+01
1.79750e+02
AR4
80 98E1
AR4
80 98E0
AR5
80 9803
AR5
80 9804
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8098E1h
57B4000
6.281250e+01
809804h
733C000
1.79750e+02
Data memory
8098E1h
809804h
57B400000 6.281250e+01
0
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-179
NEGI Negate Integer
Syntax
NEGI src, dst
Operation
0 − src → dst
Operands
src general addressing modes (G):
00
01
10
11
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst any CPU register
Opcode
31
24 23
0 0 0 0 1 1 0 0 0
16 15
G
8 7
dst
0
src
Description
The difference of the 0 and src operands is loaded into the dst register. The
dst and src operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
NEGI 174,R5
(174 = 0AEh)
Before Instruction
R5
13-180
00 0000 00DC 220
After Instruction
R5
00 FFFF FF52 −174
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
1
Parallel NEGI and STI
Syntax
||
NEGI
STI
||
0 − src2 → dst1
src3 → dst2
Operation
Operands
src2
dst1
src3
dst2
NEGI||STI
src2, dst1
src3, dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
Description
24 23
1 0 0 1 0
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
An integer negation and an integer store are performed in parallel. All registers
are read at the beginning and loaded at the end of the execute cycle. If one
of the parallel operations (STI) reads from a register and the operation being
performed in parallel (NEGI) writes to the same register, STI accepts the contents of the register as input before it is modified by the NEGI.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-181
NEGI||STI Parallel NEGI and STI
Example
NEGI
STI
||
*−AR3,R2
R2,*AR1++
Before Instruction
After Instruction
R2
00 0000 0019
R2
00 FFFF FF24
AR1
80 98A5
AR1
80 98A6
AR3
80 982F
AR3
80 982F
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
25
Z
0
Z
0
V
0
V
0
C
0
C
1
80982Eh
0DC
8098A5h
19
−220
Data memory
80982Eh
0DC
8098A5h
0
220
220
25
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
13-182
No Operation
Syntax
NOP src
Operation
No ALU or multiplier operations.
ARn is modified if src is specified in indirect mode.
Operands
src general addressing modes (G):
00
10
NOP
register(no operation)
indirect (modify ARn, 0 ≤ n ≤ 7)
(disp = 0−255, IR0, IR1)
Opcode
31
0 0 0
24 23
0 1 1 0 0 1
16 15
G
8 7
0
src
0 0 0 0 0
Description
If the src operand is specified in the indirect mode, the specified addressing
operation is performed, and a dummy memory read occurs. If the src operand
is omitted, no operation is performed.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example 1
NOP
Before Instruction
PC
Example 2
NOP
3A
After Instruction
PC
3B
*AR3−− (1)
Before Instruction
After Instruction
AR3
80 9900
AR3
80 98FF
PC
5
PC
6
Assembly Language Instructions
13-183
NORM
Normalize
Syntax
NORM src, dst
Operation
norm (src) → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
Opcode
31
0 0 0
Description
24 23
0 1 1 0 1 0
16 15
G
dst
8 7
0
src
The src operand is assumed to be an unnormalized floating-point number; that
is, the implied bit is set equal to the sign bit. The dst is set equal to the normalized src operand with the implied bit removed. The dst operand exponent is
set to the src operand exponent minus the size of the left shift necessary to
normalize the src. The dst operand is assumed to be a normalized floatingpoint number.
If src (exp) = −128 and src (man) = 0, then dst = 0, Z = 1, and UF = 0.
If src (exp) = −128 and src (man) ≠ 0, then dst = 0, Z = 0, and UF = 1.
For all other cases of the src, if a floating-point underflow occurs, then
dst (man) is forced to 0 and dst (exp) = −128.
If src (man) = 0, then dst (man) = 0 and dst (exp) = −128.
Refer to Section 5.7, Normalization Using the NORM Instruction, on page 5-37
for more information.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-184
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
Unaffected
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Normalize
Example
NORM
NORM R1,R2
Before Instruction
After Instruction
R1
04 0000 3AF5
R1
04 0000 3AF5
R2
07 0C80 0000
R2
F2 6BD4 0000 1.12451613e − 04
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Assembly Language Instructions
13-185
NOT
Bitwise-Logical Complement
Syntax
NOT src, dst
Operation
∼src → dst
Operands
src general addressing modes (G):
00
01
10
11
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst any CPU register
Opcode
31
0 0 0
24 23
0 1 1 0 1 1
16 15
G
dst
8 7
0
src
Description
The bitwise-logical complement of the src operand is loaded into the dst register. The complement is formed by a logical NOT of each bit of the src operand.
The dst and src operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-186
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is affected by OVM bit value.
Bitwise-Logical Complement
Example
NOT
NOT @982Ch,R4
Before Instruction
After Instruction
R4
00 0000 0000
R4
00 FFFF A1D0
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
0
5E2F
80982Ch
5E2F
Data memory
80982Ch
Assembly Language Instructions
13-187
NOT||STI Parallel NOT and STI
Syntax
NOT
STI
||
src2, dst1
src3, dst2
Operation
∼src2 → dst1
|| src3 → dst2
Operands
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src2
dst1
src3
dst2
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn1, 0 ≤ n1 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
24 23
1 1 1 0 0 1 1
Description
dst1
16 15
0 0 0
src3
8 7
dst2
0
src2
A bitwise-logical NOT and an integer store are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. This
means that if one of the parallel operations (STI) reads from a register and the
operation being performed in parallel (NOT) writes to the same register, STI
accepts the contents of the register as input before it is modified by the NOT.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-188
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
NOT||STI
Parallel NOT and STI
Example
NOT
STI
||
*+AR2,R3
R7,*−−AR4 (IR1)
Before Instruction
R3
00 0000 0000
R7
00 0000 00DC
AR2
AR4
After Instruction
R3
00 FFFF F3D0
R7
00 0000 00DC
80 99CB
AR2
80 99CB
80 9850
AR4
80 9840
IR1
10
IR1
10
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
0
8099CCh
0C2F
8099CCh
0C2F
809840h
0
809840h
0DC
220
220
Data memory
220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-189
OR Bitwise-Logical OR
Syntax
OR src, dst
Operation
dst OR src → dst
Operands
src general addressing modes (G):
00
01
10
11
any CPU register
direct
indirect (disp = 0−255, IR0, IR1)
immediate (not sign-extended)
dst any CPU register
Opcode
31
0 0 0
24 23
1 0 0 0 0 0
16 15
G
dst
8 7
0
src
Description
The bitwise-logical OR between the src and dst operands is loaded into the dst
register. The dst and src operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-190
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Bitwise-Logical OR
Example
OR
OR *++AR1(IR1),R2
Before Instruction
After Instruction
R2
00 1256 0000
R2
00 1256 2BCD
AR1
80 9800
AR1
80 9804
IR1
4
IR1
4
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
2BCD
809804h
2BCD
Data memory
809804h
Assembly Language Instructions
13-191
OR3
Bitwise-Logical OR, 3-Operand
Syntax
OR3 src2, src1, dst
Operation
src1 OR src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 27)
register (Rn2, 0 ≤ n2 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
0 0 1
24 23
0 0 1 0 1 1
16 15
T
dst
8 7
src1
0
src2
Description
The bitwise-logical OR between the src1 and src2 operands is loaded into the
dst register. The src1, src2, and dst operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-192
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Bitwise-Logical OR, 3-Operand
Example
OR3
OR3 *++AR1(IR1),R2,R7
Before Instruction
After Instruction
R2
00 1256 0000
R2
00 1256 0000
R7
00 0000 0000
R7
0 1256 2BCD
AR1
80 9800
AR1
80 9804
IR1
4
IR1
4
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
2BCD
809804h
2BCD
Data memory
809804h
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-193
OR3||STI Parallel OR3 and STI
Syntax
OR3 src2, src1, dst1
STI src3, dst2
||
src1 OR src2 → dst1
src3 → dst2
Operation
|
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
24 23
1 0 1 0 0
dst1
16 15
src1
src3
8 7
dst2
0
src2
A bitwise-logical OR and an integer store are performed in parallel. All registers
are read at the beginning and loaded at the end of the execute cycle. This
means that if one of the parallel operations (STI) reads from a register and the
operation being performed in parallel (OR3) writes to the same register, then STI
accepts the contents of the register as input before it is modified by the OR3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
13-194
1
Parallel OR3 and STI
Status Bits
Mode Bit
OR3||STI
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 result is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
||
OR3
STI
*++AR2,R5,R2
R6,*AR1−−
Before Instruction
R2
00 0000 0000
R5
00 0080 0000
R6
00 0000 00DC
AR1
AR2
After Instruction
R2
00 0080 9800
R5
00 0080 0000
R6
00 0000 00DC
80 9883
AR1
80 9882
80 9830
AR2
80 9831
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
809831h
9800
809831h
9800
809883h
0
809883h
0DC
220
220
Data memory
220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-195
POP Pop Integer
Syntax
POP dst
Operation
*SP−− → dst
Operands
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
0 0 0
24 23
0 1 1 1 0 0
16 15
01
dst
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
The top of the current system stack is popped and loaded into the dst register
(32 LSBs). The top of the stack is assumed to be a signed integer. The POP
is performed with a postdecrement of the stack pointer. The exponent bits of
an extended-precision register (R7−R0) are left unmodified.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
POP
R3
Before Instruction
After Instruction
R3
00 0000 12DA
SP
809856
SP
809855
LUF
0
LUF
0
4,826
R3
00 FFFF 0DA4 −62,044
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
0
809856h
FFFF0DA4
Data memory
809856h
13-196
FFFF0DA4 −62,044
−62,044
Pop Floating-Point Value
Syntax
POPF dst
Operation
*SP−− → dst1
Operands
dst register (Rn, 0 ≤ n ≤ 7)
POPF
Opcode
31
24 23
0 0 0
0 1 1 1 0 1 0 1
16 15
dst
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
The top of the current system stack (32 MSBs) is popped and loaded into the
dst register. The top of the stack is assumed to be a floating-point number. The
POP is performed with a postdecrement of the stack pointer. The eight LSBs
of an extended-precision register (R7−R0) are zero-filled.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
UF
LV
N
Z
V
C
Unaffected
0
Unaffected
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
0
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
POPF R4
Before Instruction
R4
02 5D2E 0123 6.91186578e+00
After Instruction
R4
5F 2C13 0200
SP
80984A
SP
809849
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
80984Ah
5F2C1302
5.32544007e+28
Data memory
80984Ah
5F2C1302 5.32544007e+28
5.32544007e+28
Assembly Language Instructions
13-197
PUSH PUSH Integer
Syntax
PUSH src
Operation
src → *++SP
Operands
src register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0
16 15
0 1 1 1 1 0 0 1
src
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
The contents of the src register (32 LSBs) are pushed on the current system
stack. The src is assumed to be a signed integer. The PUSH is performed with
a preincrement of the stack pointer. The integer or mantissa portion of an extended-precision register (R7−R0) is saved with this instruction.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
PUSH R6
Before Instruction
R6
After Instruction
02 5C12 8081 633,415,688 R6
02 5C12 8081
SP
8098AE
SP
8098AF
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
633,415,688
Data memory
8098AFh
13-198
0 −62,044 8098AFh
5C128081 1,544,716,417
PUSH Floating-Point Value
Syntax
PUSHF src
Operation
src → *++SP
Operands
src register (Rn, 0 ≤ n ≤ 7)
PUSHF
Opcode
31
24 23
0 0 0
0 1 1 1 1 1 0 1
16 15
src
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
The contents of the src register (32 MSBs) are pushed on the current system
stack. The src is assumed to be a floating-point number. The PUSH is performed with a preincrement of the stack pointer. The eight LSBs of the mantissa are not saved. (Note the difference in R2 and the value on the stack in the
example below.)
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
PUSHF
R2
Before Instruction
R2
After Instruction
R2
02 5C12 8081
SP
809801
SP
809802
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
02 5C12 8081 6.87725854e+00
V
0
V
0
C
0
C
0
0
809802h
025C1280
6.87725854e+00
Data memory
809802h
6.87725830e+00
Assembly Language Instructions
13-199
RETIcond
Return From Interrupt Conditionally
Syntax
RETIcond
Operation
If cond is true:
*SP − − → PC
1 → ST (GIE).
Else, continue.
Operands
None
Opcode
31
24 23
0 1 1 1 1
Description
0 0 0 0 0 0
16 15
cond
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A conditional return is performed. If the condition is true, the top of the stack
is popped to the PC, and a 1 is written to the global interrupt enable (GIE) bit
of the status register. This has the effect of enabling all interrupts for which the
corresponding interrupt enable bit is a 1.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7−R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
13-200
Return From Interrupt Conditionally
Example
RETIcond
RETINZ
Before Instruction
After Instruction
PC
0456
PC
0123
SP
809830
SP
80982F
ST
0
ST
2000
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
123
809830h
123
Data memory
809830h
Assembly Language Instructions
13-201
RETScond
Return From Subroutine Conditionally
Syntax
RETScond
Operation
If cond is true:
*SP− − → PC.
Else, continue.
Operands
None
Opcode
31
24 23
0 1 1 1 1
Description
0 0 0 1 0 0
16 15
cond
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A conditional return is performed. If the condition is true, the top of the stack
is popped to the PC.
The ’C3x provides 20 condition codes that you can use with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7−R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
13-202
Return From Subroutine Conditionally
Example
RETScond
RETSGE
Before Instruction
After Instruction
PC
0123
PC
0456
SP
80983C
SP
80983B
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
456
80983Ch
456
Data memory
80983Ch
Assembly Language Instructions
13-203
RND Round Floating-Point Value
Syntax
RND src, dst
Operation
rnd(src) → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 7)
Opcode
31
0 0 0
24 23
1 0 0 0 1 0
16 15
G
dst
8 7
0
src
Description
The result of rounding the src operand is loaded into the dst register.The src
operand is rounded to the nearest single-precision floating-point value. If the
src operand is exactly halfway between two single-precision values, it is
rounded to the most positive value.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
Mode Bit
13-204
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs or the src operand is 0;
0 otherwise
1 if a negative result is generated; 0 otherwise
Unaffected
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is affected by OVM bit value.
Round Floating-Point Value
Example
RND
RND R5,R2
Before Instruction
After Instruction
R2
00 0000 0000
R2
07 33C1 6F00 1.79755600e+02
R5
07 33C1 6EEF 1.79755599e+02
R5
07 33C1 6EEF 1.79755599e+02
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Note: BZUF Instruction
If a BZ instruction is executed immediately following an RND instruction with
a 0 operand, the branch is not performed because the zero flag is not set.
To circumvent this problem, execute a BZUF instruction instead of a BZ
instruction.
Assembly Language Instructions
13-205
ROL
Rotate Left
Syntax
ROL dst
Operation
dst left-rotated 1 bit → dst
Operands
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
1 0 0 0 1 1 1 1
0 0 0
Description
16 15
dst
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
The contents of the dst operand are left rotated one bit and loaded into the dst
register. This is a circular rotation, with the MSB simultaneously transferred
into the carry (C) bit and the LSB.
Rotate left:
C
dst
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Set to the value of the bit rotated out of the high-order bit; unaffected
if dst is not R7 − R0
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
ROL R3
Before Instruction
13-206
After Instruction
R3
00 8002 5CD4
R3
00 0004 B9A9
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
1
Rotate Left Through Carry
Syntax
ROLC dst
Operation
dst left-rotated one bit through carry bit → dst
Operands
dst register (Rn, 0 ≤ n ≤ 27)
ROLC
Opcode
31
24 23
0 0 0 1 0 0 1 0 0 1 1
Description
16 15
dst
8 7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
The contents of the dst operand are left rotated one bit through the carry (C)
bit and loaded into the dst register. The MSB is rotated to the carry bit at the
same time the carry bit is transferred to the LSB.
Rotate left through carry bit:
C
dst
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7− R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Set to the value of the bit rotated out of the high-order bit; if dst is not
R7−R0, then C is shifted into the dst but not changed
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example 1
ROLC R3
Before Instruction
After Instruction
R3
00 0000 0420
R3
00 0000 0841
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
1
C
0
Assembly Language Instructions
13-207
ROLC
Rotate Left Through Carry
Example 2
ROLC R3
Before Instruction
13-208
After Instruction
R3
00 8000 4281
R3
00 0000 8502
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
1
Rotate Right
Syntax
ROR dst
Operation
dst right-rotated one bit through carry bit → dst
Operands
dst register (Rn, 0 ≤ n ≤ 27)
ROR
Opcode
31
24 23
1 0 0 1 0 1 1 1
0 0 0
Description
16 15
dst
8 7
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The contents of the dst operand are right rotated one bit and loaded into the
dst register. The LSB is rotated into the carry (C) bit and also transferred into
the MSB.
Rotate right:
dst
C
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7− R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Set to the value of the bit rotated out of the high-order bit; unaffected
if dst is not R7−R0
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
ROR R7
Before Instruction
After Instruction
R7
00 0000 0421
R7
00 8000 0210
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
1
Assembly Language Instructions
13-209
RORC Rotate Right Through Carry
Syntax
RORC dst
Operation
dst right-rotated one bit through carry bit → dst
Operands
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0
Description
16 15
1 0 0 1 1 0 1 1
dst
8 7
1 1 1 1
0
1 1 1 1 1 1 1 1 1 1 1 1
The contents of the dst operand are right rotated one bit through the status register’s carry (C) bit. This could be viewed as a 33-bit shift. The carry bit value
is rotated into the MSB of the dst, while at the same time the dst LSB is rotated
into the carry bit.
Rotate right through carry bit:
C
dst
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Set to the value of the bit rotated out of the high-order bit; if dst is not
R7 − R0, then C is shifted in but not changed
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
RORC R4
Before Instruction
13-210
After Instruction
R4
00 8000 0081
R4
00 4000 0040
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
1
N
0
Z
0
Z
0
V
0
V
0
C
0
C
1
Repeat Block
Syntax
RPTB src
Operation
src → RE
1 → ST (RM)
Next PC → RS
Operands
src long-immediate addressing mode
RPTB
Opcode
31
24 23
0 1 1 0 0 1 0 0
Description
16 15
8 7
0
src
RPTB allows a block of instructions to be repeated RC register + 1 times without any penalty for looping. This instruction activates the block repeat mode
of updating the PC. The src operand is a 24-bit unsigned immediate value that
is loaded into the repeat end-address (RE) register. A 1 is written into the repeat mode bit of status register ST (RM) to indicate that the PC is being updated in the repeat mode. The address of the next instruction is loaded into the
repeat start-address (RS) register.
RE should be greater than or equal to RS (RE RS). Otherwise, the code
does not repeat, even though the RM bit remains set to 1.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-211
RPTB Repeat Block
Example
RPTB
127h
Before Instruction
After Instruction
PC
0123
PC
0124
RE
0
RE
127
RS
0
RS
124
ST
0
ST
100
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Because the block-repeat modes modify the program counter, no
other instruction can modify the program counter at the same time.
The following two rules apply:
Rule 1: The last instruction in the block (or the only instruction in a
block of size 1) cannot be a Bcond, BR, DBcond, CALL,
CALLcond, TRAPcond, RETIcond, RETScond, IDLE, IDLE2,
RPTB, or RPTS. Example 7−3 on page 7-6 shows an
incorrectly placed standard branch.
Rule 2: None of the last four instructions at the bottom of the block
(or the only instruction in a block of size 1) can be a
BcondD, BRD, or DBcondD. Example 7−4 on page 7-7
shows an incorrectly placed delayed branch.
If either rule is violated, the PC will be undefined.
13-212
Repeat Single Instruction
Syntax
RPTS src
Operation
src → RC
1 → ST (RM)
1→S
Next PC → RS
Next PC → RE
Operands
src general addressing modes (G):
00
01
10
11
RPTS
register
direct
indirect (disp = 0−255, IR0, IR1)
immediate
Opcode
31
0 0 0
Description
24 23
1 0 0 1 1 1
16 15
G
1 1 0 1 1
8 7
0
src
The RPTS instruction allows you to repeat a single instruction src + 1 times
without any penalty for looping. Fetches can also be made from the instruction
register (IR), thus avoiding repeated memory access.
The src operand is loaded into the repeat counter (RC). A 1 is written into the
repeat mode bit of the status register ST (RM). A 1 is also written into the repeat single bit (S). This indicates that the program fetches are to be performed
only from the instruction register. The next PC is loaded into the repeat end-address (RE) register and the repeat start-address (RS) register.
For the immediate mode, the src operand is assumed to be an unsigned integer and is not sign extended.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-213
RPTS Repeat Single Instruction
Example
RPTS AR5
Before Instruction
After Instruction
AR5
00 00FF
AR5
00 00FF
PC
0123
PC
0124
RC
0
RC
0FF
RE
0
RE
124
RS
0
RS
124
ST
0
ST
100
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Because the block-repeat modes modify the program counter, no
other instruction can modify the program counter at the same time.
Therefore, the repeated instruction cannot be a Bcond, BR,
DBcond, CALL, CALLcond, TRAPcond, RETIcond, RETScond,
IDLE, IDLE2, RPTB, or RPTS. If this rule is violated, the PC will be
undefined.
Note:
The RPTS instruction cannot be interrupted because instruction fetches are
halted.
13-214
Signal, Interlocked
Syntax
SIGI
Operation
Signal interlocked operation.
Wait for interlock acknowledge.
Clear interlock.
Operands
None
SIGI
Opcode
31
0 0 0
24 23
16 15
8 7
0
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
An interlocked operation is signaled over XF0 and XF1. After the interlocked
operation is acknowledged, the interlocked operation ends. SIGI ignores the
external ready signals. Refer to Section 7.4, Interlocked Operations, on page
7-13 for detailed information.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
SIGI
; The processor sets XF0 to 0, idles
; until XF1 is set to 0, and then
; sets XF0 to 1.
Assembly Language Instructions
13-215
STF
Store Floating-Point Value
Syntax
STF src, dst
Operation
src → dst
Operands
src register (Rn, 0 ≤ n ≤ 7)
dst general addressing modes (G):
01
10
direct
indirect (disp = 0−255, IR0, IR1)
Opcode
31
24 23
0 0 0
1 0 1 0 0 0
16 15
G
8 7
src
0
dst
Description
The src register is loaded into the dst memory location. The src and dst operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
STF R2,@98A1h
Before Instruction
R2
05 2C50 1900
After Instruction
4.30782204e+01
R2
05 2C50 1900 4.30782204e+01
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
0
8098A1h
Data memory
8098A1h
13-216
52C5019 4.30782204e+01
Store Floating-Point Value, Interlocked
Syntax
STFI src, dst
Operation
src → dst
Signal end of interlocked operation.
Operands
src register (Rn, 0 ≤ n ≤ 7)
STFI
dst general addressing modes (G):
01
10
direct
indirect (disp = 0−255, IR0, IR1)
Opcode
31
24 23
0 0 0
1 0 1
0 0 1
16 15
8 7
src
G
0
dst
Description
The src register is loaded into the dst memory location. An interlocked operation is signaled over pins XF0 and XF1. The src and dst operands are assumed
to be floating-point numbers. Refer to Section 7.4, Interlocked Operations, on
page 7-13 for detailed information.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
STFI
R3,*−AR4
Before Instruction
R3
After Instruction
R3
07 33C0 0000
80 993C
AR4
80 993C
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
AR4
07 33C0 0000 1.79750e+02
Z
0
Z
0
V
0
V
0
C
0
C
0
0
80993Bh
733C000
1.79750e+02
Data memory
80993Bh
1.79750e+02
Assembly Language Instructions
13-217
STFI
Store Floating-Point Value, Interlocked
Note:
The STFI instruction is not interruptible because it completes when ready is
signaled. See Section 7.4, Interlocked Operations, on page 7-13.
13-218
Parallel Store Floating-Point Value
Syntax
||
STF
STF
STF||STF
src2, dst2
src1, dst1
Operation
src2 → dst2
|| src1 → dst1
Operands
src1
dst1
src2
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented on the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
dst1
src2
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
Opcode
31
24 23
1 1 0 0 0 0 0
src2
16 15
0 0 0
src1
8 7
dst1
0
dst2
Description
Two STF instructions are executed in parallel. Both src1 and src2 are assumed
to be floating-point numbers.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-219
STF||STF
Parallel Store Floating-Point Value
Example
||
R4,*AR3−−
R3,*++AR5
STF
STF
Before Instruction
After Instruction
R3
07 33C0 0000 1.79750e+02
R4
07 0C80 0000
1.4050e+02
R3
07 33C0 0000 1.79750e+02
R4
07 0C80 0000 1.4050e+02
AR3
80 9835
AR3
80 9834
AR5
80 99D2
AR5
80 99D3
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809835h
0
809835h
070C8000 1.4050e+02
8099D3h
0
8099D3h
0733C000
1.79750e+02
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
13-220
STI
Store Integer
Syntax
STI src, dst
Operation
src → dst
Operands
src register (Rn, 0 ≤ n ≤ 27)
dst general addressing modes (G):
01
10
direct
indirect (disp = 0−255, IR0, IR1)
Opcode
31
24 23
16 15
G
0 0 0 1 0 1 0 1 0
8 7
0
dst
src
Description
The src register is loaded into the dst memory location. The src and dst operands are assumed to be signed integers.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
STI R4,@982Bh
Before Instruction
After Instruction
R4
00 0004 2BD7 273,367
R4
00 0004 2BD7 273,367
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
80982Bh
42BD7
Data memory
80982Bh
0E5FC
58,876
273,367
Assembly Language Instructions
13-221
STII
Store Integer, Interlocked
Syntax
STII src, dst
Operation
src → dst
Signal end of interlocked operation
Operands
src register (Rn, 0 ≤ n ≤ 27)
dst general addressing modes (G):
01
direct
10
indirect (disp = 0−255, IR0, IR1)
Opcode
31
24 23
0 0 0 1 0 1 0 1 1
16 15
G
87
0
dst
src
Description
The src register is loaded into the dst memory location. An interlocked operation is signaled over pins XF0 and XF1. The src and dst operands are assumed
to be signed integers. Refer to Section 7.4, Interlocked Operations, on page
7-13 for detailed information.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
STII
R1,@98AEh
Before Instruction
After Instruction
R1
00 0000 078D
R1
00 0000 078D
DP
080
DP
080
25C
8098AEh
78D
Data memory
8098AEh
Note:
The STII instruction is not interruptible because it completes when ready is
signaled. See Section 7.4, Interlocked Operations, on page 7-13.
13-222
Parallel STI and STI
Syntax
||
STI
STI
STI||STI
src2, dst2
src1, dst1
Operation
src2 → dst2
|| src1 → dst1
Operands
src1
dst1
src2
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented on the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
dst1
src2
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
Opcode
31
24 23
1 1 0 0 0 0 1
src2
16 15
0 0 0
src1
8 7
dst1
0
dst2
Description
Two integer stores are performed in parallel. If both stores are executed to the
same address, the value written is that of STI src2, dst2.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-223
STI||STI Parallel STI and STI
Example
||
STI R0,*++AR2(IR0)
STI R5,*AR0
Before Instruction
After Instruction
R0
00 0000 00DC
220
53
R0
00 0000 00DC
220
53
R5
00 0000 0035
R5
00 0000 0035
AR0
80 98D3
AR0
80 98D3
AR2
80 9830
AR2
80 9838
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
809838h
0
809838h
0DC
220
8098D3h
0
8098D3h
35
53
Data memory
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
13-224
Subtract Integer With Borrow
Syntax
SUBB src, dst
Operation
dst − src − C → dst
Operands
src general addressing modes (G):
00
01
10
11
SUBB
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0
1 0 1 1 0 1
16 15
8 7
dst
G
0
src
Description
The difference of the dst, src, and C operands is loaded into the dst register.
The dst and src operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
SUBB *AR5++(4),R5
Before Instruction
R5
00 0000 00FA
AR5
After Instruction
R5
00 0000 0032
80 9800
AR5
80 9804
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
250
Z
0
Z
0
V
0
V
0
C
1
C
0
809800h
0C7
50
Data memory
809800h
0C7
199
199
Assembly Language Instructions
13-225
SUBB3 Subtract Integer With Borrow, 3-Operand
Syntax
SUBB3 src2, src1, dst
Operation
src1 − src2 − C → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 27)
register (Rn2, 0 ≤ n2 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
0 0 1
24 23
0 0 1 1 0 0
16 15
T
dst
8 7
src1
0
src2
Description
The difference among the src1 and src2 operands and the C flag is loaded into
the dst register. The src1, src2, and dst operands are assumed to be signed
integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-226
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Subtract Integer With Borrow, 3-Operand
Example
SUBB3
SUBB3 R5,*AR5++(IR0),R0
Before Instruction
R0
00 0000 0000
After Instruction
R0
00 0000 0032
50
199
R5
00 0000 00C7
R5
00 0000 00C7
AR5
80 9800
AR5
80 9804
IR0
4
IR0
4
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
1
C
0
809800h
0FA
199
Data memory
809800h
0FA
250
250
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-227
SUBC Subtract Integer Conditionally
Syntax
SUBC src, dst
Operation
If (dst − src ≥ 0):
(dst − src << 1) OR 1 → dst
Else:
dst << 1 → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
0 0 0
Description
24 23
1 0 1 1 1 0
16 15
G
dst
8 7
0
src
The src operand is subtracted from the dst operand. The dst operand is loaded
with a value dependent on the result of the subtraction. If (dst − src) is greater
than or equal to 0, then (dst − src) is left-shifted one bit, the least significant
bit is set to 1, and the result is loaded into the dst register. If (dst − src) is less
than 0, dst is left-shifted one bit and loaded into the dst register. The dst and
src operands are assumed to be unsigned integers.
You can use SUBC to perform a single step of a multi-bit integer division. See
the TMS320C3x General Purpose Applications Guide for a detailed description.
Cycles
1
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
13-228
Subtract Integer Conditionally
Example 1
SUBC
SUBC
@98C5h,R1
Before Instruction
R1
00 0000 04F6
DP
After Instruction
R1
00 0000 00C9
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
1270
Z
0
Z
0
V
0
V
0
C
0
C
0
8098C5h
492
201
Data memory
8098C5h
Example 2
492
SUBC 3000,R0
1170
1170
(3000 = 0BB8h)
Before Instruction
R0
00 0000 07D0
LUF
After Instruction
R0
00 0000 0FA0
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
2000
Z
0
Z
0
V
0
V
0
C
0
C
0
4000
Assembly Language Instructions
13-229
SUBF Subtract Floating-Point Value
Syntax
SUBF src, dst
Operation
dst − src → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 7)
Opcode
31
24 23
0 0 0 1 0 1 1 1 1
16 15
G
dst
8 7
0
src
Description
The difference between the dst operand and the src operand is loaded into the
dst register. The dst and src operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-230
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Subtract Floating-Point Value
Example
SUBF
*AR0−− (IR0),R5
Before Instruction
R5
SUBF
After Instruction
07 33C0 0000 1.79750000e+02
AR0
80 9888
R5
05 1D00 0000 3.9250e+01
AR0
80 9808
IR0
80
IR0
80
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
809888h
70C8000
Data memory
809888h
70C8000
1.4050e+02
1.4050e+02
Assembly Language Instructions
13-231
SUBF3 Subtract Floating-Point Value, 3-Operand
Syntax
SUBF3 src2, src1, dst
Operation
src1 − src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn2, 0 ≤ n2 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
dst register (Rn, 0 ≤ n ≤ 7)
Opcode
31
0 0 1
24 23
0 0 1 1 0 1
16 15
T
dst
8 7
src1
0
src2
Description
The difference between the src1 and src2 operands is loaded into the dst register. The src1, src2, and dst operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-232
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Subtract Floating-Point Value, 3-Operand
Example 1
SUBF3
SUBF3
*AR0−− (IR0),*AR1,R4
Before Instruction
After Instruction
R4
00 0000 0000
R4
05 1D00 0000
AR0
80 9888
AR0
80 9808
AR1
80 9851
AR1
80 9851
IR0
80
IR0
80
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
3.9250e+01
Data memory
809888h
70C8000 1.4050e+02
809888h
70C8000
1.4050e+02
809851h
733C000
809851h
733C000
1.79750e+02
Example 2
SUBF3
1.79750e+02
R7,R0,R6
Before Instruction
After Instruction
R0
03 4C20 0000 1.27578125e+01
R0
03 4C20 0000 1.27578125e+01
R6
00 0000 0000
R6
05 B7C8 0000 −5.00546875e+01
R7
05 7B40 0000 6.281250e+01
R7
05 7B40 0000 6.281250e+01
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
1
V
0
V
0
C
0
C
0
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-233
SUBF3||STF Parallel SUBF3 and STF
Syntax
||
SUBF3 src1, src2, dst1
STF
src3, dst2
Operation
src2 − src1 → dst1
|| src3 → dst2
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
Description
24 23
1 0 1 0 1
dst1
16 15
src1
src3
8 7
dst2
0
src2
A floating-point subtraction and a floating-point store are performed in parallel.
All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (STF) reads from a register and the operation being performed in parallel (SUBF3) writes to the same register, STF accepts the contents of the register as input before it is modified by the SUBF3.
If src3 and dst1 point to the same location, src3 is read before the write to dst1.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-234
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
OVM
Operation is not affected by OVM bit value.
Parallel SUBF3 and STF
Example
||
SUBF3
STF
R1,*−AR4(IR1),R0
R7,*+AR5(IR0)
Before Instruction
R0
SUBF3||STF
00 0000 0000
After Instruction
R0
06 1B60 0000
7.768750e+01
R1
05 7B40 0000 6.28125e+01
R1
05 7B40 0000
6.28125e+01
R7
07 33C0 0000 1.79750e+02
R7
07 33C0 0000
1.79750e+02
AR4
80 98B8
AR4
80 98B8
AR5
80 9850
AR5
80 9850
IR0
10
IR0
10
IR1
8
IR1
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
8098B0h
70C8000
1.4050e+02
809860h
733C000
1.79750e+02
Data memory
8098B0h
809860h
70C8000 1.4050e+02
0
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-235
SUBI Subtract Integer
Syntax
SUBI src, dst
Operation
dst − src → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0
16 15
G
1 1 0 0 0 0
8 7
dst
0
src
Description
The difference between the dst operand and the src operand is loaded into the
dst register. The dst and src operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
SUBI 220,R7
Before Instruction
13-236
After Instruction
R7
00 0000 0226
R7
00 0000 014A
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
550
Z
0
Z
0
V
0
V
0
C
0
C
0
330
Subtract Integer, 3-Operand
Syntax
SUBI3 src2, src1, dst
Operation
src1 − src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
SUBI3
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 27)
register (Rn2, 0 ≤ n2 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
0 0 1
24 23
0 0 1 1 1 0
16 15
T
dst
8 7
src1
0
src2
Description
The difference between the src1 operand and the src2 operand is loaded into
the dst register. The src1, src2, and dst operands are assumed to be signed
integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-237
SUBI3 Subtract Integer, 3-Operand
Example 1
SUBI3
R7,R2,R0
Before Instruction
Example 2
R0
00 0000 0000
R2
00 0000 0866
R7
00 0000 0834
LUF
0
After Instruction
R0
00 0000 0032
50
2150
R2
00 0000 0866
2150
2100
R7
00 0000 0834
2100
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
0
C
0
C
0
SUBI3 *−AR2(1),R4,R3
Before Instruction
R3
00 0000 0000
After Instruction
R3
00 0000 014A
330
550
R4
00 0000 0226
R4
00 0000 0226
AR2
80 985E
AR2
80 985E
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
80985Dh
0DC
550
Data memory
80985Dh
0DC
220
220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
13-238
Parallel SUBI3 and STI
Syntax
SUBI3||STI
SUBI3 src1, src2, dst1
STI
src3, dst2
||
Operation
src2 − src1 → dst1
|| src3 → dst2
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
Description
24 23
1 0 1 1 0
dst1
16 15
src1
src3
8 7
dst2
0
src2
An integer subtraction and an integer store are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. This
means that if one of the parallel operations (STI) reads from a register and the
operation being performed in parallel (SUBI3) writes to the same register, STI
accepts the contents of the register as input before it is modified by the SUBI3.
If src3 and dst1 point to the same location, src3 is read before the write to dst1.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Assembly Language Instructions
13-239
SUBI3||STI Parallel SUBI3 and STI
Example
||
SUBI3
STI
R7,*+AR2(IR0),R1
R3,*++AR7
Before Instruction
R1
After Instruction
00 0000 0000
R1
00 0000 00C8
200
R3
00 0000 0035
53
R3
00 0000 0035
53
R7
00 0000 0014
20
R7
00 0000 0014
20
AR2
80 982F
AR2
80 982F
AR7
80 983B
AR7
80 983C
IR0
10
IR0
10
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
80983Fh
0DC
220
80983Ch
35
53
Data memory
80983Fh
0DC
80983Ch
0
220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
13-240
Subtract Reverse Integer With Borrow
Syntax
SUBRB src, dst
Operation
src − dst − C → dst
Operands
src general addressing modes (G):
00
01
10
11
SUBRB
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0
1 1 0 0 0 1
16 15
G
87
0
src
dst
Description
The difference of the src, dst, and C operands is loaded into the dst register.
The dst and src operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
SUBRB R4,R6
Before Instruction
After Instruction
R4
00 0000 03CB
971
R4
00 0000 03CB
971
R6
00 0000 0258
600
R6
00 0000 0172
370
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
1
C
0
Assembly Language Instructions
13-241
SUBRF Subtract Reverse Floating-Point Value
Syntax
SUBRF src, dst
Operation
src − dst → dst
Operands
src general addressing modes (G):
00
01
10
11
register (Rn, 0 ≤ n ≤ 7)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 7)
Opcode
31
0 0 0
24 23
1 1 0 0 1 0
16 15
G
8 7
0
src
dst
Description
The difference between the src operand and the dst operand is loaded into the
dst register. The dst and src operands are assumed to be floating-point numbers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
1 if a floating-point underflow occurs; unchanged otherwise
1 if a floating-point overflow occurs; unchanged otherwise
1 if a floating-point underflow occurs; 0 otherwise
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if a floating-point overflow occurs; 0 otherwise
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
SUBRF @9905h,R5
Before Instruction
R5
After Instruction
R5
06 69E0 0000
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
DP
05 7B40 0000 6.281250e+01
Z
0
Z
0
V
0
V
0
C
0
C
0
809905h
733C000
1.16937500e+02
Data memory
809905h
13-242
733C000
1.79750e+02
1.79750e+02
Subtract Reverse Integer
Syntax
SUBRI src, dst
Operation
src − dst → dst
Operands
src general addressing modes (G):
00
01
10
11
SUBRI
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0
1 1 0 0 1 1
16 15
G
8 7
0
src
dst
Description
The difference between the src operand and the dst operand is loaded into the
dst register. The dst and src operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
1 if an integer overflow occurs; unchanged otherwise
0
1 if a negative result is generated; 0 otherwise
1 if a 0 result is generated; 0 otherwise
1 if an integer overflow occurs; 0 otherwise
1 if a borrow occurs; 0 otherwise
Mode Bit
OVM
Operation is affected by OVM bit value.
Example
SUBRI *AR5++(IR0),R3
Before Instruction
After Instruction
R3
00 0000 00DC
R3
00 0000 014A
AR5
80 9900
AR5
80 9908
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
220
Z
0
Z
0
V
0
V
0
C
0
C
0
809900h
226
330
Data memory
809900h
226
550
550
Assembly Language Instructions
13-243
SWI Software Interrupt
Syntax
SWI
Operation
Performs an emulation interrupt
Operands
None
Opcode
31
24 23
16 15
8 7
0
0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
The SWI instruction performs an emulator interrupt. This is a reserved instruction and should not be used in normal programming.
Cycles
4
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
13-244
Trap Conditionally
Syntax
TRAPcond N
Operation
0 → ST(GIE)
If cond is true:
Next PC → *++SP,
Trap vector N → PC.
TRAPcond
Else:
Set ST(GIE) to original state.
Continue.
Operands
N (0 ≤ N ≤ 31)
Opcode
31
24 23
0 1 1 1 0 1 0 0 0 0 0
Description
16 15
cond
8 7
0 0 0 0 0 0 0 0 0 0 1
0
N + 20h
Interrupts are disabled globally when 0 is written to ST(GIE). If the condition
is true, the contents of the PC are pushed onto the system stack, and the PC
is loaded with the contents of the specified trap vector (N). If the condition is
not true, ST(GIE) is set to its value before the TRAPcond instruction changes
it.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13−12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7−R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Cycles
5
Status Bits
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-245
TRAPcond
Example
Trap Conditionally
TRAPZ
16
Before Instruction
After Instruction
PC
0123
PC
0010
SP
809870
SP
809871
ST
0
ST
0
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
10
809871h
124
Data memory
Trap V.16
13-246
Test Bit Fields
Syntax
TSTB src, dst
Operation
dst AND src
Operands
src general addressing modes (G):
00
01
10
11
TSTB
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
0 0 0 1 1 0 1 0 0
16 15
G
dst
8 7
0
src
Description
The bitwise-logical AND of the dst and src operands is formed, but the result
is not loaded in any register. This allows for nondestructive compares. The dst
and src operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified for all destination registers (R27 −R0).
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-247
TSTB
Test Bit Fields
Example
TSTB *−AR4(1),R5
Before Instruction
R5
00 0000 0898
AR4
After Instruction
R5
00 0000 0898
80 99C5
AR4
80 99C5
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
1
V
0
V
0
C
0
C
0
8099C4h
767
2200
2200
Data memory
8099C4h
13-248
767
1895
1895
Test Bit Fields, 3-Operand
Syntax
TSTB3 src2, src1
Operation
src1 AND src2
Operands
src1 3-operand addressing modes (T):
00
01
10
11
TSTB3
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 27)
register (Rn2, 0 ≤ n2 ≤ 127)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
0 0 1
24 23
0 0 1 1 1 1
16 15
T
0 0 0 0 0
8 7
src1
0
src2
Description
The bitwise-logical AND between the src1 and src2 operands is formed but is
not loaded into any register. This allows for nondestructive compares. The
src1 and src2 operands are assumed to be unsigned integers. Although this
instruction has only two operands, it is designated as a 3-operand instruction
because operands are specified in the 3-operand format.
Cycles
1
Status Bits
These condition flags are modified for all destination registers (R27 −R0).
Mode Bit
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Assembly Language Instructions
13-249
TSTB3
Test Bit Fields, 3-Operand
Example 1
TSTB3
*AR5−− (IR0),*+AR0(1)
Before Instruction
After Instruction
AR0
80 992C
AR0
80 992C
AR5
80 9885
AR5
80 9805
IR0
80
IR0
80
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
1
V
0
V
0
C
0
C
0
Data memory
Example 2
809885h
898
2200
809885h
898
2200
80992Dh
767
1895
80992Dh
767
1895
TSTB3
R4,*AR6−− (IR0)
Before Instruction
After Instruction
R4
00 0000 FBC4
R4
00 0000 FBC4
AR6
80 99F8
AR6
80 99F0
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
1568
8099F8h
1568
Data memory
8099F8h
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
13-250
Bitwise-Exclusive OR
Syntax
XOR src, dst
Operation
dst XOR src → dst
Operands
src general addressing modes (G):
00
01
10
11
XOR
register (Rn, 0 ≤ n ≤ 27)
direct
indirect (disp = 0−255, IR0, IR1)
immediate
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
24 23
16 15
G
0 0 0 1 1 0 1 0 1
8 7
0
src
dst
Description
The bitwise-exclusive OR of the src and dst operands is loaded into the dst
register. The dst and src operands are assumed to be unsigned integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Unaffected
Mode Bit
OVM
Operation is not affected by OVM bit value.
Example
XOR R1,R2
Before Instruction
After Instruction
R1
00 000F FA32
R1
00 000F F412
R2
00 000F F5C1
R2
00 0000 0FF3
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Assembly Language Instructions
13-251
XOR3 Bitwise-Exclusive OR, 3-Operand
Syntax
XOR3 src2, src1, dst
Operation
src1 XOR src2 → dst
Operands
src1 3-operand addressing modes (T):
00
01
10
11
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
register (Rn1, 0 ≤ n1 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
00
01
10
11
register (Rn2, 0 ≤ n2 ≤ 27)
register (Rn2, 0 ≤ n2 ≤ 27)
indirect (disp = 0, 1, IR0, IR1)
indirect (disp = 0, 1, IR0, IR1)
dst register (Rn, 0 ≤ n ≤ 27)
Opcode
31
0 0 1
24 23
0 1 0 0 0 0
16 15
T
dst
8 7
src1
0
src2
Description
The bitwise-exclusive OR between the src1 and src2 operands is loaded into
the dst register. The src1, src2, and dst operands are assumed to be unsigned
integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 −R0.
Mode Bit
13-252
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Bitwise-Exclusive OR, 3-Operand
Example 1
XOR3
XOR3 *AR3++(IR0),R7,R4
Before Instruction
After Instruction
R4
00 0000 0000
R4
00 0000 A53C
R7
00 0000 FFFF
R7
00 0000 FFFF
AR3
80 9800
AR3
80 9810
IR0
10
IR0
10
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
5AC3
809800h
5AC3
Data memory
809800h
Example 2
XOR3
R5,*−AR1(1),R1
Before Instruction
After Instruction
R1
00 0000 0000
R1
00 0000 0F33
R5
00 000F FA32
R5
00 000F FA32
AR1
80 9826
AR1
80 9826
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
0FF5C1
809825h
0FF5C1
Data memory
809825h
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-253
XOR3||STI Parallel XOR3 and STI
Syntax
||
XOR3
STI
src2, src1, dst1
src3, dst2
Operation
src1 XOR src2 → dst1
|| src3 → dst2
Operands
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
- ’VC33
src1
src2
dst1
src3
dst2
register (Rn1, 0 ≤ n1 ≤ 7)
indirect (disp = 0, 1, IR0, IR1) or any CPU register
register (Rn2, 0 ≤ n2 ≤ 7)
register (Rn3, 0 ≤ n3 ≤ 7)
indirect (disp = 0, 1, IR0, IR1)
Opcode
31
1 1
Description
24 23
1 0 1 1 1
dst
16 15
src1
src3
8 7
dst2
0
src2
A bitwise-exclusive XOR and an integer store are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. If
one of the parallel operations (STI) reads from a register and the operation being performed in parallel (XOR3) writes to the same register, STI accepts as
input the contents of the register before it is modified by the XOR3.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
13-254
1
Parallel XOR3 and STI
Status Bits
Mode Bit
XOR3||STI
These condition flags are modified only if the destination register is R7 −R0.
LUF
LV
UF
N
Z
V
C
Unaffected
Unaffected
0
MSB of the output
1 if a 0 output is generated; 0 otherwise
0
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
||
XOR3
STI
*AR1++,R3,R3
R6,*−AR2(IR0)
Before Instruction
R3
After Instruction
00 0000 0085
R3
00 0000 0000
R6
00 0000 00DC
R6
00 0000 00DC
AR1
80 987E
AR1
80 987F
AR2
80 98B4
AR2
80 98B4
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
220
220
Data memory
80987Eh
85
80987Eh
85
8098ACh
0
8098ACh
0DC
220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores, on page 8-24 for the effects
of operand ordering on the cycle count.
Assembly Language Instructions
13-255
13-256
Appendix
AppendixAA
The opcode fields for all TMS320C3x instructions are shown in Table A−1. Bits
in the table marked with a hyphen are defined in the individual instruction
descriptions (see Chapter 13, Assembly Language Instructions). Table A−1,
along with the instruction descriptions, fully defines the instruction words. The
opcodes are listed in numerical order. Note that an undefined operation may
occur if an illegal opcode is executed. (An Illegal opcode can only be generated
by the misuse of the TMS320 floating-point software tools, by an error in the
ROM code, or by a defective RAM.)
A-1
Instruction Opcodes
Table A−1. TMS320C3x Instruction Opcodes
Instruction
31
30
29
28
27
26
25
24
23
ABSF
0
0
0
0
0
0
0
0
0
ABSI
0
0
0
0
0
0
0
0
1
ADDC
0
0
0
0
0
0
0
1
0
ADDF
0
0
0
0
0
0
0
1
1
ADDI
0
0
0
0
0
0
1
0
0
AND
0
0
0
0
0
0
1
0
1
ANDN
0
0
0
0
0
0
1
1
0
ASH
0
0
0
0
0
0
1
1
1
CMPF
0
0
0
0
0
1
0
0
0
CMPI
0
0
0
0
0
1
0
0
1
FIX
0
0
0
0
0
1
0
1
0
FLOAT
0
0
0
0
0
1
0
1
1
IDLE
0
0
0
0
0
1
1
0
0
IDLE2
0
0
0
0
0
1
1
0
0
LDE
0
0
0
0
0
1
1
0
1
LDF
0
0
0
0
0
1
1
1
0
LDFI
0
0
0
0
0
1
1
1
1
LDI
0
0
0
0
1
0
0
0
0
LDII
0
0
0
0
1
0
0
0
1
LDM
0
0
0
0
1
0
0
1
0
LDP
0
0
0
0
1
0
0
0
0
LSH
0
0
0
0
1
0
0
1
1
LOPOWER
0
0
0
1
0
0
0
0
1
MAXSPEED
0
0
0
1
0
0
0
0
1
MPYF
0
0
0
0
1
0
1
0
0
† The opcode is the same for standard and delayed instructions.
A-2
Instruction Opcodes
Table A−1. TMS320C3x Instruction Opcodes (Continued)
Instruction
31
30
29
28
27
26
25
24
23
MPYI
0
0
0
0
1
0
1
0
1
NEGB
0
0
0
0
1
0
1
1
0
NEGF
0
0
0
0
1
0
1
1
1
NEGI
0
0
0
0
1
1
0
0
0
NOP
0
0
0
0
1
1
0
0
1
NORM
0
0
0
0
1
1
0
1
0
NOT
0
0
0
0
1
1
0
1
1
POP
0
0
0
0
1
1
1
0
0
POPF
0
0
0
0
1
1
1
0
1
PUSH
0
0
0
0
1
1
1
1
0
PUSHF
0
0
0
0
1
1
1
1
1
OR
0
0
0
1
0
0
0
0
0
RND
0
0
0
1
0
0
0
1
0
ROL
0
0
0
1
0
0
0
1
1
ROLC
0
0
0
1
0
0
1
0
0
ROR
0
0
0
1
0
0
1
0
1
RORC
0
0
0
1
0
0
1
1
0
RPTS
0
0
0
1
0
0
1
1
1
STF
0
0
0
1
0
1
0
0
0
STFI
0
0
0
1
0
1
0
0
1
STI
0
0
0
1
0
1
0
1
0
STII
0
0
0
1
0
1
0
1
1
SIGI
0
0
0
1
0
1
1
0
0
SUBB
0
0
0
1
0
1
1
0
1
SUBC
0
0
0
1
0
1
1
1
0
SUBF
0
0
0
1
0
1
1
1
1
SUBI
0
0
0
1
1
0
0
0
0
† The opcode is the same for standard and delayed instructions.
Instruction Opcodes
A-3
Instruction Opcodes
Table A−1. TMS320C3x Instruction Opcodes (Continued)
Instruction
31
30
29
28
27
26
25
24
23
SUBRB
0
0
0
1
1
0
0
0
1
SUBRF
0
0
0
1
1
0
0
1
0
SUBRI
0
0
0
1
1
0
0
1
1
TSTB
0
0
0
1
1
0
1
0
0
XOR
0
0
0
1
1
0
1
0
1
IACK
0
0
0
1
1
0
1
1
0
ADDC3
0
0
1
0
0
0
0
0
0
ADDF3
0
0
1
0
0
0
0
0
1
ADDI3
0
0
1
0
0
0
0
1
0
AND3
0
0
1
0
0
0
0
1
1
ANDN3
0
0
1
0
0
0
1
0
0
ASH3
0
0
1
0
0
0
1
0
1
CMPF3
0
0
1
0
0
0
1
1
0
CMPI3
0
0
1
0
0
0
1
1
1
LSH3
0
0
1
0
0
1
0
0
0
MPYF3
0
0
1
0
0
1
0
0
1
MPYI3
0
0
1
0
0
1
0
1
0
OR3
0
0
1
0
0
1
0
1
1
SUBB3
0
0
1
0
0
1
1
0
0
SUBF3
0
0
1
0
0
1
1
0
1
SUB13
0
0
1
0
0
1
1
1
0
TSTB3
0
0
1
0
0
1
1
1
1
XOR3
0
0
1
0
1
0
0
0
0
LDFcond
0
1
0
0
−
−
−
−
−
LDIcond
0
1
0
1
−
−
−
−
−
BR(D)†
0
1
1
0
0
0
0
−
−
CALL
0
1
1
0
0
0
1
−
−
† The opcode is the same for standard and delayed instructions.
A-4
Instruction Opcodes
Table A−1. TMS320C3x Instruction Opcodes (Continued)
Instruction
31
30
29
28
27
26
25
24
23
RPTB
0
1
1
0
0
1
0
−
−
SWI
0
1
1
0
0
1
1
−
−
Bcond(D)†
0
1
1
0
1
0
−
−
−
DBcond(D)†
0
1
1
0
1
1
−
−
−
CALLcond
0
1
1
1
0
0
−
−
−
TRAPcond
0
1
1
1
0
1
0
−
−
RETIcond
0
1
1
1
1
0
0
0
0
RETScond
0
1
1
1
1
0
0
0
1
MPYF3||ADDF3
1
0
0
0
0
0
0
0
−
1
0
0
0
0
0
0
1
−
1
0
0
0
0
0
1
0
−
1
0
0
0
0
0
1
1
−
1
0
0
0
0
1
0
0
−
1
0
0
0
0
1
0
1
−
1
0
0
0
0
1
1
0
−
1
0
0
0
0
1
1
1
−
1
0
0
0
1
0
0
0
−
1
0
0
0
1
0
0
1
−
1
0
0
0
1
0
1
0
−
1
0
0
0
1
0
1
1
−
1
0
0
0
1
1
0
0
−
1
0
0
0
1
1
0
1
−
1
0
0
0
1
1
1
0
−
1
0
0
0
1
1
1
1
−
STF||STF
1
1
0
0
0
0
0
−
−
STI||STI
1
1
0
0
0
0
1
−
−
LDF||LDF
1
1
0
0
0
1
0
−
−
LDI||LDI
1
1
0
0
0
1
1
−
−
ABSF||STF
1
1
0
0
1
0
0
−
−
MPYF3||SUBF3
MPYI3||ADDI3
MPYI3||SUBI3
† The opcode is the same for standard and delayed instructions.
Instruction Opcodes
A-5
Instruction Opcodes
Table A−1. TMS320C3x Instruction Opcodes (Continued)
Instruction
31
30
29
28
27
26
25
24
23
ABSI||STI
1
1
0
0
1
0
1
−
−
ADDF3||STF
1
1
0
0
1
1
0
−
−
ADDI3||STI
1
1
0
0
1
1
1
−
−
AND3||STI
1
1
0
1
0
0
0
−
−
ASH3||STI
1
1
0
1
0
0
1
−
−
FIX||STI
1
1
0
1
0
1
0
−
−
FLOAT||STF
1
1
0
1
0
1
1
−
−
LDF||STF
1
1
0
1
1
0
0
−
−
LDI||STI
1
1
0
1
1
0
1
−
−
LSH3||STI
1
1
0
1
1
1
0
−
−
MPYF3||STF
1
1
0
1
1
1
1
−
−
MPYI3||STI
1
1
1
0
0
0
0
−
−
NEGF||STF
1
1
1
0
0
0
1
−
−
NEGI||STI
1
1
1
0
0
1
0
−
−
NOT||STI
1
1
1
0
0
1
1
−
−
OR3||STI
1
1
1
0
1
0
0
−
−
SUBF3||STF
1
1
1
0
1
0
1
−
−
SUBI3||STI
1
1
1
0
1
1
0
−
−
XOR3||STI
1
1
1
0
1
1
1
−
−
Reserved for reset,
traps, and interrupts
0
1
1
1
1
1
1
1
1
† The opcode is the same for standard and delayed instructions.
A-6
Appendix
AppendixBA
!%&'(&)*+&&-.%
This appendix contains the source code for the ’C31/VC33 boot loader.
Note: VC33
The TMS320VC33 is logically and functionally a superset of the TMS320C31
making nearly all literature and documentation for the TMS320C31 applica−
ble. However, the electrical characteristics are different and are covered in
detail in the TMS320VC33 data sheet (literature number SPRS087).
B-1
TMS320C31 Boot Loader Source Code
************************************************************************
*
C31BOOT − TMS320C31 BOOT LOADER PROGRAM
*
(C) COPYRIGHT TEXAS INSTRUMENTS INC., 1990
*
*
NOTE:
1. AFTER DEVICE RESET, THE PROGRAM IS SET TO WAIT FOR
*
THE EXTERNAL INTERRUPTS. THE FUNCTION SELECTION OF
*
THE EXTERNAL INTERRUPTS IS AS FOLLOWS:
*
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
INTERRUPT PIN |
FUNCTION
*
−−−−−−−−−−−−−−−|−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
0
| EPROM boot loader from 1000H
*
−−−−−−−−−−−−−−−|−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
1
| EPROM boot loader from 400000H
*
−−−−−−−−−−−−−−−|−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
2
| EPROM boot loader from FFF000H
*
−−−−−−−−−−−−−−−|−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
3
| Serial port 0 boot loader
*
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
*
*
2. THE EPROM BOOT LOADER LOADS WORD, HALFWORD, OR BYTE*
WIDE PROGRAMS TO SPECIFIED LOCATIONS. THE
*
8 LSBs OF FIRST MEMORY SPECIFY THE MEMORY WIDTH OF
*
THE EPROM. IF THE HALFWORD OR BYTE-WIDE PROGRAM IS
*
SELECTED, THE LSBs ARE LOADED FIRST, FOLLOWED BY THE MSBs.
*
THE FOLLOWING WORD CONTAINS THE CONTROL WORD FOR
*
THE LOCAL MEMORY REGISTER. THE PROGRAM BLOCKS FOLLOW.
*
THE FIRST TWO WORDS OF EACH PROGRAM BLOCK CONTAIN
*
THE BLOCK SIZE AND MEMORY ADDRESS TO BE LOADED INTO.
*
WHEN THE ZERO BLOCK SIZE IS READ, THE PROGRAM BLOCK
*
LOADING IS TERMINATED. THE PC WILL BRANCH TO THE
*
STARTING ADDRESS OF THE FIRST PROGRAM BLOCK.
*
*
3. IF SERIAL PORT 0 IS SELECTED FOR BOOT LOADING, THE
*
PROCESSOR WILL WAIT FOR THE INTERRUPT FROM THE
*
RECEIVE SERIAL PORT 0 AND PERFORM THE DOWNLOAD.
*
AS WITH THE EPROM LOADER, PROGRAMS CAN BE LOADED
*
INTO DIFFERENT MEMORY BLOCKS. THE FIRST TWO WORDS OF EACH
*
PROGRAM BLOCK CONTAIN THE BLOCK SIZE AND MEMORY ADDRESS
*
TO BE LOADED INTO. WHEN THE ZERO BLOCK SIZE IS READ,
*
PROGRAM BLOCK LOADING IS TERMINATED. IN OTHER WORDS,
*
IN ORDER TO TERMINATE THE PROGRAM BLOCK LOADING,
*
A ZERO HAS TO BE ADDED AT THE END OF THE PROGRAM BLOCK.
*
AFTER THE BOOT LOADING IS COMPLETED, THE PC WILL BRANCH
*
TO THE STARTING ADDRESS OF THE FIRST PROGRAM BLOCK.
*
************************************************************************
B-2
TMS320C31 Boot Loader Source Code
reset
int0
int1
int2
int3
xint0
rint0
tint0
tint1
dint
.global check
.sect ”vectors”
.word check
.word 809FC1h
.word 809FC2h
.word 809FC3h
.word 809FC4h
.word 809FC5h
.word 809FC6h
.word 809FC7h
.word 809FC8h
.word 809FC9h
.word 809FCAh
.word 809FCBh
.word 809FCCh
.word 809FCDh
.word 809FCEh
.word 809FCFh
.word 809FD0h
.word 809FD1h
.word 809FD2h
.word 809FD3h
.word 809FD4h
.word 809FD5h
.word 809FD6h
.word 809FD7h
.word 809FD8h
.word 809FD9h
.word 809FDAh
.word 809FDBh
.word 809FDCh
.word 809FDDh
.word 809FDEh
.word 809FDFh
***************************************************************************
trap0 .word
trap1 .word
trap2 .word
trap3 .word
trap4 .word
trap5 .word
trap6 .word
trap7 .word
trap8 .word
trap9 .word
trap10 .word
809FE0h
809FE1h
809FE2h
809FE3h
809FE4h
809FE5h
809FE6h
809FE7h
809FE8h
809FE9h
809FEAh
TMS320C31 Boot Loader Source Code
B-3
TMS320C31 Boot Loader Source Code
trap11 .word
trap12 .word
trap13 .word
trap14 .word
trap15 .word
trap16 .word
trap17 .word
trap18 .word
trap19 .word
trap20 .word
trap21 .word
trap22 .word
trap23 .word
trap24 .word
trap25 .word
trap26 .word
trap27 .word
.word
.word
.word
.word
809FEBh
809FECh
809FEDh
809FEEh
809FEFh
809FF0h
809FF1h
809FF2h
809FF3h
809FF4h
809FF5h
809FF6h
809FF7h
809FF8h
809FF9h
809FFAh
809FFBh
809FFCh
809FFDh
809FFEh
809FFFh
***************************************************************************
.space 5
check:
LDI
LSH
LDI
LSH
LDI
4040h,AR0
9,AR0
404Ch,SP
9,SP
0,R0
;
;
;
;
;
intloop
TSTB
BNZ
8,IF
serial
; test for ext int3
; on int3 go to serial
LDI
TSTB
BNZ
8,AR1
1,IF
eprom_load
; load 001000h / 2^9 −> AR1
; test for int0
; branch to eprom_load if int0 = 1
LDI
TSTB
BNZ
2000h,AR1
2,IF
eprom_load
; load 400000h / 2^9 −> AR1
; test for int1
; branch to eprom_load if int1 = 1
LDI
TSTB
BZ
7FF8h,AR1
4,IF
intloop
; load FFF000h / 2^9 −> AR1
; test for int2
; if no intX go to intloop
LSH
LDI
9,AR1
*AR1++(1),R1
; eprom address = AR1 * 2^9
; load eprom mem. width
LDI
sub_w,AR3
LSH
BN
26,R1
load0
;
;
;
;
;
eprom_load
B-4
load peripheral mem. map
start addr. 808000h
initialize stack pointer to
ram0 addr. 809800h
set start address flag off
full−word size subroutine
address −> AR3
test bit 5 of mem. width word
if ’1’ start PGM loading
(32 bits width)
TMS320C31 Boot Loader Source Code
load0
load2
NOP
LDI
*AR1++(1)
sub_h,AR3
LSH
BN
1,R1
load0
LDI
ADDI
sub_b,AR3
2,AR1
; byte size subroutine address −> AR3
; jump last 2 bytes from mem. word
CALLU
AR3
STI
R1,*+AR0(64h)
; load new word
; according to mem. width
; set primary bus control
CALLU
AR3
LDI
CMPI
BZ
SUBI
R1,RC
0,RC
AR2
1,RC
CALLU
AR3
LDI
LDI
LDIZ
LDI
SUBI
R1,AR4
R0,R0
R1,AR2
−1,R0
1,AR3
CALLUAR3
LDI
ADDI
BR
1,R0
1,AR3
load2
;
;
;
;
;
;
;
;
;
;
jump last half word from mem. word
half word size subroutine
address −> AR3
test bit 4 of mem. width word
if ’1’ start PGM loading
(16 bits width)
load new word according to
mem. width
set block size for repeat loop
if 0 block size start PGM
; block size −1
;
;
;
;
;
;
;
load new word according to
mem. width
set destination address
test start address loaded flag
load start address if flag off
set start & dest. address flag on
sub address with loop
;
;
;
;
;
;
load new word according to
mem. width
set dest. address flag off
sub address without loop
jump to load a new block
when loop completed
;
;
;
;
serial words subroutine
address −> AR3
R1 = 0000111h
set CLKR,DR,FSR as serial port pins
;
;
;
;
R2 = A300000h
set serial port global
ctrl. register
jump to load 1st block
.space 1
serial
LDI
sub_s,AR3
LDI
STI
LDI
LSH
STI
111h,R1
R1,*+AR0(43h)
0A30h,R2
16,R2
R2,*+AR0(40h)
BR
load2
.space 29
loop_s
sub_s
RPTB
TSTB
BZ
AND
load_s
20h,IF
sub_s
0FDFh,IF
; PGM load loop
; wait for receive buffer full
; reset interrupt flag
TMS320C31 Boot Loader Source Code
B-5
TMS320C31 Boot Loader Source Code
load_s
end_s
LDI
LDI
BNN
STI
RETSU
*+AR0(4Ch),R1
R0,R0
end_s
R1,*AR4++(1)
; test load address flag
; store new word to dest. address
; return from subroutine
.space 22
loop_h
sub_h
load_h
end_h
RPTB
LDI
AND
LDI
LSH
OR
LDI
BNN
STI
RETSU
load_h
*AR1++(1),R1
0FFFFh,R1
*AR1++(1),R2
16,R2
R2,R1
R0,R0
end_h
R1,*AR4++(1)
; PGM load loop
; load LSB half word
; load MSB half word
; R1 = a new 32-bit word
; test load address flag
; store new word to dest. address
; return from subroutine
.space 26
loop_w
sub_w
load_w
end_w
RPTB
LDI
LDI
BNN
STI
RETSU
load_w
*AR1++(1),R1
R0,R0
end_w
R1,*AR4++(1)
; PGM load loop
; read a new 32-bit word
; test load address flag
; store new word to dest. address
; return from subroutine
.space 14
loop_b
sub_b
load_b
end_b
RPTB
LDI
AND
LDI
AND
LSH
OR
LDI
AND
LSH
OR
LDI
OR
LDI
BNN
STI
RETSU
.space 1
.end
B-6
load_b
*AR1++(1),R1
0FFh,R1
*AR1++(1),R2
0FFh,R2
8,R2
R2,R1
*AR1++(1),R2
0FFh,R2
16,R2
R2,R1
*AR1++(1),R2
LSH 24,R2
R2,R1
R0,R0
end_b
R1,*AR4++(1)
; PGM load loop
; load 1st byte ( LSB )
; load 2nd byte
; load 3rd byte
; load 4th byte ( MSB )
; R1 = a new 32-bit word
; test load address flag
; store new word to dest. address
; return from subroutine
Appendix
AppendixCA
!%&'(&'-.%
This appendix includes a description of the ’C32 boot loader sequence of
events and a listing of its source code.
Topic
Page
C.1
Boot-Loader Source Code Description . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C.2
Boot-Loader Source Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
C-1
Boot-Loader Source Code Description
C.1 Boot-Loader Source Code Description
Figure C−1 shows the boot loader program flow chart. The boot loader program starts by initializing three registers: AR7, SP, and IR0. These registers
hold the peripheral bus memory map register base address, the timer counter
register (used as a stack), and a flag that indicates the first block, respectively.
Then, the program checks for serial port boot load or memory boot load mode
by processing the bit fields set in the interrupt flag register (IF). For a serial port
boot load, the program initializes the serial port for 32-bit fixed-burst-mode
reads with an externally generated serial port clock and FSR.
For a memory boot load, AR3 is set to the boot source address, AR2 points
to the boot source strobe control register, and R2 contains the value that is
stored in this strobe control register. The boot loader also sets the bit field I/
OXF0 of the I/O flag register (IOF) if the handshake mode was selected. Then
the boot loader reads the first word of the boot source program. This 32-bit
word indicates the boot memory width and the boot load program stores this
value in R5. AR0 points to the read_mc routine that performs this read.
After reading the memory width word, the boot loader reads IOSTRB, STRB0,
and STRB1 control register values of the source program. These values are
temporarily saved in the DMA source address register, DMA destination address register, and DMA transfer counter registers, respectively. Then, the
program reads the block size with the read_mc routine. If the block size is 0,
the boot loader restores the values of IOSTRB, STRB0, and STRB1 previously
saved and branches to the destination address of the first block loaded and
begins program execution. If the block size is not 0, the boot loader stores the
block size in the BK register. This is used as a counter in a repeat block (RPTB)
to transfer all the data or program in that block.
For each block, the boot loader reads the destination address and the destination strobe control word. The program stores the destination address in the
AR5 register. The destination strobe control word includes the destination
strobe identification, the contents of the destination strobe control register
(includes memory width and data size). The boot loader extracts this information from the destination control word and stores the destination strobe-control
register memory-mapped address in the AR4 register, the contents of the destination strobe control register in the R4 register, and the source data size in
the R3 register. The boot loader sets the AR1 register to the appropriate read
routine read_s0 for serial port boot load and read_mb for memory boot load.
The read routine uses these registers to control the transfer of a block of data
or program.
C-2
Boot-Loader Source Code Description
Figure C−1. Boot-Loader Flow Chart
Start
Initialize registers:
AR7, SP, IR0
Interrupt flag IF
Serial initialize
serial global
control register
Serial
boot?
No
Process interrupts
INT0, INT1, INT2
Memory width: R5
Process memory
width word
Memory control word
read routine: AR0
Boot source
address: AR3
Boot strobe
pointer: AR2
Boot strobe value:
R2
Handshake mode:
IOF
Read and store
strobe values
Read block size
Yes
Block size RC
Block
size=0?
No
Restore strobe
values previously
saved
Read destination
address
Start
program execution
Read destination
strobe
Destination
address: AR3
Transfer one block of data or program
Yes
Destination strobe
pointer: AR4
Destination strobe
value: R4
Destination data
size: R3
Select read
routine
Memory block read
routine: AR1
Memory width:
R5
TMS320C32 Boot Loader Source Code
C-3
Boot-Loader Source Code Listing
C.2 Boot-Loader Source Code Listing
**********************************************************************************
* C32BOOT − TMS320C32 BOOT LOADER PROGRAM
(143 words)
March−96
*
(C) COPYRIGHT TEXAS INSTRUMENTS INCORPORATED, 1994
v.27
*================================================================================*
*
* NOTE:
*
* 1. Following device reset, the program waits for an external interrupt.
*
The interrupt type determines the initial address from which the boot
*
loader will start loading the boot table to the destination memory:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
C-4
INTERRUPT PIN
BOOT TABLE START ADDRESS
INT0
1000h
INT1
BOOT SOURCE
(STRB0)
EPROM
810000h
(IOSTRB)
EPROM
INT2
900000h
(STRB1)
EPROM
INT3
80804Ch
(sport0 Rx)
SERIAL
(STRB0)
ASYNC
EPROM,XF0/XF1
810000h
(IOSTRB)
ASYNC
EPROM,XF0/XF1
900000h
(STRB1)
ASYNC
EPROM,XF0/XF1
INT0 and INT3
1000h
INT1 and INT3
INT2 and INT3
If INT3 is asserted together with (INT2 or INT1 or INT0) following reset,
that indicates that the boot table is to be read asynchronously from EPROM
using pins XF0 and XF1 for handshaking. The handshaking protocol assumes
that the data ready signal generated by the host arrives through pin XF1.
The data acknowledge signal is output from the C32 on pin XF0.Both signals
are active low. The C32 will continuous