A Quadrature Pulse Generator for Short-Range UWB

A Quadrature Pulse Generator for Short-Range UWB
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 10, OCTOBER 2011
2285
A Quadrature Pulse Generator for Short-Range
UWB Vehicular Radar Applications Using a Pulsed
Oscillator and a Variable Attenuator
Ahmed M. El-Gabaly, Student Member, IEEE, and Carlos E. Saavedra, Senior Member, IEEE
Abstract—A new quadrature tunable pulse generator is presented in this paper using 0.13 m CMOS for 22–29 GHz ultrawideband (UWB) vehicular radar. A quadrature inductor-capacitor
(LC) oscillator is quickly switched on and off for the duration
of the pulse, and the amplitude envelope is modulated with an
impulse using a variable passive CMOS attenuator. The impulse
is realized using a glitch generator (CMOS NAND gate) and its
duration can be changed over a wide range (375 ps to more than
1 ns). The switching technique used in the quadrature oscillator
creates a large initial voltage for fast startup (0.5 ns) and locks
the initial phase of the oscillations to the input clock for pulse
coherence. The measured phase noise thus matches that of the
clock signal, with a relatively low phase noise of 70 dBc/Hz
and 100 dBc/Hz at 1kHz and 1 MHz offsets respectively. The
entire circuit operates in switched-mode with a low average power
consumption of less than 2.2 mW and 14.8 mW at 50 MHz and
600 MHz pulse repetition frequencies, or below 11 pJ of energy
for each of the four differential quadrature pulses. It occupies an
active area of less than 0.41 mm2 .
Index Terms—CMOS integrated circuits, pulse generator, ultrawideband, vehicular radar.
I. INTRODUCTION
HE FREQUENCY spectrum from 22 GHz to 29 GHz
was made available by the U.S. Federal Communications
Commission (FCC) for short-range radar (SRR) systems on terrestrial transportation vehicles [1]. Such systems are able to detect the location and movement of objects near a vehicle by developing a 360 radar map of its surroundings, to provide safety
features such as near collision avoidance, enhanced airbag activation, and improved suspension system control that better responds to road conditions [1], [2]. Normally, the average power
spectral density (PSD) should not exceed 41.3 dBm/MHz to
avoid interference [1], affecting the introduction of vehicular
radars in the U.S. and global markets, and having a significant
impact on system and pulse waveform design.
T
Manuscript received September 13, 2010; revised January 04, 2011; accepted
February 04, 2011. Date of publication April 07, 2011; date of current version
September 28, 2011. This paper was recommended by Associate Editor A. Neviani.
The authors are with the Department of Electrical and Computer Engineering,
Queen’s University, Kingston, ON, K7L 3N6 CANADA (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2011.2123550
UWB SRR is considered a key element in comprehensive environment sensing for automobiles, complementing other technologies such as infrared (IR), ultrasonic, video, and long-range
active cruise control (ACC) radars [2]. A network of 16 or more
UWB radar sensors around the vehicle [3] can provide a variety
of features to improve passenger safety, ranging from simple
parking aids to more sophisticated blind-spot monitoring, precrash detection, and stop-and-go or short-range cruise control.
Such applications require a high resolution of about 10 cm. Increasing the number of radar sensors can increase the processing
capability and reliability of the SRR system.
Pulsed UWB technology is based on the transmission of short
pulses with subnanosecond time duration, thereby spreading
the signal bandwidth over several gigahertz. Pulsed UWB techniques potentially offer several advantages over conventional
radar approaches, including higher range resolution, enhanced
target radar cross section (RCS) and identification, increased
immunity to passive interference (e.g., rain), and the ability to
detect very slowly moving targets. [4], [5]. Their transceiver architecture is also one of the simplest to implement, potentially
making them very cost-effective. Furthermore, time-gating can
increase isolation between the transmitter and receiver for a
longer operating range, and low duty cycling can significantly
reduce the power consumption.
In conventional pulsed vehicular radars [2], [6]–[16], pulses
are generated by time gating the output of a high-frequency local
oscillator (LO) phase-locked loop (PLL) using a switch. The
output amplitude envelope typically has a rectangular shape,
which results in an inefficient sinc spectrum with high out-ofband power that will need to be filtered [17]. The LO PLL is also
continuously running since its turn-on and locking transient are
usually not short enough for it to be switched off and on during
the interpulse period, resulting in high LO leakage and a low
power efficiency. Furthermore the LO PLL can be rather complex, consuming a significant amount of power. Even though
power consumption is not a primary concern in automobile applications, the total power consumption can become significant
as the number of sensors increases [18]. Pulsed or gated local
oscillators have been investigated to reduce LO leakage, circuit
complexity, and power consumption [19]–[26]. However, the
oscillator turn-on and stabilization time can be relatively long,
limiting the pulse duration and bandwidth. In addition, there
is little control over the startup and turn off transients and the
output pulse shape cannot be readily tuned. Other pulse generators have been reported that use passive filters [27] or distributed structures of edge combiners [18]. They are often lim-
1549-8328/$26.00 © 2011 IEEE
2286
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 10, OCTOBER 2011
Fig. 1. Proposed UWB pulse generator circuit diagram.
ited to a specific pulse shape and frequency spectrum that highly
depend on device parameters and matching, and are difficult to
control to handle process variations, regulatory differences, and
changes in the channel or antenna characteristics.
In this paper, a new quadrature pulse generator is proposed
in 0.13 m CMOS for short-range 22–29 GHz UWB vehicular radar. It can be used in pulsed UWB vehicular radar transceivers to provide template pulses for quadrature pulse correlation and detection [2], [8], [28], [29], or to enable quadri-phase
coding for enhanced pulse compression, detection, and interference mitigation. A quadrature inductor-capacitor (LC) oscillator
operating at 24 GHz is used in this work, which can be switched
off between pulses to reduce LO leakage, LO self mixing, dc
offsets, and power consumption. The oscillator switching technique injects a current impulse upon startup with a short time duration and large harmonic components out to 24 GHz, creating
a large initial condition for a short settling time of about 0.5 ns,
and locking the initial phase of the oscillations to the input clock
for high pulse-to-pulse coherence. The measured output phase
noise matches that of the clock signal, yielding a relatively low
phase noise of 70 dBc/Hz at 1 kHz offset, and 100 dBc/Hz
at 1 MHz offset. This amounts to a low integrated rms jitter from
100 Hz to 1 MHz of less than 720 fs. A -network attenuator
then modulates the LO signal to generate the UWB pulse. The
attenuator is controlled with two inverted impulses, which can
be readily tuned to vary the width of the UWB pulse over a wide
range from 375 ps to more than 1 ns. Such an approach provides
good control of the radiated frequency spectrum, as the 10 dB
bandwidth can reach 4.9 GHz and the out-of-band rejection can
exceed 23 dB. The pulse generator can operate with a pulse repetition frequency (PRF) as high as 600 MHz, allowing it to be
readily shared between the transmitter and receiver with a time
delay as short as 1.66 ns. The circuit is fully differential and operates in switched mode with zero static current for a low power
consumption of only 2.2 mW and 14.8 mW at PRFs of 50 MHz
and 600 MHz respectively, or less than 11 pJ of energy for each
of the four differential quadrature pulses. The integrated circuit
(IC) occupies a die area of 0.94 mm including bonding pads
and decoupling capacitors, and the active circuit area is only
0.41 mm .
II. CIRCUIT ARCHITECTURE AND DESIGN
A circuit schematic of the 22–29 GHz UWB pulse generator
is shown in Fig. 1. It consists of a quadrature LC local oscillator
EL-GABALY AND SAAVEDRA: QUADRATURE PULSE GENERATOR FOR SHORT-RANGE UWB VEHICULAR RADAR APPLICATIONS
Fig. 2. Pulse generator clock timing and output waveforms.
(LO), buffers, a glitch generator and variable -network attenuators. An inverter chain first sharpens the rising/falling edge
of the clock signal (CLK), which is used to turn the LO and
buffers on and off. The clock signal (TRIG) then triggers the
glitch generator, where a NAND gate operates on the rising-edge
.
and its delayed inverse to form a short impulse
This impulse and its inverse control the variable -network
attenuator to shape the amplitude envelope of the LO signals
LO
LO
LO
LO
and form the desired quadra. Fig. 2
ture UWB pulses at the outputs
illustrates the timing of the clock signals (CLK, TRIG) and
the generated pulse waveforms. Note that the glitch generator
clock signal (TRIG) is delayed with respect to the LO’s clock
signal (CLK) using current-starved inverters (Fig. 1). This in
, allowing sufficient time for the
turn delays the onset of
oscillations to stabilize and reach steady state before amplitude
shaping takes place. The delay between TRIG and CLK can be
(Fig. 1).
tuned using the control voltage
A. Pulsed Quadrature LC Oscillator
A common way of implementing a differential LC oscillator
is to use a cross-coupled pair of transistors to generate the negative resistance required and overcome the losses in the LC tank.
seen looking into the cross-coupled pair is
The resistance
given by
, where
is the transconductance of each of
the transistors. Therefore, with sufficient device size and biasing
current, a negative resistance larger than the equivalent parallel
can be realized to sustain the oscilresistance of the tank
lations.
The quadrature LC oscillator circuit designed in this work
is shown in Fig. 3. It consists of two cross-coupled oscillators
that are connected together through the body terminals (or back,
,
and
. Adding
gates) of the PMOS devices
2287
and
)
cross-coupled PMOS transistors (
and
above the cross-coupled NMOS transistors (
) increases the transconductance per unit current
for a low power consumption. It also improves the symmetry and phase noise of the oscillations as shown in [30], [31].
Quadrature-coupling the two oscillators using the body terminals of the core PMOS devices saves power as opposed to using
additional transistors which will also add noise [32], [33]. The
are added for dc biasing of the body terminals and
resistors
for ac coupling. The free-running oscillathe capacitors
for each oscillator is specified by the resotion frequency
nant frequency of the LC tank
LC, where is the value of
the on-chip spiral inductor and is the total parasitic capacitance at the output nodes. The inductors used in this circuit are
m
m in size with one
symmetric spirals, and are
turn and 7.5 m trace width. An electromagnetic (EM) simulation of the inductors predicts an inductance of 0.16 nH and a
quality-factor (Q) of approximately 26 at 24 GHz. The total capacitance including the parasitic capacitance of the cross-coupled transistors, common-source buffers (
,
,
, and
) and metal interconnects
is about 0.27 pF to provide oscillation at 24 GHz.
The initial startup transient of the oscillations can be characterized by the well-known “van der Pol” nonlinear differential
equation [34] given by
(1)
is a damping factor. An apwhere
proximate solution to (1) for the differential output voltage
can be found as [35]
(2)
where
is the initial condition and
is the steady-state
oscillation amplitude. The oscillation phase depends on the
to
initial conditions. The settling time for the oscillation
reach 90% of its steady state value
can be derived from
(2) [35]
(3)
where
is the open-loop gain and
is the quality-factor of the LC tank. It is clear
that the settling time
is shorter for larger initial conditions
. In addition, the settling time can be reduced by decreasing
, which can be approximated for
as:
LC
(4)
From (4), the settling time
can be reduced by decreasing
or increasing the transistor transconthe tank capacitance
. Thus, the capacitance is minimized to include
ductance
only the parasitic capacitance of the cross-coupled transistors
2288
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 10, OCTOBER 2011
Fig. 3. Circuit schematic of quadrature LC oscillators and buffers.
and the connecting common-source
and
).
buffers (
The biasing currents of the two differential oscillators are
switched on and off using a pair of NMOS switches (
and
) as shown in Fig. 3. Similarly the
biasing currents of the four output common-source buffers are
and
switched using NMOS switches
. By switching on one side of each differential oscillator
before the other (i.e., switching on
before
, and
before
), a current
initially flows through the
LC tank as shown in Fig. 4. The current-starved inverters shown
in Fig. 3 are used to introduce a short delay between the clock
signals CLK and CLK that trigger the pair of switches, and
only flows for a short time. In effect,
thus the initial current
a current impulse with a short time duration and high frequency
content out to 24 GHz is injected through the LC tank. This crefor a short settling time as
ates a large initial condition
indicated by (3) [35]. It also sets the initial phase of the oscillations at the turn-on instant. By setting the same initial oscillation phase at each clock rising edge, the LO pulses are phase
coherent with the input clock and pulse-to-pulse coherency is
between the clock signals
maintained. Note that the delay
CLK and CLK can be tuned using the control voltage
(Fig. 3) to vary the time duration of the current impulse
.
Time-domain simulations of the oscillator differential output
are shown in Fig. 5, with different delays
introvoltage
duced between the clock signals CLK and CLK using the
. The input clock frequency is set to 500
control voltage
Fig. 4. Illustration of the current injected into the differential LC oscillator.
MHz for these simulations. Fig. 5(a) shows the output voltage
V and
ps in comparison with that
for
obtained for
V and
ps. It is clear
that the settling time is reduced by roughly a factor of 2 when
ps is applied. Fig. 5(b) shows the output
a delay of
set to 0.8 V, 0.98 V, and 1.2 V, and it is clear
voltage with
EL-GABALY AND SAAVEDRA: QUADRATURE PULSE GENERATOR FOR SHORT-RANGE UWB VEHICULAR RADAR APPLICATIONS
Fig. 5. Simulated oscillator output voltage v(t) for: (a) V
set to 0.8 V, 0.98 V, and 1.2 V.
1.4 V, and (b) V
2289
set to 0.98 V and
Fig. 7. Simulated timing diagrams for: (a) clock signals and (b) oscillator waveforms.
Fig. 6. Simulated injected current impulse I for V
set to 0.8 V, 0.98 V,
and 1.2 V. (a) Time-domain waveform. (b) Frequency spectrum.
that the shortest settling time is achieved with
V
and
ps. The injected current impulse
is also illustrated in Fig. 6(a) for the same control voltages, and its frequency spectrum is plotted in Fig. 6(b). The injected current imV has an amplitude of 4 mA and a short
pulse for
time duration of about 48 ps. It also has a large frequency component at 24 GHz compared to the injected current impulses for
V and
V, yielding a relatively large
of about 45 mV for the shortest
initial condition voltage
settling time.
Timing diagrams for the clock signals CLK CLK
and the differential quadrature oscillating waveforms
LO
LO
and LO
LO
LO )
(LO
are shown in Fig. 7 for
V. It is clear that the LO
signals (LO and LO ) reach steady state within 0.5 ns from
startup (i.e., CLK rising edge). The LO remains on for the
duration of the clock signal CLK when it is in logic 1 to
allow sufficient time for amplitude shaping using the generated
impulse signals.
B. Glitch Generator
The subnanosecond glitch generator [12], [36]–[38] shown
in Fig. 1 creates a wideband impulse having the required
width and shape. The pulse produced is also tunable to allow
for different pulse durations and bandwidth. The circuit is
implemented using low-power CMOS digital logic, providing
full voltage swing required to operate the variable attenuator.
A Gaussian-like pulse is created in a glitch fashion by feeding
the NAND gate with a clock rising edge along with its delayed
in Fig. 1). The short duration where both
inverse ( and
signals are high causes the NAND gate’s output to be temporarily pulled low thus generating the pulse (Fig. 1). The
propagation time through the feedback loop, which consists
of the propagation time through the NAND gate, the following
inverter and the charging time of transistor
, specifies this
duration and thus the pulse width. A CMOS transmission gate
is added in the feedback path to control the charging
time constant of transistor
. By varying the control voltage
2290
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 10, OCTOBER 2011
, the charging time-constant changes, which tunes the
generated pulse width. Two cascaded inverters serve as a buffer
,
to drive the variable attenuator for the generated pulse
while a transmission gate followed by an inverter realize the
. In addition, varactors
are connected
inverted pulse
and
as shown in Fig. 1 to vary the
to the outputs
loading capacitance and thus tune the rise/fall times (slopes)
of the generated pulses. The optimum size for each device is
determined by extensive simulation. Simulations indicate that
pulses with different time durations can be generated, with
the minimum duration being below 400 ps and the maximum
duration being bounded by the on period of the clock signal
(TRIG). The pulse peak voltage is equal to the supply voltage
V for all pulse durations.
of
C. Variable Attenuator
The variable attenuator consists of two series NMOS devices
and
connected to two shunt NMOS devices
and
in a -network configuration as shown in Fig. 1. These are
and
. When
driven by the glitch generator pulses
is low and
is high, the series NMOS devices are
off and the shunt NMOS devices are on, blocking the LC oscillator’s signal and shorting the output for maximum attenuation.
is high and
is low, the opposite occurs and
When
the signal is passed to the output with minimum loss. This in efand
fect performs the desired envelope modulation as
vary with time.
The -network attenuator configuration offers a higher attenuation range than using a single NMOS device but at the
cost of a higher insertion loss and a lower bandwidth. Tranalso serves as a load for the LO when the control
sistor
impulse
is low. This ensures an approximately constant
loading impedance at the LO outputs regardless of the state of
the impulse. The design of the variable attenuator involves several trade-offs, such as minimizing the on-state insertion loss,
the off-state LO leakage and the pulse rise and fall times. Larger
devices tend to reduce the insertion loss and increase the attenuation range; however, the increased parasitic capacitance
adversely affects the bandwidth. In this design, on-chip spiral
inductors are connected in series (series-peaking) as shown in
Fig. 1 to absorb the transistors’ parasitic capacitances and inof the attenuator
crease the bandwidth. The ac voltage gain
has been simulated and plotted in Fig. 8. The minimum loss at
V is about
the maximum gate voltage of
4.0 dB. It is also evident that the maximum attenuation achieved
at the center frequency of 24.0 GHz is 41 dB, giving an attenuation range of more than 30 dB. Note that 30 dB of attenuation
range is sufficient since the LO can be switched off shortly after
the pulse to mitigate LO leakage. Furthermore, the transmission
in the on state remains quite flat, with less than 2.8 dB deviation
over the 22–29 GHz UWB bandwidth.
III. MEASUREMENT AND SIMULATION RESULTS
A. Pulsed Quadrature Oscillator
The pulsed quadrature oscillator was first fabricated and characterized separately in 0.13 m CMOS. A photograph of the
Fig. 8. Simulated voltage gain jA
(V
= 1:4 V) and off-state (V
j
of the variable attenuator in the on-state
= 0 :0 V ) .
Fig. 9. Photograph of quadrature pulsed oscillator IC.
IC is shown in Fig. 9. It occupies a die area of 0.54 mm including bonding pads, decoupling capacitors and the chip guard
ring (plus chamfer regions), while the core circuit area is 0.17
mm .
The pulsed oscillator IC was measured directly on-wafer
using 40 GHz coplanar waveguide (CPW) probes and dc
probes. The Agilent 50 GHz spectrum analyzer (E4448A) was
used to examine the output power spectrum and phase noise.
Fig. 10 shows the measured output power spectrum when the
quadrature oscillator is in free running mode, i.e., the input
V . The spectrum
clock is held at logic high
plot is centered at 23.9 GHz and covers a span of 500 MHz.
It is clear that the free-running output power level is about
4.5 dBm at a frequency of 23.9 GHz. The phase noise of the
free-running oscillations was measured and is plotted in Fig. 11
against the simulated phase noise. It is apparent that there is
good agreement between measurement and simulation, and that
a relatively low phase noise of 100 dBc/Hz is achieved at 1
MHz offset. The oscillation frequency can be tuned using the
of the PMOS devices
body biasing voltage
(Fig. 3), and Fig. 12 shows the measured oscillation frequency
. The results
and output power level with different values of
indicate that the tuning range is about 600 MHz, over which
the output power varies by less than 1.5 dB.
EL-GABALY AND SAAVEDRA: QUADRATURE PULSE GENERATOR FOR SHORT-RANGE UWB VEHICULAR RADAR APPLICATIONS
2291
Fig. 10. Measured free-running output spectrum over a span of 500 MHz centered at 23.9 GHz.
Fig. 11. Measured and simulated free-running output phase noise PSD from 1
kHz to 1 MHz.
Fig. 12. Measured oscillation frequency and output power with different values
of V .
The pulsed output power spectrum was also measured directly using a spectrum analyzer over a span of 8 GHz and is
plotted in Fig. 13(a). The input clock is a periodic sinusoidal
signal which is readily converted on-chip into a digital square
wave using the edge sharpening inverters (Fig. 1). The clock
frequency was set to about 500 MHz (508 MHz) for this measurement. The power spectrum exhibits peaks at multiples of
the PRF since the output is a periodic (unmodulated) extension
of the pulses. It is also apparent that the generated harmonic
components are coherent and well-defined. Fig. 13(b) shows the
Fig. 13. Measured pulsed output spectrum at 24 GHz: (a) 8 GHz span and (b)
1 MHz span.
generated peak at 23.92 GHz in more detail over a span of only
1 MHz, clearly showing stable and locked operation.
Fig. 14 shows the measured phase noise of the generated
pulsed output at 23.92 GHz. The measured phase noise of the
clock reference and that of the free-running output shown in
Fig. 11 are also included in Fig. 14 for comparison. As depicted
in Fig. 14, the output phase noise matches that of the clock reference but is approximately 33 dB higher. This corresponds to
the frequency ratio between the output and the clock reference
dB. Fig. 14 verifies that the
since
24-GHz pulsed oscillator is phase locked to the 500 MHz clock
reference, achieving a relatively low phase noise of 62 dBc/Hz
at 100 Hz, 70 dBc/Hz at 1 kHz and 65 dBc/Hz at 10 kHz.
This amounts to a low integrated rms jitter of 720 fs from 100
Hz to 1 MHz.
The locking bandwidth of the oscillator was verified in both
continuous and pulsed operation. In continuous operation, the
V and a 24 GHz
input clock is held at logic high
sinusoidal signal is added using a bias-T for injection locking.
of the oscillator can be characterized
The locking bandwidth
by the well-known “Adler” formula given by
(5)
where is the free-running oscillator frequency,
is the inis the oscillator output power level, and
jected power level,
is the quality factor of the LC tank. Thus, the locking bandwidth can be controlled by the injected-to-output power ratio
2292
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 10, OCTOBER 2011
Fig. 14. Measured phase noise of pulsed output at 24 GHz.
Fig. 16. Variations of the pulse center frequency with: (a) process, (b) temperature, and (c) supply voltage.
Fig. 15. Measured locking bandwidth for different levels of injected power
P .
. Fig. 15 shows the measured locking bandwidth for different injected power levels. It is clear that the locking bandwidth varies with the injected power according to (5), and that
a locking bandwidth of 100 MHz is achieved at a low injected
dB . In pulsed operation, the ospower level
at startup
cillator output voltage amplitude and power level
are small compared to those in steady state. The current impulse
injected at startup can also have a relatively large frequency
component at 24 GHz as shown in Section II-A. Therefore a
can be achieved
higher injected-to-output power ratio
for a wider locking bandwidth. The locking bandwidth was measured in pulsed operation and it was found to exceed 11 MHz
around the 500 MHz input clock frequency. This translates to
a locking bandwidth of more than 500 MHz at the output frequency of 23.9 GHz, thus ensuring phase-coherent pulsed operation.
The oscillator center frequency may drift due to changes in
process, supply voltage and temperature (PVT). Simulations of
the center frequency as a function of PVT variations are shown
in Fig. 16. Corner simulation is performed in three modes (SS,
TT, FF) to capture variations in process at the nominal supply
voltage of 1.4 V and temperature of 25 C. From Fig. 16(a), the
oscillator frequency varies by about 1.6% due to the process.
Meanwhile, as the temperature changes from 0 C to 75 C in
typical process conditions and at the nominal supply voltage,
the oscillation frequency shows a variation of less than 0.75%
[Fig. 16(b)]. In addition, the oscillation frequency changes by
only 0.15% [Fig. 16(c)] as the power supply voltage changes
by 0.1 V at nominal process and temperature. These variations
should be tolerable, since they are relatively small compared to
the pulse frequency bandwidth of more than 2.7 GHz or 11%.
The integrated power lost into adjacent channels, over a 2.7 GHz
bandwidth would be relatively small and the receiver would still
be able to detect the pulse to a certain extent. Furthermore, the
oscillator frequency tuning range of 600 MHz and the available
locking bandwidth of more than 500 MHz are sufficient to account for the PVT variations.
B. Quadrature Pulse Generator
The complete quadrature pulse generator was also fabricated
in 0.13 m CMOS and a photograph of the IC is shown in
Fig. 17. It occupies a die area of 0.94 mm including bonding
pads, decoupling capacitors and the chip guard ring (plus
chamfer regions), while the core circuit area is 0.41 mm . The
circuit consumes less than 2.2 mW of average power
at a PRF of 50 MHz. The power consumption increases with
the PRF, reaching 14.8 mW at the maximum PRF of 600 MHz.
of less than 11.0 pJ and
This gives an energy consumption
6.2 pJ at 50 MHz and 600 MHz PRF respectively for each of
the four differential quadrature pulses. The energy consumption
is given by:
(6)
where PRI is the pulse repetition time.
The UWB pulse generator IC was also measured directly
on-wafer and a 60 GHz Tektronix Digital Serial Analyzer (DSA)
was used to observe the pulses in the time domain. The input
clock is a periodic sinusoidal signal which is readily converted
on-chip into a digital square wave using the edge sharpening
EL-GABALY AND SAAVEDRA: QUADRATURE PULSE GENERATOR FOR SHORT-RANGE UWB VEHICULAR RADAR APPLICATIONS
2293
Fig. 17. Photograph of quadrature UWB pulse generator IC.
Fig. 19. Measured UWB waveforms with different time durations: (a) long
(650 ps), (b) moderate (525 ps), and (c) short (375 ps).
Fig. 18. Output UWB waveforms: (a) simulated and (b) measured.
inverters (Fig. 1). Fig. 18 shows a comparison between a simulated output signal and the DSA’s measurement result. Both simulation and measurements have the same bias conditions, and
there is good agreement between the simulated and measured
waveforms. The measured pulses have a peak-to-peak voltage
amplitude of 240 mV and a peak power level of 5.4 dBm,
with good symmetry about the 0 V (ground) level
. The ringing level is also about
24.0 dB, which is somewhat higher than simulated, most probably due to unmodeled substrate coupling and inductive parasitics. The pulse time duration can be tuned over a wide range
and
in the glitch
using the control voltages
generator and Fig. 19 shows the measured pulses with time durations of 375 ps, 525 ps, and 650 ps. Moreover, the phase difand
outputs is about
. It
ference between the
should be noted that the DSA is an equivalent time sampling oscilloscope and not a real-time oscillocope, sampling the signal
only once per trigger event. The DSA is thus triggered using the
input clock for this measurement. Since 24 GHz cycles with a
time period of around 40 ps are clearly visible, the generated
Fig. 20. Calculated normalized PSD of the measured output UWB signals.
oscillations are indeed coherent with the input clock, and thus
pulse-to-pulse coherency is maintained.
The normalized power spectral density (PSD) of the measured signals shown in Fig. 19(a) and Fig. 19(c) was calculated
and is illustrated in Fig. 20. It is apparent that the measured 10
dB bandwidth varies from about 2.7 GHz to 4.9 GHz and is
centered at 23.9 GHz which corresponds to the LO signal frequency. The spectra are also free from spikes or spectral lines
that occur due to LO leakage in typical pulse generators. Furthermore the spectrum roll-off can be quite sharp with more than
23 dB of out-of-band rejection relative to the peak power level
for the pulse in Fig. 19(c).
Table I summarizes the circuit’s characteristics in comparison
with other work [8], [11], [18], [25]–[27]. The proposed pulse
generator offers quadrature tunable outputs with comparable or
2294
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 10, OCTOBER 2011
TABLE I
SUMMARY OF UWB PULSE GENERATOR CHARACTERISTICS
better phase noise at a low energy consumption of 6.2 pJ/pulse.
It is also more energy efficient than most of the other designs if
the energy consumption is normalized with respect to the output
peak-to-peak voltage. Furthermore, the proposed circuit has a
relatively small area compared to the other work.
IV. CONCLUSION
A new quadrature tunable pulse generator has been developed
in 0.13 m CMOS for 22–29 GHz UWB applications. A quadrature LC oscillator is quickly switched on and off for the pulse
duration, and the amplitude envelope is shaped using a variable
passive CMOS attenuator. By switching on one side of each differential oscillator just before the other, a current impulse is injected with a short time duration and large harmonic components out to 24 GHz, creating a large initial condition for fast
startup and setting the initial phase of the oscillations for high
pulse-to-pulse coherence. The measured output phase noise thus
matches that of the clock signal, yielding a relatively low phase
noise of 70 dBc/Hz at 1 kHz offset, and 100 dBc/Hz at 1
MHz offset. This amounts to a low integrated rms jitter from 100
Hz to 1 MHz of less than 720 fs. The attenuator is controlled
with an impulse which is created by a digital, tunable glitch
generator (CMOS NAND gate). Several UWB pulses were measured and demonstrated, with the pulse time duration and 10
dB bandwidth varying over a range of 375–650 ps and 2.7–4.9
GHz respectively. The entire circuit operates in switched-mode
with a low average power consumption of less than 2.2 mW and
14.8 mW at 50 MHz and 600 MHz PRFs, or below 11 pJ for each
of the four differential quadrature pulses. It occupies a total area
of 0.94 mm including bonding pads and decoupling capacitors,
and the active circuit area is only 0.41 mm .
ACKNOWLEDGMENT
The authors would like to acknowledge the products and services provided by CMC Microsystems that facilitated this research, including CAD tools and design methodology, fabrication services using the 0.13 m CMOS technology from IBM,
test support, and engineering services.
REFERENCES
[1] First Report and Order, Revision of Part 15 of the Commission’s Rules
Regarding Ultra Wideband Transmission Systems, ET Docket 98-153,
FCC. Washington, DC, 2002.
[2] I. Gresham, A. Jenkins, R. Egri, C. Eswarappa, N. Kinayman, N.
Jain, R. Anderson, F. Kolak, R. Wohlert, S. Bawell, J. Bennett, and
J.-P. Lanteri, “Ultra-wideband radar sensors for short-range vehicular
applications,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, pp.
2105–2122, Sep. 2004.
[3] M. Klotz, “An automotive short-range high resolution pulse radar network,” Ph.D. dissertation, Dept. Telecommun., Technical Univ. Hamburg, Harburg, Germany, Jan. 2002.
[4] R. J. Fontana, “Recent system applications of short-pulse ultra-wideband (UWB) technology,” IEEE Trans. Microw. Theory Tech., vol. 52,
no. 9, pp. 2087–2104, Sep. 2004.
[5] I. Immoreev and P. Fedotov, “Ultra wideband radar systems: Advantages and disadvantages,” in Proc. IEEE Conf. Ultra Wideband Syst.
Technol., 2002, pp. 201–205.
[6] I. Gresham, A. Jenkins, R. Egri, C. Eswarappa, F. Kolak, R. Wohlert, J.
Bennett, and J.-P. Lanteri, “Ultra wide band 24 GHz automotive radar
front-end,” in Proc. IEEE MTT-S Int. Microw. Symp., Jun. 2003, vol.
1, pp. 369–372.
[7] I. Gresham, N. Kinayman, A. Jenkins, R. Point, A. Street, Y. Lu, A.
Khalil, R. Ito, and R. Anderson, “A fully integrated 24 GHz SiGe receiver chip in a low-cost QFN plastic package,” in Proc. IEEE Radio
Freq. Integr. Circuits Symp., Jun. 2006, p. 4.
[8] V. Jain, S. Sundararaman, and P. Heydari, “A 22–29-GHz UWB pulseradar receiver front-end in 0.18- m CMOS,” IEEE Trans. Microw.
Theory Tech., vol. 57, no. 8, pp. 1903–1914, Aug. 2009.
[9] V. Jain, F. Tzeng, L. Zhou, and P. Heydari, “A single-chip dual-band
22-to-29 GHz/77-to-81 GHz BiCMOS transceiver for automotive
radars,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp.
308–309.
[10] V. Jain, B. Javid, and P. Heydari, “A BiCMOS dual-band millimeterwave frequency synthesizer for automotive radars,” IEEE J. Solid-State
Circuits, vol. 44, no. 8, pp. 2100–2113, Aug. 2009.
[11] A. Scuderi, E. Ragonese, and G. Palmisano, “0.13- m SiGe BiCMOS
radio front-end circuits for 24-GHz automotive short-range radar sensors,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2008, pp. 494–497.
[12] A. Scuderi, E. Ragonese, and G. Palmisano, “24-GHz ultra-wideband
transmitter for vehicular short-range radar applications,” IET Circuits,
Devices, Syst., vol. 3, no. 6, pp. 313–321, Dec. 2009.
[13] E. Ragonese, A. Scuderi, V. Giammello, E. Messina, and G. Palmisano,
“A fully integrated 24 GHz UWB radar sensor for automotive applications,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
2009, pp. 306–307.
[14] T. Hancock, I. Gresham, and G. Rebeiz, “A differential subnanosecond high-isolation absorptive active SiGe 24 GHz switch for
UWB applications,” in Proc. IEEE Radio Freq. Integr. Circuits Symp.,
Jun. 2004, pp. 497–500.
[15] K. Shiojima, T. Makimura, T. Kosugi, T. Suemitsu, N. Shigekawa, M.
Hiroki, and H. Yokoyama, “AlGaN/GaN dual-gate HEMT mixers for
24 GHz pulse-modulation,” in Proc. IEEE Int. Microw. Symp., Jun.
2006, pp. 1331–1334.
[16] J.-C. Li, S. Jung, M. Lu, and K. Min, “A CMOS ultra-wideband transmitter with bi-phase modulation for 22–29 GHz vehicular radar application,” in Proc. IEEE Int. Midwest Symp. Circuits Syst., Aug. 2010,
pp. 449–452.
[17] C.-L. Yang, S.-Y. Shu, and Y.-C. Chiang, “Design of a K-band chip
filter with three tunable transmission zeros using a standard 0.13- m
CMOS technology,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57,
no. 7, pp. 522–526, Jul. 2010.
EL-GABALY AND SAAVEDRA: QUADRATURE PULSE GENERATOR FOR SHORT-RANGE UWB VEHICULAR RADAR APPLICATIONS
[18] A. Oncu, B. W. Badalawa, and M. Fujishima, “22–29 GHz ultra-wideband CMOS pulse generator for short-range radar applications,” IEEE
J. Solid-State Circuits, vol. 42, no. 7, pp. 1464–1471, Jul. 2007.
[19] N. Deparis, C. Loyez, N. Rolland, and P.-A. Rolland, “UWB in millimeter wave band with pulsed ILO,” IEEE Trans. Circuits Syst. II, Exp.
Briefs, vol. 55, no. 4, pp. 339–343, Apr. 2008.
[20] A. T. Phan, J. Lee, V. Krizhanovskii, Q. Le, S.-K. Han, and S.-G. Lee,
“Energy-efficient low-complexity CMOS pulse generator for multiband UWB impulse radio,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 55, no. 11, pp. 3552–3563, Dec. 2008.
[21] X. Wang and A. Apsel, “Pulse coupled oscillator synchronization for
low power UWB wireless transceivers,” in Proc. IEEE Int. Midwest
Symp. Circuits Syst., Aug. 2007, pp. 1524–1527.
[22] E. Blokhina, O. Feely, J. Ricart, and M. Dominguez, “On some properties of the output of a pulsed digital oscillator working with multiple
resonances,” in Proc. IEEE Int. Symp. Circuits Syst., May 2010, pp.
1320–1323.
[23] T. Wuchenauer, M. Nalezinski, and W. Menzel, “UWB pulse oscillator
at 24 GHz with 2.1 GHz bandwidth for industrial radar sensor applications,” in Proc. IEEE Int. Microw. Symp., Jun. 2007, pp. 839–842.
[24] A. Kryshtopin, G. Sevskiy, K. Markov, P. Heide, M. Nalezinski, R.
Roskosch, and M. Vossiek, “Cost-minimized 24 GHz pulse oscillator
for short-range automotive radar applications,” in Proc. Eur. Microw.
Conf., Oct. 2003, vol. 3, pp. 1131–1134.
[25] D. Kim, D. Kim, and S. Hong, “A 24-GHz power-efficient MMIC pulse
oscillator for UWB radar applications,” Microw. Opt. Technol. Lett.,
vol. 49, no. 6, pp. 1412–1415, 2007.
[26] T. Teshirogi, S. Saito, M. Uchino, M. Ejima, K. Hamaguchi, H. Ogawa,
and R. Kohno, “Residual-carrier-free burst oscillator for automotive
UWB radar applications,” Electron. Lett., vol. 41, no. 9, pp. 535–536,
Apr. 2005.
[27] Y. Kawano, Y. Nakasha, K. Yokoo, S. Masuda, T. Takahashi, T. Hirose,
Y. Oishi, and K. Hamaguchi, “RF chipset for impulse UWB radar using
0.13- m InP-HEMT technology,” IEEE Trans. Microw. Theory Tech.,
vol. 54, no. 12, pp. 4489–4497, Dec. 2006.
[28] J. Ryckaert, M. Verhelst, M. Badaroglu, S. D’Amico, V. De Heyn, C.
Desset, P. Nuzzo, B. Van Poucke, P. Wambacq, A. Baschirotto, W.
Dehaene, and G. Van der Plas, “A CMOS ultra-wideband receiver for
low data-rate communication,” IEEE J. Solid-State Circuits, vol. 42,
no. 11, pp. 2515–2527, Nov. 2007.
[29] N. Karandikar, S. Jung, S. C. Lee, P. Gui, and Y. Joo, “Design of an
analog correlator for 22–29 GHz UWB vehicular radar system using
improved high gain multiplier architecture,” in Proc. IEEE Int. Midwest
Symp. Circuits Syst., Aug. 2010, pp. 930–933.
[30] T. Lee and A. Hajimiri, “Oscillator phase noise: A tutorial,” IEEE J.
Solid-State Circuits, vol. 35, no. 3, pp. 326–336, Mar. 2000.
[31] A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May
1999.
[32] H.-R. Kim, C.-Y. Cha, S.-M. Oh, M.-S. Yang, and S.-G. Lee, “A very
low-power quadrature VCO with back-gate coupling,” IEEE J. SolidState Circuits, vol. 39, no. 6, pp. 952–955, Jun. 2004.
[33] J.-P. Hong, S.-J. Yun, N.-J. Oh, and S.-G. Lee, “A 2.2-mW backgate
coupled LC quadrature VCO with current reused structure,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 4, pp. 298–300, Apr. 2007.
[34] B. van der Pol, “The nonlinear theory of electric oscillations,” Proc.
IRE, vol. 22, no. 9, pp. 1051–1086, Sep. 1934.
2295
[35] D. Barras, F. Ellinger, H. Jackel, and W. Hirt, “Low-power ultra-wideband wavelets generator with fast start-up circuit,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 5, pp. 2138–2145, May 2006.
[36] H. Kim and Y. Joo, “Fifth-derivative gaussian pulse generator for UWB
system,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2005,
pp. 671–674.
[37] Y. Jeong, S. Jung, and J. Liu, “A CMOS impulse generator for UWB
wireless communication systems,” in Proc. IEEE Int. Symp. Circuits
Syst., May 2004, vol. 4, pp. 129–132.
[38] Y. Zhu, J. Zuegel, J. Marciante, and H. Wu, “A 10 GS/s distributed
waveform generator for sub-nanosecond pulse generation and modulation in 0.18 m standard digital CMOS,” in Proc. IEEE Radio Freq.
Integr. Circuits Symp., Jun. 2007, pp. 35–38.
Ahmed M. El-Gabaly (S’07) received the B.A.Sc.
degree in computer engineering from the University
of Waterloo, ON, Canada, in 2005 and the M.Sc.
(Eng.) degree from Queen’s University, Kingston,
ON, in 2007. Since September 2007 he has been
working toward the Ph.D. degree at Queen’s University undertaking research in the area of RF and
microwave integrated circuits.
Throughout his undergraduate career, he worked
on several co-op jobs including embedded software
development at Intellon Canada Ltd, where he
quality-assured and assisted the design of an ARM9-based system-on-chip
(SoC) for powerline OFDM communications. For his Master’s degree, he
researched and developed high-speed direct-digital QPSK modulators for
low-power short-range wireless communications. His current research activities are in high-frequency, low-power ultrawideband (UWB) pulse generators
and switched RF circuits for communications, biological and automotive
applications.
Carlos E. Saavedra (S’92-M’98-SM’05) received
the B.Sc. degree from the University of Virginia,
Charlottesville, and the M.Sc. and Ph.D. degrees
from Cornell University, Ithaca, NY, all in electrical
engineering.
From 1998 to 2000 he was with Millitech Corporation, South Deerfield, MA. Since August 2000 he
has been with the Department of Electrical and Computer Engineering, Queen’s University, Kingston,
ON, Canada, where he is now an Associate Professor
and the Coordinator of Graduate Studies (Graduate
Chair). His research interests are in the field of very high frequency integrated
circuits and systems for communications, radar, and biomedical applications.
Prof. Saavedra is the Vice-Chair of the IEEE MTT-S Technical Committee 22
and is a member of the Technical Program Committee of the IEEE RFIC Symposium. He is a reviewer for several journals including the IEEE TRANSACTIONS
ON MICROWAVE THEORY AND TECHNIQUES, IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS—PART II, and Electronics Letters.
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertisement