Taiwan Liton Electronic Co., Ltd.
 FEATURES
0.3 INCH (7.62 mm ) DIGIT HEIGHT.
FOUR-DIGIT,RIGHT HAND DECIMAL.
WIDE SUPPLY VOLTAGE OPERATION.
SERIAL DATA INPUT.
CONSTANT CURRENT DRIVERS.
CONTINUOUS BRIGHTNESS CONTROL.
OUTPUT AVAILABLE FOR TWO EXTERNAL LEDS.
WIDE VIEWING ANGLE.
TTL COMPATIBLE.
DESCRIPTION
The LTM-8328PKR-04 is a 0.3 inch (7.62mm) digit
display. It has a built-in M5450 MOS IC that contains
serial data input and 35 bit shift control. The MOS IC
produced with N-channel silicon gate technology. This
device utilizes bright red LED chips, which are made
from GaP on a transparent GaP substrate. Have black
face with diffusion tape.
DEVICE
PART
NO
Bright red
LTM-8328PKR-04
DESCRIPTION
FOUR DIGIT R.H.D.P,
WITH I.C DRIVER
PACKAGE DIMENSIONS
NOTES: All dimensions are in millimeters. Tolerances are ± 0.25mm(0.01“) unless otherwise noted.
PIN CONNECTION
NO.
CONNECTION
NO.
CONNECTION
1
EXT LED1
6
VDD
2
EXT LED2
7
DIMMER
3
DATA ENABLE
8
GND
4
DATA SERIAL
9
VLED
5
CLOCK
SERIAL DATA INPUT SEQUENCE
BIT
DIGIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
SEGMENT BIT
A
B
C
D
E
F
G
DP
A
B
C
D
E
F
G
DP
A
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
DIGIT
SEGMENT
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
B
C
D
E
F
G
DP
A
B
C
D
E
F
G
DP
LED1
LED2
ABSOLUTE MAXIMUM RATING AT TA=25oC
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VDD
-0.3
12
V
VI
VO(off)
-0.3
12
12
V
V
VLED
2.8
3.5
V
PD(IC)
335
mW
Supply Current
IDD
8.5
mA
Operating Temperature
Range
Storage Temperature Range
TOP
-20
+60
0
C
Tstg
-20
+60
0
C
Supply Voltage
Input Voltage
Off State Output Voltage
LED Supply Voltage
Power Dissipation of IC
Solder Temperature: inch Below Seating Plane for 3 Seconds at 2600C
NOTE:1.All Voltages are with respect to VSS(GND).
2.Power dissipation of IC is given by PD =( VLED - VF) • (IF) • (NO. of Segments)
+ (8.5mA) • (VDD)
* VF is LED forward voltage.
RECOMMENDED OPERATING CONDITION AT TA=25oC
PARAMETER
Supply Voltage
Input Voltage
Logical “0” Level
Logical “1” Level
Logical “1” Level
Brightness Input Current
Brightness Input Voltage
SYMBOL MIN.
VDD
4.75
VI
IB
VB
Off State Voltage
Ouput Sink Current
Segment Off
Segment On
VO(off)
Input Clock Frequency
Ouput Matching
FCLOCK
IO
TYP.
-0.3
2.2
VDD-2
0
3
MAX.
11
UNIT
V
TEST CONDITION
0.8
VDD
VDD
0.75
4.3
V
V
V
mA
V
±10uA Input Bias
4.75V< VDD<5.25V
VDD > 5.25V
11
V
10
uA
mA
mA
MHZ
%
3
6
0
0.5
±20
Input Current
=750uA
IB=0uA
IB=100uA
IB=200uA
ELECTRICAL OPTICAL CHARACTERISTICS AT TA=25oC
PARAMETER
SYMBOL MIN. TYP. MAX. UNIT TEST CONDITION
Average Luminous Intensity
Peak Emission Wavelength
Spectral Line Half-Width
Dominant Wavelength
Luminous Intensity Matching Ratio
Iv
p
!
d
Iv-m
79
155
ucd
IB=0.4mA
697
nm
IB=0.4mA
90
nm
IB=0.4mA
638
nm
IF=20mA
2:1
IB=0.4mA
FUNCTIONAL DESCRIPTION
Serial data transfer from the data source to the display driver is accomplished with 2
signals serial data and clock. Using a format of a leading “1” following by the 35 data bits
allows data transfer without an additional load signal. The 35 data bits are latched after the
36th bit is completed, thus providing non-multiplexed, direct drive to the display. Outputs
change only if the serial data bits differ from the previous time.
Brightness of display is determined by control the 0utput current of LED display. A 1nF
capacitor should be connected to brightness control, Pin 7 to prevent possible oscillations.
The output current is typically 25 times greater than the current into Pin 7 which is set by an
external variable resistor. There is an internal limiting resistor of 400Ω nominal value.
Figure 1 shows the input data format. A start bit of logical “1” proceed the 35 bits of data. At
the 36th clock, a LOAD signal is generated synchronously with the high state of the clock,
which loads the 35 bits of the shift registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift registers for the next set of data. The
shift registers are static master-slave configuration. There is no clear for portion of the first
register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers won’t clear. When power
is first applied to the chip an internal power ON reset signal is generated which reset all
registers and all latched. The ATART bit and first clock return the chip on its normal
operation. Bit 1 is the first following the start bit and it will appear on the Figure 2 shows the
timing relationship between data clock, and DATA ENABLE. A maximum clock frequency of
0.5 MHz is assumed.
FIGURE.1 Input Data Format
FIGURE.2 Timing Relationship
Mouser Electronics
Authorized Distributor
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LTM-8328PKR-04
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