1973 , Volume , Issue Nov-1973

1973 , Volume , Issue Nov-1973
NOVEMBER 1973
HEWLETT-PACKARDJOURNAL
© Copr. 1949-1998 Hewlett-Packard Co.
A Self-Contained, Hand-Held Digital
Multimeter — A New Concept in Instrument
Utility
Aside from clipping the coiled lead to any convenient refer
ence point, only one hand is needed to hold this instru
ment, and take a reading.
by Robert L. Dudley and Virgil L. Laing
IT IS GENERALLY ACCEPTED that a multimeter
for measuring voltage and resistance is an indispensible tool for service specialists, technicians and
engineers. There have been many improvements in
the last few years, such as digital readout, high input
impedance, better accuracy and resolution, and
these improvements have helped the user make
measurements more precisely with fewer errors. Lit
tle has been done, however, to make the multimeter
easier to use and better suited to the technician or
engineer who needs to make fast measurements in
hard-to-get-at places.
Shown in Fig. 1 is a new battery-powered 3l/2 di
git Probe Multimeter that is completely self-con
tained and can be held and operated in one hand.
The instrument has autoranging, autopolarity, and
autozero, which means the user need only set the
function switch and depress the power bar to get an
accurate reading.
To use the instrument, the coiled lead is attached
to a suitable ground or reference point, and the
probe tip is placed on the point to be measured.
When the power switch is pressed, the voltage or re
sistance value appears on the display with range
and polarity automatically selected.
Several advantages of this probe configuration
are apparent. Portability is an obvious one, and the
location of the display close to the point of measure
ment speeds reading time while eliminating the
need to shift the eyes to get a reading.
Another advantage is the ability to invert the dis
play to facilitate readings when the Probe is held
upside-down to reach a hard-to-get-to place (Fig.
2). In addition, the probe tip can be pivoted into
three detented positions: straight, tilted at 30°, and
tilted at 60°. The tip can be folded back so that the
Probe can be carried in a pocket or the belt-carrying
case provided with the instrument.
A Real Instrument
This hand-held instrument is a true digital multi
meter with three digits of readout plus a "1" for 10%
overranging. The most sensitive range for both ac
and dc measurements is 100 mV full scale with
0.1 mV resolution. Although the input is protected
up to 1000 V, for safety reasons the maximum input
voltage is specified at 500 V.
The accuracy of readings is better than 1% for dc
voltages and between 2 and 5% for ac. The input
Cover: The hand-held digi
tal multimeter -a concept
that's been in the back of
many an engineer's mind
ever since integrated circuits
went large-scale-has be
come a reality. Doing it re
quired more than an integ
rated circuit, however; it re
quired a combination of technologies as de
scribed here. (Zero is added to 3-digit display
here to indicate range.)
In this Issue:
A Self-Contained, Hand-Held Digital
Multimeter-A New Concept in Instru
ment Utility, by Robert L. Dudley and
V i r g i l L . L a i n g
p a g e 2
A Portable High-Resolution Counter for
Low-Frequency Measurements, by
Kenneth J. MacLeod
page 10
A High-Speed Pattern Generator and
an Error Detector for Testing Digital
Systems, by Thomas Crawford, James
Robertson, John Stinson, and Ivan
Y o u n g
p a g e
1 6
-PACKARD COMPANY 1973
PRINTED IN U SA
© Copr. 1949-1998 Hewlett-Packard Co.
Fig. 1. Model 970 A Digital Multimeter was designed for con
venient hand-held operation. The user needs only to select
the desired function and press the power switch (the long,
'lat bar) to lake a reading • •••••. • hart rt , .
lects the right measurement range.
impedance is 10 megohms paralleled by less than
30 pF. The ac frequency range is up to 3500 Hz,
wide enough for power line and most voice-chan
nel measurements.
As an ohmmeter, the new multimeter has fullscale ranges from 1 to 10,000 kilohms with a resolu
tion of 1 ohm on the lowest range. The accuracy of
ohms readings is better than 2%. In all functions,
the instrument displays a reading in less than 2 se
conds after the switch is pressed (to speed this up,
it starts at mid-range and then ranges in the appro
priate direction). In continuous operation, it makes
3 readings per second.
The Ni-Cad batteries that power the instrument
can operate continuously for a minimum of 2Vz
hours before needing recharge, but by pressing the
switch only when a reading needs to be taken, the
user can make at least 2000 readings on one charge.
The power switch has a lock position for those occa
sions when continuous monitoring may be desired.
For recharge, the batteries slip out of the instru
ment and into a charger that plugs into a wall outlet
(see Fig. 12 ). Where heavy use is anticipated, an ex
tra set can be obtained so one set can be recharging
while the other is used in the instrument.
lowest possible cost consistent with traditional HP
dependability. As the circuit design evolved it be
came apparent that the circuits could be contained
within a surprisingly small space at modest cost, us
ing recently-developed monolithic and thin-film
hybrid integrated-circuit technologies. Thus, a
hand-held, self-contained instrument was a possi
ble configuration to be considered.
Other than the obvious operating conveniences,
other advantages would accrue from a hand-held
configuration. Since the display would be close to
the point of measurement, it would not have to be
read from a distance and therefore could be small
and more economical. The miniature LED display
developed for the HP hand-held calculators was
ideal for this situation, and it uses less power than a
larger display. Since the display could be in line and
close to the point of measurement, a press-to-read
type of operation could be used to further conserve
power. Hence smaller batteries could be used. It
was decided, then, to place project emphasis on pro
viding the multimeter capability in a hand-held in
strument.
Many shapes and configurations were evaluated.
The elliptical cross-section was adopted as this fits
the hand comfortably while providing a tactile clue
as to the orientation of the instrument. In keeping
with the concept of hand-held convenience, the
case surface is textured to minimize slippage. The
problem of where to place a multi-position function
switch was solved by development of the "watchband" switch. The power switch was designed as a
bar that can be operated along most of its length.
This, plus the invertible display and swiveled
Design Philosophy
The original objective at the start of the design
phase was to design a SVi-digit multimeter at the
© Copr. 1949-1998 Hewlett-Packard Co.
Fig. 2. Slide switch adjacent to the display inverts the numer
als so readings can be taken with the probe upside down.
to V,
i n
Fig. 3. Digital-to-analog conver
sion by the dual-slope technique
is essentially a voltage-to-time
conversion with digital measure
ment of the resulting time inter
val.
t .
probe tip, allows the instrument to be used conven
iently in a variety of positions. To protect the user
against accidental contact to high voltages, the in
strument was designed so there are no exposed me
tallic parts anywhere on the instrument, except for
the probe tip and the ground clip.
Inside
The Probe Multimeter is an integrating digital
voltmeter that employs the widely-used dual-slope
technique to derive a digital display from a dc vol
tage. Although described recently in this publica
tion1, the description is repeated here for the sake of
completeness.
With reference to the timing diagram of Fig. 3 , at
time tj the unknown input voltage Vin is applied to
the integrator. Capacitor Cl then charges at a rate pro
portional to Vin.
The counter starts totalizing clock pulses at time
tt and when a predetermined number of clock pulses
has been counted, the control logic switches the in
tegrator input to Vref, a known voltage with a polarity
opposite to that of Vin. This is at time t2. Capaci
tor Cl now discharges at a rate determined by Vref.
The counter is reset at time t2 and again it counts
clock pulses, continuing to do so until the compara
tor indicates that the integrator output has returned
to the starting level, stopping the count. This is at
time t3.
The count retained in the counter is proportional
to the input voltage. This is because the time taken
for capacitor Cl to discharge is proportional to the
charge acquired, which in turn is proportional to the
input voltage. The number in the counter is then dis
played to give the measurement reading.
The attractive characteristic of this technique is
that many of the variables are self-cancelling. For
example, long-term changes in the clock rate or in
the characteristics of the integrator amplifier, resis
tor, or capacitor affect both the charge and dis
charge cycles alike. Considerable long-term devia
tion from normal values can be tolerated without in
troducing errors.
Also, since the input voltage is integrated during
the up slope, the final charge on Cl is proportional
to the average value of the input during the charge
cycle. Noise and other disturbances are thus aver
aged out and have a reduced effect on the measure
ment. In particular, by making the charging cycle
equal to an integral number of power line cycles,
the effect of any power line hum is reduced by a sub
stantial amount.
The Overview
A block diagram of the new multimeter is shown
in Fig. 4. The input is applied to amplifier Al,
which has feedback resistors that can be switched
to change gain and hence the sensitivity range. The
10-megohm resistor in series with the input, be
sides being an essential part of the amplifier con
figuration, also provides protection against high in
put voltages.
The offsets in the amplifiers and integrator are
compensated for by an autozero technique similar
to that used in other HP digital multimeters.1 Just
prior to the integration cycle (see Fig. 4), MOSFET
switches disconnect the input signal and connect a
matching 10-megohm resistor to the input of ampli
fier Al. In the autozero mode, the comparator oper
ates as a high-gain amplifier and a feedback loop is
© Copr. 1949-1998 Hewlett-Packard Co.
Fig. 4. FUNCTION block diagram of Model 970A Digital Multimeter. Except for the FUNCTION
switch, chip. the switches shown here are MOSFET switches on the main monolithic 1C chip.
closed around the input amplifier, integrator, and
comparator, charging the autozero capacitor C2 to a
voltage that compensates for the offset voltages in
the entire feedback loop. When the input is recon
nected to amplifier Al, the feedback to C2 is discon
nected but the charge on C2 remains during the
measurement to compensate for the offsets. The au
tozero circuit thus eliminates the requirement for a
zero-adjust potentiometer.
Following the input amplifier, dc voltages are ap
plied to the integrator for conversion to digital
form. A number of changes were made, however, to
the standard dual-slope integration to enhance the
operation of the Probe Multimeter. For example, by
using an integration time of 1/6 second on some
ranges rather than 1/60 second (1/5 and 1/50 second
in European versions), sensitivity can be increased
by a factor of 10. Then, only three range resistors,
providing 100:1 steps, are needed in the input am
plifier with switching of the integration time to
give the 10:1 range steps. This reduces the number
of resistors and interconnections required in the
feedback loop around the input amplifier.
With reference to the logic diagram of Fig. 5 , oper
ation of the A-to-D converter is as follows.
The counter is a modulus 3000 counter, which is
used to provide qualifying signals to the control lo
gic as well as to help perform the analog-to-digital
conversion. The counter is counting at time t0 and
the control logic maintains the autozero mode un
til the counter reaches the point at which either
159 or 1590 counts are left before it resets, depend
ing on whether the range requires the short integra
tion time (159 counts) or the long integration time
(1590 counts). The integrator is then connected to
the input amplifier and the integrator output ramps
either up or down, depending on the polarity of the
input signal.
When the counter reaches 3000 counts, the com
parator output is sampled to determine whether
the positive or negative reference voltage is to be
connected to the integrator to return the output vol
tage to the starting level. When the comparator out
put is negative, the integrator output voltage goes in
a positive direction when the reference voltage is
connected, and the minus sign appears in the dis
play. If the comparator output voltage is positive,
the integrator output will decrease in a negative
direction, and the minus sign will not appear.
When the comparator output voltage goes
through zero volts and changes sign, the counter
reading is tested for greater-than 1100 counts. If the
© Copr. 1949-1998 Hewlett-Packard Co.
HI R» LO
( 1 V
P e l )
" i n
Fig. 6. Input configuration for resistance measurements.
C3, full-wave rectification is used. This is accom
plished with inverter A3, which overrides the out
put of A2 on positive-going signal excursions at its
output .
Resistances are measured by supplying a 1-volt
reference signal to the input amplifier through a
range resistor and configuring the amplifier to
place the unknown as the feedback resistor, as
shown in Fig. 6 . The amplifier output is proportion
al to the ratio of the unknown resistance to the
range resistor.
To protect the ohms circuit from inadvertent ap
plication of an external voltage, a series resistor
protects the input and it also acts as a fuse for vol
tages greater than 130 volts. This resistor is clipmounted to the circuit board so that it can be replaced
easily without soldering.
Power Supply
Fig. 5. Flow diagram of control logic in Multimeter's analogto-digital converter.
counter output is greater than 1100 counts, the in
strument is up-ranged one range and resequenced
through an integrator recovery phase, to re-zero the
integrator, and then sequenced to the autozero
phase to repeat the measurement.
If the count is less than 1100 counts, the counter
output is transferred to the display and is tested for
less than 100 counts. If the count is less than 100,
the instrument is down-ranged one range, and rese
quenced through the integrator recovery and autozero phases.
Multimeter Operation
Ac voltages are rectified to derive a dc voltage
proportional to the average value of the ac wave
form calibrated to the rms value for a sine wave,
and the resulting dc voltage is applied to the inte
grator. To minimize the size of the filter capacitor
A single 10-volt battery pack supplies all power
for operation of the multimeter. Positive and nega
tive reference voltages are established by tying the
ground to a tap in a resistive divider that spans the
battery (Fig. 7 ). Actually, three ground reference
points are established: (1) analog circuit ground; (2)
logic circuit ground; and (3) LED display ground.
Separation of the analog circuit ground from the
other grounds is necessary to prevent digital circuit
transients from interfering with operation of the an
alog circuits, and to provide proper voltages for
MOS switching.
As shown in the diagram, the analog and logic
grounds are isolated from the resistive divider by
operational amplifiers that provide low impedance
sources for the ground circuits. The voltage across
the resistive divider is maintained constant
through all useful levels of battery charge by a
zener diode with a thermistor providing compensa
tion for the temperature characteristics of the zener.
If the zener voltage should drift with age, it can be
compensated for with the potentiometer provided.
This is the only circuit adjustment required in the
entire instrument.
© Copr. 1949-1998 Hewlett-Packard Co.
Number
Decode ROM BCD - 7 S«g
D e e * d *
/
D e c o d e r
Counter» / _
Scanner
Analog. »"*> "»"9« ,
Switch.. Conlro1 Counter /
Logic
Decimal
St««fing
Segment
Drivers
Analog
Switch**
Fig. 8. As much of the circuitry as possible was placed on
one custom-made monolithic 1C chip. This chip has 40 flipflops, 19 MOSFET switches and about 3500 bits of ROM.
Fig. 7. Power supply isolates analog circuit ground from
other grounds to minimize coupling of transients.
The LED display circuits work directly from the
battery. As the battery charge depletes, the LED dis
play dims and finally becomes unreadable, indicat
ing that the battery needs recharging. The accuracy
of readings is affected by only 1 or 2 counts in the
least significant digit when the battery level is too
low for a readable display, so this is a practical
way to indicate the need for battery recharging.
Putting It All Together
Circuit simplification was a key factor in making
the Probe Multimeter feasible. One step taken was
to do as much digitally as possible because digital
circuits can be implemented very inexpensively.
For example, digital comparison, rather than ana
log comparison, is used to trigger autorange
changes.
As much of the circuitry as possible was put on
one monolithic integrated circuit, a 150 x 170 mil
chip (3.9 x 4.3 mm) made by an N-MOS process
developed for the 4096-bit ROM's used in HP calcu
lators. This chip (Fig. 8) includes the counters,
buffer storage, code conversion for the display, dis-
play scanner, autorange circuits, several ROM's
that store the programs needed to operate the multi
meter (approximately 3500 bits are stored in ROM),
and most of the analog switching.
A distinct advantage of placing all of the digital
circuitry on a single chip is the large reduction in
the number of interconnections required. This is
particularly true in the case of the analog switches
required for the analog-to-digital conversion and
autoranging. The simplified circuit in Fig. 9
shows how this is accomplished. All of the MOS
FET gates as well as many of the sources and drains
are connected internally on the MOS chip. Only
three mechanical switches are required to operate
the instrument: the power switch, function switch,
and display invert switch. The remaining 19
switches are on the MOS chip.
As much as possible of the remaining circuitry
was put on a 28 x 38 mm thin-film hybrid circuit
(Fig. 10 ). This includes six operational amplifiers
(three chips, each with two op amps), the compara
tor, one chip with the two input FET's, the bipolar
current amplifier that drives the display, four diode
chips (rectifiers and protection diodes), capacitor
chips, high-value resistor chips, and tantalum-ni
tride thin-film resistors.
For resistors with values higher than is practical
with this thin-film process (greater than 60k ohms),
resistor chips bonded to the substrate are used if the
value is not critical, e.g. a pull-up resistor. But
where accuracy and stability are required, such as
in the high-value range resistors, discrete resistors
mounted on a circuit board are used. To minimize
size and cost, resistors with accuracies specified
within 1% were chosen, rather than the larger high-
© Copr. 1949-1998 Hewlett-Packard Co.
i — VWo-u_j-é-
Fig. 9. Simplified diagram of the
input amplifier and integrator in
put shows how MOSFET
switches are used. Only ten ex
ternal connections are required
for eight switches.
V
precision resistors. However, a small-value thinfilm resistor is in series with each of these resistors,
and the thin-film resistors are laser trimmed to give
the series combination the 0.1% accuracy desired.
The thin-film resistors have a stability of 0.01% per
year and a temperature coefficient of approximately
-75 ppm/°C.
Resistor trimming on the thin-film substrate is ac
complished by a computer-controlled laser trim sys
tem. The value of a tantalum-nitride thin-film resis
tor is increased in steps by opening selected gold
shorting bars placed across small and medium size
resistive segments of the resistor. By this method, a
resistor can be trimmed in a few seconds to an
accuracy of 0.01%. An entire circuit can be function
ally calibrated by actively trimming resistors to
compensate for parameters such as amplifier gain,
input offset voltages, and so on. In addition to trim-
ming resistors, the computer-controlled system pre
tests the substrate and printed-circuit board prior to
trimming, and functionally tests the entire circuit
after trim.
The printed-circuit board (Fig. 11 ) also holds the
LED display cluster, large-value, high-voltage capa
citors, power supply zener diode and its compensat
ing thermistor, power supply trimmer pot, and the
power switch, as well as the thin-film substrate.
Computer or calculator controlled tests are per
formed at various stages in the production process,
beginning with evaluation of the MOS chip and fin
ishing with evaluation of the completed instru
ment. These automated tests are far more thorough
than would be economically feasible with manual
point-by-point tests and are a major contribution to
wards the realization of quality at low cost.
MOS Chip
(Logic and SW.ICUMI
* I I I I I- V t »• I 1/1 I I
f K r.' h> (• i *fcx//i
/ / I n t e g r a t o r u , , , ,t J FET V
»"»«"- mput
Fig. 10. Thin-film hybrid circuit contains the stable, lasertrimmed resistors and also serves as a high-density inter
connect for the other circuits.
© Copr. 1949-1998 Hewlett-Packard Co.
Fig. the Thin-film hybrid circuit mounts on the back side of the
printed-circuit board that holds discrete components. All of
the multimeter's electrical components, except for the bat
tery and the invert-display switch are shown here.
SPECIFICATIONS
General
HP Model 970A Digital Multimeter
DC Voltmeter
RANGES: 0 1 V. 1 V, 10 V. 100 V. 1000 V. (500 V max input)
ACCURACY (20° C lo 30' C):
±(07% ol reading + O 2% of range}
INPUT RESISTANCE: 10 MU, ±5%.
INPUT PROTECTION: - 1000 V peak
TEMPERATURE COEFFICIENT: :±(0 05% of reading + 002% ol
range)/' C.
AC Voltmeter
RANGES: 0 1 V. 1 V. 10 V. 100 V. 1000 V (500 V rms Sine wave max
input)
RESPONSE: Responds lo average value of input waveform; cali
brated to the rms value for sine waves.
ACCURACY (20° C to 30' C):
INPUT IMPEDANCE: 10 UU (*5%)//<30 pF
INPUT PROTECTION: -_ 1000 V peak
TEMPERATURE COEFFICIENT: :±{0 05% of reading + 005% of
range)/' C
Ohmmeter
RANGES: 1 k'J 10 k-.J, 100 k<J. 1000 k'J. 10,000 k'..>
ACCURACY (20' C to 30° C): (±1 5% of reading + 0.2% of range)
INPUT VOLTAGE PROTECTION (resistor fused): '"115 V rms lor up
to 1 minute • 250 V rms for up to 10 seconds
TEMPERATURE COEFFICIENT: ±(005% of reading -f 002% ol
range)/' C.
Acknowledgments
The circuit design team consisted of Paul Febvre,
HarÃ-an Talley, Joe Marriott, Harry Heflin, and the
authors. The mechanical design was accomplished
by Dave Brown, Paul Febvre, Don Aupperle (indus
trial design), Gary Peterson, Roy Buck, and Bob
Slutz.
Grateful acknowledgment is extended to Terry
Pierce (1C R&D Supervisor), John Shea (MOS pro
cessing), Bob Jarvis and Bill Bruce (substrate layout
and laser trim), LeMoyne Hadley (pre-test and func
tional test), Roy Barker (production manager), Den
nis Colard (production supervisor), Marsh Faber
and Jack Morrison (evaluation and life test), Les
Wollschlaeger (reliability test), Glenn Gibson (parts
coordination), and Rob Thurston (current shunt
and accessory design).
The authors are indebted to Bill Beierwaltes,
Marketing Coordinator, and Dick Moore, R&D Mana
ger, for many helpful suggestions. S
A/D CONVERSION: Dual Slope
RANGING: Automatic
SAMPLE RATE: 3/second
OVERRANGE: 10%.
OPERATING TEMPERATURE RANGE: 0' C to 40' C.
POWER: Rechargeable batteries
TYPICAL OPERATING TIME ¡fully charged battery). 25 hours con
tinuous at 25 C.
TYPICAL BATTERY CHARGING TIME: -14 hours (Indefinite Charg
ing will not damage battery.)
WEIGHT (with battery pack): 7 02 (200 g)
DIMENSIONS: 1'. m x 1* m x 6V, m (32 x 45 x 165 mm)
PRICE IN U.S.A.: HP 970A, 1275.
Extra Rechargeable Battery Pack: 125
MANUFACTURING DIVISION: LOVELANO DIVISION
815 Fourteenth Street. S W
Loveland, Colorado 80537
References
1. A. Gookin, "Compactness and Versatility in a New PlugTogether Digital Multimeter," Hewlett-Packard Journal,
August 1972.
Fig. 12. Model 970 A Digital Multimeter is supplied in a kit
that includes a belt-mounted carrying case and a sunshade
in addition to the three probe tips and battery charger. The
battery pack (lower left) is shown here removed from the
instrument.
ing the N-MOS process for the 4096-bit ROM's used in the
9800-series Calculators. Transferring to instruments, he
designed a major part of the N-MOS circuitry in the Probe
Multimeter and later became group leader for probe pro
ducts development. An outdoor sports enthusiast, Virgil also
enjoys hiking and camping with his family and pheasant
hunting with his two German Shorthair Pointers.
Robert L. Dudley (Left)
Virgil L Laing (Right)
Fresh out of the University of Minnesota with bachelor's,
master's, and PhD degrees in electrical engineering, Virgil
Laing went to work for the Loveland Division's 1C department
in 1968, subsequently becoming project leader for develop
Among the many products Bob Dudley had project respon
sibility for since joining HP in 1959 are the 690-series Micro
wave Sweep Oscillators, the 3300A Function Generator, and
the 3469A Digital Multimeter. As a group leader, he was al
so involved with the 204C and 209A Oscillators, the 331 OA
Function Generator, and the 970A Probe Multimeter. At
present, he is section manager in charge of basic instru
ments. Bob obtained a Bachelor's degree in Engineering
Science from Brigham Young University and later under the
HP Honors Co-op program, an MSEE from Stanford. He en
joys golf and goes skiing on water or snow. He's also been
president of the Loveland Optimist Club, regional music
leader for his church, as well as a high council member, and
student-activities chairman of the IEEE Denver section.
© Copr. 1949-1998 Hewlett-Packard Co.
A Portable High-Resolution Counter for
Low-Frequency Measurements
This snap-on functional module for the low-cost 5300 Mea
suring System makes six-digit measurements of frequen
cies between 0.833 Hz and 2 MHz. Special features help
solve many low-frequency measurement problems.
by Kenneth J. MacLeod
DIRECT FREQUENCY COUNTERS provide a sim
ple and accurate means of measuring the fre
quencies of electrical signals in the range from a few
kilohertz to hundreds of megahertz. However, they
suffer from reduced resolution at frequencies below
this range. This is an unavoidable consequence of
simply counting the number of periods of the signal
during some gate time, typically one second. At 60
kHz, for example, the display will read 60000 ±1
in a one second measurement, but at 60 Hz the read
ing will be only 60 ±1. The ±1 count uncertainty
is caused by the random phase of the input signal at
the time the gate opens.
Model 5307 A High-Resolution Counter (Fig. 1) is
designed for users who need to measure low fre
quencies with higher resolution than is possible
with direct counters, without resorting to longer
measurement times. The new counter is a snap-on
functional module for the 5300 Measuring Sys
tem.1-2 In less than one second it counts any input
frequency from 5 Hz to 2 MHz (or 0.833 Hz to 166
kHz in counts/minute mode) and displays a six-di
git answer with appropriate decimal point and an
nunciator lights.
Because many of its potential users are outside
the electronics laboratory, the new counter is de
signed to be easy to operate, even by someone not
skilled in electronics. The counter is fully autoranging. For simple measurements, none of the frontpanel buttons need be pressed and the sensitivity
knob may be left in the fully clockwise position. If a
frequency below 5 Hz is connected to the input, the
gate light will blink slowly and the display will
show 000000, clearly indicating an underrange con
dition.
As part of the 5300 Measuring System, the new
counter is portable and has a rugged case. It is small
and light, and can be battery powered using the
5310A Battery Pack.1 Digital (BCD) output for re
cording measurements is standard on the 5300A
Mainframe, and analog output can be added by in
cluding the 53 11 A Digital-to-Analog Converter mo
dule.2
Solutions to Low-Frequency Problems
Low-frequency measurements have their own
Fig. 1. Model 5307 A High-Resolution Counter snaps onto the
six-digit 5300/4 Measuring System mainframe. The combina
tion measures low frequencies much more rapidly than a dir
ect frequency counter for a given accuracy and resolution.
A counts-per-minute mode is useful in many low-frequency
applications.
10
© Copr. 1949-1998 Hewlett-Packard Co.
Schmitt
.Trigger
Input
Fig. 2. Input circuit design pro
vides flexible signal conditioning.
Two-step measurement cycle
consists of a multiple-periodaverage measurement followed
by calculation of the reciprocal
of the average period. The count
er is autoranging, automatically
selecting the number of periods
to be averaged.
special problems, and the 5307A Counter is de
signed to offer solutions to these problems.
Unlike higher frequencies, which are universally
expressed in counts per second, or hertz, lower fre
quencies are often expressed in counts per minute.
Therefore the 53 07 A has a front-panel pushbutton
that causes the frequency to be displayed in counts
per minute. This button also reduces the lower li
mit of the measurable frequency range from 5 Hz to
50 counts/min (0.833 Hz). The counts/min mode
makes the counter especially convenient for cardio
logy and tachometry; direct readings from a pace
maker can be displayed in beats per minute, and
the output of any sensor that generates one pulse
per revolution can be displayed in revolutions per
minute.
Signal conditioning requirements at low frequen
cies are also somewhat special. Because the output
levels of some sensors are quite low, the new
counter has 10 mV rms input sensitivity. The input
is ac coupled directly to a high-sensitivity FET
Schmitt trigger (Fig. 2). Ac coupling makes trigger
ing independent of any dc signal component, while
elimination of the usual separate FET buffer ampli
fier provides exceptional freedom from the over
shoot and ringing occasionally seen in ac-only in
put amplifiers.
Complex waveshapes and noisy signals are also
more common in the low-frequency environment.
To attenuate interfering high-frequency noise,
either of two low-pass single-pole filters may be se
lected by front-panel pushbuttons. These filters
have upper 3 dB frequencies of 100 Hz and 10 kHz,
and rolloffs of 20 dB per decade. They greatly reduce
the triggering ambiguity caused by noise, an impor
tant consideration if only a few periods are being
averaged. This improvement is shown in Fig. 3.
The sensitivity knob may also be used to improve
triggering in the presence of noise. Fully clockwise,
the sensitivity control sets the trigger level at +10
mV; fully counterclockwise the trigger level is
2.5V. For finer adjustments at the 10 mV end, the
position of the sensitivity knob has a logarithmic
rather than a linear relationship to the trigger level.
The trigger level and slope are switched to negative
values when the negative trigger button is pressed.
Very-high-level signals are also common in lowfrequency measurements. For example, ac power
mains usually have a frequency of 50, 60, or 400 Hz.
The 5307A is well suited to measuring these fre
quencies, and will withstand up to 300V with the at
tenuator -i-100 button pressed. This front panel but
ton also raises the trigger levels to a higher range,
IV to 250V. Note that ac mains measurements should
always be made using an isolation transformer at the
5307A input and observing proper safety precau
tions.
Internal Controls
In addition to these problem-solving front-panel
controls, two internal controls are useful under cer
tain conditions. The first is a pulse-width adjust
ment. This control varies the pulse width of the in
put one-shot multivibrator. Its effect is to provide a
variable delay after triggering, during which no
further triggering can occur. There are two ranges
11
© Copr. 1949-1998 Hewlett-Packard Co.
Fig. 3. To eliminate high-fre
quency noise that might cause
triggering errors, the 5307/4
user can select one of two builtin low-pass filters. The filters have
upper 3 dB frequencies of 100
Hz and 10 kHz and rolloffs of
20 dB per decade.
Measured Period Without Filter
Measured Period With Filter
Actual Period
achieve lock at frequencies below a few tens of
hertz, and track over a frequency range of only
about 20:1. The latter problem requires that multi
ple range switches be used, and may cause signals
outside of the selected range to be measured incor
rectly with no clear indication of error. These units
are also not suitable for measuring aperiodic or ran
dom inputs.
A third possibility for improving resolution is to
measure the period of one or more cycles of the un
known. This requires the user to calculate the reci
procal of the period.
of delay, 0.35 /AS to 3.5 /us and 1 ms to 10 ms. One
situation in which delay is useful is when ringing
follows the pulse to be counted, as shown in Fig. 4.
The delay avoids false triggering by causing the
counter to ignore the ringing.
The second internal control is the alternate range
switch. This switch, in its normal position, allows
the 5307A to change ranges automatically at every
decade point. In either of the other two positions, it
suppresses alternate range changes. The user can
elect to suppress either even-numbered or odd-num
bered range changes.
This feature is convenient when the 5307A is be
ing used to measure a varying frequency that fre
quently crosses a range-change point. It is also spe
cifically designed to reduce the number of range
changes when the Model 53 11 A Digital-to-Analog
Converter module is used. When the 5300A and
5307A are snapped apart to allow the 531 1A to be
inserted between them, the alternate range switch
is conveniently exposed. The 5311 A provides an an
alog output of the 5307A display, which can be
used to drive a strip-chart recorder or to supply the
feedback voltage for a closed-loop control system.
Two-Step System
The method chosen for the 5307A is a two-step
Trigger Level
iLJ fl
fl
Obtaining High Resolution
There are several methods for improving resolu
tion at low frequencies. A longer gate time may be
used, but only at the expense of frequent readings.
A frequency multiplier may be used to produce a
higher-frequency signal related to the input signal.
This technique is usually implemented with a
phase-locked loop. Such units typically are slow to
Output from
One-Shot
Fig. 4. Adjustable pulse width of the output monostable multi
vibrator in the 5307 'A trigger circuit is useful for eliminating
false triggering in the presence of ringing.
12
© Copr. 1949-1998 Hewlett-Packard Co.
system (Fig. 5). First, a period average of the input
signal is measured, and then the reciprocal of the
period average is calculated and displayed. During
the first step, a six-digit period counter counts an in
ternal reference frequency derived from the 10 MHz
crystal oscillator in the 5300A mainframe.
The period average counter is active during 2 x
10" periods of the input signal. Using the facilities
for autoranging built into the mainframe, the
5307A automatically selects n to average from 2 to
200,000 periods (n = 0 to 5). Thus the average per
iod of any input frequency from 5 Hz to 2 MHz (or
from 50 counts/min to 107 counts/min) can be mea
sured to an accuracy of at least 1 x 10~5. The value
of n is stored and used to control the position of the
decimal point for the next display.
After the first step is complete, the period mea
surement still must be converted to frequency for
display, that is, the reciprocal must be taken (fre
quency = I/period). This could be accomplished by
BCD division, as is done in the 5323A Automatic
Counter.3'4 But instead a method was chosen that
takes the reciprocal of the period measurement by
using hardware that is already built into the 5300A
mainframe and the period average counter itself.
To implement this method, a digitally program
mable frequency generator (PFG) is used. The PFG
has six digits of static BCD programming inputs
from the period average counter, a single reference
frequency input, and a single variable frequency
output. For each 106 pulses at the reference input,
it generates as many pulses at the output as are spe
cified by the six static BCD digits. For example, if
the BCD programming inputs are 123456, the PFG
will produce 123,456 output pulses for each mil
lion reference pulses. More details on the operation
of the PFG are given in the box on page 14.
The time base unit in the 5300A divides the PFG
output frequency by 105, and the result is used to
open and close the display gate. The display counts
the 10 MHz reference frequency during the time the
display gate is open. When the gate closes, the dis
play counter contains the frequency of the input sig
nal scaled by a factor of 10", and the previously
stored value of n is used to set the proper decimal
point and annunciator.
Because the PFG output frequency is proportion
al to the period average of the input signal, the aver
age period of the PFG output is proportional to the
input signal frequency. The second step of the
5307A measurement is equivalent to measuring the
average of 105 periods of the PFG output. Thus the
second step produces a number equal to the fre
quency of the input signal.
The reciprocation scheme has a worst-case error
of ±3 x 10~5, and this is the basic accuracy specifi-
Open Period Gate
Count Reference
Frequency Until
10" Periods of
Input Signal
Are Complete
Step 1
Autoranging
Measurement
V of Period
Average of
Input Signal
Start Digital
Programmable
Frequency
Generator (PFG)
I
Open Display Gate
T
Count Reference
Frequency into
Display Until 10s
PFG Output Pulses
Have Occurred
Step 2
Measurement
• of Period
Average of
PFG Output
Close Display Gate
Transfer New Contents
of Display Counter
to Display Storage
Fig. 5. Algorithm for the two-step frequency measurement.
After the average period of the input signal is measured, the
programmable frequency generator produces a frequency
proportional to this average period. This frequency is then in
verted to find the input frequency by measuring the average
period of the PFG output.
13
© Copr. 1949-1998 Hewlett-Packard Co.
Operation of the Digital Programmable
Frequency Generator
The 5307A uses a six-digit PFG built around a six-digit de
cade counter. The output for each decade is formed as in the
one-digit case, and all six outputs are multiplexed onto one
line. Since each decade produces only zero to nine pulses
out of a possible ten, there is one state in which it never pro
duces a pulse. This state, by design, is the "9" state for all
six decades. Thus each time the first decade is in the "9"
state, a pulse from the second decade can be multiplexed
onto the output line. Similarly, a pulse from the third decade
can be output each time the first two decades are in the "99"
state, and so on for each succeeding decade.
To reduce package count and power consumption, the
5307A has only one digit of converting and combining logic,
and multiplexes the six decade counters to it, in the order out
lined above.
While the spacing of the output pulses is generally not uni
form, the average period over 10 pulses is very accurate, ty
pically to one part in 105, and the 5307A's accuracy is depen
dent only on the time taken to generate 105 pulses.
The PFG uses digital logic to generate an output pulse train
that has an average frequency equal to a fraction of the input
reference frequency. The fraction is specified by the BCD pro
gramming inputs.
The PFG is a type of decimal rate multiplier5. As an exam
ple of PFG operation, consider the one-digit PFG shown in the
drawing. For each group of ten pulses of the reference fre
quency, this circuit produces from zero to nine output pulses,
under control of the BCD programming input. Outputs A, B,
C, and D of the BCD decade counter are used by the convert
ing logic to generate waveforms W, X, Y, and Z, which are in
the logic "1" state during one, two, four, and eight clock times
out of ten, respectively. These waveforms are then selectively
combined in the combining logic to produce a waveform that
is in the logic "1 " state from zero to nine clock times out of ten.
This output controls the gating of reference frequency pulses
from input to output. In the drawing, a BCD 6 (01 10) at the pro
gramming input causes six reference frequency pulses out of
ten to be passed through the pulse gate to the output.
BCD
Decade
Counter
Converting
BCD
Programming Input
0 1 1 0
2 3 4 5 6 7 8 9 C o m b i n i n g
Logic
Reference
Frequency
0 1 2 3 4 5 6 7 8 9
_ruuuui_rui_n_n_
ble in the logic sections to minimize power con
sumption.
cation of the counter for pulse inputs. Fig. 6 com
pares the accuracy specification of the 5307A mea
surement with the accuracy of a one-second direct
frequency count for pulse and sine-wave inputs.
This method of taking the reciprocal makes opti
mum use of the capabilities of the mainframe and
the period counter. In the mainframe, it uses the
crystal oscillator output for its reference frequency,
the programmable time base divider to count 105
PFG output pulses, and the display counter to
count the final answer. In the 5307A, it uses the six
decades of the period average counter as the heart
of the PFG. To allow this dual use of the decades,
the results of the first step are stored in a small ran
dom access memory before the second step begins.
Such economy of hardware was necessary to
meet the power and package size constraints of the
portable, battery-powered 5300 System. Lowpower TTL MSI circuits were used wherever possi
Acknowledgments
Major contributions to the 5307 A were made by the
following people. Ian Band provided overall guidance
and suggested the converting technique. Lew Masters
designed the signal conditioning electronics. Bruce
Corya was responsible for the mechanical design. Mar
keting was handled by Larry P. Johnson. *
References
1. I.T. Band, H.J. Jekat, and E.E. May, "Lilliputian
Measuring System Does Much, Costs Little", Hew
lett-Packard Journal, August 1971.
2. J.F. Homer, L.W. Masters, and P.T. Mingle,
"DMM AND DAC Modules Expand Low-Cost Mea
suring System", Hewlett-Packard Journal, June
1973.
14
© Copr. 1949-1998 Hewlett-Packard Co.
4. F. Rode and G. B. Gordon, "Computation for Mea
surement Flexibility", Hewlett-Packard Journal,
May 1969.
5. H. Schmid and D.S. Busch, "An Electronic Digi
tal Slide Rule", The Electronic Engineer, July 1968,
pp. 54-64.
SPECIFICATIONS
HP Model 5307A High Resolution Counter Module
Input
RANGE: Hz mode 5 Hz to 2 MHz.
CPM mode 50 to 10 M counts/minute (0.833 Hz to 166
kHz).
SENSITIVITY (min.):
S I N E W A V E S
H z
C P M
10 mV rms 5 Hz-1.2 MHz 120 CPM-10 MCPM
25 mV rms 1.2 MHz-2.0 MHz 50 CPM-120 CPM
PULSES
For low-duty-cycle pulses (<15%): 15 mV peak for 250 ns
pulses. 100 mV peak lor 100 ns pulses.
Basic sensitivity can be varied continuously up to 2.5 V rms by
adjusting sensitivity control.
ATTENUATOR: -;- 1 or -MOO effectively raises basic input sensi
tivity by a factor of 100 (10 mV-2.5 V to 1 V-250 V).
LOW PASS FILTERS:
3 dB point
1 0 0 H z 1 0 k H z
Max. attenuation
6 0 d B 4 0 d B
20 dB per decade
Rolloff
IMPEDANCE:
No filter
1 Mi! shunted by <50 pF
100 Hz-mter
1 MS shunted by series of
100 k« and 0.015 ^F
10 kHz filter
1 MÃÃ shunted by series of
100 k!2 and 150 pF
COUPLING: ac coupled amplifier.
OVERLOAD PROTECTION:
200 V rms below 10 kHz
2 x 10" V • Hz rms to 0.4 MHz
5 V rms above 0.4 MHz
With -MOO attenuator, 300 V rms
TRIGGER LEVEL: Selected positive or negative for optimum trigger
ing from sinusoidal inputs or pulses.
TRIGGER HOLDOFF: Adjustable from .35/is to 3.5/iS and 1 ms to
10 ms.
Fig. 6. Error limits for 5307 A measurements. Limits include
worst-case reciprocal-calculation error and worst-case trig
ger error for sine-wave inputs.
3. I.T. Band,— '^Automatic Counter Inverts Period to
Get Frequency", Hewlett-Packard Journal, May
1969.
Frequency Measurement
PERIODS AVERAGED: Automatically selected for maximum resolu
tion. Two periods are averaged for signals up to 100 Hz. For each
decade increase in the input signal, the number of periods
averaged increases by a factor of ten up to 200,000 periods
averaged above 1 MHz.
MEASUREMENT TIME: Varies from 312 ms for a display of 170000
to 815 ms for a display of 999000.
ACCURACY: ±3 x 10-s ± trigger error" ± time base error.
DISPLAY:
In Hz mode, Hz and MHz with automatically positioned decimal
point.
In CPM mode, M with automatically positioned decimal point.
General
Kenneth J. MacLeod
CHECK: Measures internal reference frequency. Displays 1.00000
MHz in Hz mode, 100000 M in CPM mode.
OPERATING TEMPERATURE: 0' to 50° C.
POWER 10 Including 5300A Mainframe, nominally 10
watts.
WEIGHT: Net, 2 Ib (0,9 kg).
PRICES IN U.S.A.: Model 5307A, $350. 5300A Mainframe, $395.
5310A Battery Pack, $195. 5311A Digital-toAnalog Converter, $295.
*±3 x 10 s is due to reciprocation scheme and is worst case.
••Trigger error is less than itO.03% of one period -r periods
averaged for sine waves with 40 dB or better signal-to-noise
ratio.
MANUFACTURING DIVISION: SANTA CLARA DIVISION
5301 Stevens Creek Boulevard
Santa Clara, California 95050 U.S.A.
Ken MacLeod, a native of Philadelphia, Pennsylvania, holds
a BA degree from Ursinus College (1969), a BSEE degree
from the University of Pennsylvania (1970), andan MSEE de
gree from Stanford University (1973). With HP since 1970,
Ken has designed hardware and software for a high-speed
test system and served as principal designer of the 5307A
Counter. He's a member of the IEEE Computer Society. Hav
ing lived on the west coast of the USA for only three years,
Ken and his wife still spend much of their time exploring, us
ing their home in San Jose, California as their base of opera
tions. Ken's explorations also extend to outer space; he's an
amateur astronomer.
15
© Copr. 1949-1998 Hewlett-Packard Co.
A High-Speed Pattern Generator and an
Error Detector for Testing Digital Systems
The rate at which errors occur in transferring digits through
systems operating at bit rates as high as 150 M bits /s
can be determined by a new Error Detector working with
a new Data Generator.
by Thomas Crawford, James Robertson, John Stinson, and Ivan Young
AS THE WORLD of electronics grows increasing
ly digital, bit rates go higher and higher. In par
ticular, growth in the demand for local and interna
tional telephony and the need for new communica
tions services, such as high-speed transfer of data be
tween computer systems, is forcing an increase in
transmission capacity. Digital transmission techni
ques like pulse-code modulation (PCM) will play a
major role in providing this capacity.
Rapid development in these new digital systems
is resulting in a requirement for test instruments that
can accommodate the higher bit rates. Here, then, is
a new pair of instruments (Fig. 1) intended for test
and evaluation of digital systems operating at bit
rates as high as 150 Mb/s. Model 3760A Data Genera
tor produces pseudorandom bit patterns up to
32,767 bits in length as a stimulus for the system un
der test. Model 3 761 A Error Detector generates an
identical pattern internally, compares it bit by bit
with the output of the system under test, and deter
mines the rate at which errors occur.
Error rate is the important performance criterion
in evaluating a digital transmission system. This
kind of test could also be applied to digital magne
tic recorders, memory systems, and some logic sys
tems. A number of conveniences have been built in-
Fig. 1. Model 3760A Data Gen
erator (lower unit) supplies a vari
ety of bit patterns that are useful
for testing digital systems and lo
gic operations. Model 3761A
Error Detector detects errors in
troduced into the data generator's
pseudorandom sequences by
equipment under test, and mea
sures the rate at which errors
occur.
16
© Copr. 1949-1998 Hewlett-Packard Co.
Binary
Binary
Transmission
Medium
Infor
mation
Infor
mation
3760A
Data
Generator
3761 A
Error
Detector
to these instruments to make them easier to operate
and also to broaden their usefulness in the develop
ment lab and on the production line, as well as in
the field.
Bit Error Rate
A typical application for these instruments is
shown in Fig. 2. The Model 3760A Data Generator
stimulates the system at any point where the infor
mation is normally in binary form. The Model
3761A checks the binary stream at the output of the
system and counts the number of times that its inter
nally generated bit sequence differs from that re
ceived. At the same time, it counts system clock per
iods so that it can determine the bit error rate (BER),
the ratio of number of bits in error to number of bits
transmitted. It continuously updates this informa
tion, presenting it on its digital display.
Test Signals
For best correlation between actual system perfor
mance and bit-error-rate measurements, the test sig
nals should resemble normal information-carrying
signals. In a typical PCM system, information from
many independent sources is time-multiplexed to
form a composite signal with a high bit rate. As the
number of sources is increased, the statistics of the
nominal aggregate signal more and more resemble
those that would be obtained from a truly random
noise source.
The 3760A/3761A measurement system uses
pseudorandom binary sequences generated by shift re
gisters with feedback taps. Since the statistical nature
of a pseudorandom binary sequence is very close to
that of a truly random pulse stream, this makes the test
signal resemble typical signals, but it also enables the
error detector to generate bit sequences identical to
those of the data generator.
Model 3760A Data Generator produces pseudoran
dom sequences in nine different lengths selectable
from 7 bits to 32,767 bits long. The shorter lengths are
useful for debugging and for situations where it is
desirable to observe the entire bit stream on an oscil
Fig. 2. Model 3760A Data Gen
erator supplies digital sequences
to a system at the point where the
information is normally in binary
form. Model 3761 A checks the se
quence at the output before any
decoding occurs.
loscope. The long sequences are more like typical
signals. A sync pulse is generated once per sequence
repetition to make it easy to synchronize an oscil
loscope or other equipment to the bit pattern.
The new data generator also generates digital
words up to 10 bits long for testing logic systems or
for reproducing key system code words. A bank of
front-panel switches allows a choice of any bit pat
tern for these words. Here too, a sync pulse is genera
ted once per word.
The switches for selecting the digital word also
select the point in the pseudorandom sequences
where the sync pulse occurs. This arrangement per
mits the operator to shift the sync pulse along the se
quence so he can observe the effect of every part of a
long sequence in detail with an oscilloscope.
Runs of zeros up to 99 bits long can be inserted be
tween repetitions of the words or pseudorandom se
quences. These are useful for checking clock-reco
very circuits that extract timing signals directly
from the data stream. Such circuits tend to fail
when pulse transitions do not occur frequently. Or,
a run of zeros may be inserted following a run of 1's
to test for dc shift in the system under test.
The instrument can also generate an alternating
bit sequence, 1010..., where a maximum number of
transitions may be wanted.
Deliberate errors can be inserted into the data
generator's pseudorandom sequences to check the
operation of the error detector. When operated in
the "add error" mode, the data generator replaces
two consecutive bits with their complements once
every 4000 sequences. This corresponds to an error
rate of 7.1 x 10~5 to 1.5 x 10~8, depending upon the
sequence in use.
Normally the data generator operates with clock
pulses supplied from the equipment being tested,
but it may also be equipped with an internal clock
generator. The data generator in turn produces out
put clock pulses in synchronism with the clock
source but gives the operator control over ampli
tude (0.1 to 3.2V), offset (±3V) and polarity. To
accommodate differing propagation delays in the
17
© Copr. 1949-1998 Hewlett-Packard Co.
error rate (BER). The BER display consists of two di
gits plus a power of ten in a range of 0.1 x 10~9 to
9.9 x 10"1.
If the operator prefers to know the total errors,
rather than have an indication of bit error rate, he
may switch to a "count" mods, which totals errors
up to 9999. He may choose to use this mode if er
rors occur at a very low rate, in which case he may
not want to wait for the accumulation of the more
than 100 errors needed for automatic BER computa
tion. The time during which errors are counted may
be controlled manually by a front-panel switch, ex
ternally through a TTL compatible input, or inter
nally. The duration of the internal gate is selected
by a front-panel switch .
Besides the front-panel numerical indication, the
error detector outputs the numerical values in BCD
form for a digital recorder. It also outputs a pulse
whenever an error is detected, for use in further sta
tistical processing.
cables that connect the data generator to the system
under test, the data stream may be delayed up to
100 ns with respect to the clock to ensure the correct
phase relationship between the data and the clock at
the system input.
To match the requirements of the system under
test, the operator has control over the pulse char
acteristics of the data stream. He can select either
the RZ format {return-to-zero, constant width
pulses) or NRZ format (non-return-to-zero, output
goes high on a "1" and stays there until the next
"0" occurs). The width of the RZ pulses is deter
mined by the width of the input clock pulses at the
triggering level.
The operator also has a choice of amplitude, off
set, and polarity for the output data, the same as for
the clock pulses. Input and output impedances are
50Ã1 in the standard instrument but 75Ã1 is available
as an option.
A second data output, delayed a fixed number of
clock pulses with respect to the main data output,
is available as an option. In the PRBS mode, the two
outputs are effectively uncorrelated (first-order)
and are therefore useful for checking out the opera
tion of the diplexers and other modulators and de
modulators used in digital radios. The delayed out
put has the same amplitude and offset capabilities
as the main output.
Pseudorandom Sequence Generation
The heart of the Model 3760A Data Generator is a
high-frequency 15-stage shift register that uses a
feedback configuration similar to that in the Model
1930A PRBS Generator1, as shown in Fig. 3. Feeding
the shift register output back into the register
through exclusive-OR gates alters the contents of
the data stream as it passes through. By proper
choice of the stages where feedback is introduced, a
maximal length pseudorandom sequence is generat
ed. A maximal length sequence is one where all pos
sible combinations of N l's and O's (except all O's) is
generated without repeating any combination,
The Error Detector
Model 3761A Error Detector accepts two inputs:
the data stream to be examined, and clock pulses
derived either from clock recovery or other exter
nal circuits, or directly from the data generator. The
clock input has oscilloscope-type triggering controls
to accommodate a variety of clock pulse amplitudes
and offsets. A front-panel indicator lights up to show
when proper triggering is achieved.
To make sure that the clock pulses do not sample
the data stream on data bit edges, which would re
sult in ambiguous operation, a variable phase con
trol is provided. The operator needs only to adjust
the phase control until a front-panel lamp lights up.
This lamp turns off when transitions occur too
closely.
With the clock trigger and phase controls set pro
perly, all that remains is to set the pseudorandom
sequence to the same length as the data generator.
Although alignment of a locally-generated pseudo
random sequence with the transmitted sequence has
been a troublesome procedure with closed-loop shift
registers, alignment occurs automatically with the
new error detector, requiring no intervention by the
operator.
To ensure statistical significance, at least 100 er
rors must occur before the system will display bit-
Binary
Sequence
bl Out
Clock pulses
etc.
Fig. 3. A typical PRBS generator. This one has three active
stages and feedback to two points to give a maximal length
sequence of 7 bits (23 - 1). Models 3760/4 and 3761 A have
15 stages with gates from the feedback tap line to establish
the number of active stages and the points where feedback
is introduced.
18
© Copr. 1949-1998 Hewlett-Packard Co.
the number of stages and the proper feedback taps
for generating a maximal length sequence for that
number of stages. The minimum is 3 stages, which
gives a 7-bit sequence, and the maximum is 15
stages, which gives a 32,767-bit sequence.
A sequence sync pulse is generated whenever the
contents of the shift register match the contents of
the front-panel WORD switch register (the data
stream output, however, is delayed one bit with re
spect to the sync pulse). It should be noted, though
that following a sync pulse the data stream out of the
register is not the same as the sync word selected.
This is because the contents of the shift register are
altered by the feedback taps as the word is shifted
through. To aid the user in setting the sync pulse
to a particular part of a sequence, the instruction
manual contains information that relates the sub
sequent output sequence to the instantaneous con
tents of the shift register.
Feedback Tap Line
The function required is:
D2 = Q,©S Q2
= a, (s+cg + a, <s eg
Modifying a Sequence
A run of zeroes is added simply by gating off the
clock pulses to the shift register when a sequence
sync pulse occurs. A counter, preset to the number
selected by the ADD-ZERO switches, then starts
counting down clock pulses. When it reaches zero,
it reopens the clock pulse gate, restarting the regis
ter. Since zero insertion is triggered by the se
quence sync pulse, zeroes can be added at any
place in a sequence by appropriate setting of the
switch register.
Deliberate errors are inserted by gating the
complement of the data stream into the output for
two clock periods. Error insertion is initiated by a
counter that counts sequence sync pulses, trigger
ing the error-insertion circuits on the 4000th count.
When the instrument is switched to the WORD
mode, the shift register recirculates its contents
without change. Each time the word circulates back
to the starting position, a sync pulse is generated by
the digital comparator. A low-pass filter derives a
dc voltage proportional to the average value of the
sync pulse train so if sync pulses do not occur regu
larly, the voltage drops to zero, enabling a reset
pulse that loads the contents of the front-panel
WORD switch register into the shift register. Thus,
the front-panel register can be changed, and the
new word will be loaded automatically.
The maximum-transition sequence (101010....) is
generated by taking the output from a flip-flop.
= Q, + S + Q1 + Q2 + Qi + S + Q2
Which may be implemented as:
Fig. 4. Exclusive-OfÃ- gate and tap-line switch in upper dia
gram are implemented by logic circuit in lower diagram. This
achieves minimum propagation delay.
where N is the number of stages in the shift regis
ter. The sequence length is 2N — 1.
The configuration chosen for the shift registers in
the new instruments limits the amount of propaga
tion delay in any feedback loop to that of one exclusive-OR gate, as contrasted with other configura
tions where feedback may be processed through
two or more gates in series. An exclusive-OR gate
that includes the feedback tap-line switch is shown
in Fig. 4. Minimum delay circuits such as this, along
with the use of high-speed emitter-coupled logic and
stripline signal paths on multilayer circuit boards,
enable operation at clock rates up to 150 MHz.
The front-panel PRBS LENGTH switch selects
The Overview
A block diagram of the Data Generator is shown
in Fig. 5. The input signal conditioning circuit is
somewhat similar to an oscilloscope time-base trig
ger circuit and need not be discussed here except to
19
© Copr. 1949-1998 Hewlett-Packard Co.
Clock
In
Out
Variable
Delay
Internal
Clock
Generator
(Optional)
^
^
^
D
a
t
Delayed
a
-*E i*^^^"^"*
Fig. 5. Simplified block diagram
of Model 3760/4 Data Generator.
point out that dc coupling is used at all times so
that the trigger level will not be affected by any
changes in the clock pulses.
The trigger level determines the width of the out
put pulses when the instrument is in the RZ mode.
For example, if the clock input is a sine wave and
the trigger level is set to midrange, the RZ output
pulse width would be half the clock period. As the
trigger level is raised towards the crest of the sine
wave, the output pulses become correspondingly
narrower.
When the "auto" trigger mode is used, the trigger
level is established by a circuit that taps off the in
put waveform, passes it through a low-pass filter to
derive the average waveform level, and uses the re
sult to define the trigger level. This insures that the
trigger level is always within the swing of the input
waveform. The "auto" trigger works with any regu
larly recurring waveform that has a pulse width
greater than 3 ns, a mark:space ratio between 1:10
and 10:1, and an amplitude of 0.5V p-p or greater. A
front-panel indicator lights up to show that the in
put circuits are triggering.
The relative timing between the data and clock
pulse edges is of concern, so provision was made for
a controllable delay between the data stream and
clock stream. Lumped delay lines give up to 90 ns
delay in switched 10-ns increments and a contin
uous vernier extends the maximum to 100 ns. The
vernier delay, diagrammed in Fig. 6, is also a
lumped line but it uses varactors to vary the delay.
The output circuits are conventional pulse gener
ator type circuits affording control of amplitude,
polarity, and offset. Such flexibility was not
deemed necessary for the sequence sync pulse; it is
a 1-volt positive-going pulse that has a duration
equal to one clock period, except in the "add-zero"
mode when it stays high for the duration of the zero
block. This allows an oscilloscope to trigger on
either the start or the end of a zero run according to
the trigger polarity selected.
The Bit Error Detector
A block diagram of the Model 3 761 A Error Detec
tor is shown in Fig. 7. The clock input conditioning
circuits are similar to the Model 3760A Data Genera
tor. The input for the data stream, however, always
works in the "auto" mode, with only the polarity se
lectable.
Because the data is sampled at clock pulse edges,
it is important that the data and clock pulse edges do
not coincide. A phase delay for the clock circuits is
therefore provided. A variable delay line similar to
that in the 3760A Data Generator is used to give a
controllable delay up to 12 ns but when the RATE
switch is set on the 1.5 - 50 Mbits range, an RC vari
able phase shifter is used (this is the only function of
the RATE switch). The front panel PHASE control
then gives delay in a range of 0 to 180° of the clock
period regardless of the cJock repetition rate. This is
accomplished by the circuit in Fig. 8.
An indication of proper phasing is needed for the
operator. This is achieved by a circuit that produces
an output pulse if a data transition occurs during
the time that a narrow guard pulse, derived from
the clock, is present (Fig. 9). A coincidence inhibits
the front-panel PHASE indicator, so as long as this
indicator is illuminated, the operator knows that
20
© Copr. 1949-1998 Hewlett-Packard Co.
Vernier Delay Control
Fig. 6. Vernier delay line uses
varactors to change the capaci
tance and thus the delay charac
teristics of the line. Push-pull ar
rangement compensates for the
change of varactor bias during a
clock pulse. The line uses
printed-circuit inductors.
proper phasing is achieved.
spondence between the locally-generated se
quences and the incoming sequence must be estab
lished. For a sequence of 2N-1 bits, this can be ac
complished within N bits simply by opening the
feedback connection to the tap line, and feeding the
incoming sequence to the tap line (Fig. 11). This
switching is initiated automatically when an auxi
liary error counter reaches a count of 20,000 errors.
The counter is reset every 100,000 clock periods so
resynchronization occurs only when more than
20,000 errors occur within 100,000 bits.
What happens if there should be an error in the
data stream at the time that resynchronization is
concluded? The error in effect causes the sequence
to start from the wrong initial word, thus generat
ing the sequence out of phase with the incoming
stream. There is then the statistical likelihood that
one half of the bits will be in error. The auxiliary er
ror counter would then contain 50,000 counts
Split Data Stream
Since the error detector operates only with
pseudorandom sequences, it was possible to realize
some economies by splitting the data stream, gating
alternate bits so two half-rate data streams are de
rived (Fig. 9). Economies are realized because the
cost of high-speed logic as a function of speed rises
with a slope greater than 1. The properties of maxi
mal-length PRBS's are such that each half-rate
stream retains the same structure as the original fullrate sequence, as shown in Fig. 10. Each half-rate
shift register may then have the same feedback con
nections as the full-rate shift register in the data gen
erator.
Automatic Sequence Synchronization
Before errors can be detected, bit-by-bit corre
Data
Shift Register
Error
Detector
T
Error
Counter
Shift Register
Error
Detector
T
PHASE
Auxiliary
Error
Counter
Resync
Clock
Counter
Clock
Fig. 7. Simplified block diagram of Model 3761 A Error Detector.
21
© Copr. 1949-1998 Hewlett-Packard Co.
Sampling a 7-Bit Maximal-Length PRBS
Fig. 8. Self-adjusting ramp generator accommodates varying
clock rates. The ramp is generated by charging capacitor C1
with current supplied by transistor 02. Capacitor Cl is dis
charged each time a pulse derived from the leading edge of
each clock pulse turns on 07. The resulting sawtooth wave
form is low-pass filtered by R2 and C2, level-shifted by the
zener diode, and used to control the current level through
02. This holds the ramp amplitude nearly constant by adjust
ing the charging current to fit the clock rate.
Original Sequence Starting at A 01 01 1 1 001 01 1 ....
Half Rate Sampled Sequence Starting at A 001011100101....
Half Rate Sampled Sequence Starting at B 111001011100....
Fig. 10. Diagram representing 7-bit maximal length se
quence shows that taking every other bit derives the same
sequence as the original.
when reset.
A count of 20,000 errors is high enough to permit
the system to accept bursts of errors without trigger
ing resynchronization in an otherwise "quiet" trans
mission.
Synchronization can also be initiated manually
or remotely by an external TTL signal. This is use
ful in lab or production test situations where it may
be desired to establish synchronization, and then
degrade the data stream, say by adding noise and/or
attenuating the signal level. The resulting high er
ror rates, which otherwise would automatically ini
tiate resynchronization, can then be measured.
Display Considerations
The BER display accommodates a wide range of
Inhibit
Signal
to Lamp
Driver
22
© Copr. 1949-1998 Hewlett-Packard Co.
Fig. 9. Guard pulse, derived from
the clock, is applied to the D in
puts of two flip-flops. If a data
transition, acting as a clock, oc
curs during the guard pulse, one
of the flip-flops, depending on
transition polarity, will produce an
output that inhibits the front-panel
PHASE indicator. Input data, fol
lowing regeneration in a Schmitt
trigger, is also applied to two
other flip-flops that sample the
data on alternate clock pulses to
get two half-rate data streams.
Data
n
Fig. 11. By feeding data stream
into PRBS generator's feedback
tap line, the generator becomes
synchronized with the data stream
within N bits, where N is the num
ber of shift register stages.
error rates without operator intervention. The
theory is illustrated in Fig. 12. Two totalizers are
employed — one that totals errors and one that si
multaneously totals clock periods. First of all, to
give statistical significance to the indication, 100 er
rors must be totaled before any action is taken.
When 100 errors have been detected, the BER calcu
lator is armed. When the currently-being-filled de
cade of the clock period totalizer is filled, the dis
play circuit is enabled. The two most significant di
gits of the error count are then displayed and the ex
ponent "n" of the XlO~n portion of the display is de
rived by subtracting the number of filled decades in
the error counter from the number of filled decades
in the clock counter.
As discussed earlier, the instrument can be oper
ated in a "count" mode wherein the error counter
Fig. 12. Timing diagram of the system for deriving the biterror-rate (BER) display. The system displays the number ex
isting in the error counter at the time that the clock reaches
the decade count that follows detection of 100 errors.
Thomas Crawford (Far left)
Tom Crawford joined Hewlett-Packard Ltd. in 1966 after
graduating with a B.Sc. degree from Heriot-Watt University.
Tom worked on the 370IA Microwave Link Analyzer until re
turning to Heriot-Watt University under HP's sponsorship
where he obtained a Ph.D. degree in 1970. He then returned
to Hewlett-Packard and worked on the design of the 3761 A
Error Detector. Tom is presently leader of the High-Frequency PCM Group at HP Ltd.
James Robertson (Left)
After graduating with a B.Sc. degree from Glasgow Univer
sity, James joined Hewlett-Packard Ltd. in 1968 and was en
gaged in early investigations related to high frequency digi
tal communications. While working on the design of the
3761 A Error Detector, James also obtained his M.Sc. degree
from Heriot-Watt University in 1972.
John Stinson (Right)
A native of Scotland, John joined Hewlett-Packard in 1968
after obtaining a B.Sc. in Electrical Engineering at Strathclyde
University in Glasgow. The first two years of his HP career
was as a design engineer on instruments such as the 371 OA
Microwave Link Analyzer. John's involvement with the 3760A
Data Generator began with the initial investigation when the
Digital Communications Section was formed at HP Ltd. Cur
rently he is Group Leader for the Low-Frequency PCM
program.
Ivan Young (Far right)
Ivan graduated with a B.Sc. degree from Heriot-Watt Univer
sity and joined Hewlett-Packard Ltd. in summer 1 969. He has
recently completed work leading to an M.Sc. degree in Digi
tal Techniques. Since joining HP, Ivan has worked in the Digi
tal Communications group and was involved ¡n the design of
the 3760A Data Generator from the initial investigation stage.
23
© Copr. 1949-1998 Hewlett-Packard Co.
totals for a given period of time and the contents are
displayed on the 4-digit display.
Acknowledgments
The authors wish to thank those in all depart
ments who helped during the projects. In particular
we would like to acknowledge the tenacity of our
production engineer, Stewart Moulton. We would
like to thank David Leahy, 3760A product designer,
and Ken Coles, 3761A product designer, for their
sustained efforts and likewise thank the engineers
who contributed to the design of the 3760A: Aileen
Appleyard, Mike Roberts, Peter Rigby, Ralph Hodg
son and Graham Cameron. Thanks also to David
Guest for designing the 3761A power supply and to
Lance Mills, project leader during the early stages,
for defining the system. 5
References
1. E.S. Donn, "Manipulating Digital Patterns With a New
Binary Sequence Generator," Hewlett-Packard Journal,
April 1971.
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r-PACKARD JCOXAL
NOVEMBER 1973 Volume 25 •
Technical Information from the Laboratories ot
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