eDP and MyDP and
DisplayPort Derivatives:
eDP and MyDP
and
Considerations of Physical Layer Test
Brian Fetz
May 6th, 2013
Topics
DisplayPort Technology
eDP and MyDP
Capabilities
Testing Considerations
Something Good is Happening…
Standard
DisplayPort
Computing
eDP
Embedded
Systems
VESA: 200 members strong!
Consumer Electronics
MyDP
Portables
DisplayPort Technology Rollouts
DP1.0
DP1.1
DP1.2
DP1.3
Today
5/2012 12/2012
Standard DP
eDP 1.0
iDP 1.0
1.2
1.3
1.4
1/2013
7/2013
MyDP
1.0
5/2012
Specification Released
4
4/2013
CTS Released
Confidentiality Label
May 10, 2013
Quick Summary
Capabilities
Standard
DisplayPort
eDP
MyDP
Competing
Technology
Noteworthy
Features
1,2, or 4 lanes
Four Settings for
Lvl and Pre-emph
SSC
3 bit rates
HDMI
DVI?
VGA?
Integrable in low
geometry silicon.
Dominating in
PCs now.
1,2, or 4 lanes
Multi-Level
Pre-emph
SSC
Multi bit rates
LVDS
MIPI
Low Power rivals
MIPI. High data rates
supported now.
Attributes similar to
DP
1 lane
Four Levels
Pre-emphasis
SSC
3 bit rates
MHL
1080p/60 24 bit color
achieved. Many
connection models.
Attributes same as DP
Why Successful?
ü 200 member companies participating
ü Original DP foundational principles serving DP extensions
ü Consumer focus in handling Legacy designs
ü Interoperability Program/Self testing/Compliance testing
ü Knowledgeable and Aggressive leaders
Craig Wiley
Parade Technologies
Alan Kobayashi
ST Micro
Key Features of DisplayPort
Ø AUX Channel
Transmitter
Very robust channel
Setup Link/Maintain Link
Test Assistance
Ø uPacket Based
Not based on Raster timings
Fixed bit rates
Ø Physical Layer Features
Multiple Bit rates
Multiple Levels
Multiple Pre Emphasis Settings
Spread Spectrum Clocking
Receiver (Sink)
AUX
Hot Plug Detect
Blanking Area
Active Video
DisplayPort Link
Sink
Image
buffer
Tx
Main Link
Hot Plug Detect
Driver
Logic
Decode
AUX
Bit Recovery
Lock
Err
Logic
AUX CH
Com
DPCD
EDID
Image
Frame
buffer
Display
The AUX Channel enables Link setup and maintenance as well as
control for testing.
AUX Channel Implementation
Manchester II Signaling
MyDP: Portable àTV
Portable
Get a pic of UTube or Netflicks
Today:
MyDP Connectivity
In the Future:
Wireless from
your portable
Your Entertainment System
My Entertainment System
Transmission Requirements
4k x 2k ?
No Way !
Not Yet Anyway
Using HDMI transmission as a benchmark…
Timing
1080i/720p
1080p/8bit
1080p/10bit
Lane Bit Rate
750Mbs
1.50Gbs
1.87Gbs
Pixel Rate
75MPs
150MPs
187MPs
Composite Bit Rate
2.23Gbs
4.46Gbs
Display Technologies Available:
DisplayPort: Maximum Lane Rate--5.4Gbs
HDMI: Maximum Lane Rate-----------3.4Gbs
5.57Gbs
Let’s Look Closer…
For both MHL and MyDP the uUSB connector is the de facto
connector, but it is not find it mentioned in either standard!
5 Pins
D- and D+ is the differential data lane
ID: USB mode detect
Conclusion: There is only one data lane through which the composite data rate must
be conveyed. So the composite bit rate rate is the metric.
Getting down to One data lane…
DisplayPort
20 Pins
AUX+/-, HPD
Config1/2
4 data
lanes
Power,
Ground
5 Pins
1 data
1 low
lane
speed line Power,
MyDP
Ground
MyDP
HDMI
uUSB
HDMI
Spec Released: 1.0
Compliance Testing starting: June 2013
Maximum Data Rate: 5.4Gbs to support 1080p/60Hz
uUSB
VGA
MyDP
q One could say that MyDP is not very new!
It is just one lane DisplayPort!
q There are other changes to get to 5 pin interface, but
nothing changes in the high speed signaling.
q Subsequent slides will be paired; the first to show the
standard DisplayPort attributes and the next those for MyDP.
DisplayPort Technology
Source Device
Main Link
(Isochronous streams)
Sink Device
AUX Ch
Link / Device Management
DisplayPort
Transmitter
FAUX:USB2.0 transport
Hot Plug Detect
(Interrupt Request)
DisplayPort
Receiver
DPCD
/ EDID
q  1 to 4 unidirectional high speed lanes
–  Fixed data rate independent of display raster (refresh)
q  Auxiliary channel for link communication and auxiliary data flow
- Link Setup and Maintenance (1Mb/s - Manchester II )
- USB 2.0 Transport (Fast AUX -540Mb/s - standard 8b/10b)
q  Auto detect of cable plug/unplug
MyDP Technology
Source Device
Main Link
(Isochronous streams)
Sink Device
AUX Ch
Link / Device Management
DisplayPort
Transmitter
FAUX:USB2.0
transport
Single Ended
Hot Plug Detect
(Interrupt Request)
DisplayPort
Receiver
DPCD
/ EDID
q 
highhigh
speed
lane lanes
q  1
1 unidirectional
to 4 unidirectional
speed
– 
–  Fixed
Fixed data
data rate
rate independent
independent of
of display
display raster
raster (refresh)
(refresh)
q 
q  Auxiliary
Auxiliary channel
channel for
for link
link communication
communication and
and auxiliary
auxiliary data
data flow
flow
-- Link
Link Setup
Setup and
and Maintenance
Maintenance (1Mb/s
(1Mb/s -- Manchester
Manchester II
II ))
-- Single
Ended
USB 2.0
Transport (Fast AUX -540Mb/s - standard 8b/10b)
q 
detect
cable
plug/unplug
q  Polling
Auto detect
of of
cable
plug/unplug
DP Technology: Specifications
Silicon structures:
•  Structure leveraged from PCI Express
•  Implementable on sub 65nm process
•  Termination Voltage must be <2volts (internal to IC)
Receiver
•  PLL BW=10MHz effective.
Jitter tolerance curve specified.
Data Rate
•  1.62 Gbs (RBR)
•  2.7 Gbs (HBR) [units supporting HBR must support RBR]
•  5.4Gbs
(HBR2) [units supporting HBR2 must support HBR]
MyDP Technology: Specifications
Silicon structures:
•  Structure leveraged from PCI Express
•  Implementable on sub 65nm process
•  Termination Voltage must be <2volts (internal to IC)
Receiver
•  PLL BW=10MHz effective.
Jitter tolerance curve specified.
Data Rate
•  1.62 Gbs (RBR)
•  2.7 Gbs (HBR)
•  5.4Gbs
(HBR2)
DP Technology: Main Link Lanes
Lanes
•  Each lane is Differential, 100Ω.
•  1, 2, 4 lane models for video data transport. 4 lane model capable must
support 1 & 2 lane models. 2 lane model must support 1 lane model.
Lanes are uni-directional.
•  ANSII standard 8b/10b.
•  Each lane has separate clock recovery from its data. No Explicit Clock.
•  Single ended lines of each lane are source and sink terminated and
biased. No external pull-up is needed for test equipment.
MyDP Technology: Main Link Lane
Lanes
•  Each lane is Differential, 100Ω.
•  1 lane for video data transport. Lane is uni-directional.
•  ANSII standard 8b/10b.
•  Clock recovery from the data.
•  Single ended lines of each lane are source and sink terminated and
biased. No external pull-up is needed for test equipment.
DP Technology: Signal Attributes
•  Four swing settings:
Setting 0: 400mV nominal
Setting 1: 600 mV nominal
Setting 2: 800 mV nominal
Setting 3: 1200 mV nominal (optional)
•  Four Pre-Emphasis settings
Setting 0: 0 dB nominal
Setting 1: 3.5 dB nominal
Setting 2: 6 dB nominal
Setting 3: 9.5 dB nominal (optional)
Compliance Test Specification emphasizes monotonicity not accuracy
•  No combination of voltage and preemphasis can exceed 1200mVolts p-p
•  Spread Spectrum Clocking
(30-33KHz spreading frequency,downspread)
DP Technology: AUX Channel, DPCD
•  Designated Control Link lane called ‘the AUX Channel’ specified.
Operates at 1Mbs and is used in Link Training and Link Management and
is Bidirectional Half Duplex.
•  The Transmitter is the master.
•  Receiver gains attention by pulling down on the Hot Plug Detect line.
•  Manchester II coding (shown subsequently)
AUX Control
AUX+
AUX-
Transmitter
Receiver (Sink)
Hot Plug Detect
Sink
Image
buffer
Tx
Hot Plug
Detect
Logic
Decode
Driver
Main Link
Bit Recovery
Lock
Err
Logic
AUX
AUX CH
Com
DPCD
EDID
Image
Frame
buffer
Display
MyDP: AUX Channel, DPCD
•  Designated Control Link lane called ‘the AUX Channel’ specified.
Operates at 1Mbs and is used in Link Training and Link Management and
is Bidirectional Half Duplex.
•  The Transmitter is the master.
•  Receiver identified by polling. Link serviced by occasional DPCD reads.
•  Manchester II coding (shown next page)
AUX+
Transmitter
Image
buffer
AUX Control
Tx
Receiver (Sink)
Main Link
Bit Recovery
Lock
Err
Logic
Logic
Decode
Driver
AUX
AUX CH
Com
DPCD
EDID
Image
Frame
buffer
Display
DP AUX Channel Implementation
Manchester II Signaling
MyDP AUX Channel Implementation
Manchester II Signaling, Single Ended
620kΩ
MyDP connection requirements.
Testing MyDP
Gnd
AUX-HPD
DD+
Pwr
MyDP Transmitters
ü AUX-HPD
ü Power Charging
ü Waveform Parametrics
ü Video/Audio Protocol Validation
MyDP Receivers
DisplayPort!
ü Power Charging
ü Video/Audio Protocol Response
ü Receiver Sensitivity/Jitter Tolerance
(using test mode BER counting)
Test Fixtures
These are the MyDP fixtures from Wilder Technologies. .
MyDP Fixture Schematic
From Wilder:
31
Confidentiality Label
May 10, 2013
MyDP Source Testing
AUX Ch
TPA
AUX Channel controller
Oscilloscope
MYDP
Device to Test
MyDP
TPA
DisplayPort Compliance
test software
The test suite for standard DP applies for MyDP
32
Confidentiality Label
May 10, 2013
Preparing for Test
Control of your MyDP Device
Agilent DisplayPort Test Application
MyDP
Main Link Phy Tests
Single ended AUX Tests
Set up your device
PHY Source Tests
-
Tx
Emp
Txn
Channel
Connector
+
Connector
Txp
TP3
TP2
TP1
TP4
Rxp
Rxn
+
EQ
-
Rx
MyDP source testing is at TP2 only
Eye Diagram
Jitter: Non ISI,Total Jitter,HBR2 RJ/DJ/TJ
Non Pre-Emph Level
Main Link Frequency
Pre-Emphasis Level
AUX Eye
Intra Pair Skew
AUX Sensitivity
MyDP Sink Testing
MyDP ‘Sink’ Calibration and Test
Test Equipment
Signal
Conditioning
Calibration
uUSB
Receptacle
uUSB Plug
Test
uUSB
PLUG
Dongle
VGA
DVI
HDMI
DP
Test
The test suite for standard DP applies for MyDP. Specs are different
Sink Test Jitter Components (RJ+DJ
+ISI)
N4903B JBERT
Sink Device
RJ+DJ+ISI
RJ+DJ
RJ
Loop Back
Rec
Rx
Error Detection
Tx Chip
ISI
RJ
DJ
Page 36
Summary of MyDP
MyDP is merely 1 lane DP so no modifications on the main link or protocol.
Only significant change is that the AUX lane is Single ended, and therefore, the
AUX sensitivity is halved.
MyDP can do 1080p/60 with 24 bits of color.
Same Connector, uUSB as MHL. Nothing else in common!
eDP1.4
Huge changes from eDP 1.3
Attribute
eDP 1.3
eDP1.4
Levels
4 (std DP)
6 (200mv-450mV)
Arbitrary allowed
Bit Rates
3 (std DP)
7 (1.45 to 5.4Gbs)
Arbitrary allowed
Pre-Emphasis
4 (std DP)
Arbitrary
Panel Self Refresh
Whole frame only
Partial Frame
enabled
Compression
No
Yes
Multi-touch
No
Yes
BackLight control
Yes
Yes Regional control
as well
AUX Channel Extended
Sink
Image
buffer
Main Link
Tx
APRL
Driver
Hot Plug
Detect
Logic
Decode
Bit Recovery
Lock
Err
Logic
DPCD
EDID
PSR
AUX
AUX CH
Com
M-Touch
BackLight
DataComp
Image
Frame
buffer
Display
Levels/PreEmphasis/BitRates
Reference Equalizers (for measurements only)
Test Points Available
eDP Test
Point.
Test Fixture
&Test Model
Test at a
Modified TP2.
Testing eDP
1.  Lots of bit rates and levels and arbitrary settings are allowed.
2.  TestPoint is TP3, the cable is considered part of the source
3.  A Test guideline is being created now. Mike Hamann of Intel
is leading this effort.
VESA® eDP1.4 PHY Compliance Test Guideline, Version 1.0
OPEN ISSUES:
HBR2 Pattern CP2520,
Data Rate Measurement (SSC),
TX AUX Channel Eye Derivation
RX AUX Over-Sampling Assumptions
Testing eDP
-
Tx
Emp
Txn
Channel
eDP source testing is at TP3 only. Equalizers need to be
applied to overcome losses of channel generally.
Eye after Channel (TP3)
Connector
+
Connector
Txp
TP3
TP2
TP1
TP4
Rxp
Rxn
+
EQ
-
Rx
eDP sink evaluation
is typical TP3 testing.
Eye after Equalizer (TP3Eq)
AUX Channel Testing
AUX Eye Testing
A
B
A Source Initiation of AUX communication
B Receiver Response to Source AUX
AUX Sensitivity
Reduce the Rx device’s AUX
level. (100mV shown, 240 spec’d)
45
A
B
May 10, 2013
eDP1.4 Fixturing
Testing eDP
A couple of points to make:
1.  There is no official compliance program—its embedded so
interoperability with other vendors is not a requirement.
2.  Use your own connector or pinoutàCreate your own fixture!
3.  Advise to consider validation/verification issues early in
process. HPD, Test Mode, level groups.
4.  What is tested will be driven by you and your vendor/
customer.
DisplayPort Technology
Continue to expect VESA will continue rolling out value-added
capabilities in Display Technologies. Our foundation is solid.
200 members strong-> Industry richness in participation to
address the transport and rendering of Display information.
Testing and validation is a core component of our interoperability
program and is seen as an ecosystem enabler.
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