KBL47S252T0-AB PC133 Unbuffered DIMM

KBL47S252T0-AB PC133 Unbuffered DIMM
PC133 Unbuffered DIMM
KBL47S252T0-AB
KBL47S252T0-AB SDRAM DIMM
32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs
GENERAL DESCRIPTION
FEATURE
The KINGBEE KBL47S252T0-AB is a 32M bit x 64 Synchronous
Dynamic RAM high density memory module. The KINGBEE
• Performance range
KBL47S252T0-AB consists of sixteen CMOS 16M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
KBL47S252T0-AB
Part No.
2K EEPROM in 8-pin TSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
Max Freq. (Speed)
133MHz (7.5ns @ CL=2)
•
•
•
•
•
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V ± 0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component
printed circuit board in parallel for each SDRAM.
The KBL47S252T0-AB is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
PIN NAMES
PIN CONFIGURATIONS (Front side/back side)
Pin Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
VSS
1
2
DQ0
3
DQ1
4
DQ2
5
DQ3
6
VD D
7
DQ4
8
DQ5
9
DQ6
10 DQ7
11 DQ8
12
VSS
13 DQ9
14 DQ10
15 DQ11
16 DQ12
17 DQ13
18
VD D
19 DQ14
20 DQ15
21 *CB0
22 *CB1
23
VSS
24
NC
25
NC
26
VD D
27
WE
28 DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
V SS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CLK0
V SS
DU
CS2
DQM2
DQM3
DU
VDD
NC
NC
*CB2
*CB3
V SS
DQ16
DQ17
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ18
DQ19
V DD
DQ20
NC
*VR E F
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
V DD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
NC
**SDA
**SCL
V DD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
V SS
DQ32
DQ33
DQ34
DQ35
VD D
DQ36
DQ37
DQ38
DQ39
DQ40
V SS
DQ41
DQ42
DQ43
DQ44
DQ45
VD D
DQ46
DQ47
*CB4
*CB5
V SS
NC
NC
VD D
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
V SS
A1
A3
A5
A7
A9
BA0
A11
VDD
CLK1
*A12
V SS
CKE0
CS3
DQM6
DQM7
*A13
VDD
NC
NC
*CB6
*CB7
V SS
DQ48
DQ49
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
VD D
DQ52
NC
*V REF
NC
V SS
DQ53
DQ54
DQ55
V SS
DQ56
DQ57
DQ58
DQ59
VD D
DQ60
DQ61
DQ62
DQ63
V SS
CLK3
NC
**SA0
**SA1
**SA2
VD D
Pin Name
Function
A0 ~ A11
Address input (Multiplexed)
BA0 ~ BA1
Select bank
DQ0 ~ DQ63
Data input/output
CLK0 ~ CLK3
Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS3
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7
DQM
VD D
Power supply (3.3V)
VSS
Ground
*V REF
Power supply for reference
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
DU
Don′t use
NC
No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
RamTek TECHNOLOGY INC. reserves the right to change products and specifications without notice.
PC133 Unbuffered DIMM
KBL47S252T0-AB
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V DD /VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
PC133 Unbuffered DIMM
KBL47S252T0-AB
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQM0
•
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
•
DQM1
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS3
CS2
DQM2
•
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
•
•
DQM4
CS
U0
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U8
DQM5
CS
U1
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U9
DQM6
U2
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U10
•
DQM3
DQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM7
CS
U3
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 ~ An, BA0 & 1
SDRAM U0 ~ U15
RAS
SDRAM U0 ~ U15
CAS
SDRAM U0 ~ U15
WE
SDRAM U0 ~ U15
CKE0
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
SDRAM U0 ~ U7
V DD
Vss
•
•
DQM CS
DQ0
DQ1
DQ2
U13
DQ3
DQ4
DQ5
DQ6
DQ7
•
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U6
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U11
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SCL
10KΩ
WP
A0
To all SDRAMs
CS
U14
U15
SDA
A1
A2
SA0 SA1 SA2
SDRAM U8 ~ U15
•
10Ω
CLK0/1/2/3
•
•
3.3pF
U0/U1/U2/U3
U4/U5/U6/U7
•
•
Two 0.1uF Capacitors
per each SDRAM
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
47KΩ
•
CS
Serial PD
V DD
CKE1
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
•
DQM
CS
Every DQpin of SDRAM
•
U12
•
DQM CS
DQ0
DQ1
DQ2
U5
DQ3
DQ4
DQ5
DQ6
DQ7
10Ω
DQn
CS
•
•
CS
•
U8/U9/U10/U11
U12/U13/U14/U15
PC133 Unbuffered DIMM
KBL47S252T0-AB
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V I N, VOUT
-1.0 ~ 4.6
V
Voltage on V D D supply relative to Vss
VDD , V DDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
16
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V SS = 0V, TA = 0 to 70 °C)
Parameter
Symbol
Min
Typ
Max
Unit
VDD , V DDQ
3.0
3.3
3.6
V
Input logic high voltage
V IH
2.0
3.0
VDDQ +0.3
V
1
Input logic low voltage
V IL
-0.3
0
0.8
V
2
Output logic high voltage
VO H
2.4
-
-
V
IO H = -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Supply voltage
Input leakage current
Note
Notes : 1. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ V DDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
(V DD = 3.3V, T A = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
CAPACITANCE
Pin
Address (A0 ~ A11, BA0 ~ BA1)
RAS, CAS, WE
Symbol
Min
Max
Unit
CADD
45
85
pF
CIN
45
85
pF
CKE (CKE0 ~ CKE1)
CCKE
25
45
pF
Clock (CLK0 ~ CLK3)
CCLK
15
21
pF
CS (CS0 ~ CS3)
CC S
15
25
pF
DQM (DQM0 ~ DQM7)
CDQM
10
15
pF
DQ (DQ0 ~ DQ63)
COUT
13
18
pF
PC133 Unbuffered DIMM
KBL47S252T0-AB
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)
Parameter
Operating current
(One bank active)
Precharge standby current
in power-down mode
Symbol
IC C 1
ICC2 P
I CC2PS
IC C 2N
Precharge standby current
in non power-down mode
IC C 2NS
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3 P
I CC3PS
IC C 3N
IC C 3NS
Version
Test Condition
Burst length = 1
tRC ≥ tRC (min)
IO = 0 mA
- 7C
-7A
1040
960
CKE ≤ VIL (max), tC C = 10ns
32
CKE & CLK ≤ V IL(max), tC C = ∞
32
CKE ≥ VI H(min), CS ≥ VIH (min), tC C = 10ns
Input signals are changed one time during 20ns
320
Note
mA
1
mA
mA
CKE ≥ VI H(min), CLK ≤ V IL(max), t C C = ∞
Input signals are stable
160
CKE ≤ VIL (max), tC C = 10ns
80
CKE & CLK ≤ V IL(max), tC C = ∞
80
CKE ≥ VI H(min), CS ≥ VIH (min), tC C = 10ns
Input signals are changed one time during 20ns
480
mA
CKE ≥ VI H(min), CLK ≤ V IL(max), t C C = ∞
Input signals are stable
400
mA
1120
IC C 4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
Refresh current
IC C 5
tRC ≥ tRC (min)
2000
Self refresh current
IC C 6
CKE ≤ 0.2V
Operating current
(Burst mode)
Unit
1840
C
32
L
12.8
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/V IL=V DDQ/V SSQ)
mA
mA
1
mA
2
mA
PC133 Unbuffered DIMM
KBL47S252T0-AB
AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200 Ω
•
Output
50Ω
VOH (DC) = 2.4V, I OH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
•
•
Z0 = 50 Ω
Output
50pF
870Ω
50pF
•
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
- 7C
- 7A
Unit
Note
Row active to row active delay
tRRD (min)
15
15
ns
1
RAS to CAS delay
tRCD (min)
15
20
ns
1
Row precharge time
tR P (min)
15
20
ns
1
tRAS (min)
45
45
ns
1
Row active time
tRAS (max)
Row cycle time
tRC (min)
Last data in to row precharge
t RDL(min)
Last data in to Active delay
100
ns
1
2
CLK
2,5
tDAL (min)
2 CLK + tRP
-
5
Last data in to new col. address delay
t CDL(min)
1
CLK
2
Last data in to burst stop
tBDL (min)
1
CLK
2
Col. address to col. address delay
tCCD (min)
1
CLK
3
ea
4
Number of valid output data
60
us
65
CAS latency=3
2
CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
PC133 Unbuffered DIMM
KBL47S252T0-AB
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter
- 7C
Symbol
Min
CAS latency=3
CLK cycle
time
tCC
CAS latency=2
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
7.5
- 7A
Max
1000
7.5
tSAC
CAS latency=2
tO H
CAS latency=2
Min
7.5
Unit
Note
ns
1
ns
1,2
ns
2
Max
1000
10
5.4
5.4
5.4
6
3
3
3
3
CLK high pulse width
tCH
2.5
2.5
ns
3
CLK low pulse width
tC L
2.5
2.5
ns
3
Input setup time
tSS
1.5
1.5
ns
3
Input hold time
tSH
0.8
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
tS H Z
CAS latency=2
5.4
5.4
5.4
6
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
ns
PC133 Unbuffered DIMM
KBL47S252T0-AB
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
H
Entry
Self
refresh
Exit
Bank active & row addr.
Read &
column address
Auto precharge disable
Write &
column address
Auto precharge disable
H
BA0,1
L
H
L
H
H
H
H
X
X
X
X
Entry
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
X
No operation command
L
L
H
L
L
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
L
L
H
Entry
H
L
L
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
H
H
X
H
X
X
X
L
H
H
H
3
Column
address
(A 0 ~ A 9)
V
L
Column
address
(A 0 ~ A 9)
H
Precharge power down mode
DQM
3
Row address
H
Exit
Exit
1,2
X
H
H
Note
3
All banks
Clock suspend or
active power down
A0 ~ A 9
A 11
3
Auto precharge enable
Bank selection
A 1 0/AP
L
Auto precharge enable
Burst stop
Precharge
CKEn-1
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA 1 : Bank select addresses.
If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A 10 /AP is "High" at row precharge, BA0 and BA 1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
PC133 Unbuffered DIMM
KBL47S252T0-AB
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.250
(133.350)
5.014
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
0.700
(17.780)
0.118
(3.000)
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.350
(8.890)
B
0.250
(6.350)
.450
(11.430)
C
0.0984 ±0.008
(2.500 ±0.2)
1.375
(34.925)
0.118
(3.000)
0.250
(6.350)
1.450
(36.830)
2.150
(54.61)
4.550
(115.57)
0.165 Min
(4.19 Min)
0.150 Max
(3.81 Max)
0.250
(6.350)
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Tolerances : ± .005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOPII
SDRAM Part No. :
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
Detail B
(2.500 ±0.2 )
0.250
(6.350)
0.0984 ±0.008
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
Detail C
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