CH7033B HDTV/VGA/ DVI Encoder

CH7033B
Chrontel
Brief Datasheet
CH7033B HDTV/VGA/ DVI Encoder
FEATURES
GENERAL DESCRIPTION
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The Chrontel CH7033B is specifically designed for
consumer electronics device and PC markets which
multiple high definition content display formats are
required. With its advanced video encoder, flexible
scaling engine and easy-to-configure audio interface, the
CH7033B satisfies manufactures’ products display
requirements and reduce their costs of development and
time-to-market.
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DVI encoder support up to 1080p
Supports Component YPrPb (HDTV) up to 1080p
and analog RGB (VGA) monitor up to 1920x1080
resolution
Support scaled and bypassed video streams output
from
VGA/HDTV
and
DVI
interfaces
simultaneously
Three 10-bit high speed DACs
SPDIF audio interface supports either 16-bit or 20bit stereo data for up to 192kHz/2ch
Support 2 channel I2S digital audio input for up to
24-bit data stream
(32kHz, 44.1kHz, 48kHz,
88.2kHz, 96kHz, 176.4kHzand 192kHz)
DDC master for reading EDID
Hot plug detection for DVI
TV/Monitor connection detect capability. DACs can
be switched off through programming internal
registers
Pixel-level color enhancement for brightness,
contrast, hue and saturation adjustment for HDTV
and VGA output
On-chip frame buffer supports frame rate conversion
provides the graphic controller the flexibility of
video timing output
Advanced scaling engine to upsize/downsize input
resolution for DVI display up to 1080p, VGA up to
1920 x1080 and HDTV up to 1080p
Supports 8/12/16/18/24-bit parallel interface input
for either RGB format (RGB-565, RGB-666 or
RGB-888 and etc.) or YCrCb format (ITU-R 656 or
ITU-R 601). 80/86 MPU interface and DE only
mode are also supported.
Wide range of input resolutions support for up to
1366x768 (i.e. 640x480, 720x480, 720x576,
800x600, 1024x600, 1024x768, 1280x800, and etc.)
Image display rotation support at 90/180/270 degree
or flipped in horizontal/vertical position
Pixel clock input frequency support for up to 165
MHz
IO Supply Voltages from 1.2V to 3.3V and
SPC/SPD Supply Voltages from 1.8V to 3.3V.
Programmable power management
Device fully programmable through serial port or
can automatically load firmware from Chrontel Boot
ROM (CH9904)
Offered in a 88-pin QFN package
High quality high-bandwidth uncompressed video like
DVI and YPrPb components or legacy VGA analog
display are supported by the device’s color format
converter. The 3 high-performance, 10-bit DACs can be
used for either HDTV display or VGA output depending
on manufactures’ products specification. The device is
compliant
with
EIA770-3
and
SMPTE
274M/293M/296M standards and supports HDTV
resolution for up to 1080p. The CH7033B has the ability
to generate composite syncs if required by the RGB
monitor.
The CH7033B’s 24-bit parallel bus accepts a wide range
of input data formats from the graphic controller. The
built-in video port supports 8/12/16/18/24-bit data
interface as well as 80/86 MPU interface. The video
format conversion module is capable of translating digital
RGB-565, RGB-666, RGB-888 or YCrCb (ITU-R 656,
ITU-R 601) signal to the DVI signal, combining with the
audio stream. The input digital signal also can be
transformed by the DACs for HDTV or VGA analog
outputs. The device’s video capture block supports input
display resolution for up to 1366x768 which can be either
interlaced or non-interlaced timing.
The CH7033B has incorporated a high speed SDRAM
that allows manufactures to design their products to
achieve simultaneous display digital signal and analog
signal. Leverage the benefit of the framebuffer, the
device’s sophisticated scaler is able to produce two same
video content, which will be routed to separate output
driver for display. Frame Rate Conversion is embedded
in the scaler; it can maximize the native input resolution
up to 1080p for HD display. Furthermore the CH7033B
provides additional image manipulation features
including image rotation that can be controlled through
programming internal registers.
The device supports both SPDIF and 2-channel I²S digital
audio input. Its high fidelity audio decoder engine has
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CHRONTEL
APPLICATION
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Media Internet Devices
Media Storage Boxes
Smart-books
Digital Video Players
Digital Video Recorders
Portable Media Players
CH7033B
audio input. Its high fidelity audio decoder engine has
the capability of sampling audio frequency for up to
192k/2ch. The SPIDF supports PCM encoded data and
compressed audio including Dolby Digital and DTS.
The CH7033B has an image enhancement function that
can fine tune brightness, contrast, hue and saturation
down to the pixel-level.
When the HPD signal is asserted, the CH7033B will
automatically generate an interrupt to the processor. A
build-in DDC port can read the EDID data from DVI
monitor through programming. registers by the processor.
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CHRONTEL
CH7033B
SDRAM
DAC0
Scaler
D[23:0]
SPDIF
DAC1
Input
format
decoder
DAC2
SPDIF
decoder
TLC*/TLC
Audio packet
org
I2S_CK
I2S_WS
I2S_D
DAC
Video
Format
Mix video and audio
TMDS
(TERC4)
encoder
TDC1*/TDC1
TDC2*/TDC2
I2S
decoder
DDC_SC
SPC
SPD
TDC0*/TDC0
Differential
serializer
I2C slave
Registers,
EDID buffer
EDID MCU
DDC_SD
IRQ
HPD
SPCM
SPDM
Figure 1: Functional Block Diagram
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CHRONTEL
CH7033B
1.0 PIN-OUT
Package Diagram
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
D22
D23
H/WEB
V
DE/CSB
VDDIO
GCLK
IRQ
ISET
AGND_DAC
DAC0
AVDD_DAC
DAC1
AGND_DAC
DAC2
AVDD_DAC
SPCM
AVDD_PLL
AGND_PLL
SPDM
XI/FIN
XO
1.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
CHRONTEL
CH7033B
88QFN
NC
GPIO
DDC_SD
DDC_SC
GNDMQ
VDDMQ
VDDMS
GNDMS
I2S_CK
I2S_WS
I2S_D/SPDIF
SPD
SPC
VDDMQ
GNDMQ
HPD
Reserved
VSO
HSO/CSYNC
AGND
AVDD
DGND
AVDD
NC
D4
D3
D2
D1
D0
VDDH
TLC*
TLC
VSSH
TDC0*
TDC0
TDC1*
TDC1
VSSH
TDC2*
TDC2
VDDH
DVDD
Reserved
Reserved
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
D21
D20
D19
D18
D17
D16
RESETB
D15
VDDMS
DVDD
GNDMS
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
AGND
Figure 2: 88 pin QFN Package (Top View)
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1.2
CH7033B
Pin Description
Table 1: Pin Name Descriptions (QFN88 Package)
Pin #
Type
Symbol
Description
1~6,8,
12~21,
25~29,
87~88,
In
D[23:0]
7
In
RESETB
31,32
Out
TLC*,TLC
34,35
Out
TDC0*,TDC0
36,37
Out
TDC1*,TDC1
39,40
Out
TDC2*,TDC2
43
N/A
Reserved
44
N/A
Reserved
48
Out
HSO/CSYNC
49
Out
VSO
50
N/A
Reserved
51
In
HPD
54
In
SPC
55
In/out
SPD
56
In
I2S_D/SPDIF
57
In
I2S_WS
Data Input
These pins accept 24 data input lines from a digital video port of a
graphics controller. The swing is defined by VDDIO.
All the unused Data input pins should be pulled low with 10KΩ
resistors or shorted to Ground directly.
Reset Input
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the serial
port.
DVI Clock Outputs
These pins provide the differential clock output for the DVI .
DVI Data Channel 0 Outputs
These pins provide the DVI differential outputs for data channel 0
DVI Data Channel 1 Outputs
These pins provide the DVI differential outputs for data channel 1
DVI Data Channel 2 Outputs
These pins provide the DVI differential outputs for data channel 2
Reserved
This pin should connect to DVDD directly
Reserved
This pin should connect to DGND directly
Horizontal Sync Signal Output
The amplitude of this pin is from 0 to AVDD
It also functions as a Composite sync output.
Vertical Sync Signal Output
The amplitude of this pin is from 0 to AVDD
Reserved
This pin should be left open or pulled low with a 10 KΩ resistor in the
application.
Hot Plug Detect
This input pin determines whether the DVI output driver is connected
to a DVI monitor. This pin should be pull low with 47 KΩ Resistor.
Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull-up
6.8 KΩ resister is required.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up 6.8 KΩ resister is required.
I2S Data input or SPDIF Audio Signal Input
In default, this pin is configured to SPDIF audio signal input. The
signal level is 0-2.5V.
I2S audio input can be configured through programming CH7033B
registers.
I2S Channel Select Signal
58
In
I2S_CK
I2S Clock Signal
63
Out
DDC_SC
Routed Serial Port Clock Output to DDC
This pin functions as the clock bus of the serial port to DDC receiver.
This pin will require a pull-up 1.8 KΩ resistor to the desired voltage
level. A pull-low resistor 10 KΩ to ground if unused.
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CHRONTEL
CH7033B
Pin #
Type
Symbol
Description
64
In/out
DDC_SD
65
In/out
GPIO
Routed Serial Port Data to DDC
This pin functions as the bi-directional data pin of the serial port to
DDC receiver. This pin will require a pull-up 1.8 KΩ resistor to the
desired voltage level. A pull-low resistor 10 KΩ to ground if unused
General Purpose Input Output
67
Out
XO
68
In
XI/FIN
69
In/Out
SPDM
72
Out
SPCM
74
Out
DAC2
Crystal Output
A parallel resonance crystal should be attached between this pin and
XI/FIN. However, if an external CMOS clock is attached to XI/FIN,
XO should be left open.
Crystal Input / External Reference Input
A parallel resonance crystal should be attached between this pin and
XO. However, an external 3.3V CMOS compatible clock can drive
the XI/FIN input.
Routed Serial Port Data to CH9904 BOOT ROM
This pin functions as the bi-directional data pin of the serial port to
CH9904 BOOT ROM. This pin will require a pull-up 6.8 KΩ resistor
to the desired voltage level. A pull-low resistor 10K to ground if
unused.
Routed Serial Port Clock Output to CH9904 BOOT ROM
This pin functions as the clock bus of the serial port to CH9904 BOOT
ROM. This pin will require a pull-up 6.8 KΩ resistor to the desired
voltage level. A pull-low resistor 10 KΩ to ground if unused.
YPrPb or Analog RGB Output
76
Out
DAC1
YPrPb or Analog RGB Output
78
Out
DAC0
YPrPb or Analog RGB Output
80
In
ISET
81
Out
IRQ
Current Set Resistor Input
This pin sets the DAC current. A 1.2 KΩ, 1% tolerance resistor should
be connected between this pin and AGND_DAC using short and wide
traces.
Programmed Interrupt output.
82
In
GCLK
84
In
DE/CSB
85
In/out
V
86
In/out
H/WEB
24, 66
N/A
NC
6
External Clock Inputs
The input is the clock signal input to the device for use with the H, V,
DE and D[23:0] data.
Data Input Indicator
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
It is also a CSB signal input of MPU interface
The amplitude will be 0V to VDDIO.
Vertical Sync Input/Output
When the SYO control bit is low, this pin accepts a vertical sync input
for use with the input data. The amplitude will be 0 to VDDIO.
When the SYO control bit is high, the device will output a vertical
sync pulse. The output is driven from the VDDIO supply.
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a horizontal sync
input for use with the input data. The amplitude will be 0 to VDDIO.
When the SYO control bit is high, the device will output a horizontal
sync pulse. The output is driven from the VDDIO supply.
It is also the WEB signal of MPU interface.
Not Connect
These pins should be left open.
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CHRONTEL
CH7033B
Pin #
Type
Symbol
Description
9,60
Power
VDDMS
SDRAM Power Supply (3.3V)
59,11
Power
GNDMS
SDRAM Ground
10,42
Power
DVDD
Digital Power Supply (1.8V)
45
Power
DGND
Digital Ground
23,46
Power
AVDD
Analog Power Supply (3.3V)
22,47
Power
AGND
Analog Ground
30,41
Power
VDDH
DVI Power Supply (3.3V)
33,38
Power
VSSH
DVI Ground
53,61
Power
VDDMQ
SDRAM output buffer Power Supply (3.3V)
52,62
Power
GNDMQ
SDRAM output buffer Ground
71
Power
AVDD_PLL
PLL Power Supply (1.8V)
70
Power
AGND_PLL
PLL Ground
77,73
Power
AVDD_DAC
DAC Power Supply (3.3V)
75,79
Power
AGND_DAC
DAC Ground
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CHRONTEL
CH7033B
2.0 PACKAGE DIMENSIONS
BOTTOM VIEW
TOP VIEW
B
A
22
1
B/2
1
22
88
23
23
88
Pin 1
3
A
C
C/2
44
67
44
67
45
66
66
45
E
D
(4x) 2
F 4
I
G
H
Figure 3: 88 Pin QFN Package (10 x 10 mm)
Table of Dimensions
No. of Leads
88 (10 x 10 mm)
MilliMIN
meters
MAX
A
10.00
B
6.60
8.25
C
6.60
8.25
D
0.40
SYMBOL
E
0.15
0.25
F
0.35
0.60
G
0.70
0.90
H
0.00
0.05
I
0.203
Notes:
1. Conforms to JEDEC standard JESD-30 MO-220.
8
2.
Side of body may be square or curved.
3.
Exposed pad may have chamfer in area of Pin 1.
4.
Pins may protrude from edge of body by 0.05 mm.
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CHRONTEL
CH7033B
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes
at any time without notice to improve and supply the best possible product and is not responsible and
does not assume any liability for misapplication or use outside the limits specified in this document. We
provide no warranty for the use of our products and assume no liability for errors contained in this
document. The customer should make sure that they have the most recent data sheet version. Customers
should take appropriate action to ensure their use of the products does not infringe upon any patents.
Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE
SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN
CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose
failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number
Package Type
Operating Temperature Range
Minimum Order Quantity
CH7033B-BF
88QFN, Lead-free
Commercial : -20 to 70°C
168/Tray
CH7033B-BFI
88QFN, Lead-free
Industrial : -40 to 85°C
168/Tray
Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: [email protected]
2011 Chrontel - All Rights Reserved.
209-1000-027
Rev. 1.2
09/01/2011
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