M366S0823DTS

M366S0823DTS

Revision History

Revision 0.0 (July, 2000)

• PC133 first published.

http://www.BDTIC.com/SAMSUNG

PC133 Unbuffered DIMM

REV. 0.0 July, 2000

http://www.BDTIC.com/SAMSUNG

M366S0823DTS PC133 Unbuffered DIMM

M366S0823DTS SDRAM DIMM

8Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD

GENERAL DESCRIPTION

The Samsung M366S0823DTS is a 8M bit x 64 Synchronous

Dynamic RAM high density memory module. The Samsung

M366S0823DTS consists of eight CMOS 8M x 8 bit with 4banks

Synchronous DRAMs in TSOP-II 400mil package and a 2K

EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM.

The M366S0823DTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURE

• Performance range

Part No.

Max Freq. (Speed)

M366S0823DTS-C7A [email protected] & [email protected]

• Burst mode operation

• Auto & self refresh capability (4096 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V

±

0.3V power supply

• MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB : Height (1,375mil), single sided component

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

20

21

22

23

24

25

14

15

16

17

18

19

26

27

28

10

11

12

13

8

9

6

7

3

4

5

1

2

48

49

50

51

52

53

42

43

44

45

46

47

54

55

56

38

39

40

41

34

35

36

37

29

30

31

32

33

DQ10

DQ11

DQ12

DQ13

V

DD

DQ14

DQ15

*CB0

*CB1

V

SS

NC

NC

V

DD

WE

DQM0

V

SS

DQ0

DQ1

DQ2

DQ3

V

DD

DQ4

DQ5

DQ6

DQ7

DQ8

V

SS

DQ9

71

72

73

74

67

68

69

70

61

62

63

64

65

66

57

58

59

60

81

82

83

84

75

76

77

78

79

80

CLK0

V

SS

DU

CS2

DQM2

DQM3

DU

V

DD

NC

NC

*CB2

*CB3

V

SS

DQ16

DQ17

DQM1

CS0

DU

V

SS

A0

A2

A4

A6

A8

A10/AP

BA1

V

DD

V

DD

104

105

106

107

108

109

98

99

100

101

102

103

110

111

112

94

95

96

97

90

91

92

93

85

86

87

88

89

DQ25

DQ26

DQ27

V

DD

DQ28

DQ29

DQ30

DQ31

V

SS

CLK2

NC

WP

**SDA

**SCL

V

DD

DQ18

DQ19

V

DD

DQ20

NC

*V

REF

*CKE1

V

SS

DQ21

DQ22

DQ23

V

SS

DQ24

132

133

134

135

136

137

126

127

128

129

130

131

138

139

140

118

119

120

121

122

123

124

125

113

114

115

116

117

DQ42

DQ43

DQ44

DQ45

V

DD

DQ46

DQ47

*CB4

*CB5

V

SS

NC

NC

V

DD

CAS

DQM4

V

SS

DQ32

DQ33

DQ34

DQ35

V

DD

DQ36

DQ37

DQ38

DQ39

DQ40

V

SS

DQ41

DQ57

DQ58

DQ59

V

DD

DQ60

DQ61

DQ62

DQ63

V

SS

*CLK3

NC

**SA0

**SA1

**SA2

V

DD

DQ50

DQ51

V

DD

DQ52

NC

*V

REF

NC

V

SS

DQ53

DQ54

DQ55

V

SS

DQ56

160

161

162

163

164

165

154

155

156

157

158

159

166

167

168

146

147

148

149

150

151

152

153

141

142

143

144

145

*A12

V

SS

CKE0

*CS3

DQM6

DQM7

*A13

V

DD

NC

NC

*CB6

*CB7

V

SS

DQ48

DQ49

DQM5

*CS1

RAS

V

SS

A1

A3

A5

A7

A9

BA0

A11

V

DD

*CLK1

PIN NAMES

Pin Name Function

A0 ~ A11

BA0 ~ BA1

Address input (Multiplexed)

Select bank

DQ0 ~ DQ63 Data input/output

CLK0, CLK2 Clock input

CKE0

CS0, CS2

RAS

CAS

Clock enable input

Chip select input

Row address strobe

Column address strobe

WE

DQM0 ~ 7

V

DD

V

SS

*V

REF

SDA

SCL

SA0 ~ 2

WP

DU

NC

Write enable

DQM

Power supply (3.3V)

Ground

Power supply for reference

Serial data I/O

Serial clock

Address in EEPROM

Write protection

Don

′ t use

No connection

* These pins are not used in this module.

** These pins should be NC in the system

which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 0.0 July, 2000

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M366S0823DTS PC133 Unbuffered DIMM

PIN CONFIGURATION DESCRIPTION

CLK

Pin

CS

CKE

A0 ~ A11

BA0 ~ BA1

Bank select address

RAS

CAS

WE

DQM0 ~ 7

DQ0 ~ 63

WP

V

DD

/V

SS

Name

System clock

Chip select

Clock enable

Address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Write protection

Power supply/ground

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+t

SS

prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA8

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

Data inputs/outputs are multiplexed on the same pins.

WP pin is connected to V

SS

through 47K

Resistor.

When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write - protected.

Power and ground for the input buffers and the core logic.

REV. 0.0 July, 2000

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M366S0823DTS PC133 Unbuffered DIMM

FUNCTIONAL BLOCK DIAGRAM

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

A0 ~ An, BA0 & 1

RAS

CAS

WE

CKE0

V

DD

Vss

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CS2

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQn

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U4

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U5

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

10

U3

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

Every DQpin of SDRAM

Two 0.1uF Capacitors per each SDRAM

To all SDRAMs

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U7

SCL

Serial PD

A0 A1 A2

SA0 SA1 SA2

SDA

WP

47K

CLK0/2

10

U0/U2

U4/U6

U1/U3

U5/U7

10

3.3pF

CLK1/3

10pF

REV. 0.0 July, 2000

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M366S0823DTS PC133 Unbuffered DIMM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

DD

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

V

IN

, V

OUT

V

DD

, V

DDQ

T

STG

P

D

I

OS

Value

-1.0 ~ 4.6

-1.0 ~ 4.6

-55 ~ +150

8

50

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Unit

V

V

°

C

W mA

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

SS

= 0V, T

A

= 0 to 70

°

C)

Parameter

Supply voltage

Input logic high votlage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

V

Symbol

DD

V

I

, V

V

V

V

IH

IL

LI

DDQ

OH

OL

Min

3.0

2.0

-0.3

2.4

-

-10

Typ

3.3

3.0

0

-

-

-

V

Max

3.6

DDQ

+0.3

0.8

-

0.4

10

Notes :

1. V

IH

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

IL

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

V

IN

V

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Unit

V

V

V

V

V uA

Note

1

2

I

OH

= -2mA

I

OL

= 2mA

3

CAPACITANCE

(V

DD

= 3.3V, T

A

= 23

°

C, f = 1MHz, V

REF

= 1.4V

±

200 mV)

Pin

Address (A0 ~ A11, BA0 ~ BA1)

RAS, CAS, WE

CKE (CKE0)

Clock (CLK0, CLK2)

CS (CS0, CS2)

DQM (DQM0 ~ DQM7)

DQ (DQ0 ~ DQ63)

Symbol

C

ADD

C

IN

C

CKE

C

CLK

C

CS

C

DQM

C

OUT

Min

22

15

6

6

30

30

30

Max

30

25

8

8

45

45

45

Unit

pF pF pF pF pF pF pF

REV. 0.0 July, 2000

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M366S0823DTS

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°

C)

PC133 Unbuffered DIMM

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

I

CC1

Burst length =1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

I

CC2

P CKE

V

IL

(max), t

CC

= 10ns

I

CC2

PS CKE & CLK

V

IL

(max), t

CC

=

I

CC2

N

CKE

V

IH

(min), CS

V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

I

I

CC2

CC3

NS

NS

CKE

V

IH

(min), CLK

V

IL

(max), t

CC

=

Input signals are stable

I

CC3

P CKE

V

IL

(max), t

CC

= 10ns

I

CC3

PS CKE & CLK

V

IL

(max), t

CC

=

I

CC3

N

CKE

V

IH

(min), CS

V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

V

IH

(min), CLK

V

IL

(max), t

CC

=

Input signals are stable

Operating current

(Burst mode)

I

CC4

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs

Refresh current

Self refresh current I

I

CC5

CC6 t

RC

≥ t

RC

(min)

CKE

0.2V

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

).

Version

-7A tCC=7.5ns

tCC=10ns

Unit Note

600

920

1,080

8

8

120

48

24

24

200

120

8

560

760

1,000 mA mA mA mA mA mA mA mA mA

1

1

2

REV. 0.0 July, 2000

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M366S0823DTS

AC OPERATING TEST CONDITIONS

(V

DD

= 3.3V

±

0.3V, T

A

= 0 to 70

°

C)

Parameter

AC input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

PC133 Unbuffered DIMM

Unit

V

V ns

V

3.3V

Vtt = 1.4V

Output

870

1200

V

OH

(DC) = 2.4V, I

OH

= -2mA

V

OL

(DC) = 0.4V, I

OL

= 2mA

50pF

Output

Z0 = 50

50

50pF

(Fig. 1) DC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

(Fig. 2) AC output load circuit

Parameter

Row active to row active delay

RAS to CAS delay

Symbol

t

RRD

(min) t

RCD

(min)

Version

-7A tCC=7.5ns

15

20

tCC=10ns

20

20

Unit

ns ns

Row precharge time t

RP

(min) t

RAS

(min)

20

45

20

50 ns ns

Row active time

Row cycle time

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

Col. address to col. address delay t

RAS

(max) t t t

RC

(min) t

RDL

(min)

DAL

(min) t

CDL

(min)

BDL

(min) t

CCD

(min)

65

100

2

2 CLK + 20 ns

1

1

1

70 us ns

CLK

-

CLK

CLK

CLK

CAS latency=3 2

Number of valid output data ea

CAS latency=2 1

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Note

1

2

4

2

2

3

1

1

1

1

REV. 0.0 July, 2000

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M366S0823DTS PC133 Unbuffered DIMM

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

-7A

CLK cycle time

CLK to valid output delay

Output data hold time

Parameter

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

CLK to output in Hi-Z

CAS latency=3

CAS latency=2

Symbol

t t t t t t t t t

CC

SAC

OH

CH

CL

SS

SH

SLZ

SLZ

-

-

3.0

-

Min tCC=7.5ns

Max

7.5

-

1000

-

2.5

2.5

1.5

0.8

1

5.4

-

-

-

5.4

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

1

-

-

3.0

3.0

2

1

3.0

3.0

-

-

Min tCC=10ns

Max

10

10

1000

6.0

6.0

6.0

6.0

Unit

ns ns ns ns ns ns ns ns ns

Note

1

1,2

1,2

3

3

3

3

2

REV. 0.0 July, 2000

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M366S0823DTS PC133 Unbuffered DIMM

SIMPLIFIED TRUTH TABLE

Command

CKEn-1 CKEn CS RAS CAS WE DQM BA

0,1

A

10

/AP

A

11,

A

9

~ A

0

Note

Register

Refresh

Mode register set

Auto refresh

Entry

Self refresh

Exit

H

H

X

H

L

L

L

L

L

L

L

L

H

X

X

OP code

X

L H

L

H

L

H

X

L

H

X

H

H

X

H

X X

Bank active & row addr.

Read & column address

Auto precharge disable

Auto precharge enable

Write & column address

Auto precharge disable

Auto precharge enable

Burst stop

H

H

H

H

X

X

X

X

L

L

L

H

H

H

L

L

H

H

L

L

X

X

X

X

V

V

V

L

H

Row address

L

H

Column address

(A

0

~ A

8

)

Column address

(A

0

~ A

8

)

X

Precharge

Bank selection

All banks

H X L L H L X

V

X

L

H

X

Clock suspend or active power down

Entry

Exit

H

L

L

H X

H

H

L

X

X

X

V

X

X

X

V

X

X

X

V

X

X

X

Entry H L X

Precharge power down mode

Exit L H

L

H

L

H

X

V

H

X

V

H

X

V

X

X

DQM H X V X 7

H X X X

No operation command H X X X

L H H H

(V=Valid, X=Don

′ t Care, H=Logic High, L=Logic Low)

Notes :

1. OP Code : Operand code

A

0

~ A

11

& BA

0

~ BA

1

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA

0

~ BA

1

: Bank select addresses.

If both BA

0

and BA

1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

0

is "Low" and BA

1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA

0

is "High" and BA

1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA

0

and BA

1 are "High" at read, write, row active and precharge, bank D is selected.

If A

10

/AP is "High" at row precharge, BA

0

and BA

1

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

RP

after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

4

4,5

4

4,5

6

1,2

3

3

3

3

REV. 0.0 July, 2000

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M366S0823DTS

PACKAGE DIMENSIONS

PC133 Unbuffered DIMM

0.375

(9.525)

0.096

(2.44)

0.118

(3.000)

0.125

(3.175)

5.250

(133.350)

5.014

(127.350)

.118DIA

±

0.004

(3.000DIA

±

0.100)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.089

(2.26)

Units : Inches (Millimeters)

R 0.050+0.04

(R 1.27+0.1)

R 0.079

(R 2.000)

0.157

±

0.004

(4.000

±

0.100)

0.100 Max

(2.54 Max)

0.250

(6.350)

0.123

±

0.005

(3.125

±

0.125)

Detail A

0.079

±

0.004

(2.000

±

0.100)

Tolerances :

±

0.005(.13) unless otherwise specified

The used device is 8Mx8 SDRAM, TSOP

SDRAM Part No. : K4S640832D-TC75

0.250

(6.350)

0.123

±

0.005

(3.125

±

0.125)

0.079

±

0.004

(2.000

±

0.100)

Detail B

0.050

±

0.0039

(1.270

±

0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

REV. 0.0 July, 2000

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