VersaLogic VL-EPM 35 dual board computer Reference Manual
Below you will find brief information for dual board computer VL-EPM 35. The VL-EPM 35 is a feature-packed dual board computer designed for OEM control projects requiring fast processing and designed-in reliability and longevity (product lifespan). Its features include Intel Core 2 Duo processor, 2.26 GHz, 1066 MHz FSB, 6 MB cache, simultaneous VGA and LVDS outputs, up to 4 GB DDR3 SO-DIMM socket, TVS devices for ESD protection, two SATA 3 Gb/s ports, six USB 2.0 ports, SPX interface supports up to four (external) SPI devices either of user design or any of the SPX™ series of expansion boards, with clock frequencies from 1-8MHz. The VL-EPM-35 is a PC/104-Plus-compliant single board computer with an Intel Core 2 Duo processor. The VL-EPM-35 is built for reliability with voltage sensing reset circuits and current limiting external power rails. VL-EPM-35 boards are subjected to 100% functional testing and are backed by a limited two-year warranty. Careful parts sourcing and US-based technical support ensure the highest possible quality, reliability, service and product longevity for this exceptional SBC.
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Reference
Manual
DOC. REV. 1/16/2012
VL-EPM-35
Intel Dual Core Based Dual
Board Computer with Dual
Gigabit Ethernet, SATA,
PC/104-Plus, Video, Audio, and
SPX
WWW.VERSALOGIC.COM
12100 SW Tualatin Road
Tualatin, OR 97062-7341
(503) 747-2261
Fax (971) 224-4708
Copyright © 2013 VersaLogic Corp. All rights reserved.
Notice:
Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes.
PC/104 and the PC/104 logo are trademarks of the PC/104 Consortium.
VL-EPM-35 Reference Manual ii
Product Release Notes
Rev 2.00 – Minor changes to improve manufacturability. No customer impact.
Rev 1.00 – Initial commercial release.
Support Page
The VL-EPM-35 support page, at http://www.versalogic.com/private/leopardsupport.asp
, contains additional information and resources for this product including:
Reference Manual (PDF format)
Operating system information and software drivers
Data sheets and manufacturers’ links for chips used in this product
Photograph of the circuit board
BIOS information and upgrades
Utility routines and benchmark software
Note: This is a private page for VL-EPM-35 users that can be accessed only be entering this address directly. It cannot be reached from the VersaLogic homepage.
The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with your
VersaLogic product.
VersaTech KnowledgeBase
VL-EPM-35 Reference Manual iii
Contents
VL-EPM-35 Connector Functions and Interface Cables ..................................... 23
CBR-3406 Connector Functions and Mating Connectors ................................... 24
VL-EPM-35 Reference Manual iv
Contents
LVDS Flat Panel Display Connector (JN9)......................................................... 47
VL-EPM-35 Reference Manual v
Contents
VL-EPM-35 Reference Manual vi
Introduction
Description
F EATURES AND C ONSTRUCTION
The VL-EPM-35 is a feature-packed dual board computer (DBC) designed for OEM control projects requiring fast processing and designed-in reliability and longevity (product lifespan). Its features include:
Intel Core 2 Duo processor, 2.26
GHz, 1066 MHz FSB, 6 MB cache
Audio stereo line in, stereo line out
Simultaneous VGA and LVDS outputs
Up to 4 GB DDR3 SO-DIMM socket
USB MiniBlade socket
Dual 10BaseT / 100BaseTX /
1000BaseT Ethernet interface
Intel GMA 4500 MHD graphics core
PC/104-Plus (PCI and ISA) expansion
Two SATA 3 Gb/s ports
CPU temperature sensor
Five serial ports
V
CC
sensing reset circuit
PC/104-compliant footprint
Field upgradeable BIOS with OEM enhancements
External HD Audio compatible
Six USB 2.0 ports
eUSB SSD site
Customizing available
PS/2 keyboard and mouse interface
TVS devices for ESD protection
Watchdog timer
SPX interface supports up to four
(external) SPI devices either of user design or any of the SPX™ series of expansion boards, with clock frequencies from 1-8MHz
The VL-EPM-35 is a PC/104-Plus-compliant single board computer with an Intel Core 2 Duo processor. The board is compatible with popular operating systems such as Windows, Windows
Embedded, QNX, VxWorks and Linux.
The VL-EPM-35 features high reliability design and construction, including voltage sensing reset circuits and current limiting external power rails.
VL-EPM-35 boards are subjected to 100% functional testing and are backed by a limited twoyear warranty. Careful parts sourcing and US-based technical support ensure the highest possible quality, reliability, service and product longevity for this exceptional SBC.
Additional I/O expansion is available through the high-speed PC/104-Plus (PCI) and PC/104
(ISA) connectors. The VL-EPM-35 is equipped with two multifunction utility cables, VL-CBR-
3406 (breakout board) and VL-CBR-8006, that provide numerous standard I/O interfaces.
VL-EPM-35 Reference Manual 1
Description
Technical Specifications
Specifications are typical at 25°C with 5.0V supply unless otherwise noted.
Board Size:
3.55” x 3.775” (PC/104 standard) with connector overhangs in designated connector areas
Storage Temperature:
-40° C to 85° C
Operating Temperature: (with Windows XP running with both CPU cores at 1.2GHz/95% utilization with active
2D and 3D video)
VL-EPM-35S: 0° C to +60° C free air, no airflow
VL-EPM-35E: -40° C to +85° C free air
Power Requirements: (with 1 GB system DDR3 SO-
DIMM, keyboard and mouse , Running Windows XP)
5V
± 5% @ 2.0A idle (6.5A max.)
+3.3V or ± 12V may be required by some expansion modules
System Reset:
V cc
sensing, resets below 4.70V typ.
DRAM:
Up to 4 GB, DDR3 SO-DIMM, 800 MHz PC3-
6400 or 1067 MHz PC3-8500
Video Interface:
Intel GMA 4500 MHD graphics core
Analog output for VGA
LVDS output for TFT FPDs
Up to 1280 x 1024 (24 bits)
SATA Interface:
Two SATA 3 Gb/s ports
Flash Interface:
One MiniBlade socket, supports USB only
USB SSD socket (eUSB)
Ethernet Interface:
PCIe based 82574IT supporting autodetect
10BaseT / 100BaseTX / 1000BaseT (top board)
PCI based 82541ER supporting autodetect
10BaseT / 100BaseTX / 1000BaseT (bottom board)
Serial Ports:
Serial Port 1 Interface: RS-232 16C550 compatible, All handshake lines implemented.
Serial Port 2 Interface: RS-232/422/485,
16C550 compatible, 4-wire RS 232 (Only CTS and RTS handshaking). Auto direction control.
Serial Port 3 Interface: RS-232/422/485,
16C550 compatible, 4-wire RS 232 (Only CTS and RTS handshaking). Auto direction control.
Serial Port 4 Interface: RS-232/422/485,
16C550 compatible, 4-wire RS 232 (Only CTS and RTS handshaking). Auto direction control.
Serial Port 5 Interface: RS-232/422/485,
16C550 compatible, 4-wire RS 232 (Only CTS and RTS handshaking).
Specifications are subject to change without notice.
LPT Interface:
Bi-directional/EPP/ECP compatible
BIOS:
Phoenix Embedded BIOS© with StrongFrame®
Technology and OEM enhancements
Field-upgradeable with Flash BIOS Update Utility
Bus Speed:
PC/104-Plus (PCI): 33MHz
PC/104 (ISA): 8MHz
Compatibility:
Embedded-PCI (PC/104-Plus version 2.3) – full compliance, 3.3V signaling
Weight:
0.306 kg (0.675 lb)
VL-EPM-35 Reference Manual 2
Description
VL-EPM-35 Block Diagram
Clock
SPI
BIOS
RJ-45
PC/104-Plus
(PCI)
PCI-to-ISA
ITE8888
PC/104 (ISA)
Intel
Core 2 Duo
Processor
DDR3
SO-DIMM
Intel
GS45
Chipset
Gigabit
Ethernet
82574IT
PCIe
PCI
Intel ICH9
I/O Controller
Hub
LVDS SVGA
Serial ATA
Digital Audio
FPGA
SPX
Mini I/O
LPC47N217
Mini-
Blade
Serial
Port 5
USB
1-4
I/O Connector
TOP BOARD
BOTTOM BOARD
Super I/O
SCH3114
Battery
Gigabit
Ethernet
82541ER
Codex
Ethernet
Serial
Ports 1/2
LPT /
Floppy
PS/2
80-pin High Density Connector
USB
5-6
Serial
Ports 3/4
USB
SSD
Audio
Figure 1. System Block Diagram
VL-EPM-35 Reference Manual 3
Description
Thermal Considerations
CPU D IE T EMPERATURE
The CPU die temperature is affected by numerous conditions, such as CPU utilization, CPU speed, ambient air temperature, air flow, thermal effects of adjacent circuit boards, external heat sources, and many others.
The CPU is protected from over temperature conditions by several mechanisms.
The CPU will automatically slow down by 50% whenever its die temperature exceeds 105° C.
When the temperature falls back below 105° C, the CPU resumes full speed operation.
As a failsafe, if the CPU die temperature climbs above 115° C, the CPU will turn itself off to prevent damage to the chip.
M ODEL D IFFERENCES
VersaLogic offers both standard and extended temperature models of the VL-EPM-35. The basic operating temperature specification for both models is shown below.
VL-EPM-35S: 0° C to +60° C free air, no airflow
VL-EPM-35E: -40° C to +85° C free air
To reliably function at extreme temperatures the extended temperature model specifications deviate from the standard model in the following ways:
The DRAM interface is slowed. PC3-6400 memory runs at 600 MHz. PC3-8500 memory runs at 800 MHz.
The DRAM refresh rates are doubled.
The Front Side Bus speed is reduced to 800 MHz.
Maximum processor speed is limited to 1200 MHz.
The graphics core is limited to 400 MHz.
RoHS Compliance
The VL-EPM-35 is RoHS-compliant.
A BOUT R O HS
In 2003, the European Union issued Directive 2002/95/EC regarding the Restriction of the use of certain Hazardous Substances (RoHS) in electrical and electronic equipment.
The RoHS directive requires producers of electrical and electronic equipment to reduce to acceptable levels the presence of six environmentally sensitive substances: lead, mercury, cadmium, hexavalent chromium, and the presence of polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE) flame retardants, in certain electrical and electronic products sold in the European Union (EU) beginning July 1, 2006.
VersaLogic Corporation is committed to supporting customers with high-quality products and services meeting the European Union’s RoHS directive.
VL-EPM-35 Reference Manual 4
Description
Warnings
E LECTROSTATIC D ISCHARGE
Warning! Electrostatic discharge (ESD) can damage circuit boards, disk drives and other components. The circuit board must only be handled at an ESD workstation. If an approved station is not available, some measure of protection can be provided by wearing a grounded antistatic wrist strap. Keep all plastic away from the board, and do not slide the board over any surface.
After removing the board from its protective wrapper, place the board on a grounded, static-free surface, component side up. Use an antistatic foam pad if available.
The board should also be protected inside a closed metallic anti-static envelope during shipment or storage.
Note: The exterior coating on some metallic antistatic bags is sufficiently conductive to cause excessive battery drain if the bag comes in contact with the battery.
L ITHIUM B ATTERY
Warning! To prevent shorting, premature failure or damage to the lithium battery, do not place the board on a conductive surface such as metal, black conductive foam or the outside surface of a metalized ESD protective pouch. The lithium battery may explode if mistreated. Do not recharge, disassemble or dispose of in fire. Dispose of used batteries promptly and in an environmentally suitable manner.
H ANDLING C ARE
Warning! Care must be taken when handling the board not to touch the exposed circuitry with your fingers. Though it will not damage the circuitry, it is possible that small amounts of oil or perspiration on the skin could have enough conductivity to cause the contents of CMOS RAM to become corrupted through careless handling, resulting in CMOS resetting to factory defaults.
VL-EPM-35 Reference Manual 5
Description
Technical Support
If you are unable to solve a problem after reading this manual please visit the VL-EPM-35
Product Support web page below. The support page provides links to component datasheets, device drivers, and BIOS and FPGA code updates.
VL-EPM-35 Support Page
http://www.versalogic.com/private/leopardsupport.asp
The VersaTech KnowledgeBase also contains a wealth of technical information about VersaLogic products, along with product advisories. Click the link below to see all KnowledgeBase articles related to the VL-EPM-35.
VersaTech KnowledgeBase
If you have further questions, contact VersaLogic Technical Support at (541) 485-8575.
VersaLogic support engineers are also available via e-mail at [email protected]
.
R EPAIR S ERVICE
If your product requires service, you must obtain a Returned Material Authorization (RMA) number by calling (541) 485-8575. Please provide the following information:
Your name, the name of your company, your phone number, and e-mail address
The name of a technician or engineer that can be contacted if any questions arise
Quantity of items being returned
The model and serial number (barcode) of each item
A detailed description of the problem
Steps you have taken to resolve or recreate the problem
The return shipping address
Warranty Repair All parts and labor charges are covered, including return shipping charges for UPS Ground delivery to United States addresses.
Non-warranty Repair All non-warranty repairs are subject to diagnosis and labor charges, parts charges and return shipping fees. Please specify the shipping method you prefer and provide a purchase order number for invoicing the repair.
Note: Please mark the RMA number clearly on the outside of the box before returning.
VL-EPM-35 Reference Manual 6
Configuration and Setup
Initial Configuration
The following components are recommended for a typical development system.
VL-EPM-35 computer
204-pin SO-DIMM (memory module): DDR3-800 or DDR3-1066
ATX power supply
SVGA video monitor
USB keyboard
USB mouse
SATA hard drive
USB CD-ROM drive
The following VersaLogic cables are recommended.
CBR-1201 – Video adapter cable
CBR-3406 – Utility I/O cable and breakout board
CBR-0701 – SATA data cable
CBR-1008 – Power adapter cable
You will also need a Windows (or other OS) installation CD.
Basic Setup
The following steps outline the procedure for setting up a typical development system. The VL-
EPM-35 should be handled at an ESD workstation or while wearing a grounded antistatic wrist strap.
Before you begin, unpack the VL-EPM-35 and accessories. Verify that you received all the items you ordered. Inspect the system visually for any damaged that may have occurred in shipping.
Contact [email protected]
immediately if any items are damaged or missing.
Gather all the peripheral devices you plan to attach to the VL-EPM-35 and their interface and power cables.
It is recommended that you attach standoffs to the board (see Hardware Assembly) to stabilize the
board and make it easier to work with.
Figure 2 shows a typical start-up configuration.
VL-EPM-35 Reference Manual 7
Configuration and Setup
OS Installation
CD-ROM
USB CD-
ROM Drive
USB Keyboard and USB Mouse
CBR-3406
J1 J2
Analog SVGA
CBR-1201
JN11
JN2
VL-EPM-35
LEOPARD
CBR-0701
JN5
SATA
Hard Drive
JN8
CBR-1008 CBR-0401
ATX
Power Supply
Figure 2. Typical Start-up Configuration
1. Install Memory
Insert the DRAM module into SO-DIMM socket JN13 on the bottom of the board and latch it into place.
2. Attach Power
Plug the power adapter cable VL-CBR-1008 into socket JN8. Attach the motherboard connector of the ATX power supply to the adapter.
3. Attach Cables and Peripherals
Plug the video adapter cable VL-CBR-1201 into socket JN11. Attach the video monitor interface cable to the video adapter.
Plug the breakout cable VL-CBR-3406 into socket JN2. (The cable and board are shipped attached.)
Plug a USB keyboard, USB mouse, and USB CD-ROM drive into socket J2 of the breakout board.
Plug the SATA hard drive data cable VL-CBR-0701 into socket JN5 (top or bottom) and attach a hard drive to the cable.
Attach an ATX power cable to the SATA hard drive using the VL-CBR-0401 SATA power adapter cable.
VL-EPM-35 Reference Manual 8
Configuration and Setup
4. Review Configuration
Before you power up the system, double check all the connections. Make sure all cables are oriented correctly and that adequate power will be supplied to the VL-EPM-35 and peripheral devices.
5. Power On
Turn on the ATX power supply and the video monitor. If the system is correctly configured, a video signal should be present.
6. Install Operating System
Install the operating system according to the instructions provided by the OS
manufacturer. (See Operating System Installation.)
Note: If you intend to operate the VL-EPM-35 under Windows XP or Windows XP
Embedded, be sure to use Service Pack 3 (SP3) for full support of the latest hardware features.
CMOS Setup
The default CMOS Setup parameters for the VL-EPM-35S are shown below. The factory default date will correspond to the BIOS build date. Some values may vary depending on the configuration of your VL-EPM-35. See VersaLogic KnowledgeBase article VT1638 – VL-EPM-
35 Leopard CMOS Setup Reference for more information about these parameters and variations for the VL-EPM-35E.
Main Menu
+--------------------------------------------------------+---------------------+
| System Summary |Use TAB to switch |
| -------------------------------------------------------|between month, day |
| Phoenix[R] System BIOS |and year. Use digits|
| VersaLogic Version 6.5.103 |and BKSP to change |
| Core Version EB(SF).005 |field. |
| BIOS Build Date 04/21/11 | |
| System BIOS Size 128KB | |
| CPM/CSPM/BPM Modules P7C7, GM45, EPMp34 | |
| StrongFrame(R) Technology, Firmbase(R) Technology | |
| | |
| Processor (CPU) | |
| Intel(R) Core(TM)2 Duo CPU P9300 @ 2.26GHz | |
| Processor Count 2 | |
| | |
| System Memory (RAM) | |
| Low Memory (KB) 626 | |
| Extended Memory (KB) 2052928 | |
| Memory Above 4GB 0 | |
| | |
| Real Time Clock (RTC) | |
| RTC Date [ 04/21/2011 ] | |
| RTC Time [01:04:15] | |
+--------------------------------------------------------+---------------------+
VL-EPM-35 Reference Manual 9
Configuration and Setup
Exit Menu
+--------------------------------------------------------+---------------------+
| Save, Restore, and Exit Setup |Press ENTER to save |
| -------------------------------------------------------|changes and reboot |
| Save Settings and Restart [ Enter ] |system. |
| | |
| Exit Setup Without Saving Changes [Enter] | |
| | |
| Reload Factory-Defaults and Restart [Enter] | |
| | |
| Reload Custom-Defaults and Restart [Enter] | |
| | |
+ ------------------------------------------------------ + ------------------- +
Boot Menu
+--------------------------------------------------------+---------------------+
| System Boot Configuration |Select initialization|
| -------------------------------------------------------|and boot priority for|
| |all devices. |
| Boot Device Prioritization (BBS) | |
| 0 [ SATA JN5_Top ] |Backspace deletes |
| 1 [SATA JN5_Bot] |selection. Space |
| 2 [None] |bar, + and - change |
| |selections. |
| Initialization Policy [All Devices] | |
| | |
| IDE Drive Configuration | |
| | |
| ICH ATA Controller Configuration | |
| -------------------------------------------------------| |
| SATA Controller [Native Mode] | |
| | |
+ ------------------------------------------------------ + ------------------- +
POST Menu
+--------------------------------------------------------+---------------------+
| POST Memory Tests |Enable basic memory |
| -------------------------------------------------------|confidence test below|
| Low Memory Standard Tes t [ Enabled ] |1MB during POST. |
| Low Memory Exhaustive Test [Disabled] | |
| High Memory Standard Test [Disabled] | |
| High Memory Exhaustive Test [Disabled] | |
| Click During Memory Test [Enabled] | |
| Clear Memory During Test [Disabled] | |
| | |
| POST Error Control | |
| -------------------------------------------------------| |
| | |
| POST User Interface | |
| -------------------------------------------------------| |
| POST Display Messages [Enabled] | |
| POST Operator Prompt [Enabled] | |
| POST Display PCI Devices [Enabled] | |
| | |
| POST Debugging | |
| -------------------------------------------------------| |
| POST Slow Reboot Cycle [Disabled] | |
| POST Fast Reboot Cycle [Disabled] | |
| | |
| Device Initialization | |
| -------------------------------------------------------| |
| POST Floppy Seek [Disabled] | |
| POST Hard Disk Seek [Enabled] | |
+ ------------------------------------------------------ + ------------------- +
VL-EPM-35 Reference Manual 10
Configuration and Setup
SIO Menu
+ ------------------------------------------------------ + ------------------- +
| BIOS Super I/O Configuration | RS-422/485/232-4wire|
| ------------------------------------------------------ | on JN2, CBR-3406. |
| | |
| SMSC LPC47N217 (North board) Devices | |
| -------------------------------------------------------| |
| Serial Port 5 [ Disabled ] | |
| Address [220h] | |
| IRQ [IRQ 5] | |
| Mode [RS-232 (4-wire)] | |
| | |
| SMSC SCH3114 (South board) Devices | |
| -------------------------------------------------------| |
| Serial Port 1 [Enabled] | |
| Address [3f8h] | |
| IRQ [IRQ 4] | |
| Serial Port 2 [Enabled] | |
| Address [2f8h] | |
| IRQ [IRQ 3] | |
| Mode [RS-232 (4-wire)] | |
| Serial Port 3 [Disabled] | |
| Address [3e8h] | |
| IRQ [IRQ 10] | |
| Mode [RS-232 (4-wire)] | |
| Serial Port 4 [Disabled] | |
| Address [2e8h] | |
| IRQ [IRQ 7] | |
| Mode [RS-232 (4-wire)] | |
| Parallel Port [Disabled] | |
| Address [378h] | |
| IRQ [IRQ 7] | |
| DMA [Channel 4] | |
| Mode [Printer] | |
| | |
+ ------------------------------------------------------ + ------------------- +
Features Menu
+ ------------------------------------------------------ + ------------------- +
| BIOS Feature Configuration |Enable to initialize |
| ------------------------------------------------------ |APICs and use them in|
| Interrupt Processing [ Use APIC ] |an emulated PIC mode.|
| MP Tables (non ACPI OSes) [Enabled] |If you wish to use |
| Quick Boot [Enabled] |full-APIC mode, this |
| ACPI [Enabled] |must be set AND |
| POST Memory Manager [Enabled] |either ACPI or MP |
| System Management BIOS [Enabled] |must be enabled. DO |
| Splash Screen [Disabled] |NOT CHANGE AFTER OS |
| |INSTALL. |
| Console Redirection | |
| ------------------------------------------------------ | |
| Use Console Assignments Below [On Remote User Detect] | |
| POST Console [COM1] | |
| | |
| Legacy Free Option | |
| ------------------------------------------------------ | |
| Legacy-Free [Disabled] | |
| ACPI FACP 8042 Flag [Disabled] | |
| | |
| Plug-n-Play (PnP) Configuration | |
| ------------------------------------------------------ | |
| Plug-n-Play [Enabled] | |
| | |
+ ------------------------------------------------------ + ------------------- +
VL-EPM-35 Reference Manual 11
Configuration and Setup
Firmbase Menu
+ ------------------------------------------------------ + ------------------- +
| Features Enabled by Firmbase[R] Technology |Enable to support USB|
| ------------------------------------------------------ |keyboard and mouse |
| Legacy USB [ Enabled ] | |
| USB Boot [Enabled] | |
| EHCI/USB 2.0 [Enabled] | |
| Firmbase User Shell [Enabled] | |
| | |
| Basic Firmbase[R] Technology Configuration | |
| ------------------------------------------------------ | |
| Firmbase Technology [Enabled] | |
| Periodic SMI [Enabled] | |
| Firmbase Debug Log [None] | |
| Firmbase System Console [None] | |
| Firmbase Shell on Serial Port [None] | |
| | |
| Firmbase[R] Technology Foreground IRQ Monitoring | |
| -------------------------- ----------------------------| |
| IRQ0 (Timer) [Disabled] | |
| IRQ1 (Keyboard) [Disabled] | |
| IRQ2 (Cascade) [Disabled] | |
| IRQ3 (COM2/COM4) [Disabled] | |
| IRQ4 (COM1/COM3) [Disabled] | |
| IRQ5 (LPT2) [Disabled] | |
| IRQ6 (Floppy) [Disabled] | |
| IRQ7 (LPT1) [Disabled] | |
| IRQ8 (RTC) [Disabled] | |
| IRQ9 (PCI/SCI) [Disabled] | |
| IRQ10 (PCI) [Disabled] | |
| IRQ11 (PCI) [Disabled] | |
| IRQ12 (Mouse) [Disabled] | |
| IRQ13 (NPX) [Disabled] | |
| IRQ14 (IDE) [Disabled] | |
| IRQ15 (IDE) [Disabled] | |
| | |
+ ------------------------------------------------------ + --------------------+
Misc Menu
+ ------------------------------------------------------ + ------------------- +
| Cache Control |Enable to allow CPU |
| ------------------------------------------------------ |caching to operate. |
| System Cache [ Enabled ] | |
| | |
| Keyboard Control | |
| ------------------------------------------------------ | |
| Keyboard Numlock LED [Disabled] | |
| Typematic Rate [30/sec] | |
| Typematic Delay [250ms] | |
| | |
+ ------------------------------------------------------ + ------------------- +
VL-EPM-35 Reference Manual 12
Configuration and Setup
Board Menu
+ ------------------------------------------------------ + ------------------- +
| Misc Control |Daniels board |
| -------------------------------------------------------|presence override. |
| Daniels Override [ Enabled ] | |
| FPGA base I/O address [0xCA0] | |
| ISA Bus [Enabled] | |
| 82574 Ethernet [Enabled] | |
| | |
| PCI Interrupt Configuration | |
| -------------------------------------------------------| |
| PCI INT A routing [IRQ 11] | |
| PCI INT B routing [IRQ 11] | |
| PCI INT C routing [IRQ 11] | |
| PCI INT D routing [IRQ 9] | |
| PCI INT E routing [IRQ 9] | |
| PCI INT F routing [IRQ 9] | |
| PCI INT G routing [IRQ 9] | |
| PCI INT H routing [IRQ 9] | |
| | |
+ ------------------------------------------------------ + ------------------- +
Video Menu
+--------------------------------------------------------+---------------------+
| |Select video boot |
| Display Device Configuration |display. |
| -------------------------------------------------------|Some modes may |
| Video Boot Display [ CRT ] |require a different |
| LCD Flat Panel Type [1024x768] |Video BIOS support. |
| Panel Fitting [Default] | |
| Video Frame Buffer Size [32MB] | |
| | |
| | |
+--------------------------------------------------------+---------------------+
Chipset Menu
+--------------------------------------------------------+---------------------+
| UHCI #6 Remapping [ Enabled ] |Remap UHCI controller|
| |#6 from Dev1A:Func2 |
| North Bridge Configuration |to Dev1D:Func3. |
| -------------------------------------------------------| |
| Memory Bandwidth Throttling [Enabled] | |
| TM Lock [Disabled] | |
| TS on DIMM [Enabled] | |
| TS on Board [Disabled] | |
| | |
+--------------------------------------------------------+---------------------+
VL-EPM-35 Reference Manual 13
Configuration and Setup
AdvancedCPU Menu
+--------------------------------------------------------+---------------------+
| |Enable |
| CPU Information |Geyserville/Speedste-|
| -------------------------------------------------------|p. |
| CPU Model and Stepping: 1658 | |
| CPU Microcode Version: 2567 | |
| On-Die Thermal Sensor, *C to Overheat: 74 | |
| | |
| CPU Configuration | |
| -------------------------------------------------------| |
| Board is standard temperature | |
| P7 Geyserville/Speedstep [ Enabled ] | |
| SpeedStep Manual Speed (ET) [1200 MHz] | |
| SpeedStep Lock [Enabled] | |
| Dynamic FSB [Enabled] | |
| Intel VT [Disabled] | |
| Microcode Update [Enabled] | |
| C1E [Disabled] | |
| C2E [Enabled] | |
| C4E [Enabled] | |
| Core Multi-Processing [Enabled] | |
| | |
| | |
+--------------------------------------------------------+---------------------+
Note: Due to changes and improvements in the system BIOS, the information on your monitor may differ from that shown above.
Operating System Installation
The standard PC architecture used on the VL-EPM-35 makes the installation and use of most of the standard x86 processor-based operating systems very simple. The operating systems listed on the VersaLogic OS Compatibility Chart use the standard installation procedures provided by the maker of the OS. Special optimized hardware drivers for a particular operating system, or a link to the drivers, are available at the VL-EPM-35 Product Support web page at http://www.versalogic.com/private/leopardsupport.asp
.
VL-EPM-35 Reference Manual 14
Physical Details
Dimensions and Mounting
The VL-EPM-35 complies with all PC/104-Plus standards. Dimensions are given below to help with pre-production planning and layout.
3.575
3.375
3.041
+ +
0.125 DIA x4
Use 3mm or #4 standoffs
3.175
0.471
0.000
-0.200
+ +
0.195
Figure 3. VL-EPM-35 Top Board Dimensions and Mounting Holes (Top View)
(Not to scale. All dimensions in inches.)
VL-EPM-35 Reference Manual 15
3.575
3.375
+
Physical Details
+
3.175
+
0.125
0.000
-0.200
+
Figure 4. VL-EPM-35 Bottom Board Dimensions and Mounting Holes (Top View)
(Not to scale. All dimensions in inches.)
VL-EPM-35 Reference Manual 16
Physical Details
0.67
0.60
0.44
1.28
0.06
Figure 5. VL-EPM-35 Height Dimensions (Side View)
(Not to scale. All dimensions in inches.)
0.06
2.44
VL-EPM-35 Reference Manual 17
Physical Details
1.17
CBR-3406 D IMENSIONS
5.50
5.10
1.57
1.95
1.38
0.06
Figure 6. VL-CBR-3406 Dimensions and Mounting Holes (Top and Side Views)
(Not to scale. All dimensions in inches.)
VL-EPM-35 Reference Manual 18
Physical Details
H ARDWARE A SSEMBLY
The VL-EPM-35 consists of two boards that are mounted together with four 5mm x 15.25mm M3 threaded hex male/female standoffs using the corner mounting holes. These standoffs are secured to the top circuit board using four pan head screws.
Caution: Care must be taken not to damage components near the corner mounting holes when tightening standoffs with nut driver tools.
Additional PC/104-Plus or PC/104 cards can be attached to the bottom of theVL-EPM-35 board set and secured with standoffs or 5mm nuts.
PC/104-Plus expansion modules can be secured directly to the underside of the EPM-32. PC/104 expansion modules can be secured to the underside of the EPM-32; however, the 40-pin and 64pin ISA pass-through connectors may need to be extended, and longer standoffs might need to be used to provide adequate clearance between the PCI connector and the components on the top side of the PC/104 expansion module.
The entire assembly can sit on a table top or be secured to a base plate. When bolting the unit down, make sure to secure all four standoffs to the mounting surface to prevent circuit board flexing. Standoffs and screws are available as part number VL-HDW-105.
An extractor tool is available (part number VL-HDW-203) to separate the PC/104 modules from the stack. Use caution when using the extractor tool not to damage any board components.
VL-EPM-35 Reference Manual
Figure 7. Stack Arrangement Example
19
Physical Details
External Connectors
VL-EPM-35 C ONNECTOR L OCATIONS
JN6
Ethernet
JN7
MiniBlade
JN3
Digital Audio
JN4
SPX
JN2
I/O
JN5
SATA
JN9
LVDS
JN11
SVGA
JN8
Power Input
VN1
JN10
Fan
CPU – Heatsink – Fan
Figure 8. Connector Locations –Top Board (Top View)
VL-EPM-35 Reference Manual 20
Physical Details
JN1
Inter-board
PC-104-Plus (PCI)
JN13
SO-DIMM
JN14
Board-to-Board
Figure 9. Connector Locations – Top Board (Bottom View)
VL-EPM-35 Reference Manual 21
Physical Details
JS1
PC/104-Plus (PCI)
USB SSD
Mounting Hole
JS3
I/O
JS4
Board-to-Board
JS2
USB SSD
JS5
Serial Ports 3-4
JS6
Audio
Row A
Row B
JS8
Power
JS7, JS9
PC/104 (ISA)
Figure 10. Connector Locations – Bottom Board (Top View)
VS1
VL-EPM-35 Reference Manual 22
Physical Details
VL-EPM-35 C ONNECTOR F UNCTIONS AND I NTERFACE C ABLES
Table 1 provides information about the function, mating connectors, and transition cables for VL-
EPM-35 connectors. Page numbers indicate where a detailed pinout or further information is available. JN connectors are located on the north board; JS designators on the south board.
Table 1: Connector Functions and Interface Cables
Connector Function
JN1 Inter-board
PC/104-Plus (PCI)
JN2 Serial Port 5, USB
1-4, LEDs, Reset,
Speaker, Battery
JN3 Digital Audio
JN4
Mating Connector
FCI 89947-334LF
FCI 89361710LF
Transition
Cable
VL-CBR-3406
Cable Description
34-pin latching I/O cable and breakout board
JN5
—
VL-CBR-1402
VL-CBR-0401
—
2mm 14-pin IDC, 2 or 4
SPX device cable
500mm 7-pin, straightto-straight SATA data
ATX to SATA power adapter
JN6
JN8
Ethernet
JN7 MiniBlade
Main Power Input Berg 69176-010 (housing)
+ Berg 47715-000 (pins)
JN9 LVDS
RJ-45 crimp-on plug
(housing), Molex 50641-
8041 (pins)
VL-CBR-1008
VL-CBR-2010, or
VL-CBR-2011, or
VL-CBR-2012
Interface from standard
ATX power supply
18-bit TFT FPD using
20-pin Hirose, or
18-bit TFT FPD using
20-pin JAE, or
24-bit TFT FPD using
20-pin Hirose
JN10
JN11
Fan
Video Output
Molex 22-01-3027 or
Molex 22-01-2025
FCI 89361-712 or
FCI 89947-712
JN13 Memory
—
JS1 PC/104-Plus (PCI) AMP 1375799-1
JS2 USB SSD —
Provided with assembly
VL-CBR-1201
—
—
—
—
1’ 12-pin 2mm latching /
15-pin HD D-Sub VGA
—
—
—
VL-F15 Series eUSB drive
Breakout to standard
PC device connectors
JS3
JS5
JS6
JS7, JS9
JS8
Serial Ports 1-2,
PS/2 keyboard and mouse, LPT, USB
(2), GB Ethernet
3M Robinson-Nugent
P50E-080S-EA
—
Serial Ports 3-4
Audio
PC/104 (ISA)
Power Input
FCI 89947-334LF
FCI 89361710LF
AMP 1375795-2
Berg 69176-010 (housing)
+ Berg 47715-000 (pins)
VL-CBR-8006
—
VL-CBR-1012
VL-CBR-0803
—
VL-CBR-1008
—
12" dual DB9 serial port cable
1’ latching 8-pin 2mm to two 3.5mm stereo audio
—
Interface from standard
ATX power supply
Pin 1 Location
1 x coord. y coord. Page
2.385 2.932
1.550 1.522 —
0.450 3.139
1.550 1.522 —
0.225 -0.050
1. The PCB Origin is the mounting hole to the lower left, as shown in Figure 8.
VL-EPM-35 Reference Manual 23
Physical Details
C ONNECTOR L OCATIONS – VL-CBR-3406
J1
Paddle Board
B1
Battery
SP1
Speaker
J3
Serial Port 5
J2
USB1-4
USB1
D1
SATA LED
(top)
PLED
(bottom)
S1
Reset
USB2
USB3
USB4
= Pin 1
Figure 11. VL-CBR-3406 Connector Locations (Top and Side Views)
CBR-3406 C
ONNECTOR
F
UNCTIONS AND
M
ATING
C
ONNECTORS
Table 2: VL-CBR-3406 Connector Functions and Interface Cables
Connector Function
J1 2mm IDC Connector
J2
J3
USB 1-4
Serial Port 5
B1 Battery
D1 SATA LED / PLED
S1 Reset
SP1 Speaker
FCI 98414-F06-34ULF
4 USB Type A
DB-9 male, Kycon K22X-E9P-N
Dual LED
Pushbutton
Piezo
VL-EPM-35 Reference Manual 24
Physical Details
Jumper Blocks
J UMPERS A S -S HIPPED C ONFIGURATION
VN1
1
3
5
2
4
6
Figure 12. Jumpers As-Shipped – Top Board
VL-EPM-35 Reference Manual 25
VL-EPM-35 Reference Manual
Physical Details
6
VS1
4
2
5
3
1
Figure 13. Jumpers As-Shipped – Bottom Board
26
Physical Details
J UMPER S UMMARY
Table 3: Jumper Summary
Jumper
Block Description
VN1[1-2] System BIOS Selector
In – Backup system BIOS selected
Out – Primary system BIOS selected
The Primary system BIOS is field upgradeable using the BIOS upgrade utility. See http://www.VersaLogic.com/private/wildcatsupport.asp
for more information.
VN1[3-4] Serial Port 5 RS-422 Termination
In – Port terminated with 120 Ohms
Out – No termination
Places terminating resistor across Serial Port 5 RS-422 RX+/RX- differential pair.
VN1[5-6] CMOS RAM and Real-time Clock Erase
In – Erase CMOS RAM and real-time clock
Out – Normal operation
VS1[1-2] Serial Port 2 RS-422 Termination
In – Port terminated with 120 Ohms
Out – No termination
Places terminating resistor across Serial Port 2 RS-422 RX+/RX- differential pair.
VS1[3-4] Serial Port 3 RS-422 Termination
In – Port terminated with 120 Ohms
Out – No termination
Places terminating resistor across Serial Port 3 RS-422 RX+/RX- differential pair.
VS1[5-6] Serial Port 4 RS-422 Termination
In – Port terminated with 120 Ohms
Out – No termination
Places terminating resistor across Serial Port 4 RS-422 RX+/RX- differential pair.
As
Shipped
Out
Page
In
Out
In
In
In
VL-EPM-35 Reference Manual 27
System Features
Power Supply
P OWER C ONNECTORS
Main power is applied to the VL-EPM-35 through a 10-pin connector at either location JN8 (top board) or JS8 (bottom board). The table below shows the pinout for both connectors.
Note: Only one power connector should be used at a time. If both JN8 and JS8 are used at the same time, a ground loop may result.
Warning! To prevent possibly irreparable damage to the system, it is critical that the power connectors are wired correctly. Make sure to use both +5VDC pins and all ground pins to prevent excess voltage drop. Some manufacturers include a pin-1 indicator
on the crimp housing that corresponds to pin-10 of the pinout shown in Figure 14.
Table 4: Main Power Connector Pinout
JN8/JS8
Pin
Signal
Name Description
1 GND Ground
3 GND Ground
5 GND Ground
9 GND Ground
Figure 14 shows the VersaLogic standard pin numbering for this type of 10-pin power connector
and the corresponding mating connector.
JN8/JS8
Some manufacturers include a pin-1 indicator that corresponds to pin-10 of the power connector pinout
2 4
6 8
10
10
8
6
4 2
1 3
5 7
9
9
7
5
3
1
Figure 14. JN8/JS8 and VL-CBR-1008 Pin Numbering
VL-CBR-1008
VL-EPM-35 Reference Manual 28
Physical Details
Note: The +3.3VDC, +12VDC and -12VDC inputs are required only for expansion modules that require these voltages.
P OWER R EQUIREMENTS
The VL-EPM-35 requires only +5 volts (±5%) for proper operation. The voltage required for the
RS-232 ports is generated with an on-board DC/DC converter. A variable low-voltage supply circuit provides power to the CPU and other on-board devices.
The exact power requirement of the VL-EPM-35 depends on several factors, including memory configuration, CPU speed, peripheral connections, type and number of expansion modules and attached devices. For example, driving long RS-232 lines at high speed can increase power demand.
The VL-EPMp-34 is equipped with a voltage sensing reset circuit. The system will reset if voltage drops below 4.63V typically (4.50V min./4.75V max.).
L ITHIUM B ATTERY
A lithium battery is mounted on the bottom board of the VL-EPM-35. The I/O connector at JN2 provides a second battery interface. Installing the VL-CBR-3406 breakout board adds a secondary battery, effectively doubling the battery life of the VL-EPM-35. Both batteries are diode protected, so if one is damaged or drained, the other will not be affected.
Warning! To prevent shorting, premature failure, or damage to the lithium battery, do not place the board on a conductive surface such as metal, black conductive foam, or the outside surface of a metalized ESD protective pouch. The lithium battery may explode if mistreated. Do not recharge, disassemble or dispose of in fire. Dispose of used batteries promptly.
Normal battery voltage should be at least +3V. If the voltage drops below +2V, contact the factory for a replacement (part number HB3/0-1). The life expectancy under normal use is approximately 10 years.
The battery interface uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
CPU
The Intel Core 2 Duo processor combines fast performance, using Intel’s 45nm technology, with advanced power savings features. The SP9300 model used on the VL-EPM-35 has a maximum clock rate of 2.26 GHz and a front side bus speed of 1066 MHz, and features 6 MB of L2 cache.
Other features include DDR3 SDRAM support and an integrated display controller. For more
CPU information see the VL-EPM-35 support page.
VL-EPM-35 Reference Manual 29
Physical Details
System RAM
The VL-EPM-35 has one DDR3 SO-DIMM socket with the following characteristics:
Storage Capacity Up to 4GB
Voltage 1.5V
Type 800 MHz PC3-6400 or 1067 MHz PC3-8500
CMOS RAM
C LEARING CMOS RAM
You can install a jumper at VN1 pins 5-6 for a minimum of three seconds to erase the contents of the CMOS RAM and the real-time clock. When clearing CMOS RAM:
1. Power off the VL-EPM-35.
2. Install a jumper on VN1[5-6] and leave it for three seconds.
3. Remove the jumper.
4. Power on the VL-EPM-35.
CMOS Setup Defaults
The VL-EPM-35 permits users to modify CMOS Setup defaults. This allows the system to boot up with user-defined settings from cleared or corrupted CMOS RAM, battery failure or batteryless operation. All CMOS setup defaults can be changed, except the time and date. CMOS Setup defaults can be updated with the BIOS Update Utility. See the General BIOS Information page for details.
Note: If CMOS Setup default settings make the system unbootable and prevent the user from entering CMOS Setup, the system can be recovered by switching to the
Backup BIOS.
D EFAULT CMOS RAM S ETUP V ALUES
After CMOS RAM is cleared, the system will load default CMOS RAM parameters the next time the board is powered on. The default CMOS RAM setup values will be used in order to boot the system whenever the main CMOS RAM values are blank, or when the system battery is dead or has been removed from the board.
Primary and Backup BIOS
The Primary system BIOS is field upgradeable using the BIOS upgrade utility (see the VL-EPM-
35 Support Page for more information). The Backup BIOS is available if the Primary BIOS becomes corrupted. Jumper VN1[1-2] controls whether the system uses the Primary or Backup
BIOS. By default the Primary BIOS is selected (jumper removed).
VL-EPM-35 Reference Manual 30
Physical Details
Real Time Clock
The VL-EPM-35 features a year 2000-compliant, battery-backed 146818-compatible real-time clock/calendar chip. Under normal battery conditions, the clock maintains accurate timekeeping functions when the board is powered off.
S ETTING THE C LOCK
The CMOS Setup utility (accessed by pressing the Delete key during the early boot cycle) can be used to set the time and date of the real time clock.
Watchdog Timer
A watchdog timer circuit is included on the VL-EPM-35 board to reset the CPU if proper software execution fails or a hardware malfunction occurs.
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire (1000 ms minimum). Writing 5Ah to the WDHOLD register
resets the watchdog timeout period. (See "Special Control Register" and "Watchdog Hold
Fan/Tachometer Monitor
The VL-EPM-35 includes a fan/tachometer indicator circuit that can generate an interrupt if the
CPU fan speed drops below 1 Hz. Bit D0 of the FANTACH register enables or disables the fan interrupt. Bit D7 indicates whether the fan is running at or above 1 Hz or below 1Hz. See
"Fan/Tachometer Control Register" for more information.
F AN /T ACH IRQ C ODE E XAMPLE
#include <stdio.h>
#include <conio.h>
#include <stdlib.h>
#include <graph.h>
#include <dos.h>
//Definitions
#define TRUE 1
#define FALSE 0
#define ESC 27
#define FANREG1 0xC94
#define FANREG2 0xCA4
#define FANIRQEN 0x01
#define SLOWFAN 0x80
//Global Variables volatile int int_hit ;
//Function Prototypes void ( __interrupt __far * old_isr )(); // holds old interrupt handler void __interrupt __far chain_isr ( void );
VL-EPM-35 Reference Manual 31
Physical Details
//Main void main ()
{ char keypressed = 0 ; int irq_count = 0 ;
_clearscreen ( _GCLEARSCREEN );
_settextposition ( 2 , 1 ); printf ( "FANTACH IRQ DEMO -- Stop the spinning fan to perform test...\n" );
_settextposition ( 4 , 1 ); printf ( "Setting new ISR for IRQ 7...\n" ); outp ( 0x20 , 0x20 ); //Clear any pending IRQs old_isr = _dos_getvect ( 0x0F ); //Assign function ptr to old_isr
_dos_setvect ( 0x0F , chain_isr ); //Set new ISR function ptr outp ( 0x21 , inp ( 0x21 ) & 0x7F ); //unmask IRQ 7 in the PIC
//Ensure slow fan status bit is cleared... outp ( FANREG1 , inp ( FANREG1 ) | SLOWFAN ); outp ( FANREG2 , inp ( FANREG2 ) | SLOWFAN );
//Enable Slow/Stalled Fan Interrupt output... outp ( FANREG1 , inp ( FANREG1 ) | FANIRQEN ); outp ( FANREG2 , inp ( FANREG2 ) | FANIRQEN );
_settextposition ( 5 , 1 ); printf ( "Listening for IRQ7...(press ESC to quit)\n" ); while ( keypressed != ESC )
{ if ( kbhit ())
{ keypressed = getch ();
}
//Check for IRQ... if ( int_hit )
{
_settextposition ( 6 , 1 ); irq_count ++; printf ( "%d Slow/Stalled Fan IRQs Detected!\n" , irq_count ); int_hit = FALSE ;
}
}
_settextposition ( 7 , 1 ); printf ( "Original IRQ7 ISR restored...\n\n" );
_dos_setvect ( 0x0F , old_isr ); //restore original ISR
//Turn off Slow/Stalled Fan IRQ output... outp ( FANREG1 , inp ( FANREG1 ) & !
FANIRQEN ); outp ( FANREG2 , inp ( FANREG2 ) & !
FANIRQEN ); exit ( 0 );
} void __interrupt __far chain_isr ( void )
VL-EPM-35 Reference Manual 32
Physical Details
{ int_hit = TRUE ;
//clear slow fan status bit...(this will trigger a new IRQ,
//if the fan is still stalled.) outp ( FANREG1 , inp ( FANREG1 ) | SLOWFAN ); outp ( FANREG2 , inp ( FANREG2 ) | SLOWFAN ); outp ( 0x20 , 0x20 ); //EOI
(* old_isr )(); //call old isr
}
VL-EPM-35 Reference Manual 33
Interfaces and Connectors
34-Pin I/O Connector (JN2)
The JN2 34-pin I/O connector incorporates one serial port, USB ports, LEDs, speaker, and the
reset button. Table 5 illustrates the function of each pin and the pinout assignments to connectors
on the VL-CBR-3406 breakout board.
Table 5: JN2 I/O Connector Pinout
JN2
Pin
3
4
CBR-3406
Connector Signal
1 Serial Port 5 Transmit +
Ground
Receive +
JN2
Pin
18
20
21
CBR-3406
Connector Signal
USB6 Data +
Ground
J2 Bottom USB3 Power
USB7 Data –
USB7 Data +
14
15
16
17
8
9
10
11
6
7 USB0 Ground
3.3V (protected)
Programmable LED
J2 Top USB0 Power
USB0 Data –
25
26
IDE LED 3.3V (protected)
D1 Top IDE LED
12
13
USB1
USB0 Data +
Ground
J2 Middle USB1 Power
Top USB1 Data –
27
29
30
Speaker 3.3V (protected)
Speaker
3.3V (protected)
Reserved
USB2
USB1 Data +
J2 Middle USB2 Power
Bottom USB6 Data –
31
33
34
Battery
Reset
S1
Ground
Ground
System Reset
All user I/O ports on this connector are protected against ESD damage.
VL-EPM-35 Reference Manual 34
Interfaces and Connectors
Serial Ports (JN2, JS3, JS5)
The VL-EPM-35 features five 16550-based serial ports, as described below.
Table 6: VL-EPM-35 Serial Ports
Port Type Connector
Serial Port 1 RS-232,16C550 compatible, all handshake lines implemented
JS3 to VL-CBR-8006
DB-9 (labeled COM1)
Serial Port 2 RS-232/422/485,16C550 compatible,
4-wire RS-232 (only CTS and RTS handshaking), auto direction control
JS3 to VL-CBR-8006
DB-9 (labeled COM2)
Serial Port 3 RS-232/422/485,16C550 compatible,
4-wire RS-232 (only CTS and RTS handshaking), auto direction control
JS5
Serial Port 4 RS-232/422/485,16C550 compatible,
4-wire RS-232 (only CTS and RTS handshaking), auto direction control
JS5
Serial Port 5 RS-232/422/485, 16C550 compatible,
4-wire RS-232 (only CTS and RTS handshaking), manual direction control
JN2 to VL-CBR-3406 J3
DB-9
Serial Port 1 operates in RS-232 mode only with all handshaking lines implemented.
Serial ports 2-5 are 4-wire connections and can operate in RS-232, RS-422, and RS-485 modes, with only CTS and RTS handshaking. For these ports, additional non-standard baud rates are also available (programmable in the normal baud registers) of up to 460K baud.
Serial ports 2-4 operate with automatic direction control. Serial port 5 operates with manual direction control.
Interrupt assignment, I/O address, and mode for serial ports are handled in CMOS Setup. Ports can be enabled or disabled in CMOS setup.
These connectors are protected against ESD damage.
VL-EPM-35 Reference Manual 35
Interfaces and Connectors
S ERIAL P ORT C ONNECTORS
Serial Ports 1 and 2
The interface to Serial Ports 1 and 2 are provided by connector JS3 on the bottom board. (See
"80-Pin I/O Connector (JS3)" for a pinout of connector JS3.) VL-CBR-8006 provides two DB-9
connectors labeled COM1 and COM2. The pinouts of these connectors are shown below.
Table 7: Serial Port 1 Pinout
JS3 Pin RS-232
B21 DCD
VL-CBR-8006
DB-9 COM1 Pin
1
B22 DSR
B23 RXD*
6
2
B24 RTS
B25 TXD*
B26 CTS
B27 DTR
B28 RI
B29 Ground
7
3
8
4
9
5
Table 8: Serial Port 2 Pinout
JS3 Pin RS-232 RS-422 RS-485
VL-CBR-8006
DB-9 COM2 Pin
B31 1
B32 6
2
7
3
8
4
B38 9
5
VL-EPM-35 Reference Manual 36
Interfaces and Connectors
Serial Ports 3 and 4
The interface to Serial Ports 3 and 4 are provided by connector JS5 on the bottom board.
VL-CBR-1012 provides two DB-9 connectors. The pinouts of the JS5 connector and the DB-9 connectors on the VL-CBR-1012 cable are shown below.
Table 9: Serial Port 3 and 4 Pinout
JS5 Serial
Port 3 Pin RS-232 RS-422 RS-485
VL-CBR-1012
1 RXD RxD– RxD–
DB-9 Pin
2
2 CTS RxD+ RxD+
3 TXD TxD– TxD–
8
3
4 RTS TxD+ TxD+
5 Ground Ground Ground
7
5
– 1
– 4
– 6
– 9
JS5 Serial
Port 4 Pin RS-232 RS-422 RS-485
VL-CBR-1012
DB-9 Pin
6 Ground Ground Ground
7 RXD RxD– RxD–
8 CTS RxD+ RxD+
9 TXD TxD– TxD–
5
2
8
3
10 RTS TxD+ TxD+ 7
– 1
– 4
– 6
– 9
VL-EPM-35 Reference Manual 37
Interfaces and Connectors
Serial Port 5
The interface to Serial Port 5 is provided by connector JN2 on the top board. (See "34-Pin I/O
Connector (JN2)" for a pinout of the JN2 connector.) VL-CBR-3406 provides a DB-9 connector
at J3. The pinout of this connector is shown below.
Table 10: Serial Port 5 Pinout
JN2 Pin RS-232 RS-422 RS-485
VL-CBR-3406
DB-9 (J3) Pin
3 Ground Ground Ground
7
3
4*
8
6 Ground Ground Ground
2
5
– 1
– 6
– 9
* Pin 4 of CBR-3406 connector J3 is not connected.
COM P ORT C ONFIGURATION
Jumper block VN1[3-4] sets the serial port 5 termination of the RS-422 differential pairs. Jumper
block VS1 sets the termination for serial ports 2-4. See the Jumper Summary on page 27 for
details on termination configuration.
RS-485 M ODE L INE D RIVER C ONTROL
The TxD+/TxD– differential line driver can be turned on and off by manipulating the RS-485/422
Transmit/Receive Control Register. Refer to page 58 for more information. Serial ports 2-4 can
be configured with CMOS Setup to operate with automatic direction control.
USB Interface (JN2, JS3)
The USB interface on the VL-EPM-35 is UHCI (Universal Host Controller Interface) and EHCI
(Enhance Host Controller Interface) compatible, which provides a common industry software/hardware interface.
Connector JN2 includes interfaces for four USB ports. There are four Type A USB connectors on the VL-CBR-3406 breakout board.
Connector JS3 includes interfaces for two USB ports. There are two Type A USB connectors on the VL-CBR-8006 breakout cable.
These connectors are protect against ESD damage.
BIOS C
ONFIGURATION
The USB channels use a number of PCI interrupts (see “Interrupt Configuration”). CMOS Setup
is used to select the IRQ line routed to each PCI interrupt line.
VL-EPM-35 Reference Manual 38
Interfaces and Connectors
Programmable LED (JN2, JS3)
Connectors JN2 and JS3 include a output signals for a software controlled LED. For connector
JN2, connect the cathode of the LED to JN2 pin 24; connect the anode to +3.3V. An on-board
200 ohm resistor limits the current. A programmable LED is provided on the VL-CBR-3406 breakout board and on the VL-CBR-8006 cable.
These connectors are protect against ESD damage.
To turn the LED on and off, set or clear bit D7 in I/O port CA0h. When changing the register, make sure not to alter the value of the other bits.
The following code examples show how to turn the LED on and off. See page 55 for more
information:
LED On LED Off
Note: The LED is turned on by the BIOS during system startup. This causes the light to function as a "power on" indicator if it is not otherwise controlled by user code.
HD LED (JN2, JS3)
Connectors JN2 and JS3 include output signals for a SATA activity LED. For JN2, connect the cathode of the LED to JN2 pin 26, and connect the anode to +5V. An on-board 200 Ohm resistor limits the current. A SATA LED is provided on the VL-CBR-3406 board and the VL-CBR-8006 cable. These interfaces are protected against ESD damage.
Internal Speaker (JN2, JS3)
Connectors JN2 and JS3 include speaker output signals. The VL-CBR-3406 breakout board and
VL-CBR-8006 each provide a Piezo electric speaker. These interfaces are protected against ESD damage.
Pushbutton Reset (JN2, JS3)
Connectors JN2 and JS3 include inputs for a pushbutton reset switch. Shorting JN2 pin 34 to ground causes the VL-EPM-35 to reboot. These interfaces are protected against ESD damage.
Audio (JN3, JS6)
D IGITAL A UDIO (JN3)
The digital audio interface on the VL-EPMp-34 allows you to connect an external audio codec to the system. Contact VersaLogic Sales for available external codecs. This interface is protected against ESD damage.
Table 11: JN3 Audio Connector
VL-EPM-35 Reference Manual 39
Interfaces and Connectors
JN3
Pin Signal Name Function
2 Ground Ground
4 Ground Ground
5 HDA_SDIN_0 Line
6 Ground Ground
A UDIO L INE I N /O UT (JS6)
8 V3_3
9 HDA_RST_0# Reset
10 V3_3
Connector JS6 provides an audio interface using the IDT 92HD75B Audio Codec. Drivers are available for most Windows-based operating systems (see the VL-EPM-35 support page ). The interface provides the line-level stereo input and line-level stereo output connection points. The outputs will drive any standard-powered PC speaker set. This interface is protected against ESD damage.
Table 12: JS6 Audio Connector Pinout
JS6 Pin
Signal
Name Function
2 Ground Ground
4 Ground Ground
6 Ground Ground
8 Ground Ground
VL-EPM-35 Reference Manual 40
Interfaces and Connectors
SPX™ Expansion Bus (JN4)
Up to four serial peripheral expansion (SPX) devices can be attached to the VL-EPM-35 at connector JN4 using the VL-CBR-1401 or VL-CBR-1402 cable. The SPX interface provides the standard serial peripheral interface (SPI) signals: SCLK, MISO, and MOSI, as well as four chip selects, SS0# to SS3#, and an interrupt input, SINT#.
The 5.0V power provided to pins 1 and 14 of JN4 is protected by a 1 Amp fuse.
Table 13: SPX Expansion Bus Pinout
JN4
Pin
Signal
Name Function
1 V5_0 +5.0V
2 SCLK Serial
3 GND Ground
4 MISO Serial Data In
8
9
10
5 GND Ground
6 MOSI Serial Data Out
7 GND Ground
SS0#
SS1#
SS2#
Chip Select 0
Chip Select 1
Chip Select 2
11 SS3#
12 GND
Chip Select 3
Ground
13 SINT# Interrupt
14 V5_0
SPI is, in its simplest form, a three wire serial bus. One signal is a Clock, driven only by the permanent Master device on-board. The others are Data In and Data Out with respect to the
Master. The SPX implementation adds additional features, such as chip selects and an interrupt input to the Master. The Master device initiates all SPI transactions. A slave device responds when its Chip Select is asserted and it receives Clock pulses from the Master.
The SPI clock rate can be software configured to operate at speeds between 1 MHz and 8 MHz.
Please note that since this clock is divided from a 33 MHz PCI clock, the actual generated frequencies are not discrete integer MHz frequencies. All four common SPI modes are supported through the use of clock polarity and clock idle state controls.
V ERSA L OGIC SPX E XPANSION M ODULES
VersaLogic offers a number of SPX modules that provide a variety of standard functions, such as analog input, digital I/O, CANbus controller, and others. These are small boards (1.2” x 3.775”) that can mount on the PC/104 stack, using standard PC/104 stand-offs, or up to two feet away from the base board. For more information, contact VersaLogic at
[email protected]
.
VL-EPM-35 Reference Manual 41
Interfaces and Connectors
SPI R EGISTERS
A set of control and data registers are available for SPI transactions. The following tables describe the SPI control registers (SPICONTROL and SPISTATUS) and data registers
(SPIDATA3-0).
SPICONTROL (READ/WRITE) CA8h (or C98h)
D7 D6 D5 D4 D3 D2 D1 D0
CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0
Table 14: SPI Control Register 1 Bit Assignments
0 = SCLK idles low
1 = SCLK idles high
0 = Data read on rising edge
1 = Data read on falling edge
D5-D4 SPILEN SPI Frame Length – Sets the SPI frame length. This selection works in manual and auto slave select modes.
SPILEN1 SPILEN0 Frame Length
0
0
1
1
0
1
0
1
8-bit
16-bit
24-bit
32-bit lines are controlled through the user software or are automatically controlled by a write operation to SPIDATA3 (CADh). If MAN_SS = 0, then the slave select operates automatically; if MAN_SS = 1, then the slave select line is controlled manually through SPICONTROL bits SS2, SS1, and SS0.
0 = Automatic, default
1 = Manual
D2-D0 SS SPI Slave Select – These bits select which slave select will be asserted. The
SSx# pin on the base board will be directly controlled by these bits when
MAN_SS = 1.
SS2 SS1 SS0 Slave Select
0
0
0
0
1
1
1
0
1
SPX Slave Select 0, JN4 pin-8
SPX Slave Select 1, JN4 pin-9
SPX Slave Select 2, JN4 pin-10
1 0 0 SPX Slave Select 3, JN4 pin-11
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
VL-EPM-35 Reference Manual 42
Interfaces and Connectors
SPISTATUS (READ/WRITE) CA9h (or C99h)
D7 D6 D5 D4 D3 D2 D1 D0
HW_INT BUSY
Table 15: SPI Control Register 2 Bit assignments
Bit Mnemonic Description
D7-D6 IRQSEL IRQ Select – These bits select which IRQ will be asserted when a hardware interrupt from a connected SPI device occurs. The HW_IRQ_EN bit must be set to enable SPI IRQ functionality.
IRQSEL1 IRQSEL0 IRQ
0
0
1
1
0
1
0
1
IRQ3
IRQ4
IRQ5
IRQ10
D5-D4 SPICLK SPI SCLK Frequency – These bits set the SPI clock frequency.
SPICLK1 SPICLK0 Frequency
0
0
1
1
0
1
0
1
(IRQSEL) by an SPI device.
0 = SPI IRQ disabled, default
1 = SPI IRQ enabled
Note: The selected IRQ is shared with PC/104 ISA bus devices. CMOS settings must be configured for the desired ISA IRQ.
The direction can be shifted toward the least significant bit or the most significant bit.
0 = SPIDATA data is left-shifted (MSbit first), default
1 = SPIDATA data is right-shifted (LSbit first) hardware SPX signal SINT# is asserted.
0 = Hardware interrupt on SINT# is deasserted
1 = Interrupt is present on SINT#
This bit is read-only and is cleared when the SPI device’s interrupt is cleared. transaction is underway.
0 = SPI bus idle
1 = SCLK is clocking data in and out of the SPIDATA registers
This bit is read-only.
VL-EPM-35 Reference Manual 43
Interfaces and Connectors
SPIDATA0 (READ/WRITE) CAAh (or C9Ah)
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA1 (READ/WRITE) CABh (or C9Bh)
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA2 (READ/WRITE) CACh (or C9Ch)
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA3 (READ/WRITE) CADh (or C90h)
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this register will initiate the SPI clock and, if the MAN_SS bit = 0, will also assert a slave select to begin an SPI bus transaction. Increasing frame sizes from 8-bit use the lowest address for the least significant byte of the SPI data word; for example, the LSB of a 24-bit frame would be
SPIDATA1. Data is sent according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSbit of SPIDATA3 is sent first, and received data will be shifted into the LSbit of the selected frame size set in the SPILEN field. When LSBIT_1ST = 1, the LSbit of the selected frame size is sent first, and the received data will be shifted into the MSbit of SPIDATA3.
Data returning from the SPI target will normally have its most significant data in the SPIDATA3 register. An exception will occur when LSBIT_1ST = 1 to indicate a right-shift transaction. In this case the most significant byte of an 8-bit transaction will be located in SPIDATA0, a 16-bit transaction’s most significant byte will be located in SPIDATA1, and a 24-bit transaction’s most significant byte will be located in SPIDATA2.
VL-EPM-35 Reference Manual 44
Interfaces and Connectors
SATA Ports (JN5)
The VL-EPM-35 provides two serial ATA (SATA) ports, which communicate at a rate of up to
3.0 gigabits per second. The SATA connectors at location JN5 are standard 7-pin straight SATA friction latching connectors.
Power to SATA drives is supplied by the ATX power supply. Note that the standard SATA drive power connector is different than the common 4-pin Molex connector used on IDE drives. Most current ATX power supplies provide SATA connectors, and many SATA drives provide both types of power connectors. If the power supply you are using does not provide SATA connectors, adapters are available.
Table 16: SATA Port Pinout (JN5)
JN5 Pin
Bottom
JN5 Pin
1 8 Ground
2 9 +
4 11 Ground
6 13 +
7 14 Ground
Ethernet Interface (JN6, JS3)
The VL-EPM-35 features two on-board gigabit Ethernet controllers, an Intel 82574IT and an
Intel 82541ER. Both controllers provide a standard IEEE 802.3 Ethernet interface for 1000Base-
T, 100Base-TX, and 10Base-T applications. The RJ-45 connector JN6 on the top board is controlled by the 82574IT. Connector JS3 on the bottom board is controlled by the 82541ER. The
VL-CBR-8006 breakout cable includes an RJ-45 connector.
These interfaces are protected against ESD damage.
While these controllers are not NE2000-compatible, it is widely supported. Drivers are readily available to support a variety of operating systems. See VersaLogic website for latest OS support.
BIOS C ONFIGURATION
Both Ethernet controllers use PCI interrupt INTA#. Use CMOS Setup to select the IRQ line routed to each PCI interrupt line.
VL-EPM-35 Reference Manual 45
Interfaces and Connectors
E THERNET S TATUS LED S
The JN6 RJ-45 connector has two built-in LEDs to provide an indication of the Ethernet status as shown in the following table.
Table 17: JN6 Ethernet Status LEDs
Green/Orange
(Link Speed)
Yellow (Activity)
Orange
Green
Off
On
Off
1 Gbps speed
100 Mbps speed
10 Mbps speed or cable not plugged into active hub
Activity detected on cable
(intermittent with activity)
No activity detected on cable
On-board LEDs provide an indication of the JS3 Ethernet interfaces, as shown below.
Table 18: JS3 Ethernet Status LEDs
Green
Yellow
On
Off
On
Off
Active Ethernet cable plugged in
Active cable not plugged in or cable not plugged into active hub
Activity detected on cable
(intermittent with activity)
No activity detected on cable
Solid State Drives (JN7, JS2)
M INI B LADE (JN7)
A vertical MiniBlade socket is provided at position JN7 for solid state storage. The MiniBlade interface on the VL-EPM-35 supports only USB devices. The VL-F23 series of MiniBlade devices are available from VersaLogic in sizes of 1 GB, 2 GB, and 4 GB. Contact VersaLogic
Sales to order.
E USB S OLID S TATE D RIVE (JS2)
Connector JS2 on the bottom board provides an interface for an eUSB solid state drive (SSD).
The VersaLogic VL-F15 series of eUSB SSDs come in sizes of 2 GB and 4 GB, as well as standard and extended temperature ratings. Contact VersaLogic Sales for information. eUSB modules are secured to the board using the VL-HDW-109 hardware kit from VersaLogic. The kit contains one M2.5 x 6mm round aluminum standoff and two M2.5 x 4mm pan head Philips screws.
VL-EPM-35 Reference Manual 46
Interfaces and Connectors
Video Interface (JN9, JN11)
An on-board video controller integrated into the chipset provides high performance video output
for the VL-EPM-35. The VL-EPM-35 can also be operated without video attached. See “Console
C ONFIGURATION
The VL-EPM-35 uses a shared-memory architecture. It supports two types of video output,
SVGA and LVDS Flat Panel Display.
SVGA O
UTPUT
C
ONNECTOR
(JN11)
See the Connector Location Diagram on page 20 for connector location information. An adapter
cable, part number VL-CBR-1201, is available to translate JN11 into a standard 15-pin D-Sub
SVGA connector.
This connector is protected against ESD damage.
Table 19: Video Output Pinout
JN11
Pin
Signal
Name Function
1 GND
2 CRED
3 GND
4 CGRN
5 GND
6 CBLU
Ground
Ground
Ground
7 GND Ground
8 CHSYNC Horizontal
9 GND Ground
10 CVSYNC Vertical Sync
11 DDC_CLK DDC Clock Signal
12 DDC_DATA DDC Data Control
Mini DB15
Pin
5
13
10
14
15
12
6
1
7
2
8
3
LVDS F LAT P ANEL D ISPLAY C ONNECTOR (JN9)
The integrated LVDS Flat Panel Display in the VL-EPM-35 is an ANSI/TIA/EIA-644-1995 specification-compliant interface. It can support up to 24 bits of RGB pixel data plus 3 bits of timing control (HSYNC/VSYNC/DE) on the 4 differential data output pairs.
The 3.3V power provided to pins 19 and 20 of JN9 is protected by a 1 Amp fuse.
See the Connector Location Diagram on page 20 for connector location information.
VL-EPM-35 Reference Manual 47
Interfaces and Connectors
Table 20: LVDS Flat Panel Display Pinout
JN9
Pin Signal Name Function
1 GND
2 NC
3 LVDSA3
4
5 GND
6
LVDSA3#
LVDSCLK0
Ground
Diff. Data 3 (+)
Diff. Data 3 (–)
Ground
Differential Clock (+)
7 LVDSCLK0# Differential Clock (–)
8 GND Ground
9 LVDSA2 Diff. Data 2 (+)
10 LVDSA2#
11 GND
12 LVDSA1
13 LVDSA1#
14 GND
15 LVDSA0
16 LVDSA0#
17 GND
18 GND
19 +3.3V
20 +3.3V
Diff. Data 2 (–)
Ground
Diff. Data 1 (+)
Diff. Data 1 (–)
Ground
Diff. Data 0 (+)
Diff. Data 0 (–)
Ground
Ground
Protected Power Supply
Protected Power Supply
C OMPATIBLE LVDS P ANEL D ISPLAYS
The following list of flat panel displays is reported to work properly with the integrated graphics video controller chip used on the VL-EPM-35.
Table 21: Compatible Flat Panel Displays
Manufacture
Model
Number
Panel
Size eVision Displays xxx084S01 series 8.4” au Optronix B084SN01 8.4” eVision Displays xxx104S01 series 10.4” au Optronix B104SN01 10.4”
Resolution
800 x 600 18-bit
800 x 600 18-bit
800 x 600 18-bit
800 x 600 18-bit eVision Displays* xxx141X01 series 14.1” 1024 x 768 18-bit
Interface
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Panel
Technology
TFT
TFT
TFT
TFT
TFT
TFT
VL-EPM-35 Reference Manual 48
Interfaces and Connectors
C ONSOLE R EDIRECTION
The VL-EPM-35 can be operated without using the on-board video output by redirecting the console to a serial communications port. CMOS Setup and some operating systems such as DOS can use this console for user interaction.
Console redirection settings are configured on the Features tab of CMOS Setup. The default setting (On Remote User Detect) causes the console not to be redirected to the serial port unless a signal (a Ctrl-C character) is detected from the terminal. Console redirection can also be set to
Always or Never. Notes on console redirection:
When console redirection is enabled, you can access CMOS Setup by typing Ctrl-C.
The decision to redirect the console is made early in BIOS execution, and cannot be changed later.
The redirected console uses 115200 baud, 8 data bits, 1 stop bit, no parity, and no flow control.
Null Modem
The following diagram illustrates a typical DB9 to DB9 RS-232 null modem adapter.
System 1 <--> System 2
Name Pin Name
------------------------------------
CTS 8
Pins 7 and 8 are shorted together on each connector. Unlisted pins have no connection.
Expansion Bus (JS1, JS7/JS9)
PC/104-P LUS – PCI (JS1)
PC/104-Plus modules can be secured directly to the bottom of the VL-EPM-35. The bottom board of the VL-EPM-35 set consumes the first slot position on the PC/104-Plus stack. Make sure to correctly configure the slot position jumpers on each PC/104-Plus module appropriately.
The VL-EPM-35 is compliant with revision 2.3 of the PC/104-Plus specification and can support three bus master capable PC/104-Plus modules.
The BIOS automatically allocates I/O and memory resources. CMOS Setup may be used to select
IRQ assignment.
VL-EPM-35 Reference Manual 49
Interfaces and Connectors
PC/104 – ISA (JS7/JS9)
The VL-EPM-35 provides full support of the PC/104 (ISA) bus, including support of 16-bit I/O and memory transfers. PC/014 modules can be added to the stack below the VL-EPM-35. Most
PC/104 cards will work, but be sure to check the requirements of your PC/104 card against the limitations listed below.
Available I/O Ranges
The following I/O ranges are available on the ISA bus:
0x200 – 0x2FF (except 0x208 – 0x20F and any on-board devices assigned in CMOS
Setup to the 0x200 – 0x2FF range; see note below)
0x300 – 0x37F
0x400 – 0x47F
0x600 – 0xBFF
Note: By default, Serial Port 2 is assigned to 0x2F8 – 0x2FF in CMOS Setup, but the base address for this device can be moved outside the 0x200 – 0x2FF range. See
KnowledgeBase article VT1638 for information on serial port settings in CMOS
Setup.
Available Memory Ranges
The following memory range is available on the ISA bus:
D000:0h – DFFF:Fh
DMA and Bus Master Support
The VL-EPM-35 does not support PC/104 DMA or bus mastering.
80-Pin I/O Connector (JS3)
Connector JS3 provides interfaces for the following VL-EPM-35 ports:
Parallel port
Serial ports 1-2
PS/2 (keyboard and mouse)
USB (two devices)
Ethernet
The connector also provides interfaces to a programmable LED, IDE LED, reset button, and
external speaker. Table 22 shows the pinout for the cable assembly.
To connect devices to any of these ports, connect the 80-pin connector of the VL-CBR-8006 transition cable to connector JS3 on the VL-EPM-35, then plug the devices into the appropriate connector on the breakout cable.
Note: Optionally, you can manufacture a cable based on the pinout information provided for each interface.
VL-EPM-35 Reference Manual 50
All user I/O ports on this connector are protected against ESD damage.
Interfaces and Connectors
VL-EPM-35 Reference Manual 51
Interfaces and Connectors
Table 22: 80-Pin I/O Connector Pinout
JS3
Pin
A1
A5
External
Connector
LPT1
A3 DB-25F
Signal
JS3
Pin
External
Connector Signal
Strobe +5V (Protected)*
Data bit 1
B2 Channel 0 Data +
B3 JD Channel 0 Data -
Printer
Data bit 2 B5 .1" Male Cable Shield
A7
A8
Data bit 3
Select input
A9 Data bit 4
A10 Ground
A11 Data bit 5
B7
B8
B9
Ground
Channel 1 Data -
Channel 1 Data +
A12
A13
Ground
Data bit 6
A14 Ground
A15
A16
Data bit 7
Ground
A17
A18
Data bit 8
Ground
B11 ETHERNET Bi-directional pair +C
B12
B13
B15
B16
B17
B18
JE
8-pin
Jack
Bi-directional pair -C
Bi-directional pair -B
Bi-directional pair +D
Bi-directional pair -D
Bi-directional pair -A
Bi-directional pair +A
A19 Acknowledge PBRESET Pushbutton Reset
A20 Ground B20 Ground
B21 Data Carrier Detect
A22
A23
Ground
Paper End
A24 Ground
A25 Select
A26
A27
MISC No Connect
Programmable LED +
B22
B23
B24
B26
B27
JF
DB-9M
Data Set Ready
Receive Data
Request to Send
Clear to Send
Data Terminal Ready
B29 Ground
B30
A31
A32 IDE Data LED +
A33
A34
MOUSE
JB
+5V (Protected)
Mouse Data
A35 6-pin Ground
A36 Mini-DIN Mouse Clock
B31 No Connect
B32 JG No Connect
B33
B34
DB-9M Receive Data
Request to Send
B35 Transmit
B36 Clear to Send
A37
A38
KBD
JC
+5V (Protected)
Keyboard Data
A39 6-pin Ground
A40 Mini-DIN Keyboard Clock
B37
B38
Ground
No Connect
B39 Ground
B40 No Connect
* The 5V power supplied to pins on this connector is protected by current limiting circuitry.
VL-EPM-35 Reference Manual 52
Interrupt Configuration
The VL-EPM-35 has the standard complement of PC type interrupts. Up to six IRQ lines can be allocated as needed to PCI devices. There are no interrupt configuration jumpers. All configuration is handled through CMOS Setup.
Table 23: VL-EPM-35 IRQ Settings
Timer 0
Keyboard
Slave PIC
Serial Port 1
Serial Port 2
Serial Port 3
Serial Port 4
Serial Port 5
Parallel Port
RTC
Mouse
Math Chip
Primary IDE
Secondary IDE
LPT1
SPX
Fan Tachometer
PCI INTA#
PCI INTB#
PCI INTC#
PCI INTD#
PCI INTE#
PCI INTF# z = default setting | = allowed setting
Source z z z
| z | z | {
| | |
| | |
| | |
|
| | |
|
|
|
|
|
|
IRQ
{
|
|
|
|
|
|
|
| | z
| | z
| | z z | | z | | z | | z z z z z z
VL-EPM-35 Reference Manual 53
System Resources and Maps
Table 24: PCI Interrupt Settings z = default setting | = allowed setting
Source
82541ER Ethernet
PCI Interrupt
INTA# INTB# INTC# INTD# INTE# INTF# z
82574IT Ethernet z
Audio z
SATA z
USB EHCI 1 z
USB EHCI 2 z
USB UHCI 1 z
USB UHCI 2 z
USB UHCI 3 z
USB UHCI 4 z
USB UHCI 5 z
USB UHCI 6 z
Video z
VL-EPM-35 Reference Manual 54
Special Registers
Product Code Register
PRODCODE (Read/Write) CA0h (or C90h)
D7 D6 D5
PLED PC6 PC5
D4
PC4
D3
PC3
D2
PC2
D1
PC1
D0
PC0
Table 25: Product Code Register Bit Assignments
Bit Mnemonic Description
JS3.
0 = Turns LED on
1 = Turns LED off
D6-D0 PC Product Code — These bits are hard-coded to represent the product type. The VL-
EPMp-34 always reads as 0000001. Other codes are reserved for future products.
PC6 PC5 PC4 PC3 PC2 PC1 PC0
0 0 0 0 0 0 1 VL-EPMp-34
VL-EPM-35
These bits are read-only.
VL-EPM-35 Reference Manual 55
Special Registers
Revision Level Register
REVLEV (Read Only) CA1h (or C91h)
D7 D6 D5 D4 D3 D2 D1 D0
Table 26: Revision Level Register Bit Assignments
Bit Mnemonic Description
D7-D3 RL FPGA Revision Level — These bits are hard-coded to represent the FPGA revision. Contact VersaLogic Support for further information.
These bits are read-only.
0 = Standard temperature range
1 = Extended temperature range
This bit is read-only.
0 = Standard
1 = Custom
This bit is read-only.
0 = Standard
1 = Beta
This bit is read-only.
VL-EPM-35 Reference Manual 56
Special Registers
Special Control Register
SCR (Read/Write) CA2h (or C92h)
D7 D6 D5 D4 D3 D2 D1 D0
BIOS_JMP BIOS_OR BIOS_SEL CMOD1 CMOD0 WDOG_STAT
Table 27: Special Control Register Bit Assignments
Bit Mnemonic Description
BIOS selector jumper at VN1[1-2].
0 = Jumper installed – backup system BIOS selected
1 = No jumper installed – primary system BIOS selected
This bit is read-only. selects the BIOS with BIOS_SEL.
0 = No BIOS override
1 = BIOS override
0 = Backup BIOS selected
1 = Primary BIOS selected
D4-D3 CMOD Serial Port 5 Mode — Sets the operation mode of Serial Port 5.
CMOD1 CMOD0 Serial Port 5 Mode
0
0
0
1
RS-232
RS-422
1
1
0
1
RS-485
Reserved
D0 Reserved
0 = Timer has not expired.
1 = Timer has expired.
This bit is read-only. circuit.
0 = Disables
1 = Enables
This bit has no function.
VL-EPM-35 Reference Manual 57
Special Registers
Watchdog Hold Register
WDHOLD (Write Only) CA3h (or C93h)
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 0 1 0
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire (1000 ms minimum). Writing 5Ah to WDHOLD resets the watchdog timeout period.
Fan/Tachometer Control Register
FANTACH (Read/Write) CA4h (or C94h)
D7 D6 D5 D4 D3 D2 D1 D0
SLOWFAN Reserved Reserved Reserved Reserved Reserved Reserved FANINT
Table 28: Fan/Tachometer Control Register Bit Assignments
Bit Mnemonic Description
D6-D1 Reserved
0 = Fan is running at or above 1 Hz.
1 = Fan is running below 1 Hz.
This bit is read-only.
These bits have no function.
0 = Disables fan interrupt
1 = Enables fan interrupt – IRQ7
VL-EPM-35 Reference Manual 58
CPU
Intel Core 2 Duo
Chipset
Intel GS45
Intel ICH9
Ethernet Controller
Intel 82574IT Ethernet Controller
Intel 82541ER Ethernet Controller
Super I/O Chip
SMSC LPC47N217
SMSC SCH3114
PC/104-Plus Interface
General PC Documentation
The Programmer’s PC Sourcebook
General PC Documentation
The Undocumented PC
Appendix A – References
Intel Core 2 Duo Datasheet
Intel GS45 Datasheet
Intel ICH9 Datasheet
Intel 82574IT Datasheet
Intel 82541ER Datasheet
LPCC47N217 Datasheet
SCH3114 Datasheet
PC/104-Plus Specification
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VL-EPM-35 Reference Manual 59

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