Efficient Watt-Level Power Amplifiers in Deeply

Efficient Watt-Level Power Amplifiers in Deeply
Efficient Watt-Level Power Amplifiers in
Deeply Scaled CMOS
Submitted in partial fulfillment of the requirements
for the degree of Doctor of Philosophy
in
Department of Electrical and Computer Engineering
Wei Tai
B.S., Electrical Engineering, National Taiwan University
Carnegie Mellon University
Pittsburgh, PA
May, 2011
To my parents, Hua and Chin
iv
Abstract
Advances in silicon processing technology have made CMOS power amplifiers a
feasible option for wireless communication applications. Compared to the compoundsemiconductor counterparts, CMOS PAs become increasingly attractive due to their
lower cost and higher level of integration. The continued scaling of CMOS technology further extends the cut-off frequency of CMOS devices up to several hundred
GHz, which makes the realization of high performance millimeter-wave CMOS PA
a possibility. On the other hand, due to the low breakdown voltage of scaled CMOS
and the lossy silicon substrate, the requirement to simultaneously achieve high output power, high linearity, and a wide power control range makes it very challenging
for conventional PAs to maintain good efficiency, especially at back-off power levels.
The first focus of this thesis is the implementation of an outphasing PA with
dynamic power control (DPC), which addresses the efficiency-linearity trade-off,
especially at power back-off. With DPC, segments of the PA are turned on or off
dynamically according to the instantaneous power level. This technique has been
experimentally demonstrated with a 2.4 GHz fully-integrated watt-level outphasing
class-D PA in 45 nm CMOS. With DPC, average PAE is improved from 12% to 16%
at 24.8 dBm average output power, and from 5% to 12% at 20.5 dBm output power.
The second focus addresses the design of high performance PAs in the millimeterwave regime. Various PA and combiner topologies are explored to optimize output
power and efficiency. Specifically, a 45 GHz 2-stage class-B PA in SiGe BiCMOS is
implemented which achieved 26% peak PAE at 16.6 dBm CW output power. In addition, a transmission line based zero-degree power combiner topology is proposed
and analyzed. Using this combiner, a 45 GHz 16-way combined cascoded classE PA is designed in a 45 nm SOI CMOS process. Simulation results indicate the
feasibility of achieving watt-level output power with high PAE with the proposed
topology.
vi
Acknowledgments
I would like to thank many people who have made the completion of my Ph.D
work possible. First and foremost, I would like to thank my co-advisors, Professor Rick Carley and Professor David Ricketts. Professor Carley has been extremely
supportive and he helped me find my passion in RF circuit design in my early Ph.D
years. He encouraged and supported me to build knowledge and experience from a
variety of sources, including the industry, and this had helped me greatly. Professor
Ricketts has been one of my biggest support and source of guidance. Without him I
wouldn’t have been able to finish my Ph.D work timely.
My thank also goes to the faculty members at CMU and other institutions who
helped me in one way or another during my Ph.D work. Professor Tamal Mukherjee
had been on my qualification exam committee, and he had given me great support
in accessing process resources. Professor Joel Dawson and Professor Vladimir Stojanovic at MIT has continually given me useful feedback on my work and has been
very supportive. I also thank Professor Jeyanandh Paramesh and Dr. Hasnain Lakdawala for being on my thesis committee and providing insightful suggestions on
my work. Professor Donhee Ham and Dr. William Andress at Harvard had helped
me with laser passivation removal in their lab. Dr. Hingloi Hung, Edward Viveiros
and Joe Qiu at the Army Research Lab had also supported me with their load pull
measurement system. Without these kind people my experiments would not have
been able to continue. I am especially thankful for the help from Dr. Hongtao Xu
at Intel Corporation. I won’t forget the time we spent together in the lab debugging
circuits, and the joy of seeing a clean spectrum measurement at 4am. I would also
like to thank Hongtao and also Dr. Chang-Tsung Fu for sharing their apartments
with me during my internship and making the experience enjoyable and memorable.
It was also a great pleasure to work under the lead of Dr. Yorgos Palaskas at Intel,
who gave me constant feedback, support, and encouragement.
I would like to acknowledge the support from Intel Corporation, the Defense Advanced Research Projects Agency (DARPA) ELASTx program, and the US Army
Research Lab under award number W911NF-10-1-0088.
I am grateful for the support from other students and friends at CMU. My friend
Cheng-Yuan Wen has always been supportive from day one at CMU. Chongzhe Li
worked on power combiner design, simulation, and fabrication, and was crucial to
my Ph.D work. I would also like to thank my lab mates: Zhenning Wang, Erkan
Alpman, Michael Chen, David Tian, Yingying Tang and Emre Karagozler, for all
the joy, tears, and laughter we had together.
Finally, I thank my parents, Hua and Chin, for inspiring and nurturing me as I
grow up, and my lovely wife, Li-Wen, for always being caring and supportive.
Contents
1
2
3
4
Introduction
1.1 PA Efficiency with Large PAPR Signals . . . . . . .
1.2 Deeply-Scaled CMOS: Opportunities and Challenges
1.3 Contributions . . . . . . . . . . . . . . . . . . . . .
1.4 Thesis Organization . . . . . . . . . . . . . . . . . .
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1
2
4
6
7
Basic Power Amplifier Topologies
2.1 Classic Power Amplifiers . . . .
2.2 Switch Mode Power Amplifiers .
2.2.1 Class-D . . . . . . . . .
2.2.2 Class-E . . . . . . . . .
2.2.3 Class-F . . . . . . . . .
2.3 Outphasing Amplifier . . . . . .
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2.4GHz PA with Dynamic Power Control
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Proposed PA Topology and Dynamic Power Control . . . . . . . . .
3.2.1 Class-D Outphasing PA . . . . . . . . . . . . . . . . . . .
3.2.2 Power Control With a Multi-section Transformer Combiner
3.2.3 Dynamic Power Control . . . . . . . . . . . . . . . . . . .
3.3 Design and Implementation . . . . . . . . . . . . . . . . . . . . . .
3.3.1 PA Topology . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Unit PA . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Transformer Combiner . . . . . . . . . . . . . . . . . . . .
3.3.4 Supply and Ground Network . . . . . . . . . . . . . . . . .
3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Delay Line Configuration . . . . . . . . . . . . . . . . . .
3.4.3 Continuous Wave Test . . . . . . . . . . . . . . . . . . . .
3.4.4 Modulated Signal Test . . . . . . . . . . . . . . . . . . . .
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A Millimeter-wave Power Amplifier in SiGe
51
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Comparison of Power Amplifier Topologies . . . . . . . . . . . . . . . . . . . . 52
viii
4.3
4.4
4.5
5
6
7
Power Amplifier Design . . . . . . . . . . . . . . . . . . . .
4.3.1 PA Stability . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 PA Cell Layout . . . . . . . . . . . . . . . . . . . . .
4.3.3 Passive Devices and Matching Networks . . . . . . .
Experimental Results . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Large Signal Measurement with 2.5V Supply . . . . .
4.4.2 Back-off Efficiency Enhancement with Scaled Supply
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Millimeter-wave 16-way Power Amplifier in SiGe
5.1 Introduction . . . . . . . . . . . . . . . . . . . .
5.2 16-Way Zero-Degree Power Combiner . . . . . .
5.3 Circuit Implementation . . . . . . . . . . . . . .
5.4 Simulation Results . . . . . . . . . . . . . . . .
5.5 Measurement Results . . . . . . . . . . . . . . .
5.6 Summary . . . . . . . . . . . . . . . . . . . . .
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A Millimeter-wave 16-way Power Amplifier in SOI CMOS
6.1 Class-E PA in Millimeter-wave Frequency . . . . . . . .
6.2 The Cascode Class-E PA . . . . . . . . . . . . . . . . .
6.2.1 Transistor Switching Loss . . . . . . . . . . . .
6.2.2 Parasitic Capacitor Charging Loss . . . . . . . .
6.2.3 Driver Loss . . . . . . . . . . . . . . . . . . . .
6.2.4 Passive Device Loss . . . . . . . . . . . . . . .
6.3 Circuit Implementation . . . . . . . . . . . . . . . . . .
6.3.1 Power Amplifier Output Stage . . . . . . . . . .
6.3.2 Driver Chain and Input Power Splitter . . . . . .
6.3.3 Output Power Combiner . . . . . . . . . . . . .
6.4 Simulation Results . . . . . . . . . . . . . . . . . . . .
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusions
7.1 Contributions . . . . . . . . . .
7.2 Future Research . . . . . . . . .
7.2.1 Dynamic Power Control
7.2.2 Millimeter-wave PAs . .
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110
ix
List of Figures
1.1
Illustration of PA efficiency degradation due to large signal PAPR. . . . . . . . .
3
1.2
Transmitter system using compound semiconductor PA vs. a CMOS SoC. . . . .
4
2.1
A simplified power amplifier schematic. . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Drain current and voltage waveforms of a class-A PA. . . . . . . . . . . . . . . . 11
2.3
Drain current and voltage waveforms of a class-B PA. . . . . . . . . . . . . . . . 13
2.4
Efficiency, Id0 and Id1 vs. θ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5
Normalized optimum load resistance and PN versus θ. . . . . . . . . . . . . . . 15
2.6
A simplified schematic of a class-D PA, and the voltage and current waveforms. . 17
2.7
A simplified schematic of a class-E PA, and the voltage and current waveforms. . 18
2.8
A simplified schematic of a class-F PA, and the voltage and current waveforms. . 20
2.9
Illustration of the outphasing technique. . . . . . . . . . . . . . . . . . . . . . . 21
2.10 Two combiner topologies for outphasing PAs. . . . . . . . . . . . . . . . . . . . 22
2.11 Outphasing PA performance comparison. . . . . . . . . . . . . . . . . . . . . . 23
3.1
Class-D outphasing system with a transformer combiner. . . . . . . . . . . . . . 27
3.2
Calculated PAE versus normalized output power. . . . . . . . . . . . . . . . . . 28
3.3
The multi-section transformer combiner topology for discrete power control. . . . 29
3.4
Calculated PAE and power consumption of a multi-section outphasing PA. . . . . 31
3.5
Illustration of the DPC scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6
Simulated average PAE with 64-QAM WiFi signal. . . . . . . . . . . . . . . . . 33
3.7
Outphasing angle versus normalized output power with DPC. . . . . . . . . . . . 34
x
3.8
Simplified PA supply network, showing source of DPC-induced supply ringing. . 35
3.9
Illustration of the “skip window” concept. . . . . . . . . . . . . . . . . . . . . . 36
3.10 ACPR and PAE versus skip window length. . . . . . . . . . . . . . . . . . . . . 37
3.11 Average PAE versus output power with skip window applied. . . . . . . . . . . . 37
3.12 Proposed transformer-combined outphasing PA topology and chip micrograph. . 39
3.13 Simplified schematics of (a) unit PA cell, and (b) low power unit PA cell. . . . . . 40
3.14 Photograph of the PA evaluation board. . . . . . . . . . . . . . . . . . . . . . . 42
3.15 Simulated output spectrum with 64-QAM WiFi under DPC. . . . . . . . . . . . 43
3.16 Block diagram of the modulated signal measurement setup. . . . . . . . . . . . . 44
3.17 Measured CW output power and PAE. . . . . . . . . . . . . . . . . . . . . . . . 46
3.18 Measured power consumption, and CW characteristics vs. frequency . . . . . . . 46
3.19 Ideal and measured PAE vs. average output power under WiFi signal at 2.4 GHz.
47
3.20 Measured output spectra and constellations of the PA under WiFi and WiMAX. . 48
4.1
Performance comparison among SiGe PAs of different classes. . . . . . . . . . . 52
4.2
Circuit diagram of the 2-stage class-B PA. . . . . . . . . . . . . . . . . . . . . . 53
4.3
Simulated stability factor and the simplified schematics of the base network. . . . 54
4.4
Top and 45-degree view of the unit transistor layout. . . . . . . . . . . . . . . . 55
4.5
Top and 45-degree view of the PA output stage layout. . . . . . . . . . . . . . . 56
4.6
3-D model of the implemented slab inductor and the spiral inductor. . . . . . . . 57
4.7
Die micrograph of the class-B PA. . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.8
Simulated load pull contours of the driver- and output-stage. . . . . . . . . . . . 58
4.9
Small signal and large signal measurement setup. . . . . . . . . . . . . . . . . . 59
4.10 Measured small signal and large signal characteristics at 45 GHz. . . . . . . . . . 60
4.11 Measured power consumption vs. input power, and PAE vs. output power. . . . . 60
4.12 Output power versus continuous operation time. . . . . . . . . . . . . . . . . . . 62
5.1
An 8-way corporate combiner and an 8-way zero-degree combiner. . . . . . . . . 65
xi
5.2
Realizable input impedances of an 8-way zero-degree combiner. . . . . . . . . . 67
5.3
Insertion loss versus Γin of an 8-way zero-degree combiner. . . . . . . . . . . . . 70
5.4
Insertion loss versus Γin of an 8-way corporate combiner. . . . . . . . . . . . . . 70
5.5
The implemented 16-way zero-degree combiner. . . . . . . . . . . . . . . . . . . 71
5.6
Schematic of unit PA of the 16-way SiGe PA. . . . . . . . . . . . . . . . . . . . 72
5.7
Schematic of pre-driver of the 16-way SiGe PA. . . . . . . . . . . . . . . . . . . 73
5.8
Die micrograph of the 16-way SiGe PA. . . . . . . . . . . . . . . . . . . . . . . 74
5.9
Simulated CW characteristics of the 16-way SiGe PA at 45 GHz. . . . . . . . . . 74
5.10 Simulated CW characteristics vs. supply voltage and frequency. . . . . . . . . . 75
5.11 Measurement setup of the 16-way SiGe PA. . . . . . . . . . . . . . . . . . . . . 76
6.1
GM AX vs. bias voltage of SiGe HBT and SOI CMOS devices. . . . . . . . . . . 80
6.2
Theoretical class-E efficiency versus frequency of different technology nodes. . . 81
6.3
Performance comparison of class-B and class-E PAs in 45nm SOI CMOS. . . . . 82
6.4
Voltage waveforms of a regular class-E PA versus a cascode class-E PA. . . . . . 83
6.5
Simplified schematics of a cascode class-E PA. . . . . . . . . . . . . . . . . . . 84
6.6
Simplified CMOS switch model. . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.7
Capacitive charging mechanism of the cascode intermediate node. . . . . . . . . 86
6.8
Impedance looking into the cascode intermediate node. . . . . . . . . . . . . . . 87
6.9
Total transistor power loss normalized to peak output power. . . . . . . . . . . . 88
6.10 Normalized power loss vs. α at different frequencies. . . . . . . . . . . . . . . . 90
6.11 Choke inductor power loss versus nc . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.12 Block diagram of the proposed 45 GHz 16-way class-E outphasing PA. . . . . . 92
6.13 Schematic diagram of the cascode class-E PA output stage. . . . . . . . . . . . . 93
6.14 Top and side view of the unit transistor finger metal wiring. . . . . . . . . . . . . 95
6.15 Top and close-up view of the transistor layout. . . . . . . . . . . . . . . . . . . . 95
6.16 Schematic diagram of the unit PA driver chain. . . . . . . . . . . . . . . . . . . 96
xii
6.17 Schematic diagram of the input power splitter. . . . . . . . . . . . . . . . . . . . 97
6.18 Layout of the 16-way zero-degree combiner and assembly cross-section. . . . . . 98
6.19 Layout of the 16-way power amplifier. . . . . . . . . . . . . . . . . . . . . . . . 100
6.20 Simulated CW characteristics vs. VDD and frequency. . . . . . . . . . . . . . . 101
6.21 Simulated PAE and power consumption under VDD scaling. . . . . . . . . . . . 102
6.22 Simulated AM-AM and AM-PM nonlinearity. . . . . . . . . . . . . . . . . . . . 102
6.23 Results of Monte Carlo simulations with and without Riso . . . . . . . . . . . . . 103
7.1
PAE improvement through transistor and driver resizing. . . . . . . . . . . . . . 108
xiii
List of Tables
3.1
Power control configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2
Performance comparison of watt level CMOS PAs in the cellular band. . . . . . . 50
4.1
Performance comparison for fully-integrated SiGe HBT power amplifiers. . . . . 63
5.1
Comparison of the simulation and measurement results of the 16-way SiGe PA. . 77
5.2
Performance comparison for fully-integrated SiGe HBT power amplifiers. . . . . 78
6.1
Simulated port isolation of the 8-way zero-degree combiner . . . . . . . . . . . . 99
6.2
Summary of the simulated performance of the 16-way combined PA. . . . . . . . 104
xiv
Chapter 1
Introduction
Radio frequency (RF) Power amplifiers (PAs) are ubiquitous in the everyday life, as they are
a key enabling component of the various communications, imaging, and radar applications. In
particular, devices that combine personal computing and communication capabilities have seen
a surge in popularity during the 2000’s with remarkable market growth. These devices are typically capable of multiple high data-rate radio standards in the cellular band that provide the
user with unprecedented wireless connectivity. In fact, each radio standard within such device
would generally require a PA for signal power amplification, and these PAs are often required
to simultaneously achieve high output power (typically over 1 W), high linearity, and a wide
power control range. These stringent requirements make it very challenging for conventional
PAs to maintain good power efficiency, especially at back-off power levels. As the power consumption of the multiple PAs often take up a considerable percentage of the device’s total power
consumption, poor power efficiency of the PAs would lead to a reduced battery life and the need
to increase battery capacity at the expense of weight and form-factor. Radio applications in the
millimeter-wave regime that promise multi-Gb/s data-rate are also on the verge of commercialization with prospects of wide adoption. However, the aforementioned trade-off between PA
linearity and efficiency is further exacerbated as frequency increases, since PA device gain and
efficiency often suffers at high frequencies.
On the other hand, the continued scaling of CMOS processing technology offers new opportunities in PA design. The raw speed of the CMOS transistors, as quantified by the cutoff frequency of the device, continues to increase as processes with smaller feature sizes are introduced
1
to the market. The faster-switching transistors generate sharper voltage transitions, which helps
to reduce power consumption and enhance efficiency. The increase in high frequency power gain
also leads to a reduced number of amplifier stages required and hence potentially improving the
overall efficiency. A second important feature that is strengthened by CMOS scaling is the lowcost signal processing capability which can be leveraged to enhance RF performance. CMOS
technology, despite these favorable features, still has limitations such as low device breakdown
voltage and a lossy conductive substrate. Our goal is to design and implement high performance
RF and millimeter-wave PAs by exploiting the advantages of scaled CMOS, while circumventing
the shortcomings through prudent circuit design techniques and optimization.
1.1 PA Efficiency with Large PAPR Signals
The trade-off between PA efficiency and linearity is one of the most challenging obstacles in
optimizing the performance of a transmitter system. This is especially true with radio systems
that utilize complex multi-carrier modulation schemes such as the ones that are popular in today’s high data-rate applications. Orthogonal frequency domain multiplexing, or OFDM, is one
example of a modulation scheme that enjoys widespread adoption in radio standards such as
WLAN (IEEE 802.11), WiMAX (IEEE 802.16), LTE (3GPP Long Term Evolution), as well as
terrestrial digital video broadcasting. OFDM transmits data by subdividing the available channel
bandwidth into smaller, closely spaced subchannels, each containing a subcarrier signal that is
orthogonal to one another and with a much lower symbol rate [1, 2]. As a result, OFDM is very
resilient against inter-symbol interference and multipath fading. OFDM also has a very high
spectral efficiency, which makes it commercially attractive.
However, one of the major drawbacks of OFDM is the high peak-to-average power ratio
(PAPR) of its modulated signal envelop. If the phases of multiple OFDM subcarriers align, the
instantaneous output power can be significantly higher than the average OFDM signal power.
This effect can have a very negative impact on system power efficiency, as shown in Fig. 1.1. On
the left side of the figure, the power-added efficiency (PAE) characteristics of a typical CMOS
2
Watt-level CMOS PA performance in literature
70
Probability Density Function of
OFDM modulated signal
Fully-integ. & packaged
Off-chip match / probed
60
PAE (%)
40
PAE (%)
30
50
40
30
20
20
29
10
30
31
32
33
Peak Output Power (dBm)
34
20
16
PAE (%)
0
−30
−20
−10
0
Output Power Back−off (dB)
12
8
4
0
19
20
21
22
23
24
Output Power at 10dB Back-off (dBm)
Figure 1.1: PAE vs. output power of watt-level CMOS PAs in the literature at peak output power and
10-dB back-off. The large PAPR of the modulated signal causes average PAE of conventional PAs to
degrade dramatically.
PA (blue curve) is overlaid on top of the probability density distribution of a 20 MHz bandwidth,
64-QAM OFDM signal power profile (shaded area), which has a PAPR of approximately 10
dB. To illustrate the efficiency degradation from peak output power to a 10 dB back-off, the
PAE of several state-of-the-art watt-level CMOS PAs from the literature [3–10] are compared
on the right side of Fig. 1.1. While PAE at peak output power can be fairly good (30-40% for
fully-integrated CMOS PAs that are packaged, and 45-60% for those not packaged when tested),
it drops to below 14% at a power back-off of 10 dB. One way to mitigate the problem is to
reduce the signal PAPR by baseband signal processing, e.g. the peak power signal level can be
3
“clipped” to reduce PAPR at the expense of bit error rate [11]. However, the gain in efficiency is
limited, and a circuit-level method to achieving higher back-off efficiency is clearly needed. The
investigation of PA topologies that address the issue of PAE degradation at large back-off is one
of the main focuses of this thesis, which is discussed in more detail in Chapter 3.
1.2 Deeply-Scaled CMOS: Opportunities and Challenges
High performance RF and millimeter-wave power amplifiers have traditionally been dominated
by compound semiconductor implementations, such as with GaAs, GaN, SiC, and InP devices,
due to the high cutoff frequency and power capability of these devices (e.g. an InP device with an
ft of 400 GHz and an fmax of over 1 THz has been reported [12]). Even in the cost-competitive
consumer device market, compound semiconductor PAs are still widely employed for their performance advantage. However, the performance of CMOS transistors is improving at a much
quicker pace compared to compound semiconductors, since the market size and demand for
CMOS digital IC products provide a much higher drive for scaling. For example, it is predicted
that the 20 nm CMOS node will provide fmax in the range of 400 GHz [13].
In addition to the improvement in raw performance, the potential of cost-saving with CMOS
implementation is particularly attractive for mass-market applications. As shown in Fig. 1.2, the
PA module in a cellular phone typically consists of a compound semiconductor PA IC, a bias and
control IC, and several discrete passive components. If the PA is fully-integrated in CMOS, it can
Compound
Semiconductor PA
CMOS
Bias/Control
+
Switch to
CMOS PA
CMOS
Baseband
and DSP
Fully Integrated
CMOS
System-on-Chip
External Passives
Figure 1.2: CMOS implementation of power amplifiers offers the possibility of system-on-chip integration, which reduces the number of discrete components required and hence cost as compared to adopting
compound semiconductor PAs.
4
then potentially be combined with the baseband IC in a system-on-chip (SoC) format. Product
cost can be lowered due to a significantly reduced number of discrete components and the simplified wire-bonding and packaging requirements. Despite the availability of higher performance
SiGe and GaAs PAs in discrete packages, great interest is recently directed at achieving full integration of watt-level PAs in CMOS in the cellular band [6, 8–10, 14–19]. For similar reasons,
research on CMOS PAs operating in the millimeter-wave band have also gathered momentum
[20–27].
Despite the potential of RF and millimeter-wave PAs implemented in deeply scaled CMOS,
their development is faced with additional challenges. One of the main obstacles is the low
break down voltage of the CMOS devices. The implication of a lower breakdown voltage, and
hence a proportionally lower supply voltage, is as follows. As the maximum swing across the
PA device is reduced due to a lower supply voltage, the load impedance presented to the device
needs to be quadratically smaller to support a proportionally larger current in order to maintain
output power. The lower load impedance mandates the use of a matching network with larger
transformation ratio, which typically exhibits higher insertion loss, degrading output power and
efficiency. Furthermore, the increase in device current would require a larger device periphery.
At high frequencies, the parasitics of such a large device would greatly reduce the gain of the
device, necessitating the use of multiple smaller transistors and a power combiner. The loss of
the combiner would again degrade overall efficiency. As a result, one often needs to resort to
innovative new circuit topologies to optimize the performance of a CMOS PA with low break
down voltage.
Another disadvantage of CMOS processes lies in the poor quality factor of on-chip passive
devices. Unlike the compound semiconductor counterparts, the substrate of silicon-based technologies is typically quite conductive. On-chip passive devices such as inductors and transmission lines, if not shielded properly, would have stray electric field lines extending into the silicon
substrate, causing eddy current losses. Even with the employment of a patterned ground shield,
the substrate loss cannot be entirely eliminated, and the extra parasitic capacitance would also
5
reduce the self resonance frequency of the inductor. As inductors implemented on a compound
semiconductor chip typically have Q > 20, a Q of 5-10 for on-chip inductors over a silicon substrate is within expectations [13]. A direct result of the lower quality factor is an increased loss
in the matching networks, combiners, and biasing chokes.
Furthermore, it is possible that a deeply scaled CMOS device with a seemingly high maximum frequency of oscillation (fmax ) may not work as well as expected in reality. To understand
the reasoning behind this observation, note that fmax of a device can be expressed as [28]
fT
,
fmax = p
2 (Ri + Rs + Rg )g0 + 2πfT Rg Cgd
(1.1)
where Ri is the intrinsic channel resistance, Rs is the series resistance in the source and drain
contacts to the channel, Rg is the gate resistance, g0 is the output conductance, and Cgd is the
gate-source parasitic capacitance. fmax is a function of the total resistance in the signal path,
which depends strongly on layout geometry such as transistor finger width, and the exact layout
of metal layers/vias used in the terminal feed lines. These parasitic components are not predicted
by the intrinsic device models, thus careful layout extraction and even EM simulations would be
required to predict the RF performance of the device.
In summary, the low-cost and high level of integration offered by CMOS PAs are only relevant if the aforementioned issues are addressed. To achieve this, new circuit topologies as well
as design methodologies may be required, which make the design effort challenging.
1.3 Contributions
There are two main contributions of this thesis. First, we propose and experimentally demonstrate the dynamic power control (DPC) scheme which enhances PA back-off efficiency. Specifically, DPC reduces DC power consumption of the PA at back-off power levels by dynamically
turning on or off segments of the PA according to the instantaneous power level. The issue of
supply ringing caused by the DPC scheme is identified and analyzed, and a strategy to mitigate
6
this effect is proposed. A 2.4 GHz watt-level outphasing class-D PA prototype in 45-nm CMOS
is implemented to demonstrate DPC as well as ringing mitigation [19].
The second contribution of the thesis is the design of efficient, watt-level PAs in the millimeterwave regime. We provide an analysis of SiGe HBT PA efficiency optimization, based on which
a 45 GHz two-stage class-B SiGe PA is designed and measured [29]. In addition, the two-stage
class-B SiGe PA is used as building blocks in a 16-way power combined PA, which utilizes a
low-loss zero-degree power combiner. Finally, we present the design and analysis of a wattlevel millimeter-wave PA in 45-nm SOI CMOS. The PA utilizes cascode class-E stages and a
16-way zero-degree combiner. The results indicate the feasibility of efficient, watt-level power
generation in millimeter-wave frequencies.
1.4 Thesis Organization
The thesis is organized as follows. To facilitate the discussion of PA efficiency optimization, a
background review will be provided in Chapter 2. Fundamental power amplifier topologies will
be discussed, including the various reduced-conduction mode and switch mode PAs. Strategies
to reach the condition for 100% efficiency will be discussed, as well as realistic considerations
and trade-offs. Then, the outphasing technique is introduced. We will explain the basic principles
of outphasing, and then discuss the issues that affect back-off efficiency when implementing an
outphasing system.
In Chapter 3, we will introduce the dynamic power control concept, its issues of supply
ringing and (Adjacent Channel Power Ratio) ACPR degradation, and we will propose a solution
to mitigate the ringing and to optimize performance. The design of the 2.4 GHz watt-level
outphasing class-D PA that implements the dynamic power control scheme is presented, along
with measurement results which confirm the intended efficiency enhancement at back-off power
levels.
Chapter 4 begins with a discussion of millimeter-wave SiGe PA efficiency optimization, followed by the design and measurement results of a two-stage class-B SiGe PA which achieves
7
state-of-the-art performance, including a peak PAE of 26% and a saturated output power of 17.5
dBm at 45 GHz.
The 16-way combined version of the 45 GHz class-B SiGe PA is presented in Chapter 5, as
well as an analysis of the low-loss zero-degree power combiner used in the design. Measurement
data of the 16-way SiGe PA is also presented.
Then, a watt-level millimeter-wave PA in 45-nm SOI CMOS is shown in Chapter 6 with a
thorough analysis of the various loss mechanisms of the PA. The 16-way CMOS PA is extensively
simulated, and results showed promise in the realization of watt-level millimeter-wave PAs.
The thesis is concluded in Chapter 7, which summarizes the key contributions and proposes
possible directions for future research.
8
Chapter 2
Basic Power Amplifier Topologies
The primary function of a power amplifier is to deliver RF power to a load with as low loss as
possible. In order to reduce loss and improve PA efficiency, a wide array of topology variations
have been developed over the years. In this chapter, we will review some of the basic power
amplifier topologies, and analyze the trade-offs involved.
In principle, the various PA topologies differ in two main aspects: the input driving condition,
and the load impedance presented to the PA transistor as a function of frequency. These two sets
of variables determine the current and voltage waveforms at the output of the transistor, and the
load network transfers some or all of the signal power into the load. Trade-offs among efficiency,
linearity, gain, output power, and reliability are involved. The basic understanding and intuition
established in this chapter will facilitate the further discussions that follow.
2.1 Classic Power Amplifiers
Stripped down to the bare bones, a classic power amplifier consists of only a few components:
the transistor, an RF choke inductor, a load impedance matching network, and the load. This is
illustrated in the simplified schematic as shown in Fig. 2.1. We define the PA efficiency as
η=
Pout
Pout
=
,
PDC
Pout + Pdiss
(2.1)
where Pout is the RF signal power delivered to the output load, PDC is the total power consumption, and Pdiss is the total power dissipated as waste heat. A PA with 100% efficiency would
9
VDD
PDC
Pout
Matching
Network
Pdiss
Zin = Z opt at ω0
Rload
vin
Figure 2.1: A simplified power amplifier schematic.
direct all of the power coming from the power supply to the load, i.e. no power is dissipated in
the transistor. This would require that there are zero “overlap” between the voltage and current
R
waveforms at the drain node (i.e. Id Vd dt = 0). In theory, this is an achievable condition if all
elements are ideal.
Let us begin the analysis with a simpler case: the linearized PA model, with the following
assumptions. We assume that the NMOS transistor has a simple piece-wise linear current-voltage
characteristics. The choke inductor connected to the drain of the transistor is assumed to be very
large, forcing the current drawn from the supply voltage to contain only a DC component. The
load of the PA, Rload , has a value of 50 Ω, while the load impedance matching network transforms
Rload into Zopt - the optimal load impedance for the transistor. The matching network is usually
implemented as a combination of passive components with a finite quality factor. For the sake
of simplicity, we assume that the matching network is lossless, and it presents Zopt to the device
only at the operation frequency ω0 , and it rejects signals at all other frequencies. Furthermore,
Zopt is assumed to contain only a real part of Ropt .
Based on these assumptions, the current and voltage waveforms at the drain node of the
10
Vd
t
V
Vin
VDD
Id
ωt
Id
I
Iq
VTH
VB
0
Vg
π
2π ωt
Figure 2.2: Drain current and voltage waveforms of a class-A PA.
transistor can be plotted as shown in Fig. 2.2. Here, the input voltage is expressed as
vin = VB + Vin cos (ω0 t),
(2.2)
whereas the current and voltage waveforms at the drain are
Id = Iq + I cos (ω0 t),
(2.3)
Vd = VDD − Ropt Id = VDD − V cos (ω0 t).
(2.4)
Note that at the drain of the transistor, since the impedance at ω0 is Ropt , the voltage and current
swings, V and I, at the same frequency must satisfy V /I = Ropt .
We assume that the input voltage magnitude, Vin , never exceeds VB . In other words, the
transistor is always on. This topology and bias condition is classified as a class-A PA. To calculate
11
efficiency, note that the DC power consumption is simply VDD Iq , and the output power is V ·I/2.
Using (2.1), we have
ηclass−A =
V I
V I/2
= 0.5
.
VDD Iq
VDD Iq
(2.5)
When the input voltage swing is on the verge of saturating the device, we obtain V = VDD and
I = Iq , hence
ηclass−A |peak = 50%.
(2.6)
This result is obtained with the simplifying assumption of a piece-wise linear device with zero
saturation voltage (i.e. V |max = VDD ). Intuitively, the “overlap” between Id and Vd , as quanR
tified by Id Vd dt, represents the power dissipated by the conducting transistor. To minimize
power dissipation, one would suggest that by increasing the value of I, the “overlap” could po-
tentially be reduced. This can be achieved by reducing the gate bias voltage VB , and the resulting
waveforms are shown in Fig. 2.3.
Now that the gate bias is reduced, there are periods of time when the transistor is turned off.
We can express the drain current analytically as
Id =



Iq + I cos (ωt),


0.
−θ ≤ ωt < θ
(2.7)
θ ≤ ωt < 2π − θ
where the “conduction angle,” 2θ, represents the period within each RF cycle when the transistor conducts current. Since we have assumed that the matching network rejects all frequency
components other than ω0 , Vd is still sinusoidal. On the other hand, Id now consists of multiple
harmonic components and it can be represented a Fourier-series expansion. In order to calculate
efficiency, we need both the DC and fundamental components of Id , which can be found as
Id0 = Iγ0 ,
γ0 =
1
(sin θ − θ cos θ),
π
12
(2.8)
Class-AB
Class-B
Class-C
Vd
t
V
VDD
Vin
Id
ωt
Id
Iq
VTH
0
Vg
θ
π
2π ωt
Figure 2.3: Drain current and voltage waveforms of a class-B PA.
Id1 = Iγ1 ,
γ1 =
1
(θ − sin θ cos θ).
π
(2.9)
We are now in a position to calculate the PA efficiency in terms of θ.
η(θ) =
Iγ1 V /2
1 sin θ − θ cos θ
.
=
Iγ0 VDD
2 θ − sin θ cos θ
(2.10)
Figure 2.4 shows the PA efficiency versus θ. The DC and fundamental components of the
drain current are also normalized and plotted against θ. Starting from the right side of the plot
with θ = 180◦ , we have the class-A condition as described previously. As θ decreases, we obtain
the following operation conditions:
• θ = 90◦ , i.e. the transistor conducts current for exactly half of each signal period, a
maximum efficiency of 78.5% is obtainable. This condition is referred to as the class-B PA,
in which the gate bias VB equals the threshold voltage of the transistor. The corresponding
13
Id1
Efficiency (%)
90
0.8
Id0
80
0.6
78.5%
70
0.4
60
0.2
50
0
0
30
60
90
120
150
Normalized Current Amplitude
1
100
180
θ (Degrees)
Figure 2.4: PA efficiency, and the amplitude of DC and fundamental components of Id versus θ.
voltage and current waveforms of a class-B PA are shown colored red in Fig. 2.3.
• 180◦ > θ > 90◦ . This is known as the class-AB PA, as exemplified by the blue dashed
waveforms in Fig. 2.3. The transistor conducts current between 50% and 100% of the time,
while efficiency is somewhere between that of a class-A and a class-B PA.
• 90◦ > θ > 0◦ . When the transistor conducts for less than 50% of a signal period, then the
PA is biased as a class-C PA. This condition is exemplified by the green dashed waveforms
in Fig. 2.3. The theoretical efficiency of the class-C PA approaches 100% as θ shrinks
towards zero.
One useful figure of merit that indicates the relative stress of the PA device is the normalized power output capability, PN , defined as the ratio of the output power to the product of the
maximum device voltage and current [30]
PN =
Pout
.
VD,max ID,max
14
(2.11)
0.16
0.14
0.12
0.08
PN
0.1
0.06
0.04
0.02
0
0
30
60
90
120
150
180
θ (Degrees)
Figure 2.5: Normalized optimum load resistance and PN versus θ.
VD,max is the maximum drain-source voltage across the transistor, which is 2VDD . ID,max is
the maximum drain current. To find ID,max , we observe that the drain current waveform can be
seen as the positive region of a sinusoid with amplitude I offset by IDC (IDC ≤ 0). Using the
following relations: ID,max = I + IDC , IDC = −I cos θ, Pout = VDD Id1 /2, and substitute Id1
with (2.9), we arrive at
ID,max =
2out (1 − cos θ)
,
VDD (θ − sin θ cos θ)
(2.12)
and therefore
PN =
θ − sin θ cos θ
.
4π(1 − cos θ)
(2.13)
Figure 2.5 shows that (a) PN is maximized at a θ of about 120◦ , and (b) its value for a class-B
PA is the same as a class-A PA. As θ decreases further, the ID,max required to keep the amplitude
of the fundamental component unchanged grows quickly, causing PN to drop. This indicates
that the device needs to be heavily stressed to keep output power the same, or conversely, output
power drops if the current swing is kept constant. Furthermore, decreasing the conduction angle
15
also tends to lower the gain of the PA. We have not formally analyzed how the power gain is
affected by the change in θ, but qualitatively speaking, since a larger voltage swing is required at
the gate to support the drain current waveform with smaller θ (as visualized in Fig. 2.3), we can
speculate that a larger signal power is needed at the gate. For these reasons, conduction angles
smaller than that of a class-B is rarely used in integrated RF PAs. To further improve efficiency
beyond the class-B condition, we turn our attention to PAs where the device is used as a switch
to reduce the voltage-current overlap product at the drain node.
2.2 Switch Mode Power Amplifiers
As mentioned earlier, the most important variable that determines the efficiency of the PA is the
voltage-current product at the drain. So far we have been treating the transistor as a controlled
current source, only changing the bias level to alter the drain current waveform. If we drive the
transistor heavily enough so that it acts as a switch that has either Id = 0 (off-state) or Vd = 0
(on-state), 100% efficiency can potentially be achieved.
2.2.1
Class-D
One of the more straightforward implementations of the switch mode PA concept is the classD topology, as shown in Fig. 2.6. Although a push-pull configuration can also be used, we
show here a complementary version of the class-D PA, which essentially behaves like a digital
inverter. Assuming that the two transistors behave as ideal switches, the voltage at the drain
node is a square wave, while the current flowing into the load resistor must be sinusoidal due
to the high-Q L-C resonant filter. This sinusoidal output current is provided alternately by M1
and M2, resulting in the half-wave rectified sinusoidal current waveforms Id1 and Id2 . Clearly,
the theoretical efficiency of the class-D PA is 100% due to the zero voltage-current overlap
product of both devices. Assuming that Id1,max = Id2,max = I, then output power can be
expressed as Pout = VDD I/π. The normalized power output capability of the class-D PA is
PN = 1/π ≈ 0.32. Compared to the maximum PN of approximately 0.134 of the classic
16
conduction mode PAs, the class-D PA has a much improved power handling capability. However,
the improved efficiency and power handling capability come at the expense of linearity, as a
switch mode PA does not have any easily predictable input-output relationship. For applications
that do not require amplitude modulation, the high efficiency of switch mode PAs in general can
be fully exploited.
Obviously, it is unlikely that a 100% efficiency can be achieved in real life. The devices
are imperfect switches with finite output voltage rise and fall time, as well as a series resistance
due to the finite conductivity of the device channels. The series on-resistance can be reduced by
increasing the size of the device, but in turn a larger driver amplifier would be needed to provide
the input drive and the efficiency of the system would be affected. In addition, the parasitic
capacitance at the drain node further softens the rising- and falling-edges of the output voltage
waveform, which introduces more V-I overlap and power dissipation. For these reasons, the
class-D PA’s high efficiency is quickly degraded as the operating frequency becomes a significant
fraction of the device cutoff frequency. Nonetheless, the class-D PA still enjoys popularity in
applications with low to moderate operating frequency.
Vd1
VDD
VDD
M2
t
Id1
Id2
vin
I
Id1
Id2
t
RL
I
M1
t
Figure 2.6: A simplified schematic of a class-D PA, and the voltage and current waveforms.
17
2.2.2
Class-E
The efficiency degradation caused by the charging of drain capacitance can be partially alleviated
by a clever arrangement of load passive elements, creating a nominally zero V-I overlap product
even in face of a drain capacitance. This is the core-idea of the class-E PA, as explained next.
Figure 2.7 shows a simplified schematic of a class-E PA. The NMOS transistor is modeled as
an ideal switch, and the load network consists of the shunt drain capacitance C1, the RF choke
L1, and the series resonant filter C2 and L2 that allows only the RF signal component to pass
through into the load. To understand how the class-E PA works, let us begin with analyzing
the current Id that flows through the switch. When the switch turns on, the drain voltage Vd
is zero, thus no current will flow through the shunt capacitor C1. Since the series resonator
enforces a sinusoidal current waveform, Id will have to be a sinusoid during the ON state. Next,
as the switch turns off, Id becomes zero. The “flywheel” effect of the L-C resonator enforces the
sinusoidal current to continue its procession, and since the RF choke only allows DC current to
Id
VDD
t
Idc
Ic1
L1
t
Irf
Id + Ic1
C2
L2
= -Irf + Idc
t
Id
Ic1
RL
Vd
C1
ON
OFF
Figure 2.7: A simplified schematic of a class-E PA, and the voltage and current waveforms.
18
t
pass through, the sinusoidal current must continue through C1. During the OFF state, Vd goes
up and then goes down as C1 is charged and discharged. Note that at the switching instant, IC1
is close to zero, resulting in a zero slope in the drain voltage at turn-on. Although ideally the
class-E PA efficiency is 100%, efficiency can degrade in the event of phase misalignment due to
mistuned circuit components. The zero-slope turn-on voltage waveform helps reduce this effect,
making the class-E PA more robust to variations.
The class-E operation depends on timing of voltage and current waveforms, which is tuned
by the values of the passive components in the load network. The design equations for the passive
components are listed as [31]
1
,
ω(5.277RL )
1.42
5.447
1+
,
C2 ≈ C1
Q
Q − 2.08
C1 ≈
L2 =
QRL
,
ω
(2.14)
(2.15)
(2.16)
where Q is the quality factor of the series resonator. Note that the intrinsic device parasitic
capacitance can usually be absorbed into C1, which is one of the primary advantages of the classE PA. Due to the “analog” nature of the class-E waveforms which contain no sharp transitions,
the class-E PA can often operate efficiently at higher frequencies compared to other switch mode
PAs. On the other hand, class-E operation proved demanding on the transistor as the peak drain
voltage can be as high as 3.6VDD . In fact, the normalized power output capability of the class-E
PA is approximately 0.1, lower than even the class-A PA. High voltage stress can be relieved by,
for example, the adoption of a cascode topology. We will revisit these topics in more detail in
Chapter 6. Similar to the class-D PA and other switch mode PAs, the input-output characteristics
of a class-E PA is fundamentally nonlinear and thus it is normally not used in applications that
require precise amplitude variations.
19
2.2.3
Class-F
The class-F PA is another topology that achieves 100% theoretical efficiency. As shown in
Fig. 2.8, the class-F PA consists of a transmission line segment that is a quarter-wavelength
at the carrier frequency ω0 , and with a characteristic impedance equal to RL . Also assuming that
both LChoke and CBlock are large and that the output L-C resonant tank has very high Q. Due to
the impedance transformation property of the quarter-wavelength transmission line1 , the transistor drain will see a zero impedance at all even harmonics of the carrier. At all odd harmonics,
the drain sees an open circuit. These conditions ensure that the drain voltage is an ideal square
wave, while the drain current is a half-wave rectified sinusoid, as shown in Fig. 2.8. Since there
is zero I-V overlap at the drain, 100% efficiency is achieved.
Vd
VDD
2VDD
LChoke
λ/4 at ω0
Id
t
CBlock
RL
vin
tuned to ω0
t
Figure 2.8: A simplified schematic of a class-F PA, and the voltage and current waveforms.
2.3 Outphasing Amplifier
The outphasing amplifier was first introduced by Chireix in 1935 [32] as a solution to the
linearity-efficiency trade-off. It promises the high efficiency of switch mode PAs while sup1
Zin · ZL = Z02 , where Zin is the impedance looking into the transmission line, ZL is the load impedance, and
Z0 is the characteristic impedance of the transmission line.
20
S1(t)
X(t)
Phase
Modulator
Y(t)
Y
S2(t)
b1
S1
X(t)
a/2
θ
b2
θ
S2
S1(t)
S2(t)
Y(t)
Figure 2.9: Illustration of the outphasing technique. A phase modulator decomposes the original signal
into two constant-envelop signals, enabling the use of efficient switch mode PAs. The amplitude information of the original signal is restored at the combiner output.
porting linear amplitude modulation. The operation of an outphasing transmitter is depicted in
Fig. 2.9. The desired RF signal, Y (t) = a(t) cos (ωt + φ(t)), is decomposed by a phase modulator (i.e. signal component separator) into two constant amplitude, phase-modulated signals:
S1,2 (t) = A cos (ωt ± θ(t) + φ(t)) where θ(t), the outphasing angle, is obtained as
θ(t) = cos
−1
a(t)
2A
,
(2.17)
where
A = max
a(t)
2
.
Since the amplitude information of the original signal is transformed into the phase domain, high
efficiency switch-mode PAs can be used to provide higher power efficiency. The vector sum of
the two PA outputs will follow the desired signal amplitude.
An important detail of implementing an outphasing system is to control how the two PAs
21
ZL1 = RL
ZL1 = R1 (1 + j tan θ)
λ
S1
4
S1
RL
RISO
λ
S2
4
S2
ZL2 = RL
ZL2 = R1 (1 – j tan θ)
(a)
(b)
Figure 2.10: (a) An outphasing PA with a non-isolating transformer combiner. Load impedance seen by
each PA is a function of θ. (b) An outphasing PA with a isolating Wilkinson combiner. Load impedance
is constant.
interact with each other through the combiner. As the input signal amplitude varies, the change
in outphasing angle would make the two PAs “pull” each other through the combiner, altering the
load impedance seen by each PA. An example is shown in Fig. 2.10(a), where a transformer is
used as a combiner. It can be shown that, in addition to a constant real part, the load impedances,
ZL1 and ZL2 , each has an imaginary component proportional to ± tan θ [32]. This can be problematic for some PA types, e.g. class-B and class-C, since efficiency degrades as the imaginary
component of the load impedance becomes larger in magnitude. A classical solution is to intentionally introduce reactive elements at the output of each PA, so that the ± tan θ components are
canceled, optimizing efficiency [32]. However, this optimization can only be achieved at a single
outphasing angle (i.e. output power level) if the reactive elements are fixed in value.
Another method is to employ an isolating combiner, such as a Wilkinson combiner as shown
in Fig. 2.10(b). Owing to the port isolating property, the load impedance seen by each PA is constant, independent of θ. This configuration provides a linear and predictable PA characteristics.
Since the power consumption of each PA is also independent of θ, the power dissipated by the
isolating resistor RISO increases as output power is reduced. This can be visualized in vector
form (right side of Fig. 2.9), where S1 (S2 ) can be seen as the sum of the vector a/2 and b1 (b2 ).
With an isolating combiner, the signal power associated with the two vectors b1 and b2 is dissipated through RISO , whereas if a non-isolating combiner is used, it is reflected and dissipated
22
RL
1.2
100
Normalized PAE (%)
Normalized PDC
1
0.8
0.6
0.4
0.2
80
60
40
10
0
0
0
0.2
0.4
0.6
0.8
0
1
0.2
0.4
0.6
0.8
1
Normalized Output Power
Normalized Output Power
Class-E, Wilkinson Combiner
Class-D, Transf ormer Combiner
Class-E, Wilkinson Combiner
Class-F, Chireix Combiner
(Numbers are estimated from figures in references)
Class-D, Chireix Combiner
Figure 2.11: Comparison of power consumption and efficiency vs. power back-off among outphasing
PAs in the literature.
within the PAs (assuming that the PAs’ characteristics are not changed by the load impedance
variation).
As mentioned previously, the behavior of an outphasing system strongly depends on the type
of PA used. In fact, if the PAs sufficiently resemble ideal voltage sources, e.g. class-D PAs,
it can be shown that efficiency is independent of load impedance variation. Essentially, the
average current drawn from the power supply by a class-D PA scales linearly with output power
[33, 34]. If the devices are modeled as ideal switches, 100% efficiency is achieved regardless
of output power level [35]. In reality, loss sources such as driver power dissipation, device onresistance, and short-circuit current loss degrades efficiency as output power is reduced. To gain
a feel of the performance of different outphasing PA topologies in real life implementations,
several outphasing PAs from the literature are compared in Fig. 2.11 [19, 36–39]. To facilitate
the comparison, the normalized DC power consumption (i.e. PDC /PDC,max ) and normalized
PAE (i.e. P AE/P AEmax ) of each design are plotted against the normalized output power. The
two curves that represent outphasing PAs with an isolating combiner are very linear, due to the
near-constant power dissipation versus output power. On the other hand, designs using class-D
23
and class-F PAs with non-isolating combiners show linearly decreasing PDC as output power
backs off. The slope of the PDC curves is a function of the constant PDC components in the
system (e.g. driver power consumption), whose value can be obtained by intercepting the curves
at the Y axis. At 6 dB power back-off (i.e. normalized output power of 0.25), the normalized
PAE of isolating outphasing PAs is degraded by a factor of more than 3, while PAE is degraded
by no more than a factor of 2 for the non-isolating counterparts.
Despite the advantage of a higher back-off efficiency, non-isolating outphasing PAs require
extra care to meet the stringent linearity and spectrum emission standards, which often require
the augmentation of the core PA with sophisticated digital signal processing. In either case,
further improvement of back-off efficiency is desired. We will propose a solution to this problem
in the following chapter.
24
Chapter 3
2.4GHz PA with Dynamic Power Control
As mentioned in Chapter 1, high data-rate modulation schemes such as OFDM place stringent
requirements on the power amplifier. In addition to watt-level output power and good linearity, a
large power control range and good efficiency at power back-off are also necessities. In addition,
CMOS implementations of such PAs incur additional challenges due to the low device breakdown voltage and the lossy silicon substrate. In this chapter, a fully-integrated CMOS outphasing PA that simultaneously meets the aforementioned requirements is presented. Key concepts
include the implementation of the dynamic power control scheme which extends output power
range and improves PA back-off efficiency, as well as the use of a transformer power combiner
and a cascode inverter-based class-D topology to achieve watt-level output power using 45 nm
digital CMOS devices.
3.1 Introduction
The outphasing architecture is a promising candidate for power amplifier integration in CMOS,
as has been repeatedly demonstrated in recent literature [18, 19, 32–34, 36, 38–42]. It utilizes
high efficiency switch-mode PAs whose speed and linearity is potentially improved with the
scaling of digital CMOS processes [34], and it is compatible with modulator topologies that are
CMOS scaling-friendly as well [43–45]. As discussed in Chapter 2, an outphasing system that
employs class-D PAs and a non-isolating combiner can ideally have high efficiency at back-off
power levels. In reality, the efficiency of an outphasing PA at power back-off is limited by the
short circuit power dissipation in the switch-mode output stage and the constant driver power
25
consumption. A conventional outphasing PA is also limited in its output power range, since a
zero output power requires the two outphasing paths to cancel each other perfectly, an impractical
assumption given the variation of scaled CMOS processes and other non-idealities.
Furthermore, cellular and wide area network standards require large power control ranges,
e.g. on the order of 50 dB for WiMAX. To extend the power control range of the outphasing
system while maintaining high back-off efficiency, a multi-section transformer-based combiner
that enables on-off switching of PA cells can be used, which is similar in concept to [8, 10, 46, 47]
which have implemented discrete power control. After the minimum transformer size has been
reached, progressively smaller unit PA cells are used to enable further power reduction.
The various discrete power control schemes demonstrated in the literature have been mostly
static across a packet. The possibility of implementing dynamic power control (DPC), i.e. turning on or off PA segments dynamically according to the instantaneous power level to further
enhance average efficiency, has been pointed out in [8] and [46], but the actual implementation
of DPC has not been demonstrated prior to this work [19].
In this chapter, a transformer combined class-D outphasing PA with DPC is presented. It
employs a transformer combiner with primary coil units that can be individually turned on or off
for power control. Each primary coil unit is itself a push-pull outphasing pair. With the proposed
PA topology, watt-level output power is achieved in a 45 nm LP digital CMOS process. Furthermore, DPC has been deployed to increase output power range and enhance average efficiency at
back-off.
3.2 Proposed PA Topology and Dynamic Power Control
In the proposed outphasing PA, voltage-mode class-D PAs are used to amplify the outphasing
signals. Output summation is achieved by a transformer combiner. In this section, the various
loss mechanisms of the proposed outphasing PA topology will be investigated to determine the
efficiency of the PA. The dynamic power control scheme will then be explained in more detail,
including a discussion of its potential limitations and a mitigation strategy for those limitations.
26
3.2.1
Class-D Outphasing PA
A voltage-mode class-D PA is typically configured as an inverter. Ideally, a square wave voltage
is generated at the output drain node. The overlap of the voltage and current waveforms of each
transistor in a class-D stage is minimum resulting in a high efficiency. The outphasing operation
of class-D PAs with a transformer combiner is illustrated in Fig. 3.1, where the two PAs are
modeled as voltage sources. The combiner consists of two ideal transformers with 1:1 turn ratio
that are connected in series at the secondary side. Following a derivation similar to that in [34],
it can be shown that
Vo =
4
(2Vi cos θ).
π
(3.1)
Since output amplitude is proportional to cos θ, the condition of (2.17) is met which validates
the outphasing summation property. Furthermore, the output current of each PA, IS1 and IS2 , are
each proportional to cos θ as well. As a result, efficiency at power back-off does not degrade in
the ideal case. As mentioned earlier, this is in contrast to outphasing systems that utilize isolating
combiners, e.g. a Wilkinson combiner, in which case the PAs’ output current before the combiner
I S1 =
Vi
4 2
Vi cos(θ)
π RL
VS 1 = Vi e jθ
− Vi
V0 =
RL
VS 2 = Vi e − jθ
2θ
IS2 =
4 2
Vi cos(θ)
π RL
Figure 3.1: Class-D outphasing system with a transformer combiner.
27
4
2Vi cos(θ)
π
is constant regardless of outphasing angle.
In general, PAE is defined as
P AE =
Pout
Pout − Pin
≈
.
PDC
Pout + Pdiss
(3.2)
We assume that the input power, Pin , is negligible, since the PA input is a small size inverter.
The power dissipation term, Pdiss , is dominated by three components:
1. The DC power consumption of the PA drivers, Pdriver .
2. The short-circuit current loss, Pshort , caused by the non-zero rise and fall time of the driving signal as well as the finite PA device switching speed and conduction overlap of the pand n-channel devices.
3. Pres , the power dissipation due to non-zero transistor on-resistance and the insertion loss
of the output matching network.
Both Pdriver and Pshort are independent of outphasing angle and hence output power, whereas
70
60
40
Pout,max
30
PAE (%)
50
Pconst
20
10
0
-30
-20
-10
0
Normalized Output Power (dB)
Figure 3.2: Calculated PAE versus normalized output power. The variable Pconst /Pout,max equals to 0.2,
0.5, 1, and 2 for each curve respectively.
28
Pres scales linearly with output power [35]. Normalizing these terms by Pout yields
1
P AE =
1+B+
Pconst
Pout
,
(3.3)
where
B=
Pres
,
Pout
Pconst = Pdriver + Pshort .
(3.4)
Note that both B and Pconst are independent of outphasing angle. At low output power levels (i.e.
large outphasing angles), PAE is limited mainly by Pconst . Fig. 3.2 shows the efficiency curves
given different Pconst to Pout,max ratios, where B is assumed to be 0.3. PAE would be greatly
improved if Pconst is decreased, especially at low power levels.
3.2.2
Power Control With a Multi-section Transformer Combiner
Power control enhances efficiency at power back-off by scaling down DC power consumption.
One way to implement power control in a transformer combined outphasing PA is by adopting
the multi-section transformer topology as shown in Fig. 3.3. A total of N unit blocks, each being
a self-contained outphasing PA identical to the structure shown in Fig. 3.1, are serially connected
at the transformer secondary side to the output load. In this configuration, each unit block can
be turned off by connecting the corresponding primary terminals to ground. The grounding of
primary terminals in the OFF sections helps maintain proper load-line matching in the remaining
Block N
VS1
VS2
VS 1 = Vi e jθ
Block 2
VS2
VS1
Block 1
IS1
IS2
VS1
VS2
VS 2 = Vi e − jθ
Figure 3.3: The multi-section transformer combiner topology for discrete power control.
29
RL
unit blocks. As unit blocks are switched off, the load impedance seen by each remaining unit
PA increases, resulting in reduced DC power consumption. The net effect on PAE is analyzed
as follows. Again, we model the unit class-D PAs as voltage sources, and the unit transformers
are assumed to be ideal with 1:1 turn ratio. Furthermore, among the N unit blocks of the PA,
assume that M unit blocks are on, while N −M unit blocks are turned off. The voltage amplitude
across the secondary transformer coil of each of the M operating unit blocks is given by (3.1).
The voltage amplitude across the output load resistor is the summation of the voltage amplitude
across each of the M blocks
Vo,load =
4
(2M Vi cos θ).
π
(3.5)
This output voltage results in a current through the output load, Io,load , given by
Io,load =
Vo,load
4
=
(2M Vi cos θ).
RL
πRL
(3.6)
Io,load is coupled back to the primary side of each transformer. Therefore, IS1 = IS2 = Io,load .
The load impedance seen by each unit PA looking into the combiner is given by
ZS1 =
ZS2
VS1
Io,load
VS2
=
Io,load
π RL
(1 + j tan θ),
4 2M
π RL
(1 − j tan θ).
=
4 2M
=
(3.7)
As seen in (3.7), the multi-section transformer combiner provides a 2M impedance transformation ratio, i.e. load impedance increases as sections of the PA are turned off. The total output
power of the PA is given by
Pout
2
Vo,load
= M2
=
2RL
30
8
Vi cos θ
π
2RL
2
.
(3.8)
30
100
1/8
25
20
4/8
15
2/8
2/8
PAE (%)
6/8
80
60
4/8
40
10
6/8
1/8
20
5
0
-40
-30
-20
-10
PDC Reduction (%)
8/8
0
0
-40
Normalized Output Power (dB)
-30
-20
-10
0
Normalized Output Power (dB)
(a)
(b)
Figure 3.4: (a) Calculated PAE of a multi-section transformer combined outphasing PA with discrete
power control. 8 unit blocks are used (N = 8) and the 5 curves represent M = 8, 6, 4, 2, 1, respectively.
(b) Calculated power consumption reduction versus normalized output power of the low power modes
as compared to the 8/8 mode. For the reference 8/8 mode, outphasing control is assumed to achieve the
different power levels.
Note that the total output power scales with M 2 . The total power dissipation of the PA can be
written as
Pdiss = (Pdriver + Pshort ) + Pres
= (M × Pconst,unit ) + B × Pout ,
(3.9)
where Pconst,unit is the sum of the driver power consumption and the short circuit power dissipation of a unit block, and the proportionality constant B is defined in (3.4).We are now in a
position to write the PAE of the multi-section transformer-combined PA, in a form similar to
(3.2), as
Pout
Pout
=
Pout + Pdiss
Pout + M × Pconst,unit + B × Pout
1
.
=
M × Pconst,unit
1+B+
Pout
P AE =
(3.10)
The resulting PAE curves are shown in Fig. 3.4(a), assuming that a multi-section outphasing
PA with 8 unit blocks (N = 8) is used, with B equals to 0.3 and a Pconst,unit to Pout,max ratio
31
of 1/4 (representing a typical implementation in deeply scaled CMOS). The 5 curves represent 5
PA modes with M set to 8, 6, 4, 2, and 1, respectively. As expected, PAE is improved whenever
unit blocks are turned off. Nonetheless, the improved back-off PAE is lower than the peak PAE
when M equals 8, since Pout scales down faster (proportional to M 2 ) than M × Pconst,unit .
A specific power back-off can be achieved by either outphasing or by turning off transformer
units. For example, a 6 dB back-off can be obtained by setting the outphasing angle (θ) to 60◦ ,
or alternatively by turning off half of the transformers units. For the reasons explained above,
transformer switching is a more power efficient back-off mechanism. To visualize this effect,
Fig. 3.4(b) shows the percentage reduction of power consumption at each low power modes (i.e.
back-off by transformer switching in addition to outphasing) compared to the peak power mode
(i.e. back-off by outphasing alone). At the same back-off of 6 dB, DC power is reduced by more
than 40% by adopting the 4/8 mode as compared to the 8/8 mode. An almost 10-fold reduction
in DC power is obtained at back-off levels greater than 20 dB with the 1/8 mode.
3.2.3
Dynamic Power Control
A PA with static discrete power control typically changes its configuration during the signal down
time between data packet transmissions. The power control setting is configured to accommodate
Pout
PA mode:
8/8
P1
6/8
P2
4/8
2/8
1/8
Static power control: Fixed at 6/8 due to P1 requirement
DPC mode: 4/8
2/8
4/8 6/8 4/8 2/8 1/8
Figure 3.5: Illustration of the DPC scheme. DPC switches PA modes instantaneously, while static power
control picks a mode that satisfies peak power requirement.
32
the peak output power requirement, which can be significantly higher than the average power for
signals with high PAPR. For example, the signal shown in Fig. 3.5 would require the PA be set
to the 6/8 mode to accommodate the peak power P1 , despite the fact that the average power of
the sequence is P2 (i.e. in the 4/8 mode power range). By contrast, a dynamic power control
(DPC) scheme reconfigures the PA according to the instantaneous power level, such that the
PA is always configured in the most efficient mode. For the same example in Fig. 3.5, the PA
dynamically switches between modes 4/8, 2/8, 4/8, etc., tracking the desired signal, as shown in
the bottom part of Fig. 3.5.
To illustrate the efficiency improvement enabled by DPC, a Matlab-based OFDM simulation
is performed which applies a 20 MHz bandwidth, 64-QAM, 6 dB PAPR WiFi signal onto a PA
with PAE characteristics as given in Fig. 3.4(a). The resulting average PAE versus the normalized
average output power of the OFDM packet is shown in Fig. 3.6. The average PAE of the static
power control configurations (i.e. 8/8, 6/8... etc.) is limited by the PAPR of the OFDM packet,
whereas DPC fully utilizes all the available configurations regardless of data packet average
power and PAPR, and it achieves the highest average PAE over the entire output power range.
When DPC is used, the outphasing angle (θ) has to be adjusted accordingly as shown in
25
DPC
15
10
Static (8/8)
Static (2/8)
Average PAE (%)
20
5
Static (6/8)
Static (4/8)
-35
-30
-25
-20
-15
0
-10
-5
Normalized Average Output Power (dB)
Figure 3.6: Simulated average PAE of the PA under a 10 MHz bandwidth, 64-QAM WiFi signal.
33
90
80
60
50
40
30
θ (degree)
70
20
10
0
-60
-40
-20
0
Normalized Output Power (dB)
Figure 3.7: Outphasing angle versus normalized output power with DPC. The dashed curve represents
the θ and output power relationship of an outphasing PA without DPC.
Fig. 3.7. As the output power is reduced from peak (0 dB), one or more PA unit blocks are
turned off whenever a DPC threshold is reached, and θ returns to 0, which corresponds to full
power for the remaining PAs. This θ trajectory with DPC is to be compared against the required
θ for an outphasing PA without DPC (dashed line in Fig. 3.7). The phase modulator used to
generate the outphasing signal needs to make abrupt phase jumps when DPC switching occurs.
This can be handled by an open loop phase modulator like the one in [48].
The greatest challenge of implementing DPC is the ACPR degradation caused by DPCinduced supply ringing. A simple model, depicted in Fig. 3.8, explains the origin of the supply
ringing waveform. The parasitic inductance in the supply network is modeled as an inductor L,
and C represents the on-chip decoupling capacitor. At the DPC switching instant, t1 , one of the
unit blocks of the PA is turned off. The abrupt change in the current drawn by the PA creates a
ringing transient on top of the DC supply voltage. The magnitude of the ringing peak is related
to the height of the PA current step, as well as the values of L and C. These ringing waveforms
distort the amplitude of the output signal through the supply voltage of the constituent outphasing PAs. At the same time, supply ringing also distorts the OFDM phase since the delay of the
34
L
VDD,PA
VDD
C
0
2.6
-20
2.4
2.2
2
I PA (A)
0.6
0
0.0000001
PSD (dB/Hz)
VDD,PA (V)
2.8
IPA
-40
With DPC
-60
-80
0.4
Ideal
-100
0.2
-120
0
73.2
0
t1 Time
78.2
100
200
Frequency (MHz)
Figure 3.8: A simplified PA supply network illustrates the generation of the ringing waveform (VDD,P A )
caused by the abrupt change in IP A due to DPC switching. The simulated output spectra of an ideal PA
and a PA with DPC ringing are shown.
PA devices and drivers changes with supply voltage. The result of these supply transients is the
“bump” in the output spectrum that limits ACPR, as shown in the simulated output spectrum in
Fig. 3.8. The single spectrum “bump” is due to a very simplified parasitic model of the supply network. More realistic models would include inductance due to board traces, board power
supply decap (decoupling capacitor), bond-wire inductance, on-chip decap, and on-chip supply
routing resistance and inductance. These components can give rise to multiple bumps at different
frequencies associated with the different parasitic supply resonances.
The amplitude of the spectrum bump is related to the ringing waveform peak amplitude,
35
Norm. Signal Power (dB)
skip window
PA mode:
0
8/8
-5
6/8
4/8
-10
2/8
-15
-20
1/8
-25
-30
-35
-40
0
50
Sample
100
150
Figure 3.9: Illustration of the “skip window” concept. DPC mode transitions are skipped if the adjacent
transition points fit within the skip window.
and also the rate at which the PA changes modes. In general, supply ringing can be reduced
by minimizing inductance in the supply network, e.g. by using a better quality package or more
bond-wires, by improving board layout with decap placement closer to IC, by using more on-chip
decap, or by using better quality board decap, etc. Nonetheless, it might be difficult to sufficiently
reduce supply ringing within reasonable cost constraints. To mitigate supply ringing, we can
apply a technique to skip some of the power control mode transitions that are narrow in time
since they contribute little to the overall efficiency improvement. To identify these short-duration
transitions, we define a “skip window” as follows. Illustrated in Fig. 3.9, a “skip window” scans
the signal amplitude sequentially until a power control transition point is reached (i.e. the signal
waveform intersects a transition threshold in its descent). If the next transition point to the same
threshold level falls within the length of the “skip window”, all mode transitions within these
two transition points are ignored and the PA stays in its current mode.
The effect of the skip window scheme on ACPR and average PAE is shown in Fig. 3.10,
which is obtained from the Matlab-based OFDM simulation by assuming a ringing waveform
from the simple supply network model shown in Fig. ??. An output power back-off of 6 dB has
36
80
20
70
19
60
18
50
17
40
ACPR (dB)
Average PAE (%)
21
30
16
10
100
1000
Skip Window
Length (ns) 1000
100
10
Figure 3.10: Simulated ACPR and average PAE versus “skip window” length.
25
(i) full DPC
15
10
(iv) no power ctrl
Average PAE (%)
20
(ii) DPC w/ skipping
for ACPR > 40dB
5
(iii) static power ctrl
0
-20
-18
-16
-14
-12
-10
-8
-6
Normalized Average Output Power (dB)
Figure 3.11: Simulated OFDM average PAE comparison between: (i) Full DPC, (ii) DPC with skip
window scheme for 40dB ACPR target, (iii) static power control, and (iv) no power control.
been used in these simulations. As shown on the far-left side of Fig. 3.10, average PAE is close
to 21% without the application of the skip window. As the skip window length increases, the
37
number of DPC transitions within the OFDM packet drops. ACPR improves as a result, but the
DPC efficiency improvement is decreased. Fig. 3.11 presents the simulated OFDM average PAE
characteristics of the PA under different power control schemes: (i) full DPC (i.e. no transition
skipping); (ii) DPC with the skip window scheme for a 40 dB ACPR target; (iii) static power
control; and (iv) no power control. The calculated PAE characteristics of Fig. 3.4 have been used
in this experiment. The difference in PAE enhancement between (i) and (ii) is greatest at high
output levels due to a wider skip window required for 40 dB ACPR. As output power decreases,
transitions between the lower power PA modes begin to dominate. Since the ringing waveforms
generated by these transitions are smaller in amplitude, a narrower skip window can be used to
achieve the same ACPR, and average PAE approaches that of full DPC. To summarize, the skip
window scheme provides us with a means to trade PAE enhancement with ACPR, allowing the
PA to benefit from DPC efficiency enhancement while meeting the spectrum mask requirement.
3.3 Design and Implementation
3.3.1
PA Topology
The transformer-combined outphasing class-D PA has been designed in a 45 nm LP digital
CMOS technology. A simplified schematic of the PA is shown in Fig. 3.12. The PA consists of 4
unit blocks that are connected in series to a transformer combiner. Each unit block, structurally
similar to the PA reported in [34], is a self-contained outphasing PA that can be turned on or off
to implement power control. The transformer combiner within each unit block is configured in a
3-coil layout. The inner- and outer-primary coils each connects to a set of two pseudo-differential
unit PAs. Both primary coils couple to the same secondary coil in the middle. The outer- and
inner-coils can also be turned on or off separately, enabling an additional level of power control
within a unit block. To implement DPC, the PA can be dynamically configured among 5 modes,
namely 4/4, 3/4, 2/4, 1/4 and 0.5/4, as shown in Table 3.1. The power back-off provided by each
mode is ideally 0 dB, 2.5 dB, 6 dB, 12 dB, and 18 dB, respectively.
38
0.54pF
0.91pF
Unit PA
3.63pF
S1+
supply feed & de-cap
S1
Out+
2.4V
GND
Out1.2V
RL
0.35nH
S1-
Block 1
S2-
S1
S2+
1.8pF
GND
1.2V
2.4V
2.4V
1.2V
GND
0.35nH
Block 2
output
match
Block 1
S2
Block 2
S2
L-C Resonant
Traps
S1
Block 3
GND
1.2V
2.4V
2.4V
1.2V
GND
0.32nH
S1
1.5pF
PA cells
Block 3
0.35nH
Block 4
GND
1.2V
2.4V
2.4V
Low Power 1.2V
GND
Unit PA
supply feed
& de-cap
Block 4
S2
2pF
1.2V
GND
2.4V
0.32nH
0.35nH
S2
(a)
(b)
Figure 3.12: (a) Proposed transformer-combined outphasing PA topology. (b) Chip micrograph.
Mode
4/4
3/4
2/4
1/4
0.5/4
Theoretical
back-off (dB)
0
2.5
6
12
18
Block 1:
ON
OFF
OFF
OFF
OFF
Block 2:
ON
ON
OFF
OFF
OFF
Block 3:
ON
ON
ON
OFF
OFF
Block 4:
ON
ON
ON
ON
Half-ON
Table 3.1: Power control configurations.
3.3.2
Unit PA
Fig. 3.13(a) depicts the simplified schematics of the unit PA half-circuit. The output stage is
implemented as a cascoded inverter-based class-D PA. The cascode structure allows the use of
39
x8
power ctrl bits
2.4 V
Variable
Delay
On/Off
Control
2.4 V
2.4 V
On/Off
Control
M4
1.2 V
M4LP
1.2 V
M3LP
M3
S1+in
scan chain
bits
power ctrl bits
S1 +out
S1 +in
S1+out
M2LP
M2
1.2 V
Variable
Delay
On/Off
Control
2.4 V
1.2 V
On/Off
Control
M1
(a)
M1LP
(b)
Figure 3.13: Simplified schematics of (a) unit PA cell, and (b) low power unit PA cell.
thin-gate digital CMOS devices under a 2.4 V supply voltage [41]. Switch devices M1 and M4
are sized at 576 µm and 1152 µm respectively, whereas the cascode devices M2 and M3 are
double the size of the switch devices to provide a lower on-resistance. Two separate voltage
domains, namely 1.2 V to 0 V and 2.4 V to 1.2 V, are used to power the driver chains of the
NMOS device (M1) and PMOS device (M4). The two supply voltages are provided externally.
DC level shifting of the signal is achieved by capacitive coupling and re-biasing in the two signal
paths. Each driver chain is preceded by an on-off control block that receives DPC control signals
from an on-chip high speed decoder. When a block is to be turned off, the PA devices are used
as low-loss switches to short the transformer primary coil to RF ground. Delay line elements are
also added in each PA device’s driver to equalize the delay mismatch over all the unit PA cells,
and also between NMOS and PMOS PA devices. The delay lines are configured statically with a
scan chain in an efficiency optimization procedure during test.
To achieve even lower power levels than what is shown in Table 3.1, smaller low-power
unit PAs are added to transformer Block 4 in Fig. 3.12(a). The low-power PAs are implemented
as separate units instead of part of the main PA, since power combining is not required. The
topology of the low-power PA units is similar to the unit PA of Fig. 3.13, but with smaller
40
transistors (sized at 8/16/32/16 µm for M1LP through M4LP respectively). Eight of these small
PAs (each consisting of S1 and S2 differential outphasing inputs) are attached to the outer primary
coil of Block 4 (Fig. 3.12). The low-power PAs can be turned on or off independently to deliver
40 dB to 60 dB output back-off. The low-power PAs are not used in the DPC operation, since
the effect on efficiency enhancement is negligible at very low power levels. Instead, their main
function is for static power control over large ranges, such as those required in cellular standards.
Since efficiency is not critical in the low-power PAs, delay trimming is not implemented here.
3.3.3
Transformer Combiner
The multi-section transformer combiner is formed by slab inductors on a 3.4 µm thick copper
layer. Lateral coplanar coupling provides a coupling coefficient of approximately 0.55 between
adjacent coils. The effective coupling coefficient from the combination of the inner- and outerprimary coils to the center secondary coil is 0.64. The coupling coefficient can be increased by
reducing the coil spacing, resulting in a slightly improved PA efficiency. However, the increase
in transformer parasitic capacitance degrades the differential symmetry of the PA and potentially
offsets the gain in efficiency. The transformer combiner is simulated in a 2.5D EM solver. The
simulated insertion loss of the entire combiner structure is 1.4 dB. To incorporate the transformer
combiner into circuit simulations, a lumped equivalent circuit model of the transformer is used.
As shown in Fig. 3.12(a), the two transformer primary coils are connected together in Blocks
1-3, whereas in Block 4 they are not connected to allow individual switching. L-C resonant
harmonic traps are located at the drain of each unit PA for second harmonic suppression to
improve drain efficiency. The inductors in the harmonic traps are laid out as right-angle wires and
are sufficiently far away from the transformer coils(Fig. 3.12(a)), hence the magnetic coupling is
low. The harmonic traps in Block 4 have different L and C values from the other blocks due to the
different transformer primary coil inductance. In each unit block, one of the transformer primary
coils is excited by PA outputs S1+ and S2− and the other by S1− and S2+ . This configuration
reduces the resistive loss in the secondary coil at back-off and minimizes the parasitic differential
41
ground inductance of the PA.
An on-chip output matching network consisting of three capacitors resonates with the transformer inductances as well as packaging parasitics to maximize output power and efficiency.
Since the transformer is utilized as an integrated balun to deliver output power to a single ended
load, the asymmetric voltage swing on the secondary transformer coil on both sides of a unit PA
could couple back to the PA drain nodes through transformer parasitic capacitances. This effect
would slightly degrade the differential symmetry of unit PAs and limit the linearity of the outphasing PA. The effect of transformer capacitive coupling is least disrupting in segments furthest
away from the output, thus for low power configurations Block 4 is used.
3.3.4
Supply and Ground Network
Fig. 3.12(b) shows the micrograph of the PA die. Die size is measured as 1.2 mm by 2.6 mm,
including bond pads. Meshed supply and ground feed lines are inserted between each unit block
to reach the PA devices. This layout reduces the unwanted coupling between adjacent blocks.
Figure 3.14: Photograph of the PA evaluation board.
42
Decoupling capacitors are placed underneath the DC feed lines to reduce high frequency supply
variations. Both the PA devices and drivers share the same on-chip ground mesh network. The
PA is packaged in a standard low cost quad-flat no-leads (QFN) format, and mounted on an
FR-4 printed circuit board (PCB) for evaluation, as shown in Fig. 3.14. As discussed in Section
3.2, parasitic inductance in the supply and ground network causes DPC ringing and degrades
ACPR. A model of the supply network was constructed to estimate the DPC ringing waveforms.
The model includes the bond-wire inductance, PCB trace inductances as well as on-chip and
PCB surface mount decoupling capacitors. Using this model, the resulting simulated output
spectrum of a DPC-enabled PA under a 64-QAM 20MHz WiFi packet is shown in Fig. 3.15. The
bump located near 50 MHz frequency is associated with board parasitics, and the bump around
150 MHz is due to the IC package. Clearly, to meet spectrum mask and ACPR requirements,
the magnitude of these bumps needs to be reduced by the application of the skip window, as
explained in Section 3.2.
10
0
PSD (dB/Hz)
-10
-20
-30
-40
-50
-60
-70
-80
0
50
100
150
200
Frequency (MHz)
Figure 3.15: Simulated output spectrum of the DPC-enabled PA with a 64-QAM, 20 MHz WiFi packet
using the supply and ground network parasitics model.
43
3.4 Experimental Results
3.4.1
Test Setup
The setup for modulated signal measurement of the outphasing PA is shown in Fig. 3.16. The
outphasing modulation and subsequent I/Q decomposition of the baseband signal are calculated
in software. The resulting signals are then played back by an arbitrary waveform generator
(AWG) at a rate of 560 MHz, and then up-converted to RF with discrete components. Mismatch
in the test setup between the two outphasing paths, as well as the two I/Q signal pairs, are
carefully calibrated as in [34]. The 3-bit power control signals are generated by the AWG using
the marker output ports. Phases of these AWG markers are fine-tuned to reduce the timing
mismatch between the power control signals and the outphasing input signals. The power loss
associated with the PCB traces and connectors are de-embedded from measurement, whereas
losses of the package leads and bond-wires are included in the measurement results.
Sig Gen
LO
φ
marker
output
AWG
90°
φ
0°
pwr_control [ 0:2 ]
DUT
S1_I
S1
Balun
S2
Balun
BB Data
Combiner
S1_Q
EVM
Meas.
S2_I
S2_Q
Figure 3.16: Block diagram of the modulated signal measurement setup.
44
Spectrum
Analyzer
3.4.2
Delay Line Configuration
As mentioned in the previous section, the driver chain of each PA device is preceded by a variable delay line. Since the PA contains a total of 16 unit PAs, and each unit PA in turn contains
two NMOS and two PMOS devices, the total number of independently configurable delay lines
is 64. An optimization routine searches for a delay line configuration that minimizes the timing
mismatch between outphasing pairs, differential pairs, and between the NMOS and PMOS devices within each unit class-D PA. The timing mismatch can be reduced to within a precision of
20ps, as long as the overall timing spread is within the delay line tuning range of 80ps.
A Matlab script is written to program the scan chain as well as reading out data from the
measurement setup. Specifically, one out of the 64 delay lines is picked randomly and its delay
range is swept. The configuration that yields the highest PA efficiency will be stored, and the next
delay line to be swept is selected randomly. Each delay line sweep would take approximately 30
seconds, and the optimization would reach a plateau in about 2 hours. The delay line optimization
routine contributed to a 0.6 dB improvement in peak output power. However, the 80ps tuning
range is exhausted across the PA (i.e. peak timing mismatch is greater than 80ps), suggesting
that by adopting delay lines with a larger tuning range, even better alignment can potentially be
achieved.
3.4.3
Continuous Wave Test
The results of CW measurements of the PA are shown in Fig. 3.17. At 2.4 GHz, the PA achieves
31.5 dBm of peak output power with 27% PAE. Each of the high power modes of the PA (i.e.
4/4, 3/4, 2/4, 1/4, and 0.5/4) has an outphasing power range of more than 38 dB. On the other
hand, each of the low power modes exhibit a smaller outphasing power range (i.e. 25-30 dB)
due to the larger mismatch between the low power PA outphasing pair, which does not contain
trimming delay lines. The total output power range, contributed from both power control and
outphasing, is 86 dB (Fig. 3.17(a)).
Continuous wave PAE enhancement at back-off output power is shown in Fig. 3.17(b), whereas
45
40
30
20
10
30
25
3/4
20
4/4
2/4
15
1/4
10
0.5/4
PAE (%)
Output Power (dBm)
40
30
20
10
0
-10
-20
-30
-40
-50
-60
5
0
0
8
12
Normalized Outphasing Output Power (dB)
16
20
24
Output Power (dBm)
(a)
28
32
(b)
Figure 3.17: (a) Measured output power versus normalized outphasing output power of all PA modes.
Normalized outphasing output power of each mode is defined by −20 log(cos θ), where θ is the outphasing
angle. (b) Measured PAE versus output power of all of the high power PA modes.
6
3
3/4
2
2/4
1
0.5/4 1/4
8
12
16
20
24
Output Power (dBm)
PAE (%), Output Power (dBm)
4
Power Consumption (W)
5
4/4
34
26
22
18
Output Power
14
PAE
10
0
28
30
1.4 1.6 1.8
32
(a)
2 2.2 2.4 2.6 2.8
Frequency (GHz)
3
3.2 3.4
(b)
Figure 3.18: (a) Measured DC power consumption versus output power of all of the high power PA
modes. (b) Measured peak output power and PAE versus frequency.
Fig. 3.18(a) presents the DC power consumption of each of the PA modes versus output power.
At low power levels, the difference in power consumption between the 4/4 mode and the 0.5/4
mode is more than 7-fold. Fig. 3.18(b) reports the peak output power and PAE of the PA versus
operation frequency. The wideband response of the transformer combiner contributed to a -3
dB output power bandwidth of greater than 1.7 GHz. However, peak output power at 2.4 GHz
is 1.45 dB lower than the simulated result. This discrepancy is attributed to the inaccuracies in
supply network and transformer combiner modeling.
46
3.4.4
Modulated Signal Test
The PA is tested using a 64-QAM, 20 MHz bandwidth WLAN signal in the setup as described
in Fig. 3.16. Predistortion of the DPC PA is performed in software to minimize nonidealities,
including the AM-AM (i.e. outphasing angle to output signal amplitude) and AM-PM (i.e. outphasing angle to output signal phase) distortion of each PA mode, the output phase offset incurred
by PA mode transitions, and S1 -S2 phase mismatch which is also mode-dependent. Fig. 3.19
shows measured PAE versus average output power with and without DPC. At 25 dBm of average
output power, the PA meets the -25 dB EVM requirement with 12% PAE without DPC. With
DPC enabled, the same requirement is met at 24.8 dBm average output power with 16% PAE
(as shown circled in Fig. 3.19). This marks a 33% reduction in power consumption. A more
significant efficiency enhancement is obtained at a lower average output power, e.g. with DPC at
20.5 dBm average output power, PAE improves from 5% to 12%, a power consumption reduc-
PAE (%)
Back-off (dB)
20.45
20
18
16
14
12
10
8
6
4
2
0
11
18.45
13
16.45
14.45
12.45
10.45
8.45
6.45
15
17
19
21
23
25
Average Output Power (dBm)
Ideal PAE w/ full DPC (no skipping)
Measrued PAE w/ DPC (optimized skip window)
Measured PAE w/o DPC
Figure 3.19: Ideal and measured PAE versus average output power under WiFi signal at 2.4 GHz.
47
tion of 140%. The dashed line in Fig. 3.19 represents the estimated ideal PAE with full DPC,
i.e. the skip window length is set to zero, using the measured CW PAE at different power levels.
The gap between the ideal and measured PAE is due to the applied non-zero skipping window,
and the gradually closing gap as output power decreases agrees with the analysis in Section 3.2
(Fig. 3.10).
A slight degradation (in the order of 1 dB) of EVM is observed with DPC enabled if the skip
window is not applied. We have determined empirically that a skip window length of 196 ns is
sufficient to suppress the DPC-induced spectral bumps to satisfy the WiFi mask requirement, as
well as restoring the EVM degradation. The actual implementation of such skip window can be
done at baseband and it would require a memory for only 4 WiFi samples. The PA with DPC also
delivers a wider average output power range (12 to 25 dBm) than the case without DPC (21 to 25
Figure 3.20: Measured output spectra and constellation diagrams of the PA under WiFi (top) and WiMAX
(bottom) signals with DPC. At lower power levels, WiFi and WiMAX EVM improve to about -29 dB and
-34 dB respectively.
48
dBm) due to the extra power back-off by turning off sections of the PA, in addition to outphasing
alone.
The PA is also tested with a 16-QAM, 10 MHz bandwidth WiMAX input signal. At 22.7
dBm average output power, the PA demonstrated 8% PAE without DPC and 12% PAE after
DPC is applied. The output spectra and constellations of the PA with DPC under both WiFi
and WiMAX input signals are shown in Fig. 3.20; OFDM power is 24.8 dBm and 22.7 dBm
respectively. Table 3.2 summarizes the performance metrics of recently published watt-level
CMOS PAs. For conventional PAs, the PAE at back-off is significantly reduced compared to
peak PAE. For example, PAE at 10 dB back-off is at least 2.9 times lower than peak PAE. The
proposed PA maintains high back-off PAE due to the transformer on-off switching, achieving a
PAE at 10 dB back-off that is only 1.9 times lower than peak PAE.
3.5 Summary
A fully-integrated outphasing class-D PA was designed in a 45 nm LP digital CMOS process.
A multi-section transformer combiner is utilized to implement dynamic power control. Unit PA
blocks are turned on or off dynamically according to the instantaneous power level, extending
the output power range and enhancing average PAE at back-off. We have described the spectral
bump issue caused by DPC supply ringing transients, which degrades ACPR. To mitigate this
effect, a technique that skips transitions with little impact on PAE enhancement is proposed, and
the effectiveness is experimentally verified.
At 2.4 GHz, the PA achieves 31.5 dBm of peak output power and 27% PAE with a 2.4 V
supply. The PA supports over 86 dB of CW output power range. Under a 64-QAM WiFi modulated signal, the DPC-enabled PA delivers 24.8 dBm of average output power and 16% PAE,
which marks a 33% efficiency enhancement compared to the DPC-disabled mode. DPC provides an efficiency enhancement of 140% at a lower average power of 20.5 dBm. The efficiency
improvement at low power levels makes the proposed PA architecture an attractive candidate for
high-PAPR OFDM applications.
49
CMOS PA
[8]
[6]
[9]
[10]
[18]
This Work
Peak Pout (dBm)
30.1
32
31.5
31
32
31.5
Peak PAE (%)
33
48
25
34.8
15.3
27
PAE (%) at 6 dB back-off
16*
31*
14*
17*
4*
20
PAE (%) at 10 dB back-off
9*
14*
7*
12*
2*
14
Frequency (GHz)
2.4
2.3
2.45
2.5
1.85
2.4
Power Supply (V)
3.3
3.3
3.3
3.3
5.5
2.4
Pout (dBm)
at -25 dB EVM
N/A
26
25.5
21
N/A
24.8
PAE (%)
at -25 dB EVM
N/A
24
16
N/A
N/A
16
PAE (%) at 6 dB
back-off from the
above row
N/A
9.3*
6.5*
N/A
N/A
9.5
Pout (dBm)
at -28 dB EVM
22.7
25
N/A
N/A
N/A
22.7
PAE (%)
at -28 dB EVM
12
21
N/A
N/A
N/A
12
-3 dB BW (GHz)
0.7
> 1.7
0.8
N/A
>1
1.7
Packaged
Yes
No
Yes
Yes
Yes
Yes
Technology (nm)
90
90
65
180
130
45
20 MHz
64-QAM
WiFi
10 MHz
16-QAM
WiMAX
* Estimated from figures.
Table 3.2: Performance comparison of watt level CMOS PAs in the cellular band.
50
Chapter 4
A Millimeter-wave Power Amplifier in SiGe
The second focus of this thesis is the design of high-efficiency silicon power amplifiers in the
millimeter-wave regime. In order to optimize performance in a frequency range where gain is
limited, the design goals for each stage in a multi-stage PA need to be carefully prioritized.
To demonstrate this design philosophy, a fully-integrated 45 GHz class-B power amplifier is
implemented in a 0.13 µm SiGe BiCMOS technology. The SiGe PA is optimized for PAE, both at
its nominal supply voltage and at reduced supply voltages to support supply scaling architectures.
High efficiency is obtained by adopting a two stage topology that combines a high gain, cascode
class-A driver and a high-efficiency class-B output stage. This two-stage approach allows the
careful partitioning of gain and efficiency of each stage to achieve an overall high peak PAE.
4.1 Introduction
The good performance of silicon based power amplifiers in the cellular band does not translate
well into the millimeter-wave region. Even with the high performance SiGe HBT devices, fullyintegrated PAs have yet to simultaneously achieve a greater than 15 dBm output power and PAE
of above 20%. Achieving simultaneous high output power and high efficiency with a non-power
combined PA is an important first step in implementing PAs that employ power combining.
Without the high efficiency of the unit PAs, the inevitable loss caused by the combiner would
further degrade efficiency, making the overall efficiency too low for the PA to be practical. In
this chapter, we investigate the use of multi-stage, non-power combined topologies that optimize
PAE while still maintaining high output power. The result will serve as a building block in a
51
80
Class-AB
Class-B
Class-E
10
Gain (dB)
Collector Efficiency (%)
12
8
6
4
2
Class-AB
Class-B
Class-E
70
60
50
40
30
20
10
0
0
-10
0
10
-10
20
0
20
Output Power (dBm)
Input Power (dBm)
20
60
Class-AB
Class-B
Class-E
16
Class-AB
Class-B
Class-E
50
PAE (%)
Output Power (dBm)
10
12
8
4
40
30
20
10
0
0
-10
0
10
20
-10
Input Power (dBm)
0
10
20
Output Power (dBm)
Figure 4.1: Comparison of the simulated gain, output power, collector efficiency and PAE of different
classes of SiGe PAs.
power combined PA that is discussed in Chapter 5.
4.2 Comparison of Power Amplifier Topologies
To optimize PA efficiency, we first investigate the performance of various PA topologies using
device models from a 0.13 µm BiCMOS technology. This process features SiGe HBTs with 200
GHz ft . Although these devices exhibit reasonable gain at 45 GHz, common practice is to adopt
class-A or class-AB biasing to further maximize power gain at the expense of PA efficiency [49–
52]. If a switch-mode PA topology is adopted, e.g. class-E [53, 54], the collector efficiency at the
output stage may improve, but the overall PAE could potentially be degraded due to the reduced
gain of the switching output stage and the increased driver stage power consumption.
The trade-off between gain, output power, and efficiency is visualized in Fig. 4.1, which is
obtained from simulating single-stage class-AB, class-B and class-E PAs at 45GHz with the 200
52
VCC
VCC
Bias
Bias
L5
L7
720 pH
270 pH
L4
L6
400 pH
50 Ohm
Input
L1
R1
104 pH
50 Ω
Q2
C3
L2
R2
137 fF
100 pH
16 Ω
C1
C2
306 fF
C5
294 fF
4 x 12μm
2 x 12μm
132 fF
50 Ohm
Output
380 pH
2 x 12μm
C4
Q1
92 fF
L3
91 pH
Q3
Figure 4.2: Circuit diagram of the 2-stage class-B PA.
GHz ft HBT models and ideal passive matching components. The peak gain and output power
of class-AB and class-B PAs are comparable, while the class-E PA achieves a similar output
power level only at a much larger input drive, resulting in a lower gain. The collector efficiency,
defined as η =
OutputP ower
,
DCP owerConsumption
does not take into account the power gain of the PA, in which
case the class-E PA outperforms the other two classes. The lower power gain of the class-E PA
partially negates the advantage of its higher collector efficiency, resulting in a greatly reduced
PAE near peak output power. On the other hand, the class-B PA offers good collector efficiency
and it maintains a higher gain when the PA compresses. These characteristics make a class-B
stage an ideal candidate as an output stage of a SiGe PA at 45GHz.
4.3 Power Amplifier Design
Based on the observations from the previous section, we adopted a 2-stage topology, as shown
in Fig. 4.2. The driver is a cascode stage biased near class-A to maximize gain and linearity. The
cascode driver also improves overall stability owing to its higher reverse isolation. It is important
to size the driver device such that it delivers sufficient output power to drive the following stage
into saturation. The driver stage transistors are sized to 2x12 µm to ensure that the peak output
power capability is not limited by the driver, whereas the output stage transistor is sized to 4x12
µm. The output stage uses a common-emitter device, Q3, instead of a cascode stage. A commonemitter stage allows the PA to maintain good efficiency over a larger output power range while
53
1000
Stability Factor
100
Bias
10
Lb
1
Rb
Simulation w/ Rb
0.1
Simulation w/o Rb
0.01
0
10
20
30
Frequency (GHz)
40
50
(a)
(b)
Figure 4.3: (a) Simulated stability factor with and without Rb . (b) Base bias network with series resistor
Rb .
the supply voltage is varied. With class-B biasing, the current density of Q3 near peak output
power is 8 mA/µm2 - slightly lower than the peak-ft bias condition.
It should be noted that the breakdown voltages of this process are BVCEO = 1.77V and
BVCBO = 5.5V. A collector voltage larger than BVCEO (but lower than BVCBO) is tolerable
as long as a low resistance path is provided at the device’s base terminal [55]. The resistance
provided to the base of Q3 is lower than approximately 300 Ohms in all frequencies, allowing
the safe use of a supply voltage up to 2.7V [56].
4.3.1
PA Stability
One drawback of using a common-emitter output stage is the potential issue of instability. The
parasitic capacitance of the common-emitter device provides a feedback path for the output signal
to couple back to the base node. Fig. 4.3(a) shows the simulated stability factor of the two-stage
PA. To ensure unconditional stability, i.e. the device is stable under all combinations of port
impedance across all frequency, the stability factor, as defined by
K=
1 − |S11 |2 − |S22 |2 + |S11 S22 − S12 S21 |2
,
2|S12 S21 |
54
(4.1)
(a)
(b)
Figure 4.4: (a) Top view and (b) 45-degree view of the unit transistor layout.
should be greater than unity across all frequency as well. Potential instability is identified near 16
GHz, which is the frequency of a secondary oscillation associated with the inter-stage matching
network. To reduce the quality factor of this secondary oscillation, a small resistor, Rb , is added
in series to the base bias choke inductor (Fig. 4.3). The addition of Rb results in unconditional
stability with negligible performance degradation.
4.3.2
PA Cell Layout
As the frequency of operation rises into the mm-wave regime, device parasitics play an increasingly crucial rule in determining the performance of a PA. While ft of a transistor depends largely
on technology parameters, the maximum frequency of oscillation, fmax , depends heavily on device layout parasitics such as trace capacitance and resistance, and it directly affects the usable
power gain of the device at mm-wave frequencies. To maximize fmax , all of the transistors are
laid-out in a C-B-E-B-C configuration (single emitter finger sandwiched between dual base and
collector fingers, as shown in Fig. 4.4) for improved frequency response as compared to a C-B-E
configuration.
55
(a)
(b)
Figure 4.5: (a) Top view and (b) 45-degree view of the PA output stage layout. The PA output stage
contains 4 unit transistor cells.
To withstand the peak DC collector current of up to 70 mA and reduce the risk of electromigration failure, multiple metal layers are required to make the transistor terminal connections. A
“tapered” layout is adopted to minimize collector-emitter parasitic capacitance and still comply
with the foundry-recommended electromigration rule. As shown in Fig. 4.4(b), the metal stack
traces to each transistor terminal is progressively wider and taller towards the direction of current flow. The emitter and collector currents are directed to opposite sides of the transistor. As
a result, the side-wall capacitance between adjacent fingers is minimized. (Note that in Fig. 4.4,
the thick M6 and M7 metal layers are not shown.) The layout of the PA output stage is shown
in Fig. 4.5. A binary tree structure distributes input base current among 4 unit transistors. A
ground plane in close proximity to the PA cell collects the emitter current to minimize ground
inductance.
4.3.3
Passive Devices and Matching Networks
The 2-stage PA features fully integrated input- and output-matching passive networks, both taking into account the parasitics of the probe pads. To minimize power dissipation, slab inductors,
56
Figure 4.6: 3-D model of the implemented on-chip slab inductor (left) and the spiral inductor (right).
implemented on a 4 µm-thick top aluminum layer, are used in the matching network (Fig. 4.2,
L1-L3). Instead of using a patterned metal ground shield, eddy current is reduced by etching deep
trench patterns in the substrate beneath the slab inductors. Return current of these inductors flow
partially through the substrate beneath them and through the ground metal layers farther away.
A 3-D model of the slab inductor is shown in Fig. 4.6. The quality factor of these inductors at
45 GHz is larger than 20. The inductances used in the matching networks are approximately 100
pH. The use of slab inductors allows a very compact die size of only 0.2 mm2 (Fig. 4.7).
The four RF chokes, namely L4-L7, are implemented as spiral inductors with inductance
ranging from 270 pH to 700 pH. As shown in the chip micrograph in Fig. 4.7, these choke inductors are placed in close proximity to each other. Simulation shows that the mutual coupling of
these inductors helps to slightly improve the overall PA performance with no penalty in stability,
as long as the equivalent coupling coefficient between neighboring inductors is lower than 0.3.
Fig. 4.6 shows a 3D model of the spiral inductor with M1 patterned ground shield. The quality factor of the spiral inductors at 45GHz ranges from 10 to 25. Metal-insulator-metal (MIM)
capacitors are used for DC blocking, as well as for the RF matching networks.
The optimal load impedances of the two stages are determined by large-signal load pull
57
0.65 mm
0.31 mm
Input
match
Q2 Inter-stage Q3 Output
match
match
Q1
Figure 4.7: Die micrograph of the class-B PA. Total area including pads is 0.2 mm2 .
Driver Stage Gain
Output Stage Pout
Output Stage Efficiency
Realized load
impedance
Gain contours, 1dB step
(a)
Pout contours, 1dB step
Efficiency contours
10% step
(b)
(c)
Figure 4.8: Simulated load pull contours of the driver- and output-stage.
simulations. We chose a load impedance that optimizes gain of the cascode driver stage, while
the output stage load impedance is chosen to optimize efficiency. As shown in Fig. 4.8, the
realized load impedances for the driver stage and output stage are not located on the exact contour
peaks. Simple L-match networks are used to implement the necessary impedance transformation
to minimize insertion loss. However, this loss is not considered in the load pull simulation, since
a lossless tuning block is used. The matching network is optimized with the load pull contour
58
Agilent E8364A
Network Analyzer
Cascade i50
GSG Probes
DUT
(a)
Agilent N1913A
Power Meter
Agilent E8364A
Network Analyzer
Driver
Amplifier
Attenuator
Agilent N8487A
Power Sensor
DUT
(b)
Figure 4.9: (a) Small signal measurement setup. (b) Large signal CW measurement setup.
peak as a starting point, and the realized load impedance is the result of this optimization which
yields a global maximum efficiency.
4.4 Experimental Results
On-die probe measurements are performed to characterize the power amplifier. The setup for
small-signal and large-signal continuous-wave (CW) measurements are shown in Fig. 4.9. A
50 GHz vector network analyzer (VNA) is used for small signal S-parameter measurement. To
measure the large-signal CW characteristics of the PA, the VNA in conjunction with an external
driver amplifier is used as a CW signal source to generate CW power of up to 5 dBm. The output
signal of the PA is attenuated and measured with a power meter. Power loss of all components
are de-embedded, and the measurement system is calibrated up to the probe tips. RF probe pads
sized at 45 µm by 35 µm are designed to be part of the matching network, hence they are not
de-embedded from measurement.
Figure 4.10(a) shows the measured small signal S-parameters of the PA. Although peak gain
at small signal levels is lower than at large signal levels due to the biasing of the class-B stage, a
59
35
20
Gain
S21
30
15
0
S11
-10
-20
S12
-30
-40
25
10
Pout
20
5
PAE
0
15
-5
10
5
-10
-50
0
-15
40
42
44
46
Frequency (GHz)
48
50
PAE (%)
10
Pout (dBm), Gain (dB)
Measured S Parameters (dB)
20
-20
(a)
-10
0
Input Power (dBm)
10
(b)
Figure 4.10: (a) Measured small signal S-parameters. (b) Measured large signal characteristics at 45
GHz.
30
250
VCC = 2.5V
25
PDC_output_stg
200
VCC = 2.1V
PDC_driver_stg
VCC = 1.7V
20
150
PAE (%)
Power Consumption (mW)
PDC_total
100
VCC = 1.3V
15
10
50
5
0
0
-20
-10
0
Input Power (dBm)
-10
10
(a)
0
10
Output Power (dBm)
20
(b)
Figure 4.11: (a) Power consumption vs. input power at 45GHz. (b) Measured PAE vs. output power
with different supply voltages.
significant gain (S21) of 12.7 dB centered at 45.2 GHz is measured. The -3dB small signal gain
bandwidth is about 4 GHz. The reverse isolation (S12) of the PA is better than 30 dB across all
frequency.
60
4.4.1
Large Signal Measurement with 2.5V Supply
The large signal characteristics of the PA at 45 GHz with a 2.5V supply are shown in Fig. 4.10(b).
The large signal gain of the PA reaches a peak value of 16.6 dB at -12 dBm input power, and a
1-dB gain flatness is maintained over a 14 dB output power range. The -1 dB compressed output
power is 15.9 dBm, and the output power saturates at 17.5 dBm. Peak PAE of 26% is reached
at 16.6 dBm output power. As shown in Fig. 4.11(a), power consumption of the class-B output
stage scales roughly with input power, and it consumes very little power at low input power
levels. The class-AB driver stage has near-constant power consumption at low power levels.
Total power consumption at peak PAE is 210 mW, and it reduces to 31 mW at idle-state.
4.4.2
Back-off Efficiency Enhancement with Scaled Supply
One of the potential applications of this PA is in an asymmetric multi-level outphasing (AMO)
transmitter system [57]. Specifically, multiple unit PAs operated in a saturated, peak efficiency
condition, are outphase-combined to generate an overall linear PA gain with maximum efficiency. Furthermore, the switching of supply voltages provides an extra level of power control in
addition to outphasing. As a result, the system efficiency at back-off power levels is enhanced.
As mentioned earlier, high data rate OFDM radio systems often require the transmission of high
peak-to-average ratio signals, therefore, efficiency enhancement through supply scaling becomes
a very attractive feature in such radio systems.
To verify the feasibility of scaled-supply operation, the PA is tested with externally varied
supply voltages ranging from 1.3V to 2.5V. In these experiments, only the supply of the output
stage is varied. As shown in Fig. 4.11(b), peak PAE of the PA is greater than 20% throughout
a 6.5 dB output power range by supply variation (1.3-2.5 V). As described previously, since the
base of the output stage transistor is presented with a low impedance, the PA can operate beyond the open-base breakdown voltage of 1.77V. The PA is stress-tested with a 48-hr continuous
operation at peak output power. As shown in Fig. 4.12, a 0.6 dB degradation of output power
was measured over the 48-hr period. However, output power is restored after a brief shut-down
61
17.5
Run 1
17.4
Output Power (dBm)
Run 2
17.3
17.2
17.1
17
16.9
16.8
16.7
0
10
20
30
40
Time from Startup (Hr)
Figure 4.12: Output power versus continuous operation time.
and restart, suggesting that the performance degradation is not permanent and possibly caused
by environmental variables, such as local temperature variations and the stability of the power
supplies.
Table 4.1 compares the performance of fully-integrated SiGe HTB power amplifiers with
greater than 24 GHz operation frequency [53, 54, 58, 59]. The PA presented in this work compares favorably to other mm-wave SiGe PAs. While [58] achieved a peak PAE of 30.8%, it is
available at an output power of 13.3 dBm compared to 26% PAE at 16.6 dBm of this work. The
proposed PA also occupies the smallest die area, which is an important feature as it can be easily
integrated into a power-combined PA as a unit PA cell (Chapter 5).
4.5 Summary
A 45 GHz class-B power amplifier implemented in 0.13 µm SiGe is presented in this chapter.
The single-ended 2-stage PA delivers 17.5 dBm saturated output power, and it achieves 26% PAE
at 16.6 dBm output power. The high PAE and small area, together with the ability to maintain
PAE with scaled supply voltages, makes the presented PA an excellent building block for supplyscaled transmitter systems.
62
Reference
Device ft
(GHz)
Freq.
(GHz)
Supply
(V)
Gain
(dB)
Psat
(dBm)
Peak
PAE (%)
Area
(mm2)
H. Debag, BCTM 2011
200
45
2.4
7.8
14.8
30.8
0.27
N. Kalantary, MWCL 2010
200
45
1.2
6
11.3
18
0.8
This Work
200
45
2.5
17
17.5
26
0.2
A. Valdes-Garcia, ASSCC 2006
200
58
1.2
4.2
11.5
20.9
0.98
V. Do, MWCL 2008
200
60
3.3
19
15.5
20
0.8
Table 4.1: Performance comparison for fully-integrated SiGe HBT power amplifiers with larger than 24
GHz carrier frequency.
63
Chapter 5
A Millimeter-wave 16-way Power Amplifier in SiGe
A 16-way power combined SiGe PA is implemented in this work, in which 16 unit PAs whose
design is similar to the non-combined version reported in Chapter 4 operate in parallel. The unit
PAs are combined using a transmission-line based zero-degree combiner that offers low insertion
loss and flexibility in impedance transformation. The proposed PA topology in conjunction with
the zero-degree combiner make the goal of achieving watt-level output power in the millimeterwave regime closer to realization as compared to conventional topologies.
5.1 Introduction
Silicon power amplifiers in the cellular band can achieve high output power (e.g. > 1 W) with
aggressive power combining, as have been demonstrated with the transformer-combined outphasing PA in Chapter 3. Unfortunately, this strategy does not work well once the frequency
is increased up to the millimeter-wave regime (i.e. above 30 GHz). The highest output power
achieved by a millimeter-wave PA in silicon was 23 dBm (0.2 W) with the use of an integrated
distributed-active transformer combiner [60]. However, insertion loss of the transformer combiner is high due to the conductive silicon substrate and lack of shielding, resulting in a peak
PAE of 6%. Alternatively, a corporate combiner with Wilkinson combiners as building blocks
can be used to generate higher output power. A Wilkinson combiner typically has lower loss
compared to an on-chip transformer combiner at mm-wave frequencies. Nonetheless, the total
insertion loss of a corporate combiner scales linearly with the depth of the combiner tree, defined as Depth = log2(N ), where N is the total number of unit PAs. In addition, the length of
64
Zin3
λ
4
Ltotal
λ
λ
= 3⋅
4
Ltotal = L1 + L2 + L3
Zin2
4
Zin1
λ
4
ZL
ZL
L1, Z01
L2, Z02
L3, Z03
Figure 5.1: An 8-way corporate combiner (left) and an 8-way zero-degree combiner (right).
the corporate combiner is approximately log2(N ) times the length of a quarter wavelength. For
example, as shown in Fig. 5.1, the signal in an 8-way corporate combiner travels an electrical
length of three quarter-wavelength segments (i.e. Ltotal = 0.75λ). The PA becomes exceedingly
inefficient as N increases, whereas the larger combiner dimensions often make this solution costprohibitive.
5.2 16-Way Zero-Degree Power Combiner
In this work, a transmission-line based zero-degree combiner is utilized. The main idea behind
the zero-degree combiner is that since all unit PAs are driven in-phase (i.e. a zero-degree phase
difference), the isolation between combiner input ports is less critical and therefore can be traded
65
for an overall lower insertion loss. A Wilkinson combiner achieves port isolation through the
use of quarter-wavelength transmission line segments. Without the need of a high level of port
isolation, quarter-wavelength segments are no longer necessary and as a result the length of
each combining arm can be reduced to minimize loss. An important feature of the zero-degree
combiner is its useful ability to perform impedance transformation. The impedance looking into
a transmission line with length l and characteristics impedance Z0 is expressed as
Zin = Z0
ZL + jZ0 tan(βl)
,
Z0 + jZL tan(βl)
where ZL is the load impedance at the far end of the transmission line, β =
(5.1)
2π
λ
is the wave
number. In the case where an N-way zero-degree combiner with log2(N ) level of branches, the
input impedance seen by the PA can be found by iteratively applying the following equation:
Zin,i+1 = Z0,i
2Zin,i + jZ0,i tan(βi li )
.
Z0,i + j2Zin,i tan(βi li )
(5.2)
An arbitrary Zin,i can be achieved if neither Z0 , i nor l, i is physically constrained. In reality,
Z0 is limited by process parameters, such as metal and dielectric thicknesses, as well as restrictions on maximum or minimum trace widths. Segment length l is usually constrained by the
minimum allowable pitch of unit PAs to be combined. To understand how these constraints limit
the achievable combiner input impedance, Zin of an 8-way zero-degree combiner is calculated
with the following parameters:
• RL = 50 Ω
• Transmission line type: microstrip line
• Signal to ground spacing: 9.25 µm
• Relative dielectric constant ǫr = 3.9
• Signal line width varied from 4 µm to 60 µm
66
Ltotal = 0.2 λ
Ltotal = 0.3 λ
+j1.0
+j1.0
−j5.0
−j
−j0.2
−j0.2
−j2.0
−j0.5
−j2.0
−j0.5
−j1.0
−j1.0
5.0
5.
0
2.0
2.
0
1.0
1.
0
0.0
−j5.0
+j5.0
+j5.
+j0.2
2
0.
5
0.5
5.0
0
2.0
1.0
1.
0
0.
5
0.5
5.0
2.0
1.0
0.5
0.2
0.0
+j2.0
+j0.5
+j5.0
0.2
0.
2
+j5.0 +j0.2
+j0.2
0.0
+j1.0
+j2.0
+j0.5
0.2
2
+j2.0
+j0.5
Ltotal = 0.5 λ
−j5.0
−j5.
2
−j0.2
−j2.0
−j0.5
−j1.0
Figure 5.2: Realizable input impedances of an 8-way zero-degree combiner with maximum total branch
length (Ltotal ) equal to (a) 0.2λ, (b) 0.3λ, and (c) 0.5λ.
• Ltotal = L1 + L2 + L3 :
(a) 0.03λ ≤ Ltotal ≤ 0.2λ
(b) 0.03λ ≤ Ltotal ≤ 0.3λ
(c) 0.03λ ≤ Ltotal ≤ 0.5λ
Figure 5.2 shows all possible values of Zin plotted on the Smith chart, given the above constraints. As Ltotal increases, the range of realizable input impedance also becomes larger. In a
sense, the combiner branch length “sweeps” the phase of Zin , whereas changing the characteristic
impedance of the combiner branches moves Zin radially on the Smith chart. With Ltotal = 0.5λ,
almost the entire useful region on the Smith chart is covered. A PA cell would typically require
an optimal load impedance with a real part of around 3 to 20 Ω and a small inductive component.
Setting Ltotal to a value slightly greater than a quarter wavelength is usually sufficient to satisfy
this requirement of impedance transformation.
In addition to providing a wide range of input impedances, the zero-degree combiner also
exhibits low insertion loss compared to a corporate combiner. It is useful to quantify the insertion loss of the combiner with regard to the achieved input impedance, as the later is usually a
critical design variable while insertion loss is to be minimized. In the following discussion, we
will assume that the combiner is implemented with microstrip line segments, and the previously
67
listed design constraints also apply. Generally speaking, the dominating loss sources of a transmission line include the conductor loss, αc , and the dielectric loss, αd . At high frequencies, αc
is potentially large due to skin effect. We find the value of αc by writing the equivalent sheet
resistance due to skin effect as
RSH =
r
πf µ
,
σ
(5.3)
where f is frequency, µ and σ are the permeability and conductivity of the conductor. It can
be shown that the conductor loss of a microstrip line can be approximated by the following
expression
αc = 8.686
RSH
2W Z0
(dB/m),
(5.4)
where W is the width of the signal conductor, and Z0 is the characteristic impedance of the
transmission line formed by the signal conductor and ground conductor.
The dielectric loss of the microstrip line is related to the dielectric loss tangent, tan δ, the
effective transmission line capacitance per unit length, C ′ , as well as f and Z0 :
αd = 8.686πC ′ Z0 tan δ
(dB/m).
(5.5)
C ′ is function of Z0 and the phase velocity (vp ) of the transmission line, written as
p
kef f
1
C =
,
=
Z0 vp
Z0 c
′
(5.6)
where kef f is the effective dielectric constant of the transmission line, c is the speed of light
in vacuum. Finally, we list without proof the characteristic impedance of a microstrip line as
follows:


120π


,


2
W
W
p
+ 1.393 + ln
+ 1.44
kef f
Z0 =
H
3
H



60
H
W


,
ln 8 + 0.25
p
W
H
kef f
68
W
≥1
H
(5.7)
W
<1
H
whereas the effective dielectric constant is written as
kef f

−0.5
H
ǫr + 1 ǫr − 1



1 + 12
,
 2 + 2
W
"
−0.5
2 #
=
ǫ
+
1
H
W
ǫ
−
1

r
r


.
1 + 12
+ 0.04 1 −
 2 + 2
W
H
W
≥1
H
W
<1
H
(5.8)
Using these equations, we can calculate the total insertion loss of the combiner by adding αc
and αd for each transmission line segment and multiply the result by the segment length. We
again use a microstrip line configuration as stated previously, and assume that tan σ = 0.001,
µ = 1.26 × 10−6 H/m, and σ = 5.96 × 107 S/m. The insertion loss of a 8-way zero-degree
combiner is plotted against all realizable input impedances on a Smith chart, as shown in Fig. 5.3.
Each data point is also decomposed into the phase and magnitude components of the equivalent
input reflection coefficient (Γin ) for better clarity. In this particular example, the zero-degree
combiner is able to very efficiently provide a capacitive Zin , while an inductive Zin would require
long segment lengths with more loss. Nonetheless, the load impedance required by typical PAs
(i.e. the region on the upper left side of the Smith chart) can be realized with a total insertion
loss of less than 0.6 dB.
As a comparison, the input impedance and insertion loss of an 8-way corporate combiner is
calculated as well. The design equations for the corporate combiner are identical to the zerodegree combiner except that the length of each transmission line segment is fixed at λ/4. As
shown in Fig. 5.4, the corporate combiner is only able to achieve purely real input impedances,
and the minimum possible insertion loss is roughly 1 dB. In order to present the PA with an
optimum load impedance that often contains an imaginary component, an additional matching
network may be required which exacerbates overall loss and reduces efficiency. The zero-degree
combiner is clearly more versatile and more efficient in this regard. The ability to provide both
real and imaginary impedance components to the PA is a useful feature of the zero-degree combiner, as this removes the need of an additional impedance transformation network between the
PA and the combiner, further reducing power loss.
69
Insertion Loss (dB)
+j1.0
+j2.0
+j0.5
1.88
1.8
1.8
1.6
1.6
1.4
1.4
1.2
1.2
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
1.56
+j0.2
2
Insertion Loss (dB)
+j5.0
+j
5.0
5.
0
2.
0
2.0
1.
0
1.0
0.
5
0.5
0.0
0.2
0.
2
1.25
0.94
0.63 −j0.2
2
−j5.0
−j
0.31
−j2.0
−j0.5
0
−200
−j1.0
−100
0
100
phase( Γin) (degrees)
200
0
0
0.5
mag( Γin)
1
Figure 5.3: Insertion loss verses magnitude and phase of all possible Γin of an 8-way zero-degree combiner (right), and the same values color-coded and plotted on a Smith chart (left).
Insertion Loss (dB)
+j1.0
3
2.5
2.5
2
2
1.5
1.5
1
1
+j2.0
+j0.5
2.81
3
2.34
Insertion Loss (dB)
+j5.0
+j0.2
5.
0
5.0
2.0
2.
1.0
1.
0.
0.5
0.0
0.2
0.
1.88
1.41
0.94 −j0.2
−j5.0
0.47
−j2.0
−j0.5
0.5
−200
−j1.0
−100
0
100
phase( Γin) (degrees)
200
0.5
0
0.5
mag( Γin)
Figure 5.4: Insertion loss verses magnitude and phase of all possible Γin of an 8-way corporate combiner
(right), and the same values color-coded and plotted on a Smith chart (left).
We have designed a fully-integrated 16-way zero-degree combiner and achieved a simulated
insertion loss of 0.48 dB (i.e. 90% combiner efficiency). The combiner is constructed with
microstrip line segments with a cross section as shown in Fig. 5.5. The characteristics impedance
70
1
PA1
PA9
T-Line
Cross-Section
4 µm Al
9.25 µm Oxide
PA2
PA10
0.55 µm Cu Ground Plane
2.95 µm Oxide
PA3
PA11
Si Substrate
OUT
PA4
PA5
PA6
PA7
PA8
Combiner Loss Comparison
PA12
PA13
0-degree
Combiner
Corporate
Combiner
Ltotal
1.34 mm (0.4λ)
3.29 mm (1λ)
Insertion Loss
0.48 dB
1.9 dB
Efficiency
90%
65%
PA14
PA15
PA16
Combiner Port Isolation Comparison
Isolation
No Riso
Riso = 10Ω
Corporate
Combiner
S12
-5 dB
-10 dB
-19 dB
S13
-10 dB
-16 dB
-25 dB
S15
-21 dB
-32 dB
-34 dB
S19
-24 dB
-24 dB
-37 dB
Figure 5.5: Layout of the integrated 16-way zero-degree combiner (left), transmission line cross section
(top right) and performance comparisons (bottom right).
of each combiner stage is selected to achieve an input impedance of 21 + j4.6, which is the
optimum load impedance presented to the designed unit PA. The total branch length Ltotal is
1.34 mm (i.e. 0.4λ at 45 GHz), which is constrained primarily by the unit PA pitch of 215 µm.
By contrast, a corporate combiner with 4 levels of Wilkinson 2-way combiners and with a similar
t-line cross section would require an Ltotal of 3.29 mm (1λ) and would result in an insertion loss
of 1.9 dB – 3.4x lossier than the zero-degree counterpart. This insertion loss does not take
into account the additional loss of the matching network required to provide the inductive load
impedance component.
71
Isolation between the input ports of the combiner minimizes the PA performance degradation
if mismatch between unit PA cells exists. The source of the mismatch could be process variation
or imperfect symmetry of circuit and layout. As shown in the comparison table in Fig. 5.5, the
port isolation of a corporate combiner is very good, with a value of -19 dB between adjacent
ports. Isolation of adjacent ports in the designed zero-degree combiner is -5 dB. In general, the
inferior port isolation of the zero-degree combiner does not pose a serious threat to performance
nor reliability. Nonetheless, with the addition of isolation resistors (as shown schematically in
Fig. 5.1), port isolation can be improved to better than -10 dB and the PA would benefit from
the reduced impact of PA mismatch. Simulation shows that with the added isolation resistor, PA
mean output power degrades by less than 3% under typical mismatch and process variation.
5.3 Circuit Implementation
The 16-way SiGe PA is designed in the same process technology as the 2-stage class-B PA
discussed in Chapter 4. Each of the 16 unit PAs that operate in parallel is similar in structure
to the 2-stage class-B PA. Fig. 5.6 shows the schematic diagram of the unit PA cells used in the
16-way PA. Gain of the unit PA peaks at about 15 dB before it compresses. Due to the class-B
biased output stage, gain is also lower at lower input power levels. To provide sufficient overall
gain to the 16-way PA, additional pre-driver stages are used. Specifically, the input signals are
fed into two pre-driver cells, each followed by an 8-way power splitter which connects to 8 unit
VCC
VCC
Bias
Bias
L5
L7
720 pH
270 pH
L4
L6
400 pH
From
Splitter
380 pH
2 x 12μm
L1
R1
90 pH
50 Ω
Q2
C3
L2
R2
172 fF
100 pH
16 Ω
C1
C2
336 fF
C5
367 fF
4 x 12μm
2 x 12μm
92 fF
To
Combiner
C4
Q1
92 fF
Q3
Figure 5.6: Schematic diagram of the unit PA used in the 16-way combined PA.
72
Bias
L5
Bias
L2
272 pH
L4
L1
272 pH
1 x 10μm
R1
C2
L7
272 pH
1 x 16μm
484 fF
R2
Q2
1 x 10μm
C1
Q1
272 pH
C4
2 x 16μm
160 fF
R4
Q4
50 Ω
50 Ω
185 fF
L8
Bias
793 pH
793 pH
Input
Feed
VCC
VCC
VCC
L3
C3
R3
115 fF
107 Ω
Q3
C6
306 fF
Q6
50 Ω
2 x 16μm
1 x 16μm
170 pH
To
Splitter
L6
278 pH
C5
R5
115 fF
156 Ω
Q5
Figure 5.7: Schematic diagram of the pre-driver used in the 16-way combined PA.
PAs. Each pre-driver cell consists of a cascade of 3 cascode stages, as shown in Fig. 5.7. The
biasing and matching network used in the pre-drivers have a similar style to those in the unit
PAs. Spiral inductors are used as biasing RF chokes, and the inductors in the matching networks
are implemented as slab inductors to save area. To ensure stability, a parallel combination of
a capacitor and a resistor is connected in series before the base of Q3 and Q5 (Fig. 5.7) to
introduce additional attenuation at lower frequencies. The 2 pre-driver cells used in the 16-way
PA together consumes about 183 mW of power, and a peak pre-driver gain of approximately 30
dB is achieved.
The die photograph is shown in Fig. 5.8. Total active area of the 16-way PA measures 2.1
mm by 2.1 mm. The small size of the unit PAs and the compact zero-degree combiner layout
allow a relatively small die area to be achieved. The PA die is directly attached and wire-bonded
onto an evaluation PCB. Supply and bias voltages are fed through the bond-wires, whereas the
input and output pads of the PA are accessed using RF probes.
5.4 Simulation Results
Simulation results of the 16-way SiGe PA is discussed in this section. The simulated circuit
includes realistic models of all inductor, capacitor, and transmission line elements as well as I/O
pads, and the simulations are performed in Cadence Spectre environment. Fig.5.9(a) shows the
continuous wave PAE, output power, and gain of the PA versus input power at 45 GHz. Peak PAE
73
Power Combiner
Unit PA
Power
Splitter
Output
Pre-driver
Input Pads
Figure 5.8: Die micrograph of the 16-way SiGe PA. Total active area measures 2.1 mm by 2.1 mm (4.41
mm2 ).
5
Power Consumption (W)
PAE (%), Pout (dBm), Gain (dB)
60
50
40
30
20
Gain
Pout
PAE
10
0
4
3
2
1
0
-30
-25
-20
Pin (dBm)
-15
-10
0
(a)
0.5
1
Output Power (W)
1.5
(b)
Figure 5.9: (a) Simulated CW characteristics versus input power at 45 GHz. (b) Simulated DC power
consumption versus output power at 45 GHz.
of 30.5% is reached at a saturated output power of 31.5 dBm (1.42 W). Thanks to the multiple
stages of drivers, a peak gain of 50 dB is achieved right before output power saturates. As stated
earlier, the shape of the gain characteristics is a results of the class-B biased output stage, whose
74
45
PAE (%), Pout (dBm), Gain (dB)
PAE (%), Pout (dBm), Gain (dB)
45
40
35
30
25
20
15
Gain
Pout
PAE
10
5
0
40
35
30
25
20
15
Gain
Pout
PAE
10
5
0
1
1.5
2
VCC (V)
2.5
3
40
(a)
42
44
46
Frequency (GHz)
48
50
(b)
Figure 5.10: (a) Simulated CW characteristics versus supply voltage at 45 GHz. (b) Simulated CW
characteristics versus operation frequency.
gain decreases as input power becomes low. DC power consumption of the PA is plotted against
output power in Fig. 5.9(b), which is close to a linear relation. 4.64 W of power is consumed by
the PA at the peak output level.
The performance of the PA under varying supply voltage at 45 GHz operation frequency
is shown in Fig. 5.10(a). As VCC is decreased from a maximum value of 3V, PAE also goes
down, but at a mild rate. In fact, the achieved PAE at a given output back-off through supply
scaling is considerably better than that of the same output back-off through input power variation.
For example, at an output power of 25 dBm, PAE is approximately 21% if supply scaling is
used to achieve the back-off. If the same back-off is obtained by lowering input power while
maintaining the same VCC of 2.7 V, PAE is approximately 15%. This result suggests that the use
of supply voltage scaling is potentially beneficial for back-off efficiency enhancement. Results of
a frequency sweep is shown in Fig. 5.10(b). A -3 dB output power bandwidth of approximately
7 GHz is achieved. Within the -3 dB bandwidth, the PA exhibits greater than 20% PAE.
5.5 Measurement Results
The 16-way SiGe PA is directly attached onto an FR4 printed circuit board for measurement.
The DC supply and bias voltages are wire-bonded from the board to the on-chip bond pads. This
75
Multi-contact
Needle Probe
Attenuator
RF Probe
Agilent N8487A
Power Sensor
DUT
Agilent N1913A
Power Meter
PCB Layout
Ribbon
Cables
Power
Splitter
Agilent E8364A
Network Analyzer
VCC
VCC
Driver
Amplif ier
Bias Board
Power
Supplies
Vbias
Figure 5.11: Measurement setup of the 16-way SiGe PA.
chip-on-board assembly configuration was selected instead of using multi-contact probes due to
the large number of feed points required. The measurement setup is shown in Fig. 5.11. All the
DC supply and bias voltages are generated on a separate bias board. The input signal is generated
using a 50 GHz vector network analyzer as a CW signal source. An external driver amplifier is
used to increase the CW signal power up to 5 dBm, which is then connected to a Wilkinson
power divider to generate two in-phase CW signals. Both the input and output pads of the PA
are accessed with RF probes. The output power of the PA is measured with a power meter.
One design flaw prevented the PA from working as predicted. In particular, an on-chip supply
switching network that switches the supply voltage of the PA among different voltage levels was
not properly designed, with larger than intended series resistance. The extra resistance in the
supply switches creates feedback from the PA output stage to the drivers, causing the PA to
oscillate at a frequency of around 16 GHz. In order to bypass the on-chip supply network, the
die passivation layer (polyimide) was selectively removed to reveal the top metal supply traces
next to each unit PA. Multi-contact needle probes were then used to access the top level metal
through these passivation windows to provide the supply voltage (see Fig. 5.11).
76
Simulation
Measurement
Simulation
Peak Pout
20.5 dBm
31.5 dBm
19.6 dBm
PDC,total
2.9 W
4.64 W
3.1 W
PDC,drv
0.17 W
0.18 W
0.2 W
PAE
4%
31 %
3%
Lgnd = 2.4 nH
Table 5.1: Comparison of the simulation and measurement results of the 16-way SiGe PA.
The measured CW peak performance of the 16-way SiGe PA is summarized in Table 5.1, as
well as the simulated results for the sake of comparison. Under a 2.7V supply voltage, a peak
output power of 20.5 dBm with 4% peak PAE is measured. The lower measured performance of
the PA is attributed to the series inductance in the multi-contact needle probes. Although the onchip VCC bond pads are heavily decoupled with arrays of decoupling capacitors, the net between
the supply network switches and the choke inductor of each unit PA, i.e. the net accessed by the
needle, is not sufficiently decoupled. The needle inductance, especially in the ground return path,
would cause the emitters of the PA devices to float and carry signal (i.e. a sort of inductive emitter
degeneration). In simulation, an effective ground inductance of 2.4 nH would greatly reduce the
gain of the PA, and the resulting simulated peak output power and PAE are 19.6 dBm and 3%
respectively. These results mirror the findings from the measurement. However, since the supply
voltage of the pre-drivers are not provided through the needle probes but instead from the bias
board through wire-bonds (i.e. they are well decoupled), the measured power consumption of
the pre-drivers is close to simulation.
The measured and simulated performance of the 16-way SiGe PA is compared to the millimeterwave fully-integrated SiGe PAs in the literature in Table 5.2 [51, 52, 60–62]. To date, the highest
output power achieved by a millimeter-wave fully-integrated SiGe PA is 23 dBm at 60 GHz,
with a peak PAE of 6.3% [60]. It achieved a high output power with an on-chip distributedactive transformer, but due to the high loss of the combiner, PAE is not optimized. The proposed
77
PA did not achieve the intended watt-level peak output power due to issues in the supply network. Nonetheless, the cause of the reduced performance is well understood, and the measured
data together with the simulation results are indicative of the potential feasibility of watt-level
power generation at millimeter-wave frequencies.
5.6 Summary
In this chapter, we have introduced and analyzed the zero-degree power combiner. It is implemented in a transmission line tree structure and features low insertion loss and a large degree of
freedom to perform impedance transformation, as compared to a conventional corporate combiner. A 16-way SiGe PA using an on-chip zero-degree combiner is presented, which according
to circuit simulations is able to achieve watt-level output power with greater than 30% peak PAE.
Measured peak output power is 20.5 dBm due to a design issue that led to a larger supply and
ground inductance, reducing the power gain of the PA. Nonetheless, the achieved peak output
power is not far from the state-of-the-art, and a good understanding of the issue is obtained which
indicate the potential feasibility of the proposed topology.
Reference
Freq.
(GHz)
Supply
(V)
Gain
(dB)
Psat
(dBm)
Peak PAE
(%)
Topology
S. Glisic, BCTM 2008
65
4
25
19
10
Differential
U. Pf eif f er, JSSC 2007
60
4
21
23
6.3
DAT
U. Pf eif f er, JSSC 2007
60
4
18
20
12.7
Diff. cascode
A. Hamidian, BCTM 2008
60
3.3
15
18
14
Cascode
This Work, Measured
45
2.7
15.5
20.5
4
Zero-degree
Combiner
This Work, Simulated
45
2.7
38
31.5
31
Zero-degree
Combiner
M. Chang, RFIC 2007
32
1.4
13
19.4
11
Balanced
Table 5.2: Performance comparison for fully-integrated millimeter-wave SiGe power amplifiers with
peak output power near 20 dBm.
78
Chapter 6
A Millimeter-wave 16-way Power Amplifier in SOI CMOS
In the previous chapters, we described numerous design techniques for high performance millimeterwave power amplifiers using SiGe HBT technology. From a cost standpoint, there is an obvious
need to transition these designs into CMOS processes, which offer a much higher level of system integration and affordability. Using a deeply scaled CMOS process, the millimeter-wave
PA designer is faced with many new challenges, and at the same time new opportunities are
also available that are not easily achieved with other technology options. In this chapter, we
describe the challenges and design techniques for implementing a 45 GHz, 16-way combined
power amplifier in a 45nm Silicon-on-Insulator (SOI) CMOS process. A thorough analysis of
the PA topology along with simulation data will be presented. The focus of the design is to
achieve watt-level output power with maximized peak power-added efficiency – a goal not yet
realized experimentally in the literature.
6.1 Class-E PA in Millimeter-wave Frequency
The analysis in Chapter 4 led to a conclusion that a class-B PA topology provides the best combination of gain, output power, and efficiency at 45 GHz with SiGe HBT technology. Class-E
SiGe PAs compared less favorably to class-B due to the lower gain and consequently lower PAE.
A CMOS device, on the other hand, behaves naturally as switches and is more easily matched
to provide adequate gain with a large gate signal swing. The difference is visualized in Fig. 6.1,
where the simulated maximum available gain (GM AX ) at 45 GHz of a 45nm SOI CMOS transistor is compared to a 130nm SiGe HBT device. The HBT provides useful gain only within
79
Maximum Available Gain (dB)
20
45nm SOI CMOS
130nm SiGe HBT
15
10
5
0
-5
0
0.2
0.4
0.6
0.8
1
1.2
Input Voltage (V)
Figure 6.1: Comparison of GM AX dependency on bias voltage of SiGe HBT and SOI CMOS devices.
a small input voltage range, whereas gain of the CMOS transistor remains high as long as it is
on. The latter characteristic better suits in a class-E topology where input voltage drive is large.
This behavior normally diminishes as the operation frequency approaches the millimeter-wave
regime. However, the high cutoff frequency (e.g. > 200 GHz) of deeply scaled CMOS processes
extends the useful frequency range of efficient class-E operation, making the design of a 45 GHz
class-E CMOS PA a feasible goal.
The effect of CMOS scaling on class-E PA drain efficiency (η) can be analytically approximated as [63, 64]
η=
1
,
1 + 7.46ω0 ron−0 cdd−0
(6.1)
where ω0 is the frequency of operation, ron−0 and cdd−0 are the total device resistance and drain
capacitance per unit width. (6.1) does not take into account passive component loss and driver
power consumption; therefore, it only serves as a first-order approximation of class-E drain
efficiency. Using typical ron−0 and cdd−0 values of different CMOS technology nodes, the results
of (6.1) are plotted in Fig. 6.2. As expected, η approaches the theoretical 100% limit at low
frequency. With an ft of higher than 200 GHz, η is still above 50% at an operation frequency of
50 GHz. The prediction of η at even higher frequency becomes too optimistic as the PA driver
80
100
f_t=250GHz (45nm CMOS)
f_t=100GHz (90nm CMOS)
Drain Efficiency (%)
80
f_t=50GHz (180nm CMOS)
60
40
20
0
1
10
100
1000
Frequency (GHz)
Figure 6.2: Theoretical class-E efficiency versus frequency of different technology nodes.
consumes more power to compensate for the decrease in gain. Nonetheless, gain of the 45 nm
SOI CMOS device is sufficient to support high PAE class-E operation at 45 GHz.
Figure 6.3 compares the performance of several PA classes in 45 nm SOI CMOS, with an
operating frequency of 45 GHz. In each of the simulated PAs, the core device is a 300 µm
width transistor with layout parasitics modeled (the class-D PA uses an additional 450 µm width
PMOS transistor). To simplify the comparison, lossless passive elements are used in the output
matching network, whereas the input drive is an ideal voltage source. With a 1.1V supply voltage,
the class-B and class-F PAs deliver similar peak output power of approximately 16 dBm with a
15 Ω load impedance. The class-D PA has limited voltage swing at the drain node as compared to
the other topologies, hence a lower load impedance of approximately 10 Ω is required to generate
comparable peak output power. On the other hand, the class-E PA delvers the highest peak output
power of 17 dBm, even with a reduced supply voltage of 0.9V1 .
The bias levels and drain waveforms of the class-B and class-F PAs are similar, resulting in
similar input-output transfer characteristics and drain efficiency curves, with the class-F drain
efficiency being slightly higher due to the harmonic shaping filters. The class-D PA has the low1
Supply voltage is reduced from the nominal 1.1V to 0.9V to prevent over-stressing the drain node of the class-E
device.
81
18
80
Drain Efficiency (%)
Output Power (dBm)
70
16
14
12
Class-E
Class-D
10
Class-F
60
50
40
30
Class-E
Class-D
20
Class-F
10
Class-B
8
Class-B
0
0
0.5
1
1.5
Input Voltage Swing (V)
0
0.5
1
1.5
Input Voltage Swing (V)
Figure 6.3: Performance comparison of class-B and class-E PAs in 45nm SOI CMOS.
est drain efficiency, as it relies heavily on the transistor switching transition period being a small
fraction of the signal period - a condition that is hard to realize at 45 GHz. Furthermore, class-D
PAs are prone to the effect of parasitic capacitance at the drain node. The presence of the PMOS
device adds even more capacitance that smooths out the switching transition further. Drain parasitic capacitance in a class-E PA is less disruptive, since it can be entirely absorbed into the load
matching network to help shape an efficient non-overlapping waveform. This mechanism works
reasonably well even at 45 GHz, resulting in an exceptional peak drain efficiency.
The advantages of the class-E topology in this technology over other PA classes are as follows: (a) it provides the highest output power under similar gate drive, supply voltage, and load
impedance; and (b) it offers the highest drain efficiency with a simple load network that can
be design to exhibit low insertion loss. One potential drawback is the large voltage swing at
the drain node which could degrade long-term reliability. As described below, using a cascode
topology greatly alleviates stress across devices. In the following section, we identify all the loss
components and additional sources of power consumption in a class-E PA and further optimize
the design to maximize power-added efficiency.
82
6.2 The Cascode Class-E PA
As explained in Chapter 2, the drain voltage of a class-E PA can swing up to as high as 3.5
times the supply voltage. To avoid transistor oxide breakdown and hot-carrier induced long
term degradations, either the supply voltage needs to be reduced or a thick gate-oxide device be
used. Both solutions normally result in a less efficient PA. As shown in Fig. 6.4, the insertion
of a cascode device greatly reduces voltage stress across individual devices. The gate of M2 is
biased at VB with a shunt capacitor. This capacitor forms a voltage divider with the parasitics
capacitances of the two transistors, allowing the large voltage swing at node d2 to partially appear
at node g2. The voltage swing at node g2 reduces the peak value of the drain-gate voltage,
Vdg,max , thereby improving reliability. Since the capacitive divider voltage ratio is determined by
the value of the shunt capacitor, precise partitioning of voltage stress can be achieved to create
margin for an increase of supply voltage. Note that as the voltage swing at node g2 increases, the
overdrive voltage of M2 during M1 on-state is reduced. The resulting increase of on-resistance
of M2 contributes to the switching loss of the device. The sizing of the shunt capacitor poses a
trade-off between device reliability and efficiency.
Figure 6.5 shows simplified schematics of the cascode class-E PA. In addition to the PA
devices, RF choke, and bias elements, the PA is preceded by a driver amplifier and an inter-
Vd
Vds,max
Vd2
Vdg,max Vds,max =
Vdg,max + VTH
VB
= Vdg,max
Vd
Vd2
= 3.56 VDD
Vg2
M2
Vg2
Vd1
M1
M1
Vd1
Figure 6.4: Voltage waveforms of a regular class-E PA versus a cascode class-E PA.
83
Choke
Inductor
VB
Matching
Network
To
combiner
M2
Driver
Matching
Network
M1
Figure 6.5: Simplified schematics of a cascode class-E PA.
stage matching network, and followed by a load matching network that connects to the power
combiner which represents the load of the PA. All of these components introduce power loss
that degrades the total power efficiency of the PA, and the dependency of these loss terms differs
from component to component. We will analyze these loss terms one by one in the following
sections. Strategies to minimize power loss in each component will also be discussed. Some of
the presented equations follow the analyses in reference [63–67].
6.2.1
Transistor Switching Loss
The loss caused by transistor nonidealities plays an important role in determining the total efficiency of the PA. The on-resistance of both the input and cascode devices contribute greatly
to total loss. Furthermore, parasitic capacitances can create additional current paths and cause
loss even when the device is turned off. To gain insight on these mechanisms, we first model
the transistor as an equivalent circuit shown in Fig. 6.6. The input signal is applied on the gate
capacitance, Cgg . When the device is turned on, it is modeled as a parallel combination of the
on-resistance, ron , and the drain capacitance, Cdd . These components can be expressed in terms
84
ron
Cdd
Cgg
Figure 6.6: CMOS device modeled as a simple switch, an input capacitor, and a parallel combination of
a resistor and capacitor at the output.
of the total device width, W :
Cgg = cgg−0 W,
Cdd = cdd−0 W,
ron =
ron−0
,
W
(6.2)
where cgg−0 , cdd−0 and ron−0 are the unit gate capacitance, drain capacitance and channel resistance per unit width, respectively. Second order nonlinear dependencies on terminal voltages
exist on these parameters, but these effects are not critical to the analysis of PA power loss.
Recall from Chapter 2 that the optimum value of the drain shunt capacitor for class-E operation is given by
Cshunt = 0.183
1
.
ω0 RL
(6.3)
We define a parameter α as
α=
Cdd
.
Cshunt
(6.4)
Cshunt can be realized either entirely as the drain parasitic capacitance (α = 1), or as a combination of the drain capacitance and a separate capacitor (α < 1). Reference [67] provides an
expression that relates theoretical class-E PA power loss to the ratio of ron /RL . It is rearranged
and normalized to peak output power as
ron
ω0 ron−0 cdd−0
Ploss,ron
,
= 1.365
= 7.46
Pout
RL
α
85
(6.5)
where the last equality is obtained by using (6.2),(6.3) and (6.4). (6.5) tells us that the transistor
switching loss caused by finite ron is minimized by maximizing α (i.e. α = 1). This result
agrees with intuition, since ron is reduced as device width increases. Although (6.5) is derived
for a classical class-E PA, it is equally applicable to a cascode class-E PA if the cascode device
is assumed biased at a condition similar to the on-state of the input device.
6.2.2
Parasitic Capacitor Charging Loss
The cascode class-E topology provides voltage stress relief and potentially increases the output
power capability of the PA by allowing a higher supply voltage. However, parasitic capacitance
at the intermediate node (drain of input device M1, as shown in Fig. 6.7) can be problematic if
left unattended. During the off-state of M1, Vd1 experiences a substantial voltage swing which
is a significant portion of Vd2 . The parasitic capacitance Cp at the intermediate node, which
comprises the M1 drain-bulk and drain-gate capacitances and M2 source-bulk and gate-source
capacitances, will have to be charged through M2, since M1 is switched off. In reality, this
mechanism begins even before M1 is sufficiently turned off, therefore the charging current is
supplied through the channels of both M1 and M2. This extra current component increases the
voltage and current waveform overlap of both M1 and M2, and since it does not contribute to the
Vd2
Vd2
Vd2
M2
M2
charging
current
M1
Vd1
Lres Cblock
Vd1
M1
Vd1
charging
current
Cp
Figure 6.7: Intermediate node of the cascode is charged and discharged through M1 and M2, causing
power loss (left). Adding a resonant inductor to provide charging current reduces loss (right).
86
8
real(Zin)
Impedance (Ohm)
6
no Lres
4
with Lres
2
with Lres
0
imag(Zin)
-2
no Lres
-4
35
40
45
50
55
Frequency (GHz)
Figure 6.8: Impedance looking into the cascode intermediate node.
PA output power, it has a noticeable impact on PA efficiency.
To solve this problem, an inductor Lres is added in parallel to Cp to form a tank that resonates
at the operation frequency of the PA. In this case, Cp is charged and discharged through Lres
instead of the lossy transistor channels, greatly reducing power loss associated with the capacitor
charging effect. A large capacitor (Cblock ) is inserted in series with Lres to remove the DC path
to ground. To analyze the effectiveness of this strategy, Cadence simulations are performed
with post-layout extraction parasitics and realistic passive device models. A coplanar-waveguide
segment implemented on a 1.2 µm thick copper layer has a reasonably high quality factor (> 20)
at 45 GHz, and it is used to resonate with Cp at 45 GH. Fig. 6.8 shows the impedance looking into
the intermediate node, with and without the resonance circuit. The effect of Cp is removed over
a very wide bandwidth, indicating that the loss reduction is robust over modeling inaccuracies
and process variations.
The total power loss of each transistor is also simulated. It is normalized to peak output
power of the PA and is shown in Fig. 6.9. The loss peaks, caused by non-zero overlapping of
the voltage and current waveforms, occur at the onset of transistor switching. They account for
more than 50% of total transistor power loss. The addition of Lres is shown to greatly reduce
87
500
100
without Lres
without Lres
80
Ploss,M2 /Pout (%)
Ploss,M1 /Pout (%)
400
300
200
with Lres
100
60
40
20
with Lres
0
0
-100
-20
10
20
30
40
10
20
30
40
Figure 6.9: Total power loss normalized to peak output power of the input device, M1 (left), and the
cascode device, M2 (right).
the peak loss in M1 by 45%. Loss in M2 is reduced over the entire transient period. Normalized
to peak output power, a 62% reduction in total transistor power loss is achieved by using the
resonant network. (Note that in Fig. 6.9, the segments of negative loss are caused by reactive
energy storage.)
6.2.3
Driver Loss
We have found from (6.5) that the power loss caused by transistor on-resistance is inversely
proportional to device width. However, increasing device size would lead to a proportionally
larger gate capacitance, resulting in extra power dissipation in the driver stage. This trade-off
can be analyzed as follows [64]. Assuming that the inter-stage matching network between the
driver and the PA presents an equivalent load resistor RD to the driver with a resonant quality
factor QD . RD can be written as
RD =
QD
RL QD cdd−0
=
ω0 Cgg
0.183α cgg−0
88
(6.6)
where (6.2),(6.3) and (6.4) are used for the last expression. Then, the total power loss of the
driver can be written as
Ploss,drv =
2
Vdd−drv
2RD ηdrv
(6.7)
where Vdd−drv is the supply voltage of the driver, ηdrv is the driver power efficiency. Combining
2
this expression with the class-E PA peak output power of 0.577VDD
/RL , we obtain the normal-
ized driver power loss
2
Ploss,drv
0.158α Vdd−drv cgg−0
=
Pout
ηdrv QD
Vdd
cdd−0
(6.8)
(6.8) assumes that the voltage swing at the input of the class-E PA equals Vdd−drv . As expected, driver power loss scales linearly with the parameter α and hence with the width of the
PA device. Additionally, loss depends strongly on the resonant quality factor QD , which is
determined by transistor configuration, layout, and the quality factors of passive matching components. While QD can be increased with careful layout practices, it typically does not exceed 5
in millimeter-wave frequency.
The opposite trend of Ploss,ron (6.5) and Ploss,drv (6.8) as functions of α suggests that a minimum loss condition can be achieved by the proper sizing the PA devices. To visualize the
trade-off, we use the following parameter values from a 45-nm SOI CMOS process,
• QD = 3
• Vdd = Vdd−drv = 1.1 V
• cgg−0 = 0.9 fF/µm
• cdd−0 = 0.5 fF/µm
• ron−0 = 0.8 kΩ.µm
• Also, assume that ηdrv = 1/(1 + 10ω0 ron−0 cdd0 )
The results of (6.5) and (6.8) are plotted in Fig. 6.10.
At 1 GHz, an optimal α of approximately 0.42 results in minimum total loss of the PA. That
is, Cshunt is implemented as a parallel combination of the transistor drain capacitance, and a
89
10
Normalized Power Loss
1 GHz
6.5 GHz
45 GHz
P loss,total/P out
1
P loss,total/P out
P loss,ron/P out
P loss,total/P out
0.1
P loss,ron/P out
P loss,drv/P out
P loss,ron/P out
P loss,drv/P out
P loss,drv/P out
0.01
0.1
0.4
0.7
1 0.1
0.4
α
0.7
α
1 0.1
0.4
0.7
1
α
Figure 6.10: Calculated normalized ron power loss, driver power loss, and total power loss, as functions
of α at 1 GHz, 6.5 GHz and 45 GHz.
separate capacitor that comprises the remaining 58% of Cshunt . When frequency goes up to 6.5
GHz, Ploss,ron and Ploss,drv are identical at α = 1. Since Ploss,drv is a weaker function of frequency
than Ploss,ron , as frequency further increases, minimum total loss will always be achieved when
Ploss,ron is minimized (i.e. by setting α = 1).
6.2.4
Passive Device Loss
Passive devices often contribute to PA power loss considerably. On-chip inductors suffers from
various sources of power loss, including skin effect loss, loss due to proximity effect, and eddy
current loss caused by capacitive coupling to the lossy silicon substrate. These loss sources
contribute to the low quality factor of on-chip inductors, which typically ranges from less than
10 to about 20. In a class-E PA, typically three inductors are used: the series resonant inductor,
Ls ; the impedance matching inductor, Lm ; and the choke inductor, Lc . For simplicity, assume
that all of these inductors have the same quality factor of Q. Also assume that the impedance
90
0.07
Pc,total / Pout
Pc,DC / Pout
Pc,RF / Pout
Normalized Loss
0.06
0.05
0.04
0.03
0.02
0.01
0
1
2
3
4
5
nc
Figure 6.11: Choke inductor power loss versus nc .
matching network is implemented as an L-match section. It can be shown [30, 64] that
Qout
Ploss,Ls
=
Pout
Q
r
Ploss,Lm
1 Rant
=
−1
Pout
Q RL
nc
Ploss,Lc
= 0.577
Pout
Q
(6.9)
where Qout = ω0 Ls /RL is a design parameter that involves a trade-off between operation bandwidth and output signal harmonic content, Rant is the antenna input impedance, usually 50Ω, and
nc = ω0 Lc /RL is the ratio between the choke inductor input impedance to the load impedance
and is assumed large (i.e. > 20).
The following observations can be made from (6.9): The series L-C resonator loss depends
only on Q and operation bandwidth of the resonator as set by Qout . The L-match network loss
depends on both Q and the impedance transformation ratio, Rant /RL . Finally, the loss caused by
the choke inductor is a linear function of nc . A small nc would result in more RF power diverted
into the power supply instead of the load, which constitutes loss (Pc,RF ). On the other hand, a
large nc increases the ohmic loss (Pc,DC ) of the choke inductor itself. These two loss components
91
are normalized to the PA output power and plotted against nc in Fig. 6.11. An optimum value
that yields minimum choke inductor loss is achieved with an nc of approximately 2.
6.3 Circuit Implementation
With a thorough understanding of the various loss mechanisms of a cascode class-E PA established, we will describe the actual circuit implementation of the PA in this section. A block
diagram of the proposed PA architecture is shown in Fig. 6.12. To generate watt-level output
power, a 16-way outphasing PA topology is adopted, in which 16 identical unit power amplifiers
operate in two groups, each containing 8 unit PAs that share the same signal phase. In this section, the most critical block - the power amplifier output stage, will be examined first. The output
stage design is optimized for maximum efficiency with the application of loss reduction techniques. We will then discuss the design of other building blocks in detail, including the driver
chain, the input power splitters, and the output power combiner.
50 Ω Load
Driver
PA
Unit Power Amplifier
Input S1
Input S2
Output Power Combiner
Input Power
Splitter
Figure 6.12: Block diagram of the proposed 45 GHz 16-way class-E outphasing PA.
92
6.3.1
Power Amplifier Output Stage
The design priorities of the cascode class-E stage can be summarized as follows:
1. The parameter α is set to 1 to minimize transistor ron loss.
2. Use parallel resonant tank to reduce the parasitic capacitance charging loss at the drain of
the cascode input device.
3. Minimize driver power consumption by resonating out the input device gate capacitance
with high resonant quality factor.
Following these requirements, the resulting design of the PA output stage is shown schematically in Fig. 6.13. Transistors M1 and M2 are sized identically at a total width of 350 µm. The
transistor finger width is set to 840 nm, which according to simulation provides the highest fmax .
Drain capacitance of M2 is 131 fF, a value slightly larger than the optimum Cshunt calculated by
(6.3). The benefit of using a slightly larger sized transistor than required (i.e. α > 1) in this case
actually outweighs the effect of a sub-optimal Cshunt . The total capacitance at the drain of M1,
including routing parasitics, is 525 fF. With a swing at this node of more than 2V, supplying the
VDD
VB2
TL4
L: 56 µm
Z0: 47 Ω
To
combiner
R2
4.5 kΩ
VB1
R1
C4
4.5 kΩ
710 f F
Driver
C1
TL1
TL2
915 f F
L: 85 µm
Z0: 40 Ω
L: 32 µm
Z0: 37 Ω
M2
C5
W: 350 µm
L: 45 nm
220 f F
M1
TL3
W: 350 µm
L: 45 nm
L: 120 µm
Z0: 43 Ω
C3
28.8 pF
C2
3.5 pF
Figure 6.13: Schematic diagram of the cascode class-E PA output stage.
93
charge through even a 1Ω resistor would cause more than 50 mW of power loss. To mitigate this
source of loss, the transmission line, TL3, is used to form a high-Q resonant tank with the M1
drain capacitance. Transmission line TL2 serves a similar purpose as it resonates with the gate
capacitance of M1 to reduce power consumption of the driver. The transmission lines are implemented as coplanar waveguides on a 1.2 µm copper layer, with quality factor of approximately
20 at 45 GHz.
Due to the lack of high quality factor MIM capacitors in this process, all capacitors in the
PA output stage are implemented as inter-digital metal sidewall capacitors (except for supply
decoupling capacitors). To minimize capacitor series resistance, the metal finger length is kept
short as long as layout permits. As mentioned previously, capacitor C4 is part of a capacitive
voltage divider that allows voltage swing on the gate of M2. A small value of C4 translates to
a large voltage swing at M2 gate, and the voltage stress on both transistors is relieved in the
expense of a higher ron power loss (gate overdrive of M2 is smaller during M1 on-state). The
value of C4 is determined by circuit simulation and optimization.
Layout of the transistor cell requires special attention. Due to the high DC current density of
the PA, i.e. up to 0.8 mA/µm, sufficiently robust metal wiring and parallel vias are needed for
the source and drain connections of the transistor to prevent excessive electromigration, which
causes performance degradation or device failure in the long term. The top and side view of
the transistor unit finger layout is shown in Fig. 6.14. Since stacks of multiple metal layers
are placed side by side in close proximity, side-wall parasitic capacitance from source to drain
can be substantial, which limits fmax of the device and degrades the performance of the PA. A
“tapered” stack layout is adopted to minimize the lateral overlap between source and drain feeds,
as visualized in Fig. 6.14 and also in Fig. 6.15. Compared to a transistor layout without tapering
finger feed lines, the source-drain feed line parasitic capacitance of the tapered layout is reduced
by more than 30%.
The load impedance transformation is performed within the output power combiner. The
optimum load impedance ZL is obtained from large signal load-pull simulations, in which an
94
Gate
Top View
Drain
Source
Drain
Source
Gate
Gate
Side View
Figure 6.14: Top and side view of the unit transistor finger metal wiring.
Gate
Drain
Source
Source
Drain
Gate
Thick metal layers (orange) not shown.
Unit FET (45 fingers)
Figure 6.15: Top view of the transistor layout (left), and the close-up 3-D view of the transistor finger
wiring (right).
95
ideal tuner is inserted after the capacitor C5 to simulate the impedance looking into the combiner
port. The resulting ZL is 6 + j34.7.
6.3.2
Driver Chain and Input Power Splitter
To obtain high efficiency with a class-E PA, the input device should be driven with a sufficiently
large voltage swing. This task is often achieved by inverter-based driver topologies at frequencies
below the millimeter-wave regime. The high cutoff frequency of the 45-nm SOI CMOS allows
the inverter chain topology to remain useful at 45 GHz. The schematic diagram of the proposed
driver chain is shown in Fig. 6.16, which includes all component values and transistor sizing. The
input signal of the driver chain is capacitively coupled to the first inverter, while the DC level
is set locally and passed down the chain by a resistor network. The first 4 stages of the chain
are identical 1x inverters that ensures a near rail-to-rail signal swing, followed by progressively
From
60 f F
Input Power
Splitter
1.1 kΩ
2.1 kΩ
INV 1x
INV 1x
Wn: 1 µm
Wp: 1.6 µm
INV 1.3x
Wn: 1.3 µm
Wp: 2.1 µm
L: 165 µm
Z0: 42Ω
INV 13.1x
INV 3.2x
INV 5.1x
INV 8.2x
Wn: 3.2 µm Wn: 5.1 µm Wn: 8.2 µm Wn: 13.1 µm
Wp: 5.1 µm Wp: 8.2 µm Wp: 13.1 µm Wp: 21 µm
INV 2x
Wn: 2 µm
Wp: 3.2 µm
INV 21x
Wn: 21 µm
Wp: 34 µm
Figure 6.16: Schematic diagram of the unit PA driver chain.
96
To
Matching
Network
L: 165 µm
Z0: 42Ω
INV 30x
Wn: 30 µm
Wp: 48 µm
To unit PA driver chain
L: 90 µm
Z0:94Ω
L: 190 µm
Z0:95Ω
50 Ω
Input
63 fF
L: 232 µm
Z0: 72Ω
L: 368 µm
Z0: 74Ω
L: 340 µm
Z0: 66Ω
L: 381 µm
Z0: 60Ω
172 fF
2.1 kΩ
1x
1x
1x
1x
1.3x
2x
3.2x
5.1x 8.2x 13.1x
1x
Figure 6.17: Schematic diagram of the input power splitter.
larger inverter stages to finally reach the PA input matching network. A total of 12 inverters
are used with a scaling factor of 1.6 each. The last two inverter stages are each preceded by a
transmission line segment to take advantage of inductive peaking. This technique ensures railto-rail swings throughout the chain. The driver chain consumes 70 mW of power from a 1.2V
power supply, and it provides a power gain of more than 26 dB.
Preceding each of the PA driver chains is an 8-way power splitter that buffers and distributes
input power. The schematic diagram of the power splitter is shown in Fig. 6.17. The power splitter consists of multiple coplanar waveguide segments that form a binary tree structure. Length
of each segment is mainly constrained by the 200 µm pitch of the unit PAs. The splitter tree as
a whole presents a purely real resistance (143 Ω) to the input buffer, which is embedded within
the input arm of the splitter. The buffer topology is similar to the inverter driver chain discussed
earlier. An input matching network, consisting of two coplanar waveguide segments and a capacitor, minimizes input reflection to below -10 dB. The buffer consumes 27 mW of DC power,
and the entire splitter as a whole is able to deliver 122 mW of power to each of the 8 PA drivers
97
with only 8 µW of input power, which translates to a total equivalent power gain of 21 dB.
6.3.3
Output Power Combiner
Similar to the 16-way SiGe power amplifier described in Chapter 5, a 16-way zero-degree power
combiner based on a transmission line binary tree structure is used to combine the output of
16 unit PAs. The zero-degree combiner has low loss due to the short length that signal travels
through as compared to, for example, a corporate power combiner. To further increase combiner
efficiency, a flip-chip assembly configuration is used that utilizes a very low loss liquid crystal
polymer (LCP) substrate to implement the power combiner. A cross-section view of the configuration is shown in Fig. 6.18(a). A 25 µm thick LCP substrate is sandwiched by two copper
layers on each side. The combiner, which is based on microstrip line traces, is implemented using one side of the LCP substrate as signal path and the other as a ground plane. The silicon die
containing the 16 unit PAs is flip-chip attached to the LCP substrate with bump structures. The
die surface directly above the combiner structure is covered with a top aluminum metal ground
50 Ω Output
Silicon Die
Top Ground Plane
~50 µm
Polyimide
Combiner Trace
Bump
Liquid Crystal Polymer (25 µm)
Bottom Ground Plane
Backing Substrate
PA1
PA9
PA2
PA10
PA3
PA11
PA4
PA12
PA5
PA13
PA6
PA14
PA7
PA15
PA8
PA16
(a)
(b)
Figure 6.18: (a) Cross-section view of the flip-chip assembly configuration (not drawn to scale). (b)
Layout of the 16-way zero-degree combiner (courtesy of Chongzhe Li).
98
Isolation (dB)
without / with RISO
port 1
port 2
port 3
port 2
7.2 / 12.6
port 3
12.5 / 22.3
12.6 / 17.6
port 4
12.5 / 28.2
12.6 / 31.1
7.3 / 20.6
port 5
12.9 / 20.2
12.9 / 22.4
12.9 / 31
port 6
12.9 / 17.2
12.9 / 18.2
12.9 / 21.2
port 7
12.9 / 15.8
12.9 / 26.5
port 8
12.9 / 15.3
port 4
12.9 / 21.8
Table 6.1: Simulated port isolation of the 8-way zero-degree combiner without and with isolation resistors
inserted between input ports.
plane that acts as a second ground to the combiner. The backing substrate on the other side of
the LCP substrate provides mechanical support.
The layout of the 16-way combiner2 is presented in Fig. 6.18(b). Each of the combiner
input ports is connected to a bump pad that bonds to the PA on the silicon die. The length and
characteristic impedance of each combiner transmission line segment determine the port input
impedance, which is equal to 6 + j34.7 for optimal PA performance. Parasitics of the flip-chip
bumps are taken into account during the design. A total insertion loss of 0.35 dB is achieved,
which is equivalent to a combiner efficiency of 92%.
Although the zero-degree combiner inherently provides less isolation between ports as compared to a corporate combiner, the impact on PA performance is minimal since the combiner is
operated with all input signals at the same phase. Nonetheless, it is relatively easy to improve
port isolation of the zero-degree combiner, as explained in Chapter 5. By simply adding small
isolation resistors (e.g. 10 Ω) between adjacent input ports, port isolation is improved by up to
18 dB, as shown in Table 6.1. The improved port isolation ensures that the output power and
efficiency of the PA degrades gracefully in the rare event of unit PA failure, as well as being
more resistant to device mismatch and process variation.
2
Combiner design, simulation, and fabrication courtesy of Chongzhe Li.
99
Unit
PA
Input
Power
Splitter
DC
Pads
Pads to
Input Pads Off-chip
Combiner
Figure 6.19: Layout of the 16-way power amplifier. Die area measured 2.4 mm by 1.9 mm, including all
pads.
The layout of the power amplifier is shown in Fig. 6.19. Two sets of G-S-G pads connect
the input signals to the two input power splitters from the bottom of the figure. The unit PAs are
oriented so that the driver chains are closer to the center of the chip, whereas the output is facing
the two sides. This configuration allows the two columns of combiner input pads to be spaced
sufficiently far away to make the design of the combiner easier. The PA consumes 2.4 mm by
1.9 mm, or 4.56 mm2 of die area, including all pads. All of the pads are to be flip-chip bumped
on to the LCP substrate.
100
6.4 Simulation Results
Designed with a 45-nm SOI CMOS process development kit (PDK), the 16-way combined PA is
fully simulated and characterized using the Cadence Spectre simulation environment. The PDK
provides high frequency transmission line and inter-digital metal side-wall capacitor models.
All transistors in the design are simulated with full layout R-C parasitics extraction. The offchip 16-way combiner s-parameters are obtained from a 2.5-D EM simulator. The combiner
s-parameters are then converted to Verilog-A hardware description language to be simulated
within the Cadence environment.
Simulated output power, drain efficiency (DE), and PAE versus a VDD variation from 0.5
V to 2.2 V are shown in Fig 6.20(a). Outphasing angle θ is set to zero in this simulation, i.e.
all 16 unit PAs are in-phase, and the output power is altered only by supply variation. With a
2.2 V supply, peak output power of 36 dBm (4 W) is reached with 44% PAE. DE remains high
across the VDD sweep range due to the linear VDD dependence in power consumption of the
cascode class-E stages. On the other hand, total power consumption of the driver stages remain
constant regardless of output stage supply voltage variation, causing PAE to degrade as output
power decreases. PAE drops to below 30% at 1V supply voltage when the PA generates 29.3
50
50
Pout (dBm), PAE (%)
Pout (dBm), PAE (%), DE(%)
60
40
30
20
DE
PAE
Pout
10
45
PAE
40
Pout
35
30
25
20
15
10
5
0
0
0
0.5
1
1.5
2
40
2.5
42
44
46
48
50
Frequency (GHz)
VDD (V)
(a)
(b)
Figure 6.20: (a) Simulated Drain efficiency, PAE, and output power versus VDD. (b) Simulated PAE and
output power versus carrier frequency.
101
50
10
35
-3.5dB
-6.7dB
30
25
20
15
10
Vdd = 2.2
Vdd = 1.8
Vdd = 1.4
Vdd = 1
9
Power Consumption (W)
40
PAE (%)
-1.4dB
Vdd = 2.2
Vdd = 1.8
Vdd = 1.4
Vdd = 1
45
8
7
6
5
4
3
2
5
1
0
0
-30
-20
-10
0
-30
Normalized Output Power (dBm)
-20
-10
0
Normalized Output Power (dBm)
Figure 6.21: Simulated PAE and power consumption versus normalized output power, with different
VDD applied.
0
Vdd = 2.2
Vdd = 1.8
Vdd = 1.4
Vdd = 1
1
AM-PM Nonlinearity (degrees)
AM-AM Nonlinearity (dB)
2
0
-1
-2
-3
-4
Vdd = 2.2
Vdd = 1.8
Vdd = 1.4
Vdd = 1
-5
-10
-15
-20
-25
-30
-35
-30
-20
-10
0
Normalized Output Power (dBm)
-30
-20
-10
0
Normalized Output Power (dBm)
Figure 6.22: Simulated AM-AM and AM-PM nonlinearity versus normalized output power, with different VDD applied.
dBm (850 W) of output power. The simulated performance versus carrier frequency is shown
in Fig 6.20(b). Peak PAE is centered at 45 GHz and it remains about 40% within a 2 GHz
bandwidth. The rather sharp roll-off of the PAE characteristics is a result of multiple resonant
circuits in the PA, including the power splitter input match, the driver-to-PA interstage match,
and the cascode intermediate node resonant tank, as well as the bandwidth of the combiner. The
-3 dB bandwidth of the PA is approximately 5 GHz.
In Fig. 6.21, outphasing angle θ is swept to generate output power back-off, in addition to
102
140
Count
100
std = 0.15
Count
120
Pmean
= 1.79
no Riso
out with
mean
1.79
std ==0.15
80
60
40
20
0
180
160
140
120
100
80
60
40
20
0
160
140
120
100
80
60
40
20
0
PAE with no Riso
mean = 43.4
std = 1.95
mean = 1.96
std = 0.06
Output Power (W)
Count
Count
Output Power (W)
Pout with Riso=10
PAE (%)
160
140
120
100
80
60
40
20
0
PAE with Riso=10
mean = 45.2
std = 0.82
PAE (%)
Figure 6.23: Simulated PAE and output power distribution from Monte Carlo analysis of 500 points,
with and without Riso resistors.
a supply variation of 4 discrete levels (2.2 V, 1.8 V, 1.4 V, and 1 V). The 3 lower VDD levels
enable power back-off of 1.4 dB, 3.5 dB and 6.7 dB respectively. The simulated linearity of the
outphasing characteristics is presented in Fig. 6.22. The AM-AM (i.e. outphasing angle to output
amplitude) nonlinearity ranges from -2 dB with 2.2 V supply, up to almost -4 dB with 1 V supply.
The AM-PM (i.e. outphasing angle to output phase) nonlinearity has a maximum value of -30
degrees, and it tends to improve a VDD is lowered. These levels of nonlinearity may require
substantial pre-distortion in the baseband to improve EVM and prevent spurious emissions.
Performance degradation caused by device mismatch and process variation is investigated
through Monte Carlo statistical analysis. In particular, we are interested in the statistical behavior
of the PA under improved combiner port isolation with the addition of between-port isolation
resistors, Riso (Section 6.3.3). A half of the 16-way combined PA, which contains 8 unit PAs
103
driven in-phase, are used for the analyses to conserve simulation time. The results shown in
Fig. 6.23 indicate that the mean values of output power and PAE differ slightly between the two
cases (with and without Riso ), while the inclusion of Riso greatly reduces standard deviation of
both output power (from 0.15 W to 0.06 W) and PAE (from 1.95% to 0.82%). These results
justify the use of a zero-degree combiner with non-ideal port isolation.
The simulated performance of the 16-way combined PA is summarized in Table 6.2.
Frequency
Pout
PDC
Die Area
45 GHz
36 dBm
9.2 W
4.56 mm2
Bandwidth
DE
PAE
5 GHz
50%
44%
Table 6.2: Summary of the simulated performance of the 16-way combined PA.
6.5 Summary
The design of a millimeter-wave cascode class-E power amplifier has been thoroughly analyzed,
including the various loss mechanisms and efficiency improvement techniques. A 45 GHz 16way combined PA with an off-chip combiner is designed in a 45-nm SOI CMOS technology,
and the characteristics of the PA has been studied through simulations. With realistic device
models and complete layout parasitics extraction, a simulated performance of 44% PAE at 36
dBm output power is predicted, which far exceeds the state-of-the-art experimental results. High
PAE is maintain with supply voltage scaling, and it achieves greater than 30% PAE at 7 dB power
back-off.
104
Chapter 7
Conclusions
This thesis explores techniques of implementing efficient, watt-level integrated power amplifiers for RF and millimeter-wave wireless applications. An efficiency enhancement technique is
proposed and implemented in a cellular band watt-level outphasing CMOS PA. In the millimeterwave frequency range, we explore loss reducing techniques to maximize PA efficiency. A compact, low-loss, impedance-matching power combiner is presented and analyzed that enables efficient watt-level power amplifiers in the millimeter-wave regime. In the following sections,
contributions of this thesis are summarized, and possible directions of future research are discussed.
7.1 Contributions
There are two main contributions of this thesis. Firstly, a cellular-band PA that utilizes dynamic
power control (DPC) has been experimentally demonstrated for the first time (Chapter 3). The
large peak-to-average power ratio of high data-rate communication standards degrades average
PA efficiency due to the low efficiency at back-off in conventional PAs. We have shown that the
proposed DPC scheme is able to reduce power consumption at power back-off by dynamically
switching on and off segments of the PA according to the instantaneous power level. The DPC
scheme is implemented in a 2.4 GHz class-D outphasing PA, fully integrated in a 45-nm digital
CMOS process. A multi-segment transformer combiner is used to generate 31.5 dBm of peak
output power with 27% peak PAE, and a CW output power range of more than 86 dB. A supply
ringing effect that is induced by the DPC operation is identified, which degrades ACPR and
105
would require more back-off for the PA to meet spectrum mask requirements. The cause of
supply ringing is fully analyzed and understood, and a “skip window” technique is implemented
to mitigate this effect. With the DPC scheme enabled, the measured PAE under a 64-QAM WiFi
modulated signal is 16% at 25.8 dBm average output power (6.7 dB back-off), which marks
a 33% reduction in power consumption as compared to the DPC-disabled mode. At a lower
average output power of 20.5 dBm (11 dB back-off), the DPC scheme allows a 140% reduction
in power consumption with a PAE of 12%.
The proposed implementation of the DPC scheme provides a new opportunity to improve
energy efficiency and hence battery life of hand-held wireless devices. Furthermore, the proposed
PA topology is suitable for system-on-chip integration in scaled-CMOS processes.
The second contribution of the thesis is the design and analysis of efficient PAs operating in
the millimeter-wave regime. We described the various trade-offs between different PA classes
and topologies, based on which a 45 GHz, 2-stage, class-B PA in 130-nm SiGe BiCMOS technology is designed and implemented (Chapter 4). The PA achieved a peak CW PAE of 26% at
16.6 dBm output power, which is to date the highest PAE achieved by an integrated SiGe PA with
greater than 13.3 dBm output power and operates above 10 GHz. Based on the optimized class-B
PA topology, a 16-way combined PA is designed and fabricated (Chapter 5). It utilizes a 16-way
zero-degree combiner that is compact, low-loss, and provides the capability of impedance transformation. The zero-degree combiner is analyzed in detail and implemented with microstrip line
segments on the SiGe die. The measured peak output power of the 16-way SiGe PA is 20 dBm
which is roughly 10 dB lower than simulation. The cause of this discrepancy is well understood
and has been replicated in simulation.
The millimeter-wave PA design techniques developed for the SiGe PA have been extended
to designing a 45-GHz 16-way combined PA in 45-nm SOI CMOS technology (Chapter 6). A
cascode class-E topology has been chosen based on the performance analysis of different CMOS
PA classes. We also analyzed the various design trade-offs and sources of power loss in a CMOS
cascode class-E PA. The zero-degree power combiner topology is also adopted in this design,
106
which provides low loss impedance transformation to 16 unit PAs. Several circuit and layout
techniques have been utilized to optimize the performance of the PA, whose simulated performance at 45 GHz includes 44% peak PAE and 36 dBm peak output power. In the literature,
silicon-based millimeter-wave PAs have yet to achieve output power that exceeds 23 dBm. The
presented analysis and simulation results indicate that a feasible CMOS solution for watt-level
power generation in the millimeter-wave regime exists, and that by using the proposed PA topology a high PAE can potentially be achieved.
7.2 Future Research
7.2.1
Dynamic Power Control
The concept of dynamic power control can be extended in several ways. Since the reduction in
power consumption at low power levels is achieved by turning off segments of the PA, thereby
increasing the ratio of output power to driver power consumption, more levels of power control
can further enhance efficiency at low power. With the increased granularity of power control,
efficiency at even high output power can be improved, since on average the PA is operating with
outphasing angle closer to zero. The number of segments in the presented PA is limited to 8 due
to layout constraints of the transformer combiner.
A possible alternative to the proposed power control topology would be to implement a combination of transistor resizing and transformer combining. Each PA cell is sub-divided into
smaller units that share the same load impedance, whereas multiple PA cells are connected to
a transformer combiner as described in this work. For example, assume that a total of N PA
cells are combined with a transformer combiner that allows each cell to turn on or off separately,
while each PA cell is sub-divided into N transistor units that are also independently switchable.
When M PA cells are on, PAE can be expressed as (3.10). Note that as output power scales
with (M/N )2 , the driver power consumption scales with M/N , indicating a degraded PAE as M
becomes smaller. However, if we also scale the size of the transistor and driver within each PA
cell by M/N , to the first order, there will be two effects on power consumption: (a) the driver
107
With Transformer Power Control
and Transistor/driver resizing
30
25
25
20
20
PAE (%)
30
15
15
10
10
5
5
0
-40
-30
-20
-10
PAE (%)
With Transformer Power Control
0
0
-40
Normalized Output Power (dB)
-30
-20
-10
0
Normalized Output Power (dB)
Figure 7.1: Back-off PAE improvement with additional resizing of transistor and driver within each PA
cell.
power consumption will now scale with (M/N )2 as well. (b) The on-resistance of the PA cell
now scale with N/M , indicating an increased loss coefficient B in (3.10). With transistor and
driver resizing, PAE can now be expressed as
P AE =
Pout
=
Pout + Pdiss
=
1+
N
M
Pout
M
N
Pconst,unit
Pout
Pout +
B+
1
M2
N
2
× Pconst,unit +
.
N
M
B × Pout
(7.1)
Assuming the same values of B and Pconst,unit , the PAE according to (3.10) and (7.1) with N = 8
is plotted in Fig. 7.1.
Although (7.1) tend to under-estimate power consumption at low output power levels due
to its inability to predict output power degradation associated with the higher on-resistance, it
is potentially true that extra power savings can be achieved at low power levels by dynamically
resizing transistors, in addition to switching on or off PA segments.
7.2.2
Millimeter-wave PAs
With continued transistor scaling and improvement in the cutoff frequency, extending the range
of operation deeper into the millimeter-wave regime is possible. In this work we have developed
108
45 GHz PAs with transmission line based power combiners. As the wavelength becomes shorter
at even higher frequencies, we can make the combiner proportionally more compact and potentially reduce conductor loss of the combiner, since the conductor sheet resistance only scales
with the square root of frequency. Class-E behavior may not be easily achieved at higher frequencies, e.g. at 94 GHz the transistor does not switch fast enough to generate useful harmonic
components. Nonetheless, a class-E like load can still potentially improve efficiency and PAE,
provided that power gain of the output stage is reasonable.
An objective of future work is the realization of the proposed cascode class-E PA presented in
Chapter 6. Owing to its excellent efficiency characteristics under scaled supply voltage, it is naturally suited to supply scaled transmitter topologies, e.g. an asymmetric multilevel outphasing
transmitter [57, 68]. We believe that with proper execution, the PA topology presented in Chapter 6 can serve as a building block in a watt-level, high data-rate, millimeter-wave transmitter
system.
109
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