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LM4992, LM4992SDBD
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LM4992
420mW Stereo Cell Phone Audio Amplifier
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FEATURES
DESCRIPTION
•
•
•
•
The LM4992 is a stereo audio power amplifier
primarily designed for demanding applications in
mobile phones and other portable communication
device applications. It is capable of delivering 1 watt,
per channel, of continuous average power to an 8Ω
BTL load with less than 1% distortion (THD+N) from
a 5VDC power supply.
1
2
•
•
•
•
Available in Space-Saving WSON Package
Ultra Low Current Shutdown Mode
BTL Output Can Drive Capacitive Loads
Improved Click and Pop Circuitry Eliminates
Noise During Turn-On and Turn-Off
Transitions
2.2 - 5.5V Operation
No Output Coupling Capacitors, Snubber
Networks or Bootstrap Capacitors Required
Unity-Gain Stable
External Gain Configuration Capability
APPLICATIONS
•
•
•
The LM4992 features independent shutdown control
for each channel and a low-power consumption
shutdown mode, which is achieved by driving both
shutdown pins with logic low. Additionally, the
LM4992 features an internal thermal shutdown
protection mechanism.
Mobile Phones
PDAs
Portable Electronic Devices
KEY SPECIFICATIONS
•
•
•
•
Boomer audio power amplifiers were designed
specifically to provide high quality output power with a
minimal amount of external components. The
LM4992 does not require output coupling capacitors
or bootstrap capacitors, and therefore is ideally suited
for mobile phone and other low voltage applications
where minimal power consumption is a primary
requirement.
Improved PSRR at 217Hz & 1KHz: 64 dB
(1KHz)
Stereo Output Power at 5.0V, 1% THD, 8Ω:
1.07 W (typ)
Stereo Output Power at 3.3V, 1% THD, 8Ω:
420 mW (typ)
Shutdown Current, Vdd = 3.3V: 0.2 µA (typ)
The LM4992 contains advanced click and pop
circuitry which eliminates noise which would
otherwise occur during turn-on and turn-off
transitions.
The LM4992 is unity-gain stable and can be
configured by external gain-setting resistors.
Connection Diagram
14 Pin WSON (Top View)
See Package Number NHK0014A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
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SNAS220B – NOVEMBER 2003 – REVISED MAY 2013
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TYPICAL APPLICATION
V DD
Cs
1 PF
Rf
20k
Audio
Input
Ri
20k
-IN
Ci
0.39 PF
+IN
Vo1
+
-
20 k:
RL
20 k:
8:
Bypass
V IH
Shutdown
Shutdown
Control
Shutdown
BIAS
Shutdown
Control
V IH
Bypass
VIL
+
+
Vo1
BIAS
CB
1.0 PF
V IL
A V = -1
V DD /2
VDD /2
+
CB
1.0 PF
Vo2
A V = -1
+
-
RL
20 k:
+IN
Audio
Input
+
Ri
20k
-IN
Ci
0.39 PF
8:
20 k:
Vo2
-
GND
Rf
20k
Figure 1. Typical Audio Amplifier Application Circuit
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage
(1) (2)
(3)
6.0V
−65°C to +150°C
Storage Temperature
−0.3V to VDD +0.3V
Input Voltage
Power Dissipation
(4) (5)
ESD Susceptibility
(6)
ESD Susceptibility
(7)
Internally Limited
2000V
200V
Junction Temperature
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
150°C
θJA (WSON)
103°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
If the product is in Shutdown mode and VDD exceeds 6V (to a max of 8V VDD), then most of the excess current will flow through the
ESD protection circuits. If the source impedance limits the current to a max of 10mA, then the device will be protected. If the device is
enabled when VDD is greater than 5.5V and less than 6.5V, no damage will occur, although operation life will be reduced. Operation
above 6.5V with no current limit will result in permanent damage.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower.
Maximum power dissipation in the device (PDMAX) occurs at an output power level significantly below full output power. PDMAX can be
calculated using Equation (1) shown in the APPLICATION INFORMATION section. It may also be obtained from the power dissipation
graphs.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF–240pF discharged through all pins.
OPERATING RATINGS
TMIN ≤ TA ≤ TMAX
Temperature Range
−40°C ≤ TA ≤ 85°C
2.2V ≤ VDD ≤ 5.5V
Supply Voltage
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ELECTRICAL CHARACTERISTICS VDD = 5V (1)
(2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
LM4992
Conditions
Typical
14
mA (max)
7
18
mA (max)
1.4
3
µA (max)
Shutdown Current
VSDIH
Shutdown Voltage Input High
1.5
VSDIL
Shutdown Voltage Input Low
1.3
VOS
Output Offset Voltage
Po
Output Power
TWU
Wake-up time
THD+N
Total Harmonic Distortion+Noise
Xtalk
Crosstalk
(3)
(4)
(5)
Units
(Limits)
6
ISD
(1)
(2)
(4) (5)
VIN = 0V, Io = 0A, 8Ω Load
Quiescent Power Supply Current
Power Supply Rejection Ratio
Limit
VIN = 0V, Io = 0A, No Load
IDD
PSRR
(3)
VSD = VGND
V
V
7
30
mV (max)
THD = 1% (max); f = 1 kHz, per
channel
1.07
0.9
W (min)
100
ms
Po = 0.5 Wrms; f = 1kHz
0.15
%
80
dB
Vripple = 200mV sine p-p
Input terminated with 10Ω
60 (f = 217Hz)
64 (f = 1kHz)
55
dB (min)
All voltages are measured with respect to the ground pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are ensured to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
ELECTRICAL CHARACTERISTICS VDD = 3.3V (1)
(2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
LM4992
Conditions
Typical
12
mA (max)
5
15
mA (max)
0.2
2.0
µA (max)
Shutdown Current
VSDIH
Shutdown Voltage Input High
1.2
VSDIL
Shutdown Voltage Input Low
1.0
VOS
Output Offset Voltage
Wake-up time
THD+N
Total Harmonic Distortion+Noise
Xtalk
Crosstalk
PSRR
(1)
(2)
(3)
(4)
(5)
4
Power Supply Rejection Ratio
Units
(Limits)
4
ISD
TWU
(4) (5)
VIN = 0V, Io = 0A, 8Ω Load
Quiescent Power Supply Current
Output Power
Limit
VIN = 0V, Io = 0A, No Load
IDD
Po
(3)
VSD = VGND
7
V
V
30
mV (max)
THD = 1% (max); f = 1 kHz, per
channel
420
mW (min)
75
ms
Po = 0.25 Wrms; f = 1kHz
0.1
%
80
dB
Vripple = 200mV sine p-p
Input terminated with 10Ω
65 (f = 217Hz)
70 (f = 1kHz)
55
dB (min)
All voltages are measured with respect to the ground pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are ensured to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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ELECTRICAL CHARACTERISTICS VDD = 2.6V (1)
(2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
LM4992
Conditions
Typical
VIN = 0V, Io = 0A, No Load
4.0
VIN = 0V, Io = 0A, 8Ω Load
6.0
VSD = VGND
0.02
IDD
Quiescent Power Supply Current
ISD
Shutdown Current
VSDIH
Shutdown Voltage Input High
1.2
VSDIL
Shutdown Voltage Input Low
1.0
VOS
Output Offset Voltage
Po
Output Power
TWU
Wake-up time
THD+N
Total Harmonic Distortion+Noise
Xtalk
Crosstalk
PSRR
(1)
(2)
(3)
(4)
(5)
(3)
5
Power Supply Rejection Ratio
Limit
(4) (5)
Units
(Limits)
mA (max)
mA (max)
2.0
µA (max)
V
V
30
mV (max)
THD = 1% (max); f = 1 kHz, per
channel
240
70
ms
Po = 0.15 Wrms; f = 1kHz
0.1
%
80
dB
Vripple = 200mV sine p-p
Input terminated with 10Ω
51 (f = 217Hz)
51 (f = 1kHz)
dB (min)
mW (min)
All voltages are measured with respect to the ground pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are ensured to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
External Components Description
(Figure 1)
Components
Functional Description
1.
Ri
Inverting input resistance which sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass
filter with Ci at fC= 1/(2π RiCi).
2.
Ci
Input coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with
Ri at fc = 1/(2π RiCi). Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for an explanation
of how to determine the value of Ci.
3.
Rf
Feedback resistance which sets the closed-loop gain in conjunction with Ri.
4.
CS
Supply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for
information concerning proper placement and selection of the supply bypass capacitor.
5.
CB
Bypass pin capacitor which provides half-supply filtering. Refer to the section, PROPER SELECTION OF EXTERNAL
COMPONENTS, for information concerning proper placement and selection of CB.
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TYPICAL PERFORMANCE CHARACTERISTICs
THD+N vs Frequency
at VDD = 3.3V, 8Ω RL,
and PWR = 250mW, per channel
20
20
10
10
5
5
2
2
THD + N (%)
THD + N (%)
THD+N vs Frequency
at VDD = 5V, 8Ω RL,
and PWR = 500mW, per channel
1
0.5
0.2
1
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
20
50 100 200 500 1k 2k
0.01
20
5k 10k 20k
50 100 200 500 1k 2k
FREQUENCY (Hz)
Figure 2.
Figure 3.
THD+N vs Frequency
at VDD = 2.6V, 8Ω RL,
and PWR = 150mW, per channel
THD+N vs Power Out
at VDD = 5V, 8Ω RL,
1kHz, per channel
20
20
10
10
5
5
2
2
THD + N (%)
THD + N (%)
FREQUENCY (Hz)
1
0.5
0.2
1
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
20
50 100 200 500 1k 2k
0.01
10m 20m
5k 10k 20k
Figure 4.
Figure 5.
THD+N vs Power Out
at VDD = 3.3V, 8Ω RL,
1kHz, per channel
THD+N vs Power Out
at VDD = 2.6V, 8Ω RL,
1kHz, per channel
20
20
10
10
5
5
2
2
THD + N (%)
THD + N (%)
50m 100m 200m 500m
1
0.5
0.2
1
0.2
0.1
0.05
0.05
0.02
0.02
0.01
10m
0.01
10m
50m 100m 200m
500m
1
OUTPUT POWER (W)
20m
50m 100m 200m
500m
1
OUTPUT POWER (W)
Figure 6.
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2
0.5
0.1
20m
1
OUTPUT POWER (W)
FREQUENCY (Hz)
6
5k 10k 20k
Figure 7.
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TYPICAL PERFORMANCE CHARACTERISTICs (continued)
+0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
Power Supply Rejection Ratio (PSRR) vs Frequency
at VDD = 5V, 8Ω RL
+0
-10
-20
-30
LEVEL (dB)
LEVEL (dB)
Power Supply Rejection Ratio (PSRR) vs Frequency
at VDD = 5V, 8Ω RL
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
20
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 9. Input Floating
Power Supply Rejection Ratio (PSRR) vs Frequency
at VDD = 3.3V, 8Ω RL
Power Supply Rejection Ratio (PSRR) vs Frequency
at VDD = 3.3V, 8Ω RL
+0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
+0
-10
-20
-30
LEVEL (dB)
LEVEL (dB)
Figure 8. Input terminated with 10Ω
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
20
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 11. Input Floating
Power Supply Rejection Ratio (PSRR) vs Frequency
at VDD = 2.6V, 8Ω RL
Power Supply Rejection Ratio (PSRR) vs Frequency
at VDD = 2.6V, 8Ω RL
+0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
+0
-10
-20
-30
LEVEL (dB)
LEVEL (dB)
Figure 10. Input Floating
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
20
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 12. Input terminated with 10Ω
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Figure 13. Input Floating
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TYPICAL PERFORMANCE CHARACTERISTICs (continued)
Open Loop Frequency Response, 3.3V
70
180
o
70
180o
60
135o
60
135o
o
50
90o
50
90
40
45
30
o
0
o
20
-45
10
-90o
PHASE
0
100
1k
10k
100k
1M
GAIN (dB)
GAIN
o
PHASE
GAIN (dB)
GAIN
40
45o
30
0o
20
-45o
-90o
10
PHASE
-135
o
-180
o
PHASE
Open Loop Frequency Response, 5V
-135o
0
-180o
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14.
Figure 15.
Open Loop Frequency Response, 2.6V
Noise Floor, 5V, 8Ω
80kHz Bandwidth, Input to GND
60
135o
50
90o
40
45o
GAIN
30
0o
20
-45o
10
-90o
PHASE
-135o
0
-180o
100
1k
10k
100k
1M
90P
OUTPUT NOISE VOLTAGE (V)
180o
PHASE
GAIN (dB)
100P
70
80P
70P
60P
50P
40P
30P
20P
10P
0
20
10M
FREQUENCY (Hz)
Figure 17.
Crosstalk vs Frequency
5V, 8Ω, POUT = 1W
Crosstalk vs Frequency
3.3V, 8Ω, POUT = 400mW
+0
+0
-10
-10
-20
-20
OUTPUT LEVEL (dB)
OUTPUT LEVEL (dB)
5k 10k 20k
FREQUENCY (Hz)
Figure 16.
-30
-40
-50
-60
-70
-30
-40
-50
-60
-70
-80
-80
-90
-90
-100
-100
20
50 100 200 500 1k 2k
5k 10k 20k
20
FREQUENCY (Hz)
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50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 18.
8
50 100 200 500 1k 2k
Figure 19.
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TYPICAL PERFORMANCE CHARACTERISTICs (continued)
Crosstalk vs Frequency
2.6V, 8Ω, POUT = 200mW
Power Dissipation vs Output Power, 5V, 8Ω,
per channel
700
+0
POWER DISSIPATION (mW)
-10
OUTPUT LEVEL (dB)
-20
-30
-40
-50
-60
-70
-80
600
500
400
300
200
100
-90
0
-100
20
50 100 200 500 1k 2k
0
5k 10k 20k
200
400
600
800 1000 1200
OUTPUT POWER (mW)
FREQUENCY (Hz)
Figure 20.
Figure 21.
Power Dissipation vs Output Power, 3.3V, 8Ω,
per channel
Power Dissipation vs Output Power, 2.6V, 8Ω,
per channel
180
300
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
160
250
200
150
100
50
140
120
100
80
60
40
20
0
0
0
100
200
300
400
500
600
700
0
50
OUTPUT POWER (mW)
150
200
250
300 350
Figure 22.
Figure 23.
Shutdown Hysteresis Voltage
5V
Shutdown Hysteresis Voltage
3.3V
2.5
SUPPLY CURRENT/CHANNEL (mA)
SUPPLY CURRENT/CHANNEL (mA)
3.5
100
OUTPUT POWER (mW)
3
2.5
2
SD OFF
(play)
SD ON
1.5
1
0.5
0
2
1.5
SD OFF
(play)
SD ON
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
0
SHUTDOWN VOLTAGE (V)
Figure 24.
0.5
1
1.5
2
2.5
3
3.5
SHUTDOWN VOLTAGE (V)
Figure 25.
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TYPICAL PERFORMANCE CHARACTERISTICs (continued)
Shutdown Hysteresis Voltage
2.6V
Output Power vs Supply Voltage, 8Ω
1750
1500
2
OUTPUT POWER (mW)
SUPPLY CURRENT/CHANNEL (mA)
2.5
1.5
SD OFF
(play)
SD ON
1
0.5
1250
10% THD + N
1000
750
1% THD + N
500
250
0
0
0
0.5
1
1.5
2
2.5
3
2
3.5
2.5
SHUTDOWN VOLTAGE (V)
3
3.5
4
4.5
Figure 26.
Figure 27.
Frequency Response vs Input Capacitor Size
Wakeup Time vs
Supply Voltage
+1
-0
CB = 1 PF
100
0.39 PF
WAKEUP TIME (ms)
OUTPUT LEVEL (dB)
5.5
120
0.1 PF
-1
-2
5
SUPPLY VOLTAGE (V)
-3
-4
-5
-6
-7
-8
CB = 0.68 PF
80
60
CB = 0.47 PF
40
CB = 0.22 PF
20
-9
-10
20
0
50 100 200 500 1k 2k
5k 10k 20k
2
FREQUENCY (Hz)
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3.5
4
4.5
5
5.5
SUPPLY VOLTAGE (V)
Figure 28.
10
2.5
Figure 29.
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APPLICATION INFORMATION
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 1, the LM4992 has two internal operational amplifiers per channel. The first amplifier's gain is
externally configurable , while the second amplifier is internally fixed in a unity-gain, inverting configuration. The
closed-loop gain of the first amplifier is set by selecting the ratio of Rf to Ri while the second amplifier's gain is
fixed by the two internal 20kΩ resistors. Figure 1 shows that the output of amplifier one serves as the input to
amplifier two which results in both amplifiers producing signals identical in magnitude, but out of phase by 180°.
Consequently, the differential gain for the IC is
AVD= 2 *(Rf/Ri)
(1)
By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as
“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground.
A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closedloop gain without causing excessive clipping, please refer to the AUDIO POWER AMPLIFIER DESIGN section.
A bridge configuration, such as the one used in LM4992, also creates a second advantage over single-ended
amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists across
the load. This eliminates the need for an output coupling capacitor which is required in a single supply, singleended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would
result in both increased internal IC power dissipation and also possible loudspeaker damage.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. The maximum internal power dissipation per channel is 4 times that of a
single-ended amplifier. The maximum power dissipation for a given application can be derived from the power
dissipation graphs or from Equation (2).
PDMAX = 4*(VDD)2/(2π2RL)
(2)
It is critical that the maximum junction temperature TJMAX of 150°C is not exceeded. TJMAX is a function of PDMAX
and the PC board foil area. By adding copper foil, the thermal resistance of the application can be reduced from
the free air value of θJA, resulting in higher PDMAX values without thermal shutdown protection circuitry being
activated. Additional copper foil can be added to any of the leads connected to the LM4992. It is especially
effective when connected to VDD, GND, and the output pins. Refer to the application information on the LM4992
reference design board for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional
changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced
ambient temperature. Internal power dissipation is a function of output power. Refer to the TYPICAL
PERFORMANCE CHARACTERISTICs curves for power dissipation information for different output powers and
output loading.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4992's exposed-DAP (die attach paddle) packages (NHK) provide a low thermal resistance between the
die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a
low voltage audio power amplifier that produces 1.07W dissipation per channel in an 8Ω load at ≤ 1% THD+N.
This power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal
design may compromise the LM4992's performance and activate unwanted, though necessary, thermal
shutdown protection.
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The LM4992SD must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is then,
ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink,
and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-layer
PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance,
however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with
vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by
plugging and tenting the vias with plating and solder mask, respectively.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as
possible. Typical applications employ a 5V regulator with 10 µF tantalum or electrolytic capacitor and a ceramic
bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of
the LM4992. The selection of a bypass capacitor, CB, is dependent upon PSRR requirements, click and pop
performance (as explained in the section, PROPER SELECTION OF EXTERNAL COMPONENTS), system cost,
and size constraints.
SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the LM4992 contains shutdown circuitry that is used to
independently turn off each channel's bias circuitry. This shutdown feature turns a given channel off when logic
low is placed on the corresponding shutdown pin. By switching a particular shutdown pin to GND, the LM4992
supply current draw due to that channel will be minimized in idle mode. Idle current is measured with the
shutdown pin connected to GND. The trigger point for shutdown is shown as a typical value in the Shutdown
Hysteresis Voltage graphs in the TYPICAL PERFORMANCE CHARACTERISTICs section. It is best to switch
between ground and supply for maximum performance. While the device may be disabled with shutdown
voltages in between ground and supply, the idle current may be greater than the typical value of 0.2µA. In either
case, the shutdown pin should be tied to a definite voltage to avoid unwanted state changes.
In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry, which
provides a quick, smooth transition to shutdown. Another solution is to use a single-throw switch in conjunction
with an external pull-up resistor. This scheme ensures that the shutdown pin will not float, thus preventing
unwanted state changes.
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications using integrated power amplifiers is critical to optimize
device and system performance. While the LM4992 is tolerant of external component combinations,
consideration to component values must be used to maximize overall system quality.
The LM4992 is unity-gain stable which gives the designer maximum system flexibility. The LM4992 should be
used in low gain configurations to minimize THD+N values, and maximize the signal to noise ratio. Low gain
configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1
Vrms are available from sources such as audio codecs. Please refer to the section, AUDIO POWER AMPLIFIER
DESIGN, for a more complete explanation of proper gain selection.
Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the
bandwidth is dictated by the choice of external components shown in Figure 1. The input coupling capacitor, Ci,
forms a first order high pass filter which limits low frequency response. This value should be chosen based on
needed frequency response for a few distinct reasons.
Selection Of Input Capacitor Size
Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized
capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers
used in portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to
150Hz. Thus, using a large input capacitor may not increase actual system performance.
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In addition to system cost and size, click and pop performance is effected by the size of the input coupling
capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally
1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device enable.
Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be
minimized.
Besides minimizing the input capacitor size, careful consideration should be paid to the bypass capacitor value.
Bypass capacitor, CB, is the most critical component to minimize turn-on pops since it determines how fast the
LM4992 turns on. The slower the LM4992's outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the
smaller the turn-on pop. Choosing CB equal to 1.0µF along with a small value of Ci (in the range of 0.1µF to
0.39µF), should produce a virtually clickless and popless shutdown function. While the device will function
properly, (no oscillations or motorboating), with CB equal to 0.1µF, the device will be much more susceptible to
turn-on clicks and pops. Thus, a value of CB equal to 1.0µF is recommended in all but the most cost sensitive
designs.
AUDIO POWER AMPLIFIER DESIGN
A 1W/8Ω Audio Amplifier
Given:
Power Output
1 Wrms
Load Impedance
8Ω
Input Level
1 Vrms
Input Impedance
Bandwidth
20 kΩ
100 Hz–20 kHz ± 0.25 dB
A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating
from the Output Power vs Supply Voltage graphs in the TYPICAL PERFORMANCE CHARACTERISTICs
section, the supply rail can be easily found.
5V is a standard voltage in most applications, it is chosen for the supply rail. Extra supply voltage creates
headroom that allows the LM4992 to reproduce peaks in excess of 1W without producing audible distortion. At
this time, the designer must make sure that the power supply choice along with the output impedance does not
violate the conditions explained in the POWER DISSIPATION section.
Once the power dissipation equations have been addressed, the required differential gain can be determined
from Equation (3).
(3)
(4)
Rf/Ri = AVD/2
From Equation (3), the minimum AVD is 2.83; use AVD = 3.
Since the desired input impedance was 20 kΩ, and with a AVD impedance of 2, a ratio of 1.5:1 of Rf to Ri results
in an allocation of Ri = 20 kΩ and Rf = 30 kΩ. The final design step is to address the bandwidth requirements
which must be stated as a pair of −3 dB frequency points. Five times away from a −3 dB point is 0.17 dB down
from passband response which is better than the required ±0.25 dB specified.
fL = 100 Hz/5 = 20 Hz
fH = 20 kHz * 5 = 100 kHz
(5)
(6)
As stated in the PROPER SELECTION OF EXTERNAL COMPONENTS section, Ri in conjunction with Ci create
a highpass filter.
Ci ≥ 1/(2π*20 kΩ*20 Hz) = 0.397 µF; use 0.39 µF
(7)
The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain,
AVD. With a AVD = 3 and fH = 100 kHz, the resulting GBWP = 300kHz which is much smaller than the LM4992
GBWP of 1.5MHz. This figure displays that if a designer has a need to design an amplifier with a higher
differential gain, the LM4992 can still be used without running into bandwidth limitations.
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The LM4992 is unity-gain stable and requires no external components besides gain-setting resistors, an input
coupling capacitor, and proper supply bypassing in the typical application. However, if a closed-loop differential
gain of greater than 10 is required, a feedback capacitor (C4) may be needed as shown in SCHEMATIC
DRAWING to bandwidth limit the amplifier. This feedback capacitor creates a low pass filter that eliminates
possible high frequency oscillations. Care should be taken when calculating the -3dB frequency in that an
incorrect combination of R3 and C4 will cause rolloff before 20kHz. A typical combination of feedback resistor and
capacitor that will not produce audio band high frequency rolloff is R3 = 20kΩ and C4 = 25pf. These components
result in a -3dB point of approximately 320 kHz.
PCB LAYOUT GUIDELINES
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
GENERAL MIXED SIGNAL LAYOUT RECOMMENDATION
Power and Ground Circuits
For 2 layer mixed signal design, it is important to isolate the digital power and ground trace paths from the
analog power and ground trace paths. Star trace routing techniques (bringing individual traces back to a central
point rather than daisy chaining traces together in a serial manner) can have a major impact on low level signal
performance. Star trace routing refers to using individual traces to feed power and ground to each circuit or even
device. This technique will require a greater amount of design time but will not increase the final price of the
board. The only extra parts required will be some jumpers.
Single-Point Power / Ground Connections
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing High Frequency noise coupling between the analog and digital sections. It is further
recommended to put digital and analog power traces over the corresponding digital and analog ground traces to
minimize noise coupling.
Placement of Digital and Analog Components
All digital components and high-speed digital signal traces should be located as far away as possible from analog
components and circuit traces.
Avoiding Typical Design / Layout Problems
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and cross talk.
14
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SCHEMATIC DRAWING
VDD
R3
C4
R2
C2 20 k:
+
0.38 PF
C1
1 PF
-IN
-
+IN
+
Vo1
-
20 k:
20 k:
J2
VDD
+
Vo1
+
Vo2
BIAS
C3
1.0 PF
R1
20 k:
+
VDD/2
Bypass
Shutdown
J1
VDD
R1
20 k:
J1
BIAS
Shutdown
Bypass
C3
1.0 PF
VDD/2
+
J2
20 k:
20 k:
+
C2
R2
20 k:
+IN
-IN
+
-
Vo2
-
0.38 PF
C4
R3
Figure 30. Higher Gain Schematic Drawing
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Demonstration Board Layout
Figure 31. Recommended WSON Board Layout:
Top Overlay
Figure 32. Recommended WSON Board Layout:
Top Layer
16
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Figure 33. Recommended WSON Board Layout:
Bottom Layer
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REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM4992SD/NOPB
ACTIVE
WSON
NHK
14
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
L4992
LM4992SDX/NOPB
ACTIVE
WSON
NHK
14
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
L4992
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM4992SD/NOPB
WSON
NHK
14
1000
178.0
12.4
3.3
4.3
1.0
8.0
12.0
Q1
LM4992SDX/NOPB
WSON
NHK
14
4500
330.0
12.4
3.3
4.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM4992SD/NOPB
WSON
NHK
14
1000
203.0
190.0
41.0
LM4992SDX/NOPB
WSON
NHK
14
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NHK0014A
SDA14A (Rev A)
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