LF147QML www.ti.com

SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

LF147QML Wide Bandwidth Quad JFET Input Operational Amplifier

Check for Samples: LF147QML

1

FEATURES

23

• Internally Trimmed Offset Voltage: 5 mV Max

• Low Input Bias Current: 50 pA Typ.

• Low Input Noise Current: 0.01 pA/ √ Hz Typ.

• Wide Gain Bandwidth: 4 MHz Typ.

• High Slew Rate: 13 V/ μ s Typ.

• Low Supply Current: 7.2 mA Typ.

• High Input Impedance: 10

12

Ω Typ.

• Low Total Harmonic Distortion:

– A

V

= 10, R

L

= 10K Ω , V

O

= 20V

P-P

– BW = 20Hz – 20KHz ≤ 0.02% Typ.

• Low 1/f Noise Corner: 50 Hz Typ.

• Fast Settling Time to 0.01%: 2 μ s Typ.

DESCRIPTION

The LF147 is a low cost, high speed quad JFET input operational amplifier with an internally trimmed input offset voltage ( BI-FET II™ technology). The device requires a low supply current and yet maintains a large gain bandwidth product and a fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF147 is pin compatible with the standard LM148. This feature allows designers to immediately upgrade the overall performance of existing LF148 and LM124 designs.

The LF147 may be used in applications such as high speed integrators, fast D/A converters, sample-andhold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The device has low noise and offset voltage drift.

CONNECTION DIAGRAM

Dual-In-Line Package (CDIP)

Top View

See Package Number J0014A

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

BI-FET II is a trademark of dcl_owner.

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2005–2013, Texas Instruments Incorporated

LF147QML

SNOSAI1A – APRIL 2005 – REVISED MARCH 2013 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Simplified Schematic

Figure 1. ¼ Quad

Detailed Schematic

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Absolute Maximum Ratings

(1)

Supply Voltage

Differential Input Voltage

Input Voltage Range

(2)

Output Short Circuit Duration

(3)

Power Dissipation

(4) (5)

T

J max

θ

JA

CERDIP

Operating Temperature Range

Storage Temperature Range

Lead Temperature (Soldering, 10 sec.)

ESD

(6)

±22V

±38V

±19V

Continuous

900 mW

150°C

70°C/W

− 55°C ≤ T

A

≤ 125°C

− 65°C ≤ T

A

≤ 150°C

260°C

900V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical

Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

(2) Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

(3) Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded.

(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by T

Jmax

θ

JA

(Package junction to ambient thermal resistance), and T

A

(maximum junction temperature),

(ambient temperature). The maximum allowable power dissipation at any temperature is P

Dmax

= (T

Jmax

— T

A

) / θ

JA or the number given in the Absolute Maximum Ratings, whichever is lower.

(5) Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside specified limits.

(6) Human body model, 1.5 k Ω in series with 100 pF.

Quality Conformance Inspection

Mil-Std-883, Method 5005 - Group A

Subgroup

1

2

3

4

5

6

7

8A

8B

9

10

11

Description

Static tests at

Static tests at

Static tests at

Dynamic tests at

Dynamic tests at

Dynamic tests at

Functional tests at

Functional tests at

Functional tests at

Switching tests at

Switching tests at

Switching tests at

Temp (°C)

25

125

-55

25

125

-55

25

125

-55

25

125

-55

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

LF147 883 Electrical Characteristics DC Parameters

The following conditions apply, unless otherwise specified: V

S

= ±20V, V

CM

= 0V, R

S

= 50 Ω

Symbol Parameter Conditions Notes Min Max

V

IO

Input Offset Voltage R

S

= 10K Ω

I

IO

±I

IB

Input Offset Current

Input Bias Current

R

L

= 10K Ω

R

L

=10K Ω

V

CM

CMRR

PSRR

I

S

I

OS

Input Common Mode Voltage

Range

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Supply Current

Output Short Circuit

R

V

S

S

≤ 10K Ω , V

CM

= ±20V to V

S

= ±16V

= ±5V

V

S

= ±15V, V

I

= +1V,

Output short to GND

V

S

= ±15V, V

I

= -1V,

Output short to GND

A

VS

Large Signal Voltage Gain V

S

R

L

= ±15V, V

O

= 2K Ω , R

S

= 0 to +10V,

= 10K Ω

V

S

R

L

= ±15V, V

O

= 0 to -10V

= 2 K Ω , R

S

=10K Ω

V

O

Output Voltage Swing V

S

V

I

= ±15V, R

= +1V

L

= 10K Ω ,

V

S

V

I

= ±15V, R

= -1V

L

= 10K Ω ,

V

S

= ±15V, R

L

= 2K Ω , V

I

= +1V

V

S

= ±15V, R

L

= 2K Ω , V

I

= -1V

(1) Specified by CMRR test

(2) V/mV in units column is equivalent to K in datalog

(1)

(2)

(2)

(2)

(2)

5

8

0.1

25

-0.2

0.2

-50 50

-16 16

-40

13

6

50

25

50

25

80

80

11

-57 -13

-6

57

40

12

10

-12

-10

LF147 883 Electrical Characteristics AC Parameters

The following conditions apply, unless otherwise specified: V

S

= ±20V, V

CM

= 0V, R

S

= 50 Ω

Symbol Parameter Conditions

Notes Min Max

SR Slew Rate V

I

R

L

= -5V to +5V, A

V

=1

= 2K Ω , CL = 100pF

V

I

R

L

= +5V to -5V, A

V

= 1

= 2K Ω , CL = 100pF

8

5

8

5

Unit mV mV nA nA nA nA

V dB dB mA mA mA mA mA

V/mV

V/mV

V/mV

V/mV

V

V

V

V

Unit

V/µs

V/µs

V/µS

V/µS www.ti.com

Subgroups

7

8A, 8B

7

8A, 8B

1, 2, 3

1, 2, 3

1, 2, 3

1, 3

2

1, 3

2

4

5, 6

4

5, 6

4, 5, 6

Subgroups

1

2, 3

1

2, 3

1

2, 3

1, 2, 3

4, 5, 6

4, 5, 6

4, 5, 6

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

LF147 SMD Electrical Characteristics DC Parameters

The following conditions apply, unless otherwise specified: V

S

= ±15V, V

CM

= 0V, R

S

= 0 Ω , R

L

= Open

Symbol Parameter Conditions Notes Min Max

V

IO

Input Offset Voltage Vcc = ±15V

I

IO

±I

IB

A

VS

+V

O

-V

O

V

CM

CMRR

+PSRR

-PSRR

+I

S

-I

S

+I

OS

-I

OS

Input Offset Current

Input Bias Current

Large Signal Voltage Gain

Output Voltage Swing

Output Voltage Swing

Input Common Mode Voltage

Range

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Power Supply Rejection Ratio

Supply Current

Supply Current

Output Short Circuit Current

Output Short Circuit Current

Vcc = ±9V

V

S

R

L

= ±15V, V

O

= 2K Ω

= 0 to +10V,

V

S

R

L

= ±15V, V

O

= 2K Ω

= 0 to -10V,

V

S

= ±15V, R

L

= 10K Ω

V

S

= ±15V, R

L

= 2K Ω

V

S

= ±15V, R

L

= 10K Ω

V

S

= ±15V, R

L

= 2K Ω

V

CM

= ±11V

+V

S

= 15 to 9V, -V

S

= -15V

+V

S

= 15V, -V

S

= -15 to -9V

V

S

= ±15V

V

S

= ±15V

(1)

±11

80

80

80

14

-14

-57 -13

-40

13

6

-6

57

40

15

35

15

12

10

-9

-15

-9

-0.1

0.1

-20 20

-0.2

0.2

-50

35

50

9

15

9

-12

-10

(1) Specified by CMRR test

1, 2, 3

1

1

1

1

1

1, 3

2

1, 3

2

Subgroups

1

2, 3

1

1

2

5, 6

4, 5, 6

4, 5, 6

4, 5, 6

4, 5, 6

1

2

4

5, 6

4

Unit nA nA

V/mV

V/mV

V/mV mV mV mV nA nA

V/mV

V

V

V

V

V dB dB dB mA mA mA mA mA mA

LF147 SMD Electrical Characteristics AC Parameters

The following conditions apply, unless otherwise specified: V

S

= ±15V, V

CM

= 0V, R

S

= 0 Ω , R

L

= Open

Symbol Parameter Conditions Notes Min Max

SR Slew Rate V

I

R

L

= -5V to +5V, A

V

= 2K Ω , C

L

=1

= 100pF

V

I

R

L

= +5V to -5V, A

V

=1

= 2K Ω , C

L

= 100pF

8

5

8

5

Unit

V/µs

V/µs

V/µS

V/µS

Subgroups

7

8A, 8B

7

8A, 8B

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Typical Performance Characteristics

Input Bias Current Input Bias Current www.ti.com

Figure 2.

Supply Current

Figure 3.

Positive Common-Mode

Input Voltage Limit

Figure 4.

Negative Common-Mode

Input Voltage Limit

Figure 5.

Positive Current Limit

Figure 6.

Figure 7.

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LF147QML

SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Typical Performance Characteristics (continued)

Negative Current Limit Output Voltage Swing

Figure 8.

Output Voltage Swing

Figure 9.

Gain Bandwidth

Figure 10.

Bode Plot

Figure 11.

Slew Rate

Figure 12.

Figure 13.

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Typical Performance Characteristics (continued)

Distortion vs

Frequency

Undistorted Output Voltage

Swing www.ti.com

Figure 14.

Open Loop Frequency

Response

Figure 16.

Power Supply Rejection

Ratio

Figure 15.

Common-Mode Rejection

Ratio

Figure 17.

Equivalent Input Noise

Voltage

Figure 18.

Figure 19.

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LF147QML

SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Typical Performance Characteristics (continued)

Open Loop Voltage Gain Output Impedance

Figure 20.

Inverter Settling Time

Figure 21.

Figure 22.

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

R

L

= 2 k Ω , C

L

= 10 pF

Small Signal Inverting

Pulse Response

Small Signal Non-Inverting www.ti.com

Large Signal Inverting Large Signal Non-Inverting

Current Limit (R

L

=100 Ω )

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

APPLICATION INFORMATION

The LF147 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II).

These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit.

Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode.

Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state.

The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur.

Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±4.5V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate.

The LF147 will drive a 2 k Ω load resistance to ±10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings.

Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit.

As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground.

A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.

In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Typical Applications

Figure 23. Digitally Selectable Precision Attenuator www.ti.com

All resistors 1% tolerance

• Accuracy of better than 0.4% with standard 1% value resistors

No offset adjustment necessary

• Expandable to any number of stages

• Very high input impedance

A1 A2 A3

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

V

O

Attenuation

0

− 1 dB

− 2 dB

− 3 dB

− 4 dB

− 5 dB

− 6 dB

− 7 dB

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LF147QML

SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Figure 24. Long Time Integrator with Reset, Hold and Starting Threshold Adjustment

• V

OUT starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage:

• Output starts when V

IN

≥ V

TH

• Switch S1 permits stopping and holding any output value

• Switch S2 resets system to zero

Figure 25. Universal State Variable Filter

For circuit shown: f

O

= 3 kHz, f

NOTCH

= 9.5 kHz

Q=3.4

Passband gain: Highpass—0.1

Bandpass—1

Lowpass—1

Notch—10

• f o

×Q ≤ 200 kHz

• 10V peak sinusoidal output swing without slew limiting to 200 kHz

• See LM148 data sheet for design equations

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SNOSAI1A – APRIL 2005 – REVISED MARCH 2013

Revision Section Date

Released

04/18/05 A New Release into corporate format

03/20/13 A All

Originator

L. Lytle www.ti.com

Changes

2 MDS datasheets converted into one Corp.

datasheet format. MNLF147–X Rev. 0A2 and

MDLF147–X Rev. 0A1, data sheets will be

Archived

Changed layout of National Data Sheet to TI format

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PACKAGE OPTION ADDENDUM www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

CDIP J 14 25

Eco Plan

(2)

TBD

Lead/Ball Finish MSL Peak Temp

(3)

Call TI Call TI

Op Temp (°C) Top-Side Markings

(4)

LF147J/883 Q LF147J/883 -55 to 125

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

J0014A

12X .100

[2.54]

PIN 1 ID

(OPTIONAL)

1

SCALE 0.900

A

4X .005 MIN

[0.13]

14

14X .045

-.065

[ 1.15

-1.65

]

.754

-.785

[ 19.15

-19.94

]

PACKAGE OUTLINE

CDIP - 5.08 mm max height

CERAMIC DUAL IN LINE PACKAGE

.015

-.060

[ 0.38

-1.52

]

TYP

14X .014

-.026

[ 0.36

-0.66

]

.010 [0.25] C A B

B

7

.245

-.283

[ 6.22

-7.19

]

8

.308

-.314

[ 7.83

-7.97

]

AT GAGE PLANE

.2 MAX TYP

[5.08]

C

.13 MIN TYP

[3.3]

SEATING PLANE

.015 GAGE PLANE

[0.38]

0 -15

TYP

14X .008-.014

[0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for

reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermitically sealed with a ceramic lid using glass frit.

4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.

5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com

J0014A

SEE DETAIL A

1

12X (.100 )

[2.54]

(.300 ) TYP

[7.62]

EXAMPLE BOARD LAYOUT

CDIP - 5.08 mm max height

CERAMIC DUAL IN LINE PACKAGE

14

SEE DETAIL B

SYMM

14X ( .039)

[1]

7

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED

SCALE: 5X

8

.002

MAX

[0.05]

ALL AROUND

(.063)

[1.6]

(R.002 ) TYP

[0.05]

DETAIL A

SCALE: 15X

METAL

SOLDER MASK

OPENING

METAL

( .063)

[1.6]

SOLDER MASK

OPENING

DETAIL B

13X, SCALE: 15X

.002 MAX

[0.05]

ALL AROUND

4214771/A 05/2017 www.ti.com

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Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications.

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource.

Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE

TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY

RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR

REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO

ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL

PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,

INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF

PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,

DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN

CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.

Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).

Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection.

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.

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